/*
 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */


#include "dccg.h"
#include "clk_mgr_internal.h"
#include "dce100/dce_clk_mgr.h"
#include "dce110/dce110_clk_mgr.h"
#include "dce60_clk_mgr.h"
#include "reg_helper.h"
#include "dmcu.h"
#include "core_types.h"
#include "dal_asic_id.h"

/*
 * Currently the register shifts and masks in this file are used for dce60
 * which has no DPREFCLK_CNTL register
 * TODO: remove this when DENTIST_DISPCLK_CNTL
 * is moved to dccg, where it belongs
 */
#include "dce/dce_6_0_d.h"
#include "dce/dce_6_0_sh_mask.h"

#define REG(reg) \
        (clk_mgr->regs->reg)

#undef FN
#define FN(reg_name, field_name) \
        clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

/* set register offset */
#define SR(reg_name)\
        .reg_name = mm ## reg_name

static const struct clk_mgr_registers disp_clk_regs = {
                CLK_COMMON_REG_LIST_DCE60_BASE()
};

static const struct clk_mgr_shift disp_clk_shift = {
                CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT)
};

static const struct clk_mgr_mask disp_clk_mask = {
                CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)
};


/* Max clock values for each state indexed by "enum clocks_state": */
static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
/* ClocksStateInvalid - should not be used */
{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
/* ClocksStateLow */
{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
/* ClocksStateNominal */
{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
/* ClocksStatePerformance */
{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };

static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
        struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
        struct dc_context *ctx = clk_mgr_base->ctx;
        int dp_ref_clk_khz = 0;

        if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
                dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
        else
                dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;

        return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
}

static void dce60_pplib_apply_display_requirements(
        struct dc *dc,
        struct dc_state *context)
{
        struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

        dce110_fill_display_configs(context, pp_display_cfg);

        if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
                dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
}

static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
                        struct dc_state *context,
                        bool safe_to_lower)
{
        struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
        struct dm_pp_power_level_change_request level_change_req;
        const int max_disp_clk =
                clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
        int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);

        level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
        /* get max clock state from PPLIB */
        if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
                        || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
                if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
                        clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
        }

        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
                patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
                clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
        }
        dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
}








static struct clk_mgr_funcs dce60_funcs = {
        .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
        .update_clocks = dce60_update_clocks
};

void dce60_clk_mgr_construct(
                struct dc_context *ctx,
                struct clk_mgr_internal *clk_mgr)
{
        struct clk_mgr *base = &clk_mgr->base;

        dce_clk_mgr_construct(ctx, clk_mgr);

        memcpy(clk_mgr->max_clks_by_state,
                dce60_max_clks_by_state,
                sizeof(dce60_max_clks_by_state));

        clk_mgr->regs = &disp_clk_regs;
        clk_mgr->clk_mgr_shift = &disp_clk_shift;
        clk_mgr->clk_mgr_mask = &disp_clk_mask;
        clk_mgr->base.funcs = &dce60_funcs;

        base->clks.max_supported_dispclk_khz =
                clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
}