PCI_COMMAND_MASTER
*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MASTER;
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
if (value & PCI_COMMAND_MASTER)
conf_data |= PCI_COMMAND_MASTER;
if (value & PCI_COMMAND_MASTER)
hi |= PCI_COMMAND_MASTER;
hi &= ~PCI_COMMAND_MASTER;
if (hi & PCI_COMMAND_MASTER)
conf_data |= PCI_COMMAND_MASTER;
conf_data |= PCI_COMMAND_MASTER;
if (value & PCI_COMMAND_MASTER)
if (value & PCI_COMMAND_MASTER)
hi |= PCI_COMMAND_MASTER;
hi &= ~PCI_COMMAND_MASTER;
if (hi & PCI_COMMAND_MASTER)
conf_data |= PCI_COMMAND_MASTER;
cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER);
__raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
PCI_COMMAND_MASTER | \
if (!(cmdreg & PCI_COMMAND_MASTER)) {
val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
if (!(cmdreg & PCI_COMMAND_MASTER)) {
if (cmdreg & PCI_COMMAND_MASTER) {
edev->config_space[1] |= PCI_COMMAND_MASTER;
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
PCI_COMMAND_MASTER | PCI_COMMAND_IO);
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
if ((reg != PCI_ROM_ADDRESS) && (reg != PCI_COMMAND_MASTER) &&
PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER);
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER )))
tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
if (status != EFI_SUCCESS || !(command & PCI_COMMAND_MASTER))
command &= ~PCI_COMMAND_MASTER;
| PCI_COMMAND_MASTER);
xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
command &= ~PCI_COMMAND_MASTER;
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
if (!(cmd & PCI_COMMAND_MASTER)) {
if (!(cmd & PCI_COMMAND_MASTER)) {
command &= ~PCI_COMMAND_MASTER;
#define ALX_PCI_CMD (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
if (0 == (cmd & PCI_COMMAND_MASTER))
cmd |= PCI_COMMAND_MASTER;
if ((cmd & PCI_COMMAND_MASTER) == 0) {
if ((cmd & PCI_COMMAND_MASTER) == 0) {
cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
PCI_COMMAND_MASTER));
PCI_COMMAND_MASTER));
iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
if (val & PCI_COMMAND_MASTER) {
value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
val |= PCI_COMMAND_MASTER;
ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
val |= PCI_COMMAND_MASTER;
val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
command &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
if (pci_command & PCI_COMMAND_MASTER) {
pci_command &= ~PCI_COMMAND_MASTER;
cmd = old_cmd | PCI_COMMAND_MASTER;
cmd = old_cmd & ~PCI_COMMAND_MASTER;
old_command | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER |
cmd &= ~PCI_COMMAND_MASTER;
cmd |= PCI_COMMAND_MASTER;
if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
msg16 |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
msg16 &= ~(PCI_COMMAND_MASTER);
pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
if (!(cmd & PCI_COMMAND_MASTER)) {
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
#define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
PCI_COMMAND_MASTER |
PCI_COMMAND_MASTER |
ASSERT_FALSE(command & PCI_COMMAND_MASTER);
vfio_pci_config_writew(self->device, PCI_COMMAND, command | PCI_COMMAND_MASTER);
ASSERT_TRUE(command & PCI_COMMAND_MASTER);
vfio_pci_config_writew(self->device, PCI_COMMAND, command & ~PCI_COMMAND_MASTER);
ASSERT_FALSE(command & PCI_COMMAND_MASTER);