arch/alpha/include/asm/io.h

162

REMAP2(u64, writeq, volatile)

arch/alpha/include/asm/io.h

248

extern void writeq(u64 b, volatile void __iomem *addr);

arch/alpha/include/asm/io.h

256

#define writeq writeq

arch/alpha/include/asm/io.h

507

IO_CONCAT(__IO_PREFIX,writeq)(b, addr);

arch/alpha/include/asm/io.h

595

#define writeq_relaxed writeq

arch/alpha/include/asm/io_trivial.h

134

IO_CONCAT(__IO_PREFIX,writeq)(u64 b, volatile void __iomem *a)

arch/alpha/kernel/io.c

160

IO_CONCAT(__IO_PREFIX,writeq)(b, addr);

arch/alpha/kernel/io.c

239

EXPORT_SYMBOL(writeq);

arch/mips/include/asm/io.h

515

#define writeq writeq

arch/parisc/lib/iomap.c

222

writeq(datum, addr);

arch/powerpc/include/asm/io.h

688

#define writeq writeq

arch/powerpc/include/asm/io.h

701

#define writeq_relaxed(v, addr) writeq(v, addr)

arch/sparc/include/asm/io_64.h

186

#define writeq writeq

arch/sparc/include/asm/io_64.h

187

#define writeq_relaxed writeq

arch/x86/include/asm/io.h

108

#define writeq writeq

arch/x86/include/asm/io.h

97

build_mmio_write(writeq, "q", u64, "r", :"memory")

arch/x86/include/asm/numachip/numachip_csr.h

90

writeq(val, numachip2_lcsr_address(offset));

arch/x86/include/asm/uv/uv_hub.h

571

writeq(val, uv_global_mmr32_address(pnode, offset));

arch/x86/include/asm/uv/uv_hub.h

591

writeq(val, uv_global_mmr64_address(pnode, offset));

arch/x86/include/asm/uv/uv_hub.h

625

writeq(val, uv_local_mmr_address(offset));

drivers/accel/habanalabs/common/device.c

106

writeq(*val, acc_addr);

drivers/accel/habanalabs/gaudi/gaudi.c

2536

writeq(0, hdev->pcie_bar[SRAM_BAR_ID] + i);

drivers/accel/habanalabs/gaudi/gaudi.c

6058

writeq(val, hdev->pcie_bar[HBM_BAR_ID] +

drivers/accel/habanalabs/gaudi2/gaudi2.c

11902

writeq(val, hdev->pcie_bar[DRAM_BAR_ID] + (addr - gaudi2->dram_bar_cur_addr));

drivers/accel/habanalabs/goya/goya.c

4219

writeq(val, hdev->pcie_bar[DDR_BAR_ID] +

drivers/accel/ivpu/ivpu_hw_reg_io.h

119

writeq(val, base + reg);

drivers/acpi/osl.c

800

writeq(value, virt_addr);

drivers/bus/fsl-mc/mc-sys.c

112

writeq(le64_to_cpu(cmd->header), &portal->header);

drivers/cache/starfive_starlink_cache.c

49

writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),

drivers/cache/starfive_starlink_cache.c

51

writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),

drivers/cache/starfive_starlink_cache.c

55

writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,

drivers/cache/starfive_starlink_cache.c

64

writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),

drivers/cache/starfive_starlink_cache.c

66

writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),

drivers/cache/starfive_starlink_cache.c

70

writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,

drivers/cache/starfive_starlink_cache.c

79

writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),

drivers/cache/starfive_starlink_cache.c

81

writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),

drivers/cache/starfive_starlink_cache.c

85

writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,

drivers/char/agp/parisc-agp.c

96

writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM);

drivers/char/hpet.c

404

writeq((readq(&timer->hpet_config) & ~Tn_INT_ENB_CNF_MASK),

drivers/char/hpet.c

418

writeq(v, &timer->hpet_config);

drivers/char/hpet.c

508

writeq(v, &timer->hpet_config);

drivers/char/hpet.c

535

writeq(g, &timer->hpet_config);

drivers/char/hpet.c

57

#define write_counter(V, MC) writeq(V, MC)

drivers/char/hpet.c

583

writeq(v, &timer->hpet_config);

drivers/char/hpet.c

620

writeq(v, &timer->hpet_config);

drivers/char/hpet.c

886

writeq(mcfg, &hpet->hpet_config);

drivers/char/hw_random/cavium-rng.c

42

writeq(THUNDERX_RNM_RNG_EN | THUNDERX_RNM_ENT_EN,

drivers/char/hw_random/cavium-rng.c

51

writeq(0, rng->control_status);

drivers/char/hw_random/cavium-rng.c

72

writeq(0, rng->control_status);

drivers/char/ipmi/ipmi_si_mem_io.c

54

writeq((u64)b << io->regshift, (io->addr)+(offset * io->regspacing));

drivers/crypto/cavium/cpt/cpt_common.h

146

writeq(val, hw_addr + offset);

drivers/crypto/cavium/nitrox/nitrox_dev.h

289

writeq(value, (ndev->bar_addr + offset));

drivers/crypto/cavium/nitrox/nitrox_reqmgr.c

308

writeq(1, cmdq->dbell_csr_addr);

drivers/crypto/cavium/nitrox/nitrox_reqmgr.c

603

writeq(slc_cnts.value, cmdq->compl_cnt_csr_addr);

drivers/crypto/hisilicon/qm.c

1604

writeq(vf_mask, qm->io_base + QM_IFC_INT_SOURCE_P);

drivers/crypto/hisilicon/qm.c

1952

writeq(msg, qm->io_base + offset);

drivers/crypto/hisilicon/qm.c

803

writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);

drivers/crypto/hisilicon/qm.c

823

writeq(doorbell, io_base);

drivers/crypto/marvell/octeontx/otx_cptpf_main.c

20

writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0));

drivers/crypto/marvell/octeontx/otx_cptpf_main.c

26

writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0));

drivers/crypto/marvell/octeontx/otx_cptpf_main.c

39

writeq(1, cpt->reg_base + OTX_CPT_PF_RESET);

drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c

106

writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0));

drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c

120

writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf));

drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c

132

writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf));

drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c

162

writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(q));

drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c

78

writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1));

drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c

79

writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0));

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

1560

writeq(0, cpt->reg_base + OTX_CPT_PF_GX_EN(grp));

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

1575

writeq(0, cpt->reg_base + OTX_CPT_PF_EXE_CTL);

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

199

writeq((u64) dma_addr, cpt->reg_base +

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

225

writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx));

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

247

writeq(reg, cpt->reg_base + OTX_CPT_PF_EXE_CTL);

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

272

writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx));

drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

278

writeq(reg, cpt->reg_base + OTX_CPT_PF_EXE_CTL);

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

352

writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

361

writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

370

writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

379

writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

396

writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

415

writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

425

writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

435

writeq(vqx_done_ena.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

445

writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

455

writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

465

writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

475

writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

485

writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

564

writeq(vqx_dack_cnt.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ACK(0));

drivers/crypto/marvell/octeontx/otx_cptvf_main.c

620

writeq(vqx_saddr.u, cptvf->reg_base + OTX_CPT_VQX_SADDR(0));

drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c

79

writeq(mbx->msg, cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 0));

drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c

80

writeq(mbx->data, cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 1));

drivers/cxl/pci.c

260

writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET);

drivers/dma/dw-edma/dw-edma-v0-core.c

296

writeq(sar, &lli->sar.reg);

drivers/dma/dw-edma/dw-edma-v0-core.c

297

writeq(dar, &lli->dar.reg);

drivers/dma/dw-edma/dw-edma-v0-core.c

315

writeq(pointer, &llp->llp.reg);

drivers/dma/dw-edma/dw-edma-v0-core.c

59

writeq(value, &(__dw_regs(dw)->name))

drivers/dma/dw-edma/dw-hdma-v0-core.c

172

writeq(sar, &lli->sar.reg);

drivers/dma/dw-edma/dw-hdma-v0-core.c

173

writeq(dar, &lli->dar.reg);

drivers/dma/dw-edma/dw-hdma-v0-core.c

191

writeq(pointer, &llp->llp.reg);

drivers/dma/ioat/dma.c

1052

writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000);

drivers/dma/ioat/dma.c

1053

writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008);

drivers/dma/ioat/dma.c

1054

writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800);

drivers/dma/sf-pdma/sf-pdma.c

265

writeq(desc->xfer_size, regs->xfer_size);

drivers/dma/sf-pdma/sf-pdma.c

266

writeq(desc->dst_addr, regs->dst_addr);

drivers/dma/sf-pdma/sf-pdma.c

267

writeq(desc->src_addr, regs->src_addr);

drivers/dma/sf-pdma/sf-pdma.c

37

#ifndef writeq

drivers/edac/igen6_edac.c

891

writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);

drivers/edac/thunderx_edac.c

1088

writeq(ctx->reg_lane_int[lane], ocx->regs + OCX_LNE_INT(lane));

drivers/edac/thunderx_edac.c

1091

writeq(ctx->reg_com_int, ocx->regs + OCX_COM_INT);

drivers/edac/thunderx_edac.c

1174

writeq(ctx->reg_com_link_int, ocx->regs + OCX_COM_LINKX_INT(ctx->link));

drivers/edac/thunderx_edac.c

1329

writeq(cfg, ocx->regs + OCX_LNE_CFG(lane));

drivers/edac/thunderx_edac.c

1438

writeq(OCX_LNE_INT_ENA_ALL,

drivers/edac/thunderx_edac.c

1442

writeq(reg, ocx->regs + OCX_LNE_INT(i));

drivers/edac/thunderx_edac.c

1448

writeq(reg, ocx->regs + OCX_COM_LINKX_INT(i));

drivers/edac/thunderx_edac.c

1450

writeq(OCX_COM_LINKX_INT_ENA_ALL,

drivers/edac/thunderx_edac.c

1455

writeq(reg, ocx->regs + OCX_COM_INT);

drivers/edac/thunderx_edac.c

1457

writeq(OCX_COM_INT_ENA_ALL, ocx->regs + OCX_COM_INT_ENA_W1S);

drivers/edac/thunderx_edac.c

1472

writeq(OCX_COM_INT_ENA_ALL, ocx->regs + OCX_COM_INT_ENA_W1C);

drivers/edac/thunderx_edac.c

1475

writeq(OCX_COM_LINKX_INT_ENA_ALL,

drivers/edac/thunderx_edac.c

1778

writeq(ctx->reg_int, tad->regs + L2C_TAD_INT_W1C);

drivers/edac/thunderx_edac.c

1807

writeq(ctx->reg_int, cbc->regs + L2C_CBC_INT_W1C);

drivers/edac/thunderx_edac.c

1826

writeq(ctx->reg_int, mci->regs + L2C_MCI_INT_W1C);

drivers/edac/thunderx_edac.c

2063

writeq(reg_en_mask, l2c->regs + reg_en_offs);

drivers/edac/thunderx_edac.c

2080

writeq(L2C_TAD_INT_ENA_ALL, l2c->regs + L2C_TAD_INT_ENA_W1C);

drivers/edac/thunderx_edac.c

2083

writeq(L2C_CBC_INT_ENA_ALL, l2c->regs + L2C_CBC_INT_ENA_W1C);

drivers/edac/thunderx_edac.c

2086

writeq(L2C_MCI_INT_ENA_ALL, l2c->regs + L2C_MCI_INT_ENA_W1C);

drivers/edac/thunderx_edac.c

275

writeq(val, pdata->regs + _reg); \

drivers/edac/thunderx_edac.c

309

writeq(val, lmc->regs + LMC_INT_W1S);

drivers/edac/thunderx_edac.c

345

writeq(lmc->mask0, lmc->regs + LMC_CHAR_MASK0);

drivers/edac/thunderx_edac.c

346

writeq(lmc->mask2, lmc->regs + LMC_CHAR_MASK2);

drivers/edac/thunderx_edac.c

347

writeq(lmc->parity_test, lmc->regs + LMC_ECC_PARITY_TEST);

drivers/edac/thunderx_edac.c

547

writeq(0, lmc->regs + LMC_CHAR_MASK0);

drivers/edac/thunderx_edac.c

548

writeq(0, lmc->regs + LMC_CHAR_MASK2);

drivers/edac/thunderx_edac.c

549

writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST);

drivers/edac/thunderx_edac.c

562

writeq(ctx->reg_int, lmc->regs + LMC_INT);

drivers/edac/thunderx_edac.c

772

writeq(lmc_int, lmc->regs + LMC_INT);

drivers/edac/thunderx_edac.c

774

writeq(LMC_INT_ENA_ALL, lmc->regs + LMC_INT_ENA_W1S);

drivers/edac/thunderx_edac.c

802

writeq(LMC_INT_ENA_ALL, lmc->regs + LMC_INT_ENA_W1C);

drivers/fpga/dfl-afu-error.c

37

writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK);

drivers/fpga/dfl-afu-error.c

93

writeq(v, base_err + PORT_ERROR);

drivers/fpga/dfl-afu-error.c

96

writeq(v, base_err + PORT_FIRST_ERROR);

drivers/fpga/dfl-afu-main.c

197

writeq(v, base + PORT_HDR_CTRL);

drivers/fpga/dfl-afu-main.c

234

writeq(PORT_STS_AP1_EVT, base + PORT_HDR_STS);

drivers/fpga/dfl-afu-main.c

272

writeq(PORT_STS_AP2_EVT, base + PORT_HDR_STS);

drivers/fpga/dfl-afu-main.c

310

writeq(userclk_freq_cmd, base + PORT_HDR_USRCLK_CMD0);

drivers/fpga/dfl-afu-main.c

331

writeq(userclk_freqcntr_cmd, base + PORT_HDR_USRCLK_CMD1);

drivers/fpga/dfl-afu-main.c

53

writeq(v, base + PORT_HDR_CTRL);

drivers/fpga/dfl-afu-main.c

91

writeq(v, base + PORT_HDR_CTRL);

drivers/fpga/dfl-fme-error.c

118

writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

122

writeq(v, base + PCIE1_ERROR);

drivers/fpga/dfl-fme-error.c

126

writeq(0ULL, base + PCIE1_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

196

writeq(v, base + RAS_ERROR_INJECT);

drivers/fpga/dfl-fme-error.c

234

writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

238

writeq(v, base + FME_ERROR);

drivers/fpga/dfl-fme-error.c

243

writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR,

drivers/fpga/dfl-fme-error.c

330

writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

332

writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

334

writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

335

writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

336

writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

337

writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

73

writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

77

writeq(v, base + PCIE0_ERROR);

drivers/fpga/dfl-fme-error.c

81

writeq(0ULL, base + PCIE0_ERROR_MASK);

drivers/fpga/dfl-fme-main.c

434

writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);

drivers/fpga/dfl-fme-main.c

440

writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);

drivers/fpga/dfl-fme-mgr.c

102

writeq(pr_error, fme_pr + FME_PR_ERR);

drivers/fpga/dfl-fme-mgr.c

125

writeq(pr_ctrl, fme_pr + FME_PR_CTRL);

drivers/fpga/dfl-fme-mgr.c

136

writeq(pr_ctrl, fme_pr + FME_PR_CTRL);

drivers/fpga/dfl-fme-mgr.c

160

writeq(pr_ctrl, fme_pr + FME_PR_CTRL);

drivers/fpga/dfl-fme-mgr.c

178

writeq(pr_ctrl, fme_pr + FME_PR_CTRL);

drivers/fpga/dfl-fme-mgr.c

211

writeq(pr_data, fme_pr + FME_PR_DATA);

drivers/fpga/dfl-fme-mgr.c

230

writeq(pr_ctrl, fme_pr + FME_PR_CTRL);

drivers/fpga/dfl-fme-perf.c

332

writeq(v, base + CACHE_CTRL);

drivers/fpga/dfl-fme-perf.c

407

writeq(v, base + FAB_CTRL);

drivers/fpga/dfl-fme-perf.c

431

writeq(v, base + FAB_CTRL);

drivers/fpga/dfl-fme-perf.c

464

writeq(v, base + VTD_CTRL);

drivers/fpga/dfl-fme-perf.c

495

writeq(v, base + VTD_SIP_CTRL);

drivers/fpga/dfl-n3000-nios.c

487

writeq(v, nn->base + N3000_NS_CTRL);

drivers/fpga/dfl-n3000-nios.c

505

writeq(v, nn->base + N3000_NS_CTRL);

drivers/fpga/dfl.c

1791

writeq(v, base + FME_HDR_PORT_OFST(port_id));

drivers/gpio/gpio-mlxbf.c

119

writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD);

drivers/gpio/gpio-mlxbf.c

120

writeq(gs->csave_regs.pad_control[0],

drivers/gpio/gpio-mlxbf.c

122

writeq(gs->csave_regs.pad_control[1],

drivers/gpio/gpio-mlxbf.c

124

writeq(gs->csave_regs.pad_control[2],

drivers/gpio/gpio-mlxbf.c

126

writeq(gs->csave_regs.pad_control[3],

drivers/gpio/gpio-mlxbf.c

128

writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I);

drivers/gpio/gpio-mlxbf.c

129

writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O);

drivers/gpio/gpio-mmio.c

98

writeq(data, reg);

drivers/gpio/gpio-thunderx.c

113

writeq(txgpio->line_entries[line].fil_bits,

drivers/gpio/gpio-thunderx.c

129

writeq(BIT_ULL(bank_bit), reg);

drivers/gpio/gpio-thunderx.c

153

writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

241

writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

285

writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);

drivers/gpio/gpio-thunderx.c

286

writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);

drivers/gpio/gpio-thunderx.c

297

writeq(GPIO_INTR_INTR,

drivers/gpio/gpio-thunderx.c

306

writeq(GPIO_INTR_ENA_W1C,

drivers/gpio/gpio-thunderx.c

315

writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,

drivers/gpio/gpio-thunderx.c

324

writeq(GPIO_INTR_ENA_W1S,

drivers/gpio/gpio-thunderx.c

356

writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

174

writeq(value, ptr + (gpu_page_idx * 8));

drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c

203

writeq(value, (u64 __iomem *)db);

drivers/gpu/drm/i915/display/intel_dpt.c

40

writeq(pte, addr);

drivers/gpu/drm/i915/gt/intel_ggtt.c

444

writeq(pte, addr);

drivers/gpu/drm/i915/gvt/gtt.c

237

writeq(pte, addr);

drivers/gpu/drm/loongson/lsdc_pixpll.c

267

writeq(src->d, this->mmio);

drivers/gpu/drm/radeon/rs600.c

663

writeq(entry, ptr + (i * 8));

drivers/gpu/drm/xe/xe_ggtt.c

184

writeq(pte, &ggtt->gsm[addr >> XE_PTE_SHIFT]);

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c

162

writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG2);

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c

177

writeq(0x0, privdata->mmio + AMD_C2P_MSG2);

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c

71

writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG1);

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c

86

writeq(0x0, privdata->mmio + AMD_C2P_MSG1);

drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c

55

writeq(0x0, privdata->mmio + amd_get_c2p_val(privdata, 1));

drivers/i2c/busses/i2c-amd-mp2-pci.c

102

writeq((u64)i2c_common->dma_addr,

drivers/i2c/busses/i2c-ismt.c

730

writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);

drivers/i2c/busses/i2c-ismt.c

732

writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);

drivers/infiniband/hw/bng_re/bng_res.h

174

writeq(key, info->db);

drivers/infiniband/hw/bnxt_re/qplib_res.h

506

writeq(key, info->db);

drivers/infiniband/hw/bnxt_re/qplib_res.h

519

writeq(key, info->db);

drivers/infiniband/hw/bnxt_re/qplib_res.h

532

writeq(key, info->priv_db);

drivers/infiniband/hw/bnxt_re/qplib_res.h

541

writeq(key, info->priv_db);

drivers/infiniband/hw/cxgb4/t4.h

575

writeq(*src, dst);

drivers/infiniband/hw/erdma/erdma.h

249

writeq(value, dev->func_bar + reg);

drivers/infiniband/hw/erdma/erdma_cmdq.c

18

writeq(db_data, dev->func_bar + ERDMA_CMDQ_CQDB_REG);

drivers/infiniband/hw/erdma/erdma_cmdq.c

29

writeq(db_data, dev->func_bar + ERDMA_CMDQ_SQDB_REG);

drivers/infiniband/hw/erdma/erdma_cq.c

30

writeq(db_data, cq->kern_cq.db);

drivers/infiniband/hw/erdma/erdma_eq.c

17

writeq(db_data, eq->db);

drivers/infiniband/hw/erdma/erdma_qp.c

657

writeq(db_data, qp->kern_qp.hw_sq_db);

drivers/infiniband/hw/erdma/erdma_qp.c

722

writeq(*(u64 *)rqe, qp->kern_qp.hw_rq_db);

drivers/infiniband/hw/hfi1/chip.c

1329

writeq(value, base);

drivers/infiniband/hw/hfi1/chip.c

9958

writeq(reg, dd->rcvarray_wc + (index * 8));

drivers/infiniband/hw/hfi1/exp_rcv.h

99

writeq(0, dd->rcvarray_wc + (index * 8));

drivers/infiniband/hw/hfi1/pio_copy.c

110

writeq(val.val64, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

118

writeq(0, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

224

writeq(temp, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

233

writeq(carry.val64, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

245

writeq(pbuf->carry.val64, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

269

writeq(pbc, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

282

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

298

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

317

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

328

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

38

writeq(pbc, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

51

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

513

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

540

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

551

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

67

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

708

writeq(0, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

86

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/pio_copy.c

97

writeq(*(u64 *)from, dest);

drivers/infiniband/hw/hfi1/sdma.c

1954

writeq(tail, sde->tail_csr);

drivers/infiniband/hw/hns/hns_roce_device.h

1105

writeq(*(u64 *)val, dest);

drivers/infiniband/hw/qedr/verbs.c

863

writeq(cq->db.raw, cq->db_addr);

drivers/input/misc/sgi_btns.c

33

writeq(status & ~(3U << 23), &mace->perif.audio.control);

drivers/iommu/amd/init.c

2446

writeq(xt.capxt, iommu->mmio_base + irqd->hwirq);

drivers/iommu/amd/init.c

2453

writeq(0, iommu->mmio_base + irqd->hwirq);

drivers/iommu/amd/init.c

426

writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

drivers/iommu/intel/iommu.h

152

#define dmar_writeq(a,v) writeq(v,a)

drivers/mailbox/pcc.c

159

writeq(val, vaddr);

drivers/mailbox/qcom-cpucp-mbox.c

132

writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);

drivers/mailbox/qcom-cpucp-mbox.c

133

writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);

drivers/mailbox/qcom-cpucp-mbox.c

134

writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP);

drivers/mailbox/qcom-cpucp-mbox.c

145

writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP);

drivers/mailbox/qcom-cpucp-mbox.c

65

writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);

drivers/mailbox/qcom-cpucp-mbox.c

80

writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);

drivers/mailbox/qcom-cpucp-mbox.c

93

writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);

drivers/memory/dfl-emif.c

93

writeq(val, base + EMIF_CTRL);

drivers/misc/mrvl_cn10k_dpi.c

190

writeq(val, dpi->reg_base + offset);

drivers/misc/mrvl_cn10k_dpi.c

340

writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);

drivers/misc/mrvl_cn10k_dpi.c

342

writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);

drivers/misc/ocxl/mmio.c

100

writeq(val, (char *)afu->global_mmio_ptr + offset);

drivers/misc/ocxl/mmio.c

163

writeq(tmp, (char *)afu->global_mmio_ptr + offset);

drivers/misc/ocxl/mmio.c

226

writeq(tmp, (char *)afu->global_mmio_ptr + offset);

drivers/misc/ocxl/mmio.c

230

writeq(tmp, (char *)afu->global_mmio_ptr + offset);

drivers/mmc/host/cavium-octeon.c

112

writeq(val, host->base + MIO_EMM_INT(host));

drivers/mmc/host/cavium-octeon.c

114

writeq(val, host->base + MIO_EMM_INT_EN(host));

drivers/mmc/host/cavium-octeon.c

235

writeq(val, host->base + MIO_EMM_INT(host));

drivers/mmc/host/cavium-octeon.c

311

writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));

drivers/mmc/host/cavium-octeon.c

96

writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL);

drivers/mmc/host/cavium-thunderx.c

123

writeq(127, host->base + MIO_EMM_INT_EN(host));

drivers/mmc/host/cavium-thunderx.c

124

writeq(3, host->base + MIO_EMM_DMA_INT_ENA_W1C(host));

drivers/mmc/host/cavium-thunderx.c

126

writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host));

drivers/mmc/host/cavium-thunderx.c

182

writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));

drivers/mmc/host/cavium-thunderx.c

33

writeq(val, host->base + MIO_EMM_INT(host));

drivers/mmc/host/cavium-thunderx.c

34

writeq(val, host->base + MIO_EMM_INT_EN_SET(host));

drivers/mmc/host/cavium.c

212

writeq(emm_switch, host->base + MIO_EMM_SWITCH(host));

drivers/mmc/host/cavium.c

215

writeq(emm_switch, host->base + MIO_EMM_SWITCH(host));

drivers/mmc/host/cavium.c

247

writeq(timeout, slot->host->base + MIO_EMM_WDOG(slot->host));

drivers/mmc/host/cavium.c

267

writeq(wdog, slot->host->base + MIO_EMM_WDOG(host));

drivers/mmc/host/cavium.c

286

writeq(slot->cached_rca, host->base + MIO_EMM_RCA(host));

drivers/mmc/host/cavium.c

293

writeq(emm_sample, host->base + MIO_EMM_SAMPLE(host));

drivers/mmc/host/cavium.c

307

writeq((0x10000 | (dbuf << 6)), host->base + MIO_EMM_BUF_IDX(host));

drivers/mmc/host/cavium.c

396

writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host));

drivers/mmc/host/cavium.c

432

writeq(emm_dma, host->base + MIO_EMM_DMA(host));

drivers/mmc/host/cavium.c

449

writeq(emm_int, host->base + MIO_EMM_INT(host));

drivers/mmc/host/cavium.c

538

writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));

drivers/mmc/host/cavium.c

544

writeq(addr, host->dma_base + MIO_EMM_DMA_ADR(host));

drivers/mmc/host/cavium.c

566

writeq(0, host->dma_base + MIO_EMM_DMA_FIFO_CFG(host));

drivers/mmc/host/cavium.c

573

writeq(addr, host->dma_base + MIO_EMM_DMA_FIFO_ADR(host));

drivers/mmc/host/cavium.c

596

writeq(fifo_cmd, host->dma_base + MIO_EMM_DMA_FIFO_CMD(host));

drivers/mmc/host/cavium.c

613

writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host));

drivers/mmc/host/cavium.c

694

writeq(0x00b00000ull, host->base + MIO_EMM_STS_MASK(host));

drivers/mmc/host/cavium.c

696

writeq(0xe4390080ull, host->base + MIO_EMM_STS_MASK(host));

drivers/mmc/host/cavium.c

697

writeq(emm_dma, host->base + MIO_EMM_DMA(host));

drivers/mmc/host/cavium.c

725

writeq(0x10000ull, host->base + MIO_EMM_BUF_IDX(host));

drivers/mmc/host/cavium.c

742

writeq(dat, host->base + MIO_EMM_BUF_DAT(host));

drivers/mmc/host/cavium.c

805

writeq(0, host->base + MIO_EMM_STS_MASK(host));

drivers/mmc/host/cavium.c

819

writeq(emm_cmd, host->base + MIO_EMM_CMD(host));

drivers/mmc/host/cavium.c

920

writeq(host->emm_cfg, slot->host->base + MIO_EMM_CFG(host));

drivers/mmc/host/cavium.c

944

writeq(0xe4390080ull, host->base + MIO_EMM_STS_MASK(host));

drivers/mmc/host/cavium.c

945

writeq(1, host->base + MIO_EMM_RCA(host));

drivers/mtd/devices/mtd_intel_dg.c

137

writeq(data, base + NVM_TRIGGER_REG);

drivers/net/ethernet/amd/pds_core/core.h

246

writeq(val, &db_page[qtype]);

drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c

80

writeq(value, hw->mmio + reg);

drivers/net/ethernet/broadcom/bnge/bnge.h

240

writeq(val, addr);

drivers/net/ethernet/broadcom/bnxt/bnxt.h

2845

writeq(val, addr);

drivers/net/ethernet/cavium/common/cavium_ptp.c

129

writeq(comp, clock->reg_base + PTP_CLOCK_COMP);

drivers/net/ethernet/cavium/common/cavium_ptp.c

276

writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/cavium/common/cavium_ptp.c

279

writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP);

drivers/net/ethernet/cavium/common/cavium_ptp.c

293

writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/cavium/common/cavium_ptp.c

322

writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

297

writeq((readq(inst_cnt_reg) &

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

374

writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

382

writeq(readq((u8 *)oct->mmio[0].hw_addr +

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

388

writeq(0xffffffffffffffffULL,

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

391

writeq(0xffffffffffffffffULL,

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

447

writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

453

writeq(pkt_in_done, iq->inst_cnt_reg);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

520

writeq(mbox_int_val, mbox->mbox_int_reg);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

584

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

825

writeq(BIT_ULL(q_no),

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

866

writeq(intr64, cn23xx->intr_sum_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

940

writeq(cn23xx->intr_mask64, cn23xx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

944

writeq(intr_val, cn23xx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

950

writeq(intr_val, cn23xx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

962

writeq(0, cn23xx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

966

writeq(intr_val, cn23xx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

972

writeq(intr_val, cn23xx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

142

writeq((readq(inst_cnt_reg) &

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

239

writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

311

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

480

writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

477

writeq(mask, cn6xxx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

486

writeq(0, cn6xxx->intr_enb_reg64);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

602

writeq(intr64, cn6xxx->intr_sum_reg64);

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2410

writeq(val, inst_cnt_reg);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1382

writeq(addr, oct->reg_list.pci_win_wr_addr);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1463

writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1467

writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) |

drivers/net/ethernet/cavium/liquidio/octeon_device.h

737

writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

115

writeq(OCTEON_PFVFACK, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

172

writeq(mbox_cmd->msg.u64, mbox->mbox_write_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

184

writeq(mbox_cmd->data[i], mbox->mbox_write_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

193

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

306

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

316

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

325

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

341

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

371

writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

80

writeq(OCTEON_PFVFERR,

drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c

55

writeq(*((u64 *)hostbuf), mapped_addr);

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

1532

writeq(val, adap->regs + reg_addr);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c

1311

writeq(data[i], addr + 8 * i);

drivers/net/ethernet/chelsio/cxgb4/sge.c

996

writeq(*src, dst);

drivers/net/ethernet/chelsio/cxgb4vf/adapter.h

484

writeq(val, adapter->regs + reg_addr);

drivers/net/ethernet/chelsio/cxgb4vf/sge.c

1018

writeq((__force u64)*src, dst);

drivers/net/ethernet/cisco/enic/vnic_cq.c

47

writeq(paddr, &cq->ctrl->ring_base);

drivers/net/ethernet/cisco/enic/vnic_cq.c

58

writeq(cq_message_addr, &cq->ctrl->cq_message_addr);

drivers/net/ethernet/cisco/enic/vnic_dev.c

233

writeq(vdev->args[i], &devcmd->args[i]);

drivers/net/ethernet/cisco/enic/vnic_rq.c

110

writeq(paddr, &rq->ctrl->ring_base);

drivers/net/ethernet/cisco/enic/vnic_wq.c

130

writeq(paddr, &wq->ctrl->ring_base);

drivers/net/ethernet/fungible/funcore/fun_dev.c

273

writeq(funq->sq_dma_addr, fdev->bar + NVME_REG_ASQ);

drivers/net/ethernet/fungible/funcore/fun_dev.c

274

writeq(funq->cq_dma_addr, fdev->bar + NVME_REG_ACQ);

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

335

writeq(*(u64 *)&db, db_base + db_ofs);

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

94

writeq(*((u64 *)&db), DB_ADDR(queue, pi));

drivers/net/ethernet/intel/iavf/iavf_osdep.h

19

#define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))

drivers/net/ethernet/intel/ice/ice_osdep.h

24

#define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))

drivers/net/ethernet/intel/idpf/idpf_mem.h

17

#define idpf_mbx_wr64(a, reg, value) writeq((value), ((a)->mbx.vaddr + (reg)))

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

153

#ifndef writeq

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

154

#define writeq writeq

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

168

writeq(value, reg_addr + reg);

drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c

103

writeq(OCTEP_CTRL_MBOX_STATUS_INIT,

drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c

121

writeq(mbox->version, OCTEP_CTRL_MBOX_INFO_HOST_VERSION(mbox->barmem));

drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c

124

writeq(OCTEP_CTRL_MBOX_STATUS_READY,

drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c

267

writeq(0, OCTEP_CTRL_MBOX_INFO_HOST_VERSION(mbox->barmem));

drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c

268

writeq(OCTEP_CTRL_MBOX_STATUS_INVALID,

drivers/net/ethernet/marvell/octeon_ep/octep_main.c

594

writeq(1UL << OCTEP_OQ_INTR_RESEND_BIT, oq->pkts_sent_reg);

drivers/net/ethernet/marvell/octeon_ep/octep_main.c

595

writeq(1UL << OCTEP_IQ_INTR_RESEND_BIT, iq->inst_cnt_reg);

drivers/net/ethernet/marvell/octeon_ep/octep_main.h

347

writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))

drivers/net/ethernet/marvell/octeon_ep/octep_main.h

370

writeq(addr, oct->pci_win_regs.pci_win_rd_addr);

drivers/net/ethernet/marvell/octeon_ep/octep_main.h

392

writeq(addr, oct->pci_win_regs.pci_win_wr_addr);

drivers/net/ethernet/marvell/octeon_ep/octep_main.h

393

writeq(val, oct->pci_win_regs.pci_win_wr_data);

drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c

122

writeq(cmd.u64, mbox->pf_vf_data_reg);

drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c

470

writeq(rsp.u64, mbox->vf_pf_data_reg);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.c

328

writeq(1UL << OCTEP_VF_OQ_INTR_RESEND_BIT, oq->pkts_sent_reg);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.c

329

writeq(1UL << OCTEP_VF_IQ_INTR_RESEND_BIT, iq->inst_cnt_reg);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h

315

writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off))

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.c

124

writeq(cmd.u64, mbox->mbox_write_reg);

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

131

writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +

drivers/net/ethernet/marvell/octeontx2/af/mbox.c

365

writeq(intr_val, (void __iomem *)mbox->reg_base +

drivers/net/ethernet/marvell/octeontx2/af/mcs.h

169

writeq(val, mcs->reg_base + offset);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

134

writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

258

writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

259

writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

260

writeq(timestamp / NSEC_PER_SEC,

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

265

writeq(nxt_rollover_set, ptp->reg_base + PTP_NXT_ROLLOVER_SET);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

266

writeq(curr_rollover_set, ptp->reg_base + PTP_CURR_ROLLOVER_SET);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

272

writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

301

writeq(delta, ptp->reg_base + PTP_NANO_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

302

writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

308

writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

354

writeq(comp, ptp->reg_base + PTP_CLOCK_COMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

389

writeq(0, ptp->reg_base + PTP_NANO_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

390

writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

391

writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

392

writeq(0, ptp->reg_base + PTP_CURR_ROLLOVER_SET);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

393

writeq(0x3b9aca00, ptp->reg_base + PTP_NXT_ROLLOVER_SET);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

394

writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

415

writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

419

writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

427

writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

447

writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

484

writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

486

writeq(0, ptp->reg_base + PTP_PPS_THRESH_HI);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

487

writeq(0, ptp->reg_base + PTP_PPS_THRESH_LO);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

491

writeq(((u64)period << 32), ptp->reg_base + PTP_PPS_HI_INCR);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

492

writeq(((u64)period << 32), ptp->reg_base + PTP_PPS_LO_INCR);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

495

writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

507

writeq((0x1dcd6500ULL - ptp->clock_period) << 32,

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

585

writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

675

writeq(val, rvu->afreg_base + ((block << 28) | offset));

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

685

writeq(val, rvu->pfreg_base + offset);

drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c

380

writeq(cfg, base + offset);

drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c

44

writeq((*val), (lmt_map_base + index));

drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c

50

writeq(cfg, (lmt_map_base + (index + 8)));

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

693

writeq(val, addr);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

773

#define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

352

writeq(MBOX_DOWN_MSG, (void __iomem *)pfvf_mbox->reg_base + offset);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c

65

writeq(int_status, priv->base + MLXBF_GIGE_INT_STATUS);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

113

writeq(control, priv->base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

125

writeq(control, priv->base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

141

writeq(control, priv->base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

195

writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

217

writeq(0, priv->base + MLXBF_GIGE_INT_EN);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

105

writeq(control, base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

154

writeq(priv->rx_wqe_base_dma, priv->base + MLXBF_GIGE_RX_WQ_BASE);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

167

writeq(priv->rx_cqe_base_dma, priv->base + MLXBF_GIGE_RX_CQ_BASE);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

170

writeq(priv->rx_q_entries, priv->base + MLXBF_GIGE_RX_WQE_PI);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

175

writeq(data, priv->base + MLXBF_GIGE_RX);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

178

writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN,

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

180

writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN,

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

183

writeq(ilog2(priv->rx_q_entries),

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

191

writeq(data, priv->base + MLXBF_GIGE_INT_MASK);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

196

writeq(data, priv->base + MLXBF_GIGE_RX_DMA);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

21

writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

227

writeq(data, priv->base + MLXBF_GIGE_RX_DMA);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

250

writeq(0, priv->base + MLXBF_GIGE_RX_WQ_BASE);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

251

writeq(0, priv->base + MLXBF_GIGE_RX_CQ_BASE);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

31

writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

320

writeq(rx_pi, priv->base + MLXBF_GIGE_RX_WQE_PI);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

360

writeq(data, priv->base + MLXBF_GIGE_INT_MASK);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

43

writeq(control, base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

55

writeq(control, base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

64

writeq(dmac, base + MLXBF_GIGE_RX_MAC_FILTER +

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

87

writeq(control, base + MLXBF_GIGE_CONTROL);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

90

writeq(0, base + MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c

94

writeq(end_mac, base + MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_tx.c

267

writeq(priv->tx_pi, priv->base + MLXBF_GIGE_TX_PRODUCER_INDEX);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_tx.c

31

writeq(priv->tx_wqe_base_dma, priv->base + MLXBF_GIGE_TX_WQ_BASE);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_tx.c

43

writeq(priv->tx_cc_dma, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_tx.c

45

writeq(ilog2(priv->tx_q_entries),

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_tx.c

88

writeq(0, priv->base + MLXBF_GIGE_TX_WQ_BASE);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_tx.c

89

writeq(0, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS);

drivers/net/ethernet/microsoft/mana/gdma_main.c

376

writeq(e.as_uint64, addr);

drivers/net/ethernet/netronome/nfp/nfp_net.h

817

writeq(val, nn->dp.ctrl_bar + off);

drivers/net/ethernet/pensando/ionic/ionic_regs.h

133

writeq(val, &db_page[qtype]);

drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c

1401

writeq(*data, addr);

drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c

1429

writeq(data, addr);

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

1262

writeq(*data, addr);

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

1290

writeq(data, addr);

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

42

#ifndef writeq

drivers/net/ethernet/rocker/rocker_main.c

117

writeq((val), (rocker)->hw_addr + (ROCKER_ ## reg))

drivers/net/ethernet/sun/niu.c

101

#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))

drivers/net/ethernet/sun/niu.c

104

#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))

drivers/net/ethernet/sun/niu.c

92

#define nw64(reg, val) writeq((val), np->regs + (reg))

drivers/net/ethernet/sun/niu.c

95

#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))

drivers/net/ethernet/sun/niu.c

98

#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))

drivers/net/mdio/mdio-cavium.h

113

#define oct_mdio_writeq(val, addr) writeq(val, addr)

drivers/ntb/hw/amd/ntb_hw_amd.h

78

#ifdef writeq

drivers/ntb/hw/amd/ntb_hw_amd.h

79

#define write64 writeq

drivers/nvdimm/region_devs.c

1150

writeq(1, ndrd_get_flush_wpq(ndrd, i, idx));

drivers/nvme/host/apple.c

1147

writeq(anv->adminq.sq_dma_addr, anv->mmio_nvme + NVME_REG_ASQ);

drivers/nvme/host/apple.c

1148

writeq(anv->adminq.cq_dma_addr, anv->mmio_nvme + NVME_REG_ACQ);

drivers/nvme/host/apple.c

1152

writeq(anv->adminq.tcb_dma_addr,

drivers/nvme/host/apple.c

1154

writeq(anv->ioq.tcb_dma_addr,

drivers/parisc/sba_iommu.c

136

#define WRITE_REG64(val, addr) writeq((val), (addr))

drivers/parport/parport_ip32.c

519

writeq(ctxval, ctxreg);

drivers/parport/parport_ip32.c

581

writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);

drivers/parport/parport_ip32.c

601

writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);

drivers/parport/parport_ip32.c

610

writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);

drivers/parport/parport_ip32.c

649

writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);

drivers/parport/parport_ip32.c

672

writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);

drivers/parport/parport_ip32.c

705

writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);

drivers/pci/controller/pci-thunder-pem.c

235

writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);

drivers/pci/controller/pci-thunder-pem.c

244

writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);

drivers/pci/controller/pci-thunder-pem.c

283

writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);

drivers/pci/controller/pci-thunder-pem.c

54

writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);

drivers/pci/controller/pci-thunder-pem.c

83

writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);

drivers/pci/hotplug/octep_hp.c

272

writeq(intr_val, hp_ctrl->base + OCTEP_HP_INTR_OFFSET(type));

drivers/pci/switch/switchtec.c

1303

writeq(stdev->dma_mrpc_dma_addr, &stdev->mmio_mrpc->dma_addr);

drivers/pci/switch/switchtec.c

1647

writeq(0, &stdev->mmio_mrpc->dma_addr);

drivers/perf/arm_cspmu/arm_cspmu.c

710

writeq(val, cspmu->base1 + offset);

drivers/perf/arm_smmuv3_pmu.c

205

writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));

drivers/perf/arm_smmuv3_pmu.c

224

writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);

drivers/perf/arm_smmuv3_pmu.c

229

writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);

drivers/perf/arm_smmuv3_pmu.c

234

writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);

drivers/perf/arm_smmuv3_pmu.c

240

writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);

drivers/perf/arm_smmuv3_pmu.c

699

writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);

drivers/perf/cxl_pmu.c

594

writeq(0, base + CXL_PMU_FREEZE_REG);

drivers/perf/cxl_pmu.c

609

writeq(GENMASK_ULL(63, 0), base + CXL_PMU_FREEZE_REG);

drivers/perf/cxl_pmu.c

638

writeq(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0));

drivers/perf/cxl_pmu.c

668

writeq(cfg, base + CXL_PMU_COUNTER_CFG_REG(hwc->idx));

drivers/perf/cxl_pmu.c

671

writeq(0, base + CXL_PMU_COUNTER_REG(hwc->idx));

drivers/perf/cxl_pmu.c

725

writeq(cfg, base + CXL_PMU_COUNTER_CFG_REG(hwc->idx));

drivers/perf/cxl_pmu.c

794

writeq(overflowed, base + CXL_PMU_OVERFLOW_REG);

drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c

58

writeq(val, cpa_pmu->base + hisi_cpa_pmu_get_counter_offset(hwc->idx));

drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c

105

writeq(val, ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx));

drivers/perf/hisilicon/hisi_uncore_hha_pmu.c

179

writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(hwc->idx));

drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c

175

writeq(val, (void __iomem *)hwc->event_base + reg);

drivers/perf/hisilicon/hisi_uncore_mn_pmu.c

86

writeq(val, mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx));

drivers/perf/hisilicon/hisi_uncore_noc_pmu.c

105

writeq(val, noc_pmu->base + NOC_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->idx));

drivers/perf/hisilicon/hisi_uncore_pa_pmu.c

165

writeq(val, pa_pmu->base + hisi_pa_pmu_get_counter_offset(hwc->idx));

drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c

227

writeq(val, sllc_pmu->base + SLLC_EVENT_CNTn(regs->event_cnt0, hwc->idx));

drivers/perf/hisilicon/hisi_uncore_uc_pmu.c

300

writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx));

drivers/perf/hisilicon/hns3_pmu.c

763

writeq(val, hns3_pmu->base + offset);

drivers/perf/starfive_starlink_pmu.c

169

writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CYCLE_COUNTER);

drivers/perf/starfive_starlink_pmu.c

171

writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_EVENT_COUNTER +

drivers/perf/starfive_starlink_pmu.c

200

writeq(event->hw.config, starlink_pmu->pmu_base +

drivers/perf/starfive_starlink_pmu.c

206

writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE);

drivers/perf/starfive_starlink_pmu.c

208

writeq(STARLINK_PMU_GLOBAL_ENABLE, starlink_pmu->pmu_base +

drivers/perf/starfive_starlink_pmu.c

221

writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CONTROL);

drivers/perf/starfive_starlink_pmu.c

229

writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE);

drivers/perf/starfive_starlink_pmu.c

417

writeq(BIT_ULL(idx), starlink_pmu->pmu_base +

drivers/platform/mellanox/mlxbf-bootctl.c

376

writeq(0, mlxbf_rsh_semaphore);

drivers/platform/mellanox/mlxbf-bootctl.c

431

writeq(data, mlxbf_rsh_scratch_buf_data);

drivers/platform/mellanox/mlxbf-bootctl.c

444

writeq(data, mlxbf_rsh_scratch_buf_data);

drivers/platform/mellanox/mlxbf-pmc.c

1091

writeq(value, addr);

drivers/platform/mellanox/mlxbf-tmfifo.c

1306

writeq(ctl, fifo->tx.ctl);

drivers/platform/mellanox/mlxbf-tmfifo.c

1316

writeq(ctl, fifo->rx.ctl);

drivers/platform/mellanox/mlxbf-tmfifo.c

568

writeq(*(u64 *)&hdr, fifo->tx.data);

drivers/platform/mellanox/mlxbf-tmfifo.c

585

writeq(data, fifo->tx.data);

drivers/platform/mellanox/mlxbf-tmfifo.c

645

writeq(data, fifo->tx.data);

drivers/platform/mellanox/mlxbf-tmfifo.c

721

writeq(*(u64 *)&hdr, fifo->tx.data);

drivers/platform/mellanox/mlxbf-tmfifo.c

911

writeq(0, vring->fifo->tx.data);

drivers/platform/x86/amd/pmc/mp2_stb.c

95

writeq(mp2->dma_addr, mp2->mmio + AMD_C2P_MSG1);

drivers/platform/x86/intel/plr_tpmi.c

118

writeq(val, plr_die->base + offset);

drivers/platform/x86/intel/sdsi.c

129

writeq(from[i], &to[i]);

drivers/platform/x86/intel/sdsi.c

147

writeq(control, priv->control_addr);

drivers/platform/x86/intel/sdsi.c

256

writeq(control, priv->control_addr);

drivers/platform/x86/intel/sdsi.c

279

writeq(control, priv->control_addr);

drivers/platform/x86/intel/sdsi.c

305

writeq(info->payload[0], priv->mbox_addr);

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1795

writeq(pd_info->saved_sst_cp_control, cp_base + SST_CP_CONTROL_OFFSET);

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1805

writeq(pd_info->saved_pp_control, power_domain_info->sst_base +

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

589

writeq(val, power_domain_info->sst_base + power_domain_info->sst_header.cp_offset +\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

772

writeq(val, power_domain_info->sst_base +

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

808

writeq(val, power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

267

writeq(control, cluster_info->cluster_base + UNCORE_CONTROL_INDEX);

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

288

writeq(control, (cluster_info->cluster_base + UNCORE_CONTROL_INDEX));

drivers/platform/x86/intel/vsec_tpmi.c

297

writeq(data, tpmi_info->tpmi_control_mem + TPMI_COMMAND_OFFSET);

drivers/platform/x86/intel/vsec_tpmi.c

309

writeq(control, tpmi_info->tpmi_control_mem + TPMI_CONTROL_STATUS_OFFSET);

drivers/platform/x86/intel/vsec_tpmi.c

332

writeq(TPMI_CONTROL_STATUS_CPL, tpmi_info->tpmi_control_mem + TPMI_CONTROL_STATUS_OFFSET);

drivers/powercap/intel_rapl_tpmi.c

86

writeq(val, ra->reg.mmio);

drivers/scsi/aacraid/aacraid.h

1211

#if defined(writeq)

drivers/scsi/aacraid/aacraid.h

1212

#define src_writeq(AEP, CSR, value) writeq(value, \

drivers/scsi/aacraid/src.c

491

#if !defined(writeq)

drivers/scsi/aacraid/src.c

556

#if defined(writeq)

drivers/scsi/aacraid/src.c

599

#if defined(writeq)

drivers/scsi/csiostor/csio_hw.h

572

#define csio_wr_reg64(_h, _v, _r) writeq((_v), \

drivers/scsi/fnic/vnic_cq.c

49

writeq(paddr, &cq->ctrl->ring_base);

drivers/scsi/fnic/vnic_cq.c

60

writeq(cq_message_addr, &cq->ctrl->cq_message_addr);

drivers/scsi/fnic/vnic_dev.c

273

writeq(*a0, &devcmd->args[0]);

drivers/scsi/fnic/vnic_dev.c

274

writeq(*a1, &devcmd->args[1]);

drivers/scsi/fnic/vnic_rq.c

107

writeq(paddr, &rq->ctrl->ring_base);

drivers/scsi/fnic/vnic_wq.c

150

writeq(paddr, &wq->ctrl->ring_base);

drivers/scsi/fnic/vnic_wq.c

172

writeq(paddr, &wq->ctrl->ring_base);

drivers/scsi/fnic/vnic_wq_copy.c

91

writeq(paddr, &wq->ctrl->ring_base);

drivers/scsi/ipr.c

740

writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);

drivers/scsi/ipr.c

7594

writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);

drivers/scsi/ipr.c

7657

writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);

drivers/scsi/ipr.c

908

writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);

drivers/scsi/ipr.h

1921

#ifndef writeq

drivers/scsi/megaraid/megaraid_sas_fusion.c

296

#if defined(writeq) && defined(CONFIG_64BIT)

drivers/scsi/megaraid/megaraid_sas_fusion.c

299

writeq(req_data, &instance->reg_set->inbound_low_queue_port);

drivers/scsi/mpi3mr/mpi3mr_fw.c

29

#if defined(writeq) && defined(CONFIG_64BIT)

drivers/scsi/mpi3mr/mpi3mr_fw.c

33

writeq(b, addr);

drivers/scsi/mpt3sas/mpt3sas_base.c

4126

#if defined(writeq) && defined(CONFIG_64BIT)

drivers/scsi/qla2xxx/qla_nx.c

776

writeq(*(u64 *)data, addr);

drivers/scsi/qla4xxx/ql4_nx.c

832

writeq(*(u64 *)data, addr);

drivers/scsi/smartpqi/smartpqi_init.c

4394

writeq((u64)admin_queues->iq_element_array_bus_addr,

drivers/scsi/smartpqi/smartpqi_init.c

4396

writeq((u64)admin_queues->oq_element_array_bus_addr,

drivers/scsi/smartpqi/smartpqi_init.c

4398

writeq((u64)admin_queues->iq_ci_bus_addr,

drivers/scsi/smartpqi/smartpqi_init.c

4400

writeq((u64)admin_queues->oq_pi_bus_addr,

drivers/scsi/snic/vnic_cq.c

42

writeq(paddr, &cq->ctrl->ring_base);

drivers/scsi/snic/vnic_cq.c

53

writeq(cq_message_addr, &cq->ctrl->cq_message_addr);

drivers/scsi/snic/vnic_wq.c

149

writeq(paddr, &wq->ctrl->ring_base);

drivers/spi/spi-altera-dfl.c

56

writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);

drivers/spi/spi-altera-dfl.c

81

writeq(val, base + INDIRECT_WR_DATA);

drivers/spi/spi-altera-dfl.c

82

writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);

drivers/spi/spi-amd.c

163

writeq(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));

drivers/spi/spi-cadence-xspi.c

639

writeq(*buffer++, addr);

drivers/spi/spi-cadence-xspi.c

647

writeq(tmp_buf, addr);

drivers/spi/spi-cavium-octeon.c

77

writeq(0, p->register_base + OCTEON_SPI_CFG(p));

drivers/spi/spi-cavium-thunderx.c

94

writeq(0, p->register_base + OCTEON_SPI_CFG(p));

drivers/spi/spi-cavium.c

102

writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));

drivers/spi/spi-cavium.c

113

writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));

drivers/spi/spi-cavium.c

66

writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));

drivers/spi/spi-cavium.c

78

writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));

drivers/spi/spi-cavium.c

85

writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

142

writeq(reg_val, (void __iomem *) (proc_priv->mmio_base + offset));

drivers/thermal/intel/int340x_thermal/processor_thermal_device_pci.c

146

writeq(status & ~SOC_WT_RES_INT_STATUS_MASK,

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

42

writeq(val, ra->reg.mmio);

drivers/thermal/intel/int340x_thermal/processor_thermal_soc_slider.c

172

writeq(val, proc_priv->mmio_base + SOC_POWER_SLIDER_OFFSET);

drivers/vdpa/octeon_ep/octep_vdpa_main.c

578

writeq(0, addr + OCTEP_VF_MBOX_DATA(0));

drivers/vdpa/octeon_ep/octep_vdpa_main.c

746

writeq(OCTEP_DEV_READY_SIGNATURE, addr + OCTEP_PF_MBOX_DATA(i));

drivers/vfio/fsl-mc/vfio_fsl_mc.c

286

writeq(cmd_data[0], ioaddr);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

295

writeq(doorbell, qm->io_base + dbase);

drivers/watchdog/marvell_gti_wdt.c

102

writeq(GTI_CWD_POKE_VAL,

drivers/watchdog/marvell_gti_wdt.c

119

writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx),

drivers/watchdog/marvell_gti_wdt.c

123

writeq(GTI_CWD_INT_ENA_SET_VAL(priv->wdt_timer_idx),

drivers/watchdog/marvell_gti_wdt.c

129

writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

140

writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx),

drivers/watchdog/marvell_gti_wdt.c

146

writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

182

writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

195

writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx),

drivers/watchdog/marvell_gti_wdt.c

90

writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx),

fs/xfs/xfs_trace.h

1536

__field(int, writeq)

fs/xfs/xfs_trace.h

1553

__entry->writeq = list_empty(&log->l_write_head.waiters);

fs/xfs/xfs_trace.h

1576

__entry->writeq ? "empty" : "active",

include/asm-generic/io.h

1001

writeq(swab64(value), addr);

include/asm-generic/io.h

301

#ifndef writeq

include/asm-generic/io.h

302

#define writeq writeq

include/asm-generic/io.h

417

#if defined(writeq) && !defined(writeq_relaxed)

include/asm-generic/io.h

949

writeq(value, addr);

include/linux/coresight.h

567

writeq(val, csa->base + offset);

include/linux/io-64-nonatomic-hi-lo.h

46

#ifndef writeq

include/linux/io-64-nonatomic-lo-hi.h

46

#ifndef writeq

include/linux/iosys-map.h

349

u64: writeq(val_, vaddr_iomem_)

include/linux/qed/qed_if.h

446

#define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \

include/sound/hdaudio.h

462

#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)

lib/iomap.c

200

#define mmio_write64be(val,port) writeq(swab64(val),port)

lib/iomap.c

269

writeq(val, addr));

lib/iomap.c

277

writeq(val, addr));

rust/helpers/io.c

62

writeq(value, addr);

sound/core/seq/oss/seq_oss_device.h

90

struct seq_oss_writeq *writeq;

sound/core/seq/oss/seq_oss_event.c

435

snd_seq_oss_writeq_wakeup(dp->writeq, rec->t.time);

sound/core/seq/oss/seq_oss_init.c

235

dp->writeq = snd_seq_oss_writeq_new(dp, maxqlen);

sound/core/seq/oss/seq_oss_init.c

236

if (!dp->writeq) {

sound/core/seq/oss/seq_oss_init.c

388

snd_seq_oss_writeq_delete(dp->writeq);

sound/core/seq/oss/seq_oss_init.c

441

if (dp->writeq)

sound/core/seq/oss/seq_oss_init.c

442

snd_seq_oss_writeq_clear(dp->writeq);

sound/core/seq/oss/seq_oss_ioctl.c

107

if (! is_write_mode(dp->file_mode) || dp->writeq == NULL)

sound/core/seq/oss/seq_oss_ioctl.c

109

return put_user(snd_seq_oss_writeq_get_free_size(dp->writeq), p) ? -EFAULT : 0;

sound/core/seq/oss/seq_oss_ioctl.c

154

if (val >= dp->writeq->maxlen)

sound/core/seq/oss/seq_oss_ioctl.c

155

val = dp->writeq->maxlen - 1;

sound/core/seq/oss/seq_oss_ioctl.c

156

snd_seq_oss_writeq_set_output(dp->writeq, val);

sound/core/seq/oss/seq_oss_ioctl.c

84

if (! is_write_mode(dp->file_mode) || dp->writeq == NULL)

sound/core/seq/oss/seq_oss_ioctl.c

86

while (snd_seq_oss_writeq_sync(dp->writeq))

sound/core/seq/oss/seq_oss_rw.c

196

if (dp->writeq && is_write_mode(dp->file_mode)) {

sound/core/seq/oss/seq_oss_rw.c

89

if (! is_write_mode(dp->file_mode) || dp->writeq == NULL)

sound/mips/sgio2audio.c

109

writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) |

sound/mips/sgio2audio.c

130

writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) |

sound/mips/sgio2audio.c

378

writeq(src_pos, &mace->perif.audio.chan[ch].read_ptr); /* in bytes */

sound/mips/sgio2audio.c

426

writeq(dst_pos, &mace->perif.audio.chan[ch].write_ptr); /* in bytes */

sound/mips/sgio2audio.c

439

writeq(CHANNEL_CONTROL_RESET, &mace->perif.audio.chan[ch].control);

sound/mips/sgio2audio.c

441

writeq(0, &mace->perif.audio.chan[ch].control);

sound/mips/sgio2audio.c

448

writeq(CHANNEL_DMA_ENABLE | CHANNEL_INT_THRESHOLD_50,

sound/mips/sgio2audio.c

457

writeq(0, &mace->perif.audio.chan[chan->idx].control);

sound/mips/sgio2audio.c

750

writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control);

sound/mips/sgio2audio.c

752

writeq(0, &mace->perif.audio.control);

sound/mips/sgio2audio.c

830

writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control);

sound/mips/sgio2audio.c

832

writeq(0, &mace->perif.audio.control);

sound/mips/sgio2audio.c

836

writeq(chip->ring_base_dma, &mace->perif.ctrl.ringbase);

sound/soc/loongson/loongson_dma.c

110

writeq(val, order_reg);

sound/soc/loongson/loongson_dma.c

122

writeq(val, order_reg);

sound/soc/loongson/loongson_dma.c

83

writeq(val, order_reg);

sound/soc/sof/iomem-utils.c

40

writeq(value, addr);

sound/soc/sof/ops.h

337

writeq(value, sdev->bar[bar] + offset);

tools/arch/x86/include/asm/io.h

59

build_mmio_write(writeq, "q", u64, "r", :"memory")

tools/arch/x86/include/asm/io.h

70

#define writeq writeq

tools/include/asm-generic/io.h

245

#ifndef writeq

tools/include/asm-generic/io.h

246

#define writeq writeq

tools/include/asm-generic/io.h

344

#if defined(writeq) && !defined(writeq_relaxed)

tools/testing/selftests/vfio/lib/drivers/dsa/dsa.c

180

writeq(1, dsa->grpcfg_table + offsetof(struct grpcfg, wqs[0]));

tools/testing/selftests/vfio/lib/drivers/dsa/dsa.c

181

writeq(1, dsa->grpcfg_table + offsetof(struct grpcfg, engines));

tools/testing/selftests/vfio/lib/drivers/ioat/ioat.c

198

writeq(desc_iova, registers + IOAT2_CHAINADDR_OFFSET);