readw_relaxed
extern u16 readw_relaxed(const volatile void __iomem *addr);
#define readw_relaxed readw_relaxed
EXPORT_SYMBOL(readw_relaxed);
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define imx_readw readw_relaxed
return readw_relaxed(oh->_mpu_rt_va + reg_offs);
#define readw(c) ({ u16 __v = readw_relaxed(c); rmb(); __v; })
#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
*val = readw_relaxed(vaddr);
prev_val = readw_relaxed(vaddr);
return readw_relaxed(ctx->regs + reg);
val = readw_relaxed(ddata->module_va + offset);
u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
return (u64)readw_relaxed(to_mmio_clksrc(c)->reg);
return ~(u64)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask;
val = readw_relaxed(addr);
val = readw_relaxed(addr);
val |= readw_relaxed(addr + 2) << 16;
rev = readw_relaxed(bank->base + bank->regs->revision);
return readw_relaxed(i2c_dev->base + reg);
rev = readw_relaxed(omap->base + 0x04);
return readw_relaxed(omap->base +
return readw_relaxed(adc->common->base + adc->offset + reg);
irqstat = readw_relaxed(clps711x_intc->intmr[0]) &
readw_relaxed(clps711x_intc->intsr[0]);
irqstat = readw_relaxed(clps711x_intc->intmr[1]) &
readw_relaxed(clps711x_intc->intsr[1]);
cd->saved_polarity_conf[i] = readw_relaxed(addr + i * 4);
val = readw_relaxed(cd->base + offset) | mask;
val = readw_relaxed(cd->base + offset) & ~mask;
tmp = readw_relaxed(priv->base + IRQRR);
tmp = readw_relaxed(priv->base + ICR1);
data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
readw_relaxed(&msgq->type),
readw_relaxed(&msgq->num),
readw_relaxed((dev)->regs + SDMMC_##reg)
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
return readw_relaxed(nfc->regs + reg);
*(u16 *)buf = readw_relaxed(io_addr_r);
*(u16 *)buf = readw_relaxed(io_addr_r);
#define readw_o readw_relaxed
#define readw_u readw_relaxed
*val = readw_relaxed(conf_data + (where & 2));
return readw_relaxed(pcie->cra_base + reg);
return (readw_relaxed(addr) & PCI_EXP_LNKSTA_DLLLA);
*value = readw_relaxed(addr);
ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA);
reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
#define RD_REG_WORD(addr) readw_relaxed(addr)
return readw_relaxed(addr);
return readw_relaxed(dws->regs + offset);
rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD);
var = readw_relaxed(spi_st->base + SSC_CTL);
*((u16 *)val) = readw_relaxed(addr);
*((u16 *)val) = readw_relaxed(addr);
*rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR);
*rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR);
*rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
data = readw_relaxed(tmu->base + IMX91_TMU_DATA0);
readl_relaxed(addr) : readw_relaxed(addr);
u16 val = readw_relaxed(priv->base + RWTCNT);
#ifndef readw_relaxed
#define readw_relaxed readw_relaxed
readx_poll_timeout(readw_relaxed, addr, val, cond, delay_us, timeout_us)
readx_poll_timeout_atomic(readw_relaxed, addr, val, cond, delay_us, timeout_us)
return readw_relaxed(addr);
return !from_cache ? readw_relaxed(addr) :
#ifndef readw_relaxed
#define readw_relaxed readw_relaxed