Symbol: div
crypto/krb5/src/util/verto/ev.c
1172
static inline T ecb_div_rd (T val, T div)
crypto/krb5/src/util/verto/ev.c
1174
return val < 0 ? - ((-val + div - 1) / div) : (val ) / div;
crypto/krb5/src/util/verto/ev.c
1177
static inline T ecb_div_ru (T val, T div)
crypto/krb5/src/util/verto/ev.c
1179
return val < 0 ? - ((-val ) / div) : (val + div - 1) / div;
crypto/krb5/src/util/verto/ev.c
1182
#define ecb_div_rd(val,div) ((val) < 0 ? - ((-(val) + (div) - 1) / (div)) : ((val) ) / (div))
crypto/krb5/src/util/verto/ev.c
1183
#define ecb_div_ru(val,div) ((val) < 0 ? - ((-(val) ) / (div)) : ((val) + (div) - 1) / (div))
include/stdlib.h
94
div_t div(int, int) __pure2;
sys/amd64/amd64/machdep.c
1426
setidt(IDT_DE, pti ? &IDTVEC(div_pti) : &IDTVEC(div), SDT_SYSIGT,
sys/amd64/amd64/machdep.c
500
IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
sys/arm/allwinner/aw_i2s.c
246
sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div)
sys/arm/allwinner/aw_i2s.c
251
if (divmap[n] == div)
sys/arm/allwinner/aw_mmc.c
1331
uint32_t reg, div = 1;
sys/arm/allwinner/aw_mmc.c
1416
div = 2;
sys/arm/allwinner/aw_mmc.c
1423
reg |= div - 1;
sys/arm/allwinner/if_awg.c
1618
int error, div;
sys/arm/allwinner/if_awg.c
1716
div = freq / MDIO_FREQ;
sys/arm/allwinner/if_awg.c
1717
if (div <= 16)
sys/arm/allwinner/if_awg.c
1719
else if (div <= 32)
sys/arm/allwinner/if_awg.c
1721
else if (div <= 64)
sys/arm/allwinner/if_awg.c
1723
else if (div <= 128)
sys/arm/freescale/imx/imx6_ipu.c
628
uint32_t div, i;
sys/arm/freescale/imx/imx6_ipu.c
632
div = 255;
sys/arm/freescale/imx/imx6_ipu.c
637
div = i;
sys/arm/freescale/imx/imx6_ipu.c
642
return (div);
sys/arm/freescale/imx/imx6_ipu.c
648
uint32_t div;
sys/arm/freescale/imx/imx6_ipu.c
660
div = ipu_calc_divisor(imx_ccm_ipu_hz(), freq);
sys/arm/freescale/imx/imx6_ipu.c
664
IPU_WRITE4(sc, bs_clkgen_offset, DI_BS_CLKGEN0(div, 0));
sys/arm/freescale/imx/imx6_ipu.c
666
IPU_WRITE4(sc, bs_clkgen_offset + 4, DI_BS_CLKGEN1_DOWN(div / 2, div % 2));
sys/arm/freescale/imx/imx6_ipu.c
670
dw_gen = DW_GEN_DI_ACCESS_SIZE(div - 1) | DW_GEN_DI_COMPONENT_SIZE(div - 1);
sys/arm/freescale/imx/imx6_ipu.c
676
dw_set = DW_SET_DATA_CNT_DOWN(div * 2) | DW_SET_DATA_CNT_UP(0);
sys/arm/freescale/imx/imx_i2c.c
600
u_int busfreq, div, i, ipgfreq;
sys/arm/freescale/imx/imx_i2c.c
625
div = howmany(ipgfreq, busfreq);
sys/arm/freescale/imx/imx_i2c.c
627
if (clkdiv_table[i].divisor >= div)
sys/arm/freescale/vybrid/vf_sai.c
110
uint32_t div; /* Bit Clock Divide. Division value is (div + 1) * 2. */
sys/arm/freescale/vybrid/vf_sai.c
357
reg |= (sr->div << 0);
sys/arm/mv/armada/thermal.c
261
u_long m, b, div;
sys/arm/mv/armada/thermal.c
274
div = tdata->coef_div;
sys/arm/mv/armada/thermal.c
277
tmp = ((m * reg) - b) / div;
sys/arm/mv/armada/thermal.c
279
tmp = (b - (m * reg)) / div;
sys/arm/mv/clk/a37x0_xtal.c
93
def.div = 0;
sys/arm/mv/clk/periph.c
69
struct clk_div_def *div, int id)
sys/arm/mv/clk/periph.c
73
div->clkdef.id = id;
sys/arm/mv/clk/periph.c
75
error = clknode_div_register(clkdom, div);
sys/arm/mv/clk/periph.c
77
printf("Failed to register %s: %d\n", div->clkdef.name, error);
sys/arm/mv/clk/periph.h
113
.clk_def.full_d.div.clkdef.name = _div1_name, \
sys/arm/mv/clk/periph.h
114
.clk_def.full_d.div.offset = _div1_reg, \
sys/arm/mv/clk/periph.h
115
.clk_def.full_d.div.i_shift = _div1_shift, \
sys/arm/mv/clk/periph.h
116
.clk_def.full_d.div.i_width = 0x3, \
sys/arm/mv/clk/periph.h
117
.clk_def.full_d.div.f_shift = 0x0, \
sys/arm/mv/clk/periph.h
118
.clk_def.full_d.div.f_width = 0x0, \
sys/arm/mv/clk/periph.h
119
.clk_def.full_d.div.div_flags = 0x0, \
sys/arm/mv/clk/periph.h
120
.clk_def.full_d.div.div_table = _div_table, \
sys/arm/mv/clk/periph.h
146
.clk_def.cpu.div.clkdef.name = _div1_name, \
sys/arm/mv/clk/periph.h
147
.clk_def.cpu.div.offset = _div1_reg, \
sys/arm/mv/clk/periph.h
148
.clk_def.cpu.div.i_shift = _div1_shift, \
sys/arm/mv/clk/periph.h
149
.clk_def.cpu.div.i_width = 0x3, \
sys/arm/mv/clk/periph.h
150
.clk_def.cpu.div.f_shift = 0x0, \
sys/arm/mv/clk/periph.h
151
.clk_def.cpu.div.f_width = 0x0, \
sys/arm/mv/clk/periph.h
152
.clk_def.cpu.div.div_flags = 0x0, \
sys/arm/mv/clk/periph.h
153
.clk_def.cpu.div.div_table = _div_table, \
sys/arm/mv/clk/periph.h
296
struct clk_div_def div;
sys/arm/mv/clk/periph.h
302
struct clk_div_def div;
sys/arm/mv/clk/periph.h
326
struct clk_div_def div;
sys/arm/mv/clk/periph_clk_d.c
131
struct clk_div_def *div;
sys/arm/mv/clk/periph_clk_d.c
136
div = &device_def->clk_def.full_d.div;
sys/arm/mv/clk/periph_clk_d.c
147
a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1);
sys/arm/mv/clk/periph_clk_d.c
148
error = a37x0_periph_create_div(clkdom, div,
sys/arm/mv/clk/periph_clk_d.c
154
parent_names[1] = div->clkdef.name;
sys/arm/mv/clk/periph_clk_d.c
185
struct clk_div_def *div;
sys/arm/mv/clk/periph_clk_d.c
190
div = &device_def->clk_def.cpu.div;
sys/arm/mv/clk/periph_clk_d.c
200
a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1);
sys/arm/mv/clk/periph_clk_d.c
201
error = a37x0_periph_create_div(clkdom, div,
sys/arm/mv/clk/periph_clk_d.c
207
parent_names[1] = div->clkdef.name;
sys/arm/mv/clk/periph_clk_fixed.c
77
fixed_def.div = 2;
sys/arm/mv/clk/periph_clk_mux_gate.c
130
fixed1->div = 2;
sys/arm/mv/clk/periph_clk_mux_gate.c
78
fixed.div = 2;
sys/arm/mv/mv_ap806_clock.c
77
.div = 6,
sys/arm/mv/mv_ap806_clock.c
87
.div = 3,
sys/arm/mv/mv_cp110_clock.c
67
.div = 3,
sys/arm/mv/mv_cp110_clock.c
74
.div = 2,
sys/arm/mv/mv_cp110_clock.c
84
.div = 2,
sys/arm/mv/mv_cp110_clock.c
91
.div = 5,
sys/arm/nvidia/drm2/tegra_dc.c
312
struct drm_display_mode *mode, uint32_t *div)
sys/arm/nvidia/drm2/tegra_dc.c
344
*div = (freq * 2 / pclk) - 2;
sys/arm/nvidia/drm2/tegra_dc.c
346
DRM_DEBUG_KMS("frequency: %llu, DC divider: %u\n", freq, *div);
sys/arm/nvidia/drm2/tegra_dc.c
645
uint32_t div, h_ref_to_sync, v_ref_to_sync;
sys/arm/nvidia/drm2/tegra_dc.c
655
rv = dc_setup_clk(sc, drm_crtc, mode, &div);
sys/arm/nvidia/drm2/tegra_dc.c
686
SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER(PCD1));
sys/arm/nvidia/tegra124/tegra124_car.c
170
.div = _div, \
sys/arm/nvidia/tegra124/tegra124_car.c
379
fixed_osc_div_clk.div = 1 << val;
sys/arm/nvidia/tegra124/tegra124_cpufreq.c
210
#define DIV_ROUND_CLOSEST(val, div) (((val) + ((div) / 2)) / (div))
sys/arm/nvidia/tegra124/tegra124_cpufreq.c
212
#define ROUND_UP(val, div) roundup(val, div)
sys/arm/nvidia/tegra124/tegra124_cpufreq.c
213
#define ROUND_DOWN(val, div) rounddown(val, div)
sys/arm/nvidia/tegra_i2c.c
265
int div;
sys/arm/nvidia/tegra_i2c.c
267
div = ((sc->core_freq / clk_freq) / 10) - 1;
sys/arm/nvidia/tegra_i2c.c
268
if ((sc->core_freq / (10 * (div + 1))) > clk_freq)
sys/arm/nvidia/tegra_i2c.c
269
div++;
sys/arm/nvidia/tegra_i2c.c
270
if (div > 65535)
sys/arm/nvidia/tegra_i2c.c
271
div = 65535;
sys/arm/nvidia/tegra_i2c.c
274
(div << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT));
sys/arm/nvidia/tegra_soctherm.c
462
int mult, div, calib_cp, calib_ft;
sys/arm/nvidia/tegra_soctherm.c
486
div = cfg->tsample * cfg->pdiv_ate;
sys/arm/nvidia/tegra_soctherm.c
489
(int64_t) delta_sens * div);
sys/arm/ti/am335x/am335x_lcd.c
242
uint32_t div, i;
sys/arm/ti/am335x/am335x_lcd.c
246
div = 255;
sys/arm/ti/am335x/am335x_lcd.c
252
div = i;
sys/arm/ti/am335x/am335x_lcd.c
257
return (div);
sys/arm/ti/am335x/am335x_lcd.c
614
int div;
sys/arm/ti/am335x/am335x_lcd.c
685
div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk);
sys/arm/ti/am335x/am335x_lcd.c
686
reg |= (div << CTRL_DIV_SHIFT);
sys/arm/ti/am335x/tda19988.c
434
uint8_t reg, div;
sys/arm/ti/am335x/tda19988.c
478
div = 148500 / mode->dot_clock;
sys/arm/ti/am335x/tda19988.c
479
if (div != 0) {
sys/arm/ti/am335x/tda19988.c
480
div--;
sys/arm/ti/am335x/tda19988.c
481
if (div > 3)
sys/arm/ti/am335x/tda19988.c
482
div = 3;
sys/arm/ti/am335x/tda19988.c
507
tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
sys/arm/ti/ti_spi.c
101
div = 1;
sys/arm/ti/ti_spi.c
104
div <<= 1;
sys/arm/ti/ti_spi.c
106
clk = TI_SPI_GCLK / div;
sys/arm/ti/ti_spi.c
121
uint32_t clkdiv, conf, div, extclk, reg;
sys/arm/ti/ti_spi.c
127
div = 1;
sys/arm/ti/ti_spi.c
128
while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) {
sys/arm/ti/ti_spi.c
130
div <<= 1;
sys/arm/ti/ti_spi.c
78
int clk, conf, ctrl, div, i, j, wl;
sys/arm/ti/ti_spi.c
98
div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK;
sys/arm/ti/ti_spi.c
99
div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4;
sys/arm64/freescale/imx/clk/imx_clk_composite.c
149
dprintf("parent_freq=%ju, div=%u\n", *freq, div);
sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c
117
uint64_t div, divfi, divff, divf_val;
sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c
126
div = (cfg0 & CFG0_OUTPUT_DIV_MASK) >> CFG0_OUTPUT_DIV_SHIFT;
sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c
127
div = (div + 1) * 2;
sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c
136
*freq = *freq * 8 * divf_val / div;
sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c
126
int divr1, divr2, divf1, divf2, div;
sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c
143
div = (cfg2 & CFG2_DIV_MASK) >> CFG2_DIV_SHIFT;
sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c
146
*freq = *freq / ((divr2 + 1) * (div + 1));
sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c
151
*freq /= (divr1 + 1) * (divr2 + 1) * (div + 1);
sys/arm64/freescale/imx/imx_ccm.c
143
clknode_div_register(sc->clkdom, sc->clks[i].clk.div);
sys/arm64/freescale/imx/imx_ccm.h
130
.div = _div, \
sys/arm64/freescale/imx/imx_ccm.h
212
.clk.div = &(struct clk_div_def) { \
sys/arm64/freescale/imx/imx_ccm.h
73
struct clk_div_def *div;
sys/arm64/nvidia/tegra210/tegra210_car.c
171
.div = _div, \
sys/arm64/nvidia/tegra210/tegra210_car.c
370
fixed_osc_div.div = 1 << OSC_CTRL_PLL_REF_DIV_GET(val);
sys/arm64/nvidia/tegra210/tegra210_car.c
376
fixed_clk_m.div = SPARE_REG0_MDIV_GET(val) + 1;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
245
.div = _div, \
sys/arm64/nvidia/tegra210/tegra210_cpufreq.c
167
#define DIV_ROUND_CLOSEST(val, div) (((val) + ((div) / 2)) / (div))
sys/arm64/nvidia/tegra210/tegra210_cpufreq.c
169
#define ROUND_UP(val, div) roundup(val, div)
sys/arm64/nvidia/tegra210/tegra210_cpufreq.c
170
#define ROUND_DOWN(val, div) rounddown(val, div)
sys/arm64/qoriq/clk/ls1046a_clkgen.c
213
def.div = 1;
sys/arm64/qoriq/clk/qoriq_clk_pll.c
137
def.div = clkdef->dividers[i];
sys/arm64/qoriq/clk/qoriq_clkgen.c
206
def.div = 1;
sys/compat/linuxkpi/common/include/linux/ktime.h
55
ktime_divns(const ktime_t kt, int64_t div)
sys/compat/linuxkpi/common/include/linux/ktime.h
57
return (kt / div);
sys/compat/linuxkpi/common/include/linux/math64.h
111
mul_u64_u32_div(uint64_t x, uint32_t y, uint32_t div)
sys/compat/linuxkpi/common/include/linux/math64.h
113
const uint64_t rem = x % div;
sys/compat/linuxkpi/common/include/linux/math64.h
115
return ((x / div) * y + (rem * y) / div);
sys/dev/acpica/acpi_hpet.c
109
uint32_t div;
sys/dev/acpica/acpi_hpet.c
215
t->div = (sc->freq * period) >> 32;
sys/dev/acpica/acpi_hpet.c
218
t->div = 0;
sys/dev/acpica/acpi_hpet.c
223
fdiv = t->div;
sys/dev/acpica/acpi_hpet.c
237
t->div);
sys/dev/acpica/acpi_hpet.c
301
t->next += t->div;
sys/dev/acpica/acpi_hpet.c
303
if ((int32_t)((now + t->div / 2) - t->next) > 0)
sys/dev/acpica/acpi_hpet.c
304
t->next = now + t->div / 2;
sys/dev/acpica/acpi_hpet.c
910
t->next += t->div;
sys/dev/acpica/acpi_hpet.c
917
t->div);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
361
uint32_t div;
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
369
div = 64;
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
371
div = 32;
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
373
div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
374
div = CHIPC_GET_BITS(div, CHIPC_SCC_CD);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
375
div = 4 * (div + 1);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
378
div = 1;
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
380
div = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
381
div = CHIPC_GET_BITS(div, CHIPC_SYCC_CD);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
382
div = 4 * (div + 1);
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
405
return (hz / div);
sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
2221
uint32_t div;
sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
2262
div = (tmp >> ((m - 1) * BHND_PMU5_PLL_MDIV_WIDTH));
sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
2263
div &= BHND_PMU5_PLL_MDIV_MASK;
sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
2278
"clock=%d\n", __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div);
sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
2281
return ((fc / div) * 1000000);
sys/dev/bwi/if_bwi.c
1044
u_int div;
sys/dev/bwi/if_bwi.c
1058
div = 0;
sys/dev/bwi/if_bwi.c
1063
div = 64;
sys/dev/bwi/if_bwi.c
1066
div = 32;
sys/dev/bwi/if_bwi.c
1073
div = 1;
sys/dev/bwi/if_bwi.c
1075
div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
sys/dev/bwi/if_bwi.c
1085
div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
sys/dev/bwi/if_bwi.c
1089
KASSERT(div != 0, ("div zero"));
sys/dev/bwi/if_bwi.c
1095
freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
sys/dev/bwi/if_bwi.c
1096
freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
sys/dev/bwn/if_bwn_phy_lp.c
1626
#define CALC_CTL7(freq, div) \
sys/dev/bwn/if_bwn_phy_lp.c
1627
(((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff)
sys/dev/bwn/if_bwn_phy_lp.c
1628
#define CALC_CTL18(freq, div) \
sys/dev/bwn/if_bwn_phy_lp.c
1629
((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff)
sys/dev/bwn/if_bwn_phy_lp.c
1630
#define CALC_CTL19(freq, div) \
sys/dev/bwn/if_bwn_phy_lp.c
1631
((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff)
sys/dev/bwn/if_bwn_phy_lp.c
1949
bwn_phy_lp_roundup(uint32_t value, uint32_t div, uint8_t pre)
sys/dev/bwn/if_bwn_phy_lp.c
1953
if (div == 0)
sys/dev/bwn/if_bwn_phy_lp.c
1956
for (i = 0, q = value / div, r = value % div; i < pre; i++) {
sys/dev/bwn/if_bwn_phy_lp.c
1958
if (r << 1 >= div) {
sys/dev/bwn/if_bwn_phy_lp.c
1960
r = (r << 1) - div;
sys/dev/bwn/if_bwn_phy_lp.c
1963
if (r << 1 >= div)
sys/dev/bwn/if_bwn_phy_lp.c
821
int error, i, div;
sys/dev/bwn/if_bwn_phy_lp.c
857
div = (freqxtal <= 26000000 ? 1 : 2);
sys/dev/bwn/if_bwn_phy_lp.c
858
timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1;
sys/dev/bwn/if_bwn_phy_lp.c
859
timeoutref = ((((8 * freqxtal) / (div * (timeout + 1))) +
sys/dev/bwn/if_bwn_phy_lp.c
870
val[1] = bwn_phy_lp_roundup(freqxtal, 1000000 * div, 16);
sys/dev/clk/allwinner/aw_ccung.c
290
clknode_div_register(sc->clkdom, sc->clks[i].clk.div);
sys/dev/clk/allwinner/aw_ccung.h
63
struct clk_div_def *div;
sys/dev/clk/allwinner/aw_clk.h
486
.div.shift = _div_shift, \
sys/dev/clk/allwinner/aw_clk.h
487
.div.width = _div_width, \
sys/dev/clk/allwinner/aw_clk.h
488
.div.value = _div_value, \
sys/dev/clk/allwinner/aw_clk.h
489
.div.flags = _div_flags, \
sys/dev/clk/allwinner/aw_clk.h
515
.div.shift = _div_shift, \
sys/dev/clk/allwinner/aw_clk.h
516
.div.width = _div_width, \
sys/dev/clk/allwinner/aw_clk.h
517
.div.value = _div_value, \
sys/dev/clk/allwinner/aw_clk.h
518
.div.flags = _div_flags, \
sys/dev/clk/allwinner/aw_clk.h
598
.div = _div, \
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
110
uint32_t val, div, prediv;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
118
div = aw_clk_get_factor(val, &sc->div);
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
121
*freq = *freq / prediv / div;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
154
sc->div.shift = clkdef->div.shift;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
155
sc->div.mask = ((1 << clkdef->div.width) - 1) << sc->div.shift;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
156
sc->div.value = clkdef->div.value;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
157
sc->div.cond_shift = clkdef->div.cond_shift;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
158
sc->div.cond_mask = ((1 << clkdef->div.cond_width) - 1) << sc->div.shift;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
159
sc->div.cond_value = clkdef->div.cond_value;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
160
sc->div.flags = clkdef->div.flags;
sys/dev/clk/allwinner/aw_clk_prediv_mux.c
52
struct aw_clk_factor div;
sys/dev/clk/allwinner/aw_clk_prediv_mux.h
38
struct aw_clk_factor div;
sys/dev/clk/allwinner/ccu_a13.c
293
.div = {
sys/dev/clk/allwinner/ccu_a13.c
514
{ .type = AW_CLK_DIV, .clk.div = &pll_ddr},
sys/dev/clk/allwinner/ccu_a13.c
515
{ .type = AW_CLK_DIV, .clk.div = &pll_ddr_other},
sys/dev/clk/allwinner/ccu_a13.c
516
{ .type = AW_CLK_DIV, .clk.div = &axi_clk},
sys/dev/clk/allwinner/ccu_a13.c
517
{ .type = AW_CLK_DIV, .clk.div = &apb0_clk},
sys/dev/clk/allwinner/ccu_a31.c
917
{ .type = AW_CLK_DIV, .clk.div = &axi_clk},
sys/dev/clk/allwinner/ccu_a31.c
918
{ .type = AW_CLK_DIV, .clk.div = &apb1_clk},
sys/dev/clk/allwinner/ccu_a64.c
770
{ .type = AW_CLK_DIV, .clk.div = &axi_clk},
sys/dev/clk/allwinner/ccu_a64.c
771
{ .type = AW_CLK_DIV, .clk.div = &apb1_clk},
sys/dev/clk/allwinner/ccu_a64.c
772
{ .type = AW_CLK_DIV, .clk.div = &apb_clk},
sys/dev/clk/allwinner/ccu_a64.c
773
{ .type = AW_CLK_DIV, .clk.div = &ths_clk},
sys/dev/clk/allwinner/ccu_a83t.c
724
{ .type = AW_CLK_DIV, .clk.div = &axi0_clk},
sys/dev/clk/allwinner/ccu_a83t.c
725
{ .type = AW_CLK_DIV, .clk.div = &axi1_clk},
sys/dev/clk/allwinner/ccu_a83t.c
726
{ .type = AW_CLK_DIV, .clk.div = &apb1_clk},
sys/dev/clk/allwinner/ccu_d1.c
1018
{ .type = AW_CLK_DIV, .clk.div = &riscv_axi_clk},
sys/dev/clk/allwinner/ccu_h3.c
717
{ .type = AW_CLK_DIV, .clk.div = &axi_clk},
sys/dev/clk/allwinner/ccu_h3.c
718
{ .type = AW_CLK_DIV, .clk.div = &apb1_clk},
sys/dev/clk/allwinner/ccu_h3.c
719
{ .type = AW_CLK_DIV, .clk.div = &thsdiv_clk},
sys/dev/clk/allwinner/ccu_h6_r.c
113
{ .type = AW_CLK_DIV, .clk.div = &r_apb1_clk},
sys/dev/clk/allwinner/ccu_sun8i_r.c
146
{ .type = AW_CLK_DIV, .clk.div = &apb0_clk},
sys/dev/clk/allwinner/ccu_sun8i_r.c
153
{ .type = AW_CLK_DIV, .clk.div = &apb0_clk},
sys/dev/clk/clk_fixed.c
106
if (sc->mult == 0 || sc->div == 0) {
sys/dev/clk/clk_fixed.c
115
*fout = (*fout / sc->mult) * sc->div;
sys/dev/clk/clk_fixed.c
133
sc->div = clkdef->div;
sys/dev/clk/clk_fixed.c
206
rv = OF_getencprop(node, "clock-div", &def->div, sizeof(def->div));
sys/dev/clk/clk_fixed.c
61
uint32_t div;
sys/dev/clk/clk_fixed.c
92
if ((sc->mult != 0) && (sc->div != 0))
sys/dev/clk/clk_fixed.c
93
*freq = (*freq / sc->div) * sc->mult;
sys/dev/clk/clk_fixed.h
44
uint32_t div;
sys/dev/clk/rockchip/rk3328_cru.c
745
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
749
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
753
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
757
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
761
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
765
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
769
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
773
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
777
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
781
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
785
.div = 1,
sys/dev/clk/rockchip/rk3328_cru.c
789
.div = 1,
sys/dev/clk/rockchip/rk_clk_armclk.c
121
uint32_t reg, div;
sys/dev/clk/rockchip/rk_clk_armclk.c
132
div = ((reg & sc->div_mask) >> sc->div_shift) + 1;
sys/dev/clk/rockchip/rk_clk_armclk.c
133
dprintf("parent_freq=%ju, div=%u\n", *freq, div);
sys/dev/clk/rockchip/rk_clk_armclk.c
135
*freq = *freq / div;
sys/dev/clk/rockchip/rk_clk_armclk.c
148
uint32_t div = 0, val = 0;
sys/dev/clk/rockchip/rk_clk_armclk.c
160
div = sc->rates[i].div;
sys/dev/clk/rockchip/rk_clk_armclk.c
161
best_p = best * div;
sys/dev/clk/rockchip/rk_clk_armclk.c
193
val |= (div - 1) << sc->div_shift;
sys/dev/clk/rockchip/rk_clk_armclk.h
35
uint32_t div;
sys/dev/clk/rockchip/rk_clk_composite.c
170
uint32_t reg, div;
sys/dev/clk/rockchip/rk_clk_composite.c
181
div = ((reg & sc->div_mask) >> sc->div_shift);
sys/dev/clk/rockchip/rk_clk_composite.c
183
div = 1 << div;
sys/dev/clk/rockchip/rk_clk_composite.c
185
div += 1;
sys/dev/clk/rockchip/rk_clk_composite.c
186
dprintf("parent_freq=%ju, div=%u\n", *freq, div);
sys/dev/clk/rockchip/rk_clk_composite.c
187
*freq = *freq / div;
sys/dev/clk/rockchip/rk_clk_composite.c
198
uint32_t div, div_reg;
sys/dev/clk/rockchip/rk_clk_composite.c
207
div = 1 << div_reg;
sys/dev/clk/rockchip/rk_clk_composite.c
209
div = div_reg + 1;
sys/dev/clk/rockchip/rk_clk_composite.c
210
cur = fparent / div;
sys/dev/clk/rockchip/rk_clk_composite.c
213
best_div = div;
sys/dev/clk/rockchip/rk_clk_composite.c
230
uint32_t div, div_reg, best_div, best_div_reg, val;
sys/dev/clk/rockchip/rk_clk_composite.c
242
div = rk_clk_composite_find_best(sc, fparent, *fout, &div_reg);
sys/dev/clk/rockchip/rk_clk_composite.c
243
cur = fparent / div;
sys/dev/clk/rockchip/rk_clk_composite.c
246
best_div = div;
sys/dev/clk/rockchip/rk_cru.h
84
.div = _div, \
sys/dev/clk/xilinx/zynqmp_clk_div.c
100
rv = ZYNQMP_FIRMWARE_CLOCK_SETDIVIDER(sc->firmware, sc->id, div);
sys/dev/clk/xilinx/zynqmp_clk_div.c
61
uint32_t div;
sys/dev/clk/xilinx/zynqmp_clk_div.c
65
rv = ZYNQMP_FIRMWARE_CLOCK_GETDIVIDER(sc->firmware, sc->id, &div);
sys/dev/clk/xilinx/zynqmp_clk_div.c
74
div &= 0xFFFF;
sys/dev/clk/xilinx/zynqmp_clk_div.c
76
div = div >> 16;
sys/dev/clk/xilinx/zynqmp_clk_div.c
77
*freq = howmany((unsigned long long)*freq, div + 1);
sys/dev/clk/xilinx/zynqmp_clk_div.c
86
uint32_t div;
sys/dev/clk/xilinx/zynqmp_clk_div.c
91
div = DIV_ROUND_CLOSEST(fparent, *fout);
sys/dev/clk/xilinx/zynqmp_clk_div.c
93
div &= 0xFFFF;
sys/dev/clk/xilinx/zynqmp_clk_div.c
94
div |= 0xFFFF << 16;
sys/dev/clk/xilinx/zynqmp_clk_div.c
96
div <<= 16;
sys/dev/clk/xilinx/zynqmp_clk_div.c
97
div |= 0xFFFF;
sys/dev/clk/xilinx/zynqmp_clk_fixed.c
58
uint32_t mult, div;
sys/dev/clk/xilinx/zynqmp_clk_fixed.c
62
rv = ZYNQMP_FIRMWARE_CLOCK_GET_FIXEDFACTOR(sc->firmware, sc->id, &mult, &div);
sys/dev/clk/xilinx/zynqmp_clk_fixed.c
70
*freq = (*freq * mult) / div;
sys/dev/clk/xilinx/zynqmp_clk_pll.c
65
uint32_t div, mode, frac;
sys/dev/clk/xilinx/zynqmp_clk_pll.c
69
rv = ZYNQMP_FIRMWARE_CLOCK_GETDIVIDER(sc->firmware, sc->id, &div);
sys/dev/clk/xilinx/zynqmp_clk_pll.c
84
pll_freq = *freq * div;
sys/dev/enic/enic.h
129
u32 div;
sys/dev/enic/vnic_dev.c
910
vdev->intr_coal_timer_info.div = 3;
sys/dev/enic/vnic_dev.c
934
vdev->intr_coal_timer_info.div;
sys/dev/enic/vnic_dev.c
939
return (hw_cycles * vdev->intr_coal_timer_info.div) /
sys/dev/firmware/xilinx/zynqmp_firmware.c
223
zynqmp_firmware_clock_setdivider(device_t dev, uint32_t clkid, uint32_t div)
sys/dev/firmware/xilinx/zynqmp_firmware.c
230
rv = zynqmp_call_smc(PM_CLOCK_SETDIVIDER, clkid, div, 0, 0, payload, false);
sys/dev/firmware/xilinx/zynqmp_firmware.c
237
zynqmp_firmware_clock_getdivider(device_t dev, uint32_t clkid, uint32_t *div)
sys/dev/firmware/xilinx/zynqmp_firmware.c
249
*div = payload[1];
sys/dev/firmware/xilinx/zynqmp_firmware.c
324
zynqmp_firmware_clock_get_fixedfactor(device_t dev, uint32_t clkid, uint32_t *mult, uint32_t *div)
sys/dev/firmware/xilinx/zynqmp_firmware.c
337
*div = payload[2];
sys/dev/iicbus/controller/vybrid/vf_i2c.c
120
uint32_t div;
sys/dev/iicbus/controller/vybrid/vf_i2c.c
431
if ((clk_freq / vf610_div_table[i].div) <= sc->freq)
sys/dev/iwm/if_iwmreg.h
3543
struct iwm_statistics_div div;
sys/dev/iwn/if_iwn.c
6149
int i, ant, div, delta;
sys/dev/iwn/if_iwn.c
6154
div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
sys/dev/iwn/if_iwn.c
6167
(int32_t)calib->noise[i]) / div;
sys/dev/mmc/host/dwmmc.c
810
int div;
sys/dev/mmc/host/dwmmc.c
831
div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0;
sys/dev/mmc/host/dwmmc.c
833
WRITE4(sc, SDMMC_CLKDIV, div);
sys/dev/netmap/if_vtnet_netmap.h
372
int div;
sys/dev/netmap/if_vtnet_netmap.h
385
div = 1;
sys/dev/netmap/if_vtnet_netmap.h
387
div = 2;
sys/dev/netmap/if_vtnet_netmap.h
389
return virtqueue_size(sc->vtnet_txqs[0].vtntx_vq) / div;
sys/dev/netmap/if_vtnet_netmap.h
395
int div;
sys/dev/netmap/if_vtnet_netmap.h
408
div = 1;
sys/dev/netmap/if_vtnet_netmap.h
410
div = 2;
sys/dev/netmap/if_vtnet_netmap.h
412
return virtqueue_size(sc->vtnet_rxqs[0].vtnrx_vq) / div;
sys/dev/pwm/controller/allwinner/aw_pwm.c
245
uint64_t clk_rate, div;
sys/dev/pwm/controller/allwinner/aw_pwm.c
278
div = AW_PWM_MAX_FREQ / period_freq;
sys/dev/pwm/controller/allwinner/aw_pwm.c
279
if ((div - 1) > AW_PWM_PERIOD_TOTAL_MASK) {
sys/dev/pwm/controller/allwinner/aw_pwm.c
284
div = AW_PWM_MAX_FREQ / aw_pwm_clk_prescaler[i] / period_freq;
sys/dev/pwm/controller/allwinner/aw_pwm.c
285
if ((div - 1) < AW_PWM_PERIOD_TOTAL_MASK ) {
sys/dev/qat/qat_api/qat_kernel/src/qat_transport.c
20
Cpa32U div = data >> shift;
sys/dev/qat/qat_api/qat_kernel/src/qat_transport.c
21
Cpa32U mult = div << shift;
sys/dev/qat/qat_common/adf_transport.c
25
u32 div = data >> shift;
sys/dev/qat/qat_common/adf_transport.c
26
u32 mult = div << shift;
sys/dev/qat_c2xxx/qat.c
985
u_int div = data >> shift;
sys/dev/qat_c2xxx/qat.c
986
u_int mult = div << shift;
sys/dev/qcom_clk/qcom_clk_ro_div.c
100
*freq = *freq / div;
sys/dev/qcom_clk/qcom_clk_ro_div.c
69
uint32_t reg, idx, div = 1;
sys/dev/qcom_clk/qcom_clk_ro_div.c
85
for (i = 0; (sc->div_tbl[i].div != 0); i++) {
sys/dev/qcom_clk/qcom_clk_ro_div.c
87
div = sc->div_tbl[i].div;
sys/dev/qcom_clk/qcom_clk_ro_div.c
97
div,
sys/dev/qcom_clk/qcom_clk_ro_div.c
98
*freq / div);
sys/dev/qcom_clk/qcom_clk_ro_div.h
33
uint32_t div;
sys/dev/rtsx/rtsx.c
1841
uint8_t clk_divider, n, div, mcu;
sys/dev/rtsx/rtsx.c
1888
div = RTSX_CLK_DIV_1;
sys/dev/rtsx/rtsx.c
1889
while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) {
sys/dev/rtsx/rtsx.c
1900
div++;
sys/dev/rtsx/rtsx.c
1906
if (div > RTSX_CLK_DIV_1) {
sys/dev/rtsx/rtsx.c
1907
if (sc->rtsx_ssc_depth > (div - 1))
sys/dev/rtsx/rtsx.c
1908
sc->rtsx_ssc_depth -= (div - 1);
sys/dev/rtsx/rtsx.c
1914
error = rtsx_switch_sd_clock(sc, clk, n, div, mcu);
sys/dev/rtsx/rtsx.c
1929
rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu)
sys/dev/rtsx/rtsx.c
1935
clk, n, div, mcu);
sys/dev/rtsx/rtsx.c
1939
RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);
sys/dev/rtsx/rtsx.c
224
static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu);
sys/dev/sdhci/sdhci.c
1930
uint8_t div;
sys/dev/sdhci/sdhci.c
1942
div = 0xE;
sys/dev/sdhci/sdhci.c
1945
div = 0;
sys/dev/sdhci/sdhci.c
1947
while (current_timeout < target_timeout && div < 0xE) {
sys/dev/sdhci/sdhci.c
1948
++div;
sys/dev/sdhci/sdhci.c
1952
if (div < 0xE &&
sys/dev/sdhci/sdhci.c
1954
++div;
sys/dev/sdhci/sdhci.c
1957
WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
sys/dev/sdhci/sdhci.c
414
uint16_t div;
sys/dev/sdhci/sdhci.c
457
for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
sys/dev/sdhci/sdhci.c
463
div >>= 1;
sys/dev/sdhci/sdhci.c
467
div = 0;
sys/dev/sdhci/sdhci.c
469
for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
sys/dev/sdhci/sdhci.c
470
if ((clk_base / div) <= clock)
sys/dev/sdhci/sdhci.c
474
div >>= 1;
sys/dev/sdhci/sdhci.c
479
div, clock, clk_base);
sys/dev/sdhci/sdhci.c
482
clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
sys/dev/sdhci/sdhci.c
483
clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
sys/dev/sdhci/sdhci_fsl_fdt.c
1070
uint32_t prescale, div;
sys/dev/sdhci/sdhci_fsl_fdt.c
1081
SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div);
sys/dev/sdhci/sdhci_fsl_fdt.c
1082
slot->host.ios.clock = sc->baseclk_hz / (prescale * div);
sys/dev/sdhci/sdhci_fsl_fdt.c
304
#define SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div) \
sys/dev/sdhci/sdhci_fsl_fdt.c
310
(div) = ((pre) == 1 ? 2 : 1); \
sys/dev/sdhci/sdhci_fsl_fdt.c
311
while ((freq) < (base) / ((pre) * (div)) && (div) < 16) \
sys/dev/sdhci/sdhci_fsl_fdt.c
312
++(div); \
sys/dev/sdhci/sdhci_fsl_fdt.c
319
uint32_t prescale, div, val32, div_ratio;
sys/dev/sdhci/sdhci_fsl_fdt.c
333
SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div);
sys/dev/sdhci/sdhci_fsl_fdt.c
335
div_ratio = prescale * div;
sys/dev/sdhci/sdhci_fsl_fdt.c
346
div = 1;
sys/dev/sdhci/sdhci_fsl_fdt.c
349
div = 2;
sys/dev/sdhci/sdhci_fsl_fdt.c
352
div = 3;
sys/dev/sdhci/sdhci_fsl_fdt.c
358
sc->div_ratio = prescale * div;
sys/dev/sdhci/sdhci_fsl_fdt.c
362
slot->clock, sc->baseclk_hz / (prescale * div),
sys/dev/sdhci/sdhci_fsl_fdt.c
363
sc->baseclk_hz, prescale, div);
sys/dev/sdhci/sdhci_fsl_fdt.c
366
div -= 1;
sys/dev/sdhci/sdhci_fsl_fdt.c
369
val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT;
sys/dev/sound/pci/hda/hdaa.c
124
uint16_t div;
sys/dev/sound/pci/hda/hdaa.c
1846
fmt |= hda_rate_tab[i].div;
sys/dev/spibus/controller/rockchip/rk_spi.c
165
uint32_t div;
sys/dev/spibus/controller/rockchip/rk_spi.c
182
div = ((sc->max_freq + freq - 1) / freq);
sys/dev/spibus/controller/rockchip/rk_spi.c
183
div = (div + 1) & 0xfffe;
sys/dev/spibus/controller/rockchip/rk_spi.c
184
RK_SPI_WRITE_4(sc, RK_SPI_BAUDR, div);
sys/dev/sym/sym_hipd.c
2185
u_char div, u_char fak);
sys/dev/sym/sym_hipd.c
2188
u_char per, u_char wide, u_char div, u_char fak);
sys/dev/sym/sym_hipd.c
2190
u_char per, u_char wide, u_char div, u_char fak);
sys/dev/sym/sym_hipd.c
3320
int div = np->clock_divn; /* Number of divisors supported */
sys/dev/sym/sym_hipd.c
3353
while (div > 0) {
sys/dev/sym/sym_hipd.c
3354
--div;
sys/dev/sym/sym_hipd.c
3355
if (kpc > (div_10M[div] << 2)) {
sys/dev/sym/sym_hipd.c
3356
++div;
sys/dev/sym/sym_hipd.c
3361
if (div == np->clock_divn) { /* Are we too fast ? */
sys/dev/sym/sym_hipd.c
3364
*divp = div;
sys/dev/sym/sym_hipd.c
3374
while (div-- > 0)
sys/dev/sym/sym_hipd.c
3375
if (kpc >= (div_10M[div] << 2)) break;
sys/dev/sym/sym_hipd.c
3384
fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
sys/dev/sym/sym_hipd.c
3388
fak = (kpc - 1) / div_10M[div] + 1 - 4;
sys/dev/sym/sym_hipd.c
3400
*divp = div;
sys/dev/sym/sym_hipd.c
3488
sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak)
sys/dev/sym/sym_hipd.c
3493
sym_settrans(np, cp, 0, ofs, per, wide, div, fak);
sys/dev/sym/sym_hipd.c
3510
u_char per, u_char wide, u_char div, u_char fak)
sys/dev/sym/sym_hipd.c
3514
sym_settrans(np, cp, dt, ofs, per, wide, div, fak);
sys/dev/sym/sym_hipd.c
3531
u_char per, u_char wide, u_char div, u_char fak)
sys/dev/sym/sym_hipd.c
3567
wval = (wval & ~0x70) | ((div+1) << 4);
sys/dev/sym/sym_hipd.c
5587
u_char chg, ofs, per, fak, div;
sys/dev/sym/sym_hipd.c
5635
div = fak = 0;
sys/dev/sym/sym_hipd.c
5636
if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0)
sys/dev/sym/sym_hipd.c
5642
ofs, per, div, fak, chg);
sys/dev/sym/sym_hipd.c
5651
sym_setsync (np, cp, ofs, per, div, fak);
sys/dev/sym/sym_hipd.c
5660
sym_setsync (np, cp, ofs, per, div, fak);
sys/dev/sym/sym_hipd.c
5688
u_char chg, ofs, per, fak, dt, div, wide;
sys/dev/sym/sym_hipd.c
5760
div = fak = 0;
sys/dev/sym/sym_hipd.c
5761
if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0)
sys/dev/sym/sym_hipd.c
5768
dt, ofs, per, wide, div, fak, chg);
sys/dev/sym/sym_hipd.c
5777
sym_setpprot (np, cp, dt, ofs, per, wide, div, fak);
sys/dev/sym/sym_hipd.c
5786
sym_setpprot (np, cp, dt, ofs, per, wide, div, fak);
sys/dev/uart/uart_dev_ns8250.c
421
uint32_t div;
sys/dev/uart/uart_dev_ns8250.c
423
div = ns8250_get_divisor(bas);
sys/dev/uart/uart_dev_ns8250.c
424
bas->rclk = baudrate * div * 16;
sys/dev/uart/uart_dev_pl011.c
266
uint32_t div;
sys/dev/uart/uart_dev_pl011.c
268
div = ((__uart_getreg(bas, UART_IBRD) & IBRD_BDIVINT) << 6) |
sys/dev/uart/uart_dev_pl011.c
270
bas->rclk = (div * baudrate) / 4;
sys/dev/usb/serial/uchcom.c
642
uint8_t factor, div;
sys/dev/usb/serial/uchcom.c
644
uchcom_calc_baudrate(sc, rate, &div, &factor);
sys/dev/usb/serial/uchcom.c
645
div |= (sc->sc_chiptype != TYPE_CH343) ? 0x80 : 0x00;
sys/dev/usb/serial/uchcom.c
646
idx = (factor << 8) | div;
sys/i386/i386/machdep.c
1308
setidt(IDT_DE, &IDTVEC(div), SDT_SYS386IGT, SEL_KPL,
sys/i386/i386/machdep.c
624
IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
sys/kern/kern_clock.c
555
#define TIME_INT_SCALE(value, mul, div) \
sys/kern/kern_clock.c
556
(((value) / (div)) * (mul) + (((value) % (div)) * (mul)) / (div))
sys/kern/kern_clocksource.c
567
uint64_t div;
sys/kern/kern_clocksource.c
570
div = lmax((et->et_frequency + freq / 2) / freq, 1);
sys/kern/kern_clocksource.c
572
div = 1 << (flsl(div + div / 2) - 1);
sys/kern/kern_clocksource.c
573
freq = (et->et_frequency + div / 2) / div;
sys/kern/kern_clocksource.c
592
int base, div, cpu;
sys/kern/kern_clocksource.c
649
div = base / 128;
sys/kern/kern_clocksource.c
650
if (div >= singlemul && (div % singlemul) == 0)
sys/kern/kern_clocksource.c
651
div++;
sys/kern/kern_clocksource.c
652
stathz = base / div;
sys/kern/sched_ule.c
1693
int div;
sys/kern/sched_ule.c
1706
div = max(1, ts->ts_runtime / SCHED_INTERACT_HALF);
sys/kern/sched_ule.c
1708
(SCHED_INTERACT_HALF - (ts->ts_slptime / div)));
sys/kern/sched_ule.c
1711
div = max(1, ts->ts_slptime / SCHED_INTERACT_HALF);
sys/kern/sched_ule.c
1712
return (ts->ts_runtime / div);
sys/netinet/sctp_cc_functions.c
573
uint64_t div, inst_off;
sys/netinet/sctp_cc_functions.c
625
div = net->rtt / 1000;
sys/netinet/sctp_cc_functions.c
626
if (div) {
sys/netinet/sctp_cc_functions.c
627
inst_bw = bytes_for_this_rtt / div;
sys/netpfil/pf/pf_lb.c
1248
uint16_t div;
sys/netpfil/pf/pf_lb.c
1250
div = r->rdr.proxy_port[1] - r->rdr.proxy_port[0] + 1;
sys/netpfil/pf/pf_lb.c
1251
div = (div == 0) ? 1 : div;
sys/netpfil/pf/pf_lb.c
1253
tmp_nport = ((ntohs(pd->ndport) - ntohs(r->dst.port[0])) % div) +
sys/powerpc/powerpc/clock.c
100
int32_t div; /* Periodic divisor. */
sys/powerpc/powerpc/clock.c
146
val += s->div;
sys/powerpc/powerpc/clock.c
267
s->div = (decr_et.et_frequency * period) >> 32;
sys/powerpc/powerpc/clock.c
270
s->div = 0;
sys/powerpc/powerpc/clock.c
275
fdiv = s->div;
sys/powerpc/powerpc/clock.c
281
mtspr(SPR_DECAR, s->div);
sys/powerpc/powerpc/clock.c
306
s->div = 0x7fffffff;
sys/powerpc/powerpc/clock.c
312
mtdec(s->div);
sys/riscv/include/encoding.h
815
DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
sys/riscv/sifive/sifive_prci.c
191
.div = 2,
sys/riscv/sifive/sifive_prci.c
253
.div = 2,
sys/riscv/sifive/sifive_prci.c
345
uint32_t div;
sys/riscv/sifive/sifive_prci.c
366
div = PRCI_READ(sc->parent_sc, sc->reg);
sys/riscv/sifive/sifive_prci.c
368
*freq = refclk / (div + sc->bias);
sys/x86/cpufreq/hwpstate_amd.c
539
hwpstate_amd_iscale(int val, int div)
sys/x86/cpufreq/hwpstate_amd.c
541
switch (div) {
usr.bin/sdiff/sdiff.c
1009
if (!sflag || diffp->div == '|' || diffp->div == '<' ||
usr.bin/sdiff/sdiff.c
1010
diffp->div == '>')
usr.bin/sdiff/sdiff.c
1011
println(diffp->left, diffp->div, diffp->right);
usr.bin/sdiff/sdiff.c
45
char div;
usr.bin/sdiff/sdiff.c
899
diffp->div = divider;
usr.bin/sdiff/sdiff.c
996
divc = STAILQ_FIRST(&diffhead)->div;
usr.bin/systat/vmstat.c
631
do_putuint64(uint64_t n, int l, int lc, int w, int div)
usr.bin/systat/vmstat.c
651
HN_NOSPACE | HN_DECIMAL | div);
usr.sbin/bhyve/hda_codec.c
618
uint8_t div = 0;
usr.sbin/bhyve/hda_codec.c
637
div = (fmt >> HDA_CODEC_FMT_DIV_SHIFT) & HDA_CODEC_FMT_DIV_MASK;
usr.sbin/bhyve/hda_codec.c
638
params->rate /= (div + 1);
usr.sbin/bhyve/snapshot.c
550
static size_t div;
usr.sbin/bhyve/snapshot.c
565
div = GB;
usr.sbin/bhyve/snapshot.c
568
div = MB;
usr.sbin/bhyve/snapshot.c
571
div = KB;
usr.sbin/bhyve/snapshot.c
575
crtval_gb = (double) crtval / div;
usr.sbin/bhyve/snapshot.c
576
maxval_gb = (double) maxval / div;
usr.sbin/virtual_oss/virtual_oss/main.c
1112
vclient_scale(uint64_t value, uint64_t mul, uint64_t div)
usr.sbin/virtual_oss/virtual_oss/main.c
1114
uint64_t gcd = vclient_gcd_64(mul, div);
usr.sbin/virtual_oss/virtual_oss/main.c
1117
div /= gcd;
usr.sbin/virtual_oss/virtual_oss/main.c
1119
return ((value * mul) / div);