crypto/heimdal/lib/roken/rkpty.c

253

char ctrl;

crypto/heimdal/lib/roken/rkpty.c

256

case 'n': ctrl = '\n'; break;

crypto/heimdal/lib/roken/rkpty.c

257

case 'r': ctrl = '\r'; break;

crypto/heimdal/lib/roken/rkpty.c

258

case 't': ctrl = '\t'; break;

crypto/heimdal/lib/roken/rkpty.c

263

if (net_write(master, &ctrl, 1) != 1)

crypto/openssl/apps/lib/app_x509.c

121

rv = ctrl(object, cmd, vtmp, vtmp_len);

crypto/openssl/apps/lib/app_x509.c

83

static int do_x509_ctrl_string(int (*ctrl)(void *object, int cmd,

crypto/openssl/crypto/bio/bio_lib.c

662

if (b->method == NULL || b->method->ctrl == NULL) {

crypto/openssl/crypto/bio/bio_lib.c

673

ret = b->method->ctrl(b, cmd, larg, parg);

crypto/openssl/crypto/bio/bio_meth.c

186

return biom->ctrl;

crypto/openssl/crypto/bio/bio_meth.c

191

long (*ctrl)(BIO *, int, long, void *))

crypto/openssl/crypto/bio/bio_meth.c

193

biom->ctrl = ctrl;

crypto/openssl/crypto/crmf/crmf_lib.c

107

if (!sk_OSSL_CRMF_ATTRIBUTETYPEANDVALUE_push(crm->certReq->controls, ctrl))

crypto/openssl/crypto/crmf/crmf_lib.c

92

OSSL_CRMF_ATTRIBUTETYPEANDVALUE *ctrl)

crypto/openssl/crypto/crmf/crmf_lib.c

96

if (crm == NULL || crm->certReq == NULL || ctrl == NULL) {

crypto/openssl/crypto/engine/eng_ctrl.c

134

ctrl_exists = ((e->ctrl == NULL) ? 0 : 1);

crypto/openssl/crypto/engine/eng_ctrl.c

170

return e->ctrl(e, cmd, i, p, f);

crypto/openssl/crypto/engine/eng_ctrl.c

194

if (e->ctrl == NULL

crypto/openssl/crypto/engine/eng_ctrl.c

233

if (e->ctrl == NULL

crypto/openssl/crypto/engine/eng_lib.c

243

e->ctrl = ctrl_f;

crypto/openssl/crypto/engine/eng_lib.c

286

return e->ctrl;

crypto/openssl/crypto/engine/eng_lib.c

69

e->ctrl = NULL;

crypto/openssl/crypto/engine/eng_list.c

399

dest->ctrl = src->ctrl;

crypto/openssl/crypto/engine/eng_local.h

130

ENGINE_CTRL_FUNC_PTR ctrl;

crypto/openssl/crypto/evp/cmeth_lib.c

153

int (*ctrl)(EVP_CIPHER_CTX *, int type,

crypto/openssl/crypto/evp/cmeth_lib.c

156

if (cipher->ctrl != NULL)

crypto/openssl/crypto/evp/cmeth_lib.c

159

cipher->ctrl = ctrl;

crypto/openssl/crypto/evp/cmeth_lib.c

199

return cipher->ctrl;

crypto/openssl/crypto/evp/evp_enc.c

1629

if (ctx->cipher->ctrl == NULL) {

crypto/openssl/crypto/evp/evp_enc.c

1634

ret = ctx->cipher->ctrl(ctx, type, arg, ptr);

crypto/openssl/crypto/evp/evp_enc.c

1837

if (!in->cipher->ctrl((EVP_CIPHER_CTX *)in, EVP_CTRL_COPY, 0, out)) {

crypto/openssl/crypto/evp/evp_lib.c

944

int EVP_MD_meth_set_ctrl(EVP_MD *md, int (*ctrl)(EVP_MD_CTX *ctx, int cmd, int p1, void *p2))

crypto/openssl/crypto/evp/evp_lib.c

949

md->md_ctrl = ctrl;

crypto/openssl/crypto/evp/exchange.c

453

|| ctx->pmeth->ctrl == NULL) {

crypto/openssl/crypto/evp/exchange.c

464

ret = ctx->pmeth->ctrl(ctx, EVP_PKEY_CTRL_PEER_KEY, 0, peer);

crypto/openssl/crypto/evp/exchange.c

494

ret = ctx->pmeth->ctrl(ctx, EVP_PKEY_CTRL_PEER_KEY, 1, peer);

crypto/openssl/crypto/evp/legacy_meth.h

38

#define LEGACY_EVP_MD_METH_TABLE(init, update, final, ctrl, blksz) \

crypto/openssl/crypto/evp/legacy_meth.h

39

init, update, final, NULL, NULL, blksz, 0, ctrl

crypto/openssl/crypto/evp/pmeth_lib.c

1004

return EVP_PKEY_CTX_ctrl(ctx, -1, op, ctrl, datalen, (void *)(data));

crypto/openssl/crypto/evp/pmeth_lib.c

1025

const char *param, int op, int ctrl,

crypto/openssl/crypto/evp/pmeth_lib.c

1044

return EVP_PKEY_CTX_ctrl(ctx, -1, op, ctrl, datalen, (void *)(data));

crypto/openssl/crypto/evp/pmeth_lib.c

1057

return evp_pkey_ctx_set1_octet_string(ctx, fallback, param, op, ctrl,

crypto/openssl/crypto/evp/pmeth_lib.c

1201

int op, int ctrl, uint64_t val)

crypto/openssl/crypto/evp/pmeth_lib.c

1213

return EVP_PKEY_CTX_ctrl_uint64(ctx, -1, op, ctrl, val);

crypto/openssl/crypto/evp/pmeth_lib.c

1324

if (ctx->pmeth == NULL || ctx->pmeth->ctrl == NULL) {

crypto/openssl/crypto/evp/pmeth_lib.c

1331

ret = ctx->pmeth->ctrl(ctx, cmd, p1, p2);

crypto/openssl/crypto/evp/pmeth_lib.c

1595

return ctx->pmeth->ctrl(ctx, cmd, len, (void *)str);

crypto/openssl/crypto/evp/pmeth_lib.c

1608

rv = ctx->pmeth->ctrl(ctx, cmd, binlen, bin);

crypto/openssl/crypto/evp/pmeth_lib.c

1800

int (*ctrl)(EVP_PKEY_CTX *ctx, int type, int p1,

crypto/openssl/crypto/evp/pmeth_lib.c

1806

pmeth->ctrl = ctrl;

crypto/openssl/crypto/evp/pmeth_lib.c

2011

*pctrl = pmeth->ctrl;

crypto/openssl/crypto/evp/pmeth_lib.c

944

int ctrl)

crypto/openssl/crypto/evp/pmeth_lib.c

956

return EVP_PKEY_CTX_ctrl(ctx, -1, op, ctrl, 0, (void *)(md));

crypto/openssl/crypto/evp/pmeth_lib.c

990

const char *param, int op, int ctrl,

crypto/openssl/crypto/store/store_lib.c

281

} else if (ctx->loader->ctrl != NULL) {

crypto/openssl/crypto/store/store_lib.c

282

return ctx->loader->ctrl(ctx->loader_ctx, cmd, args);

crypto/openssl/crypto/store/store_local.h

89

OSSL_STORE_ctrl_fn ctrl;

crypto/openssl/crypto/store/store_register.c

88

loader->ctrl = ctrl_function;

crypto/openssl/crypto/x509/x509_local.h

80

int (*ctrl)(X509_LOOKUP *ctx, int cmd, const char *argc, long argl,

crypto/openssl/crypto/x509/x509_lu.c

84

if (ctx->method->ctrl != NULL)

crypto/openssl/crypto/x509/x509_lu.c

85

return ctx->method->ctrl(ctx, cmd, argc, argl, ret);

crypto/openssl/crypto/x509/x509_meth.c

104

return method->ctrl;

crypto/openssl/crypto/x509/x509_meth.c

96

X509_LOOKUP_ctrl_fn ctrl)

crypto/openssl/crypto/x509/x509_meth.c

98

method->ctrl = ctrl;

crypto/openssl/include/crypto/evp.h

180

int (*ctrl)(EVP_PKEY_CTX *ctx, int type, int p1, void *p2);

crypto/openssl/include/crypto/evp.h

328

int (*ctrl)(EVP_CIPHER_CTX *, int type, int arg, void *ptr);

crypto/openssl/include/crypto/evp.h

450

set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

460

ctrl, \

crypto/openssl/include/crypto/evp.h

467

get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

469

iv_len, flags, init_key, cleanup, set_asn1, get_asn1, ctrl)

crypto/openssl/include/crypto/evp.h

473

set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

476

get_asn1, ctrl)

crypto/openssl/include/crypto/evp.h

480

set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

483

get_asn1, ctrl)

crypto/openssl/include/crypto/evp.h

487

get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

489

0, flags, init_key, cleanup, set_asn1, get_asn1, ctrl)

crypto/openssl/include/crypto/evp.h

493

init_key, cleanup, set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

495

init_key, cleanup, set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

497

flags, init_key, cleanup, set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

499

flags, init_key, cleanup, set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

501

init_key, cleanup, set_asn1, get_asn1, ctrl)

crypto/openssl/include/crypto/evp.h

568

cleanup, set_asn1, get_asn1, ctrl) \

crypto/openssl/include/crypto/evp.h

572

get_asn1, ctrl)

crypto/openssl/include/internal/bio.h

26

long (*ctrl)(BIO *, int, long, void *);

crypto/openssl/include/openssl/bio.h

996

long (*ctrl)(BIO *, int, long, void *));

crypto/openssl/include/openssl/evp.h

153

int EVP_MD_meth_set_ctrl(EVP_MD *md, int (*ctrl)(EVP_MD_CTX *ctx, int cmd, int p1, void *p2));

crypto/openssl/include/openssl/evp.h

2139

OSSL_DEPRECATEDIN_3_0 void EVP_PKEY_meth_set_ctrl(EVP_PKEY_METHOD *pmeth, int (*ctrl)(EVP_PKEY_CTX *ctx, int type, int p1, void *p2),

crypto/openssl/include/openssl/evp.h

287

int (*ctrl)(EVP_CIPHER_CTX *, int type,

lib/libc/tests/secure/fortify_poll_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_poll_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_poll_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_random_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_random_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_random_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_select_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_select_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_select_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_signal_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_signal_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_signal_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_socket_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_socket_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_socket_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_stdio_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_stdio_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_stdio_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_stdlib_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_stdlib_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_stdlib_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_string_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_string_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_string_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_strings_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_strings_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_strings_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_uio_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_uio_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_uio_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_unistd_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_unistd_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_unistd_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libc/tests/secure/fortify_wchar_test.c

101

hdr.msg_control = ctrl;

lib/libc/tests/secure/fortify_wchar_test.c

102

hdr.msg_controllen = sizeof(ctrl);

lib/libc/tests/secure/fortify_wchar_test.c

79

unsigned char ctrl[CMSG_SPACE(sizeof(int))] = { 0 };

lib/libsysdecode/flags.c

425

unsigned int ctrl, data;

lib/libsysdecode/flags.c

427

ctrl = fflags & NOTE_FFCTRLMASK;

lib/libsysdecode/flags.c

444

if (ctrl != NOTE_FFNOP || fflags & NOTE_TRIGGER) {

lib/libsysdecode/flags.c

446

lookup_value(kevent_user_ffctrl, ctrl), data);

sbin/camcontrol/camcontrol.c

2597

(pwd->ctrl & ATA_SECURITY_PASSWORD_MASTER) ?

sbin/camcontrol/camcontrol.c

2602

(pwd->ctrl & ATA_SECURITY_LEVEL_MAXIMUM) ?

sbin/camcontrol/camcontrol.c

3265

pwd.ctrl |= ATA_SECURITY_PASSWORD_MASTER;

sbin/camcontrol/camcontrol.c

3277

pwd.ctrl |= ATA_SECURITY_PASSWORD_USER;

sbin/camcontrol/camcontrol.c

3278

pwd.ctrl &= ~ATA_SECURITY_PASSWORD_MASTER;

sbin/camcontrol/camcontrol.c

3280

pwd.ctrl |= ATA_SECURITY_PASSWORD_MASTER;

sbin/camcontrol/camcontrol.c

3281

pwd.ctrl &= ~ATA_SECURITY_PASSWORD_USER;

sbin/camcontrol/camcontrol.c

3291

pwd.ctrl |= ATA_SECURITY_LEVEL_HIGH;

sbin/camcontrol/camcontrol.c

3292

pwd.ctrl &= ~ATA_SECURITY_LEVEL_MAXIMUM;

sbin/camcontrol/camcontrol.c

3294

pwd.ctrl |= ATA_SECURITY_LEVEL_MAXIMUM;

sbin/camcontrol/camcontrol.c

3295

pwd.ctrl &= ~ATA_SECURITY_LEVEL_HIGH;

sbin/camcontrol/camcontrol.c

3327

pwd.ctrl |= ATA_SECURITY_ERASE_ENHANCED;

sbin/camcontrol/camcontrol.c

3411

if (pwd.ctrl & ATA_SECURITY_PASSWORD_MASTER) {

sbin/hastd/lzf.c

324

unsigned int ctrl = *ip++;

sbin/hastd/lzf.c

326

if (ctrl < (1 << 5)) /* literal run */

sbin/hastd/lzf.c

328

ctrl++;

sbin/hastd/lzf.c

330

if (op + ctrl > out_end)

sbin/hastd/lzf.c

337

if (ip + ctrl > in_end)

sbin/hastd/lzf.c

345

lzf_movsb (op, ip, ctrl);

sbin/hastd/lzf.c

349

while (--ctrl);

sbin/hastd/lzf.c

354

unsigned int len = ctrl >> 5;

sbin/hastd/lzf.c

356

u8 *ref = op - ((ctrl & 0x1f) << 8) - 1;

sbin/hastd/proto_common.c

164

unsigned char ctrl[CMSG_SPACE(sizeof(*fdp))];

sbin/hastd/proto_common.c

172

bzero(&ctrl, sizeof(ctrl));

sbin/hastd/proto_common.c

176

msg.msg_control = ctrl;

sbin/hastd/proto_common.c

177

msg.msg_controllen = sizeof(ctrl);

sbin/hastd/proto_common.c

64

unsigned char ctrl[CMSG_SPACE(sizeof(fd))];

sbin/hastd/proto_common.c

72

bzero(&ctrl, sizeof(ctrl));

sbin/hastd/proto_common.c

76

msg.msg_control = ctrl;

sbin/hastd/proto_common.c

77

msg.msg_controllen = sizeof(ctrl);

sbin/ping/ping.c

219

char ctrl[CMSG_SPACE(sizeof(struct timespec))];

sbin/ping/ping.c

865

msg.msg_control = (caddr_t)ctrl;

sbin/ping/ping.c

866

msg.msg_controllen = sizeof(ctrl);

sys/amd64/vmm/amd/amdvi_hw.c

1307

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

1315

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

1316

KASSERT(ctrl, ("ctrl is NULL\n"));

sys/amd64/vmm/amd/amdvi_hw.c

1335

ctrl->control = val;

sys/amd64/vmm/amd/amdvi_hw.c

1342

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

1349

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

1350

KASSERT(ctrl, ("ctrl is NULL\n"));

sys/amd64/vmm/amd/amdvi_hw.c

1352

ctrl->control = 0;

sys/amd64/vmm/amd/amdvi_hw.c

235

struct amdvi_ctrl *ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

237

ctrl->cmd.len = 8; /* Use 256 command buffer entries. */

sys/amd64/vmm/amd/amdvi_hw.c

238

softc->cmd_max = 1 << ctrl->cmd.len;

sys/amd64/vmm/amd/amdvi_hw.c

246

ctrl->cmd.base = vtophys(softc->cmd) / PAGE_SIZE;

sys/amd64/vmm/amd/amdvi_hw.c

251

ctrl->cmd_tail = 0;

sys/amd64/vmm/amd/amdvi_hw.c

252

ctrl->cmd_head = 0;

sys/amd64/vmm/amd/amdvi_hw.c

266

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

272

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

273

KASSERT(ctrl != NULL, ("ctrl is NULL"));

sys/amd64/vmm/amd/amdvi_hw.c

276

ctrl->cmd_tail);

sys/amd64/vmm/amd/amdvi_hw.c

288

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

294

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

295

KASSERT(ctrl != NULL, ("ctrl is NULL"));

sys/amd64/vmm/amd/amdvi_hw.c

297

ctrl->cmd_tail = MOD_INC(ctrl->cmd_tail, size, softc->cmd_max);

sys/amd64/vmm/amd/amdvi_hw.c

302

ctrl->cmd_tail,

sys/amd64/vmm/amd/amdvi_hw.c

303

ctrl->cmd_head);

sys/amd64/vmm/amd/amdvi_hw.c

437

struct amdvi_ctrl *ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

456

"Head:0x%x, loop:%d.\n", ctrl->cmd_tail,

sys/amd64/vmm/amd/amdvi_hw.c

457

ctrl->cmd_head, loop);

sys/amd64/vmm/amd/amdvi_hw.c

465

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

470

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

471

KASSERT(ctrl != NULL, ("ctrl is NULL"));

sys/amd64/vmm/amd/amdvi_hw.c

473

if ((ctrl->control & AMDVI_CTRL_EN) == 0)

sys/amd64/vmm/amd/amdvi_hw.c

483

ctrl->cmd_tail, ctrl->cmd_head);

sys/amd64/vmm/amd/amdvi_hw.c

491

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

495

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

501

off = MOD_DEC(ctrl->cmd_head, sizeof(struct amdvi_cmd),

sys/amd64/vmm/amd/amdvi_hw.c

503

for (i = 0; off != ctrl->cmd_tail && i < count; i++) {

sys/amd64/vmm/amd/amdvi_hw.c

515

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

517

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

518

ctrl->event.len = 8;

sys/amd64/vmm/amd/amdvi_hw.c

519

softc->event_max = 1 << ctrl->event.len;

sys/amd64/vmm/amd/amdvi_hw.c

526

ctrl->event.base = vtophys(softc->event) / PAGE_SIZE;

sys/amd64/vmm/amd/amdvi_hw.c

529

ctrl->evt_head = 0;

sys/amd64/vmm/amd/amdvi_hw.c

530

ctrl->evt_tail = 0;

sys/amd64/vmm/amd/amdvi_hw.c

681

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

685

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

688

event = &softc->event[ctrl->evt_head / size];

sys/amd64/vmm/amd/amdvi_hw.c

692

i, ctrl->evt_head, ctrl->evt_tail);

sys/amd64/vmm/amd/amdvi_hw.c

694

ctrl->evt_head = MOD_INC(ctrl->evt_head, size,

sys/amd64/vmm/amd/amdvi_hw.c

702

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

704

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

705

ctrl->dte.base = vtophys(amdvi_dte) / PAGE_SIZE;

sys/amd64/vmm/amd/amdvi_hw.c

706

ctrl->dte.size = 0x1FF; /* 2MB device table. */

sys/amd64/vmm/amd/amdvi_hw.c

746

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

749

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

752

ctrl->status, ctrl->evt_head, ctrl->evt_tail);

sys/amd64/vmm/amd/amdvi_hw.c

754

softc->total_cmd, ctrl->cmd_tail, ctrl->cmd_head);

sys/amd64/vmm/amd/amdvi_hw.c

757

ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR;

sys/amd64/vmm/amd/amdvi_hw.c

776

struct amdvi_ctrl *ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

784

ctrl = softc->ctrl;

sys/amd64/vmm/amd/amdvi_hw.c

785

ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR;

sys/amd64/vmm/amd/amdvi_hw.c

823

result = softc->ctrl->cmd_head;

sys/amd64/vmm/amd/amdvi_hw.c

828

result = softc->ctrl->cmd_tail;

sys/amd64/vmm/amd/amdvi_hw.c

833

result = softc->ctrl->evt_head;

sys/amd64/vmm/amd/amdvi_hw.c

838

result = softc->ctrl->evt_tail;

sys/amd64/vmm/amd/amdvi_priv.h

377

struct amdvi_ctrl *ctrl; /* Control area. */

sys/amd64/vmm/amd/ivrs_drv.c

683

softc->ctrl = (struct amdvi_ctrl *) PHYS_TO_DMAP(ivhd->BaseAddress);

sys/amd64/vmm/amd/svm.c

1000

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1003

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1006

vlapic_set_cr8(vlapic, ctrl->v_tpr);

sys/amd64/vmm/amd/svm.c

1009

KASSERT(ctrl->v_intr_vector == 0, ("%s: invalid "

sys/amd64/vmm/amd/svm.c

1010

"v_intr_vector %d", __func__, ctrl->v_intr_vector));

sys/amd64/vmm/amd/svm.c

1016

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1019

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1020

intinfo = ctrl->exitintinfo;

sys/amd64/vmm/amd/svm.c

1048

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1050

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1052

if (ctrl->v_irq && ctrl->v_intr_vector == 0) {

sys/amd64/vmm/amd/svm.c

1053

KASSERT(ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__));

sys/amd64/vmm/amd/svm.c

1060

ctrl->v_irq = 1;

sys/amd64/vmm/amd/svm.c

1061

ctrl->v_ign_tpr = 1;

sys/amd64/vmm/amd/svm.c

1062

ctrl->v_intr_vector = 0;

sys/amd64/vmm/amd/svm.c

1070

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1072

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1074

if (!ctrl->v_irq && ctrl->v_intr_vector == 0) {

sys/amd64/vmm/amd/svm.c

1081

ctrl->v_irq = 0;

sys/amd64/vmm/amd/svm.c

1082

ctrl->v_intr_vector = 0;

sys/amd64/vmm/amd/svm.c

1090

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1093

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1094

oldval = ctrl->intr_shadow;

sys/amd64/vmm/amd/svm.c

1097

ctrl->intr_shadow = newval;

sys/amd64/vmm/amd/svm.c

1106

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1108

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1109

*val = ctrl->intr_shadow;

sys/amd64/vmm/amd/svm.c

1354

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1364

ctrl = &vmcb->ctrl;

sys/amd64/vmm/amd/svm.c

1367

code = ctrl->exitcode;

sys/amd64/vmm/amd/svm.c

1368

info1 = ctrl->exitinfo1;

sys/amd64/vmm/amd/svm.c

1369

info2 = ctrl->exitinfo2;

sys/amd64/vmm/amd/svm.c

1373

vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0;

sys/amd64/vmm/amd/svm.c

1387

KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event "

sys/amd64/vmm/amd/svm.c

1388

"injection valid bit is set %#lx", __func__, ctrl->eventinj));

sys/amd64/vmm/amd/svm.c

1747

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1758

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1763

ctrl->intr_shadow = 0;

sys/amd64/vmm/amd/svm.c

1789

} else if (ctrl->intr_shadow) {

sys/amd64/vmm/amd/svm.c

1797

} else if (ctrl->eventinj & VMCB_EVENTINJ_VALID) {

sys/amd64/vmm/amd/svm.c

1803

"eventinj %#lx", ctrl->eventinj);

sys/amd64/vmm/amd/svm.c

1854

if (ctrl->intr_shadow) {

sys/amd64/vmm/amd/svm.c

1861

if (ctrl->eventinj & VMCB_EVENTINJ_VALID) {

sys/amd64/vmm/amd/svm.c

1863

"eventinj %#lx", vector, ctrl->eventinj);

sys/amd64/vmm/amd/svm.c

1898

if (ctrl->v_tpr != v_tpr) {

sys/amd64/vmm/amd/svm.c

1900

ctrl->v_tpr, v_tpr);

sys/amd64/vmm/amd/svm.c

1901

ctrl->v_tpr = v_tpr;

sys/amd64/vmm/amd/svm.c

1915

KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 ||

sys/amd64/vmm/amd/svm.c

1916

(state->rflags & PSL_I) == 0 || ctrl->intr_shadow,

sys/amd64/vmm/amd/svm.c

1919

ctrl->eventinj, ctrl->intr_shadow, state->rflags));

sys/amd64/vmm/amd/svm.c

1946

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

1955

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

1994

ctrl->tlb_ctrl = VMCB_TLB_FLUSH_NOTHING;

sys/amd64/vmm/amd/svm.c

2000

ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; /* (b1) */

sys/amd64/vmm/amd/svm.c

2008

KASSERT(ctrl->tlb_ctrl == VMCB_TLB_FLUSH_NOTHING,

sys/amd64/vmm/amd/svm.c

2009

("Invalid VMCB tlb_ctrl: %#x", ctrl->tlb_ctrl));

sys/amd64/vmm/amd/svm.c

2024

ctrl->tlb_ctrl = VMCB_TLB_FLUSH_ALL;

sys/amd64/vmm/amd/svm.c

2029

ctrl->asid = vcpu->asid.num;

sys/amd64/vmm/amd/svm.c

2037

ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST;

sys/amd64/vmm/amd/svm.c

2041

KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero"));

sys/amd64/vmm/amd/svm.c

2042

KASSERT(ctrl->asid == vcpu->asid.num,

sys/amd64/vmm/amd/svm.c

2043

("ASID mismatch: %u/%u", ctrl->asid, vcpu->asid.num));

sys/amd64/vmm/amd/svm.c

2131

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

2141

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

2236

ctrl->vmcb_clean = vmcb_clean & ~vcpu->dirty;

sys/amd64/vmm/amd/svm.c

2238

SVM_CTR1(vcpu, "vmcb clean %#x", ctrl->vmcb_clean);

sys/amd64/vmm/amd/svm.c

298

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

300

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

301

ctrl->tsc_offset = offset;

sys/amd64/vmm/amd/svm.c

421

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

425

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

426

return (ctrl->intercept[idx] & bitmask ? 1 : 0);

sys/amd64/vmm/amd/svm.c

432

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

437

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

438

oldval = ctrl->intercept[idx];

sys/amd64/vmm/amd/svm.c

441

ctrl->intercept[idx] |= bitmask;

sys/amd64/vmm/amd/svm.c

443

ctrl->intercept[idx] &= ~bitmask;

sys/amd64/vmm/amd/svm.c

445

if (ctrl->intercept[idx] != oldval) {

sys/amd64/vmm/amd/svm.c

448

oldval, ctrl->intercept[idx]);

sys/amd64/vmm/amd/svm.c

470

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

475

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

478

ctrl->iopm_base_pa = iopm_base_pa;

sys/amd64/vmm/amd/svm.c

479

ctrl->msrpm_base_pa = msrpm_base_pa;

sys/amd64/vmm/amd/svm.c

482

ctrl->np_enable = 1;

sys/amd64/vmm/amd/svm.c

483

ctrl->n_cr3 = np_pml4;

sys/amd64/vmm/amd/svm.c

555

ctrl->asid = 0;

sys/amd64/vmm/amd/svm.c

563

ctrl->v_intr_masking = 1;

sys/amd64/vmm/amd/svm.c

566

ctrl->lbr_virt_en = 1;

sys/amd64/vmm/amd/svm.c

833

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

841

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

844

info1 = ctrl->exitinfo1;

sys/amd64/vmm/amd/svm.c

907

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

911

ctrl = &vmcb->ctrl;

sys/amd64/vmm/amd/svm.c

926

inst_len = ctrl->inst_len;

sys/amd64/vmm/amd/svm.c

927

inst_bytes = ctrl->inst_bytes;

sys/amd64/vmm/amd/svm.c

961

struct vmcb_ctrl *ctrl;

sys/amd64/vmm/amd/svm.c

963

ctrl = svm_get_vmcb_ctrl(vcpu);

sys/amd64/vmm/amd/svm.c

965

KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0,

sys/amd64/vmm/amd/svm.c

966

("%s: event already pending %#lx", __func__, ctrl->eventinj));

sys/amd64/vmm/amd/svm.c

984

ctrl->eventinj = vector | (intr_type << 8) | VMCB_EVENTINJ_VALID;

sys/amd64/vmm/amd/svm.c

986

ctrl->eventinj |= VMCB_EVENTINJ_EC_VALID;

sys/amd64/vmm/amd/svm.c

987

ctrl->eventinj |= (uint64_t)error << 32;

sys/amd64/vmm/amd/svm_softc.h

110

return (&vcpu->vmcb->ctrl);

sys/amd64/vmm/amd/vmcb.h

349

struct vmcb_ctrl ctrl;

sys/arm/arm/debug_monitor.c

620

uint32_t reg_ctrl, reg_addr, ctrl, addr;

sys/arm/arm/debug_monitor.c

681

ctrl = (cr_size | cr_access | cr_priv | DBG_WB_CTRL_E);

sys/arm/arm/debug_monitor.c

701

ctrl = (cr_size | cr_access | cr_priv | DBG_WB_CTRL_E);

sys/arm/arm/debug_monitor.c

707

dbg_wb_write_reg(reg_ctrl, i, ctrl);

sys/arm/arm/debug_monitor.c

720

d->dbg_wcr[i] = ctrl;

sys/arm/arm/generic_timer.c

375

int counts, ctrl;

sys/arm/arm/generic_timer.c

381

ctrl = get_ctrl(sc->physical_sys);

sys/arm/arm/generic_timer.c

382

ctrl &= ~GT_CTRL_INT_MASK;

sys/arm/arm/generic_timer.c

383

ctrl |= GT_CTRL_ENABLE;

sys/arm/arm/generic_timer.c

385

set_ctrl(ctrl, sc->physical_sys);

sys/arm/arm/generic_timer.c

396

int ctrl;

sys/arm/arm/generic_timer.c

398

ctrl = get_ctrl(physical);

sys/arm/arm/generic_timer.c

399

ctrl &= ~GT_CTRL_ENABLE;

sys/arm/arm/generic_timer.c

400

set_ctrl(ctrl, physical);

sys/arm/arm/generic_timer.c

418

int ctrl;

sys/arm/arm/generic_timer.c

421

ctrl = get_ctrl(sc->physical_sys);

sys/arm/arm/generic_timer.c

422

if (ctrl & GT_CTRL_INT_STAT) {

sys/arm/arm/generic_timer.c

423

ctrl |= GT_CTRL_INT_MASK;

sys/arm/arm/generic_timer.c

424

set_ctrl(ctrl, sc->physical_sys);

sys/arm/arm/mpcore_timer.c

185

uint32_t ctrl;

sys/arm/arm/mpcore_timer.c

191

ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;

sys/arm/arm/mpcore_timer.c

195

ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;

sys/arm/arm/mpcore_timer.c

206

tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl);

sys/arm/broadcom/bcm2835/bcm2835_rng.c

271

uint32_t ctrl;

sys/arm/broadcom/bcm2835/bcm2835_rng.c

283

ctrl = bcm2835_rng_read4(sc, sc->conf->control_reg);

sys/arm/broadcom/bcm2835/bcm2835_rng.c

284

ctrl |= RNG_RBGEN_BIT;

sys/arm/broadcom/bcm2835/bcm2835_rng.c

286

ctrl |= RNG_RBG2X;

sys/arm/broadcom/bcm2835/bcm2835_rng.c

287

bcm2835_rng_write4(sc, sc->conf->control_reg, ctrl);

sys/arm/broadcom/bcm2835/bcm2835_rng.c

293

uint32_t ctrl;

sys/arm/broadcom/bcm2835/bcm2835_rng.c

296

ctrl = bcm2835_rng_read4(sc, sc->conf->control_reg);

sys/arm/broadcom/bcm2835/bcm2835_rng.c

297

ctrl &= ~RNG_RBGEN_BIT;

sys/arm/broadcom/bcm2835/bcm2835_rng.c

298

bcm2835_rng_write4(sc, sc->conf->control_reg, ctrl);

sys/arm/mv/mpic.c

87

#define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff)

sys/arm/nvidia/as3722_gpio.c

144

uint8_t ctrl;

sys/arm/nvidia/as3722_gpio.c

156

ctrl = sc->gpio_pins[pin]->pin_ctrl_reg;

sys/arm/nvidia/as3722_gpio.c

174

ctrl &= ~(AS3722_GPIO_MODE_MASK <<

sys/arm/nvidia/as3722_gpio.c

176

ctrl |= AS3722_MODE_PUSH_PULL << AS3722_GPIO_MODE_SHIFT;

sys/arm/nvidia/as3722_gpio.c

184

ctrl &= ~(AS3722_GPIO_MODE_MASK <<

sys/arm/nvidia/as3722_gpio.c

186

ctrl |= AS3722_MODE_INPUT << AS3722_GPIO_MODE_SHIFT;

sys/arm/nvidia/as3722_gpio.c

192

ctrl &= ~(AS3722_GPIO_IOSF_MASK << AS3722_GPIO_IOSF_SHIFT);

sys/arm/nvidia/as3722_gpio.c

193

ctrl |= fnc << AS3722_GPIO_IOSF_SHIFT;

sys/arm/nvidia/as3722_gpio.c

196

if (ctrl != sc->gpio_pins[pin]->pin_ctrl_reg) {

sys/arm/nvidia/as3722_gpio.c

197

rv = WR1(sc, AS3722_GPIO0_CONTROL + pin, ctrl);

sys/arm/nvidia/as3722_gpio.c

198

sc->gpio_pins[pin]->pin_ctrl_reg = ctrl;

sys/arm/nvidia/as3722_gpio.c

424

uint8_t ctrl, mode, iosf;

sys/arm/nvidia/as3722_gpio.c

432

ctrl = sc->gpio_pins[pin]->pin_ctrl_reg;

sys/arm/nvidia/as3722_gpio.c

433

iosf = (ctrl >> AS3722_GPIO_IOSF_SHIFT) & AS3722_GPIO_IOSF_MASK;

sys/arm/nvidia/as3722_gpio.c

440

ctrl &= ~(AS3722_GPIO_MODE_MASK << AS3722_GPIO_MODE_SHIFT);

sys/arm/nvidia/as3722_gpio.c

441

ctrl |= mode << AS3722_GPIO_MODE_SHIFT;

sys/arm/nvidia/as3722_gpio.c

443

if (ctrl != sc->gpio_pins[pin]->pin_ctrl_reg) {

sys/arm/nvidia/as3722_gpio.c

444

rv = WR1(sc, AS3722_GPIO0_CONTROL + pin, ctrl);

sys/arm/nvidia/as3722_gpio.c

445

sc->gpio_pins[pin]->pin_ctrl_reg = ctrl;

sys/arm/nvidia/as3722_gpio.c

476

uint8_t tmp, mode, ctrl;

sys/arm/nvidia/as3722_gpio.c

484

ctrl = sc->gpio_pins[pin]->pin_ctrl_reg;

sys/arm/nvidia/as3722_gpio.c

485

mode = (ctrl >> AS3722_GPIO_MODE_SHIFT) & AS3722_GPIO_MODE_MASK;

sys/arm/nvidia/as3722_gpio.c

496

if (ctrl & AS3722_GPIO_INVERT)

sys/arm/ti/cpsw/if_cpsw.c

2609

uint32_t ctrl, intr_per_ms;

sys/arm/ti/cpsw/if_cpsw.c

2616

ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);

sys/arm/ti/cpsw/if_cpsw.c

2617

ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK);

sys/arm/ti/cpsw/if_cpsw.c

2620

cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);

sys/arm/ti/cpsw/if_cpsw.c

2638

ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK;

sys/arm/ti/cpsw/if_cpsw.c

2643

ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE;

sys/arm/ti/cpsw/if_cpsw.c

2644

cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);

sys/arm/ti/ti_spi.c

111

device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS);

sys/arm/ti/ti_spi.c

78

int clk, conf, ctrl, div, i, j, wl;

sys/arm/ti/ti_spi.c

94

ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i));

sys/arm/ti/ti_spi.c

99

div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4;

sys/arm64/arm64/exec_machdep.c

253

uint32_t ctrl;

sys/arm64/arm64/exec_machdep.c

261

ctrl = regs->db_breakregs[i].dbr_ctrl;

sys/arm64/arm64/exec_machdep.c

284

ctrl &= DBGBCR_EN | DBGBCR_PMC | DBGBCR_BAS;

sys/arm64/arm64/exec_machdep.c

285

if ((ctrl & DBGBCR_EN) != 0) {

sys/arm64/arm64/exec_machdep.c

287

if ((ctrl & DBGBCR_PMC) != DBGBCR_PMC_EL0)

sys/arm64/arm64/exec_machdep.c

294

monitor->dbg_bcr[i] = ctrl;

sys/arm64/arm64/exec_machdep.c

299

ctrl = regs->db_watchregs[i].dbw_ctrl;

sys/arm64/arm64/exec_machdep.c

312

ctrl &= DBGWCR_EN | DBGWCR_PAC | DBGWCR_LSC | DBGWCR_BAS |

sys/arm64/arm64/exec_machdep.c

315

if ((ctrl & DBGWCR_EN) != 0) {

sys/arm64/arm64/exec_machdep.c

317

if ((ctrl & DBGWCR_PAC) != DBGWCR_PAC_EL0)

sys/arm64/arm64/exec_machdep.c

321

if ((ctrl & DBGWCR_LSC) == 0)

sys/arm64/arm64/exec_machdep.c

328

if ((ctrl & DBGWCR_BAS) != DBGWCR_BAS &&

sys/arm64/arm64/exec_machdep.c

329

(ctrl & DBGWCR_MASK) != 0)

sys/arm64/arm64/exec_machdep.c

335

monitor->dbg_wcr[i] = ctrl;

sys/dev/acpi_support/acpi_system76.c

224

struct acpi_ctrl *ctrl;

sys/dev/acpi_support/acpi_system76.c

233

if ((ctrl = acpi_system76_ctrl_map(sc, method)) == NULL)

sys/dev/acpi_support/acpi_system76.c

248

Arg[1].Integer.Value = ctrl->val;

sys/dev/acpi_support/acpi_system76.c

257

ctrl->val = Obj.Integer.Value;

sys/dev/acpi_support/acpi_system76.c

264

ctrl->val);

sys/dev/acpi_support/acpi_system76.c

267

&ctrl->val);

sys/dev/acpi_support/acpi_system76.c

306

struct acpi_ctrl *ctrl;

sys/dev/acpi_support/acpi_system76.c

313

if ((ctrl = acpi_system76_ctrl_map(sc, method)) == NULL)

sys/dev/acpi_support/acpi_system76.c

319

ctrl->exists = true;

sys/dev/acpi_support/acpi_system76.c

325

s76_sysctl_table[method].get_method, &ctrl->val))) {

sys/dev/acpi_support/acpi_system76.c

326

ctrl->exists = false;

sys/dev/acpi_support/acpi_system76.c

330

ctrl->exists = true;

sys/dev/acpi_support/acpi_system76.c

359

struct acpi_ctrl *ctrl, *ctrl_cmp;

sys/dev/acpi_support/acpi_system76.c

368

if ((ctrl = acpi_system76_ctrl_map(sc, method)) == NULL)

sys/dev/acpi_support/acpi_system76.c

371

val = ctrl->val;

sys/dev/acpi_support/acpi_system76.c

412

ctrl->val = val;

sys/dev/acpi_support/acpi_system76.c

426

struct acpi_ctrl *ctrl;

sys/dev/acpi_support/acpi_system76.c

439

if ((ctrl = acpi_system76_ctrl_map(sc, method)) == NULL)

sys/dev/acpi_support/acpi_system76.c

442

if (!ctrl->exists)

sys/dev/acpi_support/acpi_system76.c

542

struct acpi_ctrl *ctrl;

sys/dev/acpi_support/acpi_system76.c

545

if ((ctrl = acpi_system76_ctrl_map(sc, S76_CTRL_KBB)) != NULL) {

sys/dev/acpi_support/acpi_system76.c

546

ctrl->val = 0;

sys/dev/acpi_support/acpi_system76.c

557

struct acpi_ctrl *ctrl;

sys/dev/acpi_support/acpi_system76.c

560

if ((ctrl = acpi_system76_ctrl_map(sc, S76_CTRL_KBB)) != NULL) {

sys/dev/acpi_support/acpi_system76.c

561

ctrl->val = backlight_to_devstate(sc->backlight_level);

sys/dev/ahci/ahci_fsl_fdt.c

191

ahci_fsl_fdt_ecc_init(struct ahci_fsl_fdt_controller *ctrl)

sys/dev/ahci/ahci_fsl_fdt.c

195

switch (ctrl->soc_type) {

sys/dev/ahci/ahci_fsl_fdt.c

201

if (!ecc_inited && ctrl->r_ecc == NULL)

sys/dev/ahci/ahci_fsl_fdt.c

204

ATA_OUTL(ctrl->r_ecc, AHCI_FSL_REG_ECC,

sys/dev/ahci/ahci_fsl_fdt.c

210

if (!ecc_inited && ctrl->r_ecc == NULL)

sys/dev/ahci/ahci_fsl_fdt.c

213

val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC);

sys/dev/ahci/ahci_fsl_fdt.c

215

ATA_OUTL(ctrl->r_ecc, AHCI_FSL_REG_ECC, val);

sys/dev/ahci/ahci_fsl_fdt.c

222

if (!ecc_inited && ctrl->r_ecc == NULL)

sys/dev/ahci/ahci_fsl_fdt.c

226

val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC);

sys/dev/ahci/ahci_fsl_fdt.c

228

ATA_OUTL(ctrl->r_ecc, AHCI_FSL_REG_ECC, val);

sys/dev/ahci/ahci_fsl_fdt.c

233

panic("Unimplemented SOC type: %d", ctrl->soc_type);

sys/dev/ahci/ahci_fsl_fdt.c

241

ahci_fsl_fdt_phy_init(struct ahci_fsl_fdt_controller *ctrl)

sys/dev/ahci/ahci_fsl_fdt.c

245

ahci = &ctrl->ctlr;

sys/dev/ahci/ahci_fsl_fdt.c

246

if (ctrl->soc_type == QORIQ_AHCI_LS1021A) {

sys/dev/ahci/ahci_fsl_fdt.c

260

if (ctrl->ctlr.dma_coherent)

sys/dev/ahci/ahci_fsl_fdt.c

273

if (ctrl->ctlr.dma_coherent)

sys/dev/aq/aq_fw2x.c

422

uint64_t ctrl = get_mpi_ctrl_(hw);

sys/dev/aq/aq_fw2x.c

427

if ((ctrl & mask) != (state & mask)) {

sys/dev/aq/aq_fw2x.c

430

(unsigned long long)ctrl, (unsigned long long)state,

sys/dev/aq/aq_fw2x.c

437

ctrl ^= mask;

sys/dev/aq/aq_fw2x.c

438

set_mpi_ctrl_(hw, ctrl);

sys/dev/aq/aq_fw2x.c

441

ctrl &= mask;

sys/dev/aq/aq_fw2x.c

445

if ((get_mpi_state_(hw) & mask) == ctrl)

sys/dev/bfe/if_bfe.c

784

u_int32_t ctrl;

sys/dev/bfe/if_bfe.c

815

ctrl = segs[0].ds_len & BFE_DESC_LEN;

sys/dev/bfe/if_bfe.c

816

KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",

sys/dev/bfe/if_bfe.c

817

__func__, ctrl));

sys/dev/bfe/if_bfe.c

819

ctrl |= BFE_DESC_EOT;

sys/dev/bfe/if_bfe.c

820

r->bfe_ctrl = ctrl;

sys/dev/bfe/if_bfe.c

823

d->bfe_ctrl = htole32(ctrl);

sys/dev/bhnd/cores/chipc/chipc_gpio.c

461

uint32_t out, outen, ctrl;

sys/dev/bhnd/cores/chipc/chipc_gpio.c

492

ctrl = CC_GPIO_RD4(sc, CHIPC_GPIOCTRL);

sys/dev/bhnd/cores/chipc/chipc_gpio.c

507

if ((ctrl & (1 << pin)) != 0) {

sys/dev/bhnd/cores/chipc/chipc_gpio.c

617

chipc_gpio_commit_reg(sc, CHIPC_GPIOCTRL, &update->ctrl);

sys/dev/bhnd/cores/chipc/chipc_gpio.c

648

CC_GPIO_UPDATE(update, pin_num, ctrl, false);

sys/dev/bhnd/cores/chipc/chipc_gpio.c

663

CC_GPIO_UPDATE(update, pin_num, ctrl, false);

sys/dev/bhnd/cores/chipc/chipc_gpio.c

682

CC_GPIO_UPDATE(update, pin_num, ctrl, true);

sys/dev/bhnd/cores/chipc/chipc_gpiovar.h

104

struct chipc_gpio_reg ctrl; /**< CHIPC_GPIOCTRL changes */

sys/dev/bwi/bwiphy.c

135

bwi_phy_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)

sys/dev/bwi/bwiphy.c

139

CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);

sys/dev/bwi/bwiphy.c

144

bwi_phy_read(struct bwi_mac *mac, uint16_t ctrl)

sys/dev/bwi/bwiphy.c

148

CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);

sys/dev/bwi/bwiphy.h

67

#define PHY_WRITE(mac, ctrl, val) bwi_phy_write((mac), (ctrl), (val))

sys/dev/bwi/bwiphy.h

68

#define PHY_READ(mac, ctrl) bwi_phy_read((mac), (ctrl))

sys/dev/bwi/bwiphy.h

70

#define PHY_SETBITS(mac, ctrl, bits) \

sys/dev/bwi/bwiphy.h

71

PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) | (bits))

sys/dev/bwi/bwiphy.h

72

#define PHY_CLRBITS(mac, ctrl, bits) \

sys/dev/bwi/bwiphy.h

73

PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) & ~(bits))

sys/dev/bwi/bwiphy.h

74

#define PHY_FILT_SETBITS(mac, ctrl, filt, bits) \

sys/dev/bwi/bwiphy.h

75

PHY_WRITE((mac), (ctrl), (PHY_READ((mac), (ctrl)) & (filt)) | (bits))

sys/dev/bwi/bwirf.c

1389

bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)

sys/dev/bwi/bwirf.c

1396

ctrl <<= 8;

sys/dev/bwi/bwirf.c

1401

PHY_WRITE(mac, 0x812, ctrl | 0xb0);

sys/dev/bwi/bwirf.c

1403

PHY_WRITE(mac, 0x812, ctrl | 0xb2);

sys/dev/bwi/bwirf.c

1405

PHY_WRITE(mac, 0x812, ctrl | 0xb3);

sys/dev/bwi/bwirf.c

1409

PHY_WRITE(mac, 0x15, ctrl | 0xefa0);

sys/dev/bwi/bwirf.c

1411

PHY_WRITE(mac, 0x15, ctrl | 0xefe0);

sys/dev/bwi/bwirf.c

1413

PHY_WRITE(mac, 0x15, ctrl | 0xffe0);

sys/dev/bwi/bwirf.c

197

bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)

sys/dev/bwi/bwirf.c

201

CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);

sys/dev/bwi/bwirf.c

206

bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)

sys/dev/bwi/bwirf.c

211

ctrl |= rf->rf_ctrl_rd;

sys/dev/bwi/bwirf.c

214

if (ctrl < 0x70)

sys/dev/bwi/bwirf.c

215

ctrl += 0x80;

sys/dev/bwi/bwirf.c

216

else if (ctrl < 0x80)

sys/dev/bwi/bwirf.c

217

ctrl += 0x70;

sys/dev/bwi/bwirf.c

220

CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);

sys/dev/bwi/if_bwi.c

330

uint32_t ctrl, addr, addr_hi, addr_lo;

sys/dev/bwi/if_bwi.c

338

ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |

sys/dev/bwi/if_bwi.c

341

ctrl |= BWI_DESC32_C_EOR;

sys/dev/bwi/if_bwi.c

344

ctrl |= BWI_DESC32_C_FRAME_START |

sys/dev/bwi/if_bwi.c

350

desc->ctrl = htole32(ctrl);

sys/dev/bwi/if_bwivar.h

124

uint32_t ctrl;

sys/dev/bxe/bxe_elink.c

6877

uint16_t cnt, ctrl;

sys/dev/bxe/bxe_elink.c

6882

MDIO_PMA_REG_CTRL, &ctrl);

sys/dev/bxe/bxe_elink.c

6886

MDIO_PMA_REG_CTRL, &ctrl);

sys/dev/bxe/bxe_elink.c

6887

if (!(ctrl & (1<<15)))

sys/dev/bxe/bxe_elink.c

6896

ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);

sys/dev/cxgb/common/cxgb_t3_hw.c

2647

unsigned int ctrl, intr = 0;

sys/dev/cxgb/common/cxgb_t3_hw.c

2659

ctrl = t3_read_reg(adapter, A_SG_CONTROL);

sys/dev/cxgb/common/cxgb_t3_hw.c

2661

((irq_vec_idx == 0) && !(ctrl & F_ONEINTMULTQ)))

sys/dev/cxgb/common/cxgb_xgmac.c

74

u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;

sys/dev/cxgb/common/cxgb_xgmac.c

76

t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |

sys/dev/cxgb/common/cxgb_xgmac.c

80

(void)t3_read_reg(adap, ctrl);

sys/dev/cxgb/common/cxgb_xgmac.c

84

t3_set_reg_field(adap, ctrl, clear[i], 0);

sys/dev/cxgb/cxgb_adapter.h

163

struct lro_ctrl ctrl;

sys/dev/cxgb/cxgb_offload.h

107

oh->flags = V_HDR_NDESC(1) | V_HDR_QSET(qset) | V_HDR_CTRL(ctrl);

sys/dev/cxgb/cxgb_offload.h

94

#define M_GETHDR_OFLD(qset, ctrl, cpl) \

sys/dev/cxgb/cxgb_offload.h

95

m_gethdr_ofld(qset, ctrl, sizeof(*cpl), (void **)&cpl)

sys/dev/cxgb/cxgb_offload.h

97

m_gethdr_ofld(int qset, int ctrl, int cpllen, void **cpl)

sys/dev/cxgb/cxgb_sge.c

2048

tcp_lro_free(&q->lro.ctrl);

sys/dev/cxgb/cxgb_sge.c

2525

ret = tcp_lro_init(&q->lro.ctrl);

sys/dev/cxgb/cxgb_sge.c

2531

q->lro.ctrl.ifp = pi->ifp;

sys/dev/cxgb/cxgb_sge.c

2829

struct lro_ctrl *lro_ctrl = &qs->lro.ctrl;

sys/dev/cxgb/cxgb_sge.c

3588

CTLFLAG_RD, &qs->lro.ctrl.lro_queued, 0, NULL);

sys/dev/cxgb/cxgb_sge.c

3590

CTLFLAG_RD, &qs->lro.ctrl.lro_flushed, 0, NULL);

sys/dev/cxgb/cxgb_sge.c

3592

CTLFLAG_RD, &qs->lro.ctrl.lro_bad_csum, 0, NULL);

sys/dev/cxgb/cxgb_sge.c

3594

CTLFLAG_RD, &qs->lro.ctrl.lro_cnt, 0, NULL);

sys/dev/cxgb/cxgb_sge.c

430

u_int ctrl, ups;

sys/dev/cxgb/cxgb_sge.c

434

ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |

sys/dev/cxgb/cxgb_sge.c

439

ctrl |= F_EGRGENCTRL;

sys/dev/cxgb/cxgb_sge.c

443

ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;

sys/dev/cxgb/cxgb_sge.c

445

t3_write_reg(adap, A_SG_CONTROL, ctrl);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1115

uint32_t ctrl;

sys/dev/cxgbe/crypto/t6_kern_tls.c

1129

ctrl = sizeof(struct cpl_tx_pkt_core) + pktlen;

sys/dev/cxgbe/crypto/t6_kern_tls.c

1130

len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + ctrl, 16);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1136

V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));

sys/dev/cxgbe/crypto/t6_kern_tls.c

1138

ctrl = V_FW_WR_LEN16(len16);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1139

wr->equiq_to_len16 = htobe32(ctrl);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1210

uint32_t ctrl;

sys/dev/cxgbe/crypto/t6_kern_tls.c

1230

ctrl = sizeof(struct cpl_tx_pkt_core) + pktlen;

sys/dev/cxgbe/crypto/t6_kern_tls.c

1231

len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + ctrl, 16);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1237

V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));

sys/dev/cxgbe/crypto/t6_kern_tls.c

1239

ctrl = V_FW_WR_LEN16(len16);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1240

wr->equiq_to_len16 = htobe32(ctrl);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1861

uint32_t ctrl;

sys/dev/cxgbe/crypto/t6_kern_tls.c

1875

ctrl = sizeof(struct cpl_tx_pkt_core) + pktlen;

sys/dev/cxgbe/crypto/t6_kern_tls.c

1876

len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + ctrl, 16);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1882

V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));

sys/dev/cxgbe/crypto/t6_kern_tls.c

1884

ctrl = V_FW_WR_LEN16(len16);

sys/dev/cxgbe/crypto/t6_kern_tls.c

1885

wr->equiq_to_len16 = htobe32(ctrl);

sys/dev/cxgbe/crypto/t7_kern_tls.c

1155

uint32_t ctrl;

sys/dev/cxgbe/crypto/t7_kern_tls.c

1168

ctrl = sizeof(struct cpl_tx_pkt_core) + pktlen;

sys/dev/cxgbe/crypto/t7_kern_tls.c

1169

len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + ctrl, 16);

sys/dev/cxgbe/crypto/t7_kern_tls.c

1176

V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));

sys/dev/cxgbe/crypto/t7_kern_tls.c

1178

ctrl = V_FW_WR_LEN16(len16);

sys/dev/cxgbe/crypto/t7_kern_tls.c

1179

wr->equiq_to_len16 = htobe32(ctrl);

sys/dev/cxgbe/crypto/t7_kern_tls.c

966

uint32_t ctrl;

sys/dev/cxgbe/crypto/t7_kern_tls.c

973

ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |

sys/dev/cxgbe/crypto/t7_kern_tls.c

979

ctrl |= F_LSO_IPV6;

sys/dev/cxgbe/crypto/t7_kern_tls.c

982

lso->lso_ctrl = htobe32(ctrl);

sys/dev/cxgbe/cudbg/fastlz.c

436

unsigned int ctrl = (*ip++) & 31;

sys/dev/cxgbe/cudbg/fastlz.c

441

unsigned int len = ctrl >> 5;

sys/dev/cxgbe/cudbg/fastlz.c

442

unsigned int ofs = (ctrl & 31) << 8;

sys/dev/cxgbe/cudbg/fastlz.c

444

if (ctrl >= 32) {

sys/dev/cxgbe/cudbg/fastlz.c

484

ctrl = *ip++;

sys/dev/cxgbe/cudbg/fastlz.c

532

ctrl++;

sys/dev/cxgbe/cudbg/fastlz.c

534

if (FASTLZ_UNEXPECT_CONDITIONAL(op + ctrl > op_limit))

sys/dev/cxgbe/cudbg/fastlz.c

536

if (FASTLZ_UNEXPECT_CONDITIONAL(ip + ctrl > ip_limit))

sys/dev/cxgbe/cudbg/fastlz.c

541

for (--ctrl; ctrl; ctrl--)

sys/dev/cxgbe/cudbg/fastlz.c

546

ctrl = *ip++;

sys/dev/cxgbe/t4_sge.c

5467

uint64_t ctrl;

sys/dev/cxgbe/t4_sge.c

5499

ctrl = 0;

sys/dev/cxgbe/t4_sge.c

5501

ctrl |= F_TXPKT_IPCSUM_DIS;

sys/dev/cxgbe/t4_sge.c

5527

ctrl |= F_TXPKT_L4CSUM_DIS;

sys/dev/cxgbe/t4_sge.c

5528

ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);

sys/dev/cxgbe/t4_sge.c

5530

ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);

sys/dev/cxgbe/t4_sge.c

5532

ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);

sys/dev/cxgbe/t4_sge.c

5534

return (ctrl);

sys/dev/cxgbe/t4_sge.c

5541

uint32_t ctrl;

sys/dev/cxgbe/t4_sge.c

5548

ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |

sys/dev/cxgbe/t4_sge.c

5554

ctrl |= F_LSO_IPV6;

sys/dev/cxgbe/t4_sge.c

5557

lso->lso_ctrl = htobe32(ctrl);

sys/dev/cxgbe/t4_sge.c

5570

uint32_t ctrl;

sys/dev/cxgbe/t4_sge.c

5583

ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |

sys/dev/cxgbe/t4_sge.c

5590

ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;

sys/dev/cxgbe/t4_sge.c

5592

ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |

sys/dev/cxgbe/t4_sge.c

5595

tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);

sys/dev/cxgbe/t4_sge.c

5608

ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(

sys/dev/cxgbe/t4_sge.c

5613

ctrl |= F_CPL_TX_TNL_LSO_IPV6;

sys/dev/cxgbe/t4_sge.c

5614

tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);

sys/dev/cxgbe/t4_sge.c

5641

uint32_t ctrl; /* used in many unrelated places */

sys/dev/cxgbe/t4_sge.c

5651

ctrl = sizeof(struct cpl_tx_pkt_core);

sys/dev/cxgbe/t4_sge.c

5653

ctrl += sizeof(struct cpl_tx_pkt_lso_core);

sys/dev/cxgbe/t4_sge.c

5660

V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));

sys/dev/cxgbe/t4_sge.c

5662

ctrl = V_FW_WR_LEN16(len16);

sys/dev/cxgbe/t4_sge.c

5663

wr->equiq_to_len16 = htobe32(ctrl);

sys/dev/cxgbe/t4_sge.c

5774

uint32_t ctrl; /* used in many unrelated places */

sys/dev/cxgbe/t4_sge.c

5785

ctrl = sizeof(struct cpl_tx_pkt_core);

sys/dev/cxgbe/t4_sge.c

5788

ctrl += sizeof(struct cpl_tx_tnl_lso);

sys/dev/cxgbe/t4_sge.c

5790

ctrl += sizeof(struct cpl_tx_pkt_lso_core);

sys/dev/cxgbe/t4_sge.c

5794

ctrl += pktlen;

sys/dev/cxgbe/t4_sge.c

5806

V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));

sys/dev/cxgbe/t4_sge.c

5808

ctrl = V_FW_WR_LEN16(len16);

sys/dev/cxgbe/t4_sge.c

5809

wr->equiq_to_len16 = htobe32(ctrl);

sys/dev/cxgbe/t4_sge.c

6827

uint32_t ctrl; /* used in many unrelated places */

sys/dev/cxgbe/t4_sge.c

6843

ctrl = sizeof(struct cpl_tx_pkt_core);

sys/dev/cxgbe/t4_sge.c

6845

ctrl += sizeof(struct cpl_tx_pkt_lso_core);

sys/dev/cxgbe/t4_sge.c

6847

ctrl += immhdrs;

sys/dev/cxgbe/t4_sge.c

6850

V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));

sys/dev/cxgbe/t4_sge.c

6881

ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |

sys/dev/cxgbe/t4_sge.c

6888

ctrl |= F_LSO_IPV6;

sys/dev/cxgbe/t4_sge.c

6889

lso->lso_ctrl = htobe32(ctrl);

sys/dev/dpaa2/dpaa2_frame.c

101

fd->ctrl = (0x4u & DPAA2_FD_PTAC_MASK) << DPAA2_FD_PTAC_SHIFT;

sys/dev/dpaa2/dpaa2_frame.c

109

return ((fd->ctrl >> DPAA2_FD_ERR_SHIFT) & DPAA2_FD_ERR_MASK);

sys/dev/dpaa2/dpaa2_frame.c

149

if (((fd->ctrl >> DPAA2_FD_PTAC_SHIFT) & DPAA2_FD_PTAC_MASK) >= 0x4u) {

sys/dev/dpaa2/dpaa2_frame.h

105

uint32_t ctrl;

sys/dev/dpaa2/dpaa2_swp.c

519

uint8_t ctrl;

sys/dev/dpaa2/dpaa2_swp.c

537

cmd.ctrl = cdan_en ? 1u : 0u;

sys/dev/e1000/e1000_80003es2lan.c

1118

u32 ctrl;

sys/dev/e1000/e1000_80003es2lan.c

1124

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_80003es2lan.c

1125

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_80003es2lan.c

1126

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_80003es2lan.c

1127

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_80003es2lan.c

748

u32 ctrl;

sys/dev/e1000/e1000_80003es2lan.c

770

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_80003es2lan.c

777

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82540.c

272

u32 ctrl, manc;

sys/dev/e1000/e1000_82540.c

290

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82540.c

296

E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82540.c

304

E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82540.c

413

u32 ctrl;

sys/dev/e1000/e1000_82540.c

419

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82540.c

420

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_82540.c

421

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82540.c

422

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82541.c

298

u32 ledctl, ctrl, manc;

sys/dev/e1000/e1000_82541.c

315

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82541.c

319

E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));

sys/dev/e1000/e1000_82541.c

333

E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82541.c

336

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82541.c

538

u32 ctrl, ledctl;

sys/dev/e1000/e1000_82541.c

542

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82541.c

543

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_82541.c

544

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82541.c

545

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82542.c

196

u32 ctrl;

sys/dev/e1000/e1000_82542.c

218

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82542.c

221

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82542.c

248

u32 ctrl;

sys/dev/e1000/e1000_82542.c

289

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82542.c

290

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);

sys/dev/e1000/e1000_82542.c

375

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82542.c

379

ctrl |= E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_82542.c

380

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_82542.c

381

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82542.c

394

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82542.c

398

ctrl &= ~E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_82542.c

399

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_82542.c

400

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1062

u32 ctrl;

sys/dev/e1000/e1000_82543.c

1068

ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;

sys/dev/e1000/e1000_82543.c

1076

ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82543.c

1077

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1082

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82543.c

1083

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1150

u32 ctrl;

sys/dev/e1000/e1000_82543.c

1155

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

1158

ctrl &= ~E1000_CTRL_LRST;

sys/dev/e1000/e1000_82543.c

1168

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1336

u32 rxcw, ctrl, status;

sys/dev/e1000/e1000_82543.c

1341

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

1354

if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&

sys/dev/e1000/e1000_82543.c

1368

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

1369

ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

sys/dev/e1000/e1000_82543.c

1370

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1378

} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

sys/dev/e1000/e1000_82543.c

1387

E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));

sys/dev/e1000/e1000_82543.c

1405

u32 ctrl;

sys/dev/e1000/e1000_82543.c

1415

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

1416

ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82543.c

1417

ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);

sys/dev/e1000/e1000_82543.c

1427

ctrl &= ~E1000_CTRL_FD;

sys/dev/e1000/e1000_82543.c

1429

ctrl |= E1000_CTRL_FD;

sys/dev/e1000/e1000_82543.c

1438

ctrl |= E1000_CTRL_SPD_1000;

sys/dev/e1000/e1000_82543.c

1440

ctrl |= E1000_CTRL_SPD_100;

sys/dev/e1000/e1000_82543.c

1442

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1482

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

1489

ctrl &= ~E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_82543.c

1490

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_82543.c

1493

ctrl |= E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_82543.c

1494

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_82543.c

1496

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

1509

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

1516

ctrl |= E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_82543.c

1517

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_82543.c

1519

ctrl &= ~E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_82543.c

1520

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_82543.c

1522

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

590

static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)

sys/dev/e1000/e1000_82543.c

596

E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));

sys/dev/e1000/e1000_82543.c

609

static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)

sys/dev/e1000/e1000_82543.c

615

E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));

sys/dev/e1000/e1000_82543.c

633

u32 ctrl, mask;

sys/dev/e1000/e1000_82543.c

644

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

647

ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);

sys/dev/e1000/e1000_82543.c

657

ctrl |= E1000_CTRL_MDIO;

sys/dev/e1000/e1000_82543.c

659

ctrl &= ~E1000_CTRL_MDIO;

sys/dev/e1000/e1000_82543.c

661

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

666

e1000_raise_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

667

e1000_lower_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

684

u32 ctrl;

sys/dev/e1000/e1000_82543.c

69

static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);

sys/dev/e1000/e1000_82543.c

697

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

703

ctrl &= ~E1000_CTRL_MDIO_DIR;

sys/dev/e1000/e1000_82543.c

704

ctrl &= ~E1000_CTRL_MDIO;

sys/dev/e1000/e1000_82543.c

706

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82543.c

71

static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);

sys/dev/e1000/e1000_82543.c

714

e1000_raise_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

715

e1000_lower_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

719

e1000_raise_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

720

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

722

if (ctrl & E1000_CTRL_MDIO)

sys/dev/e1000/e1000_82543.c

724

e1000_lower_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

727

e1000_raise_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

728

e1000_lower_mdi_clk_82543(hw, &ctrl);

sys/dev/e1000/e1000_82543.c

903

u32 ctrl;

sys/dev/e1000/e1000_82543.c

923

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

927

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82543.c

933

E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82543.c

960

u32 ctrl;

sys/dev/e1000/e1000_82543.c

986

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82543.c

987

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);

sys/dev/e1000/e1000_82571.c

1355

u32 ctrl;

sys/dev/e1000/e1000_82571.c

1360

ctrl = hw->mac.ledctl_mode2;

sys/dev/e1000/e1000_82571.c

1368

ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));

sys/dev/e1000/e1000_82571.c

1370

E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);

sys/dev/e1000/e1000_82571.c

1452

u32 ctrl;

sys/dev/e1000/e1000_82571.c

1457

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82571.c

1458

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_82571.c

1459

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82571.c

1460

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82571.c

1534

u32 ctrl;

sys/dev/e1000/e1000_82571.c

1542

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82571.c

1576

(ctrl & ~E1000_CTRL_SLU));

sys/dev/e1000/e1000_82571.c

1610

ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

sys/dev/e1000/e1000_82571.c

1611

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82571.c

1634

E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &

sys/dev/e1000/e1000_82571.c

951

u32 ctrl, ctrl_ext, eecd, tctl;

sys/dev/e1000/e1000_82571.c

987

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82571.c

990

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82575.c

1300

u32 ctrl;

sys/dev/e1000/e1000_82575.c

1327

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82575.c

1330

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/e1000_82575.c

1405

u32 ctrl;

sys/dev/e1000/e1000_82575.c

1410

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82575.c

1411

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_82575.c

1412

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_82575.c

1413

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_82575.c

2229

u32 ctrl;

sys/dev/e1000/e1000_82575.c

2241

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82575.c

2266

ctrl |= E1000_CTRL_DEV_RST;

sys/dev/e1000/e1000_82575.c

2268

ctrl |= E1000_CTRL_RST;

sys/dev/e1000/e1000_82575.c

2270

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_i210.c

711

u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;

sys/dev/e1000/e1000_i210.c

745

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_i210.c

746

E1000_WRITE_REG(hw, E1000_CTRL, ctrl|E1000_CTRL_PHY_RST);

sys/dev/e1000/e1000_ich8lan.c

4979

u32 ctrl, reg;

sys/dev/e1000/e1000_ich8lan.c

5025

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_ich8lan.c

5032

ctrl |= E1000_CTRL_PHY_RST;

sys/dev/e1000/e1000_ich8lan.c

5052

E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));

sys/dev/e1000/e1000_ich8lan.c

5073

if (ctrl & E1000_CTRL_PHY_RST) {

sys/dev/e1000/e1000_ich8lan.c

5343

u32 ctrl;

sys/dev/e1000/e1000_ich8lan.c

5349

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_ich8lan.c

5350

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_ich8lan.c

5351

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_ich8lan.c

5352

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_ich8lan.c

5434

u32 ctrl;

sys/dev/e1000/e1000_ich8lan.c

5439

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_ich8lan.c

5440

ctrl |= E1000_CTRL_SLU;

sys/dev/e1000/e1000_ich8lan.c

5441

ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_ich8lan.c

5442

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

1185

u32 ctrl;

sys/dev/e1000/e1000_mac.c

1190

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

1193

ctrl &= ~E1000_CTRL_LRST;

sys/dev/e1000/e1000_mac.c

1209

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

1298

u32 ctrl;

sys/dev/e1000/e1000_mac.c

1302

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

1325

ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));

sys/dev/e1000/e1000_mac.c

1328

ctrl &= (~E1000_CTRL_TFCE);

sys/dev/e1000/e1000_mac.c

1329

ctrl |= E1000_CTRL_RFCE;

sys/dev/e1000/e1000_mac.c

1332

ctrl &= (~E1000_CTRL_RFCE);

sys/dev/e1000/e1000_mac.c

1333

ctrl |= E1000_CTRL_TFCE;

sys/dev/e1000/e1000_mac.c

1336

ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);

sys/dev/e1000/e1000_mac.c

1343

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

1937

u32 ctrl;

sys/dev/e1000/e1000_mac.c

1943

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

1944

ctrl &= ~E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_mac.c

1945

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_mac.c

1946

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

1966

u32 ctrl;

sys/dev/e1000/e1000_mac.c

1972

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

1973

ctrl |= E1000_CTRL_SWDPIN0;

sys/dev/e1000/e1000_mac.c

1974

ctrl |= E1000_CTRL_SWDPIO0;

sys/dev/e1000/e1000_mac.c

1975

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

2024

u32 ctrl;

sys/dev/e1000/e1000_mac.c

2032

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

2033

ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;

sys/dev/e1000/e1000_mac.c

2034

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

785

u32 ctrl;

sys/dev/e1000/e1000_mac.c

791

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

803

if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&

sys/dev/e1000/e1000_mac.c

815

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

816

ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

sys/dev/e1000/e1000_mac.c

817

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

825

} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

sys/dev/e1000/e1000_mac.c

833

E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));

sys/dev/e1000/e1000_mac.c

852

u32 ctrl;

sys/dev/e1000/e1000_mac.c

858

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

880

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_mac.c

881

ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

sys/dev/e1000/e1000_mac.c

882

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_mac.c

890

} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

sys/dev/e1000/e1000_mac.c

898

E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));

sys/dev/e1000/e1000_phy.c

2027

u32 ctrl;

sys/dev/e1000/e1000_phy.c

2035

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_phy.c

2036

ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

sys/dev/e1000/e1000_phy.c

2037

ctrl &= ~E1000_CTRL_SPD_SEL;

sys/dev/e1000/e1000_phy.c

2040

ctrl &= ~E1000_CTRL_ASDE;

sys/dev/e1000/e1000_phy.c

2047

ctrl &= ~E1000_CTRL_FD;

sys/dev/e1000/e1000_phy.c

2051

ctrl |= E1000_CTRL_FD;

sys/dev/e1000/e1000_phy.c

2058

ctrl |= E1000_CTRL_SPD_100;

sys/dev/e1000/e1000_phy.c

2063

ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);

sys/dev/e1000/e1000_phy.c

2070

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_phy.c

2865

u32 ctrl;

sys/dev/e1000/e1000_phy.c

2879

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_phy.c

2880

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);

sys/dev/e1000/e1000_phy.c

2885

E1000_WRITE_REG(hw, E1000_CTRL, ctrl);

sys/dev/e1000/e1000_vf.c

263

u32 ctrl, msgbuf[3];

sys/dev/e1000/e1000_vf.c

269

ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_vf.c

270

E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);

sys/dev/e1000/if_em.c

2221

u32 link_check, thstat, ctrl;

sys/dev/e1000/if_em.c

2224

link_check = thstat = ctrl = 0;

sys/dev/e1000/if_em.c

2261

ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/if_em.c

2284

if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==

sys/dev/e1000/if_em.c

4503

u32 ctrl, ctrl_ext, rctl;

sys/dev/e1000/if_em.c

4530

ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);

sys/dev/e1000/if_em.c

4531

ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);

sys/dev/e1000/if_em.c

4532

E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);

sys/dev/enic/enic_txrx.c

164

ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, head_idx);

sys/dev/enic/enic_txrx.c

297

ENIC_BUS_WRITE_4(rq->ctrl, RX_FETCH_INDEX, 0);

sys/dev/enic/enic_txrx.c

320

ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, pidx);

sys/dev/enic/enic_txrx.c

368

ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, rq->posted_index);

sys/dev/enic/if_enic.c

577

enic->intr[i].ctrl = vnic_dev_get_res(enic->vdev,

sys/dev/enic/if_enic.c

595

enic->intr[i].ctrl = vnic_dev_get_res(enic->vdev,

sys/dev/enic/if_enic.c

613

enic->intr[i].ctrl = vnic_dev_get_res(enic->vdev, RES_TYPE_INTR_CTRL,

sys/dev/enic/if_enic.c

629

enic->intr[i].ctrl = vnic_dev_get_res(enic->vdev, RES_TYPE_INTR_CTRL,

sys/dev/enic/if_enic.c

744

wq->ctrl = vnic_dev_get_res(softc->enic.vdev, RES_TYPE_WQ,

sys/dev/enic/if_enic.c

761

cq->ctrl = vnic_dev_get_res(softc->enic.vdev,

sys/dev/enic/if_enic.c

816

cq->ctrl = vnic_dev_get_res(softc->enic.vdev, RES_TYPE_CQ,

sys/dev/enic/if_enic.c

829

rq->ctrl = vnic_dev_get_res(softc->enic.vdev,

sys/dev/enic/vnic_cq.c

19

ENIC_BUS_WRITE_8(cq->ctrl, CQ_RING_BASE, paddr);

sys/dev/enic/vnic_cq.c

20

ENIC_BUS_WRITE_4(cq->ctrl, CQ_RING_SIZE, cq->ring.desc_count);

sys/dev/enic/vnic_cq.c

21

ENIC_BUS_WRITE_4(cq->ctrl, CQ_FLOW_CONTROL_ENABLE, flow_control_enable);

sys/dev/enic/vnic_cq.c

22

ENIC_BUS_WRITE_4(cq->ctrl, CQ_COLOR_ENABLE, color_enable);

sys/dev/enic/vnic_cq.c

23

ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, cq_head);

sys/dev/enic/vnic_cq.c

24

ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, cq_tail);

sys/dev/enic/vnic_cq.c

25

ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, cq_tail_color);

sys/dev/enic/vnic_cq.c

26

ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_ENABLE, interrupt_enable);

sys/dev/enic/vnic_cq.c

27

ENIC_BUS_WRITE_4(cq->ctrl, CQ_ENTRY_ENABLE, cq_entry_enable);

sys/dev/enic/vnic_cq.c

28

ENIC_BUS_WRITE_4(cq->ctrl, CQ_MESSAGE_ENABLE, cq_message_enable);

sys/dev/enic/vnic_cq.c

29

ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_OFFSET, interrupt_offset);

sys/dev/enic/vnic_cq.c

30

ENIC_BUS_WRITE_8(cq->ctrl, CQ_MESSAGE_ADDR, cq_message_addr);

sys/dev/enic/vnic_cq.c

40

ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, 0);

sys/dev/enic/vnic_cq.c

41

ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, 0);

sys/dev/enic/vnic_cq.c

42

ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, 1);

sys/dev/enic/vnic_cq.h

61

struct vnic_res *ctrl;

sys/dev/enic/vnic_dev.c

1054

vdev->devcmd2->wq_ctrl = vdev->devcmd2->wq.ctrl;

sys/dev/enic/vnic_dev.c

1057

fetch_index = ENIC_BUS_READ_4(vdev->devcmd2->wq.ctrl, TX_FETCH_INDEX);

sys/dev/enic/vnic_intr.c

12

intr->ctrl = NULL;

sys/dev/enic/vnic_intr.c

21

intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index);

sys/dev/enic/vnic_intr.c

22

if (!intr->ctrl) {

sys/dev/enic/vnic_intr.c

34

ENIC_BUS_WRITE_4(intr->ctrl, INTR_COALESCING_TYPE, coalescing_type);

sys/dev/enic/vnic_intr.c

35

ENIC_BUS_WRITE_4(intr->ctrl, INTR_MASK_ON_ASSERTION, mask_on_assertion);

sys/dev/enic/vnic_intr.c

36

ENIC_BUS_WRITE_4(intr->ctrl, INTR_CREDITS, 0);

sys/dev/enic/vnic_intr.c

42

ENIC_BUS_WRITE_4(intr->ctrl, INTR_COALESCING_TIMER,

sys/dev/enic/vnic_intr.c

48

ENIC_BUS_WRITE_4(intr->ctrl, INTR_CREDITS, 0);

sys/dev/enic/vnic_intr.h

43

struct vnic_res *ctrl;

sys/dev/enic/vnic_intr.h

48

ENIC_BUS_WRITE_4(intr->ctrl, INTR_MASK, 1);

sys/dev/enic/vnic_intr.h

55

ret = ENIC_BUS_READ_4(intr->ctrl, INTR_MASK);

sys/dev/enic/vnic_intr.h

61

ENIC_BUS_WRITE_4(intr->ctrl, INTR_MASK, 0);

sys/dev/enic/vnic_intr.h

74

ENIC_BUS_WRITE_4(intr->ctrl, INTR_CREDIT_RETURN, int_credit_return);

sys/dev/enic/vnic_intr.h

79

return (ENIC_BUS_READ_4(intr->ctrl, INTR_CREDITS));

sys/dev/enic/vnic_rq.c

19

ENIC_BUS_WRITE_8(rq->ctrl, RX_RING_BASE, paddr);

sys/dev/enic/vnic_rq.c

20

ENIC_BUS_WRITE_4(rq->ctrl, RX_RING_SIZE, count);

sys/dev/enic/vnic_rq.c

21

ENIC_BUS_WRITE_4(rq->ctrl, RX_CQ_INDEX, cq_index);

sys/dev/enic/vnic_rq.c

22

ENIC_BUS_WRITE_4(rq->ctrl, RX_ERROR_INTR_ENABLE, error_interrupt_enable);

sys/dev/enic/vnic_rq.c

23

ENIC_BUS_WRITE_4(rq->ctrl, RX_ERROR_INTR_OFFSET, error_interrupt_offset);

sys/dev/enic/vnic_rq.c

24

ENIC_BUS_WRITE_4(rq->ctrl, RX_ERROR_STATUS, 0);

sys/dev/enic/vnic_rq.c

25

ENIC_BUS_WRITE_4(rq->ctrl, RX_FETCH_INDEX, fetch_index);

sys/dev/enic/vnic_rq.c

26

ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, posted_index);

sys/dev/enic/vnic_rq.c

36

fetch_index = ENIC_BUS_READ_4(rq->ctrl, RX_FETCH_INDEX);

sys/dev/enic/vnic_rq.c

54

return (ENIC_BUS_READ_4(rq->ctrl, RX_ERROR_STATUS));

sys/dev/enic/vnic_rq.c

59

ENIC_BUS_WRITE_4(rq->ctrl, RX_ENABLE, 1);

sys/dev/enic/vnic_rq.c

66

ENIC_BUS_WRITE_4(rq->ctrl, RX_ENABLE, 0);

sys/dev/enic/vnic_rq.c

70

if (!(ENIC_BUS_READ_4(rq->ctrl, RX_RUNNING)))

sys/dev/enic/vnic_rq.c

89

fetch_index = ENIC_BUS_READ_4(rq->ctrl, RX_FETCH_INDEX);

sys/dev/enic/vnic_rq.c

95

ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, fetch_index);

sys/dev/enic/vnic_rq.h

61

struct vnic_res *ctrl;

sys/dev/enic/vnic_wq.c

115

ENIC_BUS_WRITE_8(wq->ctrl, TX_RING_BASE, paddr);

sys/dev/enic/vnic_wq.c

116

ENIC_BUS_WRITE_4(wq->ctrl, TX_RING_SIZE, count);

sys/dev/enic/vnic_wq.c

117

ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, fetch_index);

sys/dev/enic/vnic_wq.c

118

ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, posted_index);

sys/dev/enic/vnic_wq.c

119

ENIC_BUS_WRITE_4(wq->ctrl, TX_CQ_INDEX, cq_index);

sys/dev/enic/vnic_wq.c

120

ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_ENABLE, error_interrupt_enable);

sys/dev/enic/vnic_wq.c

121

ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_OFFSET, error_interrupt_offset);

sys/dev/enic/vnic_wq.c

122

ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0);

sys/dev/enic/vnic_wq.c

141

return (ENIC_BUS_READ_4(wq->ctrl, TX_ERROR_STATUS));

sys/dev/enic/vnic_wq.c

146

ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 1);

sys/dev/enic/vnic_wq.c

153

ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 0);

sys/dev/enic/vnic_wq.c

157

if (!(ENIC_BUS_READ_4(wq->ctrl, TX_RUNNING)))

sys/dev/enic/vnic_wq.c

180

ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, 0);

sys/dev/enic/vnic_wq.c

181

ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, 0);

sys/dev/enic/vnic_wq.c

182

ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0);

sys/dev/enic/vnic_wq.c

64

wq->ctrl = NULL;

sys/dev/enic/vnic_wq.c

76

wq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);

sys/dev/enic/vnic_wq.c

77

if (!wq->ctrl)

sys/dev/enic/vnic_wq.h

52

struct vnic_res *ctrl;

sys/dev/et/if_et.c

498

uint32_t cfg1, cfg2, ctrl;

sys/dev/et/if_et.c

529

ctrl = CSR_READ_4(sc, ET_MAC_CTRL);

sys/dev/et/if_et.c

530

ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);

sys/dev/et/if_et.c

545

ctrl |= ET_MAC_CTRL_MODE_MII;

sys/dev/et/if_et.c

568

ctrl |= ET_MAC_CTRL_GHDX;

sys/dev/et/if_et.c

570

CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);

sys/dev/etherswitch/arswitch/arswitch_phy.c

114

uint32_t data = 0, ctrl;

sys/dev/etherswitch/arswitch/arswitch_phy.c

141

ctrl = arswitch_readreg_msb(dev, a);

sys/dev/etherswitch/arswitch/arswitch_phy.c

142

if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)

sys/dev/etherswitch/arswitch/arswitch_phy.c

175

uint32_t ctrl;

sys/dev/etherswitch/arswitch/arswitch_phy.c

201

ctrl = arswitch_readreg(dev, a);

sys/dev/etherswitch/arswitch/arswitch_phy.c

202

if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)

sys/dev/igc/if_igc.c

1391

u32 link_check, thstat, ctrl;

sys/dev/igc/if_igc.c

1393

link_check = thstat = ctrl = 0;

sys/dev/igc/if_igc.c

2453

u32 ctrl, rctl;

sys/dev/igc/if_igc.c

2480

ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL);

sys/dev/igc/if_igc.c

2481

ctrl |= IGC_CTRL_ADVD3WUC;

sys/dev/igc/if_igc.c

2482

IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl);

sys/dev/igc/igc_i225.c

184

u32 ctrl;

sys/dev/igc/igc_i225.c

206

ctrl = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/igc_i225.c

209

IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);

sys/dev/igc/igc_i225.c

348

u32 ctrl;

sys/dev/igc/igc_i225.c

352

ctrl = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/igc_i225.c

353

ctrl |= IGC_CTRL_SLU;

sys/dev/igc/igc_i225.c

354

ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);

sys/dev/igc/igc_i225.c

355

IGC_WRITE_REG(hw, IGC_CTRL, ctrl);

sys/dev/igc/igc_mac.c

1025

u32 ctrl;

sys/dev/igc/igc_mac.c

1030

ctrl = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/igc_mac.c

1031

ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;

sys/dev/igc/igc_mac.c

1032

IGC_WRITE_REG(hw, IGC_CTRL, ctrl);

sys/dev/igc/igc_mac.c

645

u32 ctrl;

sys/dev/igc/igc_mac.c

649

ctrl = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/igc_mac.c

672

ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));

sys/dev/igc/igc_mac.c

675

ctrl &= (~IGC_CTRL_TFCE);

sys/dev/igc/igc_mac.c

676

ctrl |= IGC_CTRL_RFCE;

sys/dev/igc/igc_mac.c

679

ctrl &= (~IGC_CTRL_RFCE);

sys/dev/igc/igc_mac.c

680

ctrl |= IGC_CTRL_TFCE;

sys/dev/igc/igc_mac.c

683

ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);

sys/dev/igc/igc_mac.c

690

IGC_WRITE_REG(hw, IGC_CTRL, ctrl);

sys/dev/igc/igc_phy.c

594

u32 ctrl;

sys/dev/igc/igc_phy.c

602

ctrl = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/igc_phy.c

603

ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);

sys/dev/igc/igc_phy.c

604

ctrl &= ~IGC_CTRL_SPD_SEL;

sys/dev/igc/igc_phy.c

607

ctrl &= ~IGC_CTRL_ASDE;

sys/dev/igc/igc_phy.c

614

ctrl &= ~IGC_CTRL_FD;

sys/dev/igc/igc_phy.c

618

ctrl |= IGC_CTRL_FD;

sys/dev/igc/igc_phy.c

625

ctrl |= IGC_CTRL_SPD_100;

sys/dev/igc/igc_phy.c

630

ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);

sys/dev/igc/igc_phy.c

637

IGC_WRITE_REG(hw, IGC_CTRL, ctrl);

sys/dev/igc/igc_phy.c

857

u32 ctrl, timeout = 10000, phpm = 0;

sys/dev/igc/igc_phy.c

873

ctrl = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/igc_phy.c

874

IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);

sys/dev/igc/igc_phy.c

879

IGC_WRITE_REG(hw, IGC_CTRL, ctrl);

sys/dev/iicbus/pmic/rockchip/rk805.c

171

sc->rtc_regs.ctrl = RK805_RTC_CTRL;

sys/dev/iicbus/pmic/rockchip/rk808.c

246

sc->rtc_regs.ctrl = RK808_RTC_CTRL;

sys/dev/iicbus/pmic/rockchip/rk817.c

502

sc->rtc_regs.ctrl = RK817_RTC_CTRL;

sys/dev/iicbus/pmic/rockchip/rk8xx.h

86

uint8_t ctrl;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

112

uint8_t ctrl;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

138

error = rk8xx_read(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

142

ctrl |= sc->rtc_regs.ctrl_stop_mask;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

143

ctrl &= ~sc->rtc_regs.ctrl_ampm_mask;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

144

error = rk8xx_write(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

149

ctrl &= ~sc->rtc_regs.ctrl_stop_mask;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

150

rk8xx_write(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

42

uint8_t ctrl;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

48

error = rk8xx_read(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

52

ctrl |= sc->rtc_regs.ctrl_readsel_mask;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

53

ctrl &= ~(sc->rtc_regs.ctrl_ampm_mask | sc->rtc_regs.ctrl_gettime_mask);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

54

error = rk8xx_write(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

57

ctrl |= sc->rtc_regs.ctrl_gettime_mask;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

58

error = rk8xx_write(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

65

ctrl &= ~sc->rtc_regs.ctrl_gettime_mask;

sys/dev/iicbus/pmic/rockchip/rk8xx_rtc.c

66

error = rk8xx_write(dev, sc->rtc_regs.ctrl, &ctrl, 1);

sys/dev/iicbus/rtc/ds1307.c

118

uint8_t ctrl;

sys/dev/iicbus/rtc/ds1307.c

120

ctrl = sc->sc_ctrl & DS1307_CTRL_MASK;

sys/dev/iicbus/rtc/ds1307.c

121

error = ds1307_write1(sc->sc_dev, DS1307_CONTROL, ctrl);

sys/dev/iicbus/rtc/ds1672.c

100

uint8_t ctrl;

sys/dev/iicbus/rtc/ds1672.c

103

error = ds1672_read(dev, DS1672_CTRL, &ctrl, 1);

sys/dev/iicbus/rtc/ds1672.c

110

if (ctrl & DS1672_CTRL_EOSC) {

sys/dev/iicbus/rtc/ds1672.c

113

ctrl &= ~DS1672_CTRL_EOSC; /* Start oscillator. */

sys/dev/iicbus/rtc/ds1672.c

114

error = ds1672_write(dev, DS1672_CTRL, &ctrl, 1);

sys/dev/ixgbe/if_ix.c

2350

u32 ctrl;

sys/dev/ixgbe/if_ix.c

2366

ctrl = IXGBE_READ_REG(hw,

sys/dev/ixgbe/if_ix.c

2368

ctrl &= ~IXGBE_RXDCTL_VME;

sys/dev/ixgbe/if_ix.c

2370

ctrl);

sys/dev/ixgbe/if_ix.c

2374

ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);

sys/dev/ixgbe/if_ix.c

2376

ctrl |= IXGBE_VLNCTRL_CFIEN;

sys/dev/ixgbe/if_ix.c

2377

ctrl &= ~IXGBE_VLNCTRL_VFE;

sys/dev/ixgbe/if_ix.c

2379

ctrl &= ~IXGBE_VLNCTRL_VME;

sys/dev/ixgbe/if_ix.c

2380

IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);

sys/dev/ixgbe/if_ix.c

2390

ctrl = IXGBE_READ_REG(hw,

sys/dev/ixgbe/if_ix.c

2392

ctrl |= IXGBE_RXDCTL_VME;

sys/dev/ixgbe/if_ix.c

2394

ctrl);

sys/dev/ixgbe/if_ix.c

2411

ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);

sys/dev/ixgbe/if_ix.c

2414

ctrl &= ~IXGBE_VLNCTRL_CFIEN;

sys/dev/ixgbe/if_ix.c

2415

ctrl |= IXGBE_VLNCTRL_VFE;

sys/dev/ixgbe/if_ix.c

2418

ctrl |= IXGBE_VLNCTRL_VME;

sys/dev/ixgbe/if_ix.c

2419

IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);

sys/dev/ixgbe/if_ixv.c

1528

u32 ctrl, vid, vfta, retry;

sys/dev/ixgbe/if_ixv.c

1542

ctrl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));

sys/dev/ixgbe/if_ixv.c

1543

ctrl |= IXGBE_RXDCTL_VME;

sys/dev/ixgbe/if_ixv.c

1544

IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), ctrl);

sys/dev/ixgbe/ixgbe_82598.c

814

u32 ctrl;

sys/dev/ixgbe/ixgbe_82598.c

879

ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;

sys/dev/ixgbe/ixgbe_82598.c

880

IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);

sys/dev/ixgbe/ixgbe_82598.c

886

ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_82598.c

887

if (!(ctrl & IXGBE_CTRL_RST))

sys/dev/ixgbe/ixgbe_82598.c

890

if (ctrl & IXGBE_CTRL_RST) {

sys/dev/ixgbe/ixgbe_82599.c

1059

u32 ctrl = 0;

sys/dev/ixgbe/ixgbe_82599.c

1105

ctrl = IXGBE_CTRL_LNK_RST;

sys/dev/ixgbe/ixgbe_82599.c

1109

ctrl = IXGBE_CTRL_RST;

sys/dev/ixgbe/ixgbe_82599.c

1112

ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_82599.c

1113

IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);

sys/dev/ixgbe/ixgbe_82599.c

1119

ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_82599.c

1120

if (!(ctrl & IXGBE_CTRL_RST_MASK))

sys/dev/ixgbe/ixgbe_82599.c

1124

if (ctrl & IXGBE_CTRL_RST_MASK) {

sys/dev/ixgbe/ixgbe_common.c

5287

s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,

sys/dev/ixgbe/ixgbe_common.c

5295

cmd = ctrl; /* just reading only need control number */

sys/dev/ixgbe/ixgbe_common.h

172

s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,

sys/dev/ixgbe/ixgbe_e610.c

4429

u32 ctrl, i;

sys/dev/ixgbe/ixgbe_e610.c

4453

ctrl = IXGBE_CTRL_RST;

sys/dev/ixgbe/ixgbe_e610.c

4454

ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_e610.c

4455

IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);

sys/dev/ixgbe/ixgbe_e610.c

4462

ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_e610.c

4463

if (!(ctrl & IXGBE_CTRL_RST_MASK))

sys/dev/ixgbe/ixgbe_e610.c

4467

if (ctrl & IXGBE_CTRL_RST_MASK) {

sys/dev/ixgbe/ixgbe_phy.c

497

u16 ctrl = 0;

sys/dev/ixgbe/ixgbe_phy.c

536

&ctrl);

sys/dev/ixgbe/ixgbe_phy.c

540

if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {

sys/dev/ixgbe/ixgbe_phy.c

548

&ctrl);

sys/dev/ixgbe/ixgbe_phy.c

552

if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {

sys/dev/ixgbe/ixgbe_phy.c

559

if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {

sys/dev/ixgbe/ixgbe_x540.c

217

u32 ctrl, i;

sys/dev/ixgbe/ixgbe_x540.c

237

ctrl = IXGBE_CTRL_RST;

sys/dev/ixgbe/ixgbe_x540.c

238

ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_x540.c

239

IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);

sys/dev/ixgbe/ixgbe_x540.c

246

ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_x540.c

247

if (!(ctrl & IXGBE_CTRL_RST_MASK))

sys/dev/ixgbe/ixgbe_x540.c

251

if (ctrl & IXGBE_CTRL_RST_MASK) {

sys/dev/ixgbe/ixgbe_x550.c

1098

static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)

sys/dev/ixgbe/ixgbe_x550.c

1112

if (ctrl)

sys/dev/ixgbe/ixgbe_x550.c

1113

*ctrl = command;

sys/dev/ixgbe/ixgbe_x550.c

2371

u32 ctrl = 0;

sys/dev/ixgbe/ixgbe_x550.c

2433

ctrl = IXGBE_CTRL_LNK_RST;

sys/dev/ixgbe/ixgbe_x550.c

2437

ctrl = IXGBE_CTRL_RST;

sys/dev/ixgbe/ixgbe_x550.c

2446

ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_x550.c

2447

IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);

sys/dev/ixgbe/ixgbe_x550.c

2454

ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);

sys/dev/ixgbe/ixgbe_x550.c

2455

if (!(ctrl & IXGBE_CTRL_RST_MASK))

sys/dev/ixgbe/ixgbe_x550.c

2459

if (ctrl & IXGBE_CTRL_RST_MASK) {

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

773

static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

778

flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

779

flags |= ctrl->exclusive ? (1 << 2) : 0;

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

780

flags |= ctrl->allow_loopback ? (1 << 3) : 0;

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

783

hw->type = __promisc_mode[ctrl->promisc_mode];

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

784

hw->prio = cpu_to_be16(ctrl->priority);

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

785

hw->port = ctrl->port;

sys/dev/mlx4/mlx4_core/mlx4_mcg.c

786

hw->qpn = cpu_to_be32(ctrl->qpn);

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4166

static void handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4178

ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4192

struct mlx4_net_trans_rule_hw_ctrl *ctrl;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4199

ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4200

port = ctrl->port;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4201

eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4339

struct mlx4_net_trans_rule_hw_ctrl *ctrl;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4349

ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4350

err = mlx4_slave_convert_port(dev, slave, ctrl->port);

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4353

ctrl->port = err;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4354

qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4360

rule_header = (struct _rule_hw *)(ctrl + 1);

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4364

handle_eth_header_mcast_prio(ctrl, rule_header);

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4425

ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4426

if (ctrl->port == 1)

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4427

ctrl->port = 2;

sys/dev/mlx4/mlx4_core/mlx4_resource_tracker.c

4429

ctrl->port = 1;

sys/dev/mlx4/mlx4_en/en.h

254

struct mlx4_wqe_ctrl_seg ctrl;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

695

tx_desc->ctrl.srcrb_flags = CTRL_FLAGS;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

698

tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

702

tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM);

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

705

if (likely(tx_desc->ctrl.srcrb_flags != CTRL_FLAGS)) {

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

712

tx_desc->ctrl.vlan_tag = cpu_to_be16(mb->m_pkthdr.ether_vtag);

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

713

tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

715

tx_desc->ctrl.vlan_tag = 0;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

716

tx_desc->ctrl.ins_vlan = 0;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

725

m_copydata(mb, 0, 2, __DEVOLATILE(void *, &tx_desc->ctrl.srcrb_flags16[0]));

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

726

m_copydata(mb, 2, 4, __DEVOLATILE(void *, &tx_desc->ctrl.imm));

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

729

tx_desc->ctrl.imm = 0;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

842

tx_desc->ctrl.fence_size = (ds_cnt & 0x3f);

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

891

(tx_desc->ctrl.ins_vlan != MLX4_WQE_CTRL_INS_CVLAN)) {

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

894

*(volatile __be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

904

tx_desc->ctrl.owner_opcode = opcode;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

907

(volatile unsigned long *) &tx_desc->ctrl, bf_size);

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

916

tx_desc->ctrl.owner_opcode = opcode;

sys/dev/mlx4/mlx4_ib/mlx4_ib_main.c

1479

struct mlx4_net_trans_rule_hw_ctrl *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_main.c

1505

ctrl = mailbox->buf;

sys/dev/mlx4/mlx4_ib/mlx4_ib_main.c

1507

ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |

sys/dev/mlx4/mlx4_ib/mlx4_ib_main.c

1509

ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);

sys/dev/mlx4/mlx4_ib/mlx4_ib_main.c

1510

ctrl->port = flow_attr->port;

sys/dev/mlx4/mlx4_ib/mlx4_ib_main.c

1511

ctrl->qpn = cpu_to_be32(qp->qp_num);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

1998

struct mlx4_wqe_ctrl_seg *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2002

ctrl = get_send_wqe(qp, i);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2003

ctrl->owner_opcode = cpu_to_be32(1U << 31);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2005

ctrl->fence_size =

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

224

struct mlx4_wqe_ctrl_seg *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

237

ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

238

s = (ctrl->fence_size & 0x3f) << 4;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2432

struct mlx4_wqe_ctrl_seg *ctrl = wqe;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

248

struct mlx4_wqe_ctrl_seg *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

253

ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

257

struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2597

memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2598

memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

269

ctrl->srcrb_flags = 0;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

270

ctrl->fence_size = size / 16;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

277

ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

2936

struct mlx4_wqe_ctrl_seg *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3001

ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3004

ctrl->srcrb_flags =

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3014

ctrl->imm = send_ieth(wr);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3016

wqe += sizeof *ctrl;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3017

size = sizeof *ctrl / 16;

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3061

ctrl->srcrb_flags |=

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3069

ctrl->srcrb_flags |=

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3084

ctrl, &seglen);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3121

ctrl, &seglen);

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3154

err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3199

ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?

sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c

3215

ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

232

static void mlx5e_ipsec_aso_copy(struct mlx5_wqe_aso_ctrl_seg *ctrl,

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

238

ctrl->data_mask_mode = data->data_mask_mode;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

239

ctrl->condition_1_0_operand = data->condition_1_0_operand;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

240

ctrl->condition_1_0_offset = data->condition_1_0_offset;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

241

ctrl->data_offset_condition_operand = data->data_offset_condition_operand;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

242

ctrl->condition_0_data = data->condition_0_data;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

243

ctrl->condition_0_mask = data->condition_0_mask;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

244

ctrl->condition_1_data = data->condition_1_data;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

245

ctrl->condition_1_mask = data->condition_1_mask;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

246

ctrl->bitwise_data = data->bitwise_data;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

247

ctrl->data_mask = data->data_mask;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

255

struct mlx5_wqe_aso_ctrl_seg *ctrl;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

268

ctrl = &wqe->aso_ctrl;

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

269

ctrl->va_l = cpu_to_be32(lower_32_bits(aso->dma_addr) | ASO_CTRL_READ_EN);

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

270

ctrl->va_h = cpu_to_be32(upper_32_bits(aso->dma_addr));

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

271

ctrl->l_key = cpu_to_be32(ipsec->mkey);

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

272

mlx5e_ipsec_aso_copy(ctrl, data);

sys/dev/mlx5/mlx5_accel/mlx5_ipsec_offload.c

274

mlx5_aso_post_wqe(aso->aso, false, &wqe->ctrl);

sys/dev/mlx5/mlx5_en/en.h

1158

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_en/en.h

1163

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_en/en.h

1169

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_en/en.h

1174

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

617

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) |

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

619

wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

620

wqe->ctrl.imm = cpu_to_be32(ptag->tisn << 8);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

623

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE | MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

625

wqe->ctrl.fm_ce_se = MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

636

memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

662

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) |

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

664

wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

667

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

674

memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

694

memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

696

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

697

wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

699

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE | MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

701

wqe->ctrl.fm_ce_se = MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c

704

memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

172

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((iq->pc << 8) |

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

174

wqe->ctrl.qpn_ds = cpu_to_be32((iq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

175

wqe->ctrl.imm = cpu_to_be32(ptag->tirn << 8);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

176

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE | MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

188

memcpy(iq->doorbell.d32, &wqe->ctrl, sizeof(iq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

245

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((iq->pc << 8) |

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

247

wqe->ctrl.qpn_ds = cpu_to_be32((iq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

248

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

255

memcpy(iq->doorbell.d32, &wqe->ctrl, sizeof(iq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

286

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

376

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((iq->pc << 8) |

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

378

wqe->ctrl.qpn_ds = cpu_to_be32((iq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

379

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c

386

memcpy(iq->doorbell.d32, &wqe->ctrl, sizeof(iq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_iq.c

111

memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));

sys/dev/mlx5/mlx5_en/mlx5_en_iq.c

113

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((iq->pc << 8) | MLX5_OPCODE_NOP);

sys/dev/mlx5/mlx5_en/mlx5_en_iq.c

114

wqe->ctrl.qpn_ds = cpu_to_be32((iq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_iq.c

115

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_iq.c

118

memcpy(iq->doorbell.d32, &wqe->ctrl, sizeof(iq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_rl.c

446

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((iq->pc << 8) |

sys/dev/mlx5/mlx5_en/mlx5_en_rl.c

448

wqe->ctrl.qpn_ds = cpu_to_be32((iq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_rl.c

449

wqe->ctrl.imm = cpu_to_be32(iq->priv->tisn[0] << 8);

sys/dev/mlx5/mlx5_en/mlx5_en_rl.c

450

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE | MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_rl.c

453

memcpy(iq->doorbell.d32, &wqe->ctrl, sizeof(iq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

541

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

60

memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

62

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

63

wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

630

memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

633

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

634

wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

635

wqe->ctrl.imm = cpu_to_be32(parg->tisn << 8);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

65

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

657

wqe->ctrl.fm_ce_se |= MLX5_FENCE_MODE_INITIATOR_SMALL;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

661

wqe_last->ctrl.fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

67

wqe->ctrl.fm_ce_se = 0;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

70

memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

942

dseg = ((struct mlx5_wqe_data_seg *)&wqe->ctrl) + ds_cnt;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

983

ds_cnt = (dseg - ((struct mlx5_wqe_data_seg *)&wqe->ctrl));

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

985

wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

986

wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

987

wqe->ctrl.imm = cpu_to_be32(args.tisn << 8);

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

990

wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

992

wqe->ctrl.fm_ce_se = 0;

sys/dev/mlx5/mlx5_en/mlx5_en_tx.c

995

memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

142

struct mlx5_wqe_ctrl_seg *ctrl;

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

149

ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

150

data = (void *)(ctrl + 1);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

162

ctrl->imm = 0;

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

163

ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

164

ctrl->opmod_idx_opcode = cpu_to_be32(((conn->qp.sq.pc & 0xffff) << 8) |

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

166

ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.mqp.qpn << 8));

sys/dev/mlx5/mlx5_fpga/mlx5fpga_conn.c

170

mlx5_fpga_conn_notify_hw(conn, ctrl);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

168

struct mlx5_wqe_ctrl_seg *ctrl = buffer;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

169

int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3848

struct mlx5_wqe_ctrl_seg **ctrl,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3857

*ctrl = *seg;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3859

(*ctrl)->imm = send_ieth(wr);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3860

(*ctrl)->fm_ce_se = qp->sq_signal_bits |

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3866

*seg += sizeof(**ctrl);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3867

*size = sizeof(**ctrl) / 16;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3873

struct mlx5_wqe_ctrl_seg *ctrl,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3880

ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3882

ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3883

ctrl->fm_ce_se |= fence;

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3886

ctrl->signature = wq_sig(ctrl);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3899

struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3952

err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq, wr->send_flags);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3988

ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

3996

ctrl->imm = cpu_to_be32(reg_wr(wr)->key);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4009

ctrl->imm = cpu_to_be32(mr->ibmr.rkey);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4017

finish_wqe(qp, ctrl, size, idx, wr->wr_id,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4024

err = begin_wqe(qp, &seg, &ctrl, wr,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4042

finish_wqe(qp, ctrl, size, idx, wr->wr_id,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4045

err = begin_wqe(qp, &seg, &ctrl, wr,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4064

finish_wqe(qp, ctrl, size, idx, wr->wr_id,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4128

ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4170

finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

4193

mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset,

sys/dev/mlx5/mlx5_lib/aso.h

40

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_lib/aso.h

45

struct mlx5_wqe_ctrl_seg ctrl;

sys/dev/mlx5/mlx5_lib/mlx5_aso.c

342

struct mlx5_wqe_ctrl_seg *cseg = &aso_wqe->ctrl;

sys/dev/oce/oce_hw.c

446

mpu_ep_control_t ctrl;

sys/dev/oce/oce_hw.c

448

ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);

sys/dev/oce/oce_hw.c

449

ctrl.bits.cpu_reset = 1;

sys/dev/oce/oce_hw.c

450

OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);

sys/dev/ocs_fc/ocs_hw.c

2623

ocs_hw_port_control(ocs_hw_t *hw, ocs_hw_port_e ctrl, uintptr_t value, ocs_hw_port_control_cb_t cb, void *arg)

sys/dev/ocs_fc/ocs_hw.c

2627

switch (ctrl) {

sys/dev/ocs_fc/ocs_hw.c

2718

ocs_log_test(hw->os, "unhandled control %#x\n", ctrl);

sys/dev/pccbb/pccbb.c

841

uint32_t ctrl;

sys/dev/pccbb/pccbb.c

843

ctrl = cbb_get(sc, CBB_SOCKET_CONTROL);

sys/dev/pccbb/pccbb.c

844

switch (ctrl & CBB_SOCKET_CTRL_VCCMASK) {

sys/dev/pci/pci.c

1836

uint16_t ctrl, msgnum;

sys/dev/pci/pci.c

1875

ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,

sys/dev/pci/pci.c

1877

msgnum = PCI_MSIX_MSGNUM(ctrl);

sys/dev/pci/pci.c

1945

cfg->msix.msix_ctrl = ctrl;

sys/dev/pci/pci.c

1961

ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;

sys/dev/pci/pci.c

1963

ctrl, 2);

sys/dev/pci/pci.c

1964

cfg->msix.msix_ctrl = ctrl;

sys/dev/pci/pci.c

2193

uint16_t ctrl;

sys/dev/pci/pci.c

2196

ctrl = pci_read_config(child, msix->msix_location +

sys/dev/pci/pci.c

2198

return (PCI_MSIX_MSGNUM(ctrl));

sys/dev/pci/pci.c

2634

uint16_t ctrl, msgnum;

sys/dev/pci/pci.c

2657

ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2);

sys/dev/pci/pci.c

2658

msgnum = PCI_MSI_MSGNUM(ctrl);

sys/dev/pci/pci.c

2734

ctrl &= ~PCIM_MSICTRL_MME_MASK;

sys/dev/pci/pci.c

2735

ctrl |= (ffs(actual) - 1) << 4;

sys/dev/pci/pci.c

2736

cfg->msi.msi_ctrl = ctrl;

sys/dev/pci/pci.c

2737

pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);

sys/dev/pci/pci.c

2807

uint16_t ctrl;

sys/dev/pci/pci.c

2810

ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL,

sys/dev/pci/pci.c

2812

return (PCI_MSI_MSGNUM(ctrl));

sys/dev/pci/pci.c

3115

uint16_t ctrl, msgnum;

sys/dev/pci/pci.c

3117

ctrl = cfg->msi.msi_ctrl;

sys/dev/pci/pci.c

3118

msgnum = PCI_MSI_MSGNUM(ctrl);

sys/dev/pci/pci.c

3121

(ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",

sys/dev/pci/pci.c

3122

(ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");

sys/dev/pci/pcireg.h

619

#define PCI_MSI_MSGNUM(ctrl) \

sys/dev/pci/pcireg.h

620

(1 << (((ctrl) & PCIM_MSICTRL_MMC_MASK) >> 1))

sys/dev/pci/pcireg.h

970

#define PCI_MSIX_MSGNUM(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)

sys/dev/qlnx/qlnxe/ecore_dev.c

3484

u16 ctrl;

sys/dev/qlnx/qlnxe/ecore_dev.c

3561

OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);

sys/dev/qlnx/qlnxe/ecore_dev.c

3564

ctrl |= PCI_EXP_DEVCTL_RELAX_EN;

sys/dev/qlnx/qlnxe/ecore_dev.c

3566

pos + PCI_EXP_DEVCTL, ctrl);

sys/dev/qlnx/qlnxe/ecore_dev.c

3568

ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;

sys/dev/qlnx/qlnxe/ecore_dev.c

3570

pos + PCI_EXP_DEVCTL, ctrl);

sys/dev/qlnx/qlnxe/ecore_dev.c

3574

ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;

sys/dev/qlnx/qlnxe/ecore_dev.c

3576

pos + PCI_EXP_DEVCTL, ctrl);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1024

u32 ctrl, inc_val, reg_offset;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1028

ctrl = NIG_RL_BASE_TYPE << NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1029

ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1040

ctrl |= 1 << NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1041

ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1045

ctrl = NIG_RL_BASE_TYPE << NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1046

ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1057

ctrl |= 1 << NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1058

ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1064

ctrl = NIG_RL_BASE_TYPE << NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1065

ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1078

ctrl |= 1 << NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1079

ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);

sys/dev/qlnx/qlnxe/ecore_iov_api.h

165

u16 ctrl; /* SR-IOV Control */

sys/dev/qlnx/qlnxe/ecore_sriov.c

406

&iov->ctrl);

sys/dev/qlnx/qlnxe/ecore_sriov.c

453

iov->nres, iov->cap, iov->ctrl,

sys/dev/sound/macio/i2s.c

136

int ctrl;

sys/dev/sound/macio/i2s.c

278

enum gpio_ctrl ctrl;

sys/dev/sound/macio/i2s.c

333

gpio_ctrls[m->ctrl] = sc;

sys/dev/sound/macio/i2s.c

335

sc->ctrl = m->ctrl;

sys/dev/sound/macio/i2s.c

343

if ((1 << m->ctrl) & GPIO_CTRL_EXTINT_SET)

sys/dev/sound/macio/i2s.c

365

if ((1 << sc->ctrl) & GPIO_CTRL_EXTINT_SET) {

sys/dev/sound/macio/i2s.c

596

gpio_read(enum gpio_ctrl ctrl)

sys/dev/sound/macio/i2s.c

600

if ((sc = gpio_ctrls[ctrl]) == NULL)

sys/dev/sound/macio/i2s.c

607

gpio_write(enum gpio_ctrl ctrl, u_int x)

sys/dev/sound/macio/i2s.c

612

if ((sc = gpio_ctrls[ctrl]) == NULL)

sys/dev/sound/pci/envy24.c

823

i2c_wrbit(void *codec, void (*ctrl)(void*, unsigned int, unsigned int), int bit)

sys/dev/sound/pci/envy24.c

833

ctrl(ptr, 0, sda);

sys/dev/sound/pci/envy24.c

835

ctrl(ptr, 1, sda);

sys/dev/sound/pci/envy24.c

837

ctrl(ptr, 0, sda);

sys/dev/sound/pci/envy24.c

842

i2c_start(void *codec, void (*ctrl)(void*, unsigned int, unsigned int))

sys/dev/sound/pci/envy24.c

846

ctrl(ptr, 1, 1);

sys/dev/sound/pci/envy24.c

848

ctrl(ptr, 1, 0);

sys/dev/sound/pci/envy24.c

850

ctrl(ptr, 0, 0);

sys/dev/sound/pci/envy24.c

855

i2c_stop(void *codec, void (*ctrl)(void*, unsigned int, unsigned int))

sys/dev/sound/pci/envy24.c

859

ctrl(ptr, 0, 0);

sys/dev/sound/pci/envy24.c

861

ctrl(ptr, 1, 0);

sys/dev/sound/pci/envy24.c

863

ctrl(ptr, 1, 1);

sys/dev/sound/pci/envy24.c

868

i2c_ack(void *codec, void (*ctrl)(void*, unsigned int, unsigned int))

sys/dev/sound/pci/envy24.c

872

ctrl(ptr, 0, 1);

sys/dev/sound/pci/envy24.c

874

ctrl(ptr, 1, 1);

sys/dev/sound/pci/envy24.c

877

ctrl(ptr, 0, 1);

sys/dev/sound/pci/envy24.c

882

i2c_wr(void *codec, void (*ctrl)(void*, unsigned int, unsigned int), u_int32_t dev, int reg, u_int8_t val)

sys/dev/sound/pci/envy24.c

887

i2c_start(ptr, ctrl);

sys/dev/sound/pci/envy24.c

890

i2c_wrbit(ptr, ctrl, dev & mask);

sys/dev/sound/pci/envy24.c

891

i2c_ack(ptr, ctrl);

sys/dev/sound/pci/envy24.c

895

i2c_wrbit(ptr, ctrl, reg & mask);

sys/dev/sound/pci/envy24.c

896

i2c_ack(ptr, ctrl);

sys/dev/sound/pci/envy24.c

900

i2c_wrbit(ptr, ctrl, val & mask);

sys/dev/sound/pci/envy24.c

901

i2c_ack(ptr, ctrl);

sys/dev/sound/pci/envy24.c

903

i2c_stop(ptr, ctrl);

sys/dev/sound/pci/es137x.c

1044

es->ctrl = 0;

sys/dev/sound/pci/es137x.c

1047

es->ctrl = CTRL_JYSTK_EN;

sys/dev/sound/pci/es137x.c

1052

es->ctrl |= (1 << 16);

sys/dev/sound/pci/es137x.c

1055

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/es137x.c

1068

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/es137x.c

1418

es->ctrl |= SPDIFEN_B;

sys/dev/sound/pci/es137x.c

1419

es->ctrl |= RECEN_B;

sys/dev/sound/pci/es137x.c

1422

es->ctrl &= ~SPDIFEN_B;

sys/dev/sound/pci/es137x.c

1423

es->ctrl &= ~RECEN_B;

sys/dev/sound/pci/es137x.c

1425

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/es137x.c

1482

if (es->ctrl & (CTRL_DAC2_EN|CTRL_ADC_EN)) {

sys/dev/sound/pci/es137x.c

1493

es->ctrl &= ~CTRL_PCLKDIV;

sys/dev/sound/pci/es137x.c

1494

es->ctrl |= DAC2_SRTODIV(val) << CTRL_SH_PCLKDIV;

sys/dev/sound/pci/es137x.c

1495

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/es137x.c

1551

if (es->ctrl & (CTRL_ADC_EN | CTRL_DAC1_EN | CTRL_DAC2_EN)) {

sys/dev/sound/pci/es137x.c

223

uint32_t ctrl;

sys/dev/sound/pci/es137x.c

589

es->ctrl &= ~CTRL_WTSRSEL;

sys/dev/sound/pci/es137x.c

592

es->ctrl |= 0 << CTRL_SH_WTSRSEL;

sys/dev/sound/pci/es137x.c

595

es->ctrl |= 1 << CTRL_SH_WTSRSEL;

sys/dev/sound/pci/es137x.c

598

es->ctrl |= 2 << CTRL_SH_WTSRSEL;

sys/dev/sound/pci/es137x.c

601

es->ctrl |= 3 << CTRL_SH_WTSRSEL;

sys/dev/sound/pci/es137x.c

604

es->ctrl &= ~CTRL_PCLKDIV;

sys/dev/sound/pci/es137x.c

605

es->ctrl |= DAC2_SRTODIV(speed) << CTRL_SH_PCLKDIV;

sys/dev/sound/pci/es137x.c

607

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/es137x.c

773

es->ctrl |= CTRL_DAC1_EN;

sys/dev/sound/pci/es137x.c

788

es->ctrl |= CTRL_DAC2_EN;

sys/dev/sound/pci/es137x.c

806

es->ctrl &= ~((ch->index == ES_DAC1) ?

sys/dev/sound/pci/es137x.c

810

es->ctrl |= CTRL_ADC_EN;

sys/dev/sound/pci/es137x.c

824

es->ctrl &= ~CTRL_ADC_EN;

sys/dev/sound/pci/es137x.c

827

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/es137x.c

996

es->ctrl = CTRL_CDC_EN | CTRL_JYSTK_EN | CTRL_SERR_DIS |

sys/dev/sound/pci/es137x.c

998

es->ctrl |= 3 << CTRL_SH_WTSRSEL;

sys/dev/sound/pci/es137x.c

999

es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4);

sys/dev/sound/pci/hda/hdaa.c

1117

sbuf_printf(sb, " Pin control: 0x%08x", w->wclass.pin.ctrl);

sys/dev/sound/pci/hda/hdaa.c

1118

if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)

sys/dev/sound/pci/hda/hdaa.c

1120

if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)

sys/dev/sound/pci/hda/hdaa.c

1122

if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)

sys/dev/sound/pci/hda/hdaa.c

1125

if ((w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

1128

else if ((w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

1132

if ((w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

1565

w->wclass.pin.ctrl = hda_command(dev,

sys/dev/sound/pci/hda/hdaa.c

1986

wp->wclass.pin.ctrl &=

sys/dev/sound/pci/hda/hdaa.c

1989

wp->wclass.pin.ctrl |= 0x03;

sys/dev/sound/pci/hda/hdaa.c

1992

wp->wclass.pin.ctrl));

sys/dev/sound/pci/hda/hdaa.c

409

val = w->wclass.pin.ctrl |

sys/dev/sound/pci/hda/hdaa.c

412

val = w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

414

if (val != w->wclass.pin.ctrl) {

sys/dev/sound/pci/hda/hdaa.c

415

w->wclass.pin.ctrl = val;

sys/dev/sound/pci/hda/hdaa.c

418

w->nid, w->wclass.pin.ctrl));

sys/dev/sound/pci/hda/hdaa.c

442

val = w1->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

445

val = w1->wclass.pin.ctrl |

sys/dev/sound/pci/hda/hdaa.c

447

if (val != w1->wclass.pin.ctrl) {

sys/dev/sound/pci/hda/hdaa.c

448

w1->wclass.pin.ctrl = val;

sys/dev/sound/pci/hda/hdaa.c

451

w1->nid, w1->wclass.pin.ctrl));

sys/dev/sound/pci/hda/hdaa.c

5060

w->wclass.pin.ctrl &= ~(

sys/dev/sound/pci/hda/hdaa.c

5072

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5080

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5085

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5090

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5095

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5101

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5108

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5113

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5118

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5123

w->wclass.pin.ctrl |=

sys/dev/sound/pci/hda/hdaa.c

5254

w->wclass.pin.ctrl));

sys/dev/sound/pci/hda/hdaa.c

5745

device_printf(w->devinfo->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);

sys/dev/sound/pci/hda/hdaa.c

5746

if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)

sys/dev/sound/pci/hda/hdaa.c

5748

if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)

sys/dev/sound/pci/hda/hdaa.c

5750

if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)

sys/dev/sound/pci/hda/hdaa.c

5753

if ((w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

5756

else if ((w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.c

5760

if ((w->wclass.pin.ctrl &

sys/dev/sound/pci/hda/hdaa.h

127

uint32_t ctrl;

sys/dev/sound/pci/spicds.c

128

codec->ctrl(codec->devinfo, 0, 1, 0);

sys/dev/sound/pci/spicds.c

130

codec->ctrl(codec->devinfo, 1, 1, 0);

sys/dev/sound/pci/spicds.c

133

codec->ctrl(codec->devinfo, 1, 1, 0);

sys/dev/sound/pci/spicds.c

140

spicds_create(device_t dev, void *devinfo, int num, spicds_ctrl ctrl)

sys/dev/sound/pci/spicds.c

154

codec->ctrl = ctrl;

sys/dev/sound/pci/spicds.c

43

spicds_ctrl ctrl;

sys/dev/sound/pci/spicds.c

67

codec->ctrl(codec->devinfo, cs, 0, cdti);

sys/dev/sound/pci/spicds.c

69

codec->ctrl(codec->devinfo, cs, 1, cdti);

sys/dev/sound/pci/spicds.c

85

codec->ctrl(codec->devinfo, 1, 1, 0);

sys/dev/sound/pci/spicds.c

87

codec->ctrl(codec->devinfo, 0, 1, 0);

sys/dev/sound/pci/t4dwave.c

398

ch->ctrl &= 0x0000000f;

sys/dev/sound/pci/t4dwave.c

413

cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);

sys/dev/sound/pci/t4dwave.c

461

ch->ctrl= (cr[4] & 0x0000f000) >> 12;

sys/dev/sound/pci/t4dwave.c

522

ch->ctrl = tr_fmttobits(format) | 0x01;

sys/dev/sound/pci/t4dwave.c

73

u_int32_t gvsel, pan, vol, ctrl;

sys/dev/sound/pci/via82c686.c

253

ch->ctrl = VIA_PLAY_CONTROL;

sys/dev/sound/pci/via82c686.c

261

ch->ctrl = VIA_RECORD_CONTROL;

sys/dev/sound/pci/via82c686.c

353

via_wr(via, ch->ctrl, VIA_RPCTRL_START, 1);

sys/dev/sound/pci/via82c686.c

355

via_wr(via, ch->ctrl, VIA_RPCTRL_TERMINATE, 1);

sys/dev/sound/pci/via82c686.c

72

int base, count, mode, ctrl;

sys/dev/sound/pcm/dsp.c

1560

ei->ctrl = 0;

sys/dev/uart/uart_dev_mvebu.c

170

uint32_t ctrl = 0;

sys/dev/uart/uart_dev_mvebu.c

175

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

176

uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |

sys/dev/uart/uart_dev_mvebu.c

182

ctrl |= CTRL_TWO_STOP;

sys/dev/uart/uart_dev_mvebu.c

186

ctrl &=~ CTRL_TWO_STOP;

sys/dev/uart/uart_dev_mvebu.c

191

ctrl |= CTRL_PAR_EN;

sys/dev/uart/uart_dev_mvebu.c

194

ctrl &=~ CTRL_PAR_EN;

sys/dev/uart/uart_dev_mvebu.c

212

ctrl |= CTRL_ST_MIRR_EN;

sys/dev/uart/uart_dev_mvebu.c

214

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

326

int ctrl;

sys/dev/uart/uart_dev_mvebu.c

331

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

334

ctrl &=~ CTRL_INTR_MASK;

sys/dev/uart/uart_dev_mvebu.c

335

ctrl |= CTRL_IPEND_MASK;

sys/dev/uart/uart_dev_mvebu.c

338

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

357

int ctrl, ret = 0;

sys/dev/uart/uart_dev_mvebu.c

361

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

365

uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);

sys/dev/uart/uart_dev_mvebu.c

370

uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);

sys/dev/uart/uart_dev_mvebu.c

381

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

400

int ctrl, ret = 0;

sys/dev/uart/uart_dev_mvebu.c

407

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

409

ctrl |= CTRL_SND_BRK_SEQ;

sys/dev/uart/uart_dev_mvebu.c

411

ctrl &=~ CTRL_SND_BRK_SEQ;

sys/dev/uart/uart_dev_mvebu.c

412

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

435

int ipend, ctrl, ret = 0;

sys/dev/uart/uart_dev_mvebu.c

440

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

443

(ctrl & CTRL_TX_IDLE_INT) == CTRL_TX_IDLE_INT) {

sys/dev/uart/uart_dev_mvebu.c

445

uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);

sys/dev/uart/uart_dev_mvebu.c

550

int i, ctrl;

sys/dev/uart/uart_dev_mvebu.c

556

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

557

uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);

sys/dev/uart/uart_dev_mvebu.c

569

uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);

sys/dev/uart/uart_dev_mvebu.c

584

uint32_t ctrl;

sys/dev/uart/uart_dev_mvebu.c

588

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

589

msc->intrm = ctrl & CTRL_INTR_MASK;

sys/dev/uart/uart_dev_mvebu.c

590

uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);

sys/dev/uart/uart_dev_mvebu.c

600

uint32_t ctrl;

sys/dev/uart/uart_dev_mvebu.c

604

ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;

sys/dev/uart/uart_dev_mvebu.c

605

uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);

sys/dev/uart/uart_dev_pl011.c

203

uint32_t ctrl, line;

sys/dev/uart/uart_dev_pl011.c

210

ctrl = line = 0x0;

sys/dev/uart/uart_dev_pl011.c

211

__uart_setreg(bas, UART_CR, ctrl);

sys/dev/uart/uart_dev_pl011.c

239

ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);

sys/dev/uart/uart_dev_pl011.c

254

__uart_setreg(bas, UART_CR, ctrl);

sys/dev/usb/controller/usb_controller.c

88

static SYSCTL_NODE(_hw_usb, OID_AUTO, ctrl, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,

sys/dev/usb/controller/xhcireg.h

305

#define XHCI_DCSTATUS(ctrl, portsc) \

sys/dev/usb/controller/xhcireg.h

306

(XHCI_DCCTRL_DCE_GET(ctrl) << 4 | \

sys/dev/usb/controller/xhcireg.h

310

XHCI_DCCTRL_DCR_GET(ctrl))

sys/dev/usb/input/usbhid.c

105

struct usb_device_request ctrl; /* CTRL xfers */

sys/dev/usb/input/usbhid.c

229

struct usb_device_request *req = &xfer_ctx->req.ctrl;

sys/dev/usb/input/usbhid.c

567

req.ctrl.bmRequestType = UT_READ_CLASS_INTERFACE;

sys/dev/usb/input/usbhid.c

568

req.ctrl.bRequest = UR_GET_REPORT;

sys/dev/usb/input/usbhid.c

569

USETW2(req.ctrl.wValue, type, id);

sys/dev/usb/input/usbhid.c

570

req.ctrl.wIndex[0] = sc->sc_iface_no;

sys/dev/usb/input/usbhid.c

571

req.ctrl.wIndex[1] = 0;

sys/dev/usb/input/usbhid.c

572

USETW(req.ctrl.wLength, maxlen);

sys/dev/usb/input/usbhid.c

593

req.ctrl.bmRequestType = UT_WRITE_CLASS_INTERFACE;

sys/dev/usb/input/usbhid.c

594

req.ctrl.bRequest = UR_SET_REPORT;

sys/dev/usb/input/usbhid.c

595

USETW2(req.ctrl.wValue, type, id);

sys/dev/usb/input/usbhid.c

596

req.ctrl.wIndex[0] = sc->sc_iface_no;

sys/dev/usb/input/usbhid.c

597

req.ctrl.wIndex[1] = 0;

sys/dev/usb/input/usbhid.c

598

USETW(req.ctrl.wLength, len);

sys/dev/usb/input/usbhid.c

654

req.ctrl.bmRequestType = UT_WRITE_CLASS_INTERFACE;

sys/dev/usb/input/usbhid.c

655

req.ctrl.bRequest = UR_SET_IDLE;

sys/dev/usb/input/usbhid.c

656

USETW2(req.ctrl.wValue, (duration + 3) / 4, id);

sys/dev/usb/input/usbhid.c

657

req.ctrl.wIndex[0] = sc->sc_iface_no;

sys/dev/usb/input/usbhid.c

658

req.ctrl.wIndex[1] = 0;

sys/dev/usb/input/usbhid.c

659

USETW(req.ctrl.wLength, 0);

sys/dev/usb/input/usbhid.c

675

req.ctrl.bmRequestType = UT_WRITE_CLASS_INTERFACE;

sys/dev/usb/input/usbhid.c

676

req.ctrl.bRequest = UR_SET_PROTOCOL;

sys/dev/usb/input/usbhid.c

677

USETW(req.ctrl.wValue, protocol);

sys/dev/usb/input/usbhid.c

678

req.ctrl.wIndex[0] = sc->sc_iface_no;

sys/dev/usb/input/usbhid.c

679

req.ctrl.wIndex[1] = 0;

sys/dev/usb/input/usbhid.c

680

USETW(req.ctrl.wLength, 0);

sys/dev/usb/input/usbhid.c

697

req.ctrl = ucr->ucr_request;

sys/dev/usb/input/usbhid.c

699

sc, USBHID_CTRL_DT, UGETW(req.ctrl.wLength));

sys/dev/usb/input/usbhid.c

702

error = usb_check_request(sc->sc_udev, &req.ctrl);

sys/dev/usb/input/usbhid.c

708

ucr->ucr_actlen = UGETW(req.ctrl.wLength);

sys/dev/usb/net/if_axge.c

86

uint8_t ctrl;

sys/dev/viapm/viapm.c

480

viabb_setscl(device_t dev, int ctrl)

sys/dev/viapm/viapm.c

488

if (ctrl)

sys/dev/watchdog/watchdog.c

119

wdog_control(int ctrl)

sys/dev/watchdog/watchdog.c

122

if (ctrl == WD_CTRL_DISABLE) {

sys/dev/watchdog/watchdog.c

126

if ((ctrl & WD_CTRL_RESET) != 0) {

sys/dev/watchdog/watchdog.c

128

} else if ((ctrl & WD_CTRL_ENABLE) != 0) {

sys/netgraph/ng_l2tp.c

153

hook_p ctrl; /* hook to upper layers */

sys/netgraph/ng_l2tp.c

398

if (priv->ctrl != NULL)

sys/netgraph/ng_l2tp.c

400

priv->ctrl = hook;

sys/netgraph/ng_l2tp.c

686

if (hook == priv->ctrl)

sys/netgraph/ng_l2tp.c

687

priv->ctrl = NULL;

sys/netgraph/ng_l2tp.c

951

NG_FWD_NEW_DATA(error, item, priv->ctrl, m);

sys/powerpc/mpc85xx/fsl_sata.c

1572

uint32_t ctrl;

sys/powerpc/mpc85xx/fsl_sata.c

1634

ctrl = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f;

sys/powerpc/mpc85xx/fsl_sata.c

1636

ctrl | FSL_SATA_P_HCTRL_FATAL | FSL_SATA_P_HCTRL_PHYRDY |

sys/rpc/svc_vc.c

726

struct mbuf *m, *ctrl;

sys/rpc/svc_vc.c

827

ctrl = m = NULL;

sys/rpc/svc_vc.c

828

error = soreceive(so, NULL, &uio, &m, &ctrl, &rcvflag);

sys/rpc/svc_vc.c

903

if (ctrl != NULL) {

sys/rpc/svc_vc.c

904

cmsg = mtod(ctrl, struct cmsghdr *);

sys/rpc/svc_vc.c

916

m_free(ctrl);

sys/rpc/svc_vc.c

925

m_free(ctrl);

sys/sys/ata.h

996

u_int16_t ctrl;

sys/sys/soundcard.h

1773

int ctrl; /* Controller number */

sys/sys/soundcard.h

1848

int ctrl;

sys/sys/soundcard.h

1859

int ctrl;

sys/sys/watchdog.h

125

int wdog_control(int ctrl);

sys/x86/cpufreq/powernow.c

146

#define WRITE_FIDVID(fid, vid, ctrl) \

sys/x86/cpufreq/powernow.c

148

(((ctrl) << 32) | (1ULL << 16) | ((vid) << 8) | (fid)))

sys/x86/cpufreq/powernow.c

323

pn8_write_fidvid(u_int fid, u_int vid, uint64_t ctrl, uint64_t *status)

sys/x86/cpufreq/powernow.c

328

WRITE_FIDVID(fid, vid, ctrl);

sys/x86/cpufreq/powernow.c

761

uint32_t ctrl;

sys/x86/cpufreq/powernow.c

788

ctrl = 0;

sys/x86/cpufreq/powernow.c

791

ctrl = sets[i].spec[PX_SPEC_CONTROL];

sys/x86/cpufreq/powernow.c

794

state.fid = ACPI_PN7_CTRL_TO_FID(ctrl);

sys/x86/cpufreq/powernow.c

795

state.vid = ACPI_PN7_CTRL_TO_VID(ctrl);

sys/x86/cpufreq/powernow.c

801

state.fid = ACPI_PN8_CTRL_TO_FID(ctrl);

sys/x86/cpufreq/powernow.c

802

state.vid = ACPI_PN8_CTRL_TO_VID(ctrl);

sys/x86/cpufreq/powernow.c

826

sc->sgtc = ACPI_PN7_CTRL_TO_SGTC(ctrl);

sys/x86/cpufreq/powernow.c

840

sc->vst = ACPI_PN8_CTRL_TO_VST(ctrl),

sys/x86/cpufreq/powernow.c

841

sc->mvs = ACPI_PN8_CTRL_TO_MVS(ctrl),

sys/x86/cpufreq/powernow.c

842

sc->pll = ACPI_PN8_CTRL_TO_PLL(ctrl),

sys/x86/cpufreq/powernow.c

843

sc->rvo = ACPI_PN8_CTRL_TO_RVO(ctrl),

sys/x86/cpufreq/powernow.c

844

sc->irt = ACPI_PN8_CTRL_TO_IRT(ctrl);

sys/x86/pci/pci_early_quirks.c

100

val = ctrl & I855_GMCH_GMS_MASK;

sys/x86/pci/pci_early_quirks.c

136

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

139

ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);

sys/x86/pci/pci_early_quirks.c

140

val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;

sys/x86/pci/pci_early_quirks.c

147

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

150

ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);

sys/x86/pci/pci_early_quirks.c

151

val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;

sys/x86/pci/pci_early_quirks.c

158

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

161

ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);

sys/x86/pci/pci_early_quirks.c

162

val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;

sys/x86/pci/pci_early_quirks.c

180

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

183

ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);

sys/x86/pci/pci_early_quirks.c

184

val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;

sys/x86/pci/pci_early_quirks.c

72

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

75

ctrl = pci_cfgregread(domain, bus, slot, func, INTEL_BSM, 4);

sys/x86/pci/pci_early_quirks.c

76

val = ctrl & INTEL_BSM_MASK;

sys/x86/pci/pci_early_quirks.c

83

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

86

ctrl = pci_cfgregread(domain, bus, slot, func, INTEL_GEN11_BSM_DW0, 4);

sys/x86/pci/pci_early_quirks.c

87

val = ctrl & INTEL_BSM_MASK;

sys/x86/pci/pci_early_quirks.c

96

uint32_t ctrl;

sys/x86/pci/pci_early_quirks.c

99

ctrl = pci_cfgregread(0, 0, 0, 0, I830_GMCH_CTRL, 2);

tools/regression/capsicum/syscalls/misc.c

110

msg.msg_control = ctrl;

tools/regression/capsicum/syscalls/misc.c

111

msg.msg_controllen = sizeof(ctrl);

tools/regression/capsicum/syscalls/misc.c

54

unsigned char ctrl[CMSG_SPACE(sizeof(fd))];

tools/regression/capsicum/syscalls/misc.c

62

bzero(&ctrl, sizeof(ctrl));

tools/regression/capsicum/syscalls/misc.c

66

msg.msg_control = ctrl;

tools/regression/capsicum/syscalls/misc.c

67

msg.msg_controllen = sizeof(ctrl);

tools/regression/capsicum/syscalls/misc.c

84

unsigned char ctrl[CMSG_SPACE(sizeof(*fdp))];

tools/regression/capsicum/syscalls/misc.c

94

bzero(&ctrl, sizeof(ctrl));

usr.bin/bsdiff/bspatch/bspatch.c

113

off_t ctrl[3];

usr.bin/bsdiff/bspatch/bspatch.c

243

ctrl[i] = offtin(buf);

usr.bin/bsdiff/bspatch/bspatch.c

247

if (ctrl[0] < 0 || ctrl[0] > INT_MAX ||

usr.bin/bsdiff/bspatch/bspatch.c

248

ctrl[1] < 0 || ctrl[1] > INT_MAX)

usr.bin/bsdiff/bspatch/bspatch.c

252

if (add_off_t(newpos, ctrl[0]) > newsize)

usr.bin/bsdiff/bspatch/bspatch.c

256

lenread = BZ2_bzRead(&dbz2err, dpfbz2, new + newpos, ctrl[0]);

usr.bin/bsdiff/bspatch/bspatch.c

257

if ((lenread < ctrl[0]) ||

usr.bin/bsdiff/bspatch/bspatch.c

262

for (i = 0; i < ctrl[0]; i++)

usr.bin/bsdiff/bspatch/bspatch.c

267

newpos = add_off_t(newpos, ctrl[0]);

usr.bin/bsdiff/bspatch/bspatch.c

268

oldpos = add_off_t(oldpos, ctrl[0]);

usr.bin/bsdiff/bspatch/bspatch.c

271

if (add_off_t(newpos, ctrl[1]) > newsize)

usr.bin/bsdiff/bspatch/bspatch.c

275

lenread = BZ2_bzRead(&ebz2err, epfbz2, new + newpos, ctrl[1]);

usr.bin/bsdiff/bspatch/bspatch.c

276

if ((lenread < ctrl[1]) ||

usr.bin/bsdiff/bspatch/bspatch.c

281

newpos = add_off_t(newpos, ctrl[1]);

usr.bin/bsdiff/bspatch/bspatch.c

282

oldpos = add_off_t(oldpos, ctrl[2]);

usr.bin/tip/tip/cmds.c

446

printf("\r\ntimeout error (%s)\r\n", ctrl(c));

usr.bin/tip/tip/tip.c

448

printf("%s", ctrl(c));

usr.bin/tip/tip/tip.c

531

printf("%2s", ctrl(character(value(ESCAPE))));

usr.bin/tip/tip/tip.c

532

printf("%-2s %c %s\r\n", ctrl(p->e_char),

usr.bin/tip/tip/tip.h

277

char *ctrl(char);

usr.bin/tip/tip/value.c

250

cp = ctrl(character(p->v_value));

usr.sbin/bhyve/pci_passthru.c

73

#define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)

usr.sbin/bhyve/pci_virtio_console.c

495

struct pci_vtcon_control resp, *ctrl;

usr.sbin/bhyve/pci_virtio_console.c

501

ctrl = (struct pci_vtcon_control *)iov->iov_base;

usr.sbin/bhyve/pci_virtio_console.c

503

switch (ctrl->event) {

usr.sbin/bhyve/pci_virtio_console.c

518

tmp = &sc->vsc_ports[ctrl->id];

usr.sbin/bhyve/pci_virtio_console.c

519

if (ctrl->id >= VTCON_MAXPORTS || !tmp->vsp_enabled) {

usr.sbin/bhyve/pci_virtio_console.c

521

ctrl->id));

usr.sbin/bhyve/pci_virtio_console.c

527

resp.id = ctrl->id;

usr.sbin/bhyve/pci_virtio_console.c

568

struct pci_vtcon_control *ctrl, const void *payload, size_t len)

usr.sbin/bhyve/pci_virtio_console.c

589

memcpy(iov.iov_base, ctrl, sizeof(struct pci_vtcon_control));

usr.sbin/bluetooth/bthidd/bthidd.h

47

int32_t ctrl; /* control channel (listen) */

usr.sbin/bluetooth/bthidd/bthidd.h

62

int32_t ctrl; /* control channel */

usr.sbin/bluetooth/bthidd/client.c

106

FD_SET(s->ctrl, &srv->wfdset);

usr.sbin/bluetooth/bthidd/client.c

107

if (s->ctrl > srv->maxfd)

usr.sbin/bluetooth/bthidd/client.c

108

srv->maxfd = s->ctrl;

usr.sbin/bluetooth/bthidd/client.c

158

assert(s->ctrl == fd);

usr.sbin/bluetooth/bthidd/client.c

184

assert(s->ctrl != -1);

usr.sbin/bluetooth/bthidd/client.c

96

s->ctrl = client_socket(&s->bdaddr, d->control_psm);

usr.sbin/bluetooth/bthidd/client.c

97

if (s->ctrl < 0) {

usr.sbin/bluetooth/bthidd/hid.c

95

write(s->ctrl, rep, 3);

usr.sbin/bluetooth/bthidd/server.c

100

if (bind(srv->ctrl, (struct sockaddr *) &l2addr, sizeof(l2addr)) < 0) {

usr.sbin/bluetooth/bthidd/server.c

103

close(srv->ctrl);

usr.sbin/bluetooth/bthidd/server.c

108

if (listen(srv->ctrl, 10) < 0) {

usr.sbin/bluetooth/bthidd/server.c

111

close(srv->ctrl);

usr.sbin/bluetooth/bthidd/server.c

121

close(srv->ctrl);

usr.sbin/bluetooth/bthidd/server.c

132

close(srv->ctrl);

usr.sbin/bluetooth/bthidd/server.c

141

close(srv->ctrl);

usr.sbin/bluetooth/bthidd/server.c

146

FD_SET(srv->ctrl, &srv->rfdset);

usr.sbin/bluetooth/bthidd/server.c

148

srv->maxfd = max(srv->ctrl, srv->intr);

usr.sbin/bluetooth/bthidd/server.c

163

close(srv->ctrl);

usr.sbin/bluetooth/bthidd/server.c

208

if (fd == srv->ctrl || fd == srv->intr)

usr.sbin/bluetooth/bthidd/server.c

238

(fd == srv->ctrl)? "control" : "interrupt",

usr.sbin/bluetooth/bthidd/server.c

247

(fd == srv->ctrl)? "control" : "interrupt",

usr.sbin/bluetooth/bthidd/server.c

268

if (fd == srv->ctrl) {

usr.sbin/bluetooth/bthidd/server.c

269

assert(s->ctrl == -1);

usr.sbin/bluetooth/bthidd/server.c

270

s->ctrl = new_fd;

usr.sbin/bluetooth/bthidd/server.c

275

s->state = (s->ctrl == -1)? W4CTRL : OPEN;

usr.sbin/bluetooth/bthidd/server.c

283

(fd == srv->ctrl)? "control" : "interrupt",

usr.sbin/bluetooth/bthidd/server.c

315

if (fd == s->ctrl) {

usr.sbin/bluetooth/bthidd/server.c

338

(fd == s->ctrl)? "control" : "interrupt",

usr.sbin/bluetooth/bthidd/server.c

347

(fd == s->ctrl)? "control" : "interrupt");

usr.sbin/bluetooth/bthidd/server.c

71

srv->ctrl = srv->intr = -1;

usr.sbin/bluetooth/bthidd/server.c

85

srv->ctrl = socket(PF_BLUETOOTH, SOCK_SEQPACKET, BLUETOOTH_PROTO_L2CAP);

usr.sbin/bluetooth/bthidd/server.c

86

if (srv->ctrl < 0) {

usr.sbin/bluetooth/bthidd/session.c

127

getsockname(s->ctrl, (struct sockaddr *) &local, &len);

usr.sbin/bluetooth/bthidd/session.c

186

if (s->ctrl == fd || s->intr == fd ||

usr.sbin/bluetooth/bthidd/session.c

214

if (s->ctrl != -1) {

usr.sbin/bluetooth/bthidd/session.c

215

FD_CLR(s->ctrl, &s->srv->rfdset);

usr.sbin/bluetooth/bthidd/session.c

216

FD_CLR(s->ctrl, &s->srv->wfdset);

usr.sbin/bluetooth/bthidd/session.c

217

close(s->ctrl);

usr.sbin/bluetooth/bthidd/session.c

219

if (s->srv->maxfd == s->ctrl)

usr.sbin/bluetooth/bthidd/session.c

69

s->ctrl = -1;

usr.sbin/inetd/inetd.c

2192

cpmip(const struct servtab *sep, int ctrl)

usr.sbin/inetd/inetd.c

2205

getpeername(ctrl, (struct sockaddr *)&rss, &rssLen) == 0 ) {

usr.sbin/inetd/inetd.c

223

static struct conninfo *search_conn(struct servtab *sep, int ctrl);

usr.sbin/inetd/inetd.c

2332

search_conn(struct servtab *sep, int ctrl)

usr.sbin/inetd/inetd.c

2347

if (getpeername(ctrl, (struct sockaddr *)&ss, &sslen) != 0)

usr.sbin/inetd/inetd.c

557

int n, ctrl;

usr.sbin/inetd/inetd.c

618

ctrl = accept(sep->se_fd, (struct sockaddr *)0,

usr.sbin/inetd/inetd.c

621

warnx("accept, ctrl %d", ctrl);

usr.sbin/inetd/inetd.c

622

if (ctrl < 0) {

usr.sbin/inetd/inetd.c

629

close(ctrl);

usr.sbin/inetd/inetd.c

635

if (ioctl(ctrl, FIONBIO, &i) < 0)

usr.sbin/inetd/inetd.c

637

if (cpmip(sep, ctrl) < 0) {

usr.sbin/inetd/inetd.c

638

close(ctrl);

usr.sbin/inetd/inetd.c

642

(conn = search_conn(sep, ctrl)) != NULL &&

usr.sbin/inetd/inetd.c

644

close(ctrl);

usr.sbin/inetd/inetd.c

648

ctrl = sep->se_fd;

usr.sbin/inetd/inetd.c

653

if (getpeername(ctrl, (struct sockaddr *)

usr.sbin/inetd/inetd.c

656

if (recvfrom(ctrl, buf, sizeof(buf),

usr.sbin/inetd/inetd.c

697

close(ctrl);

usr.sbin/inetd/inetd.c

714

close(ctrl);

usr.sbin/inetd/inetd.c

738

sep = tcpmux(ctrl);

usr.sbin/inetd/inetd.c

740

close(ctrl);

usr.sbin/inetd/inetd.c

746

inetd_setproctitle("wrapping", ctrl);

usr.sbin/inetd/inetd.c

749

request_init(&req, RQ_DAEMON, service, RQ_FILE, ctrl, 0);

usr.sbin/inetd/inetd.c

760

recv(ctrl, buf, sizeof (buf), 0);

usr.sbin/inetd/inetd.c

775

(*sep->se_bi->bi_fn)(ctrl, sep);

usr.sbin/inetd/inetd.c

781

if (fcntl(ctrl, F_SETFD, 0) < 0) {

usr.sbin/inetd/inetd.c

787

if (ctrl != 0) {

usr.sbin/inetd/inetd.c

788

dup2(ctrl, 0);

usr.sbin/inetd/inetd.c

789

close(ctrl);

usr.sbin/inetd/inetd.c

880

close(ctrl);

usr.sbin/pciconf/cap.c

128

uint16_t ctrl;

usr.sbin/pciconf/cap.c

131

ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);

usr.sbin/pciconf/cap.c

132

msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);

usr.sbin/pciconf/cap.c

135

(ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",

usr.sbin/pciconf/cap.c

136

(ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");

usr.sbin/pciconf/cap.c

137

if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {

usr.sbin/pciconf/cap.c

138

msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);

usr.sbin/pciconf/cap.c

693

uint16_t ctrl;

usr.sbin/pciconf/cap.c

695

ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);

usr.sbin/pciconf/cap.c

696

msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;

usr.sbin/pciconf/cap.c

708

(ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : "");