crypto/libressl/apps/openssl/ocsp.c

1258

ASN1_OBJECT *inst = NULL;

crypto/libressl/apps/openssl/ocsp.c

1264

unpack_revinfo(&revtm, &reason, &inst, &invtm,

crypto/libressl/apps/openssl/ocsp.c

1273

else if (inst)

crypto/libressl/apps/openssl/ocsp.c

1275

NID_hold_instruction_code, inst, 0, 0);

crypto/libressl/apps/openssl/ocsp.c

1276

ASN1_OBJECT_free(inst);

crypto/libressl/include/openssl/lhash.h

206

#define LHM_lh_insert(type, lh, inst) \

crypto/libressl/include/openssl/lhash.h

208

CHECKED_PTR_OF(type, inst)))

crypto/libressl/include/openssl/lhash.h

209

#define LHM_lh_retrieve(type, lh, inst) \

crypto/libressl/include/openssl/lhash.h

211

CHECKED_PTR_OF(type, inst)))

crypto/libressl/include/openssl/lhash.h

212

#define LHM_lh_delete(type, lh, inst) \

crypto/libressl/include/openssl/lhash.h

214

CHECKED_PTR_OF(type, inst)))

crypto/libressl/include/openssl/safestack.h

2017

#define lh_ADDED_OBJ_insert(lh,inst) LHM_lh_insert(ADDED_OBJ,lh,inst)

crypto/libressl/include/openssl/safestack.h

2018

#define lh_ADDED_OBJ_retrieve(lh,inst) LHM_lh_retrieve(ADDED_OBJ,lh,inst)

crypto/libressl/include/openssl/safestack.h

2019

#define lh_ADDED_OBJ_delete(lh,inst) LHM_lh_delete(ADDED_OBJ,lh,inst)

crypto/libressl/include/openssl/safestack.h

2035

#define lh_APP_INFO_insert(lh,inst) LHM_lh_insert(APP_INFO,lh,inst)

crypto/libressl/include/openssl/safestack.h

2036

#define lh_APP_INFO_retrieve(lh,inst) LHM_lh_retrieve(APP_INFO,lh,inst)

crypto/libressl/include/openssl/safestack.h

2037

#define lh_APP_INFO_delete(lh,inst) LHM_lh_delete(APP_INFO,lh,inst)

crypto/libressl/include/openssl/safestack.h

2053

#define lh_CONF_VALUE_insert(lh,inst) LHM_lh_insert(CONF_VALUE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2054

#define lh_CONF_VALUE_retrieve(lh,inst) LHM_lh_retrieve(CONF_VALUE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2055

#define lh_CONF_VALUE_delete(lh,inst) LHM_lh_delete(CONF_VALUE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2071

#define lh_ENGINE_PILE_insert(lh,inst) LHM_lh_insert(ENGINE_PILE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2072

#define lh_ENGINE_PILE_retrieve(lh,inst) LHM_lh_retrieve(ENGINE_PILE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2073

#define lh_ENGINE_PILE_delete(lh,inst) LHM_lh_delete(ENGINE_PILE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2089

#define lh_ERR_STATE_insert(lh,inst) LHM_lh_insert(ERR_STATE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2090

#define lh_ERR_STATE_retrieve(lh,inst) LHM_lh_retrieve(ERR_STATE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2091

#define lh_ERR_STATE_delete(lh,inst) LHM_lh_delete(ERR_STATE,lh,inst)

crypto/libressl/include/openssl/safestack.h

2107

#define lh_ERR_STRING_DATA_insert(lh,inst) LHM_lh_insert(ERR_STRING_DATA,lh,inst)

crypto/libressl/include/openssl/safestack.h

2108

#define lh_ERR_STRING_DATA_retrieve(lh,inst) LHM_lh_retrieve(ERR_STRING_DATA,lh,inst)

crypto/libressl/include/openssl/safestack.h

2109

#define lh_ERR_STRING_DATA_delete(lh,inst) LHM_lh_delete(ERR_STRING_DATA,lh,inst)

crypto/libressl/include/openssl/safestack.h

2125

#define lh_EX_CLASS_ITEM_insert(lh,inst) LHM_lh_insert(EX_CLASS_ITEM,lh,inst)

crypto/libressl/include/openssl/safestack.h

2126

#define lh_EX_CLASS_ITEM_retrieve(lh,inst) LHM_lh_retrieve(EX_CLASS_ITEM,lh,inst)

crypto/libressl/include/openssl/safestack.h

2127

#define lh_EX_CLASS_ITEM_delete(lh,inst) LHM_lh_delete(EX_CLASS_ITEM,lh,inst)

crypto/libressl/include/openssl/safestack.h

2143

#define lh_FUNCTION_insert(lh,inst) LHM_lh_insert(FUNCTION,lh,inst)

crypto/libressl/include/openssl/safestack.h

2144

#define lh_FUNCTION_retrieve(lh,inst) LHM_lh_retrieve(FUNCTION,lh,inst)

crypto/libressl/include/openssl/safestack.h

2145

#define lh_FUNCTION_delete(lh,inst) LHM_lh_delete(FUNCTION,lh,inst)

crypto/libressl/include/openssl/safestack.h

2161

#define lh_MEM_insert(lh,inst) LHM_lh_insert(MEM,lh,inst)

crypto/libressl/include/openssl/safestack.h

2162

#define lh_MEM_retrieve(lh,inst) LHM_lh_retrieve(MEM,lh,inst)

crypto/libressl/include/openssl/safestack.h

2163

#define lh_MEM_delete(lh,inst) LHM_lh_delete(MEM,lh,inst)

crypto/libressl/include/openssl/safestack.h

2179

#define lh_OBJ_NAME_insert(lh,inst) LHM_lh_insert(OBJ_NAME,lh,inst)

crypto/libressl/include/openssl/safestack.h

2180

#define lh_OBJ_NAME_retrieve(lh,inst) LHM_lh_retrieve(OBJ_NAME,lh,inst)

crypto/libressl/include/openssl/safestack.h

2181

#define lh_OBJ_NAME_delete(lh,inst) LHM_lh_delete(OBJ_NAME,lh,inst)

crypto/libressl/include/openssl/safestack.h

2197

#define lh_OPENSSL_CSTRING_insert(lh,inst) LHM_lh_insert(OPENSSL_CSTRING,lh,inst)

crypto/libressl/include/openssl/safestack.h

2198

#define lh_OPENSSL_CSTRING_retrieve(lh,inst) LHM_lh_retrieve(OPENSSL_CSTRING,lh,inst)

crypto/libressl/include/openssl/safestack.h

2199

#define lh_OPENSSL_CSTRING_delete(lh,inst) LHM_lh_delete(OPENSSL_CSTRING,lh,inst)

crypto/libressl/include/openssl/safestack.h

2215

#define lh_OPENSSL_STRING_insert(lh,inst) LHM_lh_insert(OPENSSL_STRING,lh,inst)

crypto/libressl/include/openssl/safestack.h

2216

#define lh_OPENSSL_STRING_retrieve(lh,inst) LHM_lh_retrieve(OPENSSL_STRING,lh,inst)

crypto/libressl/include/openssl/safestack.h

2217

#define lh_OPENSSL_STRING_delete(lh,inst) LHM_lh_delete(OPENSSL_STRING,lh,inst)

crypto/libressl/include/openssl/safestack.h

2233

#define lh_SSL_SESSION_insert(lh,inst) LHM_lh_insert(SSL_SESSION,lh,inst)

crypto/libressl/include/openssl/safestack.h

2234

#define lh_SSL_SESSION_retrieve(lh,inst) LHM_lh_retrieve(SSL_SESSION,lh,inst)

crypto/libressl/include/openssl/safestack.h

2235

#define lh_SSL_SESSION_delete(lh,inst) LHM_lh_delete(SSL_SESSION,lh,inst)

crypto/openssh/sshconnect2.c

1942

char *name = NULL, *inst = NULL, *lang = NULL, *prompt = NULL;

crypto/openssh/sshconnect2.c

1956

(r = sshpkt_get_cstring(ssh, &inst, NULL)) != 0 ||

crypto/openssh/sshconnect2.c

1961

if (strlen(inst) > 0)

crypto/openssh/sshconnect2.c

1962

logit("%s", inst);

crypto/openssh/sshconnect2.c

2004

free(inst);

sys/cpu/x86_64/include/db_machdep.h

55

#define BKPT_SET(inst) (BKPT_INST)

sys/cpu/x86_64/misc/db_disasm.c

1070

db_disasm_esc(db_addr_t loc, int inst, int rex, int short_addr, int size,

sys/cpu/x86_64/misc/db_disasm.c

1080

fp = &db_Esc_inst[inst - 0xd8][f_reg(rex, regmodrm)];

sys/cpu/x86_64/misc/db_disasm.c

1164

int inst;

sys/cpu/x86_64/misc/db_disasm.c

1168

const struct inst * ip;

sys/cpu/x86_64/misc/db_disasm.c

1183

get_value_inc(inst, loc, 1, FALSE);

sys/cpu/x86_64/misc/db_disasm.c

1193

switch (inst) {

sys/cpu/x86_64/misc/db_disasm.c

1231

if (inst >= 0x40 && inst < 0x50) {

sys/cpu/x86_64/misc/db_disasm.c

1232

rex = inst;

sys/cpu/x86_64/misc/db_disasm.c

1236

get_value_inc(inst, loc, 1, FALSE);

sys/cpu/x86_64/misc/db_disasm.c

1240

if (inst >= 0xd8 && inst <= 0xdf) {

sys/cpu/x86_64/misc/db_disasm.c

1241

loc = db_disasm_esc(loc, inst, rex, short_addr, size, seg);

sys/cpu/x86_64/misc/db_disasm.c

1246

if (inst == 0x0f) {

sys/cpu/x86_64/misc/db_disasm.c

1247

get_value_inc(inst, loc, 1, FALSE);

sys/cpu/x86_64/misc/db_disasm.c

1248

ip = db_inst_0f[inst>>4];

sys/cpu/x86_64/misc/db_disasm.c

1253

ip = &ip[inst&0xf];

sys/cpu/x86_64/misc/db_disasm.c

1257

ip = &db_inst_table[inst];

sys/cpu/x86_64/misc/db_disasm.c

1304

if ((inst >= 0x50 && inst <= 0x5f) || inst == 0x68 || inst == 0x6a) {

sys/cpu/x86_64/misc/db_disasm.c

1373

db_printf("%s", db_reg[0][QUAD][f_rm(rex, inst)]);

sys/cpu/x86_64/misc/db_disasm.c

1377

db_printf("%s", db_reg[rex != 0 ? 1 : 0][(rex & REX_R) ? QUAD : LONG][f_rm(rex, inst)]);

sys/cpu/x86_64/misc/db_disasm.c

1385

db_printf("%s", db_seg_reg[f_reg(rex, inst)]);

sys/cpu/x86_64/misc/db_disasm.c

235

static const struct inst db_inst_0f0x[] = {

sys/cpu/x86_64/misc/db_disasm.c

255

static const struct inst db_inst_0f2x[] = {

sys/cpu/x86_64/misc/db_disasm.c

275

static const struct inst db_inst_0f3x[] = {

sys/cpu/x86_64/misc/db_disasm.c

295

static const struct inst db_inst_0f4x[] = {

sys/cpu/x86_64/misc/db_disasm.c

315

static const struct inst db_inst_0f8x[] = {

sys/cpu/x86_64/misc/db_disasm.c

335

static const struct inst db_inst_0f9x[] = {

sys/cpu/x86_64/misc/db_disasm.c

355

static const struct inst db_inst_0fax[] = {

sys/cpu/x86_64/misc/db_disasm.c

375

static const struct inst db_inst_0fbx[] = {

sys/cpu/x86_64/misc/db_disasm.c

395

static const struct inst db_inst_0fcx[] = {

sys/cpu/x86_64/misc/db_disasm.c

414

static const struct inst * const db_inst_0f[] = {

sys/cpu/x86_64/misc/db_disasm.c

581

static const struct inst db_Grp3[] = {

sys/cpu/x86_64/misc/db_disasm.c

592

static const struct inst db_Grp4[] = {

sys/cpu/x86_64/misc/db_disasm.c

603

static const struct inst db_Grp5[] = {

sys/cpu/x86_64/misc/db_disasm.c

614

static const struct inst db_inst_table[256] = {

sys/cpu/x86_64/misc/db_disasm.c

905

static const struct inst db_bad_inst = { "???", FALSE, NONE, 0, 0 };

sys/cpu/x86_64/misc/db_disasm.c

966

db_disasm_esc(db_addr_t loc, int inst, int rex, int short_addr,

sys/ddb/db_run.c

263

unsigned inst;

sys/ddb/db_run.c

269

inst = db_get_value(pc, sizeof(int), FALSE);

sys/ddb/db_run.c

270

if (inst_branch(inst) || inst_call(inst)) {

sys/ddb/db_run.c

271

brpc = branch_taken(inst, pc, regs);

sys/dev/disk/isp/ispmbox.h

2085

#define AT2_MAKE_TAGID(tid, bus, inst, aep) \

sys/dev/disk/isp/ispmbox.h

2087

tid |= (((uint64_t)inst) << 32); \

sys/dev/disk/isp/ispmbox.h

2090

#define CT2_MAKE_TAGID(tid, bus, inst, ct) \

sys/dev/disk/isp/ispmbox.h

2092

tid |= (((uint64_t)inst) << 32); \

sys/dev/disk/isp/ispmbox.h

2106

#define IN_FC_MAKE_TAGID(tid, bus, inst, seqid) \

sys/dev/disk/isp/ispmbox.h

2108

tid |= (((uint64_t)inst) << 32); \

sys/dev/disk/isp/ispmbox.h

2111

#define FC_TAG_INSERT_INST(tid, inst) \

sys/dev/disk/isp/ispmbox.h

2113

tid |= (((uint64_t)inst) << 32)

sys/dev/drm/amd/amdgpu/amdgpu_ctx.c

146

rings[0] = &adev->uvd.inst[0].ring;

sys/dev/drm/amd/amdgpu/amdgpu_ctx.c

154

rings[0] = &adev->uvd.inst[0].ring_enc[0];

sys/dev/drm/amd/amdgpu/amdgpu_fence.c

391

ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;

sys/dev/drm/amd/amdgpu/amdgpu_fence.c

392

ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

382

if (adev->uvd.inst[i].ring.ready)

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

403

if (adev->uvd.inst[i].ring_enc[j].ready)

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

1185

fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

1187

fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

259

AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

260

(u64 *)&adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

305

kvfree(adev->uvd.inst[j].saved_bo);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

307

amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

308

(u64 *)&adev->uvd.inst[j].gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

309

(void **)&adev->uvd.inst[j].cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

311

amdgpu_ring_fini(&adev->uvd.inst[j].ring);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

314

amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

333

ring = &adev->uvd.inst[0].ring;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

365

if (adev->uvd.inst[j].vcpu_bo == NULL)

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

368

size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

369

ptr = adev->uvd.inst[j].cpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

371

adev->uvd.inst[j].saved_bo = kmalloc(size, M_DRM, GFP_KERNEL);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

372

if (!adev->uvd.inst[j].saved_bo)

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

375

memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

389

if (adev->uvd.inst[i].vcpu_bo == NULL)

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

392

size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

393

ptr = adev->uvd.inst[i].cpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

395

if (adev->uvd.inst[i].saved_bo != NULL) {

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

396

memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

397

kvfree(adev->uvd.inst[i].saved_bo);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

398

adev->uvd.inst[i].saved_bo = NULL;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

406

memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

413

amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

421

struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

860

(start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {

sys/dev/drm/amd/amdgpu/amdgpu_uvd.h

62

struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES];

sys/dev/drm/amd/amdgpu/soc15.c

270

uint32_t inst;

sys/dev/drm/amd/amdgpu/soc15.c

340

if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

sys/dev/drm/amd/amdgpu/soc15.h

45

#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg

sys/dev/drm/amd/amdgpu/soc15.h

47

#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \

sys/dev/drm/amd/amdgpu/soc15.h

48

{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }

sys/dev/drm/amd/amdgpu/soc15_common.h

28

#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

sys/dev/drm/amd/amdgpu/soc15_common.h

35

#define RREG32_SOC15(ip, inst, reg) \

sys/dev/drm/amd/amdgpu/soc15_common.h

36

RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

sys/dev/drm/amd/amdgpu/soc15_common.h

38

#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \

sys/dev/drm/amd/amdgpu/soc15_common.h

39

RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)

sys/dev/drm/amd/amdgpu/soc15_common.h

41

#define WREG32_SOC15(ip, inst, reg, value) \

sys/dev/drm/amd/amdgpu/soc15_common.h

42

WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)

sys/dev/drm/amd/amdgpu/soc15_common.h

44

#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \

sys/dev/drm/amd/amdgpu/soc15_common.h

45

WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)

sys/dev/drm/amd/amdgpu/soc15_common.h

47

#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \

sys/dev/drm/amd/amdgpu/soc15_common.h

48

WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)

sys/dev/drm/amd/amdgpu/soc15_common.h

50

#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \

sys/dev/drm/amd/amdgpu/soc15_common.h

53

uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \

sys/dev/drm/amd/amdgpu/soc15_common.h

62

tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \

sys/dev/drm/amd/amdgpu/soc15_common.h

66

inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \

sys/dev/drm/amd/amdgpu/soc15_common.h

73

#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \

sys/dev/drm/amd/amdgpu/soc15_common.h

74

({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \

sys/dev/drm/amd/amdgpu/soc15_common.h

75

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \

sys/dev/drm/amd/amdgpu/soc15_common.h

77

((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \

sys/dev/drm/amd/amdgpu/soc15_common.h

80

RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })

sys/dev/drm/amd/amdgpu/soc15_common.h

82

#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \

sys/dev/drm/amd/amdgpu/soc15_common.h

84

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \

sys/dev/drm/amd/amdgpu/soc15_common.h

85

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \

sys/dev/drm/amd/amdgpu/soc15_common.h

86

WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \

sys/dev/drm/amd/amdgpu/soc15_common.h

88

((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

111

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

119

ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

121

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

158

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

216

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

259

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

556

addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

573

addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

577

addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

684

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

772

adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

782

adev->uvd.inst->irq.num_types = 1;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

783

adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

108

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

116

ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

118

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

153

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

213

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

262

lower_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

264

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

296

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

607

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

881

adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

891

adev->uvd.inst->irq.num_types = 1;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

892

adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1153

adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1156

adev->uvd.inst->srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1165

if (!adev->uvd.inst->srbm_soft_reset)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1177

if (!adev->uvd.inst->srbm_soft_reset)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1179

srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1207

if (!adev->uvd.inst->srbm_soft_reset)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1233

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1237

amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1243

amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

125

if (ring == &adev->uvd.inst->ring_enc[0])

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

156

if (ring == &adev->uvd.inst->ring_enc[0])

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1605

adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1608

adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1618

adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1631

adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1633

adev->uvd.inst->irq.num_types = 1;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1635

adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

392

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

399

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

411

adev->uvd.inst->ring_enc[i].funcs = NULL;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

413

adev->uvd.inst->irq.num_types = 1;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

419

ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

421

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

431

ring = &adev->uvd.inst->ring_enc[i];

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

433

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

455

amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

471

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

515

ring = &adev->uvd.inst->ring_enc[i];

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

546

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

594

lower_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

596

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

709

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

849

ring = &adev->uvd.inst->ring_enc[0];

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

856

ring = &adev->uvd.inst->ring_enc[1];

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

95

if (ring == &adev->uvd.inst->ring_enc[0])

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1098

ring = &adev->uvd.inst[k].ring_enc[0];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1105

ring = &adev->uvd.inst[k].ring_enc[1];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

123

if (ring == &adev->uvd.inst[ring->me].ring_enc[0])

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1474

adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1477

adev->uvd.inst[ring->me].srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1486

if (!adev->uvd.inst[ring->me].srbm_soft_reset)

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1498

if (!adev->uvd.inst[ring->me].srbm_soft_reset)

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1500

srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1528

if (!adev->uvd.inst[ring->me].srbm_soft_reset)

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1568

amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1571

amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1575

amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

161

if (ring == &adev->uvd.inst[ring->me].ring_enc[0])

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1848

adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1849

adev->uvd.inst[i].ring.me = i;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1862

adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1863

adev->uvd.inst[j].ring_enc[i].me = j;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1882

adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1883

adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

417

r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

423

r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

454

ring = &adev->uvd.inst[j].ring;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

456

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

462

ring = &adev->uvd.inst[j].ring_enc[i];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

475

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

511

amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

540

ring = &adev->uvd.inst[j].ring;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

584

ring = &adev->uvd.inst[j].ring_enc[i];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

622

adev->uvd.inst[i].ring.ready = false;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

681

lower_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

683

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

692

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

694

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

699

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

701

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

747

WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

748

adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

749

adev->uvd.inst[i].ring_enc[0].wptr = 0;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

750

adev->uvd.inst[i].ring_enc[0].wptr_old = 0;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

805

ring = &adev->uvd.inst[i].ring;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

820

lower_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

822

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

831

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

833

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

838

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

840

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

89

if (ring == &adev->uvd.inst[ring->me].ring_enc[0])

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

904

ring = &adev->uvd.inst[i].ring_enc[0];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

960

ring = &adev->uvd.inst[k].ring;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

521

secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;

sys/dev/drm/amd/display/dc/core/dc_debug.c

340

pipe_ctx->stream_res.tg->inst,

sys/dev/drm/amd/display/dc/core/dc_link.c

2217

res_ctx.pipe_ctx[i].stream_res.tg->inst +

sys/dev/drm/amd/display/dc/core/dc_link.c

2547

pipe_ctx->stream_res.tg->inst,

sys/dev/drm/amd/display/dc/core/dc_resource.c

1339

pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;

sys/dev/drm/amd/display/dc/core/dc_resource.c

1730

pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;

sys/dev/drm/amd/display/dc/core/dc_resource.c

2055

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/drm/amd/display/dc/dce/dce_audio.c

369

audio->inst, value);

sys/dev/drm/amd/display/dc/dce/dce_audio.c

394

audio->inst, value);

sys/dev/drm/amd/display/dc/dce/dce_audio.c

890

if (audio->inst != 0)

sys/dev/drm/amd/display/dc/dce/dce_audio.c

936

unsigned int inst,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

950

audio->base.inst = inst;

sys/dev/drm/amd/display/dc/dce/dce_audio.h

126

unsigned int inst,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

924

uint32_t inst,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

933

aux_engine110->base.inst = inst;

sys/dev/drm/amd/display/dc/dce/dce_aux.h

102

uint32_t inst,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

905

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

910

REG_WRITE(PHASE[inst], clock_kHz);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

911

REG_WRITE(MODULO[inst], dp_dto_ref_kHz);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

914

REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

60

val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

71

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

76

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

83

REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

528

unsigned int inst, bool enable);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

247

int inst,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

253

ipp_dce->base.inst = inst;

sys/dev/drm/amd/display/dc/dce/dce_ipp.h

231

int inst,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

771

int inst,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

778

dce_mi->base.inst = inst;

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

789

int inst,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

794

dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

801

int inst,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

806

dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

343

int inst,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

351

int inst,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

359

int inst,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

544

uint32_t inst,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

553

opp110->base.inst = inst;

sys/dev/drm/amd/display/dc/dce/dce_opp.h

277

uint32_t inst,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1345

uint32_t inst,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1352

xfm_dce->base.inst = inst;

sys/dev/drm/amd/display/dc/dce/dce_transform.h

487

uint32_t inst,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

405

struct dc_context *ctx, unsigned int inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

407

return dce_audio_create(ctx, inst,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

408

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

502

uint32_t inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

512

dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

525

uint32_t inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

533

dce_transform_construct(transform, ctx, inst,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

534

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

539

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

548

dce_ipp_construct(ipp, ctx, inst,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

549

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

582

uint32_t inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

591

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

598

uint32_t inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

606

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

608

&aux_engine_regs[inst]);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

634

uint32_t inst)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

642

dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

643

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

237

params->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

243

compressor->attached_inst = params->inst;

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

244

cp110->offsets = reg_offsets[params->inst];

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

296

uint32_t *inst)

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

303

if (inst != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

304

*inst = compressor->attached_inst;

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

313

if (inst != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

314

*inst =

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1212

pipe_ctx->stream_res.tg->inst + 1);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1224

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1378

pipe_ctx->stream_res.audio->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1383

pipe_ctx->stream_res.audio->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2159

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2280

gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2438

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2617

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2779

pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

631

crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1044

pipe_ctx->stream_res.tg->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

416

struct dc_context *ctx, unsigned int inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

418

return dce_audio_create(ctx, inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

419

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

518

uint32_t inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

528

dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

541

uint32_t inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

549

dce_transform_construct(transform, ctx, inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

550

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

555

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

564

dce_ipp_construct(ipp, ctx, inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

565

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

596

uint32_t inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

605

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

612

uint32_t inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

620

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

622

&aux_engine_regs[inst]);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

648

uint32_t inst)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

656

dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

657

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

789

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1232

gsl_params->gsl_master == tg->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

2246

tg110->base.inst = instance;

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

395

params->inst,

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

401

compressor->attached_inst = params->inst;

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

402

cp110->offsets = reg_offsets[params->inst];

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

441

uint32_t *inst)

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

448

if (inst != NULL)

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

449

*inst = compressor->attached_inst;

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

458

if (inst != NULL)

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

459

*inst =

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

424

struct dc_context *ctx, unsigned int inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

426

return dce_audio_create(ctx, inst,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

427

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

518

uint32_t inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

528

dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

540

uint32_t inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

548

dce_transform_construct(transform, ctx, inst,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

549

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

584

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

593

dce_ipp_construct(ipp, ctx, inst,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

594

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

601

uint32_t inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

610

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

617

uint32_t inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

625

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

627

&aux_engine_regs[inst]);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

653

uint32_t inst)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

661

dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

662

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

369

uint32_t inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

378

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

385

uint32_t inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

393

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

395

&aux_engine_regs[inst]);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

421

uint32_t inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

429

dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

430

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

606

struct dc_context *ctx, unsigned int inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

608

return dce_audio_create(ctx, inst,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

609

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

642

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

651

dce_ipp_construct(ipp, ctx, inst,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

652

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

729

uint32_t inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

739

dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

745

uint32_t inst)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

753

dce_transform_construct(transform, ctx, inst,

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

754

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1185

tg110->base.inst = instance;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

276

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

437

struct dc_context *ctx, unsigned int inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

439

return dce_audio_create(ctx, inst,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

440

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

460

uint32_t inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

469

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

476

uint32_t inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

484

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

486

&aux_engine_regs[inst]);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

512

uint32_t inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

520

dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

521

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

617

uint32_t inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

627

dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

640

uint32_t inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

648

dce_transform_construct(transform, ctx, inst,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

649

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

712

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

721

dce_ipp_construct(ipp, ctx, inst,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

722

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c

226

tg110->base.inst = instance;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

545

uint32_t inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

552

dpp->base.inst = inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h

1506

uint32_t inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

643

- visual_confirm_on * 4 * (dpp->base.inst + 1));

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1205

uint32_t inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1215

hubp1->base.inst = inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

736

uint32_t inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1068

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1069

hubp->mpcc_id = dpp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1073

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1377

grouped_pipes[0]->stream_res.tg->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

138

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1637

pipe_ctx->plane_res.hubp->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

167

pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

194

pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1996

mpcc_id = hubp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2020

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2025

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2077

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

224

pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2561

if (res_pool->hubps[i]->inst == mpcc_inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

263

dpp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

321

tg->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

681

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

775

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

883

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

918

dpp_pg_control(hws, dpp->inst, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

919

hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

143

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

162

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

211

pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

259

pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

310

pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

351

dpp->inst, s.igam_input_format,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

436

tg->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.c

57

int inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.c

63

ippn10->base.inst = inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h

160

int inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

33

#define MPC_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

34

SRII(MPCC_TOP_SEL, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

35

SRII(MPCC_BOT_SEL, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

36

SRII(MPCC_CONTROL, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

37

SRII(MPCC_STATUS, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

38

SRII(MPCC_OPP_ID, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

39

SRII(MPCC_BG_G_Y, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

40

SRII(MPCC_BG_R_CR, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

41

SRII(MPCC_BG_B_CB, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

42

SRII(MPCC_BG_B_CB, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

43

SRII(MPCC_SM_CONTROL, MPCC, inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

45

#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

46

SRII(MUX, MPC_OUT, inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

401

uint32_t inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

408

oppn10->base.inst = inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h

158

uint32_t inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

466

OPTC_SRC_SEL, optc->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

602

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

34

#define TG_COMMON_REG_LIST_DCN(inst) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

35

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

36

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

37

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

38

SRI(OTG_BLANK_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

39

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

40

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

41

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

42

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

43

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

44

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

45

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

46

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

47

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

48

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

49

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

50

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

51

SRI(OTG_INTERLACE_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

52

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

53

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

54

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

55

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

56

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

57

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

58

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

59

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

60

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

61

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

62

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

63

SRI(OTG_STATUS, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

64

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

65

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

66

SRI(OTG_BLACK_COLOR, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

67

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

68

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

72

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

73

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

74

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

75

SRI(CONTROL, VTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

76

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

77

SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

78

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

79

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

80

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

81

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

82

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

83

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

84

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

85

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

87

#define TG_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

88

TG_COMMON_REG_LIST_DCN(inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

89

SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

90

SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

91

SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1107

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

568

uint32_t inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

576

dpp1_construct(dpp, ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

577

&tf_regs[inst], &tf_shift, &tf_mask);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

582

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

592

dcn10_ipp_construct(ipp, ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

593

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

599

struct dc_context *ctx, uint32_t inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

609

dcn10_opp_construct(opp, ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

610

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

617

uint32_t inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

625

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

627

&aux_engine_regs[inst]);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

653

uint32_t inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

661

dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

662

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

709

tgn10->base.inst = instance;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

786

struct dc_context *ctx, unsigned int inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

788

return dce_audio_create(ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

789

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

965

uint32_t inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

973

dcn10_hubp_construct(hubp1, ctx, inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

974

&hubp_regs[inst], &hubp_shift, &hubp_mask);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

986

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/i2caux/engine.h

99

uint32_t inst;

sys/dev/drm/amd/display/dc/inc/compressor.h

50

uint32_t inst;

sys/dev/drm/amd/display/dc/inc/hw/audio.h

59

unsigned int inst;

sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h

85

uint32_t inst;

sys/dev/drm/amd/display/dc/inc/hw/dpp.h

35

int inst;

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

49

int inst;

sys/dev/drm/amd/display/dc/inc/hw/ipp.h

39

unsigned int inst;

sys/dev/drm/amd/display/dc/inc/hw/mem_input.h

71

int inst;

sys/dev/drm/amd/display/dc/inc/hw/opp.h

206

uint32_t inst;

sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h

130

int inst;

sys/dev/drm/amd/display/dc/inc/hw/transform.h

40

int inst;

sys/dev/drm/amd/display/dc/inc/resource.h

61

struct dc_context *ctx, unsigned int inst);

sys/dev/netif/bce/if_bce.c

2707

REG_WR_IND(sc, cpu_reg->inst, 0);

sys/dev/netif/bce/if_bce.c

2768

cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;

sys/dev/netif/bce/if_bce.c

2796

cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;

sys/dev/netif/bce/if_bce.c

2888

cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;

sys/dev/netif/bce/if_bce.c

2980

cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;

sys/dev/netif/bce/if_bce.c

3072

cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;

sys/dev/netif/bce/if_bce.c

3164

cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;

sys/dev/netif/bce/if_bcereg.h

5726

uint32_t inst;

sys/dev/video/bktr/bktr_core.c

2969

volatile unsigned int inst;

sys/dev/video/bktr/bktr_core.c

2991

inst = OP_WRITE | OP_SOL | (cols);

sys/dev/video/bktr/bktr_core.c

3010

*dma_prog++ = inst;

sys/dev/video/bktr/bktr_core.c

3055

*dma_prog++ = inst;

sys/dev/video/bktr/bktr_core.c

3083

volatile unsigned int inst;

sys/dev/video/bktr/bktr_core.c

3112

inst = OP_WRITE123 | OP_SOL | OP_EOL | (cols);

sys/dev/video/bktr/bktr_core.c

3127

*dma_prog++ = inst;

sys/dev/video/bktr/bktr_core.c

3171

*dma_prog++ = inst;

sys/dev/video/bktr/bktr_core.c

3196

volatile unsigned int inst;

sys/dev/video/bktr/bktr_core.c

3212

inst = OP_WRITE123 | OP_SOL | OP_EOL | (cols);

sys/dev/video/bktr/bktr_core.c

3226

*dma_prog++ = inst;

sys/dev/video/bktr/bktr_core.c

3274

*dma_prog++ = inst;

sys/platform/pc64/x86_64/db_trace.c

171

int inst;

sys/platform/pc64/x86_64/db_trace.c

182

inst = db_get_value((int)argp, 4, FALSE);

sys/platform/pc64/x86_64/db_trace.c

183

if ((inst & 0xff) == 0x59) /* popl %ecx */

sys/platform/pc64/x86_64/db_trace.c

185

else if ((inst & 0xffff) == 0xc483) /* addl $Ibs, %esp */

sys/platform/pc64/x86_64/db_trace.c

186

args = ((inst >> 16) & 0xff) / 4;

sys/platform/vkernel64/x86_64/db_trace.c

172

int inst;

sys/platform/vkernel64/x86_64/db_trace.c

183

inst = db_get_value((int)argp, 4, FALSE);

sys/platform/vkernel64/x86_64/db_trace.c

184

if ((inst & 0xff) == 0x59) /* popl %ecx */

sys/platform/vkernel64/x86_64/db_trace.c

186

else if ((inst & 0xffff) == 0xc483) /* addl $Ibs, %esp */

sys/platform/vkernel64/x86_64/db_trace.c

187

args = ((inst >> 16) & 0xff) / 4;

tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c

184

long dur, u_long *res, int do_udp, int inst)

tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c

197

int cpu = inst % cpucnt;

usr.bin/usbhidaction/usbhidaction.c

287

int inst, cinst, u, lo, hi, range, t;

usr.bin/usbhidaction/usbhidaction.c

322

inst = atoi(tmp + 1);

usr.bin/usbhidaction/usbhidaction.c

324

inst = 0;

usr.bin/usbhidaction/usbhidaction.c

410

if (inst == cinst++)