lib/libc/asr/asr_utils.c

215

unpack_u32(struct asr_unpack *p, uint32_t *u32)

lib/libc/asr/asr_utils.c

217

if (unpack_data(p, u32, 4) == -1)

lib/libc/asr/asr_utils.c

220

*u32 = ntohl(*u32);

lib/libc/crypt/chacha_private.h

14

u32 input[16]; /* could be compressed */

lib/libc/crypt/chacha_private.h

21

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

lib/libc/crypt/chacha_private.h

27

(((u32)((p)[0]) ) | \

lib/libc/crypt/chacha_private.h

28

((u32)((p)[1]) << 8) | \

lib/libc/crypt/chacha_private.h

29

((u32)((p)[2]) << 16) | \

lib/libc/crypt/chacha_private.h

30

((u32)((p)[3]) << 24))

lib/libc/crypt/chacha_private.h

55

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

lib/libc/crypt/chacha_private.h

89

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

lib/libc/crypt/chacha_private.h

91

u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15;

lib/libc/crypt/chacha_private.h

92

u32 j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15;

lib/libcrypto/camellia/camellia.c

111

# define RightRotate(x,s) ({u32 ret; asm ("rorl %1,%0":"=r"(ret):"I"(s),"0"(x):"cc"); ret; })

lib/libcrypto/camellia/camellia.c

112

# define LeftRotate(x,s) ({u32 ret; asm ("roll %1,%0":"=r"(ret):"I"(s),"0"(x):"cc"); ret; })

lib/libcrypto/camellia/camellia.c

113

# define GETU32(p) ({u32 r=*(const u32 *)(p); asm("bswapl %0":"=r"(r):"0"(r)); r; })

lib/libcrypto/camellia/camellia.c

114

# define PUTU32(p,v) ({u32 r=(v); asm("bswapl %0":"=r"(r):"0"(r)); *(u32 *)(p)=r; })

lib/libcrypto/camellia/camellia.c

117

# define LeftRotate(x,s) ({u32 ret; asm ("rlwinm %0,%1,%2,0,31":"=r"(ret):"r"(x),"I"(s)); ret; })

lib/libcrypto/camellia/camellia.c

129

# define GETU32(p) (((u32)(p)[0] << 24) ^ ((u32)(p)[1] << 16) ^ ((u32)(p)[2] << 8) ^ ((u32)(p)[3]))

lib/libcrypto/camellia/camellia.c

138

static const u32 Camellia_SBOX[][256] = {

lib/libcrypto/camellia/camellia.c

314

static const u32 SIGMA[] = {

lib/libcrypto/camellia/camellia.c

329

u32 _t0, _t1, _t2, _t3; \

lib/libcrypto/camellia/camellia.c

354

u32 _t0 = _s0 >> (32 - _n); \

lib/libcrypto/camellia/camellia.c

364

u32 s0, s1, s2, s3;

lib/libcrypto/camellia/camellia.c

483

u32 s0, s1, s2, s3;

lib/libcrypto/camellia/camellia.c

484

const u32 *k = keyTable, *kend = keyTable + grandRounds * 16;

lib/libcrypto/camellia/camellia.c

535

u32 s0, s1, s2, s3;

lib/libcrypto/camellia/camellia.c

536

const u32 *k = keyTable+grandRounds * 16, *kend = keyTable+4;

lib/libcrypto/chacha/chacha-merged.c

119

chacha_encrypt_bytes(chacha_ctx *x, const u8 *m, u8 *c, u32 bytes)

lib/libcrypto/chacha/chacha-merged.c

121

u32 x0, x1, x2, x3, x4, x5, x6, x7;

lib/libcrypto/chacha/chacha-merged.c

122

u32 x8, x9, x10, x11, x12, x13, x14, x15;

lib/libcrypto/chacha/chacha-merged.c

123

u32 j0, j1, j2, j3, j4, j5, j6, j7;

lib/libcrypto/chacha/chacha-merged.c

124

u32 j8, j9, j10, j11, j12, j13, j14, j15;

lib/libcrypto/chacha/chacha-merged.c

127

u32 i;

lib/libcrypto/chacha/chacha-merged.c

20

u32 input[16];

lib/libcrypto/chacha/chacha-merged.c

25

static inline void chacha_keysetup(struct chacha_ctx *x, const u8 *k, u32 kbits)

lib/libcrypto/chacha/chacha-merged.c

32

u8 *c, u32 bytes)

lib/libcrypto/chacha/chacha-merged.c

42

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

lib/libcrypto/chacha/chacha-merged.c

48

(((u32)((p)[0])) | \

lib/libcrypto/chacha/chacha-merged.c

49

((u32)((p)[1]) << 8) | \

lib/libcrypto/chacha/chacha-merged.c

50

((u32)((p)[2]) << 16) | \

lib/libcrypto/chacha/chacha-merged.c

51

((u32)((p)[3]) << 24))

lib/libcrypto/chacha/chacha-merged.c

85

chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)

libexec/ld.so/chacha_private.h

14

u32 input[16]; /* could be compressed */

libexec/ld.so/chacha_private.h

21

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

libexec/ld.so/chacha_private.h

27

(((u32)((p)[0]) ) | \

libexec/ld.so/chacha_private.h

28

((u32)((p)[1]) << 8) | \

libexec/ld.so/chacha_private.h

29

((u32)((p)[2]) << 16) | \

libexec/ld.so/chacha_private.h

30

((u32)((p)[3]) << 24))

libexec/ld.so/chacha_private.h

55

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

libexec/ld.so/chacha_private.h

89

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

libexec/ld.so/chacha_private.h

91

u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15;

libexec/ld.so/chacha_private.h

92

u32 j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15;

regress/lib/libc/asr/bin/common.c

505

unpack_u32(struct packed *p, uint32_t *u32)

regress/lib/libc/asr/bin/common.c

507

if (unpack_data(p, u32, 4) == -1)

regress/lib/libc/asr/bin/common.c

510

*u32 = ntohl(*u32);

regress/lib/libssl/bytestring/bytestringtest.c

104

uint32_t u32;

regress/lib/libssl/bytestring/bytestringtest.c

119

CHECK(CBS_get_u24(&prefixed, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

120

CHECK(u32 == 0x30201);

regress/lib/libssl/bytestring/bytestringtest.c

153

uint32_t u32;

regress/lib/libssl/bytestring/bytestringtest.c

162

CHECK(CBS_peek_u24(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

163

CHECK(u32 == 0x10203);

regress/lib/libssl/bytestring/bytestringtest.c

164

CHECK(CBS_peek_u32(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

165

CHECK(u32 == 0x1020304);

regress/lib/libssl/bytestring/bytestringtest.c

166

CHECK(CBS_get_u32(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

167

CHECK(u32 == 0x1020304);

regress/lib/libssl/bytestring/bytestringtest.c

170

CHECK(CBS_peek_u32(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

171

CHECK(u32 == 0x5060708);

regress/lib/libssl/bytestring/bytestringtest.c

172

CHECK(CBS_get_u32(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

173

CHECK(u32 == 0x5060708);

regress/lib/libssl/bytestring/bytestringtest.c

72

uint32_t u32;

regress/lib/libssl/bytestring/bytestringtest.c

82

CHECK(CBS_get_u24(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

83

CHECK(u32 == 0x40506);

regress/lib/libssl/bytestring/bytestringtest.c

84

CHECK(CBS_get_u32(&data, &u32));

regress/lib/libssl/bytestring/bytestringtest.c

85

CHECK(u32 == 0x708090a);

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

34

uint32_t u32;

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

42

ASSERT_INT_EQ(sshbuf_get_u32(p1, &u32), 0);

regress/usr.sbin/snmpd/agentx.c

2405

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2473

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2575

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2667

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2701

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2728

memcpy(&u32, buf, sizeof(u32));

regress/usr.sbin/snmpd/agentx.c

2729

if ((p32toh(header, u32) & 0xF0000000) != 0)

regress/usr.sbin/snmpd/agentx.c

2732

buf += sizeof(u32);

regress/usr.sbin/snmpd/agentx.c

2997

uint32_t u32;

sbin/iked/radius.c

845

uint32_t u32, cause = 0;

sbin/iked/radius.c

940

&u32) == 0) {

sbin/iked/radius.c

944

if (u32 == ((struct sockaddr_in *)&addr4->addr)

sys/arch/amd64/amd64/cpu.c

1387

uint32_t u32[2];

sys/arch/amd64/amd64/cpu.c

1410

enqueue_randomness(t.u32[0]);

sys/arch/amd64/amd64/cpu.c

1411

enqueue_randomness(t.u32[1]);

sys/crypto/chacha_private.h

128

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

sys/crypto/chacha_private.h

130

u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15;

sys/crypto/chacha_private.h

131

u32 j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15;

sys/crypto/chacha_private.h

15

u32 input[16]; /* could be compressed */

sys/crypto/chacha_private.h

22

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

sys/crypto/chacha_private.h

28

(((u32)((p)[0]) ) | \

sys/crypto/chacha_private.h

29

((u32)((p)[1]) << 8) | \

sys/crypto/chacha_private.h

30

((u32)((p)[2]) << 16) | \

sys/crypto/chacha_private.h

31

((u32)((p)[3]) << 24))

sys/crypto/chacha_private.h

56

hchacha20(u32 derived_key[8], const u8 nonce[16], const u8 key[32])

sys/crypto/chacha_private.h

89

memcpy(derived_key + 0, x + 0, sizeof(u32) * 4);

sys/crypto/chacha_private.h

90

memcpy(derived_key + 4, x + 12, sizeof(u32) * 4);

sys/crypto/chacha_private.h

94

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

sys/crypto/rijndael.c

115

static const u32 Te1[256] = {

sys/crypto/rijndael.c

181

static const u32 Te2[256] = {

sys/crypto/rijndael.c

247

static const u32 Te3[256] = {

sys/crypto/rijndael.c

313

static const u32 Td0[256] = {

sys/crypto/rijndael.c

379

static const u32 Td1[256] = {

sys/crypto/rijndael.c

445

static const u32 Td2[256] = {

sys/crypto/rijndael.c

49

static const u32 Te0[256] = {

sys/crypto/rijndael.c

511

static const u32 Td3[256] = {

sys/crypto/rijndael.c

611

static const u32 rcon[] = {

sys/crypto/rijndael.c

617

#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))

sys/crypto/rijndael.c

626

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/crypto/rijndael.c

629

u32 temp;

sys/crypto/rijndael.c

713

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/crypto/rijndael.c

716

u32 temp;

sys/crypto/rijndael.c

756

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

sys/crypto/rijndael.c

759

u32 s0, s1, s2, s3, t0, t1, t2, t3;

sys/crypto/rijndael.c

940

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

sys/crypto/rijndael.c

943

u32 s0, s1, s2, s3, t0, t1, t2, t3;

sys/crypto/rijndael.h

44

u32 ek[4*(AES_MAXROUNDS + 1)]; /* encrypt key schedule */

sys/crypto/rijndael.h

45

u32 dk[4*(AES_MAXROUNDS + 1)]; /* decrypt key schedule */

sys/dev/ic/qwx.c

11802

sizeof(u32) * PSOC_HOST_MAX_PHY_SIZE);

sys/dev/ic/qwx.c

24919

ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,

sys/dev/ic/qwz.c

22770

ath12k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,

sys/dev/ic/qwz.c

9634

sizeof(u32) * PSOC_HOST_MAX_PHY_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1098

u32 log2_max_MBps;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1131

u32 pg_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1413

u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1422

u64 reg_addr, u32 reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1432

u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1433

u32 reg_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1435

u32 reg_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1439

u32 reg_addr, u32 reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1441

u32 reg_addr, u64 reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1444

u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

152

u32 hwip;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1524

u32 tmp = RREG32_SMC(_Reg); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

153

u32 inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

154

u32 seg;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

155

u32 reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1612

const u32 *registers,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1613

const u32 array_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1634

u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1635

u32 reg);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1637

u32 reg, u32 v);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1681

u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1691

u32 clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1827

u32 status;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

399

const u32 major;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

400

const u32 minor;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

401

const u32 rev;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

413

u32 major, u32 minor);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

428

u8 *bios, u32 length_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

488

u32 target_vblank;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

568

u32 num_wb;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

585

int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

586

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

640

u32 codec_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

641

u32 max_width;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

642

u32 max_height;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

643

u32 max_pixels_per_frame;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

644

u32 max_level;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

655

const u32 codec_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

665

u8 *bios, u32 length_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

666

int (*read_register)(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

667

u32 sh_num, u32 reg_offset, u32 *value);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

672

u32 (*get_xclk)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

674

int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

675

int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

680

u32 (*get_config_memsize)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

759

u32 reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

465

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

822

u32 instidhi, instidlo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

83

static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

181

u32 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

195

int (*get_valid_aca_count)(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

210

u32 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

229

u32 val = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

230

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

474

if (val & (u32) 0x1)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

505

u32 val = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

506

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

542

if (val & (u32) 0x1)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1049

u32 *sbdf)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1111

u32 sbdf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1172

u32 sbdf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1194

u32 sbdf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

205

static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

225

static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

587

static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

716

u32 retry = 3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

948

static struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u32 sbdf)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

963

struct amdgpu_acpi_xcc_info *xcc_info, u32 sbdf)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

118

sizeof(u32)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

121

*start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

727

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

818

int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

819

u32 inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

177

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

264

int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

265

u32 inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

353

uint64_t size, u32 alloc_flag, int8_t xcp_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

355

uint64_t size, u32 alloc_flag, int8_t xcp_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

224

u32 pasid, unsigned int vmid, uint32_t xcc_inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

95

static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

93

static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

87

static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

101

int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

27

int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1491

static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

170

uint64_t size, u32 alloc_flag, int8_t xcp_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1703

u32 domain, alloc_domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

266

uint64_t size, u32 alloc_flag, int8_t xcp_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

312

u32 alloc_flags = bo->kfd_bo->alloc_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1017

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1115

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1168

u32 eng_clock, u32 mem_clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1172

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1286

u32 size = le16_to_cpu(v3->sHeader.usStructureSize);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1287

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1457

u32 i = 0, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1499

while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1501

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1505

(u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1510

(u32)le32_to_cpu(*((u32 *)reg_data + j));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1524

if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1600

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1611

u32 backlight_level)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1613

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1624

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1644

u32 src_tmp[5], dst_tmp[5];

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

223

u32 reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

901

int id, u32 clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

102

u32 mclk_max;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

103

u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

122

u32 smio_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

126

u32 count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

127

u32 mask_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

128

u32 phase_delay;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

153

int id, u32 clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

157

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

163

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

168

u32 eng_clock, u32 mem_clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

199

u32 backlight_level);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

205

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

28

u32 post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

32

u32 reserved : 6;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

33

u32 whole_fb_div : 12;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

34

u32 frac_fb_div : 14;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

36

u32 frac_fb_div : 14;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

37

u32 whole_fb_div : 12;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

38

u32 reserved : 6;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

41

u32 fb_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

43

u32 ref_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

46

u32 vco_mode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

47

u32 real_clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

49

u32 post_divider;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

50

u32 flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

57

u32 reserved : 8;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

58

u32 clkfrac : 12;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

59

u32 clkf : 12;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

61

u32 clkf : 12;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

62

u32 clkfrac : 12;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

63

u32 reserved : 8;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

66

u32 fb_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

68

u32 post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

69

u32 bwcntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

70

u32 dll_speed;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

71

u32 vco_mode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

72

u32 yclk_sel;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

73

u32 qdr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

74

u32 half_rate;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

95

u32 mclk[MAX_AC_TIMING_ENTRIES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

108

u32 start_addr, fw_size, drv_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

120

(u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

137

u32 fw_start_addr, fw_size, drv_start_addr, drv_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

311

u32 mem_channel_number;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

312

u32 mem_channel_width;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

313

u32 module_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

54

u32 fw_cap = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

557

u32 umc_config1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

623

u32 fw_cap;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

639

u32 fw_cap;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

81

u32 fw_cap;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

899

u32 fw_cap;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

667

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

669

u32 *dw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

670

u32 i, length_dw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

671

u32 rom_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

672

u32 rom_index_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

673

u32 rom_data_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

687

dw_ptr = (u32 *)bios;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

454

static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

458

u32 chunk, rec_len = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

491

u32 chunk, ent_sz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.c

39

u32 domain, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.h

33

u32 domain, uint32_t size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

139

static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

204

static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

205

const u32 ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

293

u32 *stable_pstate)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

324

u32 current_stable_pstate;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

357

u32 stable_pstate)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

361

u32 current_stable_pstate;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

434

int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

435

u32 ring, struct drm_sched_entity **entity)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

509

u32 i, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

639

bool set, u32 *stable_pstate)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h

76

int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h

77

u32 ring, struct drm_sched_entity **entity);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1302

u32 value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1449

u32 value = adev->gfx.gfx_off_state;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1451

r = put_user(value, (u32 *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1486

u32 value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1492

r = put_user(value, (u32 *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

230

static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1040

u32 reg_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1126

u32 reg_addr, u32 reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1147

u64 reg_addr, u32 reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1195

u32 reg_addr, u64 reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1211

writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1216

writel((u32)(reg_data >> 32), pcie_data_offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1249

writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1258

writel((u32)(reg_data >> 32), pcie_data_offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1277

u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1514

const u32 *registers,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1515

const u32 array_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1517

u32 tmp, reg, and_mask, or_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1638

int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1663

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2496

u32 major, u32 minor)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4482

u32 max_MBps;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5884

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5924

u32 memsize = adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7251

u32 memsize;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7584

u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7585

u32 reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7588

u32 r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7602

u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

956

u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

957

u32 reg_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

962

u32 r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

979

u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

983

u32 r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

39

u32 (*get_fb_channel_number)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

40

u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1705

u32 u, mall_size_per_umc, m_s_present, half_use;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

280

u32 msg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

793

u32 base_addr[] __counted_by(num_base_addresses);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1448

u32 src_v = 1, dst_v = 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1449

u32 src_h = 1, dst_h = 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1556

u32 vbl = 0, position = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1805

u32 color)

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

641

int num_formats, u32 format)

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

654

amdgpu_lookup_format_info(u32 format, uint64_t modifier)

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

50

amdgpu_lookup_format_info(u32 format, uint64_t modifier);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

120

u32 domains = bo->allowed_domains;

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

284

u32 domain = amdgpu_display_supported_domains(adev, bo->flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

351

u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

352

void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

353

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

354

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

36

u32 num_kernel_doorbells;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

103

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

137

return db_bo_offset / sizeof(u32) + doorbell_index *

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

159

size = ALIGN(adev->doorbell.num_kernel_doorbells * sizeof(u32), PAGE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

162

adev->mes.db_start_dw_offset = size / sizeof(u32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

178

adev->doorbell.num_kernel_doorbells = size / sizeof(u32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

226

min_t(u32, adev->doorbell.size / sizeof(u32),

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

36

u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

59

void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

80

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

181

static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

182

u8 *eeprom_buf, u32 buf_size, bool read)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

227

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

228

u32 bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

235

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

236

u32 bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

92

static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

93

u8 *eeprom_buf, u32 buf_size, bool read)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.h

30

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.h

31

u32 bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.h

34

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.h

35

u32 bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c

206

u32 pixel_clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

68

static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

772

u32 seq, last_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

829

u32 seq, last_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

84

static u32 amdgpu_fence_read(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

87

u32 seq = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

121

u32 addr, fru_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

36

static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

1374

u32 domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

245

int alignment, u32 initial_domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

562

initial_domain = (u32)(0xffffffff & args->in.domains);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.h

45

int alignment, u32 initial_domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1985

static void amdgpu_gfx_kfd_sch_ctrl(struct amdgpu_device *adev, u32 idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2042

u32 i, idx, fences = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2091

u32 idx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2146

u32 idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2186

u32 idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2216

u32 i, fences = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2301

u32 amdgpu_gfx_csb_preamble_start(u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2303

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2325

u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2329

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2352

void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2368

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2394

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2438

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2465

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

357

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

386

u32 domain = AMDGPU_GEM_DOMAIN_GTT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

884

int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

110

u32 num_mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

111

u32 num_pipe_per_mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

112

u32 num_queue_per_pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

327

u32 shadow_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

328

u32 shadow_alignment;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

329

u32 csa_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

330

u32 csa_alignment;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

336

void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

337

u32 sh_num, u32 instance, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

346

void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

347

u32 queue, u32 vmid, u32 xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

402

u32 xcp_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

563

static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

565

return (u32)((1ULL << bit_width) - 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

608

int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

645

u32 amdgpu_gfx_csb_preamble_start(u32 *buffer);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

646

u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

647

void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1508

amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1534

u32 supp_modes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1620

u32 start_addr = 0, size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

968

u32 tmp, reg, i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

465

amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

118

u32 pasid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

44

static u32 amdgpu_pasid_xa_next;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

49

u32 pasid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

65

u32 pasid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

87

void amdgpu_pasid_free(u32 pasid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

74

void amdgpu_pasid_free(u32 pasid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

76

u32 pasid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

232

u32 wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

288

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

318

uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

47

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

116

uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

54

u32 doorbell_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

89

u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

92

uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

42

u32 hwip;

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

43

u32 instance;

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

44

u32 segment;

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

45

u32 reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

46

u32 data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

47

u32 addr_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

84

u32 ip_map[][2] = {

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

446

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h

101

u32 retry_cam_doorbell_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

361

u32 i, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

389

u32 i, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

467

const struct amdgpu_hwip_reg_entry *reg, u32 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

492

u32 inst_off, inst_id, is_powered;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

521

u32 inst_off, is_powered;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

547

static inline bool amdgpu_jpeg_reg_valid(u32 reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

571

u32 i, reg, res, cond, type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

149

u32 *ip_dump;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

150

u32 reg_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

177

const struct amdgpu_hwip_reg_entry *reg, u32 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1493

u32 pasid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1563

u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1569

u32 count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

626

u32 count, inst_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

969

dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

971

dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

196

adev->mes.hung_queue_db_array_size * sizeof(u32),

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

396

u32 *hung_db_array)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

400

u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

413

adev->mes.hung_queue_db_array_size * sizeof(u32));

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

48

mes->doorbell_bitmap = bitmap_zalloc(PAGE_SIZE / sizeof(u32), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

614

u32 *ucode_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

654

ucode_ptr = (u32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

425

u32 *hung_db_array);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

251

u32 offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

253

u32 id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

266

u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

276

u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

281

u32 *vbl, u32 *position);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

333

u32 firmware_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

480

u32 pll_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

490

u32 adjusted_clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

492

u32 pll_reference_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

493

u32 pll_post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

494

u32 pll_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

498

u32 line_time;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

499

u32 lb_vblank_lead_lines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

567

u32 reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

568

u32 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

569

u32 shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

579

u32 router_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

672

u32 pixel_clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

100

u32 (*get_rom_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

102

u32 (*get_memory_partition_mode)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

103

u32 *supp_modes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

30

u32 ref_and_mask_cp0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

31

u32 ref_and_mask_cp1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

32

u32 ref_and_mask_cp2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

33

u32 ref_and_mask_cp3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

34

u32 ref_and_mask_cp4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

35

u32 ref_and_mask_cp5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

36

u32 ref_and_mask_cp6;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

37

u32 ref_and_mask_cp7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

38

u32 ref_and_mask_cp8;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

39

u32 ref_and_mask_cp9;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

40

u32 ref_and_mask_sdma0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

41

u32 ref_and_mask_sdma1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

42

u32 ref_and_mask_sdma2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

43

u32 ref_and_mask_sdma3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

44

u32 ref_and_mask_sdma4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

45

u32 ref_and_mask_sdma5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

46

u32 ref_and_mask_sdma6;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

47

u32 ref_and_mask_sdma7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

60

u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

61

u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

62

u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

63

u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

64

u32 (*get_pcie_index_hi_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

65

u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

66

u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

67

u32 (*get_rev_id)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

69

u32 (*get_memsize)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

110

void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

116

u32 c = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1190

u32 metadata_size, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

248

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

347

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

384

struct dma_buf *dma_buf, u32 domain, struct amdgpu_bo **bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

559

unsigned long size, u32 domain)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

933

int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

104

u32 preferred_domains;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

105

u32 allowed_domains;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

134

u32 metadata_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

154

static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

253

void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

260

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

264

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

267

struct dma_buf *dbuf, u32 domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

287

int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

339

unsigned size, u32 align, u32 domain);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

51

u32 bo_ptr_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

52

u32 domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

53

u32 preferred_domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

124

u32 freq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

125

u32 *dot_clock_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

126

u32 *fb_div_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

127

u32 *frac_fb_div_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

128

u32 *ref_div_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

129

u32 *post_div_p)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

269

u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

274

u32 pll_in_use = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

330

u32 adjusted_clock, test_adjusted_clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

29

u32 freq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

30

u32 *dot_clock_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

31

u32 *fb_div_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

32

u32 *frac_fb_div_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

33

u32 *ref_div_p,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

34

u32 *post_div_p);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

35

u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

281

u32 training_cnt;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

343

u32 instance_mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3444

u32 timeout = MAX_UMC_POISON_POLLING_TIME_ASYNC;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3681

u32 max_eeprom_records_count = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5319

u32 instance)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5321

u32 socket_id, aid_id, hbm_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5322

u32 fw_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5323

u32 boot_error;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5394

u32 instance)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5397

u32 reg_data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5414

void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5416

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

625

u32 err_list_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

982

void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1213

u32 ai = RAS_RI_TO_AI(control, s);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

191

control->i2c_address = ((u32) i2c_addr) << 16;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

240

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

253

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

297

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

298

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

310

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

311

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

600

u8 *buf, const u32 fri, const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

603

u32 buf_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

633

const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

637

u32 a, b, i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

691

u32 g0, g1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

717

u32 g0, g1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

758

u32 buf_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

867

const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

921

u8 *buf, const u32 fri, const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

924

u32 buf_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

964

const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

970

u32 g0, g1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

102

u32 ras_fri;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

108

u32 ras_max_record_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

116

u32 bad_channel_bitmap;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

153

struct eeprom_table_record *records, const u32 num);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

156

struct eeprom_table_record *records, const u32 num);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

59

u32 padding[64 - 1];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

71

u32 i2c_address;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

78

u32 ras_header_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

79

u32 ras_info_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

80

u32 ras_record_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

84

u32 ras_num_recs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

89

u32 ras_num_bad_pages;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

92

u32 ras_num_mca_recs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

95

u32 ras_num_pa_recs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

239

u32 *num_sched;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

240

u32 hw_ip;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

827

u32 reset_type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

108

u32 num_scheds;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

210

u32 nop;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

312

u32 *rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

369

u32 idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

370

u32 xcc_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

371

u32 xcp_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

372

u32 me;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

373

u32 pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

374

u32 queue;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

380

u32 doorbell_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

392

u32 *wptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

395

u32 *fence_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

398

u32 trail_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

401

u32 *trail_fence_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

404

u32 *cond_exe_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

406

u32 *set_q_mode_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

550

static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, uint32_t idx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

583

u32 reset_type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

130

u32 dws;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

192

u32 *dst_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

194

u32 bo_offset = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

195

u32 table_offset, table_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

89

int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

91

const u32 *src_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

92

u32 *dst_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

93

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

239

u32 (*get_csb_size)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

254

void (*get_csb_buffer)(struct amdgpu_device *adev, u32 *buffer);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

279

const u32 *reg_list;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

280

u32 reg_list_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

286

u32 clear_state_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

291

u32 cp_table_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

298

u32 save_and_restore_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

299

u32 clear_state_descriptor_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

300

u32 avail_scratch_ram_locations;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

301

u32 reg_restore_list_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

302

u32 reg_list_format_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

303

u32 reg_list_format_separate_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

304

u32 starting_offsets_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

305

u32 reg_list_format_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

306

u32 reg_list_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

307

u32 reg_list_format_direct_reg_list_length;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

308

u32 save_restore_list_cntl_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

309

u32 save_restore_list_gpm_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

310

u32 save_restore_list_srm_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

311

u32 rlc_iram_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

312

u32 rlc_dram_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

313

u32 rlcp_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

314

u32 rlcv_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

315

u32 global_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

316

u32 se0_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

317

u32 se1_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

318

u32 se2_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

319

u32 se3_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

321

u32 *register_list_format;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

322

u32 *register_restore;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

355

int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sa.c

49

unsigned int size, u32 suballoc_align, u32 domain)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

204

u32 instance, bool duplicate)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

537

static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

193

int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

56

int (*soft_reset_kernel_queue)(struct amdgpu_device *adev, u32 instance_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h

34

u32 num_sem;

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

39

u32 (*get_rom_index_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

40

u32 (*get_rom_data_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

43

u32 (*get_die_id)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

44

u32 (*get_socket_id)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

121

__field(u32, pages)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

122

__field(u32, type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

123

__field(u32, prefer)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

124

__field(u32, allow)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

125

__field(u32, visible)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

149

__field(u32, ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

150

__field(u32, dw)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

151

__field(u32, fences)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

175

__field(u32, num_ibs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

198

__field(u32, num_ibs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

219

__field(u32, pasid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

221

__field(u32, ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

222

__field(u32, vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

223

__field(u32, vm_hub)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

225

__field(u32, needs_flush)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

372

__field(u32, count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

373

__field(u32, incr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

397

__field(u32, count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

418

__field(u32, vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

419

__field(u32, vm_hub)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

530

__field(u32, new_placement)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

531

__field(u32, old_placement)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umr.h

46

u32 xcc_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umr.h

50

u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umr.h

52

u32 thread, vpgr_or_sgpr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1024

u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1053

u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1080

u32 idx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1082

u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1115

u32 idx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1117

u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

34

u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

345

db_size = sizeof(u32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

350

db_size = sizeof(u32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

37

u32 userq_ip_mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

137

u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

144

u32 idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

146

u32 idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

71

u32 xcp_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

491

u32 *bo_handles_write, num_write_bo_handles;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

492

u32 *syncobj_handles, num_syncobj_handles;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

493

u32 *bo_handles_read, num_read_bo_handles;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

509

size_mul(sizeof(u32), num_syncobj_handles));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

530

sizeof(u32) * num_read_bo_handles);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

553

sizeof(u32) * num_write_bo_handles);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

682

u32 *syncobj_handles, *timeline_points, *timeline_handles, *bo_handles_read, *bo_handles_write;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

683

u32 num_syncobj, num_read_bo_handles, num_write_bo_handles;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

706

size_mul(sizeof(u32), num_read_bo_handles));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

712

size_mul(sizeof(u32), num_write_bo_handles));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

720

size_mul(sizeof(u32), num_syncobj));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

728

sizeof(u32) * num_points);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

735

sizeof(u32) * num_points);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

963

u32 index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1401

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1426

u32 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1560

const struct amdgpu_hwip_reg_entry *reg, u32 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1585

u32 inst_off;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1614

u32 inst_off;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

369

u32 reg_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

567

const struct amdgpu_hwip_reg_entry *reg, u32 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vf_error.c

54

u32 data1, data2, data3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1021

u32 acc_flags, u32 hwip,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1022

bool write, u32 *rlcg_flag)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1053

u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1151

u32 offset, u32 value,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1152

u32 acc_flags, u32 hwip, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1154

u32 rlcg_flag;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1171

u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1172

u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1174

u32 rlcg_flag;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1377

u32 *more)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

744

static u32 amdgpu_virt_init_detect_asic(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

783

static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

122

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

123

(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

451

u32 offset, u32 value,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

452

u32 acc_flags, u32 hwip, u32 xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

453

u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

454

u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

461

u32 acc_flags, u32 hwip,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

462

bool write, u32 *rlcg_flag);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

463

u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

94

u32 data1, u32 data2, u32 data3);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2526

amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2582

amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3033

bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3034

u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

595

amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

602

bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

603

u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

481

pages_per_block = max_t(u32, pages_per_block,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

553

pages_per_block = max_t(u32, 2UL << (20UL - PAGE_SHIFT),

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

257

int amdgpu_xcp_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

482

u32 hw_ip, u32 hw_prio,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

487

u32 sel_xcp_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

492

u32 least_ref_cnt = ~0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

496

u32 total_ref_cnt;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

670

int amdgpu_xcp_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

682

int amdgpu_xcp_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

160

int amdgpu_xcp_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

179

u32 hw_ip, u32 hw_prio,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

185

int amdgpu_xcp_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

186

int amdgpu_xcp_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

314

static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link_num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

316

const u32 smn_xgmi_6_4_pcs_state_hist1[2] = { 0x11a00070, 0x11b00070 };

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

317

const u32 smn_xgmi_6_4_1_pcs_state_hist1[2] = { 0x12100070,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

319

u32 i, n;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

343

u32 xgmi_state_reg_val;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

390

u32 flags = 0;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

538

u32 mask, avail_inst, inst_mask = adev->sdma.sdma_mask;

sys/dev/pci/drm/amd/amdgpu/atom.c

232

val = get_unaligned_le32((u32 *)&ctx->ps[idx]);

sys/dev/pci/drm/amd/amdgpu/atom.h

122

u32 reg, uint32_t val); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

125

u32 reg, uint32_t val); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

128

u32 reg, uint32_t val); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

304

static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

313

u32 adjusted_clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

315

u32 dp_clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

316

u32 clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

471

u32 dispclk)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

525

u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

526

u32 freq, u8 clk_type, u8 clk_src)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

531

u32 ret_freq = 0;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

563

static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

576

u32 crtc_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

578

u32 encoder_mode,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

579

u32 encoder_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

580

u32 clock,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

581

u32 ref_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

582

u32 fb_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

583

u32 frac_fb_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

584

u32 post_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

823

u32 pll_clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

824

u32 clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

825

u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

866

u32 step_size;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

867

u32 amount = (((fb_div * 10) + frac_fb_div) *

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

868

(u32)amdgpu_crtc->ss.percentage) /

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

869

(100 * (u32)amdgpu_crtc->ss.percentage_divider);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

874

step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

877

step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

39

u32 dispclk);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

40

u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

41

u32 freq, u8 clk_type, u8 clk_src);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

43

u32 crtc_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

45

u32 encoder_mode,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

46

u32 encoder_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

47

u32 clock,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

48

u32 ref_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

49

u32 fb_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

50

u32 frac_fb_div,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

51

u32 post_div,

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1205

u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1764

u32 bios_0_scratch;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

46

u32 bios_2_scratch;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

60

u32 bios_2_scratch;

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

157

u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.h

29

u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap);

sys/dev/pci/drm/amd/amdgpu/cik.c

1013

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/cik.c

1015

u32 *dw_ptr;

sys/dev/pci/drm/amd/amdgpu/cik.c

1017

u32 i, length_dw;

sys/dev/pci/drm/amd/amdgpu/cik.c

1027

dw_ptr = (u32 *)bios;

sys/dev/pci/drm/amd/amdgpu/cik.c

1123

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/cik.c

1124

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/cik.c

1218

static int cik_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/cik.c

1219

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/cik.c

1238

u32 gmcon_reng_execute;

sys/dev/pci/drm/amd/amdgpu/cik.c

1239

u32 gmcon_misc;

sys/dev/pci/drm/amd/amdgpu/cik.c

1240

u32 gmcon_misc3;

sys/dev/pci/drm/amd/amdgpu/cik.c

1342

u32 i;

sys/dev/pci/drm/amd/amdgpu/cik.c

1446

static u32 cik_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/cik.c

1451

static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/pci/drm/amd/amdgpu/cik.c

1452

u32 cntl_reg, u32 status_reg)

sys/dev/pci/drm/amd/amdgpu/cik.c

1481

static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/pci/drm/amd/amdgpu/cik.c

1493

static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/amd/amdgpu/cik.c

1497

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/cik.c

152

static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/cik.c

1533

u32 speed_cntl, current_data_rate;

sys/dev/pci/drm/amd/amdgpu/cik.c

155

u32 r;

sys/dev/pci/drm/amd/amdgpu/cik.c

1575

u32 max_lw, current_lw, tmp;

sys/dev/pci/drm/amd/amdgpu/cik.c

165

static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/cik.c

1691

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/cik.c

177

static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/cik.c

1774

u32 lnkcap;

sys/dev/pci/drm/amd/amdgpu/cik.c

180

u32 r;

sys/dev/pci/drm/amd/amdgpu/cik.c

189

static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/cik.c

1933

u32 clock_cntl, pc;

sys/dev/pci/drm/amd/amdgpu/cik.c

199

static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/cik.c

202

u32 r;

sys/dev/pci/drm/amd/amdgpu/cik.c

211

static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/cik.c

221

static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/cik.c

224

u32 r;

sys/dev/pci/drm/amd/amdgpu/cik.c

233

static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/cik.c

243

static const u32 bonaire_golden_spm_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

248

static const u32 bonaire_golden_common_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

256

static const u32 bonaire_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

301

static const u32 bonaire_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

387

static const u32 spectre_golden_spm_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

392

static const u32 spectre_golden_common_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

400

static const u32 spectre_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

429

static const u32 spectre_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

520

static const u32 kalindi_golden_spm_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

525

static const u32 kalindi_golden_common_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

533

static const u32 kalindi_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

567

static const u32 kalindi_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

626

static const u32 hawaii_golden_spm_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

631

static const u32 hawaii_golden_common_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

640

static const u32 hawaii_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

680

static const u32 hawaii_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

791

static const u32 godavari_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/cik.c

917

static u32 cik_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/cik.c

919

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/cik.c

945

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/cik.c

947

u32 srbm_gfx_cntl =

sys/dev/pci/drm/amd/amdgpu/cik.c

969

u32 bus_cntl;

sys/dev/pci/drm/amd/amdgpu/cik.c

970

u32 d1vga_control = 0;

sys/dev/pci/drm/amd/amdgpu/cik.c

971

u32 d2vga_control = 0;

sys/dev/pci/drm/amd/amdgpu/cik.c

972

u32 vga_render_control = 0;

sys/dev/pci/drm/amd/amdgpu/cik.c

973

u32 rom_cntl;

sys/dev/pci/drm/amd/amdgpu/cik.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

110

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

188

static u32 cik_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

191

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

253

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

351

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

362

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

379

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

380

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

62

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

63

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

81

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

82

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1025

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1049

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1051

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1090

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

163

u32 rptr;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

228

u32 extra_bits = vmid & 0xf;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

249

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

251

u32 ref_and_mask;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

310

u32 rb_cntl;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

343

u32 f32_cntl, phase_quantum = 0;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

400

u32 me_cntl;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

429

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

430

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

47

static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

532

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

59

u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

606

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

658

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

801

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

852

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

876

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

897

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

238

static const u32 si_SECT_CONTEXT_def_2[] = {

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

24

static const u32 si_SECT_CONTEXT_def_1[] = {

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

512

static const u32 si_SECT_CONTEXT_def_3[] = {

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

520

static const u32 si_SECT_CONTEXT_def_4[] = {

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

679

static const u32 si_SECT_CONTEXT_def_5[] = {

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

682

static const u32 si_SECT_CONTEXT_def_6[] = {

sys/dev/pci/drm/amd/amdgpu/clearstate_si.h

685

static const u32 si_SECT_CONTEXT_def_7[] = {

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

109

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

190

static u32 cz_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

193

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

244

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

347

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

358

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

373

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

375

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

62

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

63

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

81

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

82

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1028

u32 lb_size, u32 num_heads)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1032

u32 active_time;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1033

u32 line_time = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1034

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1035

u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1038

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1039

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1040

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1041

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1042

line_time = min_t(u32, line_time, 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1072

latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1111

latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1160

u32 num_heads = 0, lb_size;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1180

u32 offset, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1214

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1234

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

124

static const u32 golden_settings_tonga_a11[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1280

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

131

static const u32 tonga_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

136

static const u32 golden_settings_fiji_a10[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1379

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1424

static const u32 pin_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

143

static const u32 fiji_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1483

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1531

static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1538

u32 dto_phase = 24 * 1000;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1539

u32 dto_modulo = clock;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1540

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1572

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

172

static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

173

u32 block_offset, u32 reg)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

176

u32 r;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1804

static const u32 vga_control_regs[6] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1818

u32 vga_control;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1851

u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1852

u32 pipe_config;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1853

u32 tmp, viewport_w, viewport_h;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

187

u32 block_offset, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

197

static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2023

(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2025

(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2092

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2109

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2237

static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2242

u32 pll_in_use;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2292

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2303

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

239

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

260

u32 *vbl, u32 *position)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2981

u32 srbm_soft_reset = 0, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3010

u32 lb_interrupt_mask;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3039

u32 lb_interrupt_mask;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

306

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3069

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3147

u32 reg;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3221

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3236

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3251

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

333

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

389

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

408

static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

415

u32 crtc_hung = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

416

u32 crtc_status[6];

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

417

u32 i, j, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

446

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

484

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

512

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

57

static const u32 crtc_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

594

static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

598

u32 tmp, buffer_alloc, i, mem_cfg;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

599

u32 pipe_offset = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

668

static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

67

static const u32 hpd_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

670

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

696

u32 dram_channels; /* number of dram channels */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

697

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

698

u32 sclk; /* engine clock in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

699

u32 disp_clk; /* display clock in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

700

u32 src_width; /* viewport width */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

701

u32 active_time; /* active display time in ns */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

702

u32 blank_time; /* blank time in ns */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

705

u32 num_heads; /* number of active crtcs */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

706

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

707

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

708

u32 vtaps; /* vertical scaler taps */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

720

static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

749

static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

778

static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

807

static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

838

static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

841

u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

842

u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

843

u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

857

static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

890

static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

893

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

894

u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

895

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

896

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

897

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

898

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

900

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

901

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

902

u32 tmp, dmif_size = 12288;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

991

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

992

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

993

u32 latency_tolerant_lines;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

994

u32 latency_hiding;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1057

static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1062

u32 tmp, buffer_alloc, i;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1063

u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1129

u32 num_heads = 0, lb_size;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1154

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1207

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1252

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1308

u32 offset;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

135

static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1356

u32 value = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

136

u32 block_offset, u32 reg)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

139

u32 r;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1402

static const u32 pin_offsets[7] =

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1468

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1485

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

150

u32 block_offset, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1528

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1558

static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1564

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1598

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

161

static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1642

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1655

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1692

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1847

static const u32 vga_control_regs[6] =

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1862

u32 vga_control;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1889

u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1890

u32 viewport_w, viewport_h;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2041

(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2043

(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

218

(u32)crtc_base);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2216

static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2221

u32 pll_in_use;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

224

u32 *vbl, u32 *position)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

270

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

287

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2919

u32 srbm_soft_reset = 0, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2948

u32 reg_block, interrupt_mask;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3007

u32 dc_hpd_int_cntl;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

312

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3122

u32 reg;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

358

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

376

static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

383

u32 crtc_hung = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

384

u32 crtc_status[6];

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

385

u32 i, j, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

436

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

464

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

521

static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

523

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

549

u32 dram_channels; /* number of dram channels */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

550

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

551

u32 sclk; /* engine clock in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

552

u32 disp_clk; /* display clock in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

553

u32 src_width; /* viewport width */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

554

u32 active_time; /* active display time in ns */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

555

u32 blank_time; /* blank time in ns */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

558

u32 num_heads; /* number of active crtcs */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

559

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

560

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

561

u32 vtaps; /* vertical scaler taps */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

573

static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

602

static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

631

static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

660

static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

67

static const u32 crtc_offsets[6] =

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

691

static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

694

u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

695

u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

696

u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

710

static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

743

static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

746

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

747

u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

748

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

749

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

750

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

751

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

753

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

754

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

755

u32 tmp, dmif_size = 12288;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

77

static const u32 hpd_offsets[] =

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

844

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

845

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

846

u32 latency_tolerant_lines;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

847

u32 latency_hiding;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

881

u32 lb_size, u32 num_heads)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

885

u32 dram_channels;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

886

u32 active_time;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

887

u32 line_time = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

888

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

889

u32 priority_a_mark = 0, priority_b_mark = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

890

u32 priority_a_cnt = PRIORITY_OFF;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

891

u32 priority_b_cnt = PRIORITY_OFF;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

892

u32 tmp, arb_control3, lb_vblank_lead_lines = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

896

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

897

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

898

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

899

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

900

line_time = min_t(u32, line_time, 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

961

latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

963

latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1025

latency_watermark_a = min_t(u32, dce_v8_0_latency_watermark(&wm_high), 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1064

latency_watermark_b = min_t(u32, dce_v8_0_latency_watermark(&wm_low), 65535);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1115

u32 num_heads = 0, lb_size;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1135

u32 offset, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1169

u32 offset;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1190

u32 tmp = 0, offset;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

123

static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

124

u32 block_offset, u32 reg)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1251

u32 offset, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

127

u32 r;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1301

u32 offset;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1350

u32 value = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

138

u32 block_offset, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1396

static const u32 pin_offsets[7] = {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

148

static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1500

static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1507

u32 dto_phase = 24 * 1000;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1508

u32 dto_modulo = clock;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1751

static const u32 vga_control_regs[6] = {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1765

u32 vga_control;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1798

u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1799

u32 pipe_config;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1800

u32 viewport_w, viewport_h;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1953

(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1955

(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

208

u32 *vbl, u32 *position)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2145

static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2150

u32 pll_in_use;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

254

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

271

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2891

u32 srbm_soft_reset = 0, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2920

u32 reg_block, lb_interrupt_mask;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

296

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2971

u32 reg_block, lb_interrupt_mask;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3023

u32 dc_hpd_int_cntl;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3138

u32 reg;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

342

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

360

static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

367

u32 crtc_hung = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

368

u32 crtc_status[6];

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

369

u32 i, j, tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

397

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

442

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

470

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

549

static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

553

u32 tmp, buffer_alloc, i;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

554

u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

57

static const u32 crtc_offsets[6] = {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

621

static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

623

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

649

u32 dram_channels; /* number of dram channels */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

650

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

651

u32 sclk; /* engine clock in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

652

u32 disp_clk; /* display clock in kHz */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

653

u32 src_width; /* viewport width */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

654

u32 active_time; /* active display time in ns */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

655

u32 blank_time; /* blank time in ns */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

658

u32 num_heads; /* number of active crtcs */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

659

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

66

static const u32 hpd_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

660

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

661

u32 vtaps; /* vertical scaler taps */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

673

static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

702

static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

731

static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

760

static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

791

static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

794

u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

795

u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

796

u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

810

static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

843

static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

846

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

847

u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

848

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

849

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

850

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

851

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

853

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

854

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

855

u32 tmp, dmif_size = 12288;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

944

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

945

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

946

u32 latency_tolerant_lines;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

947

u32 latency_hiding;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

981

u32 lb_size, u32 num_heads)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

985

u32 active_time;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

986

u32 line_time = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

987

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

988

u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

991

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

992

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

993

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

994

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

995

line_time = min_t(u32, line_time, 65535);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

106

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

30

static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

46

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

57

static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

59

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

68

static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

82

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

216

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

267

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

278

static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

280

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

295

static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

309

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

339

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

42

static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10065

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10067

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10078

static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10080

u32 disabled_mask =

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10082

u32 efuse_setting = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10083

u32 vbios_setting = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10098

static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10100

u32 wgp_idx, wgp_active_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10101

u32 cu_bitmap_per_wgp, cu_active_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10120

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10176

static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3685

static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3686

u32 sh_num, u32 instance, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3687

static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3696

static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3898

(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3903

(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3908

(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3924

(const u32)ARRAY_SIZE(golden_settings_gc_10_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3927

(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3932

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3935

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3940

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3943

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3948

(const u32)ARRAY_SIZE(golden_settings_gc_10_3));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3951

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3956

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3961

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3966

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3971

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3976

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3982

(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3987

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3992

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4295

static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4297

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4325

static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4327

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4418

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4421

u32 *fw = NULL;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4548

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4582

u32 gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5056

static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5057

u32 sh_num, u32 instance, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5059

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5083

static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5085

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5102

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5103

u32 active_rbs = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5104

u32 bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5105

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5133

static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5258

u32 tmp, wgp_active_bitmap = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5259

u32 gcrd_targets_disable_tcp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5260

u32 utcl_invreq_disable = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5266

u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5275

u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5341

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5377

static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5393

static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5421

u32 tmp, cp_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5470

u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6075

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6446

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6457

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6502

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6503

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6650

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6651

u32 usec_timeout = 50000; /* Wait for 50 ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6749

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7594

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7611

u32 grbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7612

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8301

u32 reg, pre_data, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8352

static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8359

u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8615

u32 ref_and_mask, reg_mem_engine;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8647

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8684

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9097

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9233

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9279

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9324

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9520

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h

25

static const u32 gfx_10_1_10_cleaner_shader_hex[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h

60

static const u32 gfx_10_3_0_cleaner_shader_hex[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1046

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1952

static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1953

u32 sh_num, u32 instance, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1955

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1979

static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1981

u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1997

static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1999

u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2000

u32 rb_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2018

u32 rb_bitmap_per_sa;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2019

u32 rb_bitmap_width_per_sa;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2020

u32 max_sa;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2021

u32 active_sa_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2022

u32 global_active_rb_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2023

u32 active_rb_bitmap = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2024

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2130

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2169

static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2185

static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2213

u32 tmp, cp_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2254

u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2338

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2382

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3121

u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

335

static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

336

u32 sh_num, u32 instance, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

337

static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3685

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3696

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3721

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3722

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3820

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3868

u32 *fw = NULL;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3918

u32 tmp, fw_ucode_size, fw_data_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3919

u32 i, usec_timeout = 50000; /* Wait for 50 ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3920

u32 *fw_ucode_ptr, *fw_data_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4078

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4679

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4698

u32 gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4954

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4972

u32 i, tmp, val;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5003

u32 grbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5004

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

504

(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

511

(const u32)ARRAY_SIZE(golden_settings_gc_11_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5594

u32 reg, pre_data, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5639

u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5854

u32 ref_and_mask, reg_mem_engine;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5886

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5920

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6379

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6466

u32 doorbell_offset = entry->src_data[0];

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6520

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6566

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6611

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7447

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7449

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7460

static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7462

u32 data, wgp_bitmask;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7475

static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7477

u32 wgp_idx, wgp_active_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7478

u32 cu_bitmap_per_wgp, cu_active_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7497

u32 mask, bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

828

static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

830

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

858

static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

860

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

947

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h

25

static const u32 gfx_11_0_3_cleaner_shader_hex[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1661

static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1662

u32 sh_num, u32 instance, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1664

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1688

static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1690

u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1706

static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1708

u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1709

u32 rb_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1727

u32 rb_bitmap_per_sa;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1728

u32 rb_bitmap_width_per_sa;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1729

u32 max_sa;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1730

u32 active_sa_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1731

u32 global_active_rb_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1732

u32 active_rb_bitmap = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1733

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1802

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1835

static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1849

static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1873

u32 tmp, cp_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1914

u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1998

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2329

u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2676

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2687

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2712

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2713

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

277

static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2774

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

278

u32 sh_num, u32 instance, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

279

static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2808

u32 tmp, fw_ucode_size, fw_data_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2809

u32 i, usec_timeout = 50000; /* Wait for 50 ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2810

u32 *fw_ucode_ptr, *fw_data_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3538

u32 gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3595

(const u32)ARRAY_SIZE(golden_settings_gc_12_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3600

(const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3807

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3961

u32 reg, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4388

u32 ref_and_mask, reg_mem_engine;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4420

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4443

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4740

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4821

u32 doorbell_offset = entry->src_data[0];

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4875

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4921

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4966

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5670

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5672

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5683

static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5685

u32 data, wgp_bitmask;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5698

static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5700

u32 wgp_idx, wgp_active_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5701

u32 cu_bitmap_per_wgp, cu_active_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5720

u32 mask, bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

668

static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

670

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

687

static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

689

u32 count = 0, clustercount = 0, i;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

785

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

897

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

103

static const u32 verde_rlc_save_restore_register_list[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1304

static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1305

u32 sh_num, u32 instance, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1307

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1329

static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1331

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1344

static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1377

u32 raster_config, unsigned rb_mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1469

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1470

u32 raster_config = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1471

u32 active_rbs = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1472

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1521

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1523

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1534

static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1536

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1549

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1550

u32 active_cu = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1599

u32 i, tcc, tcp_addr_config, num_active_tcc = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1601

const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1602

const u32 dis_tcc_mask =

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1646

u32 gb_addr_config = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1647

u32 mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1648

u32 sx_debug_1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1649

u32 hdp_host_path_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1650

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1925

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2022

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2138

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2139

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2235

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2236

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2305

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2306

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2422

const u32 *src_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2423

u32 *dst_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2424

u32 dws;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2431

(u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2503

static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2505

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2512

static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2514

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2555

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2570

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2573

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2615

u32 data, orig, tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2655

u32 data, orig, tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2735

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2832

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2845

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2859

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2872

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2892

static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2894

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2924

static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2926

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3069

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3261

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3283

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3324

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3349

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3612

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3615

u32 ao_cu_num;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

402

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

403

u32 reg_offset, split_equal_to_row_size, *tilemode;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

88

static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

89

static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

115

static const u32 spectre_rlc_save_restore_register_list[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1559

u32 se_num, u32 sh_num, u32 instance,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1562

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1592

static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1594

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1609

gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1642

u32 raster_config, u32 raster_config_1,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1759

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1760

u32 raster_config = 0, raster_config_1 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1761

u32 active_rbs = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1762

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1893

u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1894

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2070

u32 ref_and_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2210

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2241

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2539

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2540

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2736

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2773

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3010

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3065

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3199

const u32 *src_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3200

u32 dws;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3209

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3213

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3255

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3267

u32 i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3268

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3295

static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3297

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3304

static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3306

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3311

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3335

u32 tmp, i, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3357

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3397

u32 tmp = RREG32(mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3421

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3476

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3492

u32 data, orig, tmp, tmp2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3535

u32 data, orig, tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3636

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3650

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3663

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3676

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3698

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3726

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3728

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3739

static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3741

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3756

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3769

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3783

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3799

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3800

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3853

static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3855

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3885

static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3887

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4072

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4135

u32 gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4136

u32 mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4137

u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4138

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4493

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4509

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4510

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4589

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4611

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4663

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4688

u32 cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5024

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5027

u32 ao_cu_num;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

561

static const u32 kalindi_rlc_save_restore_register_list[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

885

static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

886

static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

995

const u32 num_tile_mode_states =

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

997

const u32 num_secondary_tile_mode_states =

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

999

u32 reg_offset, split_equal_to_row_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1223

static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1225

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1290

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1320

static const u32 vgpr_init_compute_shader[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1357

static const u32 sgpr_init_compute_shader[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1382

static const u32 vgpr_init_regs[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1403

static const u32 sgpr1_init_regs[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1424

static const u32 sgpr2_init_regs[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1445

static const u32 sec_ded_counter_registers[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1480

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1640

u32 gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1641

u32 mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1642

u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1643

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

197

static const u32 golden_settings_tonga_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2067

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2068

const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2069

u32 reg_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

217

static const u32 tonga_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

229

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

308

static const u32 golden_settings_vegam_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

329

static const u32 vegam_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3388

u32 se_num, u32 sh_num, u32 instance,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

339

static const u32 golden_settings_polaris11_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3391

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3412

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3417

static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3419

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3433

gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3475

u32 raster_config, u32 raster_config_1,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3585

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3586

u32 raster_config = 0, raster_config_1 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3587

u32 active_rbs = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3588

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

360

static const u32 polaris11_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

370

static const u32 golden_settings_polaris10_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3724

u32 tmp, sh_static_mem_cfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3807

u32 i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3808

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3846

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

391

static const u32 polaris10_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

403

static const u32 fiji_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4086

u32 tmp = RREG32(mmCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4101

static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4103

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

417

static const u32 golden_settings_fiji_a10[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4195

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4230

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4231

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

432

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4365

static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

471

static const u32 golden_settings_iceland_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4893

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4894

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

491

static const u32 iceland_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4955

u32 grbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4996

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4997

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

503

static const u32 iceland_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5058

u32 grbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5546

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

571

static const u32 cz_golden_settings_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

587

static const u32 cz_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

599

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6001

u32 ref_and_mask, reg_mem_engine;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6049

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6081

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6370

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6637

u32 enc, se_id, sh_id, cu_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

678

static const u32 stoney_golden_settings_a11[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

692

static const u32 stoney_golden_common_all[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7020

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7022

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7033

static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7035

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

704

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7048

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7051

u32 ao_cu_num;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

728

static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1157

(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1623

static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1625

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1651

static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1653

u32 count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1871

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1874

u32 *fw;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1995

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2023

u32 gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2498

void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2499

u32 instance, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2501

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2521

static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2523

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2540

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2541

u32 active_rbs = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2542

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2662

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2714

u32 i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2715

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2753

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2827

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2829

u32 *register_list_format =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3137

u32 rlc_ucode_ver;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3243

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3391

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3392

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3482

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3995

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4136

u32 grbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4137

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4337

static const u32 vgpr_init_compute_shader[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4360

static const u32 sgpr_init_compute_shader[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4371

static const u32 vgpr_init_compute_shader_arcturus[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4635

const u32 *vgpr_init_shader_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4678

for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5157

u32 reg, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5205

static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5381

u32 ref_and_mask, reg_mem_engine;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5413

u32 header, control = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5451

u32 control = ring->ring[offset];

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5514

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5950

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5999

static u32 gfx_v9_0_get_cpc_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6029

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6065

u32 cp_int_cntl_reg, cp_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7726

u32 bitmap)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7728

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7739

static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7741

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7758

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

879

static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

891

static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.h

29

void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.h

30

u32 instance, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h

24

static const u32 __maybe_unused gfx_9_0_cleaner_shader_hex[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h

29

static const u32 gfx_9_4_2_cleaner_shader_hex[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

92

static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

93

u32 sh_num, u32 instance)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

95

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

219

static const u32 sgpr112_init_compute_shader_aldebaran[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

263

static const u32 sgpr96_init_compute_shader_aldebaran[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

310

static const u32 sgpr64_init_compute_shader_aldebaran[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

349

const u32 *shader_ptr, u32 shader_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

350

const struct soc15_reg_entry *init_regs, u32 regs_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

351

u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

373

for (i = 0; i < shader_size/sizeof(u32); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

498

u32 pattern[3] = { 0x1, 0x5, 0xa };

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

642

u32 pattern = 0xa;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

791

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

859

static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

860

u32 sh_num, u32 instance)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

862

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

93

static const u32 vgpr_init_compute_shader_aldebaran[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1299

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1466

u32 i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1467

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1508

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1573

u32 rlc_ucode_ver;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1672

u32 reg, pre_data, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1723

static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1757

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1758

u32 mec_ucode_addr_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1759

u32 mec_ucode_data_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2431

u32 grbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2432

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2823

u32 ref_and_mask, reg_mem_engine;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2855

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3069

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3118

static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3148

u32 mec_int_cntl_reg, mec_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3188

u32 mec_int_cntl_reg, mec_int_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4876

u32 bitmap, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4878

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4889

static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4891

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4908

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

619

u32 *hpd;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

622

u32 *fw;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

689

static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

690

u32 sh_num, u32 instance, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

692

u32 data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

782

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

789

u32 xcp_ctl;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

801

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

859

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

893

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h

25

static const u32 gfx_9_4_3_cleaner_shader_hex[] = {

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

145

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

147

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

150

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

152

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

173

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

175

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

179

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

181

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

386

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

387

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

415

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

62

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

83

u32 cid = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

148

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

150

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

153

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

155

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

177

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

179

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

183

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

185

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

391

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

392

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

420

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

64

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

85

u32 cid = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

127

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

129

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

133

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

135

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

344

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

345

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

379

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

70

(u32)(adev->gmc.fb_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

72

(u32)(adev->gmc.fb_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

75

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

77

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

80

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

82

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

85

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

87

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

46

u32 max_num_physical_nodes;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

47

u32 max_physical_node_id;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

48

u32 xgmi_lfb_cntl;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

49

u32 max_region;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

103

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

106

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

110

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

113

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

117

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

120

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

166

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

168

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

172

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

174

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

449

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

450

u32 i, j;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

490

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

595

u32 max_num_physical_nodes;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

596

u32 max_physical_node_id;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

597

u32 xgmi_lfb_cntl;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

598

u32 max_region;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

96

(u32)(gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

99

(u32)(gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

141

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

143

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

146

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

148

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

170

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

172

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

177

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

179

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

364

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

365

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

395

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

58

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

79

u32 cid = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

144

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

146

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

149

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

151

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

175

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

177

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

181

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

183

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

388

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

389

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

420

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

511

u32 tmp = 0, disabled_sa = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

512

u32 efuse_setting, vbios_setting;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

514

u32 max_sa_mask = amdgpu_gfx_create_bitmask(

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

61

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

82

u32 cid = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

140

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

142

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

145

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

147

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

169

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

171

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

175

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

177

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

383

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

384

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

412

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

57

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

78

u32 cid = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

143

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

145

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

148

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

150

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

174

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

176

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

180

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

182

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

376

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

377

u32 i;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

405

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

60

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

81

u32 cid = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

255

u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

259

u32 sem, req, ack;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

261

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

541

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

547

u32 viewport;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

548

u32 pitch;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

240

u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

244

u32 sem, req, ack;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

246

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

532

u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

538

u32 viewport;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

539

u32 pitch;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

230

u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

231

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

333

u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

334

u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

335

u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1037

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1038

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1073

u32 addr, status;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

148

u32 running;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

243

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

273

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

397

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

423

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

474

u32 field;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

515

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

545

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

613

u32 status, u32 addr, u32 mc_client)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

615

u32 mc_id;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

616

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

617

u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

632

static const u32 mc_cg_registers[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

644

static const u32 mc_cg_ls_en[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

656

static const u32 mc_cg_en[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

66

u32 blackout;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

672

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

689

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

705

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

728

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

744

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

799

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

805

u32 viewport = RREG32(mmVIEWPORT_SIZE);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

824

u32 tmp = RREG32(mmMC_SEQ_MISC0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

91

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

964

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

991

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

992

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

114

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1150

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1176

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1177

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1222

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1223

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1262

u32 addr, status, mc_client, vmid;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1295

u32 protections = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

182

u32 running;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

261

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

330

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

438

u32 mask = 0x0;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

442

u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

525

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

61

static const u32 golden_settings_iceland_a11[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

615

u32 tmp, field;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

658

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

68

static const u32 iceland_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

688

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

740

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

769

static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

770

u32 addr, u32 mc_client, unsigned int pasid)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

772

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

773

u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

777

u32 mc_id;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

790

static const u32 mc_cg_registers[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

802

static const u32 mc_cg_ls_en[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

814

static const u32 mc_cg_en[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

830

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

847

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

863

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

886

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

902

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

91

u32 blackout;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

968

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

974

u32 viewport = RREG32(mmVIEWPORT_SIZE);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

994

u32 tmp = RREG32(mmMC_SEQ_MISC0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1003

static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1004

u32 addr, u32 mc_client, unsigned int pasid)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1006

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1007

u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1011

u32 mc_id;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

107

static const u32 cz_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1076

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1082

u32 viewport = RREG32(mmVIEWPORT_SIZE);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1104

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

111

static const u32 stoney_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

116

static const u32 golden_settings_stoney_common[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1273

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1285

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1306

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1308

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1348

u32 srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1355

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1392

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1393

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1433

u32 addr, status, mc_client, vmid;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1483

u32 protections = REG_GET_FIELD(status,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

172

u32 blackout;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

196

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

284

u32 running;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

353

u32 data;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

436

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

513

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

629

u32 mask = 0x0;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

633

u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

67

static const u32 golden_settings_tonga_a11[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

740

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

768

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

77

static const u32 tonga_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

81

static const u32 golden_settings_fiji_a10[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

832

u32 tmp, field;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

88

static const u32 fiji_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

891

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

92

static const u32 golden_settings_polaris11_a11[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

921

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

974

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

99

static const u32 golden_settings_polaris10_a11[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1345

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1353

u32 viewport;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1851

static const u32 regBIF_BIOS_SCRATCH_4 = 0x50;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1852

u32 vram_info;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

417

u32 bits, i, tmp, reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

469

u32 tmp, reg, bits, i, j;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

774

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

844

u32 j, inv_req, tmp, sem, req, ack, inst;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

201

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

110

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

190

static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

193

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

243

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

341

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

352

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

367

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

369

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

62

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

63

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

81

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

82

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

240

u32 ih_doorbell_rtpr = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

324

u32 ih_chicken;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

325

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

435

static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

438

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

94

u32 threshold, u32 timeout, bool enabled)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

96

u32 ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

212

u32 ih_doorbell_rtpr = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

296

u32 ih_chicken;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

297

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

406

static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

409

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

94

u32 threshold, u32 timeout, bool enabled)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

96

u32 ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

212

u32 ih_doorbell_rtpr = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

296

u32 ih_chicken;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

297

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

406

static u32 ih_v7_0_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

409

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

94

u32 threshold, u32 timeout, bool enabled)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

96

u32 ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

326

const u32 array_size)

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

329

u32 reg, data;

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

359

u32 reg_data;

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

366

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11));

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

370

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_2));

sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c

109

const u32 array_size)

sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c

112

u32 reg, data;

sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c

144

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_3));

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

126

u32 imu_reg_val = 0;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

146

u32 imu_reg_val;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

165

u32 imu_reg_val;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

259

const u32 array_size)

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

262

u32 reg, data;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

285

static u32 imu_v12_0_grbm_gfx_index_remap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

286

u32 data, bool high)

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

288

u32 val, inst_index;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

305

static u32 imu_v12_init_gfxhub_settings(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

306

u32 reg, u32 data)

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

343

const u32 *regs,

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

344

const u32 array_size)

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

346

u32 reg, data, val_h = 0, val_l = TRANSFER_RAM_MASK;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

369

u32 reg_data, size = 0;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

370

const u32 *data = NULL;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

379

program_imu_rlc_ram(adev, data, (const u32)size);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

382

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1));

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_1.c

88

u32 iclk, xclk;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

637

u32 i, reg, res, cond, type;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

76

u32 harvest;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

69

u32 harvest;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

103

static inline int jpeg_v4_0_3_core_reg_offset(u32 pipe)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1462

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1037

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

404

u32 reg, data, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

762

u32 i, inst;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

99

static int jpeg_v5_0_1_core_reg_offset(u32 pipe)

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

211

u32 db_array[8];

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

426

u32 fence_offset;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1083

u32 *eop;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

178

u32 seq, status_offset;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1093

u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1245

u32 *eop;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

163

u32 seq, status_offset;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

383

u32 i, tmp, val;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

121

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

123

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

127

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

129

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

247

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

251

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

255

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

259

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

393

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

394

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

427

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

75

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

77

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

80

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

82

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

100

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

139

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

141

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

145

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

147

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

377

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

378

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

411

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

572

u32 data, data1;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

82

(u32)(adev->gmc.fb_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

84

(u32)(adev->gmc.fb_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

87

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

89

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

93

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

95

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

98

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

100

(u32)(gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

103

(u32)(gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

107

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

110

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

115

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

118

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

122

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

125

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

174

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

176

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

181

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

184

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

348

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

447

u32 i, j, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

482

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

483

u32 i, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

507

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

508

u32 i, j, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

538

u32 tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

584

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

59

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

818

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

82

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

122

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

211

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

213

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

216

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

218

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

242

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

244

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

248

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

250

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

448

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

449

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

478

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

677

u32 data, data1;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

141

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

143

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

146

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

148

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

170

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

172

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

176

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

178

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

378

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

379

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

409

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

61

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

158

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

160

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

163

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

165

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

195

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

197

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

201

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

203

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

402

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

403

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

432

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

78

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

167

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

169

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

172

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

174

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

201

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

203

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

207

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

209

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

396

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

397

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

427

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

85

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

151

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

153

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

156

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

158

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

187

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

189

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

193

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

195

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

394

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

395

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

424

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

78

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

169

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

259

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

261

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

264

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

266

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

293

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

295

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

299

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

301

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

482

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

484

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

487

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

489

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

538

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

539

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

569

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

720

u32 data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

150

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

152

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

155

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

157

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

188

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

190

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

194

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

196

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

395

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

396

u32 i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

426

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

70

u32 req = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

144

(u32)(value >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

149

(u32)(value >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

156

(u32)(adev->dummy_page_addr >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

161

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

439

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

440

u32 i, j;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

483

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

691

u32 data, data1;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

84

(u32)(adev->gmc.gart_start >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

88

(u32)(adev->gmc.gart_start >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

93

(u32)(adev->gmc.gart_end >> 12));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

97

(u32)(adev->gmc.gart_end >> 44));

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

120

enum idh_request req, u32 data1, u32 data2, u32 data3) {

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

121

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

243

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

331

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

66

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

138

enum idh_request req, u32 data1, u32 data2, u32 data3)

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

174

enum idh_request req, u32 data1, u32 data2, u32 data3)

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

304

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

398

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

65

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

126

static const u32 xgpu_fiji_golden_common_all[] = {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

139

static const u32 xgpu_tonga_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

229

static const u32 xgpu_tonga_golden_settings_a11[] = {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

269

static const u32 xgpu_tonga_golden_common_all[] = {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

321

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

323

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

345

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

356

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

369

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

370

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

392

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

393

u32 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

48

static const u32 xgpu_fiji_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

504

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

537

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

98

static const u32 xgpu_fiji_golden_settings_a10[] = {

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

106

u32 threshold, u32 timeout, bool enabled)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

108

u32 ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

238

u32 ih_doorbell_rtpr = 0;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

320

u32 ih_chicken;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

406

static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

409

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

109

u32 doorbell_range;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

166

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

188

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

222

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

260

static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

265

static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

270

static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

275

static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

304

static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

306

u32 data, rom_offset;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

41

static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

43

u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

61

static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

72

u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

103

static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

112

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

117

u32 doorbell_range = RREG32(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

137

u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) :

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

140

u32 doorbell_range = RREG32(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

165

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

189

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

208

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

296

static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

301

static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

306

static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

311

static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

74

static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

76

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

105

u32 doorbell_range;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

161

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

184

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

218

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

303

static u32 nbio_v4_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

308

static u32 nbio_v4_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

313

static u32 nbio_v4_3_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

318

static u32 nbio_v4_3_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

349

static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

351

u32 data, rom_offset;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

39

static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

41

u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

59

static u32 nbio_v4_3_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

69

u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

115

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

135

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

149

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

227

static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

232

static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

237

static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

242

static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

63

static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

65

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

83

static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

91

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

94

u32 doorbell_range = RREG32(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

119

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

224

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

238

static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

243

static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

248

static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

253

static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

43

static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

45

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

62

static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

70

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

73

u32 doorbell_range = RREG32(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

87

u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

89

u32 doorbell_range = RREG32(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

116

u32 reg = instance == 0 ?

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

120

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

139

u32 reg;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

152

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

177

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

198

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

219

static u32 nbio_v7_11_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

224

static u32 nbio_v7_11_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

229

static u32 nbio_v7_11_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

234

static u32 nbio_v7_11_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

239

static u32 nbio_v7_11_get_pcie_port_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

244

static u32 nbio_v7_11_get_pcie_port_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

38

static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

40

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

59

static u32 nbio_v7_11_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

68

u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

69

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

91

u32 reg = instance == 0 ?

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

94

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

102

static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

111

u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

112

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

133

u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

134

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

153

u32 reg;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

165

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

191

u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

212

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

323

static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

328

static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

333

static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

338

static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

343

static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

348

static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

57

static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

59

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

109

static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

111

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

133

static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

141

u32 reg, doorbell_range;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

182

u32 reg;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

183

u32 doorbell_range;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

217

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

236

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

292

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

306

static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

311

static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

316

static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

321

static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

110

u32 reg;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

122

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

148

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

170

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

191

static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

196

static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

201

static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

206

static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

211

static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

216

static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

38

static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

40

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

59

static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

68

u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

69

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

90

u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

91

u32 doorbell_range = RREG32_PCIE_PORT(reg);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

175

u32 doorbell_range = 0, doorbell_ctrl = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

176

u32 aid_id = instance;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

177

u32 range_size;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

244

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

266

u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

324

u32 interrupt_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

340

static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

345

static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

350

static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

355

static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

360

static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

395

u32 tmp, px;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

406

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

415

static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

416

u32 *supp_modes)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

418

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

42

static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

433

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

44

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

449

u32 baco_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

68

static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

76

u32 doorbell_range = 0, doorbell_ctrl = 0;

sys/dev/pci/drm/amd/amdgpu/nv.c

278

static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/nv.c

281

u32 r;

sys/dev/pci/drm/amd/amdgpu/nv.c

293

static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/nv.c

306

static u32 nv_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nv.c

311

static u32 nv_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/nv.c

318

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/nv.c

320

u32 grbm_gfx_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/nv.c

357

static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/nv.c

358

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/nv.c

375

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/nv.c

376

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/nv.c

387

static int nv_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/nv.c

388

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/nv.c

412

u32 i;

sys/dev/pci/drm/amd/amdgpu/nv.c

430

u32 memsize = adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

502

static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/pci/drm/amd/amdgpu/nv.c

508

static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/amd/amdgpu/nv.c

544

u32 sol_reg;

sys/dev/pci/drm/amd/amdgpu/nv.h

32

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

153

u32 bl_status_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

864

u32 reg_data;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

889

u32 pmfw_ver;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

205

u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

277

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

340

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

375

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

404

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

405

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

537

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

590

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

60

static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = {

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

65

static const u32 golden_settings_iceland_a11[] = {

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

72

static const u32 iceland_mgcg_cgcg_init[] = {

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

737

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

917

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

929

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

945

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

947

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

989

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

100

static const u32 golden_settings_fiji_a10[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1010

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

112

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

118

static const u32 golden_settings_polaris11_a11[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1206

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1218

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1235

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1236

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1256

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1275

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1294

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1295

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

132

static const u32 golden_settings_polaris10_a11[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1327

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

146

static const u32 cz_golden_settings_a11[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

162

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

168

static const u32 stoney_golden_settings_a11[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

176

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

363

u32 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

387

u32 *wb = (u32 *)ring->wptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

392

u32 *wb = (u32 *)ring->wptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

453

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

516

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

551

u32 f32_cntl, phase_quantum = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

612

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

641

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

642

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

643

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

74

static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

80

static const u32 golden_settings_tonga_a11[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

811

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

864

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

94

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1046

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1092

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1093

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1094

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1177

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1178

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1179

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1343

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1469

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1523

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1671

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2021

u32 i;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2024

u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2036

u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2064

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2154

u32 sdma_edc_config;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

441

static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

442

u32 instance, u32 offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

863

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

924

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

958

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

983

u32 f32_cntl, phase_quantum = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1065

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1119

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

114

u32 instance_id);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

116

static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

117

u32 instance, u32 offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

119

u32 dev_inst = GET_INST(SDMA0, instance);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1267

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1402

u32 aid_id;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1612

u32 i;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1615

u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1627

u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

165

u32 val;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1664

u32 id = ring->me;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1676

u32 instance_id = ring->me;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1677

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1714

u32 inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1738

u32 instance_id)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1751

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1850

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2564

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

430

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

495

u32 doorbell_offset, doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

496

u32 rb_cntl, ib_cntl, sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

551

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

578

u32 f32_cntl, phase_quantum = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

633

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

689

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

690

u32 wb_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

691

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

692

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

795

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

796

u32 wb_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

797

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

798

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

925

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1018

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1081

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1240

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1330

static int sdma_v5_0_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1332

u32 grbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1333

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1499

u32 i;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1502

u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1514

u32 sdma0, sdma1;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1560

u32 f32_cntl, freeze, cntl, stat1_reg;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1610

u32 inst_id = ring->me;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1611

u32 freeze;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1630

u32 index = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1678

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1681

u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

218

static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

220

u32 base;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

242

(const u32)ARRAY_SIZE(golden_settings_sdma_5));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

245

(const u32)ARRAY_SIZE(golden_settings_sdma_nv10));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

250

(const u32)ARRAY_SIZE(golden_settings_sdma_5));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

253

(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

259

(const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

263

(const u32)ARRAY_SIZE(golden_settings_sdma_5));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

266

(const u32)ARRAY_SIZE(golden_settings_sdma_nv12));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

271

(const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

492

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

565

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

600

u32 f32_cntl = 0, phase_quantum = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

658

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

691

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

692

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

693

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

694

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

695

u32 temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

696

u32 wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

887

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1140

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

119

static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

121

u32 base;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1412

u32 i;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1415

u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1427

u32 sdma0, sdma1, sdma2, sdma3;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1468

u32 f32_cntl, freeze, cntl, stat1_reg;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1520

u32 inst_id = ring->me;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1521

u32 freeze;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1541

u32 index = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1587

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1588

u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

341

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

415

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

450

u32 f32_cntl, phase_quantum = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

507

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

540

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

541

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

542

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

543

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

544

u32 temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

545

u32 wptr_poll_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

734

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

766

static int sdma_v5_2_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

768

u32 grbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

769

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

918

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

981

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1145

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

126

static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

128

u32 base;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1492

u32 i;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1495

u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1507

u32 sdma0, sdma1;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1525

u32 index = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1596

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1598

u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1643

u32 doorbell_offset = entry->src_data[0];

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

327

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

396

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

431

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

454

u32 f32_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

485

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

486

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

487

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

488

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

489

u32 temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

669

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

762

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

924

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

987

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1004

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1166

u32 pad_count;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

126

static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

128

u32 base;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1448

u32 i;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1451

u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1463

u32 sdma0, sdma1;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1481

u32 index = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1531

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1533

u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1576

u32 doorbell_offset = entry->src_data[0];

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

331

u32 ref_and_mask = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

400

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

447

u32 mcu_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

478

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

479

u32 rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

480

u32 doorbell;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

481

u32 doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

482

u32 temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

683

u32 fw_size;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

755

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

941

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/si.c

1032

static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/si.c

1035

u32 r;

sys/dev/pci/drm/amd/amdgpu/si.c

1045

static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/si.c

1057

static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/si.c

1060

u32 r;

sys/dev/pci/drm/amd/amdgpu/si.c

1070

static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/si.c

1082

static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/si.c

1085

u32 r;

sys/dev/pci/drm/amd/amdgpu/si.c

1094

static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/si.c

1104

static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/si.c

1107

u32 r;

sys/dev/pci/drm/amd/amdgpu/si.c

1116

static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/si.c

113

static const u32 tahiti_golden_registers2[] =

sys/dev/pci/drm/amd/amdgpu/si.c

1179

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/si.c

118

static const u32 tahiti_golden_rlc_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

1180

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/si.c

1253

static int si_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/si.c

1254

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/si.c

1274

u32 bus_cntl;

sys/dev/pci/drm/amd/amdgpu/si.c

1275

u32 d1vga_control = 0;

sys/dev/pci/drm/amd/amdgpu/si.c

1276

u32 d2vga_control = 0;

sys/dev/pci/drm/amd/amdgpu/si.c

1277

u32 vga_render_control = 0;

sys/dev/pci/drm/amd/amdgpu/si.c

1278

u32 rom_cntl;

sys/dev/pci/drm/amd/amdgpu/si.c

129

static const u32 pitcairn_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

1321

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/si.c

1323

u32 *dw_ptr;

sys/dev/pci/drm/amd/amdgpu/si.c

1324

u32 i, length_dw;

sys/dev/pci/drm/amd/amdgpu/si.c

1334

dw_ptr = (u32 *)bios;

sys/dev/pci/drm/amd/amdgpu/si.c

1346

u32 tmp, i;

sys/dev/pci/drm/amd/amdgpu/si.c

1374

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/si.c

1395

u32 i;

sys/dev/pci/drm/amd/amdgpu/si.c

1463

static u32 si_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/si.c

1482

static u32 si_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/si.c

1484

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/si.c

1485

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/si.c

1532

u32 link_width_cntl;

sys/dev/pci/drm/amd/amdgpu/si.c

1557

u32 link_width_cntl, mask;

sys/dev/pci/drm/amd/amdgpu/si.c

165

static const u32 pitcairn_golden_rlc_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

175

static const u32 verde_pg_init[] =

sys/dev/pci/drm/amd/amdgpu/si.c

1790

static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/pci/drm/amd/amdgpu/si.c

1913

static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/amd/amdgpu/si.c

2240

u32 speed_cntl, current_data_rate;

sys/dev/pci/drm/amd/amdgpu/si.c

2281

u32 max_lw, current_lw, tmp;

sys/dev/pci/drm/amd/amdgpu/si.c

2384

static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/si.c

2387

u32 r;

sys/dev/pci/drm/amd/amdgpu/si.c

2396

static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/si.c

2406

static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/si.c

2409

u32 r;

sys/dev/pci/drm/amd/amdgpu/si.c

2418

static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/si.c

2429

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/si.c

2555

u32 lnkcap;

sys/dev/pci/drm/amd/amdgpu/si.c

302

static const u32 verde_golden_rlc_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

312

static const u32 verde_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

350

static const u32 oland_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

387

static const u32 oland_golden_rlc_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

397

static const u32 hainan_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

435

static const u32 hainan_golden_registers2[] =

sys/dev/pci/drm/amd/amdgpu/si.c

440

static const u32 tahiti_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/si.c

569

static const u32 pitcairn_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/si.c

667

static const u32 verde_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/si.c

73

static const u32 tahiti_golden_registers[] =

sys/dev/pci/drm/amd/amdgpu/si.c

767

static const u32 oland_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/si.c

847

static const u32 hainan_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/si.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

131

u32 rb_cntl;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

145

u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

214

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

265

u32 tmp = 0;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

32

const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

sys/dev/pci/drm/amd/amdgpu/si_dma.c

564

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

596

u32 sdma_cntl;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

65

u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

651

u32 orig, data, offset;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

694

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

73

u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/si_ih.c

108

static u32 si_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/si_ih.c

111

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/si_ih.c

137

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/si_ih.c

217

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/si_ih.c

242

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/si_ih.c

243

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/si_ih.c

38

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/amd/amdgpu/si_ih.c

39

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/si_ih.c

50

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/si_ih.c

51

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/amd/amdgpu/si_ih.c

67

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

270

u32 numbytes, u32 i2c_flag)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

274

u32 bytes_sent, reg, ret = I2C_OK;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

369

u32 numbytes, u32 i2c_flag)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

524

u32 status, enable, en_stat;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

676

u32 i2c_flag = 0;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

711

static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

87

u32 en_stat = RREG32_SOC15(SMUIO,

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

28

static u32 smuio_v11_0_get_rom_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

33

static u32 smuio_v11_0_get_rom_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

40

u32 def, data;

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

64

u32 data;

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

28

static u32 smuio_v11_0_6_get_rom_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

33

static u32 smuio_v11_0_6_get_rom_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

40

u32 def, data;

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

61

u32 data;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

100

u32 data, socket_id;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

117

u32 data;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

134

u32 data;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

30

static u32 smuio_v13_0_get_rom_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

35

static u32 smuio_v13_0_get_rom_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

42

u32 def, data;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

63

u32 data;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

81

static u32 smuio_v13_0_get_die_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

83

u32 data, die_id;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

98

static u32 smuio_v13_0_get_socket_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

38

static u32 smuio_v13_0_3_get_die_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

40

u32 data, die_id;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

55

static u32 smuio_v13_0_3_get_socket_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

57

u32 data, socket_id;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

76

u32 data;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_6.c

28

static u32 smuio_v13_0_6_get_rom_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_6.c

33

static u32 smuio_v13_0_6_get_rom_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

29

static u32 smuio_v14_0_2_get_rom_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

34

static u32 smuio_v14_0_2_get_rom_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

28

static u32 smuio_v9_0_get_rom_index_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

33

static u32 smuio_v9_0_get_rom_data_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

40

u32 def, data;

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

61

u32 data;

sys/dev/pci/drm/amd/amdgpu/soc15.c

240

static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/soc15.c

243

u32 r;

sys/dev/pci/drm/amd/amdgpu/soc15.c

255

static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/soc15.c

268

static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/soc15.c

271

u32 r;

sys/dev/pci/drm/amd/amdgpu/soc15.c

283

static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/soc15.c

296

static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/soc15.c

299

u32 r;

sys/dev/pci/drm/amd/amdgpu/soc15.c

308

static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/soc15.c

318

static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/soc15.c

321

u32 r;

sys/dev/pci/drm/amd/amdgpu/soc15.c

330

static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/soc15.c

340

static u32 soc15_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/soc15.c

345

static u32 soc15_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/soc15.c

347

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/soc15.c

364

u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/soc15.c

366

u32 grbm_gfx_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/soc15.c

404

static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc15.c

405

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc15.c

422

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc15.c

423

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc15.c

436

static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc15.c

437

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/soc15.c

473

const u32 array_size)

sys/dev/pci/drm/amd/amdgpu/soc15.c

476

u32 tmp, reg;

sys/dev/pci/drm/amd/amdgpu/soc15.c

678

static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/pci/drm/amd/amdgpu/soc15.c

691

static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/amd/amdgpu/soc15.c

854

u32 sol_reg;

sys/dev/pci/drm/amd/amdgpu/soc15.h

110

u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/soc15.h

115

const u32 array_size);

sys/dev/pci/drm/amd/amdgpu/soc15.h

38

u32 hwip;

sys/dev/pci/drm/amd/amdgpu/soc15.h

39

u32 instance;

sys/dev/pci/drm/amd/amdgpu/soc15.h

40

u32 segment;

sys/dev/pci/drm/amd/amdgpu/soc15.h

41

u32 reg;

sys/dev/pci/drm/amd/amdgpu/soc15.h

42

u32 and_mask;

sys/dev/pci/drm/amd/amdgpu/soc15.h

43

u32 or_mask;

sys/dev/pci/drm/amd/amdgpu/soc15.h

47

u32 hwip;

sys/dev/pci/drm/amd/amdgpu/soc15.h

48

u32 instance;

sys/dev/pci/drm/amd/amdgpu/soc15.h

49

u32 segment;

sys/dev/pci/drm/amd/amdgpu/soc15.h

50

u32 reg;

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

125

u32 tmp = RREG32(r1); \

sys/dev/pci/drm/amd/amdgpu/soc21.c

193

static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/soc21.c

196

u32 r;

sys/dev/pci/drm/amd/amdgpu/soc21.c

208

static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/soc21.c

221

static u32 soc21_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/soc21.c

226

static u32 soc21_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/soc21.c

228

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/soc21.c

239

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/soc21.c

241

u32 grbm_gfx_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/soc21.c

278

static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc21.c

279

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc21.c

296

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc21.c

297

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc21.c

308

static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc21.c

309

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/soc21.c

334

u32 i;

sys/dev/pci/drm/amd/amdgpu/soc21.c

358

u32 memsize = adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

429

static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/pci/drm/amd/amdgpu/soc21.c

435

static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/amd/amdgpu/soc21.c

471

u32 sol_reg;

sys/dev/pci/drm/amd/amdgpu/soc21.c

924

u32 sol_reg1, sol_reg2;

sys/dev/pci/drm/amd/amdgpu/soc21.h

29

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/soc24.c

102

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/soc24.c

104

u32 grbm_gfx_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/soc24.c

136

u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc24.c

137

u32 sh_num,

sys/dev/pci/drm/amd/amdgpu/soc24.c

138

u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc24.c

155

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc24.c

156

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc24.c

168

static int soc24_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc24.c

169

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/soc24.c

272

u32 sol_reg;

sys/dev/pci/drm/amd/amdgpu/soc24.c

91

static u32 soc24_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/soc24.c

96

static u32 soc24_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/soc24.h

29

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

104

u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

192

static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

195

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

247

u32 ring_index = ih->rptr >> 2;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

359

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

370

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

386

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

387

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

423

u32 srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

430

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

62

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

464

u32 ext_error_code;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

209

u32 tmp, tmp2;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

335

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

337

u32 lmi_swap_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

338

u32 mp_swap_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

608

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

292

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

294

u32 lmi_swap_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

295

u32 mp_swap_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

617

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

643

u32 tmp, tmp2;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

770

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1171

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1172

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1202

u32 srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1209

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1432

u32 orig, data;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

644

u32 data, data1;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

216

static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

280

static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

371

u32 harvest;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

149

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

318

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

353

u32 orig, tmp;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

112

u32 v;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

171

u32 data;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

366

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

603

u32 mask = 0;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

632

u32 srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

673

u32 srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

680

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

80

u32 v;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

235

u32 harvest;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2040

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1665

u32 instlo;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

183

u32 ih_doorbell_rtpr = 0;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

264

u32 ih_chicken;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

335

static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

338

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

219

u32 ih_doorbell_rtpr = 0;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

286

static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

288

u32 val = 0;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

310

u32 ih_chicken;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

416

static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

419

u32 wptr, tmp;

sys/dev/pci/drm/amd/amdgpu/vi.c

1026

static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/pci/drm/amd/amdgpu/vi.c

1051

static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/amd/amdgpu/vi.c

1055

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vi.c

1056

u32 reg_ctrl;

sys/dev/pci/drm/amd/amdgpu/vi.c

1057

u32 reg_status;

sys/dev/pci/drm/amd/amdgpu/vi.c

1058

u32 status_mask;

sys/dev/pci/drm/amd/amdgpu/vi.c

1059

u32 reg_mask;

sys/dev/pci/drm/amd/amdgpu/vi.c

1107

u32 data, orig;

sys/dev/pci/drm/amd/amdgpu/vi.c

1122

u32 data, data1, orig;

sys/dev/pci/drm/amd/amdgpu/vi.c

1281

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vi.c

1412

u32 clock_cntl, pc;

sys/dev/pci/drm/amd/amdgpu/vi.c

297

static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/vi.c

300

u32 r;

sys/dev/pci/drm/amd/amdgpu/vi.c

310

static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/vi.c

322

static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/vi.c

325

u32 r;

sys/dev/pci/drm/amd/amdgpu/vi.c

334

static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/vi.c

348

static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/vi.c

351

u32 r;

sys/dev/pci/drm/amd/amdgpu/vi.c

360

static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/vi.c

370

static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/vi.c

373

u32 r;

sys/dev/pci/drm/amd/amdgpu/vi.c

382

static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/vi.c

392

static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/vi.c

395

u32 r;

sys/dev/pci/drm/amd/amdgpu/vi.c

404

static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/vi.c

414

static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/pci/drm/amd/amdgpu/vi.c

417

u32 r;

sys/dev/pci/drm/amd/amdgpu/vi.c

426

static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/pci/drm/amd/amdgpu/vi.c

437

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/vi.c

448

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/vi.c

459

static const u32 iceland_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/vi.c

468

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/vi.c

477

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/pci/drm/amd/amdgpu/vi.c

539

static u32 vi_get_xclk(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/vi.c

541

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/vi.c

542

u32 tmp;

sys/dev/pci/drm/amd/amdgpu/vi.c

579

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/vi.c

581

u32 srbm_gfx_cntl = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

591

u32 bus_cntl;

sys/dev/pci/drm/amd/amdgpu/vi.c

592

u32 d1vga_control = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

593

u32 d2vga_control = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

594

u32 vga_render_control = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

595

u32 rom_cntl;

sys/dev/pci/drm/amd/amdgpu/vi.c

635

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/vi.c

637

u32 *dw_ptr;

sys/dev/pci/drm/amd/amdgpu/vi.c

639

u32 i, length_dw;

sys/dev/pci/drm/amd/amdgpu/vi.c

649

dw_ptr = (u32 *)bios;

sys/dev/pci/drm/amd/amdgpu/vi.c

745

bool indexed, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/vi.c

746

u32 sh_num, u32 reg_offset)

sys/dev/pci/drm/amd/amdgpu/vi.c

840

static int vi_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/vi.c

841

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/pci/drm/amd/amdgpu/vi.c

870

u32 i;

sys/dev/pci/drm/amd/amdgpu/vi.c

975

static u32 vi_get_config_memsize(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/vi.c

980

static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/pci/drm/amd/amdgpu/vi.c

981

u32 cntl_reg, u32 status_reg)

sys/dev/pci/drm/amd/amdgpu/vi.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c

94

u32 pasid = (ihre->ring_id & 0xffff0000) >> 16;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1861

int flags, u32 *shared_fd,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3282

u32 amdkfd_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2016

u32 pci_id = pci_domain_nr(kdev->adev->pdev->bus) << 16 |

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2018

u32 bdf;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2058

pxm = *((u32 *)cpu->proximity_domain_hi) << 8 |

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

404

static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

417

static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1683

u32 cam_index;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

783

max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1468

set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2609

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2693

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2694

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2722

u32 *mqd_size,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2723

u32 *ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3056

int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3609

int doorbell_off, u32 *queue_format)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

50

u32 pasid, unsigned int vmid);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

177

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

190

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

191

u32 *save_area_used_size);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

196

const struct queue *q, u32 *mqd_size,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

197

u32 *ctl_stack_size);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

214

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

329

int doorbell_off, u32 *queue_format);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

44

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

93

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c

40

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c

66

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c

39

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c

65

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c

39

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c

65

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

39

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

65

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

44

u32 misc_process_properties);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

94

u32 misc_process_properties)

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

153

u32 inx;

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

156

inx = find_first_zero_bit(kfd->doorbell_bitmap, PAGE_SIZE / sizeof(u32));

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

178

void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr)

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

190

void write_kernel_doorbell(void __iomem *db, u32 value)

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

75

kfd->doorbell_bitmap = bitmap_zalloc(size / sizeof(u32), GFP_KERNEL);

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1175

void kfd_signal_hw_exception_event(u32 pasid)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1347

void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

608

u32 num_events = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

731

void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,

sys/dev/pci/drm/amd/amdkfd/kfd_events.h

55

u32 event_id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.h

87

extern void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

359

u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0);

sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c

123

static bool dequeue_ih_ring_entry(struct kfd_node *node, u32 **ih_ring_entry)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

102

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

103

u32 *save_area_used_size);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

117

const u32 ctl_stack_size);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

264

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

302

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

239

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

240

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

287

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

330

u32 doorbell_off;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

407

const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

292

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

293

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

338

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

376

const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

416

u32 doorbell_off;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

255

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

256

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

339

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

340

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

372

static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

413

const void *ctl_stack_src, u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

461

u32 doorbell_off;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

540

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

626

u32 doorbell_off;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

783

const void *ctl_stack_src, u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

786

u32 mqd_ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

788

u32 num_xcc;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

874

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

875

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

881

u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

257

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

258

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

277

static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

296

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

401

const void *ctl_stack_src, const u32 ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1008

u32 dbg_flags;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1056

struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1109

u32 kfd_pasid_alloc(void);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1110

void kfd_pasid_free(u32 pasid);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1120

void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1121

u32 read_kernel_doorbell(u32 __iomem *db);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1122

void write_kernel_doorbell(void __iomem *db, u32 value);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1354

int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1387

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1388

u32 *save_area_used_size);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1401

u32 *mqd_size,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1402

u32 *ctl_stack_size);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1511

void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1513

void kfd_signal_hw_exception_event(u32 pasid);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1534

void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

330

u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

866

u32 pasid;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1817

static struct kfd_process_device *kfd_lookup_process_device_by_pasid(u32 pasid)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1838

struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid,

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

276

u32 queue_format;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

688

u32 *ctl_stack_used_size,

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

689

u32 *save_area_used_size)

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

238

u32 total_cwsr_size;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

344

u32 total_cwsr_size;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

401

static u32 kfd_get_vgpr_size_per_cu(u32 gfxv)

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

403

u32 vgpr_size = 0x40000;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

433

u32 gfxv = props->gfx_target_version;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

434

u32 ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

435

u32 wg_data_size;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

436

u32 wave_num;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

437

u32 cu_num;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1001

u32 count = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10200

u32 i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10654

u32 i, j;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1263

u32 i, fw_inst_const_size, fw_bss_data_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13160

u32 value, const char *func_name)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13178

u32 value;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1473

u32 logical_addr_low;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1474

u32 logical_addr_high;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1475

u32 agp_base, agp_bot, agp_top;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1732

u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

228

u32 link_index,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

247

u32 user_brightness);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

265

static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

284

u32 *vbl, u32 *position)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

286

u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3249

u32 i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

445

u32 vpos, hpos, v_blank_start, v_blank_end;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4969

static inline u32 scale_input_to_fw(int min, int max, u64 input)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4975

static inline u32 scale_fw_to_input(int min, int max, u64 input)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4984

u32 brightness = scale_input_to_fw(min, max, *user_brightness);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5044

static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5058

static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5075

u32 user_brightness)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5079

u32 brightness;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5167

static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5178

u32 avg, peak;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5366

u32 link_cnt;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6270

u32 num_clips;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6274

u32 i = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7032

u32 link_bw_in_kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7033

u32 edp_min_bpp_x16, edp_max_bpp_x16;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7094

u32 link_bandwidth_kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7096

u32 max_supported_bw_in_kbps, timing_bw_in_kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7097

u32 dsc_max_supported_bw_in_kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7098

u32 max_dsc_target_bpp_limit_override =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8612

u32 new_modes_count = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8626

static const u32 common_rates[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8726

static const u32 supported_colorspaces =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8908

static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8972

u32 link_index,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9370

u32 flip_timestamp_in_us)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9701

u32 i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9713

u32 target_vblank, last_flip_vblank;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

200

u32 aux_min_input_signal;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

205

u32 aux_max_input_signal;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

226

u32 brightness_mask;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

629

u32 brightness[AMDGPU_DM_MAX_NUM_EDP];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

635

u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

181

static const u32 amdgpu_eotf =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

189

static const u32 amdgpu_inv_eotf =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

200

u32 supported_tf)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

202

u32 transfer_functions = supported_tf |

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3123

u32 residency = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3136

u32 residency = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3167

u32 residency = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3256

u32 res;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

649

u32 srm_version = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

674

u32 srm_version;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

675

u32 srm_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

52

static u32 edid_extract_panel_id(struct edid *edid)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

54

return (u32)edid->mfg_id[0] << 24 |

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

55

(u32)edid->mfg_id[1] << 16 |

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

56

(u32)EDID_PRODUCT_ID(edid);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h

33

u32 last_flip_vblank;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

636

u32 gb_addr_config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

84

static const u32 cursor_formats[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

95

const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

61

const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

122

__field(u32, colorspace)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

182

__field(u32, plane_mask)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

183

__field(u32, connector_mask)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

184

__field(u32, encoder_mask)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

247

__field(u32, alpha)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

731

TP_PROTO(void *function, u32 user_brightness, u32 converted_brightness, bool aux, bool ac),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

735

__field(u32, user_brightness)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

736

__field(u32, converted_brightness)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

749

(u32)__entry->user_brightness,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

750

(u32)__entry->converted_brightness,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

39

static const u32 amdgpu_dm_wb_formats[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

62

for (i = 0; i < sizeof(amdgpu_dm_wb_formats) / sizeof(u32); i++) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

312

masterCmdData1.u32 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

315

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

738

masterCmdData1.u32 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

741

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

302

unsigned int u32;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

238

u32 value;

sys/dev/pci/drm/amd/include/amd_acpi.h

32

u32 notification_mask; /* supported notifications mask */

sys/dev/pci/drm/amd/include/amd_acpi.h

33

u32 function_bits; /* supported functions bit vector */

sys/dev/pci/drm/amd/include/amd_acpi.h

38

u32 valid_mask; /* valid flags mask */

sys/dev/pci/drm/amd/include/amd_acpi.h

39

u32 flags; /* flags */

sys/dev/pci/drm/amd/include/amd_acpi.h

45

u32 pending; /* pending sbios requests */

sys/dev/pci/drm/amd/include/amd_acpi.h

89

u32 function_bits; /* supported functions bit vector */

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

227

int (*set_pasid_vmid_mapping)(struct amdgpu_device *adev, u32 pasid,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

75

u32 wave_cnt;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

76

u32 doorbell_off;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

421

int (*set_fan_control_mode)(void *handle, u32 mode);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

422

int (*get_fan_control_mode)(void *handle, u32 *fan_mode);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

423

int (*set_fan_speed_pwm)(void *handle, u32 speed);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

424

int (*get_fan_speed_pwm)(void *handle, u32 *speed);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

447

struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

45

u32 evclk;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

46

u32 ecclk;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

470

u32 (*get_sclk)(void *handle, bool low);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

471

u32 (*get_mclk)(void *handle, bool low);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

48

u32 sclk;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

49

u32 mclk;

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

909

int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value)

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

40

u32 vblank_in_pixels, vblank_time_us;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1655

u32 limit;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1680

u32 value;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2194

u32 nplimit;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2217

u32 npower;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2241

u32 npower;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2264

u32 gpptresid;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2287

u32 max_nplimit;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2638

u32 limit;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2887

u32 pwm_mode = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2911

u32 pwm_mode;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2961

u32 value;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2962

u32 pwm_mode;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2999

u32 speed = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3021

u32 speed = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3042

u32 min_rpm = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3059

u32 max_rpm = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3077

u32 rpm = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3099

u32 value;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3100

u32 pwm_mode;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3135

u32 pwm_mode = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3160

u32 pwm_mode;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3192

u32 vddgfx;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3209

u32 vddboard;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3239

u32 vddnb;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3267

u32 query = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3388

u32 value;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3875

u32 *type,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

105

u32 sclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

106

u32 mclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

112

u32 count;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

113

u32 *values;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

117

u32 clk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

122

u32 count;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

129

u32 leakage;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

139

u32 count;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

145

u32 sclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

146

u32 mclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

150

u32 count;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

155

u32 vclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

156

u32 dclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

166

u32 ecclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

167

u32 evclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

179

u32 platform_tdp;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

180

u32 small_ac_platform_tdp;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

181

u32 platform_tdc;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

182

u32 small_ac_platform_tdc;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

183

u32 apu_tdp;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

184

u32 dgpu_tdp;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

185

u32 dgpu_ulv_power;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

186

u32 tj_max;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

215

u32 mclk_sclk_ratio;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

216

u32 sclk_mclk_delta;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

233

u32 cycle_delay;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

255

u32 num_of_vce_states;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

262

u32 platform_caps;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

263

u32 voltage_response_time;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

264

u32 backbias_response_time;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

268

u32 tdp_limit;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

269

u32 near_tdp_limit;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

270

u32 near_tdp_limit_adjusted;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

271

u32 sq_ramping_threshold;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

272

u32 cac_leakage;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

274

u32 tdp_adjustment;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

335

u32 current_sclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

336

u32 current_mclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

337

u32 default_sclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

338

u32 default_mclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

468

int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

60

u32 caps; /* vbios flags */

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

61

u32 class; /* vbios flags */

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

62

u32 class2; /* vbios flags */

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

64

u32 vclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

65

u32 dclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

67

u32 evclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

68

u32 ecclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

100

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1032

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1098

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1152

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

126

u32 v = RREG32(mmDOUT_SCRATCH3);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

141

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1410

u16 reg_offset, u32 value)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1419

u16 reg_offset, u32 *value)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

142

u32 n = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

143

u32 prev_sclk = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1505

u32 mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1535

static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

163

u32 i, j;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1768

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2102

u32 enable_mask, i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2122

u32 enable_mask, i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2140

u32 sclk, u32 min_sclk_in_sr)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2143

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2144

u32 temp;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2145

u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2202

u32 min_sclk = 10000; /* ??? */

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2203

u32 sclk, mclk = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2208

u32 stable_p_state_sclk = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2313

u32 index, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2323

u32 sclk_in_sr = 10000; /* ??? */

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2324

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2341

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2345

u32 mclk = max_limits->mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2395

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2409

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2414

u32 vid_2bit;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2458

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2466

static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2468

u32 new_mask = (1 << level);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2478

u32 i, new_mask = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2493

u32 nbdpmconfig1;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2517

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2678

u32 sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2768

u32 sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2859

u32 current_index =

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2863

u32 sclk, tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2920

static u32 kv_dpm_get_sclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2932

static u32 kv_dpm_get_mclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2943

u32 temp;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3122

u32 cg_thermal_int;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3265

u32 pl_index =

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

379

u32 i, count, data;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

404

u32 data;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

405

u32 cache = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

452

u32 data;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

57

static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

575

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

652

u32 index, u32 sclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

676

u32 vid_2bit)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

679

u32 vid_8bit = kv_convert_vid2_to_vid7(adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

687

static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

698

static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

708

u32 index, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

717

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

72

static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

732

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

74

u32 vid_2bit)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

743

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

773

u32 low_sclk_interrupt_t = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

78

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

783

sizeof(u32), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

791

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

861

static u32 kv_get_clock_difference(u32 a, u32 b)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

866

static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

869

u32 value;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

898

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

94

static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

96

u32 vid_7bit)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

966

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

109

u32 num_levels;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

118

u32 bootup_uma_clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

119

u32 bootup_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

120

u32 dentist_vco_freq;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

121

u32 nb_dpm_enable;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

122

u32 nbp_memory_clock[KV_NUM_NBPSTATES];

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

123

u32 nbp_n_clock[KV_NUM_NBPSTATES];

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

129

u32 uma_channel_number;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

133

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

134

u32 voltage_drop_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

141

u32 lowest_valid;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

142

u32 highest_valid;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

147

u32 sram_end;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

148

u32 dpm_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

149

u32 soft_regs_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

178

u32 low_sclk_interrupt_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

217

int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

218

int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

220

PPSMC_Msg msg, u32 parameter);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

221

int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

222

u32 *value, u32 limit);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

226

u32 smc_start_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

227

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

43

u32 num_entries;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

48

u32 sclk_frequency;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

54

u32 num_max_dpm_entries;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

71

u32 offset;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

72

u32 mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

73

u32 shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

74

u32 value;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

79

u32 block_id;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

80

u32 signal_id;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

81

u32 t;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

85

u32 cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

86

u32 block_mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

87

u32 block_shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

88

u32 signal_mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

89

u32 signal_shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

90

u32 t_mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

91

u32 t_shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

92

u32 enable_mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

93

u32 enable_shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

97

u32 sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

122

u32 smc_start_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

123

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

126

u32 data, original_data, addr, extra_shift, t_byte, count, mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

32

int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

34

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

35

u32 tmp = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

56

int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

69

PPSMC_Msg msg, u32 parameter)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

78

u32 smc_address, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

92

int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

93

u32 *value, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

162

u32 size = atom_table->ucNumEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

348

u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table);

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

399

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

452

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

482

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

50

void amdgpu_dpm_dbg_print_class_info(struct amdgpu_device *adev, u32 class, u32 class2)

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

536

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

760

struct amd_vce_state* amdgpu_get_vce_clock_state(void *handle, u32 idx)

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

775

u32 ui_class;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

93

void amdgpu_dpm_dbg_print_cap_info(struct amdgpu_device *adev, u32 caps)

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.h

26

void amdgpu_dpm_dbg_print_class_info(struct amdgpu_device *adev, u32 class, u32 class2);

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.h

27

void amdgpu_dpm_dbg_print_cap_info(struct amdgpu_device *adev, u32 caps);

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.h

33

struct amd_vce_state* amdgpu_get_vce_clock_state(void *handle, u32 idx);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

130

static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

149

static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1856

u16 reg_offset, u32 value);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1861

u32 engine_clock,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1875

u16 v, s32 t, u32 ileakage, u32 *leakage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1905

u32 i_leakage,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1906

u32 *leakage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1912

const u32 fixed_kt, u16 v,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1913

u32 ileakage, u32 *leakage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1931

const u32 fixed_kt,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1933

u32 i_leakage,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1934

u32 *leakage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1943

u32 p_limit1 = adev->pm.dpm.tdp_limit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1944

u32 p_limit2 = adev->pm.dpm.near_tdp_limit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1945

u32 k = dte_data->k;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1946

u32 t_max = dte_data->max_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1947

u32 t_split[5] = { 10, 15, 20, 25, 30 };

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1948

u32 t_0 = dte_data->t0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1949

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1956

(t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1957

(p_limit2 * (u32)100);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2195

static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2200

static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2202

u32 xclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2203

u32 wintime;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2204

u32 cac_window;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2205

u32 cac_window_size;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2220

static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2227

u32 tdp_adjustment,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2228

u32 *tdp_limit,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2229

u32 *near_tdp_limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2231

u32 adjustment_delta, max_tdp_limit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2233

if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2268

u32 scaling_factor = si_get_smc_power_scaling_factor(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2269

u32 tdp_limit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2270

u32 near_tdp_limit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2301

sizeof(u32) * 3,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2342

sizeof(u32) * 2,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2400

u32 prev_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2401

u32 max_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2402

u32 min_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2446

min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2491

u32 sq_power_throttle, sq_power_throttle2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2581

u32 table_size;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2583

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2627

for (i = 0; i < (u32)tdep_count; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2648

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2649

u32 v0_loadline;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2692

u32 leakage;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2695

u32 smc_leakage;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2696

u32 scaling_factor;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2731

u32 leakage;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2733

u32 smc_leakage;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2734

u32 scaling_factor;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2768

u32 load_line_slope, reg;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2770

u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2810

load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2815

cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2816

cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2823

cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2824

cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2851

u32 data = 0, offset;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2962

u32 fb_div, p_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2963

u32 clk_s, clk_v;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2964

u32 sclk = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2966

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3046

u32 evclk, u32 ecclk, u16 *voltage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3048

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3080

u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3082

u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3102

u32 arb_freq_src, u32 arb_freq_dest)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3104

u32 mc_arb_dram_timing;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3105

u32 mc_arb_dram_timing2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3106

u32 burst_time;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3107

u32 mc_cg_config;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3239

static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3240

u32 max_clock, u32 requested_clock)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3256

static u32 btc_get_valid_mclk(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3257

u32 max_mclk, u32 requested_mclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3263

static u32 btc_get_valid_sclk(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3264

u32 max_sclk, u32 requested_sclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3271

u32 *max_clock)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3273

u32 i, clock = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3288

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3290

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3359

static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3360

u32 *p, u32 *u)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3362

u32 b_c = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3363

u32 i_c;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3364

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3378

static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3380

u32 k, a, ah, al;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3381

u32 t1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3399

static bool r600_is_uvd_state(u32 class, u32 class2)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3456

u32 mclk, sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3458

u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3459

u32 max_sclk = 0, max_mclk = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3460

u32 high_pixelclock_count = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3707

u16 reg_offset, u32 *value)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3718

u16 reg_offset, u32 value)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3730

u32 tmp, width, row, column, bank, density;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3775

u32 index, u16 *leakage_voltage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3801

static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3876

u32 thermal_level)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3908

PPSMC_Msg msg, u32 parameter)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3929

u32 levels = ps->performance_level_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4004

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4166

u32 voltage_response_time, acpi_delay_time, vbi_time_out;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4167

u32 vddc_dly, acpi_dly, vbi_dly;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4168

u32 reference_clock;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4172

voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4195

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4213

u32 tmp, pipe;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4262

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4320

u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4344

static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4357

static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4379

static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4413

u32 data, num_bits, num_levels;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4437

u32 max_voltage_steps,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4457

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4617

(u32)si_pi->vddc_phase_shed_table.phase_delay);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4647

static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4677

for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4681

if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4692

for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4696

if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4707

if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4727

u16 voltage, u32 sclk, u32 mclk,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4747

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4776

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4792

static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4793

u32 engine_clock)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4795

u32 dram_rows;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4796

u32 dram_refresh_rate;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4797

u32 mc_arb_rfsh_rate;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4798

u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4815

u32 dram_timing;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4816

u32 dram_timing2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4817

u32 burst_time;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4894

u32 reg;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5011

u32 sys_mask,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5041

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5042

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5043

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5044

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5045

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5046

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5047

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5048

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5049

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5050

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5051

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5052

u32 reg;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5183

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5248

u32 lane_width;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5249

u32 vr_hot_gpio;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5331

u32 engine_clock,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5337

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5338

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5339

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5340

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5341

u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5342

u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5344

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5345

u32 reference_divider;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5346

u32 fbdiv;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5358

fbdiv = (u32) tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5373

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5377

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5378

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5401

u32 engine_clock,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5422

u32 engine_clock,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5423

u32 memory_clock,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5430

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5431

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5432

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5433

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5434

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5435

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5436

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5437

u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5438

u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5464

u32 freq_nom;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5465

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5466

u32 reference_clock = adev->clock.mpll.reference_freq;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5477

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5478

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5636

u32 a_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5637

u32 t_l, t_h;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5638

u32 high_bsp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5738

u32 threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5739

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5815

u32 address = si_pi->state_table_start +

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5837

u32 address = si_pi->state_table_start +

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5840

u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5856

u32 crtc_index = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5857

u32 mclk_change_block_cp_min = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5858

u32 mclk_change_block_cp_max = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5893

u32 temp_reg;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6024

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6114

u32 i, j;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6132

u32 num_entries, u32 valid_flag)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6134

u32 i, j;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6149

u32 i = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6221

u32 address = si_pi->mc_reg_table_start +

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6261

u32 speed_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6337

bool ds_status_on, u32 count_write)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6398

u32 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6449

u32 lane_width;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6450

u32 new_lane_width =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6452

u32 current_lane_width =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6471

u32 thermal_int = RREG32(mmCG_THERMAL_INT);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6516

static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6519

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6542

u32 duty100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6543

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6545

u32 reference_clock, tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6637

u32 *speed)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6639

u32 duty, duty100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6657

*speed = min_t(u32, tmp64, 255);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6663

u32 speed)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6667

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6668

u32 duty, duty100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6687

duty = (u32)tmp64;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6696

static int si_dpm_set_fan_control_mode(void *handle, u32 mode)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6719

static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6723

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6739

u32 *speed)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6741

u32 tach_period;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6742

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6760

u32 speed)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6762

u32 tach_period, tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6763

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6792

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6816

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7389

u32 sclk, mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7588

u32 current_index =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7607

u32 cg_thermal_int;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7938

u32 temp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7955

static u32 si_dpm_get_sclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7967

static u32 si_dpm_get_mclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8073

u32 pl_index =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

1017

u32 t_min;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

1018

u32 fan_ctrl_default_mode;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

252

u32 at;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

253

u32 bt;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

254

u32 av;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

255

u32 bv;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

258

u32 t_ref;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

270

u32 mclk_max;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

271

u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

307

u32 mclk_max;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

308

u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

335

u32 mc_arb_dram_timing;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

336

u32 mc_arb_dram_timing2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

337

u32 mc_arb_rfsh_rate;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

338

u32 mc_arb_burst_time;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

342

u32 rlp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

343

u32 rmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

344

u32 lhp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

345

u32 lmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

349

u32 cg_spll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

350

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

351

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

352

u32 cg_spll_func_cntl_4;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

353

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

354

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

355

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

356

u32 dll_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

357

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

358

u32 mpll_ad_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

359

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

360

u32 mpll_dq_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

361

u32 mpll_ss1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

362

u32 mpll_ss2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

492

u32 low_smio;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

496

u32 cg_spll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

497

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

498

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

499

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

500

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

501

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

502

u32 mpll_ad_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

503

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

504

u32 mpll_dq_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

505

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

506

u32 dll_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

507

u32 mpll_ss1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

508

u32 mpll_ss2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

512

u32 cg_spll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

513

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

514

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

515

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

516

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

517

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

518

u32 dll_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

519

u32 mpll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

520

u32 mpll_func_cntl2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

521

u32 mpll_func_cntl3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

522

u32 mpll_ss;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

523

u32 mpll_ss2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

553

u32 s0_vid_lower_smio_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

555

u32 vddc_mask_low;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

556

u32 mvdd_mask_low;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

557

u32 mvdd_split_frequency;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

558

u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

565

u32 mclk_odt_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

569

u32 boot_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

571

u32 ref_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

572

u32 active_auto_throttle_sources;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

573

u32 mclk_stutter_mode_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

574

u32 mclk_strobe_mode_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

575

u32 mclk_edc_enable_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

576

u32 bsp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

577

u32 bsu;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

578

u32 pbsp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

579

u32 pbsu;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

580

u32 dsp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

581

u32 psp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

582

u32 asi;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

583

u32 pasi;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

584

u32 vrc;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

585

u32 restricted_levels;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

586

u32 rlp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

587

u32 rmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

588

u32 lhp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

589

u32 lmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

606

u32 sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

607

u32 mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

610

u32 flags;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

638

u32 i_leakage;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

640

u32 pwr_const;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

641

u32 dc_cac_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

642

u32 bif_cac_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

643

u32 lkge_pwr;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

673

u32 mclk_edc_wr_enable_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

830

u32 mclk_rtt_mode_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

848

u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

861

u32 offset;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

862

u32 mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

863

u32 shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

864

u32 value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

870

u32 cac_window;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

871

u32 l2_lta_window_size_default;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

876

u32 fixed_kt;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

877

u32 lkge_lut_v0_percent;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

884

u32 cac_leakage;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

886

u32 wintime;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

887

u32 l2_lta_window_size;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

896

u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

897

u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

898

u32 k;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

899

u32 t0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

900

u32 max_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

906

u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

907

u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

908

u32 t_threshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

913

u32 cg_spll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

914

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

915

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

916

u32 cg_spll_func_cntl_4;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

917

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

918

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

919

u32 dll_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

920

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

921

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

922

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

923

u32 mpll_func_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

924

u32 mpll_func_cntl_1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

925

u32 mpll_func_cntl_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

926

u32 mpll_ss1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

927

u32 mpll_ss2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

931

u32 mclk_max;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

932

u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

958

u32 cg_ulv_control;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

959

u32 cg_ulv_parameter;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

960

u32 volt_change_delay;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

975

u32 max_cu;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

980

u32 sys_pcie_mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

990

u32 sram_end;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

991

u32 state_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

992

u32 soft_regs_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

993

u32 mc_reg_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

994

u32 arb_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

995

u32 cac_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

996

u32 dte_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

997

u32 spll_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

998

u32 papm_cfg_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

999

u32 fan_table_start;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

119

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

128

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

149

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

161

u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

162

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

173

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

215

u32 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

231

int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

235

u32 ucode_start_address;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

236

u32 ucode_size;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

238

u32 data;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

273

int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

274

u32 *value, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

288

int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

289

u32 value, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

40

u32 smc_address, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

54

u32 smc_start_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

55

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

59

u32 data, original_data, addr, extra_shift;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

394

u32 smc_start_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

395

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

403

int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

404

int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

405

u32 *value, u32 limit);

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

406

int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

407

u32 value, u32 limit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

103

const u32 array_size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

106

u32 i, reg = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

27

static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

30

u32 timeout = 5000, data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

44

static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

45

u32 shift, u32 value, u32 timeout)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

48

u32 data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

84

const u32 array_size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

86

u32 i, reg = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

59

const u32 array_size);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

62

const u32 array_size);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1347

*((uint32_t *)value) = min(activity_percent, (u32)100);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4056

static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4060

u32 tmp = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

90

uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

92

u32 mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

93

u32 shift = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

97

extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1957

u32 i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

42

u32 display_cac;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

43

u32 bapm_temp_gradient;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1892

u32 mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1899

u32 tmp = param_led_dpm.mask_low;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

114

int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

194

static u32 smu_get_mclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

208

static u32 smu_get_sclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2373

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2375

u32 workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2544

u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3300

static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3318

static int smu_set_fan_control_mode(void *handle, u32 value)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3351

static int smu_get_fan_speed_pwm(void *handle, u32 *speed)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3370

static int smu_set_fan_speed_pwm(void *handle, u32 speed)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

69

static int smu_set_fan_speed_pwm(void *handle, u32 speed);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

70

static int smu_set_fan_control_mode(void *handle, u32 value);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1222

u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1227

u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1232

u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1763

int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

637

u32 param_reg;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

638

u32 msg_reg;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

639

u32 resp_reg;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

641

u32 debug_param_reg;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

642

u32 debug_msg_reg;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

643

u32 debug_resp_reg;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

795

int (*set_power_profile_mode)(struct smu_context *smu, u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

796

long *custom_params, u32 custom_params_max_idx);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1512

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1514

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1516

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1708

static u32 arcturus_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2079

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2081

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2083

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3106

static u32 navi10_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1780

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1782

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1784

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2612

static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

474

u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1061

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1063

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1065

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2304

static u32 vangogh_get_gfxoff_status(struct smu_context *smu)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2307

u32 reg, gfxoff_status;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2448

static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2451

u32 residency;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2478

static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2497

static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

863

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

865

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

868

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1608

static u32 aldebaran_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1918

u32 fatal_err, param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2665

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2667

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2669

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2735

u32 smu_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2831

static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

643

u32 idx, sensors;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

727

u32 inst_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

786

u32 inst_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2475

static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2639

u32 inst_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2756

u32 inst_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3037

u32 aid_temp, xcd_temp, max_temp;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3038

u32 ccd_temp = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3102

u32 fatal_err, param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3332

u32 instidhi, instid;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3449

u32 ext_error_code;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3450

u32 err_cnt;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3721

static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3750

enum aca_smu_type type, u32 *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3769

int idx, int offset, u32 *val)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3790

int idx, int offset, u32 *val, int count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3810

u32 data[2] = {0, 0};

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2616

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2618

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2620

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1210

u32 min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1211

u32 max,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1887

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1889

u32 custom_params_max_idx)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1891

u32 backend_workload_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2054

static u32 smu_v14_0_2_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

110

static u32 __smu_cmn_poll_stat(struct smu_context *smu)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

114

u32 reg;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1179

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1180

u32 *backend_workload_mask)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1183

u32 profile_mode;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

128

u32 reg_c2pmsg_90,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

130

u32 param,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

135

u32 msg_idx, prm;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

192

static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

239

u32 param)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

297

u32 msg,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

298

u32 param)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

326

u32 reg;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

371

u32 reg;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

429

u32 reg;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

202

u32 workload_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

203

u32 *backend_workload_mask);

sys/dev/pci/drm/apple/afk.c

137

u32 bufsz, end;

sys/dev/pci/drm/apple/afk.c

204

u32 channel)

sys/dev/pci/drm/apple/afk.c

206

for (u32 i = 0; i < ep->num_channels; i++)

sys/dev/pci/drm/apple/afk.c

213

static void afk_recv_handle_init(struct apple_dcp_afkep *ep, u32 channel,

sys/dev/pci/drm/apple/afk.c

218

u32 ch_idx;

sys/dev/pci/drm/apple/afk.c

291

static void afk_recv_handle_teardown(struct apple_dcp_afkep *ep, u32 channel)

sys/dev/pci/drm/apple/afk.c

314

static void afk_recv_handle_reply(struct apple_dcp_afkep *ep, u32 channel,

sys/dev/pci/drm/apple/afk.c

398

static void afk_recv_handle_std_service(struct apple_dcp_afkep *ep, u32 channel,

sys/dev/pci/drm/apple/afk.c

399

u32 type, struct epic_hdr *ehdr,

sys/dev/pci/drm/apple/afk.c

462

static void afk_recv_handle(struct apple_dcp_afkep *ep, u32 channel, u32 type,

sys/dev/pci/drm/apple/afk.c

53

struct apple_dcp_afkep *afk_init(struct apple_dcp *dcp, u32 endpoint,

sys/dev/pci/drm/apple/afk.c

541

u32 rptr, wptr;

sys/dev/pci/drm/apple/afk.c

542

u32 magic, size, channel, type;

sys/dev/pci/drm/apple/afk.c

694

int afk_send_epic(struct apple_dcp_afkep *ep, u32 channel, u16 tag,

sys/dev/pci/drm/apple/afk.c

698

u32 rptr, wptr;

sys/dev/pci/drm/apple/afk.c

840

size_t output_len, u32 *retcode)

sys/dev/pci/drm/apple/afk.c

938

int afk_service_call(struct apple_epic_service *service, u16 group, u32 command,

sys/dev/pci/drm/apple/afk.c

947

u32 retcode;

sys/dev/pci/drm/apple/afk.c

948

u32 retlen;

sys/dev/pci/drm/apple/afk.h

149

u32 rptr;

sys/dev/pci/drm/apple/afk.h

157

u32 endpoint;

sys/dev/pci/drm/apple/afk.h

176

u32 num_channels;

sys/dev/pci/drm/apple/afk.h

179

struct apple_dcp_afkep *afk_init(struct apple_dcp *dcp, u32 endpoint,

sys/dev/pci/drm/apple/afk.h

183

int afk_send_epic(struct apple_dcp_afkep *ep, u32 channel, u16 tag,

sys/dev/pci/drm/apple/afk.h

188

size_t output_len, u32 *retcode);

sys/dev/pci/drm/apple/afk.h

189

int afk_service_call(struct apple_epic_service *service, u16 group, u32 command,

sys/dev/pci/drm/apple/afk.h

31

u32 retcode;

sys/dev/pci/drm/apple/afk.h

46

u32 channel;

sys/dev/pci/drm/apple/afk.h

59

int (*call)(struct apple_epic_service *service, u32 idx,

sys/dev/pci/drm/apple/afk.h

69

u32 unk;

sys/dev/pci/drm/apple/afk.h

70

u32 _pad1[14];

sys/dev/pci/drm/apple/afk.h

72

u32 _pad2[15];

sys/dev/pci/drm/apple/afk.h

74

u32 _pad3[15];

sys/dev/pci/drm/apple/apple_drv.c

148

static const u32 dcp_formats[] = {

sys/dev/pci/drm/apple/dcp-internal.h

103

u32 num_dptx_ports;

sys/dev/pci/drm/apple/dcp-internal.h

143

u32 disp_bw_scratch_index;

sys/dev/pci/drm/apple/dcp-internal.h

144

u32 disp_bw_scratch_offset;

sys/dev/pci/drm/apple/dcp-internal.h

145

u32 disp_bw_doorbell_index;

sys/dev/pci/drm/apple/dcp-internal.h

146

u32 disp_bw_doorbell_offset;

sys/dev/pci/drm/apple/dcp-internal.h

148

u32 index;

sys/dev/pci/drm/apple/dcp-internal.h

172

u32 last_swap_id;

sys/dev/pci/drm/apple/dcp-internal.h

240

u32 dptx_phy;

sys/dev/pci/drm/apple/dcp-internal.h

241

u32 dptx_die;

sys/dev/pci/drm/apple/dcp-internal.h

78

u32 swap_id;

sys/dev/pci/drm/apple/dcp-internal.h

85

u32 maximum;

sys/dev/pci/drm/apple/dcp-internal.h

86

u32 dac;

sys/dev/pci/drm/apple/dcp.c

261

static int dcp_dptx_connect(struct apple_dcp *dcp, u32 port)

sys/dev/pci/drm/apple/dcp.c

306

static int dcp_dptx_disconnect(struct apple_dcp *dcp, u32 port)

sys/dev/pci/drm/apple/dcp.c

577

static int dcp_get_bw_scratch_reg(struct apple_dcp *dcp, u32 expected)

sys/dev/pci/drm/apple/dcp.c

580

u32 addr_idx, disp_idx, offset;

sys/dev/pci/drm/apple/dcp.c

629

static int dcp_get_bw_doorbell_reg(struct apple_dcp *dcp, u32 expected)

sys/dev/pci/drm/apple/dcp.c

632

u32 addr_idx, disp_idx;

sys/dev/pci/drm/apple/dcp.c

713

u32 ver[DCP_FW_VERSION_MAX_LEN];

sys/dev/pci/drm/apple/dcp.c

790

u32 cpu_ctrl;

sys/dev/pci/drm/apple/dcp.c

938

u32 mux_index;

sys/dev/pci/drm/apple/dcp_backlight.c

112

static u32 calculate_dac(struct apple_dcp *dcp, int val)

sys/dev/pci/drm/apple/dcp_backlight.c

114

u32 dac;

sys/dev/pci/drm/apple/dcp_backlight.c

25

static u32 brightness_part1[] = {

sys/dev/pci/drm/apple/dcp_backlight.c

60

static u32 brightness_part12[] = { 0x58f058d, 0x59d058f };

sys/dev/pci/drm/apple/dcp_backlight.c

65

static u32 brightness_part2[] = {

sys/dev/pci/drm/apple/dcp_backlight.c

94

static u32 interpolate(int val, int min, int max, u32 *tbl, size_t tbl_size)

sys/dev/pci/drm/apple/dcp_backlight.c

96

u32 frac;

sys/dev/pci/drm/apple/dcp_backlight.c

98

u32 interpolated = (tbl_size - 1) * ((val - min) * SCALE_FACTOR) / (max - min);

sys/dev/pci/drm/apple/dptxep.c

105

u32 unk_field = 0x0; // seen as 0x100 under some conditions

sys/dev/pci/drm/apple/dptxep.c

107

u32 target = FIELD_PREP(DCPDPTX_REMOTE_PORT_CORE, core) |

sys/dev/pci/drm/apple/dptxep.c

351

u32 link_rate, phy_link_rate;

sys/dev/pci/drm/apple/dptxep.c

477

static int dptxport_call(struct apple_epic_service *service, u32 idx,

sys/dev/pci/drm/apple/dptxep.c

577

u32 port;

sys/dev/pci/drm/apple/dptxep.c

78

u32 target = FIELD_PREP(DCPDPTX_REMOTE_PORT_CORE, core) |

sys/dev/pci/drm/apple/dptxep.h

53

u32 unit;

sys/dev/pci/drm/apple/dptxep.h

58

u32 lane_count;

sys/dev/pci/drm/apple/dptxep.h

59

u32 link_rate, pending_link_rate;

sys/dev/pci/drm/apple/dptxep.h

60

u32 drive_settings[2];

sys/dev/pci/drm/apple/iomfb.c

157

u32 in_len, u32 out_len, void *data, dcp_callback_t cb,

sys/dev/pci/drm/apple/iomfb.c

200

u32 d[3];

sys/dev/pci/drm/apple/iomfb.c

207

d[i] = (u32)(tag[i] - '0');

sys/dev/pci/drm/apple/iomfb.c

258

void *data, u32 length, u16 offset)

sys/dev/pci/drm/apple/iomfb.c

290

void *data, u32 length)

sys/dev/pci/drm/apple/iomfb.c

318

u32 length;

sys/dev/pci/drm/apple/iomfb.c

354

u32 drm_format_to_dcp(u32 drm)

sys/dev/pci/drm/apple/iomfb.c

70

static inline u64 dcpep_msg(enum dcp_context_id id, u32 length, u16 offset)

sys/dev/pci/drm/apple/iomfb.h

103

u32 x;

sys/dev/pci/drm/apple/iomfb.h

104

u32 y;

sys/dev/pci/drm/apple/iomfb.h

105

u32 w;

sys/dev/pci/drm/apple/iomfb.h

106

u32 h;

sys/dev/pci/drm/apple/iomfb.h

116

u32 width;

sys/dev/pci/drm/apple/iomfb.h

117

u32 height;

sys/dev/pci/drm/apple/iomfb.h

118

u32 base;

sys/dev/pci/drm/apple/iomfb.h

119

u32 offset;

sys/dev/pci/drm/apple/iomfb.h

120

u32 stride;

sys/dev/pci/drm/apple/iomfb.h

121

u32 size;

sys/dev/pci/drm/apple/iomfb.h

125

u32 unk[13];

sys/dev/pci/drm/apple/iomfb.h

145

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

152

u32 unk2;

sys/dev/pci/drm/apple/iomfb.h

153

u32 doorbell_bit;

sys/dev/pci/drm/apple/iomfb.h

154

u32 padding[7];

sys/dev/pci/drm/apple/iomfb.h

215

u32 color_mode_id;

sys/dev/pci/drm/apple/iomfb.h

216

u32 timing_mode_id;

sys/dev/pci/drm/apple/iomfb.h

230

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

242

u32 unk0;

sys/dev/pci/drm/apple/iomfb.h

244

u32 unk2;

sys/dev/pci/drm/apple/iomfb.h

255

u32 mem_desc_id;

sys/dev/pci/drm/apple/iomfb.h

261

u32 flags;

sys/dev/pci/drm/apple/iomfb.h

270

u32 mem_desc_id;

sys/dev/pci/drm/apple/iomfb.h

274

u32 swap_id;

sys/dev/pci/drm/apple/iomfb.h

282

u32 swap_id;

sys/dev/pci/drm/apple/iomfb.h

284

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

312

u32 value;

sys/dev/pci/drm/apple/iomfb.h

323

u32 unkint;

sys/dev/pci/drm/apple/iomfb.h

324

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

329

u32 offset;

sys/dev/pci/drm/apple/iomfb.h

330

u32 length;

sys/dev/pci/drm/apple/iomfb.h

338

u32 param;

sys/dev/pci/drm/apple/iomfb.h

339

u32 value[8];

sys/dev/pci/drm/apple/iomfb.h

340

u32 count;

sys/dev/pci/drm/apple/iomfb.h

344

u32 swap_id;

sys/dev/pci/drm/apple/iomfb.h

346

u32 unkInt;

sys/dev/pci/drm/apple/iomfb.h

347

u32 width;

sys/dev/pci/drm/apple/iomfb.h

348

u32 height;

sys/dev/pci/drm/apple/iomfb.h

353

u32 count;

sys/dev/pci/drm/apple/iomfb.h

354

u32 value[8];

sys/dev/pci/drm/apple/iomfb.h

358

u32 value[8];

sys/dev/pci/drm/apple/iomfb.h

363

u32 id;

sys/dev/pci/drm/apple/iomfb.h

364

u32 value;

sys/dev/pci/drm/apple/iomfb.h

368

u32 mode;

sys/dev/pci/drm/apple/iomfb.h

374

u32 mode;

sys/dev/pci/drm/apple/iomfb.h

375

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

384

u32 unkint;

sys/dev/pci/drm/apple/iomfb.h

389

u32 unk;

sys/dev/pci/drm/apple/iomfb.h

403

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

407

u32 unk_u32; // maybe length?

sys/dev/pci/drm/apple/iomfb.h

416

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

420

u32 event;

sys/dev/pci/drm/apple/iomfb.h

421

u32 param;

sys/dev/pci/drm/apple/iomfb.h

422

u32 value;

sys/dev/pci/drm/apple/iomfb.h

428

u32 value;

sys/dev/pci/drm/apple/iomfb.h

429

u32 ret;

sys/dev/pci/drm/apple/iomfb.h

64

u32 in_len;

sys/dev/pci/drm/apple/iomfb.h

65

u32 out_len;

sys/dev/pci/drm/apple/iomfb.h

96

u32 unk;

sys/dev/pci/drm/apple/iomfb_internal.h

104

u32 in_len, u32 out_len, void *data, dcp_callback_t cb,

sys/dev/pci/drm/apple/iomfb_internal.h

119

u32 drm_format_to_dcp(u32 drm);

sys/dev/pci/drm/apple/iomfb_template.c

1037

dcpep_cb_abort_swap_ap_gated(struct apple_dcp *dcp, u32 *swap_id)

sys/dev/pci/drm/apple/iomfb_template.c

1060

TRAMPOLINE_OUT(trampoline_zero, dcpep_cb_zero, u32);

sys/dev/pci/drm/apple/iomfb_template.c

1078

TRAMPOLINE_INOUT(trampoline_release_mem_desc, dcpep_cb_release_mem_desc, u32,

sys/dev/pci/drm/apple/iomfb_template.c

1085

TRAMPOLINE_INOUT(trampoline_prop_start, dcpep_cb_prop_start, u32, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1103

TRAMPOLINE_IN(trampoline_abort_swap_ap_gated, dcpep_cb_abort_swap_ap_gated, u32);

sys/dev/pci/drm/apple/iomfb_template.c

115

static u32 dcpep_cb_zero(struct apple_dcp *dcp)

sys/dev/pci/drm/apple/iomfb_template.c

1453

u32 val = 0;

sys/dev/pci/drm/apple/iomfb_template.c

339

u32 id;

sys/dev/pci/drm/apple/iomfb_template.c

369

static u8 dcpep_cb_release_mem_desc(struct apple_dcp *dcp, u32 *mem_desc_id)

sys/dev/pci/drm/apple/iomfb_template.c

372

u32 id = *mem_desc_id;

sys/dev/pci/drm/apple/iomfb_template.c

428

u32 id;

sys/dev/pci/drm/apple/iomfb_template.c

504

static u8 dcpep_cb_prop_start(struct apple_dcp *dcp, u32 *length)

sys/dev/pci/drm/apple/iomfb_template.c

51

DCP_THUNK_OUT(iomfb_a131_pmu_service_matched, iomfbep_a131_pmu_service_matched, u32);

sys/dev/pci/drm/apple/iomfb_template.c

52

DCP_THUNK_OUT(iomfb_a132_backlight_service_matched, iomfbep_a132_backlight_service_matched, u32);

sys/dev/pci/drm/apple/iomfb_template.c

53

DCP_THUNK_OUT(iomfb_a358_vi_set_temperature_hint, iomfbep_a358_vi_set_temperature_hint, u32);

sys/dev/pci/drm/apple/iomfb_template.c

619

u32 v_true = 1;

sys/dev/pci/drm/apple/iomfb_template.c

628

u32 v_true = true;

sys/dev/pci/drm/apple/iomfb_template.c

670

u32 offset = dcp->disp_bw_scratch_offset;

sys/dev/pci/drm/apple/iomfb_template.c

671

u32 index = dcp->disp_bw_scratch_index;

sys/dev/pci/drm/apple/iomfb_template.c

676

u32 index = dcp->disp_bw_doorbell_index;

sys/dev/pci/drm/apple/iomfb_template.c

706

u32 swap_id;

sys/dev/pci/drm/apple/iomfb_template.c

72

struct dcp_set_digital_out_mode_req, u32);

sys/dev/pci/drm/apple/iomfb_template.c

74

DCP_THUNK_INOUT(dcp_set_display_device, dcpep_set_display_device, u32, u32);

sys/dev/pci/drm/apple/iomfb_template.c

77

dcpep_set_display_refresh_properties, u32);

sys/dev/pci/drm/apple/iomfb_template.c

798

u32 handle;

sys/dev/pci/drm/apple/iomfb_template.c

80

DCP_THUNK_INOUT(dcp_late_init_signal, dcpep_late_init_signal, u32, u32);

sys/dev/pci/drm/apple/iomfb_template.c

82

DCP_THUNK_OUT(dcp_late_init_signal, dcpep_late_init_signal, u32);

sys/dev/pci/drm/apple/iomfb_template.c

84

DCP_THUNK_IN(dcp_flush_supports_power, dcpep_flush_supports_power, u32);

sys/dev/pci/drm/apple/iomfb_template.c

85

DCP_THUNK_OUT(dcp_create_default_fb, dcpep_create_default_fb, u32);

sys/dev/pci/drm/apple/iomfb_template.c

86

DCP_THUNK_OUT(dcp_start_signal, dcpep_start_signal, u32);

sys/dev/pci/drm/apple/iomfb_template.c

92

struct dcp_set_parameter_dcp, u32);

sys/dev/pci/drm/apple/iomfb_template.c

95

dcpep_enable_disable_video_power_savings, u32, int);

sys/dev/pci/drm/apple/iomfb_template.c

97

DCP_THUNK_OUT(dcp_is_main_display, dcpep_is_main_display, u32);

sys/dev/pci/drm/apple/iomfb_template.h

108

u32 clear; // or maybe switch to default fb?

sys/dev/pci/drm/apple/iomfb_template.h

110

u32 unkU32Ptr;

sys/dev/pci/drm/apple/iomfb_template.h

128

u32 unkU32out;

sys/dev/pci/drm/apple/iomfb_template.h

130

u32 ret;

sys/dev/pci/drm/apple/iomfb_template.h

135

u32 swap_id;

sys/dev/pci/drm/apple/iomfb_template.h

143

u32 unkint;

sys/dev/pci/drm/apple/iomfb_template.h

149

u32 index;

sys/dev/pci/drm/apple/iomfb_template.h

150

u32 flags;

sys/dev/pci/drm/apple/iomfb_template.h

169

u32 ret;

sys/dev/pci/drm/apple/iomfb_template.h

25

u32 swap_id;

sys/dev/pci/drm/apple/iomfb_template.h

27

u32 surf_ids[SWAP_SURFACES];

sys/dev/pci/drm/apple/iomfb_template.h

29

u32 surf_flags[SWAP_SURFACES];

sys/dev/pci/drm/apple/iomfb_template.h

30

u32 surf_unk[SWAP_SURFACES];

sys/dev/pci/drm/apple/iomfb_template.h

32

u32 swap_enabled;

sys/dev/pci/drm/apple/iomfb_template.h

33

u32 swap_completed;

sys/dev/pci/drm/apple/iomfb_template.h

35

u32 bg_color;

sys/dev/pci/drm/apple/iomfb_template.h

37

u32 unk_2c8;

sys/dev/pci/drm/apple/iomfb_template.h

39

u32 unk_2e0;

sys/dev/pci/drm/apple/iomfb_template.h

46

u32 bl_value; // min value is 0x10000000

sys/dev/pci/drm/apple/iomfb_template.h

60

u32 plane_cnt;

sys/dev/pci/drm/apple/iomfb_template.h

61

u32 plane_cnt2;

sys/dev/pci/drm/apple/iomfb_template.h

62

u32 format; /* DCP fourcc */

sys/dev/pci/drm/apple/iomfb_template.h

63

u32 ycbcr_matrix;

sys/dev/pci/drm/apple/iomfb_template.h

66

u32 stride;

sys/dev/pci/drm/apple/iomfb_template.h

70

u32 offset;

sys/dev/pci/drm/apple/iomfb_template.h

71

u32 width;

sys/dev/pci/drm/apple/iomfb_template.h

72

u32 height;

sys/dev/pci/drm/apple/iomfb_template.h

73

u32 buf_size;

sys/dev/pci/drm/apple/iomfb_template.h

75

u32 surface_id;

sys/dev/pci/drm/apple/iomfb_template.h

80

u32 compression_info[MAX_PLANES][13];

sys/dev/pci/drm/apple/iomfb_template.h

82

u32 unk_num;

sys/dev/pci/drm/apple/iomfb_template.h

83

u32 unk_denom;

sys/dev/pci/drm/apple/parser.c

226

u32 idx, len;

sys/dev/pci/drm/apple/parser.c

255

const u32 *header;

sys/dev/pci/drm/apple/parser.c

419

static u32 calculate_clock(struct dimension *horiz, struct dimension *vert)

sys/dev/pci/drm/apple/parser.c

421

u32 pixels = horiz->total * vert->total;

sys/dev/pci/drm/apple/parser.c

44

static const u32 *parse_u32(struct dcp_parse_ctx *ctx)

sys/dev/pci/drm/apple/parser.c

46

return parse_bytes(ctx, sizeof(u32));

sys/dev/pci/drm/apple/parser.h

130

u32 timestamp;

sys/dev/pci/drm/apple/parser.h

131

u32 millinits;

sys/dev/pci/drm/apple/parser.h

132

u32 idac;

sys/dev/pci/drm/apple/parser.h

15

u32 pos, len;

sys/dev/pci/drm/apple/parser.h

74

u32 id;

sys/dev/pci/drm/apple/parser.h

88

u32 color_mode_id;

sys/dev/pci/drm/apple/parser.h

89

u32 timing_mode_id;

sys/dev/pci/drm/apple/trace.h

130

TP_PROTO(struct apple_dcp_afkep *ep, u32 rptr, u32 wptr),

sys/dev/pci/drm/apple/trace.h

134

__field(u8, endpoint) __field(u32, rptr)

sys/dev/pci/drm/apple/trace.h

135

__field(u32, wptr)),

sys/dev/pci/drm/apple/trace.h

147

TP_PROTO(struct apple_dcp_afkep *ep, u32 rptr, u32 wptr),

sys/dev/pci/drm/apple/trace.h

150

TP_PROTO(struct apple_dcp_afkep *ep, u32 rptr, u32 wptr),

sys/dev/pci/drm/apple/trace.h

153

TP_PROTO(struct apple_dcp_afkep *ep, u32 rptr, u32 wptr),

sys/dev/pci/drm/apple/trace.h

156

TP_PROTO(struct apple_dcp_afkep *ep, u32 rptr, u32 wptr),

sys/dev/pci/drm/apple/trace.h

161

TP_PROTO(struct apple_dcp_afkep *ep, u32 rptr, u32 magic, u32 size),

sys/dev/pci/drm/apple/trace.h

165

__field(u8, endpoint) __field(u32, rptr)

sys/dev/pci/drm/apple/trace.h

166

__field(u32, magic)

sys/dev/pci/drm/apple/trace.h

167

__field(u32, size)),

sys/dev/pci/drm/apple/trace.h

180

TP_PROTO(struct apple_dcp_afkep *ep, u32 channel, u32 type,

sys/dev/pci/drm/apple/trace.h

181

u32 data_size, struct epic_hdr *ehdr,

sys/dev/pci/drm/apple/trace.h

186

u8, endpoint) __field(u32, channel) __field(u32, type)

sys/dev/pci/drm/apple/trace.h

187

__field(u32, data_size) __field(u8, category)

sys/dev/pci/drm/apple/trace.h

251

TP_PROTO(struct apple_dcp *dcp, u32 swap_id),

sys/dev/pci/drm/apple/trace.h

255

__field(u32, swap_id)

sys/dev/pci/drm/apple/trace.h

267

TP_PROTO(struct apple_dcp *dcp, u32 swap_id),

sys/dev/pci/drm/apple/trace.h

271

__field(u32, swap_id)

sys/dev/pci/drm/apple/trace.h

284

TP_PROTO(struct apple_dcp *dcp, u32 swap_id, u32 width, u32 height),

sys/dev/pci/drm/apple/trace.h

288

__field(u32, swap_id)

sys/dev/pci/drm/apple/trace.h

289

__field(u32, width)

sys/dev/pci/drm/apple/trace.h

290

__field(u32, height)

sys/dev/pci/drm/apple/trace.h

307

TP_PROTO(struct apple_dcp *dcp, u32 swap_id),

sys/dev/pci/drm/apple/trace.h

311

__field(u32, swap_id)

sys/dev/pci/drm/apple/trace.h

372

__field(u32, unit) __field(int, idx) __field(size_t, len)),

sys/dev/pci/drm/apple/trace.h

387

__field(u32, unit) __field(u8, core) __field(u8, atc) __field(u8, die)),

sys/dev/pci/drm/apple/trace.h

401

__field(u32, unit) __field(u8, core) __field(u8, atc) __field(u8, die)),

sys/dev/pci/drm/apple/trace.h

411

TP_PROTO(struct dptx_port *dptx, u32 link_rate),

sys/dev/pci/drm/apple/trace.h

415

__field(u32, unit)

sys/dev/pci/drm/apple/trace.h

416

__field(u32, link_rate)),

sys/dev/pci/drm/apple/trace.h

426

TP_PROTO(struct apple_dcp *dcp, u32 nits),

sys/dev/pci/drm/apple/trace.h

430

__field(u32, nits)

sys/dev/pci/drm/apple/trace.h

494

TP_PROTO(struct apple_dcp *dcp, u32 id, u32 score, u32 depth,

sys/dev/pci/drm/apple/trace.h

495

u32 colorimetry, u32 eotf, u32 range, u32 pixel_enc),

sys/dev/pci/drm/apple/trace.h

499

__field(u32, id)

sys/dev/pci/drm/apple/trace.h

500

__field(u32, score)

sys/dev/pci/drm/apple/trace.h

501

__field(u32, depth)

sys/dev/pci/drm/apple/trace.h

502

__field(u32, colorimetry)

sys/dev/pci/drm/apple/trace.h

503

__field(u32, eotf)

sys/dev/pci/drm/apple/trace.h

504

__field(u32, range)

sys/dev/pci/drm/apple/trace.h

505

__field(u32, pixel_enc)

sys/dev/pci/drm/apple/trace.h

512

__entry->colorimetry = min_t(u32, colorimetry, 17U);

sys/dev/pci/drm/apple/trace.h

513

__entry->eotf = min_t(u32, eotf, 4U);

sys/dev/pci/drm/apple/trace.h

514

__entry->range = min_t(u32, range, 2U);

sys/dev/pci/drm/apple/trace.h

515

__entry->pixel_enc = min_t(u32, pixel_enc, 15U);

sys/dev/pci/drm/apple/trace.h

530

TP_PROTO(struct apple_dcp *dcp, u32 id, u32 score, u32 width,

sys/dev/pci/drm/apple/trace.h

531

u32 height, u32 clock, u32 color_mode),

sys/dev/pci/drm/apple/trace.h

535

__field(u32, id)

sys/dev/pci/drm/apple/trace.h

536

__field(u32, score)

sys/dev/pci/drm/apple/trace.h

537

__field(u32, width)

sys/dev/pci/drm/apple/trace.h

538

__field(u32, height)

sys/dev/pci/drm/apple/trace.h

539

__field(u32, clock)

sys/dev/pci/drm/apple/trace.h

540

__field(u32, color_mode)

sys/dev/pci/drm/apple/trace.h

564

TP_PROTO(struct apple_dcp *dcp, u32 rates, u64 formats, unsigned int nchans),

sys/dev/pci/drm/apple/trace.h

568

__field(u32, rates)

sys/dev/pci/drm/clients/drm_client_setup.c

72

void drm_client_setup_with_fourcc(struct drm_device *dev, u32 fourcc)

sys/dev/pci/drm/clients/drm_client_setup.c

91

u32 fourcc = drm_driver_color_mode_format(dev, color_mode);

sys/dev/pci/drm/clients/drm_log.c

114

u32 px_width = fb->format->cpp[0];

sys/dev/pci/drm/clients/drm_log.c

117

u32 i;

sys/dev/pci/drm/clients/drm_log.c

124

u32 color = (i < prefix_len) ? scanout->prefix_color : scanout->front_color;

sys/dev/pci/drm/clients/drm_log.c

161

u32 prefix_len = 0;

sys/dev/pci/drm/clients/drm_log.c

180

static u32 drm_log_find_usable_format(struct drm_plane *plane)

sys/dev/pci/drm/clients/drm_log.c

195

u32 width = mode_set->mode->hdisplay;

sys/dev/pci/drm/clients/drm_log.c

196

u32 height = mode_set->mode->vdisplay;

sys/dev/pci/drm/clients/drm_log.c

197

u32 format;

sys/dev/pci/drm/clients/drm_log.c

43

u32 rows;

sys/dev/pci/drm/clients/drm_log.c

44

u32 columns;

sys/dev/pci/drm/clients/drm_log.c

45

u32 scaled_font_h;

sys/dev/pci/drm/clients/drm_log.c

46

u32 scaled_font_w;

sys/dev/pci/drm/clients/drm_log.c

47

u32 line;

sys/dev/pci/drm/clients/drm_log.c

48

u32 format;

sys/dev/pci/drm/clients/drm_log.c

49

u32 px_width;

sys/dev/pci/drm/clients/drm_log.c

50

u32 front_color;

sys/dev/pci/drm/clients/drm_log.c

51

u32 prefix_color;

sys/dev/pci/drm/clients/drm_log.c

59

u32 n_scanout;

sys/dev/pci/drm/clients/drm_log.c

75

u32 height, u32 width, u32 px_width, u32 color)

sys/dev/pci/drm/clients/drm_log.c

92

static void drm_log_clear_line(struct drm_log_scanout *scanout, u32 line)

sys/dev/pci/drm/display/drm_dp_helper.c

1869

static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)

sys/dev/pci/drm/display/drm_dp_helper.c

2526

u32 quirks;

sys/dev/pci/drm/display/drm_dp_helper.c

2564

static u32

sys/dev/pci/drm/display/drm_dp_helper.c

2568

u32 quirks = 0;

sys/dev/pci/drm/display/drm_dp_helper.c

3966

u32 level)

sys/dev/pci/drm/display/drm_dp_helper.c

4055

const u32 level)

sys/dev/pci/drm/display/drm_dp_helper.c

4310

u32 max_luminance,

sys/dev/pci/drm/display/drm_dp_helper.c

4312

u32 *current_level, u8 *current_mode, bool need_luminance)

sys/dev/pci/drm/display/drm_dp_helper.c

4424

u32 current_level;

sys/dev/pci/drm/display/drm_dp_helper.c

4546

u32 overhead = 1000000;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1155

u8 port_num, u32 offset, u8 num_bytes, u8 *bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1636

u32 rem_nsec = do_div(ts_nsec, 1000000000);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2729

u8 port_num, u32 offset, u8 num_bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5959

static u32 drm_dp_mst_i2c_functionality(struct i2c_adapter *adapter)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1611

u32 stream_mask = 0;

sys/dev/pci/drm/display/drm_dp_tunnel.c

163

u32 stream_mask;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1630

static int stream_id_to_idx(u32 stream_mask, u8 stream_id)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1781

u32 *stream_mask)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1800

u32 *failed_stream_mask)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1804

u32 group_stream_mask = 0;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1858

u32 *failed_stream_mask)

sys/dev/pci/drm/display/drm_dsc_helper.c

1447

u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg)

sys/dev/pci/drm/display/drm_dsc_helper.c

1472

u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc)

sys/dev/pci/drm/display/drm_hdcp_helper.c

14

drm_hdcp_check_ksvs_revoked(struct drm_device *drm_dev, u8 *ksvs, u32 ksv_count)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

38

u32 signal_free_time, struct cec_msg *msg)

sys/dev/pci/drm/display/drm_hdmi_helper.c

106

static const u32 hdmi_colorimetry_val[] = {

sys/dev/pci/drm/display/drm_hdmi_helper.c

133

u32 colorimetry_val;

sys/dev/pci/drm/display/drm_hdmi_helper.c

134

u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;

sys/dev/pci/drm/dma-resv.c

65

u32 num_fences, max_fences;

sys/dev/pci/drm/drm_atomic_helper.c

4064

u32 *

sys/dev/pci/drm/drm_atomic_helper.c

4069

u32 output_fmt,

sys/dev/pci/drm/drm_atomic_helper.c

4072

u32 *input_fmts;

sys/dev/pci/drm/drm_atomic_helper.c

852

u32 *formats;

sys/dev/pci/drm/drm_atomic_helper.c

860

nformats = pixel_format_blob->length / sizeof(u32);

sys/dev/pci/drm/drm_bridge.c

1079

u32 *out_bus_fmts;

sys/dev/pci/drm/drm_bridge.c

1138

u32 output_flags = 0;

sys/dev/pci/drm/drm_bridge.c

953

u32 out_bus_fmt)

sys/dev/pci/drm/drm_bridge.c

959

u32 *in_bus_fmts;

sys/dev/pci/drm/drm_client.c

186

drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height,

sys/dev/pci/drm/drm_client.c

187

u32 format, u32 *handle)

sys/dev/pci/drm/drm_client.c

351

u32 width, u32 height, u32 format,

sys/dev/pci/drm/drm_client.c

352

u32 handle)

sys/dev/pci/drm/drm_client.c

395

drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format)

sys/dev/pci/drm/drm_client.c

398

u32 handle;

sys/dev/pci/drm/drm_color_mgmt.c

136

u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n)

sys/dev/pci/drm/drm_color_mgmt.c

246

u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;

sys/dev/pci/drm/drm_color_mgmt.c

247

u32 degamma_id = crtc->dev->mode_config.degamma_lut_property->base.id;

sys/dev/pci/drm/drm_color_mgmt.c

279

u32 size,

sys/dev/pci/drm/drm_color_mgmt.c

287

u32 gamma_id = dev->mode_config.gamma_lut_property->base.id;

sys/dev/pci/drm/drm_color_mgmt.c

288

u32 degamma_id = dev->mode_config.degamma_lut_property->base.id;

sys/dev/pci/drm/drm_color_mgmt.c

532

u32 supported_encodings,

sys/dev/pci/drm/drm_color_mgmt.c

533

u32 supported_ranges,

sys/dev/pci/drm/drm_color_mgmt.c

606

int drm_color_lut_check(const struct drm_property_blob *lut, u32 tests)

sys/dev/pci/drm/drm_connector.c

1196

const u32 *formats,

sys/dev/pci/drm/drm_connector.c

1199

u32 *fmts = NULL;

sys/dev/pci/drm/drm_connector.c

1378

static const u32 hdmi_colorspaces =

sys/dev/pci/drm/drm_connector.c

1396

static const u32 dp_colorspaces =

sys/dev/pci/drm/drm_connector.c

2427

u32 scaling_mode_mask)

sys/dev/pci/drm/drm_connector.c

2575

u32 supported_colorspaces)

sys/dev/pci/drm/drm_connector.c

2578

u32 colorspaces = supported_colorspaces | BIT(DRM_MODE_COLORIMETRY_DEFAULT);

sys/dev/pci/drm/drm_connector.c

2630

u32 supported_colorspaces)

sys/dev/pci/drm/drm_connector.c

2632

u32 colorspaces;

sys/dev/pci/drm/drm_connector.c

2655

u32 supported_colorspaces)

sys/dev/pci/drm/drm_connector.c

2657

u32 colorspaces;

sys/dev/pci/drm/drm_crtc.c

821

u32 out_id;

sys/dev/pci/drm/drm_crtc_internal.h

112

int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,

sys/dev/pci/drm/drm_crtc_internal.h

221

int drm_mode_rmfb(struct drm_device *dev, u32 fb_id,

sys/dev/pci/drm/drm_debugfs.c

257

u32 features = files[i].driver_features;

sys/dev/pci/drm/drm_draw.c

102

unsigned int scale, u32 fg32)

sys/dev/pci/drm/drm_draw.c

109

iosys_map_wr(dmap, y * dpitch + x * sizeof(u32), u32, fg32);

sys/dev/pci/drm/drm_draw.c

130

u32 color)

sys/dev/pci/drm/drm_draw.c

149

u32 color)

sys/dev/pci/drm/drm_draw.c

155

iosys_map_wr(dmap, y * dpitch + x * sizeof(u32), u32, color);

sys/dev/pci/drm/drm_draw.c

27

u32 drm_draw_color_from_xrgb8888(u32 color, u32 format)

sys/dev/pci/drm/drm_draw.c

80

unsigned int scale, u32 fg32)

sys/dev/pci/drm/drm_draw.c

86

u32 off = y * dpitch + x * 3;

sys/dev/pci/drm/drm_draw_internal.h

27

u32 drm_draw_color_from_xrgb8888(u32 color, u32 format);

sys/dev/pci/drm/drm_draw_internal.h

37

unsigned int scale, u32 fg32);

sys/dev/pci/drm/drm_draw_internal.h

42

unsigned int scale, u32 fg32);

sys/dev/pci/drm/drm_draw_internal.h

50

u32 color);

sys/dev/pci/drm/drm_draw_internal.h

54

u32 color);

sys/dev/pci/drm/drm_dumb_buffers.c

136

int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,

sys/dev/pci/drm/drm_dumb_buffers.c

64

u32 cpp, stride, size;

sys/dev/pci/drm/drm_edid.c

131

u32 quirks;

sys/dev/pci/drm/drm_edid.c

2821

u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)

sys/dev/pci/drm/drm_edid.c

2841

return (u32)edid->mfg_id[0] << 24 |

sys/dev/pci/drm/drm_edid.c

2842

(u32)edid->mfg_id[1] << 16 |

sys/dev/pci/drm/drm_edid.c

2843

(u32)EDID_PRODUCT_ID(edid);

sys/dev/pci/drm/drm_edid.c

2985

static u32 edid_get_quirks(const struct drm_edid *drm_edid)

sys/dev/pci/drm/drm_edid.c

3672

static u32

sys/dev/pci/drm/drm_edid.c

3692

u32 max_clock;

sys/dev/pci/drm/drm_edid.c

5441

u32 max_avg, min_cll, max, min, q, r;

sys/dev/pci/drm/drm_edid.c

7462

u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;

sys/dev/pci/drm/drm_exec.c

81

void drm_exec_init(struct drm_exec *exec, u32 flags, unsigned nr)

sys/dev/pci/drm/drm_fb_helper.c

1534

sizes->fb_width = (u32)-1;

sys/dev/pci/drm/drm_fb_helper.c

1535

sizes->fb_height = (u32)-1;

sys/dev/pci/drm/drm_fb_helper.c

1607

max_t(u32, desired_mode->hdisplay + x, sizes->surface_width);

sys/dev/pci/drm/drm_fb_helper.c

1609

max_t(u32, desired_mode->vdisplay + y, sizes->surface_height);

sys/dev/pci/drm/drm_fb_helper.c

1625

sizes->fb_width = min_t(u32, desired_mode->hdisplay + x, sizes->fb_width);

sys/dev/pci/drm/drm_fb_helper.c

1627

sizes->fb_height = min_t(u32, desired_mode->vdisplay + y, sizes->fb_height);

sys/dev/pci/drm/drm_fb_helper.c

398

clip->x1 = min_t(u32, clip->x1, clip_copy.x1);

sys/dev/pci/drm/drm_fb_helper.c

399

clip->y1 = min_t(u32, clip->y1, clip_copy.y1);

sys/dev/pci/drm/drm_fb_helper.c

400

clip->x2 = max_t(u32, clip->x2, clip_copy.x2);

sys/dev/pci/drm/drm_fb_helper.c

401

clip->y2 = max_t(u32, clip->y2, clip_copy.y2);

sys/dev/pci/drm/drm_fb_helper.c

623

static void drm_fb_helper_add_damage_clip(struct drm_fb_helper *helper, u32 x, u32 y,

sys/dev/pci/drm/drm_fb_helper.c

624

u32 width, u32 height)

sys/dev/pci/drm/drm_fb_helper.c

630

clip->x1 = min_t(u32, clip->x1, x);

sys/dev/pci/drm/drm_fb_helper.c

631

clip->y1 = min_t(u32, clip->y1, y);

sys/dev/pci/drm/drm_fb_helper.c

632

clip->x2 = max_t(u32, clip->x2, x + width);

sys/dev/pci/drm/drm_fb_helper.c

633

clip->y2 = max_t(u32, clip->y2, y + height);

sys/dev/pci/drm/drm_fb_helper.c

637

static void drm_fb_helper_damage(struct drm_fb_helper *helper, u32 x, u32 y,

sys/dev/pci/drm/drm_fb_helper.c

638

u32 width, u32 height)

sys/dev/pci/drm/drm_fb_helper.c

664

u32 line_length = info->fix.line_length;

sys/dev/pci/drm/drm_fb_helper.c

665

u32 fb_height = info->var.yres;

sys/dev/pci/drm/drm_fb_helper.c

667

u32 x1 = 0;

sys/dev/pci/drm/drm_fb_helper.c

668

u32 y1 = off / line_length;

sys/dev/pci/drm/drm_fb_helper.c

669

u32 x2 = info->var.xres;

sys/dev/pci/drm/drm_fb_helper.c

670

u32 y2 = DIV_ROUND_UP(end, line_length);

sys/dev/pci/drm/drm_fb_helper.c

707

void drm_fb_helper_damage_area(struct fb_info *info, u32 x, u32 y, u32 width, u32 height)

sys/dev/pci/drm/drm_fb_helper.c

836

u32 *palette = (u32 *)info->pseudo_palette;

sys/dev/pci/drm/drm_fb_helper.c

846

u32 value;

sys/dev/pci/drm/drm_fb_helper.c

855

u32 mask = (1 << info->var.transp.length) - 1;

sys/dev/pci/drm/drm_fbdev_dma.c

298

u32 format;

sys/dev/pci/drm/drm_fbdev_shmem.c

143

u32 format;

sys/dev/pci/drm/drm_fbdev_ttm.c

189

u32 format;

sys/dev/pci/drm/drm_format_helper.c

1350

u32 *src32;

sys/dev/pci/drm/drm_format_helper.c

1438

u32 *src32;

sys/dev/pci/drm/drm_format_helper.c

263

u32 (*xfrm_pixel)(u32))

sys/dev/pci/drm/drm_format_helper.c

272

u32 pix[4] = {

sys/dev/pci/drm/drm_format_helper.c

279

u32 val32 = xfrm_pixel(pix[0]) |

sys/dev/pci/drm/drm_format_helper.c

295

u32 (*xfrm_pixel)(u32))

sys/dev/pci/drm/drm_format_helper.c

306

u32 pix[4] = {

sys/dev/pci/drm/drm_format_helper.c

325

u32 pix[2] = {

sys/dev/pci/drm/drm_format_helper.c

330

u32 val32 = xfrm_pixel(pix[0]) |

sys/dev/pci/drm/drm_format_helper.c

344

u32 (*xfrm_pixel)(u32))

sys/dev/pci/drm/drm_format_helper.c

353

u32 val24[4] = {

sys/dev/pci/drm/drm_format_helper.c

359

u32 out32[3] = {

sys/dev/pci/drm/drm_format_helper.c

384

u32 val24 = xfrm_pixel(le32_to_cpup(sbuf32++));

sys/dev/pci/drm/drm_format_helper.c

394

u32 (*xfrm_pixel)(u32))

sys/dev/pci/drm/drm_format_helper.c

470

u32 *dbuf32 = dbuf;

sys/dev/pci/drm/drm_format_helper.c

471

const u32 *sbuf32 = sbuf;

sys/dev/pci/drm/drm_format_helper.c

472

const u32 *send32 = sbuf32 + pixels;

sys/dev/pci/drm/drm_format_internal.h

106

static inline u32 drm_pixel_xrgb8888_to_argb8888(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

112

static inline u32 drm_pixel_xrgb8888_to_xbgr8888(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

120

static inline u32 drm_pixel_xrgb8888_to_bgrx8888(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

128

static inline u32 drm_pixel_xrgb8888_to_abgr8888(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

134

static inline u32 drm_pixel_xrgb8888_to_xrgb2101010(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

142

static inline u32 drm_pixel_xrgb8888_to_argb2101010(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

148

static inline u32 drm_pixel_xrgb8888_to_xbgr2101010(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

156

static inline u32 drm_pixel_xrgb8888_to_abgr2101010(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

166

static inline u32 drm_pixel_argb8888_to_argb4444(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

39

static inline u32 drm_pixel_xrgb8888_to_r8_bt601(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

41

u32 r = (pix & 0x00ff0000) >> 16;

sys/dev/pci/drm/drm_format_internal.h

42

u32 g = (pix & 0x0000ff00) >> 8;

sys/dev/pci/drm/drm_format_internal.h

43

u32 b = pix & 0x000000ff;

sys/dev/pci/drm/drm_format_internal.h

49

static inline u32 drm_pixel_xrgb8888_to_rgb332(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

56

static inline u32 drm_pixel_xrgb8888_to_rgb565(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

63

static inline u32 drm_pixel_xrgb8888_to_rgb565be(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

68

static inline u32 drm_pixel_xrgb8888_to_rgbx5551(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

75

static inline u32 drm_pixel_xrgb8888_to_rgba5551(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

81

static inline u32 drm_pixel_xrgb8888_to_xrgb1555(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

88

static inline u32 drm_pixel_xrgb8888_to_argb1555(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

94

static inline u32 drm_pixel_xrgb8888_to_rgb888(u32 pix)

sys/dev/pci/drm/drm_format_internal.h

99

static inline u32 drm_pixel_xrgb8888_to_bgr888(u32 pix)

sys/dev/pci/drm/drm_fourcc.c

175

const struct drm_format_info *__drm_format_info(u32 format)

sys/dev/pci/drm/drm_fourcc.c

407

const struct drm_format_info *drm_format_info(u32 format)

sys/dev/pci/drm/drm_fourcc.c

429

u32 pixel_format, u64 modifier)

sys/dev/pci/drm/drm_framebuffer.c

437

int drm_mode_rmfb(struct drm_device *dev, u32 fb_id,

sys/dev/pci/drm/drm_gem.c

1000

if (copy_from_user(handles, bo_handles, count * sizeof(u32))) {

sys/dev/pci/drm/drm_gem.c

1026

drm_gem_object_lookup(struct drm_file *filp, u32 handle)

sys/dev/pci/drm/drm_gem.c

1047

long drm_gem_dma_resv_wait(struct drm_file *filep, u32 handle,

sys/dev/pci/drm/drm_gem.c

1133

u32 handle;

sys/dev/pci/drm/drm_gem.c

543

drm_gem_handle_delete(struct drm_file *filp, u32 handle)

sys/dev/pci/drm/drm_gem.c

581

u32 handle, u64 *offset)

sys/dev/pci/drm/drm_gem.c

625

u32 *handlep)

sys/dev/pci/drm/drm_gem.c

628

u32 handle;

sys/dev/pci/drm/drm_gem.c

697

u32 *handlep)

sys/dev/pci/drm/drm_gem.c

936

static int objects_lookup(struct drm_file *filp, u32 *handle, int count,

sys/dev/pci/drm/drm_gem.c

981

u32 *handles;

sys/dev/pci/drm/drm_gem.c

994

handles = kvmalloc_array(count, sizeof(u32), GFP_KERNEL);

sys/dev/pci/drm/drm_internal.h

200

u32 *handlep);

sys/dev/pci/drm/drm_ioc32.c

129

u32 unique_len; /* Length of unique */

sys/dev/pci/drm/drm_ioc32.c

130

u32 unique; /* Unique name for driver instantiation */

sys/dev/pci/drm/drm_ioc32.c

170

u32 pid; /* Process ID */

sys/dev/pci/drm/drm_ioc32.c

171

u32 uid; /* User ID */

sys/dev/pci/drm/drm_ioc32.c

172

u32 magic; /* Magic */

sys/dev/pci/drm/drm_ioc32.c

173

u32 iocs; /* Ioctl count */

sys/dev/pci/drm/drm_ioc32.c

208

u32 count;

sys/dev/pci/drm/drm_ioc32.c

210

u32 value;

sys/dev/pci/drm/drm_ioc32.c

246

u32 signal;

sys/dev/pci/drm/drm_ioc32.c

291

u32 fb_id;

sys/dev/pci/drm/drm_ioc32.c

292

u32 width;

sys/dev/pci/drm/drm_ioc32.c

293

u32 height;

sys/dev/pci/drm/drm_ioc32.c

294

u32 pixel_format;

sys/dev/pci/drm/drm_ioc32.c

295

u32 flags;

sys/dev/pci/drm/drm_ioc32.c

296

u32 handles[4];

sys/dev/pci/drm/drm_ioc32.c

297

u32 pitches[4];

sys/dev/pci/drm/drm_ioc32.c

298

u32 offsets[4];

sys/dev/pci/drm/drm_ioc32.c

84

u32 name_len; /* Length of name buffer */

sys/dev/pci/drm/drm_ioc32.c

85

u32 name; /* Name of driver */

sys/dev/pci/drm/drm_ioc32.c

86

u32 date_len; /* Length of date buffer */

sys/dev/pci/drm/drm_ioc32.c

87

u32 date; /* User-space buffer to hold date */

sys/dev/pci/drm/drm_ioc32.c

88

u32 desc_len; /* Length of desc buffer */

sys/dev/pci/drm/drm_ioc32.c

89

u32 desc; /* User-space buffer to hold desc */

sys/dev/pci/drm/drm_ioctl.c

607

static int drm_ioctl_permit(u32 flags, struct drm_file *file_priv)

sys/dev/pci/drm/drm_ioctl.c

848

u32 flags)

sys/dev/pci/drm/drm_linux.c

1069

__xa_alloc(struct xarray *xa, u32 *id, void *entry, struct xarray_range xr,

sys/dev/pci/drm/drm_linux.c

1109

__xa_alloc_cyclic(struct xarray *xa, u32 *id, void *entry,

sys/dev/pci/drm/drm_linux.c

1110

struct xarray_range xr, u32 *next, gfp_t gfp)

sys/dev/pci/drm/drm_mipi_dsi.c

168

u32 reg;

sys/dev/pci/drm/drm_mipi_dsi.c

898

u32 drm_mipi_dsi_get_input_bus_fmt(enum mipi_dsi_pixel_format dsi_format)

sys/dev/pci/drm/drm_mode_config.c

587

static u32 full_encoder_mask(struct drm_device *dev)

sys/dev/pci/drm/drm_mode_config.c

590

u32 encoder_mask = 0;

sys/dev/pci/drm/drm_mode_config.c

612

u32 encoder_mask = full_encoder_mask(dev);

sys/dev/pci/drm/drm_mode_config.c

635

static u32 full_crtc_mask(struct drm_device *dev)

sys/dev/pci/drm/drm_mode_config.c

638

u32 crtc_mask = 0;

sys/dev/pci/drm/drm_mode_config.c

648

u32 crtc_mask = full_crtc_mask(encoder->dev);

sys/dev/pci/drm/drm_mode_config.c

663

u32 primary_with_crtc = 0, cursor_with_crtc = 0;

sys/dev/pci/drm/drm_modes.c

1156

void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags)

sys/dev/pci/drm/drm_modes.c

1192

struct drm_display_mode *dmode, u32 *bus_flags,

sys/dev/pci/drm/drm_modes.c

1226

struct drm_display_mode *dmode, u32 *bus_flags)

sys/dev/pci/drm/drm_modes.c

1228

u32 width_mm = 0, height_mm = 0;

sys/dev/pci/drm/drm_panic.c

149

u32 fg_color)

sys/dev/pci/drm/drm_panic.c

166

static void drm_panic_write_pixel24(void *vaddr, unsigned int offset, u32 color)

sys/dev/pci/drm/drm_panic.c

181

unsigned int offset, u32 color)

sys/dev/pci/drm/drm_panic.c

204

static void drm_panic_write_pixel32(void *vaddr, unsigned int offset, u32 color)

sys/dev/pci/drm/drm_panic.c

206

u32 *p = vaddr + offset;

sys/dev/pci/drm/drm_panic.c

211

static void drm_panic_write_pixel(void *vaddr, unsigned int offset, u32 color, unsigned int cpp)

sys/dev/pci/drm/drm_panic.c

236

unsigned int scale, u32 fg32)

sys/dev/pci/drm/drm_panic.c

292

unsigned int scale, u32 fg_color)

sys/dev/pci/drm/drm_panic.c

327

u32 color)

sys/dev/pci/drm/drm_panic.c

338

u32 color)

sys/dev/pci/drm/drm_panic.c

382

u32 color)

sys/dev/pci/drm/drm_panic.c

433

u32 color)

sys/dev/pci/drm/drm_panic.c

472

const struct font_desc *font, u32 fg_color)

sys/dev/pci/drm/drm_panic.c

487

u32 fg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_FOREGROUND_COLOR,

sys/dev/pci/drm/drm_panic.c

489

u32 bg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_BACKGROUND_COLOR,

sys/dev/pci/drm/drm_panic.c

522

struct drm_panic_line *line, int yoffset, u32 fg_color)

sys/dev/pci/drm/drm_panic.c

556

u32 fg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_FOREGROUND_COLOR,

sys/dev/pci/drm/drm_panic.c

558

u32 bg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_BACKGROUND_COLOR,

sys/dev/pci/drm/drm_panic.c

744

u32 fg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_FOREGROUND_COLOR,

sys/dev/pci/drm/drm_panic.c

746

u32 bg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_BACKGROUND_COLOR,

sys/dev/pci/drm/drm_panic.c

80

u32 len;

sys/dev/pci/drm/drm_panic.c

852

u32 len;

sys/dev/pci/drm/drm_plane.c

1389

u32 target_vblank = page_flip->sequence;

sys/dev/pci/drm/drm_plane.c

1421

u32 current_vblank;

sys/dev/pci/drm/drm_plane.c

1428

current_vblank = (u32)drm_crtc_vblank_count(crtc);

sys/dev/pci/drm/drm_plane.c

185

static inline u32 *

sys/dev/pci/drm/drm_plane.c

188

return (u32 *)(((char *)blob) + blob->formats_offset);

sys/dev/pci/drm/drm_plane.c

201

u32 format,

sys/dev/pci/drm/drm_plane.c

917

u32 format, u64 modifier)

sys/dev/pci/drm/drm_plane.c

997

u32 format, u64 modifier)

sys/dev/pci/drm/drm_privacy_screen_x86.c

21

static acpi_status __init acpi_set_handle(acpi_handle handle, u32 level,

sys/dev/pci/drm/drm_property.c

163

u32 flags, const char *name,

sys/dev/pci/drm/drm_property.c

211

u32 flags, const char *name,

sys/dev/pci/drm/drm_property.c

243

u32 flags, const char *name,

sys/dev/pci/drm/drm_property.c

278

u32 flags, const char *name,

sys/dev/pci/drm/drm_property.c

306

u32 flags, const char *name,

sys/dev/pci/drm/drm_property.c

333

u32 flags, const char *name,

sys/dev/pci/drm/drm_property.c

370

u32 flags, const char *name)

sys/dev/pci/drm/drm_property.c

59

static bool drm_property_flags_valid(u32 flags)

sys/dev/pci/drm/drm_property.c

61

u32 legacy_type = flags & DRM_MODE_PROP_LEGACY_TYPE;

sys/dev/pci/drm/drm_property.c

62

u32 ext_type = flags & DRM_MODE_PROP_EXTENDED_TYPE;

sys/dev/pci/drm/drm_property.c

98

u32 flags, const char *name,

sys/dev/pci/drm/drm_rect.c

106

u32 new_src_h = clip_scaled(drm_rect_height(src),

sys/dev/pci/drm/drm_rect.c

114

u32 new_src_w = clip_scaled(drm_rect_width(src),

sys/dev/pci/drm/drm_rect.c

122

u32 new_src_h = clip_scaled(drm_rect_height(src),

sys/dev/pci/drm/drm_rect.c

55

static u32 clip_scaled(int src, int dst, int *clip)

sys/dev/pci/drm/drm_rect.c

98

u32 new_src_w = clip_scaled(drm_rect_width(src),

sys/dev/pci/drm/drm_suballoc.c

412

u32 idx;

sys/dev/pci/drm/drm_syncobj.c

237

u32 flags;

sys/dev/pci/drm/drm_syncobj.c

253

u32 handle)

sys/dev/pci/drm/drm_syncobj.c

443

u32 handle, u64 point, u64 flags,

sys/dev/pci/drm/drm_syncobj.c

609

struct drm_syncobj *syncobj, u32 *handle)

sys/dev/pci/drm/drm_syncobj.c

634

u32 *handle, uint32_t flags)

sys/dev/pci/drm/drm_syncobj.c

649

u32 handle)

sys/dev/pci/drm/drm_syncobj.c

717

u32 handle, int *p_fd)

sys/dev/pci/drm/drm_syncobj.c

731

int fd, u32 *handle)

sys/dev/pci/drm/drm_vblank.c

1485

u32 max_vblank_count)

sys/dev/pci/drm/drm_vblank.c

1573

u32 cur_vblank, diff = 1;

sys/dev/pci/drm/drm_vblank.c

1575

u32 max_vblank_count = drm_max_vblank_count(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1735

static u64 widen_32_to_64(u32 narrow, u64 near)

sys/dev/pci/drm/drm_vblank.c

1753

reply->tval_sec = (u32)ts.tv_sec;

sys/dev/pci/drm/drm_vblank.c

192

u32 vblank_count_inc,

sys/dev/pci/drm/drm_vblank.c

193

ktime_t t_vblank, u32 last)

sys/dev/pci/drm/drm_vblank.c

207

static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

2100

u32 flags;

sys/dev/pci/drm/drm_vblank.c

218

static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

224

static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

250

u32 cur_vblank;

sys/dev/pci/drm/drm_vblank.c

299

u32 cur_vblank, diff;

sys/dev/pci/drm/drm_vblank.c

304

u32 max_vblank_count = drm_max_vblank_count(dev, pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

1038

u32 signal_levels;

sys/dev/pci/drm/i915/display/g4x_dp.c

1053

static u32 snb_cpu_edp_signal_levels(u8 train_set)

sys/dev/pci/drm/i915/display/g4x_dp.c

1086

u32 signal_levels;

sys/dev/pci/drm/i915/display/g4x_dp.c

1101

static u32 ivb_cpu_edp_signal_levels(u8 train_set)

sys/dev/pci/drm/i915/display/g4x_dp.c

1138

u32 signal_levels;

sys/dev/pci/drm/i915/display/g4x_dp.c

1191

u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/g4x_dp.c

1199

u32 bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

1222

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/g4x_dp.c

259

u32 val = intel_de_read(display, TRANS_DP_CTL(p));

sys/dev/pci/drm/i915/display/g4x_dp.c

281

u32 val;

sys/dev/pci/drm/i915/display/g4x_dp.c

341

u32 tmp, flags = 0;

sys/dev/pci/drm/i915/display/g4x_dp.c

355

u32 trans_dp = intel_de_read(display,

sys/dev/pci/drm/i915/display/g4x_dp.c

686

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

915

u32 deemph_reg_value, margin_reg_value;

sys/dev/pci/drm/i915/display/g4x_dp.c

994

static u32 g4x_signal_levels(u8 train_set)

sys/dev/pci/drm/i915/display/g4x_dp.c

996

u32 signal_levels = 0;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

155

u32 tmp, flags = 0;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

222

u32 temp;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

281

u32 temp;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

329

u32 temp;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

35

u32 hdmi_val;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

385

u32 temp;

sys/dev/pci/drm/i915/display/hsw_ips.c

22

u32 val;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1170

u32 val, base, offset;

sys/dev/pci/drm/i915/display/i9xx_plane.c

158

static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/i9xx_plane.c

163

u32 dspcntr;

sys/dev/pci/drm/i915/display/i9xx_plane.c

235

u32 offset;

sys/dev/pci/drm/i915/display/i9xx_plane.c

30

static const u32 i8xx_primary_formats[] = {

sys/dev/pci/drm/i915/display/i9xx_plane.c

362

static u32 i8xx_plane_surf_offset(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/i9xx_plane.c

370

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/i9xx_plane.c

375

static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/i9xx_plane.c

379

u32 dspcntr = 0;

sys/dev/pci/drm/i915/display/i9xx_plane.c

38

static const u32 ivb_primary_formats[] = {

sys/dev/pci/drm/i915/display/i9xx_plane.c

478

u32 dspcntr;

sys/dev/pci/drm/i915/display/i9xx_plane.c

48

static const u32 i965_primary_formats[] = {

sys/dev/pci/drm/i915/display/i9xx_plane.c

545

u32 dspcntr;

sys/dev/pci/drm/i915/display/i9xx_plane.c

59

static const u32 vlv_primary_formats[] = {

sys/dev/pci/drm/i915/display/i9xx_plane.c

609

u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

729

u32 val;

sys/dev/pci/drm/i915/display/i9xx_plane.c

74

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/i9xx_plane.c

757

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

769

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

784

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

799

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

810

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

911

u32 dspcntr;

sys/dev/pci/drm/i915/display/i9xx_plane.c

912

u32 reg;

sys/dev/pci/drm/i915/display/i9xx_plane.c

92

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/i9xx_plane.c

935

const u32 *formats;

sys/dev/pci/drm/i915/display/i9xx_plane.h

21

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.h

27

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state);

sys/dev/pci/drm/i915/display/i9xx_plane.h

38

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1058

static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1060

u32 pri_val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

117

u32 val;

sys/dev/pci/drm/i915/display/i9xx_wm.c

143

u32 val;

sys/dev/pci/drm/i915/display/i9xx_wm.c

163

u32 val;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1872

u32 dsparb, dsparb2, dsparb3;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2228

u32 fwater_lo;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2229

u32 fwater_hi;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2371

u32 fwater_lo;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2420

static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2447

static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2449

u32 mem_value, bool is_lp)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2451

u32 method1, method2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2479

static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2481

u32 mem_value)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2483

u32 method1, method2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2506

static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2508

u32 mem_value)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2527

static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2529

u32 pri_val)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2700

result->pri_val = min_t(u32, result->pri_val, max->pri);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2701

result->spr_val = min_t(u32, result->spr_val, max->spr);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2702

result->cur_val = min_t(u32, result->cur_val, max->cur);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2765

u32 sskpd;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2780

u32 mltr;

sys/dev/pci/drm/i915/display/i9xx_wm.c

290

u32 dsparb, dsparb2, dsparb3;

sys/dev/pci/drm/i915/display/i9xx_wm.c

325

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

341

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3511

u32 tmp = hw->wm_pipe[pipe];

sys/dev/pci/drm/i915/display/i9xx_wm.c

358

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3668

u32 tmp;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3695

u32 tmp;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3913

u32 val;

sys/dev/pci/drm/i915/display/i9xx_wm.c

657

u32 reg;

sys/dev/pci/drm/i915/display/icl_dsi.c

1065

u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;

sys/dev/pci/drm/i915/display/icl_dsi.c

1110

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

1171

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

1343

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

1545

u32 val;

sys/dev/pci/drm/i915/display/icl_dsi.c

166

u32 len = packet->payload_length;

sys/dev/pci/drm/i915/display/icl_dsi.c

1731

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

176

u32 tmp = 0;

sys/dev/pci/drm/i915/display/icl_dsi.c

181

for (j = 0; j < min_t(u32, len - i, 4); j++)

sys/dev/pci/drm/i915/display/icl_dsi.c

1864

u32 tlpx_ns;

sys/dev/pci/drm/i915/display/icl_dsi.c

1865

u32 tclk_prepare_esc_clk, tclk_zero_esc_clk, tclk_pre_esc_clk;

sys/dev/pci/drm/i915/display/icl_dsi.c

1866

u32 ths_prepare_esc_clk, ths_zero_esc_clk, ths_exit_esc_clk;

sys/dev/pci/drm/i915/display/icl_dsi.c

197

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

229

u32 mode_flags;

sys/dev/pci/drm/i915/display/icl_dsi.c

255

u32 tmp, mask, val;

sys/dev/pci/drm/i915/display/icl_dsi.c

301

u32 dss_ctl1;

sys/dev/pci/drm/i915/display/icl_dsi.c

367

u32 esc_clk_div_m, esc_clk_div_m_phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

445

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

487

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

626

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

642

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

660

u32 tmp;

sys/dev/pci/drm/i915/display/icl_dsi.c

679

u32 val;

sys/dev/pci/drm/i915/display/icl_dsi.c

708

u32 tmp;

sys/dev/pci/drm/i915/display/intel_alpm.c

322

u32 alpm_ctl;

sys/dev/pci/drm/i915/display/intel_alpm.c

340

u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;

sys/dev/pci/drm/i915/display/intel_alpm.c

381

u32 alpm_ctl_val = 0, lfps_ctl_val = 0;

sys/dev/pci/drm/i915/display/intel_alpm.c

498

u32 alpm_ctl;

sys/dev/pci/drm/i915/display/intel_audio.c

1340

u32 aud_freq, aud_freq_init;

sys/dev/pci/drm/i915/display/intel_audio.c

199

static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_audio.c

258

u32 tmp;

sys/dev/pci/drm/i915/display/intel_audio.c

269

u32 *eld = (u32 *)crtc_state->eld;

sys/dev/pci/drm/i915/display/intel_audio.c

271

u32 tmp;

sys/dev/pci/drm/i915/display/intel_audio.c

307

const u32 *eld = (const u32 *)crtc_state->eld;

sys/dev/pci/drm/i915/display/intel_audio.c

357

u32 tmp;

sys/dev/pci/drm/i915/display/intel_audio.c

89

u32 config;

sys/dev/pci/drm/i915/display/intel_backlight.c

1044

static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1055

static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1065

static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1068

u32 mul;

sys/dev/pci/drm/i915/display/intel_backlight.c

108

void intel_backlight_set_pwm_level(const struct drm_connector_state *conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

1083

static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1087

u32 mul, clock;

sys/dev/pci/drm/i915/display/intel_backlight.c

1106

static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1122

static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1140

static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

1158

static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/pci/drm/i915/display/intel_backlight.c

119

u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

1196

static u32 get_backlight_max_vbt(struct intel_connector *connector)

sys/dev/pci/drm/i915/display/intel_backlight.c

1201

u32 pwm;

sys/dev/pci/drm/i915/display/intel_backlight.c

1222

static u32 get_backlight_min_vbt(struct intel_connector *connector)

sys/dev/pci/drm/i915/display/intel_backlight.c

1252

u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;

sys/dev/pci/drm/i915/display/intel_backlight.c

1309

u32 cpu_ctl2, pch_ctl1, pch_ctl2;

sys/dev/pci/drm/i915/display/intel_backlight.c

133

u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

1340

u32 ctl, val;

sys/dev/pci/drm/i915/display/intel_backlight.c

1382

u32 ctl, ctl2;

sys/dev/pci/drm/i915/display/intel_backlight.c

1415

u32 ctl, ctl2;

sys/dev/pci/drm/i915/display/intel_backlight.c

1448

u32 pwm_ctl, val;

sys/dev/pci/drm/i915/display/intel_backlight.c

150

static u32 lpt_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1516

u32 pwm_ctl;

sys/dev/pci/drm/i915/display/intel_backlight.c

1562

u32 level;

sys/dev/pci/drm/i915/display/intel_backlight.c

157

static u32 pch_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1617

static void intel_pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

1626

static u32 intel_pwm_get_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

1635

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

164

static u32 i9xx_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1644

static void intel_pwm_disable_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

168

u32 val;

sys/dev/pci/drm/i915/display/intel_backlight.c

185

static u32 vlv_get_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

195

static u32 bxt_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

203

static u32 ext_pwm_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

216

static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

220

u32 val;

sys/dev/pci/drm/i915/display/intel_backlight.c

226

static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

230

u32 tmp;

sys/dev/pci/drm/i915/display/intel_backlight.c

236

static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

241

u32 tmp, mask;

sys/dev/pci/drm/i915/display/intel_backlight.c

266

static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

271

u32 tmp;

sys/dev/pci/drm/i915/display/intel_backlight.c

277

static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

286

static void ext_pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

298

intel_panel_actually_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

314

u32 user_level, u32 user_max)

sys/dev/pci/drm/i915/display/intel_backlight.c

319

u32 hw_level;

sys/dev/pci/drm/i915/display/intel_backlight.c

349

static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

353

u32 tmp;

sys/dev/pci/drm/i915/display/intel_backlight.c

375

static void pch_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

387

static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

392

static void i965_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

402

static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

413

static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

42

static u32 scale(u32 source_val,

sys/dev/pci/drm/i915/display/intel_backlight.c

428

static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

43

u32 source_min, u32 source_max,

sys/dev/pci/drm/i915/display/intel_backlight.c

44

u32 target_min, u32 target_max)

sys/dev/pci/drm/i915/display/intel_backlight.c

440

static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

486

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

491

u32 pch_ctl1, pch_ctl2;

sys/dev/pci/drm/i915/display/intel_backlight.c

531

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

537

u32 cpu_ctl2, pch_ctl1, pch_ctl2;

sys/dev/pci/drm/i915/display/intel_backlight.c

581

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

586

u32 ctl, freq;

sys/dev/pci/drm/i915/display/intel_backlight.c

622

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

628

u32 ctl, ctl2, freq;

sys/dev/pci/drm/i915/display/intel_backlight.c

659

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

665

u32 ctl, ctl2;

sys/dev/pci/drm/i915/display/intel_backlight.c

68

static u32 clamp_user_to_hw(struct intel_connector *connector,

sys/dev/pci/drm/i915/display/intel_backlight.c

69

u32 user_level, u32 user_max)

sys/dev/pci/drm/i915/display/intel_backlight.c

691

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

697

u32 pwm_ctl, val;

sys/dev/pci/drm/i915/display/intel_backlight.c

72

u32 hw_level;

sys/dev/pci/drm/i915/display/intel_backlight.c

743

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

748

u32 pwm_ctl;

sys/dev/pci/drm/i915/display/intel_backlight.c

774

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_backlight.c

81

static u32 scale_hw_to_user(struct intel_connector *connector,

sys/dev/pci/drm/i915/display/intel_backlight.c

82

u32 hw_level, u32 user_max)

sys/dev/pci/drm/i915/display/intel_backlight.c

831

static u32 intel_panel_get_backlight(struct intel_connector *connector)

sys/dev/pci/drm/i915/display/intel_backlight.c

835

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_backlight.c

849

static u32 scale_user_to_hw(struct intel_connector *connector,

sys/dev/pci/drm/i915/display/intel_backlight.c

850

u32 user_level, u32 user_max)

sys/dev/pci/drm/i915/display/intel_backlight.c

860

u32 user_level, u32 user_max)

sys/dev/pci/drm/i915/display/intel_backlight.c

865

u32 hw_level;

sys/dev/pci/drm/i915/display/intel_backlight.c

90

u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 val)

sys/dev/pci/drm/i915/display/intel_backlight.c

924

u32 hw_level;

sys/dev/pci/drm/i915/display/intel_backlight.h

32

u32 level, u32 max);

sys/dev/pci/drm/i915/display/intel_backlight.h

34

u32 level);

sys/dev/pci/drm/i915/display/intel_backlight.h

35

u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 level);

sys/dev/pci/drm/i915/display/intel_backlight.h

36

u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32 level);

sys/dev/pci/drm/i915/display/intel_backlight.h

37

u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val);

sys/dev/pci/drm/i915/display/intel_bios.c

105

u32 total, current_size;

sys/dev/pci/drm/i915/display/intel_bios.c

134

static u32 raw_block_offset(const void *bdb, enum bdb_block_id section_id)

sys/dev/pci/drm/i915/display/intel_bios.c

1623

u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;

sys/dev/pci/drm/i915/display/intel_bios.c

1771

u16 panel_id, u32 *seq_size)

sys/dev/pci/drm/i915/display/intel_bios.c

1773

u32 total = get_blocksize(sequence);

sys/dev/pci/drm/i915/display/intel_bios.c

1776

u32 current_size;

sys/dev/pci/drm/i915/display/intel_bios.c

1794

current_size = *((const u32 *)(data + index + 1));

sys/dev/pci/drm/i915/display/intel_bios.c

1863

u32 size_of_sequence;

sys/dev/pci/drm/i915/display/intel_bios.c

1882

size_of_sequence = *((const u32 *)(data + index));

sys/dev/pci/drm/i915/display/intel_bios.c

2052

u32 seq_size;

sys/dev/pci/drm/i915/display/intel_bios.c

2481

static u32 edp_rate_override_mask(int rate)

sys/dev/pci/drm/i915/display/intel_bios.c

3106

BUILD_BUG_ON(vbt_signature_len != sizeof(u32));

sys/dev/pci/drm/i915/display/intel_bios.c

3108

offset = intel_rom_find(rom, *(const u32 *)vbt_signature);

sys/dev/pci/drm/i915/display/intel_bios.c

321

u32 offset;

sys/dev/pci/drm/i915/display/intel_bios.c

84

static u32 _get_blocksize(const u8 *block_base)

sys/dev/pci/drm/i915/display/intel_bios.c

88

return *((const u32 *)(block_base + 4));

sys/dev/pci/drm/i915/display/intel_bios.c

94

static u32 get_blocksize(const void *block_data)

sys/dev/pci/drm/i915/display/intel_bw.c

121

u32 val = 0, val2 = 0;

sys/dev/pci/drm/i915/display/intel_bw.c

148

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_bw.c

192

u32 points_mask)

sys/dev/pci/drm/i915/display/intel_bw.c

223

u32 val, val2;

sys/dev/pci/drm/i915/display/intel_bw.c

86

u32 dclk_ratio, dclk_reference;

sys/dev/pci/drm/i915/display/intel_bw.c

87

u32 val;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1016

u32 cdctl;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1090

static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1142

static u32 skl_cdclk_freq_sel(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1171

u32 freq_select, cdclk_ctl;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1239

u32 cdctl, expected;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1320

u32 cdclk;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1682

u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1703

u32 val, ratio;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1738

u32 squash_ctl = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1739

u32 divider;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1847

u32 val;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1865

u32 val;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1886

static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1906

static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1970

u32 squash_ctl = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1994

static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2101

static u32 bxt_cdclk_ctl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2108

u32 val;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2253

u32 cdctl, expected;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2519

u32 update_mask = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3447

u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3537

u32 rawclk;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3590

u32 intel_read_rawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3592

u32 freq;

sys/dev/pci/drm/i915/display/intel_cdclk.c

549

u32 lcpll = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

550

u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

609

u32 val;

sys/dev/pci/drm/i915/display/intel_cdclk.c

675

u32 val, cmd = cdclk_config->voltage_level;

sys/dev/pci/drm/i915/display/intel_cdclk.c

716

u32 divider;

sys/dev/pci/drm/i915/display/intel_cdclk.c

765

u32 val, cmd = cdclk_config->voltage_level;

sys/dev/pci/drm/i915/display/intel_cdclk.c

839

u32 lcpll = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

840

u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

863

static u32 bdw_cdclk_freq_sel(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

975

u32 val;

sys/dev/pci/drm/i915/display/intel_cdclk.h

30

u32 intel_read_rawclk(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cmtg.c

105

u32 val;

sys/dev/pci/drm/i915/display/intel_cmtg.c

131

u32 clk_sel_clr = 0;

sys/dev/pci/drm/i915/display/intel_cmtg.c

132

u32 clk_sel_set = 0;

sys/dev/pci/drm/i915/display/intel_cmtg.c

89

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_color.c

1048

static u32 hsw_read_gamma_mode(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_color.c

1055

static u32 ilk_read_csc_mode(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_color.c

1068

u32 tmp;

sys/dev/pci/drm/i915/display/intel_color.c

1093

u32 tmp;

sys/dev/pci/drm/i915/display/intel_color.c

1113

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_color.c

1338

i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

1349

i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

1430

static int ivb_lut_10_size(u32 prec_index)

sys/dev/pci/drm/i915/display/intel_color.c

1445

u32 prec_index)

sys/dev/pci/drm/i915/display/intel_color.c

1470

u32 prec_index)

sys/dev/pci/drm/i915/display/intel_color.c

1581

static u32 glk_degamma_lut(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

1586

static void glk_degamma_lut_pack(struct drm_color_lut *entry, u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

1592

static u32 mtl_degamma_lut(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

1597

static void mtl_degamma_lut_pack(struct drm_color_lut *entry, u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

1826

static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

1832

static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

1837

static void chv_cgm_degamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_color.c

1860

static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

1866

static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

1871

static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_color.c

198

u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;

sys/dev/pci/drm/i915/display/intel_color.c

199

u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,

sys/dev/pci/drm/i915/display/intel_color.c

2191

static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2202

static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2220

static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2248

u32 degamma_tests, u32 gamma_tests)

sys/dev/pci/drm/i915/display/intel_color.c

2285

static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2431

static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2433

u32 cgm_mode = 0;

sys/dev/pci/drm/i915/display/intel_color.c

2517

static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2526

static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

259

u32 tmp;

sys/dev/pci/drm/i915/display/intel_color.c

2632

static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2640

static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2746

static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2816

u32 degamma_tests = intel_degamma_lut_tests(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2817

u32 gamma_tests = intel_gamma_lut_tests(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2884

static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2887

u32 gamma_mode = 0;

sys/dev/pci/drm/i915/display/intel_color.c

2912

static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_color.c

2914

u32 csc_mode = 0;

sys/dev/pci/drm/i915/display/intel_color.c

2987

static int ilk_gamma_mode_precision(u32 gamma_mode)

sys/dev/pci/drm/i915/display/intel_color.c

3121

const struct drm_color_lut *lut2, u32 err)

sys/dev/pci/drm/i915/display/intel_color.c

3130

int lut_size, u32 err)

sys/dev/pci/drm/i915/display/intel_color.c

3148

u32 err;

sys/dev/pci/drm/i915/display/intel_color.c

3300

u32 val = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3312

u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3316

u32 ldw, udw;

sys/dev/pci/drm/i915/display/intel_color.c

3377

u32 ldw = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3379

u32 udw = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3429

u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));

sys/dev/pci/drm/i915/display/intel_color.c

3430

u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));

sys/dev/pci/drm/i915/display/intel_color.c

3455

u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));

sys/dev/pci/drm/i915/display/intel_color.c

3456

u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));

sys/dev/pci/drm/i915/display/intel_color.c

3504

u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

3529

u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

3575

u32 prec_index)

sys/dev/pci/drm/i915/display/intel_color.c

3592

u32 val;

sys/dev/pci/drm/i915/display/intel_color.c

362

u32 tmp;

sys/dev/pci/drm/i915/display/intel_color.c

3640

u32 prec_index)

sys/dev/pci/drm/i915/display/intel_color.c

3663

u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3733

u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3794

u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3795

u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

663

u32 tmp;

sys/dev/pci/drm/i915/display/intel_color.c

761

u32 tmp;

sys/dev/pci/drm/i915/display/intel_color.c

809

static u32 intel_color_lut_pack(u32 val, int bit_precision)

sys/dev/pci/drm/i915/display/intel_color.c

819

static u32 i9xx_lut_8(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

826

static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

834

static u32 _i9xx_lut_10_ldw(u16 a)

sys/dev/pci/drm/i915/display/intel_color.c

839

static u32 i9xx_lut_10_ldw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

847

static u32 _i9xx_lut_10_udw(u16 a, u16 b)

sys/dev/pci/drm/i915/display/intel_color.c

867

static u32 i9xx_lut_10_udw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

875

u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_color.c

890

u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_color.c

907

static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

915

static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

922

static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_color.c

932

static u16 i965_lut_11p6_max_pack(u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

938

static u32 ilk_lut_10(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

945

static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)

sys/dev/pci/drm/i915/display/intel_color.c

953

static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

961

static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)

sys/dev/pci/drm/i915/display/intel_color.c

968

static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

222

u32 expected_val = 0;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

315

u32 val;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

33

u32 dw1, dw9, dw10;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

60

u32 val;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

95

enum phy phy, i915_reg_t reg, u32 mask,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

96

u32 expected_val)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

98

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_connector.c

339

u32 scaling_modes;

sys/dev/pci/drm/i915/display/intel_crt.c

1012

u32 adpa;

sys/dev/pci/drm/i915/display/intel_crt.c

1127

u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |

sys/dev/pci/drm/i915/display/intel_crt.c

131

u32 tmp, flags = 0;

sys/dev/pci/drm/i915/display/intel_crt.c

182

u32 adpa;

sys/dev/pci/drm/i915/display/intel_crt.c

481

u32 adpa;

sys/dev/pci/drm/i915/display/intel_crt.c

487

u32 save_adpa;

sys/dev/pci/drm/i915/display/intel_crt.c

530

u32 adpa;

sys/dev/pci/drm/i915/display/intel_crt.c

532

u32 save_adpa;

sys/dev/pci/drm/i915/display/intel_crt.c

581

u32 stat;

sys/dev/pci/drm/i915/display/intel_crt.c

699

u32 save_bclrpat;

sys/dev/pci/drm/i915/display/intel_crt.c

700

u32 save_vtotal;

sys/dev/pci/drm/i915/display/intel_crt.c

701

u32 vtotal, vactive;

sys/dev/pci/drm/i915/display/intel_crt.c

702

u32 vsample;

sys/dev/pci/drm/i915/display/intel_crt.c

703

u32 vblank, vblank_start, vblank_end;

sys/dev/pci/drm/i915/display/intel_crt.c

704

u32 dsl;

sys/dev/pci/drm/i915/display/intel_crt.c

727

u32 transconf = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

755

u32 vsync = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

757

u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;

sys/dev/pci/drm/i915/display/intel_crt.c

94

u32 val;

sys/dev/pci/drm/i915/display/intel_crt.c

968

u32 adpa;

sys/dev/pci/drm/i915/display/intel_crtc.c

663

u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);

sys/dev/pci/drm/i915/display/intel_crtc.c

80

u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_crtc.c

88

return (u32)drm_crtc_accurate_vblank_count(&crtc->base);

sys/dev/pci/drm/i915/display/intel_crtc.c

93

u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_crtc.h

40

u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state);

sys/dev/pci/drm/i915/display/intel_crtc.h

47

u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);

sys/dev/pci/drm/i915/display/intel_cursor.c

185

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_cursor.c

198

static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_cursor.c

200

u32 cntl = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

208

static u32 i845_cursor_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/intel_cursor.c

280

u32 cntl = 0, base = 0, pos = 0, size = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

32

static const u32 intel_cursor_formats[] = {

sys/dev/pci/drm/i915/display/intel_cursor.c

346

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_cursor.c

36

static u32 intel_cursor_surf_offset(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/intel_cursor.c

379

static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_cursor.c

383

u32 cntl = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

400

static u32 i9xx_cursor_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/intel_cursor.c

403

u32 cntl = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

41

static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_cursor.c

47

u32 pos = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

551

u32 ctl = plane_state->ctl;

sys/dev/pci/drm/i915/display/intel_cursor.c

577

u32 val = intel_cursor_position(crtc_state, plane_state,

sys/dev/pci/drm/i915/display/intel_cursor.c

593

static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)

sys/dev/pci/drm/i915/display/intel_cursor.c

602

static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)

sys/dev/pci/drm/i915/display/intel_cursor.c

604

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

656

u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;

sys/dev/pci/drm/i915/display/intel_cursor.c

732

u32 val;

sys/dev/pci/drm/i915/display/intel_cursor.c

780

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_cursor.c

805

u32 src_x, u32 src_y,

sys/dev/pci/drm/i915/display/intel_cursor.c

806

u32 src_w, u32 src_h,

sys/dev/pci/drm/i915/display/intel_cursor.c

90

u32 offset;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

163

int command, int lane, u32 *val)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

217

u32 val;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2534

static u8 intel_c20_get_dp_rate(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2569

static u8 intel_c20_get_hdmi_rate(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2589

static bool is_dp2(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2598

static bool is_hdmi_frl(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2621

static int intel_get_c20_custom_width(u32 clock, bool dp)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2768

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2797

static u32 intel_cx0_get_powerdown_update(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2799

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2808

static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2810

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2871

static u32 intel_cx0_get_pclk_refclk_request(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2873

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2882

static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2884

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

289

u32 val;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2901

u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2904

u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2997

static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2999

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3008

static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3010

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3112

u32 clock, val;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3176

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3177

u32 mask;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3410

u32 val, clock;

sys/dev/pci/drm/i915/display/intel_ddi.c

1043

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

1062

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

1078

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

1154

static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_ddi.c

1173

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

1236

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

135

u32 iboost_bit = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

1442

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

1531

u32 signal_levels;

sys/dev/pci/drm/i915/display/intel_ddi.c

1553

u32 clk_sel_mask, u32 clk_sel, u32 clk_off)

sys/dev/pci/drm/i915/display/intel_ddi.c

1569

u32 clk_off)

sys/dev/pci/drm/i915/display/intel_ddi.c

1579

u32 clk_off)

sys/dev/pci/drm/i915/display/intel_ddi.c

1586

u32 clk_sel_mask, u32 clk_sel_shift)

sys/dev/pci/drm/i915/display/intel_ddi.c

167

u32 iboost_bit = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

1731

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

1826

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

1879

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

1897

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

1995

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

2046

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

2095

u32 port_mask;

sys/dev/pci/drm/i915/display/intel_ddi.c

2157

enum tc_port tc_port, u32 ln0, u32 ln1)

sys/dev/pci/drm/i915/display/intel_ddi.c

2172

u32 ln0, ln1;

sys/dev/pci/drm/i915/display/intel_ddi.c

243

static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_ddi.c

2494

u32 dss1;

sys/dev/pci/drm/i915/display/intel_ddi.c

2531

u32 dss1 = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

2556

u32 set_bits, wait_bits;

sys/dev/pci/drm/i915/display/intel_ddi.c

2589

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

2610

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

264

static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_ddi.c

303

static u32 ddi_buf_phy_link_rate(int port_clock)

sys/dev/pci/drm/i915/display/intel_ddi.c

3058

u32 clr_bits, wait_bits;

sys/dev/pci/drm/i915/display/intel_ddi.c

3084

static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl)

sys/dev/pci/drm/i915/display/intel_ddi.c

3414

u32 buf_ctl = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

3440

u32 val;

sys/dev/pci/drm/i915/display/intel_ddi.c

3485

u32 port_buf = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

3729

u32 dp_tp_ctl;

sys/dev/pci/drm/i915/display/intel_ddi.c

3787

u32 dp_tp_ctl;

sys/dev/pci/drm/i915/display/intel_ddi.c

3819

u32 temp;

sys/dev/pci/drm/i915/display/intel_ddi.c

388

u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

sys/dev/pci/drm/i915/display/intel_ddi.c

3926

u32 master_select;

sys/dev/pci/drm/i915/display/intel_ddi.c

3929

u32 ctl2 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3937

u32 ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3955

u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

sys/dev/pci/drm/i915/display/intel_ddi.c

3987

u32 ddi_func_ctl)

sys/dev/pci/drm/i915/display/intel_ddi.c

4001

u32 ddi_func_ctl)

sys/dev/pci/drm/i915/display/intel_ddi.c

4021

u32 ddi_func_ctl)

sys/dev/pci/drm/i915/display/intel_ddi.c

4033

u32 ddi_func_ctl)

sys/dev/pci/drm/i915/display/intel_ddi.c

4074

u32 ddi_func_ctl)

sys/dev/pci/drm/i915/display/intel_ddi.c

4104

u32 ddi_func_ctl, ddi_mode, flags = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

422

u32 temp;

sys/dev/pci/drm/i915/display/intel_ddi.c

477

static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)

sys/dev/pci/drm/i915/display/intel_ddi.c

4816

u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_ddi.c

4824

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_ddi.c

4832

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_ddi.c

491

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

508

static u32

sys/dev/pci/drm/i915/display/intel_ddi.c

5114

u32 ddi_buf_ctl;

sys/dev/pci/drm/i915/display/intel_ddi.c

517

u32 temp;

sys/dev/pci/drm/i915/display/intel_ddi.c

630

u32 ctl2 = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

661

u32 ctl;

sys/dev/pci/drm/i915/display/intel_ddi.c

682

u32 ctl;

sys/dev/pci/drm/i915/display/intel_ddi.c

725

bool enable, u32 hdcp_mask)

sys/dev/pci/drm/i915/display/intel_ddi.c

751

u32 ddi_mode;

sys/dev/pci/drm/i915/display/intel_ddi.c

807

u32 tmp;

sys/dev/pci/drm/i915/display/intel_ddi.c

847

u32 port_mask, ddi_select, ddi_mode;

sys/dev/pci/drm/i915/display/intel_ddi.h

79

bool enable, u32 hdcp_mask);

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

15

u32 trans1; /* balance leg enable, de-emph level */

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

16

u32 trans2; /* vref sel, vswing */

sys/dev/pci/drm/i915/display/intel_de.h

110

u32 mask, u32 value, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

119

u32 mask, u32 value,

sys/dev/pci/drm/i915/display/intel_de.h

128

u32 mask, u32 value, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

144

u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)

sys/dev/pci/drm/i915/display/intel_de.h

160

u32 mask, u32 value,

sys/dev/pci/drm/i915/display/intel_de.h

162

unsigned int slow_timeout_ms, u32 *out_value)

sys/dev/pci/drm/i915/display/intel_de.h

179

u32 mask, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

186

u32 mask, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

199

static inline u32

sys/dev/pci/drm/i915/display/intel_de.h

20

static inline u32

sys/dev/pci/drm/i915/display/intel_de.h

202

u32 val;

sys/dev/pci/drm/i915/display/intel_de.h

211

intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

217

static inline u32

sys/dev/pci/drm/i915/display/intel_de.h

224

intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

23

u32 val;

sys/dev/pci/drm/i915/display/intel_de.h

231

i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

77

intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

86

static inline u32

sys/dev/pci/drm/i915/display/intel_de.h

88

u32 clear, u32 set)

sys/dev/pci/drm/i915/display/intel_de.h

93

static inline u32

sys/dev/pci/drm/i915/display/intel_de.h

94

intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/display/intel_de.h

96

u32 val;

sys/dev/pci/drm/i915/display/intel_display.c

157

const char *name, u32 reg, int ref_freq)

sys/dev/pci/drm/i915/display/intel_display.c

159

u32 val;

sys/dev/pci/drm/i915/display/intel_display.c

1603

u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;

sys/dev/pci/drm/i915/display/intel_display.c

173

const char *name, u32 reg)

sys/dev/pci/drm/i915/display/intel_display.c

2188

static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

2190

u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;

sys/dev/pci/drm/i915/display/intel_display.c

2492

intel_reduce_m_n_ratio(u32 *num, u32 *den)

sys/dev/pci/drm/i915/display/intel_display.c

2501

static void compute_m_n(u32 *ret_m, u32 *ret_n,

sys/dev/pci/drm/i915/display/intel_display.c

2502

u32 m, u32 n, u32 constant_n)

sys/dev/pci/drm/i915/display/intel_display.c

2519

u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);

sys/dev/pci/drm/i915/display/intel_display.c

2520

u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,

sys/dev/pci/drm/i915/display/intel_display.c

2522

u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);

sys/dev/pci/drm/i915/display/intel_display.c

2646

u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;

sys/dev/pci/drm/i915/display/intel_display.c

2751

u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;

sys/dev/pci/drm/i915/display/intel_display.c

2844

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

2914

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

2929

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_display.c

2996

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3026

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3129

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3192

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3222

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3271

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3309

u32 bps = target_clock * bpp * 21 / 20;

sys/dev/pci/drm/i915/display/intel_display.c

3368

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3457

u32 tmp = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3487

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3516

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3586

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3745

u32 tmp = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3835

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3875

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3933

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

3963

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

442

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

489

u32 val;

sys/dev/pci/drm/i915/display/intel_display.c

5016

u32 exclude_infoframes = 0;

sys/dev/pci/drm/i915/display/intel_display.c

522

u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;

sys/dev/pci/drm/i915/display/intel_display.c

523

u32 set = 0;

sys/dev/pci/drm/i915/display/intel_display.c

568

u32 val;

sys/dev/pci/drm/i915/display/intel_display.c

608

u32 intel_plane_fb_max_stride(struct drm_device *drm,

sys/dev/pci/drm/i915/display/intel_display.c

609

u32 pixel_format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_display.c

733

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display.c

7690

static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_display.c

7694

u32 possible_clones = 0;

sys/dev/pci/drm/i915/display/intel_display.c

7704

static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_display.c

7708

u32 possible_crtcs = 0;

sys/dev/pci/drm/i915/display/intel_display.c

8244

u32 dpll, fp;

sys/dev/pci/drm/i915/display/intel_display.h

403

u32 intel_plane_fb_max_stride(struct drm_device *drm,

sys/dev/pci/drm/i915/display/intel_display.h

404

u32 pixel_format, u64 modifier);

sys/dev/pci/drm/i915/display/intel_display.h

440

const char *name, u32 reg, int ref_freq);

sys/dev/pci/drm/i915/display/intel_display.h

442

const char *name, u32 reg);

sys/dev/pci/drm/i915/display/intel_display_core.h

108

u32 freq_cntrl;

sys/dev/pci/drm/i915/display/intel_display_core.h

157

const u32 *hpd, *pch_hpd;

sys/dev/pci/drm/i915/display/intel_display_core.h

169

u32 event_bits;

sys/dev/pci/drm/i915/display/intel_display_core.h

170

u32 retry_bits;

sys/dev/pci/drm/i915/display/intel_display_core.h

173

u32 long_hpd_pin_mask;

sys/dev/pci/drm/i915/display/intel_display_core.h

174

u32 short_hpd_pin_mask;

sys/dev/pci/drm/i915/display/intel_display_core.h

387

u32 mmio_base;

sys/dev/pci/drm/i915/display/intel_display_core.h

397

u32 rx_config;

sys/dev/pci/drm/i915/display/intel_display_core.h

409

u32 mmio_base;

sys/dev/pci/drm/i915/display/intel_display_core.h

443

u32 state;

sys/dev/pci/drm/i915/display/intel_display_core.h

479

u32 de_irq_mask[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_display_core.h

480

u32 pipestat_irq_mask[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_display_core.h

502

u32 chv_phy_control;

sys/dev/pci/drm/i915/display/intel_display_core.h

509

u32 mmio_base;

sys/dev/pci/drm/i915/display/intel_display_core.h

530

u32 saveDSPARB;

sys/dev/pci/drm/i915/display/intel_display_core.h

531

u32 saveSWF0[16];

sys/dev/pci/drm/i915/display/intel_display_core.h

532

u32 saveSWF1[16];

sys/dev/pci/drm/i915/display/intel_display_core.h

533

u32 saveSWF3[3];

sys/dev/pci/drm/i915/display/intel_display_core.h

545

u32 block_time_us;

sys/dev/pci/drm/i915/display/intel_display_core.h

567

u32 chv_dpll_md[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_display_core.h

568

u32 bxt_phy_grc;

sys/dev/pci/drm/i915/display/intel_display_device.c

1445

u32 devid;

sys/dev/pci/drm/i915/display/intel_display_device.c

1520

u32 val;

sys/dev/pci/drm/i915/display/intel_display_device.c

1528

addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));

sys/dev/pci/drm/i915/display/intel_display_device.c

1838

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1839

u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1863

u32 dfsm = intel_de_read(display, SKL_DFSM);

sys/dev/pci/drm/i915/display/intel_display_device.c

1912

u32 cap = intel_de_read(display, XE2LPD_DE_CAP);

sys/dev/pci/drm/i915/display/intel_display_device.h

262

u32 rawclk_freq;

sys/dev/pci/drm/i915/display/intel_display_device.h

296

u32 mmio_offset;

sys/dev/pci/drm/i915/display/intel_display_device.h

299

u32 pipe_offsets[I915_MAX_TRANSCODERS];

sys/dev/pci/drm/i915/display/intel_display_device.h

300

u32 trans_offsets[I915_MAX_TRANSCODERS];

sys/dev/pci/drm/i915/display/intel_display_device.h

301

u32 cursor_offsets[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_display_device.h

304

u32 degamma_lut_size;

sys/dev/pci/drm/i915/display/intel_display_device.h

305

u32 gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_display_device.h

306

u32 degamma_lut_tests;

sys/dev/pci/drm/i915/display/intel_display_device.h

307

u32 gamma_lut_tests;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1019

static u32 gen8_de_pipe_fault_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

103

enum pipe pipe, u32 fault_errors)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1186

gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1209

u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1220

u32 psr_iir;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1250

u32 te_trigger)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1255

u32 val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1305

static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1313

static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1315

u32 pica_ier = 0;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1341

void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1343

u32 iir;

sys/dev/pci/drm/i915/display/intel_display_irq.c

135

u32 interrupt_mask, u32 enabled_irq_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

138

u32 new_val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1383

u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1390

u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1405

u32 te_trigger = iir & (DSI0_TE | DSI1_TE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1423

u32 fault_errors;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1473

u32 pica_iir;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1502

u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1504

u32 iir;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1520

void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1528

u32 disp_ctl;

sys/dev/pci/drm/i915/display/intel_display_irq.c

155

void ilk_enable_display_irq(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

160

void ilk_disable_display_irq(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1653

u32 bit = DISPLAY_VER(display) >= 7 ?

sys/dev/pci/drm/i915/display/intel_display_irq.c

1674

u32 bit = DISPLAY_VER(display) >= 7 ?

sys/dev/pci/drm/i915/display/intel_display_irq.c

172

u32 interrupt_mask, u32 enabled_irq_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

175

u32 new_val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

176

u32 old_val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1762

static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1801

static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1803

u32 status, enable, tmp;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1825

static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1830

u32 fault_errors;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1840

u32 *eir, u32 *dpinvgtt)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1842

u32 emr;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1862

u32 eir, u32 dpinvgtt)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1938

static u32 vlv_error_mask(void)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1947

u32 pipestat_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1948

u32 enable_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2031

u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

sys/dev/pci/drm/i915/display/intel_display_irq.c

205

enum pipe pipe, u32 interrupt_mask,

sys/dev/pci/drm/i915/display/intel_display_irq.c

206

u32 enabled_irq_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2082

u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |

sys/dev/pci/drm/i915/display/intel_display_irq.c

209

u32 new_val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2136

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2192

u32 display_mask, extra_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2236

u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |

sys/dev/pci/drm/i915/display/intel_display_irq.c

2238

u32 de_pipe_enables;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2239

u32 de_port_masked = gen8_de_port_aux_mask(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2240

u32 de_port_enables;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2241

u32 de_misc_masked = GEN8_DE_EDP_PSR;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2242

u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

sys/dev/pci/drm/i915/display/intel_display_irq.c

230

enum pipe pipe, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2327

u32 de_hpd_masked = 0;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2328

u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |

sys/dev/pci/drm/i915/display/intel_display_irq.c

2338

u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2339

u32 de_hpd_mask = XELPDP_AUX_TC_MASK;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2340

u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |

sys/dev/pci/drm/i915/display/intel_display_irq.c

2351

u32 mask = SDE_GMBUS_ICP;

sys/dev/pci/drm/i915/display/intel_display_irq.c

236

enum pipe pipe, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2388

u32 derrmr;

sys/dev/pci/drm/i915/display/intel_display_irq.c

248

u32 interrupt_mask,

sys/dev/pci/drm/i915/display/intel_display_irq.c

249

u32 enabled_irq_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

252

u32 sdeimr = intel_de_read(display, SDEIMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

268

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

273

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

278

u32 i915_pipestat_enable_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

281

u32 status_mask = display->irq.pipestat_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

282

u32 enable_mask = status_mask << 16;

sys/dev/pci/drm/i915/display/intel_display_irq.c

323

enum pipe pipe, u32 status_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

327

u32 enable_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

347

enum pipe pipe, u32 status_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

351

u32 enable_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

37

u32 imr_val, u32 ier_val)

sys/dev/pci/drm/i915/display/intel_display_irq.c

403

u32 crc0, u32 crc1,

sys/dev/pci/drm/i915/display/intel_display_irq.c

404

u32 crc2, u32 crc3,

sys/dev/pci/drm/i915/display/intel_display_irq.c

405

u32 crc4)

sys/dev/pci/drm/i915/display/intel_display_irq.c

409

u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };

sys/dev/pci/drm/i915/display/intel_display_irq.c

438

u32 crc0, u32 crc1,

sys/dev/pci/drm/i915/display/intel_display_irq.c

439

u32 crc2, u32 crc3,

sys/dev/pci/drm/i915/display/intel_display_irq.c

440

u32 crc4) {}

sys/dev/pci/drm/i915/display/intel_display_irq.c

481

u32 res1, res2;

sys/dev/pci/drm/i915/display/intel_display_irq.c

514

u32 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/pci/drm/i915/display/intel_display_irq.c

528

u32 status_mask, enable_mask, iir_bit = 0;

sys/dev/pci/drm/i915/display/intel_display_irq.c

581

u32 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/pci/drm/i915/display/intel_display_irq.c

605

u32 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/pci/drm/i915/display/intel_display_irq.c

632

u32 pipe_stats[I915_MAX_PIPES])

sys/dev/pci/drm/i915/display/intel_display_irq.c

654

static void ibx_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

657

u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;

sys/dev/pci/drm/i915/display/intel_display_irq.c

704

static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

739

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

752

u32 fault_errors;

sys/dev/pci/drm/i915/display/intel_display_irq.c

76

u32 fault;

sys/dev/pci/drm/i915/display/intel_display_irq.c

775

u32 serr_int = intel_de_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

788

static void cpt_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

791

u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;

sys/dev/pci/drm/i915/display/intel_display_irq.c

825

static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

854

u32 gtt_fault;

sys/dev/pci/drm/i915/display/intel_display_irq.c

866

u32 fault_errors;

sys/dev/pci/drm/i915/display/intel_display_irq.c

875

void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

878

u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;

sys/dev/pci/drm/i915/display/intel_display_irq.c

911

u32 pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

926

void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

929

u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;

sys/dev/pci/drm/i915/display/intel_display_irq.c

942

u32 psr_iir;

sys/dev/pci/drm/i915/display/intel_display_irq.c

966

u32 pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

975

static u32 gen8_de_port_aux_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

977

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_irq.h

23

u32 interrupt_mask, u32 enabled_irq_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

24

void ilk_enable_display_irq(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

25

void ilk_disable_display_irq(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

27

void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

28

void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

29

void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

32

u32 interrupt_mask, u32 enabled_irq_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

33

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

34

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

50

void ivb_display_irq_handler(struct intel_display *display, u32 de_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.h

51

void ilk_display_irq_handler(struct intel_display *display, u32 de_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.h

52

void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);

sys/dev/pci/drm/i915/display/intel_display_irq.h

55

u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);

sys/dev/pci/drm/i915/display/intel_display_irq.h

56

void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);

sys/dev/pci/drm/i915/display/intel_display_irq.h

72

u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.h

73

void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

74

void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

76

void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

78

void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

79

void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

80

void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

82

void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);

sys/dev/pci/drm/i915/display/intel_display_irq.h

83

void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);

sys/dev/pci/drm/i915/display/intel_display_power.c

1157

u32 mask, val, i;

sys/dev/pci/drm/i915/display/intel_display_power.c

1185

u32 val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1254

static u32 hsw_read_dcomp(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1262

static void hsw_write_dcomp(struct intel_display *display, u32 val)

sys/dev/pci/drm/i915/display/intel_display_power.c

1284

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power.c

1335

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power.c

1439

u32 reset_bits;

sys/dev/pci/drm/i915/display/intel_display_power.c

1589

u32 page_mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1809

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

sys/dev/pci/drm/i915/display/intel_display_power.c

1840

u32 status = intel_de_read(display, DPIO_PHY_STATUS);

sys/dev/pci/drm/i915/display/intel_display_power.c

1895

static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)

sys/dev/pci/drm/i915/display/intel_display_power.c

261

static u32

sys/dev/pci/drm/i915/display/intel_display_power.c

263

u32 target_dc_state)

sys/dev/pci/drm/i915/display/intel_display_power.c

266

static const u32 states[] = {

sys/dev/pci/drm/i915/display/intel_display_power.c

297

u32 state)

sys/dev/pci/drm/i915/display/intel_display_power.c

339

u32 intel_display_power_get_current_dc_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

343

u32 current_dc_state = DC_STATE_DISABLE;

sys/dev/pci/drm/i915/display/intel_display_power.c

951

static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)

sys/dev/pci/drm/i915/display/intel_display_power.c

953

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power.h

141

u32 dc_state;

sys/dev/pci/drm/i915/display/intel_display_power.h

142

u32 target_dc_state;

sys/dev/pci/drm/i915/display/intel_display_power.h

143

u32 allowed_dc_mask;

sys/dev/pci/drm/i915/display/intel_display_power.h

185

u32 state);

sys/dev/pci/drm/i915/display/intel_display_power.h

186

u32 intel_display_power_get_current_dc_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1007

u32 old_state = power_domains->dc_state;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1126

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1127

u32 state;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1128

u32 ctrl;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1129

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1177

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1178

u32 state;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1179

u32 ctrl;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1246

u32 val = intel_de_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1360

u32 phy_control = display->power.chv_phy_control;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1361

u32 phy_status = 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1362

u32 phy_status_mask = 0xffffffff;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1465

u32 tmp;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1560

u32 reg, val, expected, actual;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1691

u32 state, ctrl;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1721

u32 state;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1722

u32 ctrl;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1782

u32 low_val;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1783

u32 high_val = 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

304

static u32 hsw_power_well_requesters(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

308

u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

309

u32 ret;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

325

u32 reqs;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

531

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

608

u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |

sys/dev/pci/drm/i915/display/intel_display_power_well.c

610

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

675

u32 state)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

679

u32 v;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

713

static u32 gen9_dc_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

715

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

735

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

771

void gen9_set_dc_state(struct intel_display *display, u32 state)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

775

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

776

u32 val;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

932

u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

933

u32 bios_req = intel_de_read(display, regs->bios);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

937

u32 drv_req = intel_de_read(display, regs->driver);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

160

void gen9_set_dc_state(struct intel_display *display, u32 state);

sys/dev/pci/drm/i915/display/intel_display_types.h

1106

u32 ctrl, div;

sys/dev/pci/drm/i915/display/intel_display_types.h

1127

u32 dc3co_exitline;

sys/dev/pci/drm/i915/display/intel_display_types.h

1158

u32 control;

sys/dev/pci/drm/i915/display/intel_display_types.h

1159

u32 pgm_ratios;

sys/dev/pci/drm/i915/display/intel_display_types.h

1160

u32 lvds_border_bits;

sys/dev/pci/drm/i915/display/intel_display_types.h

1190

u32 data_rate[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_display_types.h

1192

u32 data_rate_y[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_display_types.h

1199

u32 gamma_mode;

sys/dev/pci/drm/i915/display/intel_display_types.h

1203

u32 csc_mode;

sys/dev/pci/drm/i915/display/intel_display_types.h

1206

u32 cgm_mode;

sys/dev/pci/drm/i915/display/intel_display_types.h

1228

u32 enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

1229

u32 gcp;

sys/dev/pci/drm/i915/display/intel_display_types.h

124

u32 offset;

sys/dev/pci/drm/i915/display/intel_display_types.h

1313

u32 psr2_man_track_ctl;

sys/dev/pci/drm/i915/display/intel_display_types.h

1315

u32 pipe_srcsz_early_tpt;

sys/dev/pci/drm/i915/display/intel_display_types.h

1324

u32 vsync_end, vsync_start;

sys/dev/pci/drm/i915/display/intel_display_types.h

1388

u32 start_mmioaddr;

sys/dev/pci/drm/i915/display/intel_display_types.h

1480

u32 ctl, surf, surflive;

sys/dev/pci/drm/i915/display/intel_display_types.h

1490

u32 frontbuffer_bit;

sys/dev/pci/drm/i915/display/intel_display_types.h

1493

u32 base, cntl, size;

sys/dev/pci/drm/i915/display/intel_display_types.h

1517

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_display_types.h

1540

u32 (*surf_offset)(const struct intel_plane_state *plane_state);

sys/dev/pci/drm/i915/display/intel_display_types.h

1656

u32 debug;

sys/dev/pci/drm/i915/display/intel_display_types.h

1684

u32 dc3co_exitline;

sys/dev/pci/drm/i915/display/intel_display_types.h

1685

u32 dc3co_exit_delay;

sys/dev/pci/drm/i915/display/intel_display_types.h

1699

u32 DP;

sys/dev/pci/drm/i915/display/intel_display_types.h

1774

u32 aux_busy_last_status;

sys/dev/pci/drm/i915/display/intel_display_types.h

1795

u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);

sys/dev/pci/drm/i915/display/intel_display_types.h

1800

u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,

sys/dev/pci/drm/i915/display/intel_display_types.h

1801

u32 aux_clock_divider);

sys/dev/pci/drm/i915/display/intel_display_types.h

1933

u32 (*infoframes_enabled)(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_display_types.h

304

u32 (*get)(struct intel_connector *connector, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display_types.h

305

void (*set)(const struct drm_connector_state *conn_state, u32 level);

sys/dev/pci/drm/i915/display/intel_display_types.h

306

void (*disable)(const struct drm_connector_state *conn_state, u32 level);

sys/dev/pci/drm/i915/display/intel_display_types.h

308

const struct drm_connector_state *conn_state, u32 level);

sys/dev/pci/drm/i915/display/intel_display_types.h

309

u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);

sys/dev/pci/drm/i915/display/intel_display_types.h

384

u32 size;

sys/dev/pci/drm/i915/display/intel_display_types.h

404

u32 level;

sys/dev/pci/drm/i915/display/intel_display_types.h

405

u32 min;

sys/dev/pci/drm/i915/display/intel_display_types.h

406

u32 max;

sys/dev/pci/drm/i915/display/intel_display_types.h

413

u32 pwm_level_min;

sys/dev/pci/drm/i915/display/intel_display_types.h

414

u32 pwm_level_max;

sys/dev/pci/drm/i915/display/intel_display_types.h

482

u32 seq_num_v;

sys/dev/pci/drm/i915/display/intel_display_types.h

490

u32 seq_num_m;

sys/dev/pci/drm/i915/display/intel_display_types.h

520

u32 acpi_device_id;

sys/dev/pci/drm/i915/display/intel_display_types.h

662

u32 ctl;

sys/dev/pci/drm/i915/display/intel_display_types.h

665

u32 color_ctl;

sys/dev/pci/drm/i915/display/intel_display_types.h

668

u32 cus_ctl;

sys/dev/pci/drm/i915/display/intel_display_types.h

671

u32 surf;

sys/dev/pci/drm/i915/display/intel_display_types.h

722

u32 base;

sys/dev/pci/drm/i915/display/intel_display_types.h

727

u32 mode;

sys/dev/pci/drm/i915/display/intel_display_types.h

781

u32 pri_val;

sys/dev/pci/drm/i915/display/intel_display_types.h

782

u32 spr_val;

sys/dev/pci/drm/i915/display/intel_display_types.h

783

u32 cur_val;

sys/dev/pci/drm/i915/display/intel_display_types.h

784

u32 fbc_val;

sys/dev/pci/drm/i915/display/intel_display_types.h

936

u32 tu;

sys/dev/pci/drm/i915/display/intel_display_types.h

937

u32 data_m;

sys/dev/pci/drm/i915/display/intel_display_types.h

938

u32 data_n;

sys/dev/pci/drm/i915/display/intel_display_types.h

939

u32 link_m;

sys/dev/pci/drm/i915/display/intel_display_types.h

940

u32 link_n;

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

46

u32

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

49

u32 val;

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

70

intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

91

intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

16

u32

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

19

intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

21

intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

14

u32 reg:24;

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

15

u32 bank_idx:4;

sys/dev/pci/drm/i915/display/intel_dmc.c

1022

static u32 parse_dmc_fw_header(struct intel_dmc *dmc,

sys/dev/pci/drm/i915/display/intel_dmc.c

1029

const u32 *mmioaddr, *mmiodata;

sys/dev/pci/drm/i915/display/intel_dmc.c

1030

u32 mmio_count, mmio_count_max, start_mmioaddr;

sys/dev/pci/drm/i915/display/intel_dmc.c

1104

u32 orig_mmiodata[2] = {

sys/dev/pci/drm/i915/display/intel_dmc.c

1162

static u32

sys/dev/pci/drm/i915/display/intel_dmc.c

1169

u32 package_size = sizeof(struct intel_package_header);

sys/dev/pci/drm/i915/display/intel_dmc.c

1170

u32 num_entries, max_entries;

sys/dev/pci/drm/i915/display/intel_dmc.c

1218

static u32 parse_dmc_fw_css(struct intel_dmc *dmc,

sys/dev/pci/drm/i915/display/intel_dmc.c

1251

u32 readcount = 0;

sys/dev/pci/drm/i915/display/intel_dmc.c

1252

u32 r, offset;

sys/dev/pci/drm/i915/display/intel_dmc.c

1511

u32 version;

sys/dev/pci/drm/i915/display/intel_dmc.c

1551

u32 dc5_cur_count;

sys/dev/pci/drm/i915/display/intel_dmc.c

1564

static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)

sys/dev/pci/drm/i915/display/intel_dmc.c

1592

u32 dc6_allowed_count;

sys/dev/pci/drm/i915/display/intel_dmc.c

1675

u32 tmp = 0, int_vector;

sys/dev/pci/drm/i915/display/intel_dmc.c

1733

u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_dmc.c

185

static const char *dmc_firmware_default(struct intel_display *display, u32 *size)

sys/dev/pci/drm/i915/display/intel_dmc.c

188

u32 max_fw_size = 0;

sys/dev/pci/drm/i915/display/intel_dmc.c

257

u32 module_type;

sys/dev/pci/drm/i915/display/intel_dmc.c

260

u32 header_len;

sys/dev/pci/drm/i915/display/intel_dmc.c

263

u32 header_ver;

sys/dev/pci/drm/i915/display/intel_dmc.c

266

u32 module_id;

sys/dev/pci/drm/i915/display/intel_dmc.c

269

u32 module_vendor;

sys/dev/pci/drm/i915/display/intel_dmc.c

272

u32 date;

sys/dev/pci/drm/i915/display/intel_dmc.c

275

u32 size;

sys/dev/pci/drm/i915/display/intel_dmc.c

278

u32 key_size;

sys/dev/pci/drm/i915/display/intel_dmc.c

281

u32 modulus_size;

sys/dev/pci/drm/i915/display/intel_dmc.c

284

u32 exponent_size;

sys/dev/pci/drm/i915/display/intel_dmc.c

287

u32 reserved1[12];

sys/dev/pci/drm/i915/display/intel_dmc.c

290

u32 version;

sys/dev/pci/drm/i915/display/intel_dmc.c

293

u32 reserved2[8];

sys/dev/pci/drm/i915/display/intel_dmc.c

296

u32 kernel_header_info;

sys/dev/pci/drm/i915/display/intel_dmc.c

311

u32 offset;

sys/dev/pci/drm/i915/display/intel_dmc.c

312

u32 reserved2;

sys/dev/pci/drm/i915/display/intel_dmc.c

325

u32 num_entries;

sys/dev/pci/drm/i915/display/intel_dmc.c

330

u32 signature;

sys/dev/pci/drm/i915/display/intel_dmc.c

342

u32 project;

sys/dev/pci/drm/i915/display/intel_dmc.c

345

u32 fw_size;

sys/dev/pci/drm/i915/display/intel_dmc.c

348

u32 fw_version;

sys/dev/pci/drm/i915/display/intel_dmc.c

355

u32 mmio_count;

sys/dev/pci/drm/i915/display/intel_dmc.c

358

u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];

sys/dev/pci/drm/i915/display/intel_dmc.c

361

u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];

sys/dev/pci/drm/i915/display/intel_dmc.c

366

u32 reserved1[2];

sys/dev/pci/drm/i915/display/intel_dmc.c

373

u32 start_mmioaddr;

sys/dev/pci/drm/i915/display/intel_dmc.c

375

u32 reserved[9];

sys/dev/pci/drm/i915/display/intel_dmc.c

381

u32 mmio_count;

sys/dev/pci/drm/i915/display/intel_dmc.c

384

u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];

sys/dev/pci/drm/i915/display/intel_dmc.c

387

u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];

sys/dev/pci/drm/i915/display/intel_dmc.c

504

static u32 pipedmc_interrupt_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

516

static u32 dmc_evt_ctl_disable(void)

sys/dev/pci/drm/i915/display/intel_dmc.c

527

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dmc.c

528

u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

529

u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

sys/dev/pci/drm/i915/display/intel_dmc.c

537

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dmc.c

538

u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

539

u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

sys/dev/pci/drm/i915/display/intel_dmc.c

547

i915_reg_t reg, u32 data)

sys/dev/pci/drm/i915/display/intel_dmc.c

555

i915_reg_t reg_ctl, u32 *data_ctl,

sys/dev/pci/drm/i915/display/intel_dmc.c

556

i915_reg_t reg_htp, u32 *data_htp)

sys/dev/pci/drm/i915/display/intel_dmc.c

585

i915_reg_t reg, u32 data)

sys/dev/pci/drm/i915/display/intel_dmc.c

607

static u32 dmc_mmiodata(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

654

u32 expected, found;

sys/dev/pci/drm/i915/display/intel_dmc.c

68

u32 max_fw_size; /* bytes */

sys/dev/pci/drm/i915/display/intel_dmc.c

69

u32 version;

sys/dev/pci/drm/i915/display/intel_dmc.c

71

u32 dc5_start;

sys/dev/pci/drm/i915/display/intel_dmc.c

72

u32 count;

sys/dev/pci/drm/i915/display/intel_dmc.c

75

u32 mmio_count;

sys/dev/pci/drm/i915/display/intel_dmc.c

77

u32 mmiodata[20];

sys/dev/pci/drm/i915/display/intel_dmc.c

78

u32 dmc_offset;

sys/dev/pci/drm/i915/display/intel_dmc.c

79

u32 start_mmioaddr;

sys/dev/pci/drm/i915/display/intel_dmc.c

80

u32 dmc_fw_size; /*dwords */

sys/dev/pci/drm/i915/display/intel_dmc.c

81

u32 *payload;

sys/dev/pci/drm/i915/display/intel_dmc.c

826

u32 data = dmc->dmc_info[dmc_id].mmiodata[i];

sys/dev/pci/drm/i915/display/intel_dmc.c

990

const u32 *mmioaddr, u32 mmio_count,

sys/dev/pci/drm/i915/display/intel_dmc.c

994

u32 start_range, end_range;

sys/dev/pci/drm/i915/display/intel_dmc.h

43

u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

231

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

234

u32 end = ranges[i].end ?: ranges[i].start;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

245

u32 dc_state)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

343

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

63

u32 start;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

64

u32 end;

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

28

u32 dc_state;

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

33

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);

sys/dev/pci/drm/i915/display/intel_dp.c

1958

static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

1959

u32 lane_count, u32 mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

1963

u32 available_bw, required_bw;

sys/dev/pci/drm/i915/display/intel_dp.c

4851

u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |

sys/dev/pci/drm/i915/display/intel_dp.c

4858

u32 val = intel_de_read(display, reg) & ~dip_enable;

sys/dev/pci/drm/i915/display/intel_dp.c

816

u32 intel_dp_mode_to_fec_clock(u32 mode_clock)

sys/dev/pci/drm/i915/display/intel_dp.c

847

static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)

sys/dev/pci/drm/i915/display/intel_dp.c

849

u32 bits_per_pixel = bpp;

sys/dev/pci/drm/i915/display/intel_dp.c

877

bits_per_pixel = min_t(u32, bits_per_pixel, 27);

sys/dev/pci/drm/i915/display/intel_dp.c

898

static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

901

u32 max_bpp;

sys/dev/pci/drm/i915/display/intel_dp.c

915

static u32 small_joiner_ram_max_bpp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

916

u32 mode_hdisplay,

sys/dev/pci/drm/i915/display/intel_dp.c

919

u32 max_bpp;

sys/dev/pci/drm/i915/display/intel_dp.c

934

static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)

sys/dev/pci/drm/i915/display/intel_dp.c

941

u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

942

u32 mode_clock, u32 mode_hdisplay,

sys/dev/pci/drm/i915/display/intel_dp.c

945

u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp.c

958

u32 link_clock, u32 lane_count,

sys/dev/pci/drm/i915/display/intel_dp.c

959

u32 mode_clock, u32 mode_hdisplay,

sys/dev/pci/drm/i915/display/intel_dp.c

962

u32 pipe_bpp,

sys/dev/pci/drm/i915/display/intel_dp.c

963

u32 timeslots)

sys/dev/pci/drm/i915/display/intel_dp.c

965

u32 bits_per_pixel, joiner_max_bpp;

sys/dev/pci/drm/i915/display/intel_dp.c

997

bits_per_pixel = min_t(u32, bits_per_pixel, 31);

sys/dev/pci/drm/i915/display/intel_dp.h

140

u32 link_clock, u32 lane_count,

sys/dev/pci/drm/i915/display/intel_dp.h

141

u32 mode_clock, u32 mode_hdisplay,

sys/dev/pci/drm/i915/display/intel_dp.h

144

u32 pipe_bpp,

sys/dev/pci/drm/i915/display/intel_dp.h

145

u32 timeslots);

sys/dev/pci/drm/i915/display/intel_dp.h

166

u32 intel_dp_mode_to_fec_clock(u32 mode_clock);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

112

static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

129

static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

176

static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

178

u32 aux_clock_divider)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

181

u32 timeout;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

200

static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

202

u32 unused)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

206

u32 ret;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

240

u32 aux_send_ctl_flags)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

246

u32 aux_clock_divider;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

252

u32 status;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

322

const u32 status = intel_de_read(display, ch_ctl);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

34

u32 intel_dp_aux_pack(const u8 *src, int src_bytes)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

342

u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

37

u32 v = 0;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

42

v |= ((u32)src[i]) << ((3 - i) * 8);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

46

static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

468

static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

489

u32 flags = intel_dp_aux_xfer_flags(msg);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

56

static u32

sys/dev/pci/drm/i915/display/intel_dp_aux.c

62

u32 status;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

77

static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

91

static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

95

u32 freq;

sys/dev/pci/drm/i915/display/intel_dp_aux.h

22

u32 intel_dp_aux_pack(const u8 *src, int src_bytes);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

174

static u32

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

192

u32 pwm_level = panel->backlight.pwm_funcs->get(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

213

intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

230

intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

239

const u32 pwm_level = intel_backlight_level_to_pwm(connector, level);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

305

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

332

u32 pwm_level = intel_backlight_level_to_pwm(connector, level);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

354

intel_dp_aux_hdr_disable_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

441

static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

446

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

467

intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

474

const u32 pwm_level = intel_backlight_level_to_pwm(connector, level);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

484

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

491

u32 pwm_level;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

506

u32 level)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

526

u32 current_level;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

228

int i, u32 *part)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

24

static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

298

u32 offset;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

300

u32 timeout;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

301

u32 timeout2; /* Added for non_paired situation */

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

303

u32 msg_read_timeout;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

492

u32 *dev_cnt, u8 *byte)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

529

u32 dev_cnt;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

773

u32 stream_enc_status;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

808

u32 val;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1029

u32 training_pattern;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

775

static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1255

u32 clear = 0;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1256

u32 set = 0;

sys/dev/pci/drm/i915/display/intel_dp_test.c

229

u32 pattern_val;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

464

u32 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

669

u32 failed_stream_mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1043

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1074

u32 demph_reg_value, u32 preemph_reg_value,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1075

u32 uniqtranscale_reg_value, u32 tx3_demph)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1138

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1174

u32 port_mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

156

u32 pwron_mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

281

static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

284

u32 clear, u32 set)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

286

u32 old, val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

329

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

383

static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

385

u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

400

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

451

u32 grc_code;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

515

i915_reg_t reg, u32 mask, u32 expected,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

520

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

544

u32 mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

577

u32 grc_code = display->state.bxt_phy_grc;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

649

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

717

u32 deemph_reg_value, u32 margin_reg_value,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

724

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

819

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

878

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

957

u32 val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

132

u32 deemph_reg_value, u32 margin_reg_value,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

159

u32 demph_reg_value, u32 preemph_reg_value,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

160

u32 uniqtranscale_reg_value, u32 tx3_demph)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

52

u32 deemph_reg_value, u32 margin_reg_value,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

67

u32 demph_reg_value, u32 preemph_reg_value,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

68

u32 uniqtranscale_reg_value, u32 tx3_demph);

sys/dev/pci/drm/i915/display/intel_dpll.c

1002

static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_dpll.c

1007

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1092

static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_dpll.c

1097

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1255

static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)

sys/dev/pci/drm/i915/display/intel_dpll.c

1257

u32 fp;

sys/dev/pci/drm/i915/display/intel_dpll.c

1266

static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_dpll.c

1271

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1421

static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_dpll.c

1424

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1447

static u32 chv_dpll(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_dpll.c

1450

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1875

u32 tmp;

sys/dev/pci/drm/i915/display/intel_dpll.c

1909

u32 tmp, coreclk;

sys/dev/pci/drm/i915/display/intel_dpll.c

2029

u32 tmp, loopfilter, tribuf_calcntr;

sys/dev/pci/drm/i915/display/intel_dpll.c

2030

u32 m2_frac;

sys/dev/pci/drm/i915/display/intel_dpll.c

2119

u32 tmp;

sys/dev/pci/drm/i915/display/intel_dpll.c

2231

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll.c

2249

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll.c

331

static u32 i9xx_dpll_compute_m(const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

397

u32 tmp;

sys/dev/pci/drm/i915/display/intel_dpll.c

428

u32 dpll = hw_state->dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

429

u32 fp;

sys/dev/pci/drm/i915/display/intel_dpll.c

482

u32 lvds = intel_de_read(display, LVDS);

sys/dev/pci/drm/i915/display/intel_dpll.c

524

u32 tmp;

sys/dev/pci/drm/i915/display/intel_dpll.c

551

u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;

sys/dev/pci/drm/i915/display/intel_dpll.c

987

u32 i9xx_dpll_compute_fp(const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

992

static u32 pnv_dpll_compute_fp(const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

997

static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_dpll.h

25

u32 i9xx_dpll_compute_fp(const struct dpll *dpll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1005

u32 wrpll = hw_state->wrpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1436

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1473

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1589

u32 dco_fraction;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1590

u32 dco_integer;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1591

u32 qdiv_ratio;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1592

u32 qdiv_mode;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1593

u32 kdiv;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1594

u32 pdiv;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1595

u32 central_freq;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1602

u32 p0, u32 p1, u32 p2)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1744

u32 p0, p1, p2, dco_freq;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1852

u32 ctrl1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2048

u32 temp;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2179

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2309

u32 prop_coef, int_coef, gain_ctl, targ_cnt;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2310

u32 lanestagger;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2561

u32 dco_freq, u32 ref_freq,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2564

u32 dco;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2798

u32 afe_clock = crtc_state->port_clock * 5;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2799

u32 dco_min = 7998000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2800

u32 dco_max = 10000000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2801

u32 dco_mid = (dco_min + dco_max) / 2;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2808

u32 dco, best_dco = 0, dco_centrality = 0;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2809

u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2842

u32 dco_fraction;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2843

u32 p0, p1, p2, dco_freq;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2903

u32 dco_fraction = pll_params->dco_fraction;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2926

u32 *target_dco_khz,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2931

u32 dco_min_freq, dco_max_freq;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2944

u32 hsdiv;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3012

u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3013

u32 iref_ndiv, iref_trim, iref_pulse_w;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3014

u32 prop_coeff, int_coeff;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3015

u32 tdc_targetcnt, feedfwgain;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3214

u32 m1, m2_int, m2_frac, div1, div2, ref_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3557

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3624

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3696

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3854

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3942

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

535

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

554

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

756

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

777

u32 val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

191

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

192

u32 dpll_md;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

193

u32 fp0;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

194

u32 fp1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

198

u32 wrpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

199

u32 spll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

209

u32 ctrl1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

211

u32 cfgcr1, cfgcr2;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

215

u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

219

u32 cfgcr0, cfgcr1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

222

u32 div0;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

224

u32 mg_refclkin_ctl;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

225

u32 mg_clktop2_coreclkctl1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

226

u32 mg_clktop2_hsclkctl;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

227

u32 mg_pll_div0;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

228

u32 mg_pll_div1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

229

u32 mg_pll_lf;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

230

u32 mg_pll_frac_lock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

231

u32 mg_pll_ssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

232

u32 mg_pll_bias;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

233

u32 mg_pll_tdc_coldst_bias;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

234

u32 mg_pll_bias_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

235

u32 mg_pll_tdc_coldst_bias_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

239

u32 clock; /* in KHz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

240

u32 ref_control;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

241

u32 mpllb_cp;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

242

u32 mpllb_div;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

243

u32 mpllb_div2;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

244

u32 mpllb_fracn1;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

245

u32 mpllb_fracn2;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

246

u32 mpllb_sscen;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

247

u32 mpllb_sscstep;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

251

u32 clock; /* in KHz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

258

u32 clock; /* in kHz */

sys/dev/pci/drm/i915/display/intel_dpt.c

45

u32 flags)

sys/dev/pci/drm/i915/display/intel_dpt.c

57

u32 flags)

sys/dev/pci/drm/i915/display/intel_dpt.c

85

u32 flags)

sys/dev/pci/drm/i915/display/intel_dpt.c

87

u32 pte_flags;

sys/dev/pci/drm/i915/display/intel_drrs.c

84

u32 bit;

sys/dev/pci/drm/i915/display/intel_dsb.c

189

static u32 dsb_chicken(struct intel_atomic_state *state,

sys/dev/pci/drm/i915/display/intel_dsb.c

273

static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)

sys/dev/pci/drm/i915/display/intel_dsb.c

289

u32 opcode, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_dsb.c

291

u32 prev_opcode, prev_reg;

sys/dev/pci/drm/i915/display/intel_dsb.c

328

i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_dsb.c

366

i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_dsb.c

374

static u32 intel_dsb_mask_to_byte_en(u32 mask)

sys/dev/pci/drm/i915/display/intel_dsb.c

384

i915_reg_t reg, u32 mask, u32 val)

sys/dev/pci/drm/i915/display/intel_dsb.c

441

u32 opcode, int lower, int upper)

sys/dev/pci/drm/i915/display/intel_dsb.c

48

u32 ins[2];

sys/dev/pci/drm/i915/display/intel_dsb.c

514

i915_reg_t reg, u32 mask, u32 val,

sys/dev/pci/drm/i915/display/intel_dsb.c

534

u32 aligned_tail, tail;

sys/dev/pci/drm/i915/display/intel_dsb.c

550

u32 aligned_tail, tail;

sys/dev/pci/drm/i915/display/intel_dsb.c

57

u32 chicken;

sys/dev/pci/drm/i915/display/intel_dsb.c

637

static u32 dsb_error_int_status(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dsb.c

639

u32 errors;

sys/dev/pci/drm/i915/display/intel_dsb.c

660

static u32 dsb_error_int_en(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dsb.c

662

u32 errors;

sys/dev/pci/drm/i915/display/intel_dsb.c

747

u32 ctrl)

sys/dev/pci/drm/i915/display/intel_dsb.c

882

u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);

sys/dev/pci/drm/i915/display/intel_dsb.c

990

u32 tmp, errors;

sys/dev/pci/drm/i915/display/intel_dsb.h

40

i915_reg_t reg, u32 val);

sys/dev/pci/drm/i915/display/intel_dsb.h

42

i915_reg_t reg, u32 val);

sys/dev/pci/drm/i915/display/intel_dsb.h

44

i915_reg_t reg, u32 mask, u32 val);

sys/dev/pci/drm/i915/display/intel_dsb.h

62

i915_reg_t reg, u32 mask, u32 val,

sys/dev/pci/drm/i915/display/intel_dsb_buffer.c

13

u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)

sys/dev/pci/drm/i915/display/intel_dsb_buffer.c

18

void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)

sys/dev/pci/drm/i915/display/intel_dsb_buffer.c

23

u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)

sys/dev/pci/drm/i915/display/intel_dsb_buffer.c

28

void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)

sys/dev/pci/drm/i915/display/intel_dsb_buffer.c

40

u32 *buf;

sys/dev/pci/drm/i915/display/intel_dsb_buffer.h

15

u32 *cmd_buf;

sys/dev/pci/drm/i915/display/intel_dsb_buffer.h

20

u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf);

sys/dev/pci/drm/i915/display/intel_dsb_buffer.h

21

void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val);

sys/dev/pci/drm/i915/display/intel_dsb_buffer.h

22

u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx);

sys/dev/pci/drm/i915/display/intel_dsb_buffer.h

23

void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size);

sys/dev/pci/drm/i915/display/intel_dsi.h

111

u32 pclk;

sys/dev/pci/drm/i915/display/intel_dsi.h

93

u32 bw_timer;

sys/dev/pci/drm/i915/display/intel_dsi.h

94

u32 dphy_reg;

sys/dev/pci/drm/i915/display/intel_dsi.h

97

u32 dphy_data_lane_reg;

sys/dev/pci/drm/i915/display/intel_dsi.h

98

u32 video_frmt_cfg_bits;

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

129

const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

47

static u32 dcs_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

67

static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

94

static void dcs_disable_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

187

u32 delay = *((const u32 *) data);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

561

u32 value, mask, reg_address;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

823

u32 bitrate;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

108

u32 target_burst_mode_freq;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

109

u32 dsi_ddr_clk;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

110

u32 bridge_ref_clk;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

131

u32 hs_tx_timeout;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

132

u32 lp_rx_timeout;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

133

u32 turn_around_timeout;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

134

u32 device_reset_timer;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

135

u32 master_init_timer;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

136

u32 dbi_bw_timer;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

137

u32 lp_byte_clk_val;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

141

u32 prepare_cnt:6;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

142

u32 rsvd8:2;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

143

u32 clk_zero_cnt:8;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

144

u32 trail_cnt:5;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

145

u32 rsvd9:3;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

146

u32 exit_zero_cnt:6;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

147

u32 rsvd10:2;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

150

u32 clk_lane_switch_cnt;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

151

u32 hl_switch_cnt;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

153

u32 rsvd11[6];

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

51

u32 enable_dithering:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

52

u32 rsvd1:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

53

u32 is_bridge:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

55

u32 panel_arch_type:2;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

56

u32 is_cmd_mode:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

61

u32 video_transfer_mode:2;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

63

u32 cabc_supported:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

66

u32 pwm_blc:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

72

u32 videomode_color_format:4;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

78

u32 rotation:2;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

79

u32 bta_disable:1;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

80

u32 rsvd2:15;

sys/dev/pci/drm/i915/display/intel_dvo.c

137

u32 tmp;

sys/dev/pci/drm/i915/display/intel_dvo.c

152

u32 tmp;

sys/dev/pci/drm/i915/display/intel_dvo.c

166

u32 tmp, flags = 0;

sys/dev/pci/drm/i915/display/intel_dvo.c

297

u32 dvo_val;

sys/dev/pci/drm/i915/display/intel_dvo.c

422

u32 dpll[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_dvo_dev.h

40

u32 gpio;

sys/dev/pci/drm/i915/display/intel_fb.c

1000

static u32 intel_adjust_linear_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fb.c

1003

u32 old_offset,

sys/dev/pci/drm/i915/display/intel_fb.c

1004

u32 new_offset)

sys/dev/pci/drm/i915/display/intel_fb.c

1014

static u32 intel_adjust_aligned_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fb.c

1019

u32 old_offset, u32 new_offset)

sys/dev/pci/drm/i915/display/intel_fb.c

1055

u32 intel_plane_adjust_aligned_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fb.c

1058

u32 old_offset, u32 new_offset)

sys/dev/pci/drm/i915/display/intel_fb.c

1080

static u32 intel_compute_aligned_offset(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

1089

u32 offset, offset_aligned;

sys/dev/pci/drm/i915/display/intel_fb.c

1135

u32 intel_plane_compute_aligned_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fb.c

1315

u32 stride, max_stride;

sys/dev/pci/drm/i915/display/intel_fb.c

1377

static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)

sys/dev/pci/drm/i915/display/intel_fb.c

1381

u32 offset;

sys/dev/pci/drm/i915/display/intel_fb.c

1487

static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,

sys/dev/pci/drm/i915/display/intel_fb.c

1489

u32 obj_offset, u32 gtt_offset, int x, int y,

sys/dev/pci/drm/i915/display/intel_fb.c

1499

u32 size = 0;

sys/dev/pci/drm/i915/display/intel_fb.c

1549

u32 aligned_offset = ALIGN(gtt_offset,

sys/dev/pci/drm/i915/display/intel_fb.c

1706

u32 gtt_offset_rotated = 0;

sys/dev/pci/drm/i915/display/intel_fb.c

1707

u32 gtt_offset_remapped = 0;

sys/dev/pci/drm/i915/display/intel_fb.c

1727

u32 offset;

sys/dev/pci/drm/i915/display/intel_fb.c

1845

u32 gtt_offset = 0;

sys/dev/pci/drm/i915/display/intel_fb.c

1874

u32 offset;

sys/dev/pci/drm/i915/display/intel_fb.c

1951

u32 intel_fb_xy_to_linear(int x, int y,

sys/dev/pci/drm/i915/display/intel_fb.c

1977

u32 intel_fb_max_stride(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

1978

u32 pixel_format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

2047

u32 stride, max_stride;

sys/dev/pci/drm/i915/display/intel_fb.c

2218

u32 max_stride;

sys/dev/pci/drm/i915/display/intel_fb.c

386

int num_formats, u32 format)

sys/dev/pci/drm/i915/display/intel_fb.c

435

intel_fb_get_format_info(u32 pixel_format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

973

static u32 intel_adjust_tile_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fb.c

978

u32 old_offset,

sys/dev/pci/drm/i915/display/intel_fb.c

979

u32 new_offset)

sys/dev/pci/drm/i915/display/intel_fb.h

50

intel_fb_get_format_info(u32 pixel_format, u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

73

u32 intel_plane_adjust_aligned_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fb.h

76

u32 old_offset, u32 new_offset);

sys/dev/pci/drm/i915/display/intel_fb.h

77

u32 intel_plane_compute_aligned_offset(int *x, int *y,

sys/dev/pci/drm/i915/display/intel_fbc.c

271

static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

276

u32 fbc_ctl;

sys/dev/pci/drm/i915/display/intel_fbc.c

299

static u32 i965_fbc_ctl2(struct intel_fbc *fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

302

u32 fbc_ctl2;

sys/dev/pci/drm/i915/display/intel_fbc.c

316

u32 fbc_ctl;

sys/dev/pci/drm/i915/display/intel_fbc.c

423

static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

438

static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

442

u32 dpfc_ctl;

sys/dev/pci/drm/i915/display/intel_fbc.c

475

u32 dpfc_ctl;

sys/dev/pci/drm/i915/display/intel_fbc.c

541

u32 dpfc_ctl;

sys/dev/pci/drm/i915/display/intel_fbc.c

585

u32 ctl = 0;

sys/dev/pci/drm/i915/display/intel_fbc.c

622

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_fbc.c

635

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_fbc.c

647

static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

651

u32 dpfc_ctl;

sys/dev/pci/drm/i915/display/intel_fbc.c

673

u32 dpfc_ctl;

sys/dev/pci/drm/i915/display/intel_fdi.c

1001

u32 temp;

sys/dev/pci/drm/i915/display/intel_fdi.c

1054

u32 temp;

sys/dev/pci/drm/i915/display/intel_fdi.c

272

u32 fdi_pll_clk;

sys/dev/pci/drm/i915/display/intel_fdi.c

391

u32 temp;

sys/dev/pci/drm/i915/display/intel_fdi.c

443

u32 temp;

sys/dev/pci/drm/i915/display/intel_fdi.c

484

u32 temp, tries;

sys/dev/pci/drm/i915/display/intel_fdi.c

585

u32 temp, i, retry;

sys/dev/pci/drm/i915/display/intel_fdi.c

720

u32 temp, i, j;

sys/dev/pci/drm/i915/display/intel_fdi.c

853

u32 temp, i, rx_ctl_val;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

122

u32 enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

137

u32 bit = (pipe == PIPE_A) ?

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

150

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

201

u32 bit = (pch_transcoder == PIPE_A) ?

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

214

u32 serr_int = intel_de_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

98

u32 enable_mask;

sys/dev/pci/drm/i915/display/intel_fixed.h

107

static inline u32 div_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t d)

sys/dev/pci/drm/i915/display/intel_fixed.h

115

return (u32)tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

118

static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul)

sys/dev/pci/drm/i915/display/intel_fixed.h

138

u32 add2)

sys/dev/pci/drm/i915/display/intel_fixed.h

15

u32 val;

sys/dev/pci/drm/i915/display/intel_fixed.h

25

static inline uint_fixed_16_16_t u32_to_fixed16(u32 val)

sys/dev/pci/drm/i915/display/intel_fixed.h

34

static inline u32 fixed16_to_u32_round_up(uint_fixed_16_16_t fp)

sys/dev/pci/drm/i915/display/intel_fixed.h

39

static inline u32 fixed16_to_u32(uint_fixed_16_16_t fp)

sys/dev/pci/drm/i915/display/intel_fixed.h

62

uint_fixed_16_16_t fp = { .val = (u32)val };

sys/dev/pci/drm/i915/display/intel_fixed.h

69

static inline u32 div_round_up_fixed16(uint_fixed_16_16_t val,

sys/dev/pci/drm/i915/display/intel_fixed.h

75

static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul)

sys/dev/pci/drm/i915/display/intel_fixed.h

83

return (u32)tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

97

static inline uint_fixed_16_16_t div_fixed16(u32 val, u32 d)

sys/dev/pci/drm/i915/display/intel_flipq.c

213

u32 tmp;

sys/dev/pci/drm/i915/display/intel_flipq.c

293

u32 start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

345

struct intel_flipq *flipq, u32 data, int i)

sys/dev/pci/drm/i915/display/intel_gmbus.c

245

static u32 get_reserved(struct intel_gmbus *bus)

sys/dev/pci/drm/i915/display/intel_gmbus.c

248

u32 preserve_bits = 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

268

u32 reserved = get_reserved(bus);

sys/dev/pci/drm/i915/display/intel_gmbus.c

280

u32 reserved = get_reserved(bus);

sys/dev/pci/drm/i915/display/intel_gmbus.c

292

u32 reserved = get_reserved(bus);

sys/dev/pci/drm/i915/display/intel_gmbus.c

293

u32 clock_bits;

sys/dev/pci/drm/i915/display/intel_gmbus.c

309

u32 reserved = get_reserved(bus);

sys/dev/pci/drm/i915/display/intel_gmbus.c

310

u32 data_bits;

sys/dev/pci/drm/i915/display/intel_gmbus.c

326

u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);

sys/dev/pci/drm/i915/display/intel_gmbus.c

327

u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |

sys/dev/pci/drm/i915/display/intel_gmbus.c

50

u32 force_bit;

sys/dev/pci/drm/i915/display/intel_gmbus.c

509

static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)

sys/dev/pci/drm/i915/display/intel_gmbus.c

51

u32 reg0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

512

u32 gmbus2;

sys/dev/pci/drm/i915/display/intel_gmbus.c

548

u32 irq_enable;

sys/dev/pci/drm/i915/display/intel_gmbus.c

576

u32 gmbus0_reg, u32 gmbus1_index)

sys/dev/pci/drm/i915/display/intel_gmbus.c

600

u32 val, loop = 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

637

u32 gmbus0_reg, u32 gmbus1_index)

sys/dev/pci/drm/i915/display/intel_gmbus.c

665

u32 gmbus1_index)

sys/dev/pci/drm/i915/display/intel_gmbus.c

668

u32 val, loop;

sys/dev/pci/drm/i915/display/intel_gmbus.c

699

u32 gmbus1_index)

sys/dev/pci/drm/i915/display/intel_gmbus.c

737

u32 gmbus0_reg)

sys/dev/pci/drm/i915/display/intel_gmbus.c

739

u32 gmbus1_index = 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

740

u32 gmbus5 = 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

769

u32 gmbus0_source)

sys/dev/pci/drm/i915/display/intel_gmbus.c

962

static u32 gmbus_func(struct i2c_adapter *adapter)

sys/dev/pci/drm/i915/display/intel_hdcp.c

1756

u32 seq_num_v, device_cnt;

sys/dev/pci/drm/i915/display/intel_hdcp.c

378

u32 val;

sys/dev/pci/drm/i915/display/intel_hdcp.c

428

static int intel_write_sha_text(struct intel_display *display, u32 sha_text)

sys/dev/pci/drm/i915/display/intel_hdcp.c

439

u32 intel_hdcp_get_repeater_ctl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

489

u32 vprime, sha_text, sha_leftovers, rep_ctl;

sys/dev/pci/drm/i915/display/intel_hdcp.c

51

u32 rekey_bit = 0;

sys/dev/pci/drm/i915/display/intel_hdcp.c

818

u32 val;

sys/dev/pci/drm/i915/display/intel_hdcp.c

820

u32 reg[2];

sys/dev/pci/drm/i915/display/intel_hdcp.c

824

u32 reg[2];

sys/dev/pci/drm/i915/display/intel_hdcp.c

828

u32 reg;

sys/dev/pci/drm/i915/display/intel_hdcp.c

990

u32 repeater_ctl;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

180

u32 reply_size, msg_size_in, msg_size_out;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

228

reply_size, (u32)msg_out_len);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

232

reply_size, (u32)msg_out_len);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

82

int i, u32 *part);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1060

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1061

u32 port = VIDEO_DIP_PORT(encoder->port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

111

static u32 g4x_infoframe_enable(unsigned int type)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1118

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1167

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1168

u32 port = VIDEO_DIP_PORT(encoder->port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1223

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1248

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

136

static u32 hsw_infoframe_enable(unsigned int type)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1481

int i, u32 *part)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1504

u32 scanline;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1576

u32 reg;

sys/dev/pci/drm/i915/display/intel_hdmi.c

218

const u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

219

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

254

u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

264

static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

268

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

286

const u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

289

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

326

u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

336

static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

342

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

361

const u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

364

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

404

u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

414

static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

419

u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

435

const u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

438

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

476

u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

487

static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

492

u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

511

const u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

516

u32 val = intel_de_read(display, ctl_reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

555

u32 *data = frame;

sys/dev/pci/drm/i915/display/intel_hdmi.c

563

static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

567

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

569

u32 mask;

sys/dev/pci/drm/i915/display/intel_hdmi.c

595

u32 intel_hdmi_infoframe_enable(unsigned int type)

sys/dev/pci/drm/i915/display/intel_hdmi.c

607

u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

612

u32 val, ret = 0;

sys/dev/pci/drm/i915/display/intel_hdmi.c

75

u32 enabled_bits;

sys/dev/pci/drm/i915/display/intel_hdmi.c

875

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

876

u32 port = VIDEO_DIP_PORT(encoder->port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

94

static u32 g4x_infoframe_index(unsigned int type)

sys/dev/pci/drm/i915/display/intel_hdmi.h

39

u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_hdmi.h

41

u32 intel_hdmi_infoframe_enable(unsigned int type);

sys/dev/pci/drm/i915/display/intel_hotplug.c

377

static u32 get_blocked_hpd_pin_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

380

u32 hpd_pin_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

395

u32 long_hpd_pin_mask, short_hpd_pin_mask;

sys/dev/pci/drm/i915/display/intel_hotplug.c

397

u32 blocked_hpd_pin_mask;

sys/dev/pci/drm/i915/display/intel_hotplug.c

398

u32 old_bits = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

475

u32 changed = 0, retry = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

476

u32 hpd_event_bits;

sys/dev/pci/drm/i915/display/intel_hotplug.c

477

u32 hpd_retry_bits;

sys/dev/pci/drm/i915/display/intel_hotplug.c

480

u32 blocked_hpd_pin_mask;

sys/dev/pci/drm/i915/display/intel_hotplug.c

508

u32 hpd_bit;

sys/dev/pci/drm/i915/display/intel_hotplug.c

588

u32 pin_mask, u32 long_mask)

sys/dev/pci/drm/i915/display/intel_hotplug.c

593

u32 long_hpd_pulse_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

594

u32 short_hpd_pulse_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

996

u32 blocked_hpd_pin_mask;

sys/dev/pci/drm/i915/display/intel_hotplug.h

23

u32 pin_mask, u32 long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

101

static const u32 hpd_xelpdp[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1035

u32 val = (INVERT_DDIA_HPD |

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1058

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1078

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

108

static const u32 hpd_icp[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1097

u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1117

u32 available_pins = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1137

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1154

static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1170

static u32 spt_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1175

static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1185

static u32 spt_hotplug2_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

120

static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1230

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1243

static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1254

static u32 ilk_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

128

static const u32 hpd_mtp[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1290

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1305

static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1319

static u32 bxt_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1321

u32 hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1362

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1385

u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1396

u32 hotplug_en;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

187

u32 mask, u32 bits)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

19

typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

20

typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

208

u32 mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

209

u32 bits)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

21

typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

216

static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

23

static const u32 hpd_ilk[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

231

static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

245

static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

258

static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

27

static const u32 hpd_ivb[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

273

static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

283

static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

299

static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

309

static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

31

static const u32 hpd_bdw[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

323

static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

345

u32 *pin_mask, u32 *long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

346

u32 hotplug_trigger, u32 dig_hotplug_reg,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

347

const u32 hpd[HPD_NUM_PINS],

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

348

bool long_pulse_detect(enum hpd_pin pin, u32 val))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

35

static const u32 hpd_ibx[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

369

static u32 intel_hpd_enabled_irqs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

370

const u32 hpd[HPD_NUM_PINS])

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

373

u32 enabled_irqs = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

382

static u32 intel_hpd_hotplug_irqs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

383

const u32 hpd[HPD_NUM_PINS])

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

386

u32 hotplug_irqs = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

394

static u32 intel_hpd_hotplug_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

398

u32 hotplug = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

406

static u32 intel_hpd_hotplug_enables(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

410

u32 hotplug = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

418

u32 i9xx_hpd_irq_ack(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

420

u32 hotplug_status = 0, hotplug_status_mask;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

43

static const u32 hpd_cpt[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

440

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

458

void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

460

u32 pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

461

u32 hotplug_trigger;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

484

void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

486

u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

496

u32 mask = PORTA_HOTPLUG_STATUS_MASK |

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

51

static const u32 hpd_spt[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

515

void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

518

u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

519

u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

520

u32 pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

526

u32 val;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

556

void icp_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

558

u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

559

u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

560

u32 pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

563

u32 dig_hotplug_reg;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

577

u32 dig_hotplug_reg;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

59

static const u32 hpd_mask_i915[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

594

void spt_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

596

u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

598

u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

599

u32 pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

602

u32 dig_hotplug_reg;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

613

u32 dig_hotplug_reg;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

630

void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

632

u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

644

void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

646

u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

658

void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

660

u32 pin_mask = 0, long_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

661

u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

662

u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

665

u32 dig_hotplug_reg;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

676

u32 dig_hotplug_reg;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

68

static const u32 hpd_status_g4x[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

693

static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

709

static u32 ibx_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

758

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

768

static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

77

static const u32 hpd_status_i915[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

781

static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

786

static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

801

static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

846

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

86

static const u32 hpd_bxt[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

863

static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

878

static u32 gen11_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

885

u32 val = (INVERT_DDIA_HPD |

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

92

static const u32 hpd_gen11[HPD_NUM_PINS] = {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

951

u32 hotplug_irqs, enabled_irqs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

967

static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

978

static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

983

static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

996

static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

14

u32 i9xx_hpd_irq_ack(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

16

void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

17

void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

18

void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

19

void gen11_hpd_irq_handler(struct intel_display *display, u32 iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

20

void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

21

void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

22

void icp_irq_handler(struct intel_display *display, u32 pch_iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

23

void spt_irq_handler(struct intel_display *display, u32 pch_iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

26

u32 mask, u32 bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

28

u32 mask, u32 bits);

sys/dev/pci/drm/i915/display/intel_hti.c

33

u32 intel_hti_dpll_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hti.h

16

u32 intel_hti_dpll_mask(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

358

u32 audio_enable;

sys/dev/pci/drm/i915/display/intel_lspcon.c

124

static u32 get_hdr_status_reg(struct intel_lspcon *lspcon)

sys/dev/pci/drm/i915/display/intel_lspcon.c

439

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_lspcon.c

440

u32 retry;

sys/dev/pci/drm/i915/display/intel_lspcon.c

615

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_lspcon.c

630

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_lspcon.c

642

u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_lspcon.c

649

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_lspcon.c

650

u32 mask, tmp;

sys/dev/pci/drm/i915/display/intel_lspcon.c

717

u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_lspcon.c

94

u32 vendor_oui;

sys/dev/pci/drm/i915/display/intel_lspcon.h

21

u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_lspcon.h

37

u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_lvds.c

127

u32 tmp, flags = 0;

sys/dev/pci/drm/i915/display/intel_lvds.c

160

u32 val;

sys/dev/pci/drm/i915/display/intel_lvds.c

214

u32 val;

sys/dev/pci/drm/i915/display/intel_lvds.c

248

u32 temp;

sys/dev/pci/drm/i915/display/intel_lvds.c

74

u32 a3_power;

sys/dev/pci/drm/i915/display/intel_lvds.c

77

u32 init_lvds_val;

sys/dev/pci/drm/i915/display/intel_lvds.c

850

u32 lvds;

sys/dev/pci/drm/i915/display/intel_lvds.c

90

u32 val;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

522

u32 crtcs_forced_off = 0;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

531

u32 old_mask = crtcs_forced_off;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

534

u32 crtc_mask = drm_crtc_mask(&crtc->base);

sys/dev/pci/drm/i915/display/intel_opregion.c

100

u32 cnot; /* current OS notification */

sys/dev/pci/drm/i915/display/intel_opregion.c

101

u32 nrdy; /* driver status */

sys/dev/pci/drm/i915/display/intel_opregion.c

102

u32 did2[7]; /* extended supported display devices ID list */

sys/dev/pci/drm/i915/display/intel_opregion.c

103

u32 cpd2[7]; /* extended attached display devices list */

sys/dev/pci/drm/i915/display/intel_opregion.c

109

u32 scic; /* SWSCI command|status|data */

sys/dev/pci/drm/i915/display/intel_opregion.c

1098

u32 panel_details;

sys/dev/pci/drm/i915/display/intel_opregion.c

110

u32 parm; /* command parameters */

sys/dev/pci/drm/i915/display/intel_opregion.c

111

u32 dslp; /* driver sleep time-out */

sys/dev/pci/drm/i915/display/intel_opregion.c

117

u32 ardy; /* driver readiness */

sys/dev/pci/drm/i915/display/intel_opregion.c

118

u32 aslc; /* ASLE interrupt command */

sys/dev/pci/drm/i915/display/intel_opregion.c

119

u32 tche; /* technology enabled indicator */

sys/dev/pci/drm/i915/display/intel_opregion.c

120

u32 alsi; /* current ALS illuminance reading */

sys/dev/pci/drm/i915/display/intel_opregion.c

121

u32 bclp; /* backlight brightness to set */

sys/dev/pci/drm/i915/display/intel_opregion.c

122

u32 pfit; /* panel fitting state */

sys/dev/pci/drm/i915/display/intel_opregion.c

123

u32 cblv; /* current brightness level */

sys/dev/pci/drm/i915/display/intel_opregion.c

125

u32 cpfm; /* current panel fitting mode */

sys/dev/pci/drm/i915/display/intel_opregion.c

126

u32 epfm; /* enabled panel fitting modes */

sys/dev/pci/drm/i915/display/intel_opregion.c

128

u32 pfmb; /* PWM freq and min brightness */

sys/dev/pci/drm/i915/display/intel_opregion.c

129

u32 cddv; /* color correction default values */

sys/dev/pci/drm/i915/display/intel_opregion.c

130

u32 pcft; /* power conservation features */

sys/dev/pci/drm/i915/display/intel_opregion.c

131

u32 srot; /* supported rotation angles */

sys/dev/pci/drm/i915/display/intel_opregion.c

132

u32 iuer; /* IUER events */

sys/dev/pci/drm/i915/display/intel_opregion.c

134

u32 fdsp;

sys/dev/pci/drm/i915/display/intel_opregion.c

135

u32 stat;

sys/dev/pci/drm/i915/display/intel_opregion.c

138

u32 rvds; /* Size of raw vbt data */

sys/dev/pci/drm/i915/display/intel_opregion.c

144

u32 phed; /* Panel Header */

sys/dev/pci/drm/i915/display/intel_opregion.c

265

u32 swsci_gbda_sub_functions;

sys/dev/pci/drm/i915/display/intel_opregion.c

266

u32 swsci_sbcb_sub_functions;

sys/dev/pci/drm/i915/display/intel_opregion.c

271

u32 vbt_size;

sys/dev/pci/drm/i915/display/intel_opregion.c

276

static int check_swsci_function(struct intel_display *display, u32 function)

sys/dev/pci/drm/i915/display/intel_opregion.c

280

u32 main_function, sub_function;

sys/dev/pci/drm/i915/display/intel_opregion.c

309

u32 function, u32 parm, u32 *parm_out)

sys/dev/pci/drm/i915/display/intel_opregion.c

313

u32 scic, dslp;

sys/dev/pci/drm/i915/display/intel_opregion.c

395

u32 parm = 0;

sys/dev/pci/drm/i915/display/intel_opregion.c

396

u32 type = 0;

sys/dev/pci/drm/i915/display/intel_opregion.c

397

u32 port;

sys/dev/pci/drm/i915/display/intel_opregion.c

467

u32 parm;

sys/dev/pci/drm/i915/display/intel_opregion.c

493

static u32 asle_set_backlight(struct intel_display *display, u32 bclp)

sys/dev/pci/drm/i915/display/intel_opregion.c

534

static u32 asle_set_als_illum(struct intel_display *display, u32 alsi)

sys/dev/pci/drm/i915/display/intel_opregion.c

542

static u32 asle_set_pwm_freq(struct intel_display *display, u32 pfmb)

sys/dev/pci/drm/i915/display/intel_opregion.c

548

static u32 asle_set_pfit(struct intel_display *display, u32 pfit)

sys/dev/pci/drm/i915/display/intel_opregion.c

556

static u32 asle_set_supported_rotation_angles(struct intel_display *display, u32 srot)

sys/dev/pci/drm/i915/display/intel_opregion.c

562

static u32 asle_set_button_array(struct intel_display *display, u32 iuer)

sys/dev/pci/drm/i915/display/intel_opregion.c

586

static u32 asle_set_convertible(struct intel_display *display, u32 iuer)

sys/dev/pci/drm/i915/display/intel_opregion.c

598

static u32 asle_set_docking(struct intel_display *display, u32 iuer)

sys/dev/pci/drm/i915/display/intel_opregion.c

609

static u32 asle_isct_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

621

u32 aslc_stat = 0;

sys/dev/pci/drm/i915/display/intel_opregion.c

622

u32 aslc_req;

sys/dev/pci/drm/i915/display/intel_opregion.c

66

u32 size;

sys/dev/pci/drm/i915/display/intel_opregion.c

718

static void set_did(struct intel_opregion *opregion, int i, u32 val)

sys/dev/pci/drm/i915/display/intel_opregion.c

76

u32 mboxes;

sys/dev/pci/drm/i915/display/intel_opregion.c

77

u32 driver_model;

sys/dev/pci/drm/i915/display/intel_opregion.c

78

u32 pcon;

sys/dev/pci/drm/i915/display/intel_opregion.c

807

u32 tmp;

sys/dev/pci/drm/i915/display/intel_opregion.c

838

u32 low = tmp & 0x7ff;

sys/dev/pci/drm/i915/display/intel_opregion.c

839

u32 high = tmp & ~0xfff; /* bit 11 is reserved */

sys/dev/pci/drm/i915/display/intel_opregion.c

844

u32 req = opregion->swsci_sbcb_sub_functions;

sys/dev/pci/drm/i915/display/intel_opregion.c

85

u32 drdy; /* driver readiness */

sys/dev/pci/drm/i915/display/intel_opregion.c

86

u32 csts; /* notification status */

sys/dev/pci/drm/i915/display/intel_opregion.c

87

u32 cevt; /* current event */

sys/dev/pci/drm/i915/display/intel_opregion.c

886

u32 asls, mboxes;

sys/dev/pci/drm/i915/display/intel_opregion.c

89

u32 didl[8]; /* supported display devices ID list */

sys/dev/pci/drm/i915/display/intel_opregion.c

891

u32 vbt_size;

sys/dev/pci/drm/i915/display/intel_opregion.c

90

u32 cpdl[8]; /* currently presented display list */

sys/dev/pci/drm/i915/display/intel_opregion.c

91

u32 cadl[8]; /* currently active display list */

sys/dev/pci/drm/i915/display/intel_opregion.c

92

u32 nadl[8]; /* next active devices list */

sys/dev/pci/drm/i915/display/intel_opregion.c

93

u32 aslp; /* ASL sleep time-out */

sys/dev/pci/drm/i915/display/intel_opregion.c

94

u32 tidx; /* toggle table index */

sys/dev/pci/drm/i915/display/intel_opregion.c

95

u32 chpd; /* current hotplug enable indicator */

sys/dev/pci/drm/i915/display/intel_opregion.c

96

u32 clid; /* current lid state*/

sys/dev/pci/drm/i915/display/intel_opregion.c

97

u32 cdck; /* current docking state */

sys/dev/pci/drm/i915/display/intel_opregion.c

98

u32 sxsw; /* Sx state resume */

sys/dev/pci/drm/i915/display/intel_opregion.c

99

u32 evts; /* ASL supported events */

sys/dev/pci/drm/i915/display/intel_overlay.c

1016

u32 stride_mask;

sys/dev/pci/drm/i915/display/intel_overlay.c

1018

u32 tmp;

sys/dev/pci/drm/i915/display/intel_overlay.c

1194

params->dst_y = (((u32)params->dst_y << 12) /

sys/dev/pci/drm/i915/display/intel_overlay.c

1197

params->dst_height = (((u32)params->dst_height << 12) /

sys/dev/pci/drm/i915/display/intel_overlay.c

1240

static bool check_gamma_bounds(u32 gamma1, u32 gamma2)

sys/dev/pci/drm/i915/display/intel_overlay.c

1255

static bool check_gamma5_errata(u32 gamma5)

sys/dev/pci/drm/i915/display/intel_overlay.c

136

u32 OBUF_0Y;

sys/dev/pci/drm/i915/display/intel_overlay.c

137

u32 OBUF_1Y;

sys/dev/pci/drm/i915/display/intel_overlay.c

138

u32 OBUF_0U;

sys/dev/pci/drm/i915/display/intel_overlay.c

139

u32 OBUF_0V;

sys/dev/pci/drm/i915/display/intel_overlay.c

140

u32 OBUF_1U;

sys/dev/pci/drm/i915/display/intel_overlay.c

141

u32 OBUF_1V;

sys/dev/pci/drm/i915/display/intel_overlay.c

142

u32 OSTRIDE;

sys/dev/pci/drm/i915/display/intel_overlay.c

143

u32 YRGB_VPH;

sys/dev/pci/drm/i915/display/intel_overlay.c

144

u32 UV_VPH;

sys/dev/pci/drm/i915/display/intel_overlay.c

145

u32 HORZ_PH;

sys/dev/pci/drm/i915/display/intel_overlay.c

146

u32 INIT_PHS;

sys/dev/pci/drm/i915/display/intel_overlay.c

147

u32 DWINPOS;

sys/dev/pci/drm/i915/display/intel_overlay.c

1477

u32 dovsta;

sys/dev/pci/drm/i915/display/intel_overlay.c

1478

u32 isr;

sys/dev/pci/drm/i915/display/intel_overlay.c

148

u32 DWINSZ;

sys/dev/pci/drm/i915/display/intel_overlay.c

149

u32 SWIDTH;

sys/dev/pci/drm/i915/display/intel_overlay.c

150

u32 SWIDTHSW;

sys/dev/pci/drm/i915/display/intel_overlay.c

151

u32 SHEIGHT;

sys/dev/pci/drm/i915/display/intel_overlay.c

152

u32 YRGBSCALE;

sys/dev/pci/drm/i915/display/intel_overlay.c

153

u32 UVSCALE;

sys/dev/pci/drm/i915/display/intel_overlay.c

154

u32 OCLRC0;

sys/dev/pci/drm/i915/display/intel_overlay.c

155

u32 OCLRC1;

sys/dev/pci/drm/i915/display/intel_overlay.c

156

u32 DCLRKV;

sys/dev/pci/drm/i915/display/intel_overlay.c

157

u32 DCLRKM;

sys/dev/pci/drm/i915/display/intel_overlay.c

158

u32 SCLRKVH;

sys/dev/pci/drm/i915/display/intel_overlay.c

159

u32 SCLRKVL;

sys/dev/pci/drm/i915/display/intel_overlay.c

160

u32 SCLRKEN;

sys/dev/pci/drm/i915/display/intel_overlay.c

161

u32 OCONFIG;

sys/dev/pci/drm/i915/display/intel_overlay.c

162

u32 OCMD;

sys/dev/pci/drm/i915/display/intel_overlay.c

163

u32 RESERVED1; /* 0x6C */

sys/dev/pci/drm/i915/display/intel_overlay.c

164

u32 OSTART_0Y;

sys/dev/pci/drm/i915/display/intel_overlay.c

165

u32 OSTART_1Y;

sys/dev/pci/drm/i915/display/intel_overlay.c

166

u32 OSTART_0U;

sys/dev/pci/drm/i915/display/intel_overlay.c

167

u32 OSTART_0V;

sys/dev/pci/drm/i915/display/intel_overlay.c

168

u32 OSTART_1U;

sys/dev/pci/drm/i915/display/intel_overlay.c

169

u32 OSTART_1V;

sys/dev/pci/drm/i915/display/intel_overlay.c

170

u32 OTILEOFF_0Y;

sys/dev/pci/drm/i915/display/intel_overlay.c

171

u32 OTILEOFF_1Y;

sys/dev/pci/drm/i915/display/intel_overlay.c

172

u32 OTILEOFF_0U;

sys/dev/pci/drm/i915/display/intel_overlay.c

173

u32 OTILEOFF_0V;

sys/dev/pci/drm/i915/display/intel_overlay.c

174

u32 OTILEOFF_1U;

sys/dev/pci/drm/i915/display/intel_overlay.c

175

u32 OTILEOFF_1V;

sys/dev/pci/drm/i915/display/intel_overlay.c

176

u32 FASTHSCALE; /* 0xA0 */

sys/dev/pci/drm/i915/display/intel_overlay.c

177

u32 UVSCALEV; /* 0xA4 */

sys/dev/pci/drm/i915/display/intel_overlay.c

178

u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */

sys/dev/pci/drm/i915/display/intel_overlay.c

198

u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */

sys/dev/pci/drm/i915/display/intel_overlay.c

199

u32 color_key:24;

sys/dev/pci/drm/i915/display/intel_overlay.c

200

u32 color_key_enabled:1;

sys/dev/pci/drm/i915/display/intel_overlay.c

201

u32 brightness, contrast, saturation;

sys/dev/pci/drm/i915/display/intel_overlay.c

202

u32 old_xscale, old_yscale;

sys/dev/pci/drm/i915/display/intel_overlay.c

206

u32 flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

261

u32 *cs;

sys/dev/pci/drm/i915/display/intel_overlay.c

326

u32 flip_addr = overlay->flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

327

u32 tmp, *cs;

sys/dev/pci/drm/i915/display/intel_overlay.c

408

u32 *cs, flip_addr = overlay->flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

466

u32 *cs;

sys/dev/pci/drm/i915/display/intel_overlay.c

512

static int packed_depth_bytes(u32 format)

sys/dev/pci/drm/i915/display/intel_overlay.c

524

static int packed_width_bytes(u32 format, short width)

sys/dev/pci/drm/i915/display/intel_overlay.c

534

static int uv_hsubsampling(u32 format)

sys/dev/pci/drm/i915/display/intel_overlay.c

548

static int uv_vsubsampling(u32 format)

sys/dev/pci/drm/i915/display/intel_overlay.c

562

static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width)

sys/dev/pci/drm/i915/display/intel_overlay.c

564

u32 sw;

sys/dev/pci/drm/i915/display/intel_overlay.c

629

u32 xscale, yscale, xscale_UV, yscale_UV;

sys/dev/pci/drm/i915/display/intel_overlay.c

689

u32 key = overlay->color_key;

sys/dev/pci/drm/i915/display/intel_overlay.c

690

u32 format = 0;

sys/dev/pci/drm/i915/display/intel_overlay.c

691

u32 flags = 0;

sys/dev/pci/drm/i915/display/intel_overlay.c

726

static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)

sys/dev/pci/drm/i915/display/intel_overlay.c

728

u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;

sys/dev/pci/drm/i915/display/intel_overlay.c

803

u32 swidth, swidthsw, sheight, ostride;

sys/dev/pci/drm/i915/display/intel_overlay.c

829

u32 oconfig = 0;

sys/dev/pci/drm/i915/display/intel_overlay.c

865

u32 tmp_U, tmp_V;

sys/dev/pci/drm/i915/display/intel_overlay.c

949

u32 ratio;

sys/dev/pci/drm/i915/display/intel_overlay.c

955

u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_overlay.c

960

u32 tmp;

sys/dev/pci/drm/i915/display/intel_overlay.c

996

u32 tmp;

sys/dev/pci/drm/i915/display/intel_panel.c

116

u32 sync_flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |

sys/dev/pci/drm/i915/display/intel_pch_display.c

108

u32 val;

sys/dev/pci/drm/i915/display/intel_pch_display.c

121

u32 val = intel_de_read(display, hdmi_reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

140

u32 val = intel_de_read(display, dp_reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

252

u32 val, pipeconf_val;

sys/dev/pci/drm/i915/display/intel_pch_display.c

368

u32 temp;

sys/dev/pci/drm/i915/display/intel_pch_display.c

380

u32 sel;

sys/dev/pci/drm/i915/display/intel_pch_display.c

419

u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))

sys/dev/pci/drm/i915/display/intel_pch_display.c

504

u32 tmp;

sys/dev/pci/drm/i915/display/intel_pch_display.c

551

u32 val, pipeconf_val;

sys/dev/pci/drm/i915/display/intel_pch_display.c

623

u32 tmp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

118

u32 temp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

132

u32 iclk_virtual_root_freq;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

133

u32 iclk_pi_range;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

134

u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

191

u32 temp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

242

u32 temp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

283

u32 reg, tmp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

321

u32 reg, tmp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

378

u32 tmp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

407

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

408

u32 ctl = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

42

u32 tmp;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

426

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

427

u32 ctl = intel_de_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

506

u32 val, final;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

541

u32 temp;

sys/dev/pci/drm/i915/display/intel_pfit.c

212

u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;

sys/dev/pci/drm/i915/display/intel_pfit.c

213

u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;

sys/dev/pci/drm/i915/display/intel_pfit.c

290

u32 border, sync_pos, blank_width, sync_width;

sys/dev/pci/drm/i915/display/intel_pfit.c

312

u32 border, sync_pos, blank_width, sync_width;

sys/dev/pci/drm/i915/display/intel_pfit.c

329

static u32 panel_fitter_scaling(u32 source, u32 target)

sys/dev/pci/drm/i915/display/intel_pfit.c

338

u32 ratio = source * FACTOR / target;

sys/dev/pci/drm/i915/display/intel_pfit.c

343

u32 *pfit_control)

sys/dev/pci/drm/i915/display/intel_pfit.c

349

u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;

sys/dev/pci/drm/i915/display/intel_pfit.c

350

u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;

sys/dev/pci/drm/i915/display/intel_pfit.c

364

u32 *pfit_control, u32 *pfit_pgm_ratios,

sys/dev/pci/drm/i915/display/intel_pfit.c

365

u32 *border)

sys/dev/pci/drm/i915/display/intel_pfit.c

370

u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;

sys/dev/pci/drm/i915/display/intel_pfit.c

371

u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;

sys/dev/pci/drm/i915/display/intel_pfit.c

372

u32 bits;

sys/dev/pci/drm/i915/display/intel_pfit.c

456

u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;

sys/dev/pci/drm/i915/display/intel_pfit.c

623

u32 ctl, pos, size;

sys/dev/pci/drm/i915/display/intel_pfit.c

710

u32 tmp;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

131

u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

173

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

198

u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

235

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

256

u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

339

u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

367

u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

409

enum intel_pipe_crc_source *source, u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

59

u32 *val)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

591

u32 val = 0; /* shut up gcc */

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

641

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

1057

u32 src_x, src_y, src_w, src_h, hsub, vsub;

sys/dev/pci/drm/i915/display/intel_plane.c

1290

u32 offset;

sys/dev/pci/drm/i915/display/intel_plane.c

1308

u32 offset;

sys/dev/pci/drm/i915/display/intel_plane.c

181

bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,

sys/dev/pci/drm/i915/display/intel_plane.c

192

u32 format,

sys/dev/pci/drm/i915/display/intel_plane.c

493

u32 old_ctl = old_plane_state->ctl;

sys/dev/pci/drm/i915/display/intel_plane.c

494

u32 new_ctl = new_plane_state->ctl;

sys/dev/pci/drm/i915/display/intel_plane.c

898

u32 update_mask = new_crtc_state->update_planes;

sys/dev/pci/drm/i915/display/intel_plane.c

933

u32 update_mask = new_crtc_state->update_planes;

sys/dev/pci/drm/i915/display/intel_plane.c

963

u32 update_mask = new_crtc_state->update_planes;

sys/dev/pci/drm/i915/display/intel_plane.h

24

bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,

sys/dev/pci/drm/i915/display/intel_plane.h

91

u32 format,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

134

u32 base, size;

sys/dev/pci/drm/i915/display/intel_plane_initial.c

79

u32 base;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

404

u32 reg1, reg2;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

461

u32 status;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

492

u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

519

u32 *reg1, u32 *reg2, bool serialized)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

540

u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \

sys/dev/pci/drm/i915/display/intel_pmdemand.c

541

u32 old_val = old ? old->params.field : 0; \

sys/dev/pci/drm/i915/display/intel_pmdemand.c

542

u32 new_val = new->params.field; \

sys/dev/pci/drm/i915/display/intel_pmdemand.c

578

u32 reg1, mod_reg1;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

579

u32 reg2, mod_reg2;

sys/dev/pci/drm/i915/display/intel_pps.c

103

u32 DP;

sys/dev/pci/drm/i915/display/intel_pps.c

1041

u32 pp;

sys/dev/pci/drm/i915/display/intel_pps.c

1109

u32 pp;

sys/dev/pci/drm/i915/display/intel_pps.c

1130

u32 pp;

sys/dev/pci/drm/i915/display/intel_pps.c

1392

u32 pp_on, pp_off, pp_ctl, power_cycle_delay;

sys/dev/pci/drm/i915/display/intel_pps.c

1413

u32 pp_div;

sys/dev/pci/drm/i915/display/intel_pps.c

1600

u32 pp_on, pp_off, port_sel = 0;

sys/dev/pci/drm/i915/display/intel_pps.c

1623

u32 pp = ilk_get_pp_control(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1843

u32 val;

sys/dev/pci/drm/i915/display/intel_pps.c

1851

u32 port_sel;

sys/dev/pci/drm/i915/display/intel_pps.c

1879

u32 port_sel;

sys/dev/pci/drm/i915/display/intel_pps.c

303

u32 port_sel = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_pps.c

607

u32 mask, u32 value)

sys/dev/pci/drm/i915/display/intel_pps.c

613

u32 val;

sys/dev/pci/drm/i915/display/intel_pps.c

724

static u32 ilk_get_pp_control(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_pps.c

727

u32 control;

sys/dev/pci/drm/i915/display/intel_pps.c

749

u32 pp;

sys/dev/pci/drm/i915/display/intel_pps.c

832

u32 pp;

sys/dev/pci/drm/i915/display/intel_pps.c

966

u32 pp;

sys/dev/pci/drm/i915/display/intel_psr.c

1011

u32 val = psr->su_region_et_enabled ?

sys/dev/pci/drm/i915/display/intel_psr.c

1033

u32 val = EDP_PSR2_ENABLE;

sys/dev/pci/drm/i915/display/intel_psr.c

1034

u32 psr_val = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

1104

u32 tmp;

sys/dev/pci/drm/i915/display/intel_psr.c

1139

static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_psr.c

1149

u32 idle_frames)

sys/dev/pci/drm/i915/display/intel_psr.c

1220

const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;

sys/dev/pci/drm/i915/display/intel_psr.c

1222

u32 exit_scanlines;

sys/dev/pci/drm/i915/display/intel_psr.c

1348

u32 hblank_total, hblank_ns, req_ns;

sys/dev/pci/drm/i915/display/intel_psr.c

1780

u32 val;

sys/dev/pci/drm/i915/display/intel_psr.c

1890

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

2012

u32 val;

sys/dev/pci/drm/i915/display/intel_psr.c

2043

u32 val;

sys/dev/pci/drm/i915/display/intel_psr.c

2112

u32 val;

sys/dev/pci/drm/i915/display/intel_psr.c

2161

u32 psr_status_mask;

sys/dev/pci/drm/i915/display/intel_psr.c

2448

static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2454

static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2461

static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2468

static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2539

u32 val = man_trk_ctl_enable_bit_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2569

static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_psr.c

272

static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

280

static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

288

static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

296

static u32 psr_irq_mask_get(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

2976

u32 val = man_trk_ctl_enable_bit_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

3194

u32 mask;

sys/dev/pci/drm/i915/display/intel_psr.c

3287

const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;

sys/dev/pci/drm/i915/display/intel_psr.c

3288

const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |

sys/dev/pci/drm/i915/display/intel_psr.c

3290

u32 old_mode, old_disable_bits;

sys/dev/pci/drm/i915/display/intel_psr.c

380

u32 mask;

sys/dev/pci/drm/i915/display/intel_psr.c

395

u32 val, bool sel_update_enabled)

sys/dev/pci/drm/i915/display/intel_psr.c

4014

u32 val, status_val;

sys/dev/pci/drm/i915/display/intel_psr.c

4115

u32 val, psr2_ctl;

sys/dev/pci/drm/i915/display/intel_psr.c

4174

u32 su_frames_val[3];

sys/dev/pci/drm/i915/display/intel_psr.c

4195

u32 su_blocks;

sys/dev/pci/drm/i915/display/intel_psr.c

432

void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)

sys/dev/pci/drm/i915/display/intel_psr.c

452

u32 val;

sys/dev/pci/drm/i915/display/intel_psr.c

707

u32 aux_clock_divider, aux_ctl;

sys/dev/pci/drm/i915/display/intel_psr.c

835

static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

839

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

908

u32 current_dc_state = intel_display_power_get_current_dc_state(display);

sys/dev/pci/drm/i915/display/intel_psr.c

922

u32 max_sleep_time = 0x1f;

sys/dev/pci/drm/i915/display/intel_psr.c

923

u32 val = EDP_PSR_ENABLE;

sys/dev/pci/drm/i915/display/intel_psr.c

956

static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

960

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_psr.h

52

void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);

sys/dev/pci/drm/i915/display/intel_sbi.c

18

u32 *val, bool is_read)

sys/dev/pci/drm/i915/display/intel_sbi.c

20

u32 cmd;

sys/dev/pci/drm/i915/display/intel_sbi.c

66

u32 intel_sbi_read(struct intel_display *display, u16 reg,

sys/dev/pci/drm/i915/display/intel_sbi.c

69

u32 result = 0;

sys/dev/pci/drm/i915/display/intel_sbi.c

76

void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,

sys/dev/pci/drm/i915/display/intel_sbi.h

22

u32 intel_sbi_read(struct intel_display *display, u16 reg,

sys/dev/pci/drm/i915/display/intel_sbi.h

24

void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1221

u32 format_map;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1536

u32 sdvox;

sys/dev/pci/drm/i915/display/intel_sdvo.c

161

u32 max_hscan, max_vscan;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1670

u32 val;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1708

u32 flags = 0, sdvox;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1842

u32 temp;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1905

u32 temp;

sys/dev/pci/drm/i915/display/intel_sdvo.c

214

static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)

sys/dev/pci/drm/i915/display/intel_sdvo.c

217

u32 bval = val, cval = val;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2306

u32 reply = 0, format_map = 0;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3073

u32 format_map, i;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3298

static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

131

static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

132

u32 ref_range,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

133

u32 ana_cp_int_gs,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

134

u32 ana_cp_prop_gs,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

139

u32 prescaler_divider,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

143

u32 ssc_up_spread = 1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

144

u32 mpll_div5_en = 1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

145

u32 hdmi_div = 1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

146

u32 ana_cp_int;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

147

u32 ana_cp_prop;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

148

u32 refclk_postscalar = refclk >> prescaler_divider;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

149

u32 tx_clk_div;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

152

u32 vco_div_refclk_integer;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

153

u32 vco_div_refclk_fracn;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

154

u32 fracn_quot;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

155

u32 fracn_rem;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

156

u32 fracn_den;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

157

u32 fracn_en;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

158

u32 pmix_en;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

159

u32 multiplier;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

23

u32 ssc_up_spread;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

24

u32 mpll_div5_en;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

25

u32 hdmi_div;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

252

u32 refclk = 100000000;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

253

u32 prescaler_divider = 1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

254

u32 ref_range = 3;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

255

u32 ana_cp_int_gs = 64;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

256

u32 ana_cp_prop_gs = 124;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

26

u32 ana_cp_int;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

27

u32 ana_cp_prop;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

28

u32 refclk_postscalar;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

29

u32 tx_clk_div;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

30

u32 fracn_quot;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

31

u32 fracn_rem;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

32

u32 fracn_den;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

323

u32 refclk = 38400000;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

324

u32 prescaler_divider = 0;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

325

u32 ref_range = 1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

326

u32 ana_cp_int_gs = 30;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

327

u32 ana_cp_prop_gs = 28;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

33

u32 fracn_en;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

34

u32 pmix_en;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

35

u32 multiplier;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

50

u32 refclk_postscalar,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

57

u32 *ana_cp_int,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

58

u32 *ana_cp_prop)

sys/dev/pci/drm/i915/display/intel_snps_phy.c

56

u32 val;

sys/dev/pci/drm/i915/display/intel_snps_phy.c

81

u32 val = 0;

sys/dev/pci/drm/i915/display/intel_sprite.c

1000

u32 dvscntr = 0;

sys/dev/pci/drm/i915/display/intel_sprite.c

1011

static u32 g4x_sprite_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/intel_sprite.c

1017

u32 dvscntr;

sys/dev/pci/drm/i915/display/intel_sprite.c

1146

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/intel_sprite.c

1147

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/intel_sprite.c

1148

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

sys/dev/pci/drm/i915/display/intel_sprite.c

1149

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

sys/dev/pci/drm/i915/display/intel_sprite.c

1150

u32 dvsscale = 0;

sys/dev/pci/drm/i915/display/intel_sprite.c

1175

u32 x = plane_state->view.color_plane[0].x;

sys/dev/pci/drm/i915/display/intel_sprite.c

1176

u32 y = plane_state->view.color_plane[0].y;

sys/dev/pci/drm/i915/display/intel_sprite.c

1177

u32 dvscntr;

sys/dev/pci/drm/i915/display/intel_sprite.c

1435

static const u32 g4x_sprite_formats[] = {

sys/dev/pci/drm/i915/display/intel_sprite.c

1443

static const u32 snb_sprite_formats[] = {

sys/dev/pci/drm/i915/display/intel_sprite.c

1456

static const u32 vlv_sprite_formats[] = {

sys/dev/pci/drm/i915/display/intel_sprite.c

1471

static const u32 chv_pipe_b_sprite_formats[] = {

sys/dev/pci/drm/i915/display/intel_sprite.c

1489

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_sprite.c

1510

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_sprite.c

1536

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_sprite.c

1600

const u32 *formats;

sys/dev/pci/drm/i915/display/intel_sprite.c

257

static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_sprite.c

259

u32 sprctl = 0;

sys/dev/pci/drm/i915/display/intel_sprite.c

267

static u32 vlv_sprite_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/intel_sprite.c

272

u32 sprctl;

sys/dev/pci/drm/i915/display/intel_sprite.c

376

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/intel_sprite.c

377

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/intel_sprite.c

397

u32 x = plane_state->view.color_plane[0].x;

sys/dev/pci/drm/i915/display/intel_sprite.c

398

u32 y = plane_state->view.color_plane[0].y;

sys/dev/pci/drm/i915/display/intel_sprite.c

399

u32 sprctl;

sys/dev/pci/drm/i915/display/intel_sprite.c

640

static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_sprite.c

642

u32 sprctl = 0;

sys/dev/pci/drm/i915/display/intel_sprite.c

662

static u32 ivb_sprite_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/intel_sprite.c

668

u32 sprctl;

sys/dev/pci/drm/i915/display/intel_sprite.c

798

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/intel_sprite.c

799

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/intel_sprite.c

800

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

sys/dev/pci/drm/i915/display/intel_sprite.c

801

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

sys/dev/pci/drm/i915/display/intel_sprite.c

802

u32 sprscale = 0;

sys/dev/pci/drm/i915/display/intel_sprite.c

828

u32 x = plane_state->view.color_plane[0].x;

sys/dev/pci/drm/i915/display/intel_sprite.c

829

u32 y = plane_state->view.color_plane[0].y;

sys/dev/pci/drm/i915/display/intel_sprite.c

830

u32 sprctl;

sys/dev/pci/drm/i915/display/intel_sprite.c

961

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_sprite.c

976

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_sprite.c

998

static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_tc.c

1011

static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc)

sys/dev/pci/drm/i915/display/intel_tc.c

1016

u32 pica_isr_bits = display->hotplug.hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

1017

u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

1019

u32 pica_isr;

sys/dev/pci/drm/i915/display/intel_tc.c

1020

u32 pch_isr;

sys/dev/pci/drm/i915/display/intel_tc.c

1021

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

1105

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

1152

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

1272

static u32 tc_phy_hpd_live_status(struct intel_tc_port *tc)

sys/dev/pci/drm/i915/display/intel_tc.c

1275

u32 mask;

sys/dev/pci/drm/i915/display/intel_tc.c

1359

hpd_mask_to_tc_mode(u32 live_status_mask)

sys/dev/pci/drm/i915/display/intel_tc.c

1370

u32 live_status_mask = tc_phy_hpd_live_status(tc);

sys/dev/pci/drm/i915/display/intel_tc.c

1463

hpd_mask_to_target_mode(struct intel_tc_port *tc, u32 live_status_mask)

sys/dev/pci/drm/i915/display/intel_tc.c

1476

u32 live_status_mask = tc_phy_hpd_live_status(tc);

sys/dev/pci/drm/i915/display/intel_tc.c

1484

u32 live_status_mask = tc_phy_hpd_live_status(tc);

sys/dev/pci/drm/i915/display/intel_tc.c

1721

u32 mask = ~0;

sys/dev/pci/drm/i915/display/intel_tc.c

269

static u32 get_lane_mask(struct intel_tc_port *tc)

sys/dev/pci/drm/i915/display/intel_tc.c

273

u32 lane_mask;

sys/dev/pci/drm/i915/display/intel_tc.c

301

u32 mask;

sys/dev/pci/drm/i915/display/intel_tc.c

302

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

363

u32 lane_mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

39

u32 (*hpd_live_status)(struct intel_tc_port *tc);

sys/dev/pci/drm/i915/display/intel_tc.c

430

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

465

u32 live_status_mask)

sys/dev/pci/drm/i915/display/intel_tc.c

468

u32 valid_hpd_mask;

sys/dev/pci/drm/i915/display/intel_tc.c

525

static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc)

sys/dev/pci/drm/i915/display/intel_tc.c

529

u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

531

u32 fia_isr;

sys/dev/pci/drm/i915/display/intel_tc.c

532

u32 pch_isr;

sys/dev/pci/drm/i915/display/intel_tc.c

533

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

569

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

588

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

613

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

73

static u32 tc_phy_hpd_live_status(struct intel_tc_port *tc);

sys/dev/pci/drm/i915/display/intel_tc.c

778

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

815

static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc)

sys/dev/pci/drm/i915/display/intel_tc.c

820

u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

821

u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

823

u32 cpu_isr;

sys/dev/pci/drm/i915/display/intel_tc.c

824

u32 pch_isr;

sys/dev/pci/drm/i915/display/intel_tc.c

825

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

854

u32 val;

sys/dev/pci/drm/i915/display/intel_tc.c

887

u32 val;

sys/dev/pci/drm/i915/display/intel_tv.c

1098

u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;

sys/dev/pci/drm/i915/display/intel_tv.c

1361

u32 hctl1, hctl2, hctl3;

sys/dev/pci/drm/i915/display/intel_tv.c

1362

u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;

sys/dev/pci/drm/i915/display/intel_tv.c

1443

u32 tv_ctl, tv_filter_ctl;

sys/dev/pci/drm/i915/display/intel_tv.c

1444

u32 scctl1, scctl2, scctl3;

sys/dev/pci/drm/i915/display/intel_tv.c

1588

u32 tv_ctl, save_tv_ctl;

sys/dev/pci/drm/i915/display/intel_tv.c

1589

u32 tv_dac, save_tv_dac;

sys/dev/pci/drm/i915/display/intel_tv.c

1936

u32 tv_dac_on, tv_dac_off, save_tv_dac;

sys/dev/pci/drm/i915/display/intel_tv.c

319

u32 clock;

sys/dev/pci/drm/i915/display/intel_tv.c

346

u32 sc_reset;

sys/dev/pci/drm/i915/display/intel_tv.c

353

const u32 *filter_table;

sys/dev/pci/drm/i915/display/intel_tv.c

74

static const u32 filter_table[] = {

sys/dev/pci/drm/i915/display/intel_tv.c

919

u32 tmp = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_vblank.c

125

u32 g4x_get_vblank_counter(struct drm_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_vblank.c

137

static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_vblank.c

142

u32 htotal = mode->crtc_htotal;

sys/dev/pci/drm/i915/display/intel_vblank.c

143

u32 clock = mode->crtc_clock;

sys/dev/pci/drm/i915/display/intel_vblank.c

144

u32 scan_prev_time, scan_curr_time, scan_post_time;

sys/dev/pci/drm/i915/display/intel_vblank.c

183

static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_vblank.c

187

u32 vblank_start = mode->crtc_vblank_start;

sys/dev/pci/drm/i915/display/intel_vblank.c

188

u32 vtotal = mode->crtc_vtotal;

sys/dev/pci/drm/i915/display/intel_vblank.c

189

u32 scanline;

sys/dev/pci/drm/i915/display/intel_vblank.c

485

u32 line1, line2;

sys/dev/pci/drm/i915/display/intel_vblank.c

73

u32 i915_get_vblank_counter(struct drm_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_vblank.c

79

u32 pixel, vbl_start, hsync_start, htotal;

sys/dev/pci/drm/i915/display/intel_vblank.h

36

u32 i915_get_vblank_counter(struct drm_crtc *crtc);

sys/dev/pci/drm/i915/display/intel_vblank.h

37

u32 g4x_get_vblank_counter(struct drm_crtc *crtc);

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

104

u32 bdb_offset;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

105

u32 aim_offset[4];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1080

u32 panel_oui;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1081

u32 dpcd_base_address;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1082

u32 dpcd_idridix_control_0;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1083

u32 dpcd_option_select;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1084

u32 dpcd_backlight;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1085

u32 ambient_light;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1086

u32 backlight_scale;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1091

u32 color_depth;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1093

u32 sdrrs_msa_timing_delay;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1204

u32 lvds_panel_channel_bits;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1212

u32 dps_panel_type_bits;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1214

u32 blt_control_type_bits; /* ???-240 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1217

u32 rotation; /* 228+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1218

u32 position; /* 240+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1250

u32 lvds_reg;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1251

u32 lvds_reg_val;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1252

u32 pp_on_reg;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1253

u32 pp_on_reg_val;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1254

u32 pp_off_reg;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1255

u32 pp_off_reg_val;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1256

u32 pp_cycle_reg;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1257

u32 pp_cycle_reg_val;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1258

u32 pfit_reg;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1259

u32 pfit_reg_val;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1473

u32 dithering:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1474

u32 pixel_format_18bpp:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1475

u32 reserved1:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1476

u32 dphy_params_valid:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1477

u32 reserved2:28;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1489

u32 dsi_ddr_clock;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1490

u32 renesas_bridge_ref_clock;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1493

u32 prepare_count:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1494

u32 reserved6:3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1495

u32 clk_zero_count:8;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1496

u32 trail_count:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1497

u32 reserved7:3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1498

u32 exit_zero_count:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1499

u32 reserved8:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1501

u32 high_low_switch_count;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1502

u32 lp_byte_clock;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1503

u32 clock_lane_switch_time_counter;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1504

u32 panel_color_depth;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1517

u32 x_res;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1518

u32 y_res;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1579

u32 slices_per_line;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1612

u32 tables[];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1620

u32 pixel_clock;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

46

u32 serial;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

566

u32 edp_data_rate_override:12; /* 263+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

567

u32 edp_data_rate_override_reserved:20; /* 263+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

635

u32 dotclock_khz;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

692

u32 dotclock;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

730

u32 psr2_tp2_tp3_wakeup_time; /* 226+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

858

u32 dotclock;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

909

u32 rotation_flags_3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

910

u32 rotation_flags_4;

sys/dev/pci/drm/i915/display/intel_vdsc.c

1010

u32 dss_ctl1, dss_ctl2;

sys/dev/pci/drm/i915/display/intel_vdsc.c

437

int pps, u32 pps_val)

sys/dev/pci/drm/i915/display/intel_vdsc.c

461

u32 pps_val;

sys/dev/pci/drm/i915/display/intel_vdsc.c

462

u32 rc_buf_thresh_dword[4];

sys/dev/pci/drm/i915/display/intel_vdsc.c

463

u32 rc_range_params_dword[8];

sys/dev/pci/drm/i915/display/intel_vdsc.c

566

(u32)(vdsc_cfg->rc_buf_thresh[i] <<

sys/dev/pci/drm/i915/display/intel_vdsc.c

616

(u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<

sys/dev/pci/drm/i915/display/intel_vdsc.c

763

u32 val;

sys/dev/pci/drm/i915/display/intel_vdsc.c

793

u32 dss_ctl1_val = 0;

sys/dev/pci/drm/i915/display/intel_vdsc.c

810

u32 dss_ctl1_val = 0;

sys/dev/pci/drm/i915/display/intel_vdsc.c

811

u32 dss_ctl2_val = 0;

sys/dev/pci/drm/i915/display/intel_vdsc.c

859

static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,

sys/dev/pci/drm/i915/display/intel_vdsc.c

865

u32 val;

sys/dev/pci/drm/i915/display/intel_vdsc.c

888

static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)

sys/dev/pci/drm/i915/display/intel_vdsc.c

891

u32 val;

sys/dev/pci/drm/i915/display/intel_vdsc.c

905

u32 pps_temp;

sys/dev/pci/drm/i915/display/intel_vdsc.c

93

u32 buf_i, bpp_i;

sys/dev/pci/drm/i915/display/intel_vga.c

50

u32 tmp;

sys/dev/pci/drm/i915/display/intel_vrr.c

443

static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_vrr.c

722

u32 trans_vrr_ctl, trans_vrr_vsync;

sys/dev/pci/drm/i915/display/intel_wm_types.h

19

u32 wm_pipe[3];

sys/dev/pci/drm/i915/display/intel_wm_types.h

20

u32 wm_lp[3];

sys/dev/pci/drm/i915/display/intel_wm_types.h

21

u32 wm_lp_spr[3];

sys/dev/pci/drm/i915/display/skl_scaler.c

386

u32 mode;

sys/dev/pci/drm/i915/display/skl_scaler.c

697

u32 tmp;

sys/dev/pci/drm/i915/display/skl_scaler.c

714

static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter)

sys/dev/pci/drm/i915/display/skl_scaler.c

757

u32 ps_ctrl;

sys/dev/pci/drm/i915/display/skl_scaler.c

815

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/skl_scaler.c

816

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

sys/dev/pci/drm/i915/display/skl_scaler.c

820

u32 ps_ctrl;

sys/dev/pci/drm/i915/display/skl_scaler.c

917

u32 ctl, pos, size;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1006

static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1024

static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1042

static u32 skl_plane_ctl_tiling(u64 fb_modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1094

static u32 skl_plane_ctl_rotate(unsigned int rotate)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1116

static u32 icl_plane_ctl_flip(unsigned int reflect)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

113

static const u32 icl_sdr_uv_plane_formats[] = {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1131

static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1154

static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1157

u32 plane_ctl = 0;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1171

static u32 skl_plane_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1177

u32 plane_ctl;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1212

static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1215

u32 plane_color_ctl = 0;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1229

static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1234

u32 plane_color_ctl = 0;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1266

static u32 skl_surf_address(const struct intel_plane_state *plane_state,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1271

u32 offset = plane_state->view.color_plane[color_plane].offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1290

static u32 skl_plane_surf_offset(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1293

u32 plane_surf;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1303

u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1309

u32 aux_dist;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1323

static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1330

static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1338

static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1342

u32 keymsk;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1386

u32 stride = skl_plane_stride(plane_state, 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1389

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

139

static const u32 icl_hdr_plane_formats[] = {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1390

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1417

u32 x = plane_state->view.color_plane[0].x;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1418

u32 y = plane_state->view.color_plane[0].y;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1419

u32 plane_ctl, plane_color_ctl = 0;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1484

u32 val;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1531

u32 stride = skl_plane_stride(plane_state, color_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1539

u32 plane_color_ctl;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1628

u32 plane_ctl;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1677

u32 plane_ctl = plane_state->ctl;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1678

u32 plane_surf = plane_state->surf;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1695

static bool intel_format_is_p01x(u32 format)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1911

int main_x, int main_y, u32 main_offset,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1918

u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1956

int *x, int *y, u32 *offset)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1962

u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2022

u32 offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2095

u32 offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2111

u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2158

u32 offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2451

static const u32 *skl_get_plane_formats(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2464

static const u32 *glk_get_plane_formats(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2477

static const u32 *icl_get_plane_formats(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2494

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2548

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2602

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2790

u32 plane_ctl;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2799

u32 stride = state->view.color_plane[0].scanout_stride / 64;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2821

const u32 *formats;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3013

u32 val, base, offset, stride_mult, tiling, alpha;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3050

u32 color_ctl;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3090

u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |

sys/dev/pci/drm/i915/display/skl_universal_plane.c

32

static const u32 skl_plane_formats[] = {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

475

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

491

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

50

static const u32 skl_planar_formats[] = {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

504

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

588

static u32 tgl_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

637

static u32 skl_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

69

static const u32 glk_planar_formats[] = {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

773

static u32 skl_plane_stride(const struct intel_plane_state *plane_state,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

778

u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

786

static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

795

static u32 xe3_plane_min_ddb_reg_val(const u16 *min_ddb,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

798

u32 val = 0;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

811

static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

813

u32 val = 0;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

91

static const u32 icl_sdr_y_plane_formats[] = {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

944

static u32 skl_plane_ctl_format(u32 pixel_format)

sys/dev/pci/drm/i915/display/skl_universal_plane.h

33

int *x, int *y, u32 *offset);

sys/dev/pci/drm/i915/display/skl_universal_plane.h

43

u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,

sys/dev/pci/drm/i915/display/skl_watermark.c

102

static u32

sys/dev/pci/drm/i915/display/skl_watermark.c

106

u32 val;

sys/dev/pci/drm/i915/display/skl_watermark.c

112

u32 val = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

1424

u32 blocks;

sys/dev/pci/drm/i915/display/skl_watermark.c

1604

skl_wm_method1(struct intel_display *display, u32 pixel_rate,

sys/dev/pci/drm/i915/display/skl_watermark.c

1605

u8 cpp, u32 latency, u32 dbuf_block_size)

sys/dev/pci/drm/i915/display/skl_watermark.c

1607

u32 wm_intermediate_val;

sys/dev/pci/drm/i915/display/skl_watermark.c

1623

skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,

sys/dev/pci/drm/i915/display/skl_watermark.c

1626

u32 wm_intermediate_val;

sys/dev/pci/drm/i915/display/skl_watermark.c

1643

u32 pixel_rate;

sys/dev/pci/drm/i915/display/skl_watermark.c

1644

u32 crtc_htotal;

sys/dev/pci/drm/i915/display/skl_watermark.c

1665

u32 plane_pixel_rate, struct skl_wm_params *wp,

sys/dev/pci/drm/i915/display/skl_watermark.c

1669

u32 interm_pbpl;

sys/dev/pci/drm/i915/display/skl_watermark.c

1809

u32 blocks, lines, min_ddb_alloc = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

2189

u32 dsc_prefill_latency = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

2998

u32 val, struct skl_wm_level *level)

sys/dev/pci/drm/i915/display/skl_watermark.c

3015

u32 val;

sys/dev/pci/drm/i915/display/skl_watermark.c

3224

u32 val;

sys/dev/pci/drm/i915/display/skl_watermark.c

3246

u32 val;

sys/dev/pci/drm/i915/display/skl_watermark.c

3361

static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc,

sys/dev/pci/drm/i915/display/skl_watermark.c

3365

u32 val = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3520

u32 mbus_ctl;

sys/dev/pci/drm/i915/display/skl_watermark.c

443

u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

535

u32 ddb_range_size;

sys/dev/pci/drm/i915/display/skl_watermark.c

536

u32 dbuf_slice_mask;

sys/dev/pci/drm/i915/display/skl_watermark.c

537

u32 start, end;

sys/dev/pci/drm/i915/display/skl_watermark.c

596

u32 plane_pixel_rate, struct skl_wm_params *wp,

sys/dev/pci/drm/i915/display/skl_watermark.c

63

u32 width;

sys/dev/pci/drm/i915/display/skl_watermark.c

65

u32 plane_pixel_rate;

sys/dev/pci/drm/i915/display/skl_watermark.c

66

u32 y_min_scanlines;

sys/dev/pci/drm/i915/display/skl_watermark.c

660

static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)

sys/dev/pci/drm/i915/display/skl_watermark.c

67

u32 plane_bytes_per_line;

sys/dev/pci/drm/i915/display/skl_watermark.c

677

u32 val;

sys/dev/pci/drm/i915/display/skl_watermark.c

70

u32 linetime_us;

sys/dev/pci/drm/i915/display/skl_watermark.c

71

u32 dbuf_block_size;

sys/dev/pci/drm/i915/display/skl_watermark.h

30

u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

104

const u8 *data, u32 len)

sys/dev/pci/drm/i915/display/vlv_dsi.c

106

u32 i, j;

sys/dev/pci/drm/i915/display/vlv_dsi.c

109

u32 val = 0;

sys/dev/pci/drm/i915/display/vlv_dsi.c

111

for (j = 0; j < min_t(u32, len - i, 4); j++)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1180

u32 pclk;

sys/dev/pci/drm/i915/display/vlv_dsi.c

120

u8 *data, u32 len)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1202

static u16 txclkesc(u32 divider, unsigned int us)

sys/dev/pci/drm/i915/display/vlv_dsi.c

122

u32 i, j;

sys/dev/pci/drm/i915/display/vlv_dsi.c

125

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/vlv_dsi.c

127

for (j = 0; j < min_t(u32, len - i, 4); j++)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1286

static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1312

u32 val, tmp;

sys/dev/pci/drm/i915/display/vlv_dsi.c

143

u32 data_mask, ctrl_mask;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1480

u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1597

u32 tlpx_ns, extra_byte_count, tlpx_ui;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1598

u32 ui_num, ui_den;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1599

u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1600

u32 ths_prepare_ns, tclk_trail_ns;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1601

u32 tclk_prepare_clkzero, ths_prepare_hszero;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1602

u32 lp_to_hs_switch, hs_to_lp_switch;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1603

u32 mul;

sys/dev/pci/drm/i915/display/vlv_dsi.c

226

static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,

sys/dev/pci/drm/i915/display/vlv_dsi.c

230

u32 mask;

sys/dev/pci/drm/i915/display/vlv_dsi.c

347

u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

436

u32 val;

sys/dev/pci/drm/i915/display/vlv_dsi.c

620

u32 temp = intel_dsi->pixel_overlap;

sys/dev/pci/drm/i915/display/vlv_dsi.c

636

u32 temp;

sys/dev/pci/drm/i915/display/vlv_dsi.c

72

static enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)

sys/dev/pci/drm/i915/display/vlv_dsi.c

92

u32 mask;

sys/dev/pci/drm/i915/display/vlv_dsi.c

976

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

988

u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

113

(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

124

u32 dsi_clock;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

125

u32 pll_ctl, pll_div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

126

u32 m = 0, p = 0, n;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

217

u32 val;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

252

u32 tmp;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

274

u32 val;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

275

u32 mask;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

328

u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

332

u32 pll_ctl, pll_div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

352

u32 dsi_ratio, dsi_clk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

360

u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

364

u32 pclk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

380

u32 temp;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

391

u32 dsi_rate = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

392

u32 pll_ratio = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

393

u32 ddr_clk = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

394

u32 div1_value = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

395

u32 div2_value = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

396

u32 txesc1_div = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

397

u32 txesc2_div = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

425

txesc2_div = min_t(u32, div2_value, 10);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

437

u32 tmp;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

438

u32 dsi_rate = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

439

u32 pll_ratio = 0;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

440

u32 rx_div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

441

u32 tx_div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

442

u32 rx_div_upper;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

443

u32 rx_div_lower;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

444

u32 mipi_8by3_divider;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

49

static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

492

u32 dsi_clk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

52

u32 dsi_clk_khz;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

53

u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

584

u32 tmp;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

21

u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

30

u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/vlv_sideband.c

24

u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg)

sys/dev/pci/drm/i915/display/vlv_sideband.c

28

u32 val;

sys/dev/pci/drm/i915/display/vlv_sideband.c

44

enum dpio_phy phy, int reg, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.h

106

static inline u32 vlv_flisdsi_read(struct drm_device *drm, u32 reg)

sys/dev/pci/drm/i915/display/vlv_sideband.h

111

static inline void vlv_flisdsi_write(struct drm_device *drm, u32 reg, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.h

126

static inline u32 vlv_nc_read(struct drm_device *drm, u8 addr)

sys/dev/pci/drm/i915/display/vlv_sideband.h

141

static inline u32 vlv_punit_read(struct drm_device *drm, u32 addr)

sys/dev/pci/drm/i915/display/vlv_sideband.h

146

static inline int vlv_punit_write(struct drm_device *drm, u32 addr, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.h

21

static inline u32 vlv_bunit_read(struct drm_device *drm, u32 reg)

sys/dev/pci/drm/i915/display/vlv_sideband.h

26

static inline void vlv_bunit_write(struct drm_device *drm, u32 reg, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.h

41

static inline u32 vlv_cck_read(struct drm_device *drm, u32 reg)

sys/dev/pci/drm/i915/display/vlv_sideband.h

46

static inline void vlv_cck_write(struct drm_device *drm, u32 reg, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.h

61

static inline u32 vlv_ccu_read(struct drm_device *drm, u32 reg)

sys/dev/pci/drm/i915/display/vlv_sideband.h

66

static inline void vlv_ccu_write(struct drm_device *drm, u32 reg, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.h

82

u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg);

sys/dev/pci/drm/i915/display/vlv_sideband.h

84

enum dpio_phy phy, int reg, u32 val);

sys/dev/pci/drm/i915/display/vlv_sideband.h

86

static inline u32 vlv_dpio_read(struct drm_device *drm, int phy, int reg)

sys/dev/pci/drm/i915/display/vlv_sideband.h

91

int phy, int reg, u32 val)

sys/dev/pci/drm/i915/gem/i915_gem_busy.c

13

static __always_inline u32 __busy_read_flag(u16 id)

sys/dev/pci/drm/i915/gem/i915_gem_busy.c

22

static __always_inline u32 __busy_write_id(u16 id)

sys/dev/pci/drm/i915/gem/i915_gem_busy.c

40

__busy_set_if_active(struct dma_fence *fence, u32 (*flag)(u16 id))

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1738

u32 id)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1843

u32 id;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1906

u32 id;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2325

__context_lookup(struct drm_i915_file_private *file_priv, u32 id)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2340

struct i915_gem_proto_context *pc, u32 id)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2370

i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2401

u32 id;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

325

u32 *id)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

348

u32 *id)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

360

i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)

sys/dev/pci/drm/i915/gem/i915_gem_context.h

142

i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id);

sys/dev/pci/drm/i915/gem/i915_gem_create.c

176

u32 format;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

19

static u32 object_max_page_size(struct intel_memory_region **placements,

sys/dev/pci/drm/i915/gem/i915_gem_create.c

22

u32 max_page_size = 0;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

280

u32 mask;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

29

max_page_size = max_t(u32, max_page_size, mr->min_page_size);

sys/dev/pci/drm/i915/gem/i915_gem_create.c

75

u32 *handle_p)

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

423

u32 alignment, unsigned int guard,

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

542

u32 read_domains = args->read_domains;

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

543

u32 write_domain = args->write_domain;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1353

static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1392

GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1398

offset += sizeof(u32);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2207

u32 *cs;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

300

u32 batch_start_offset; /** Location within object of batch */

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

301

u32 batch_flags; /** Flags composed for emit_bb_start() */

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

45

u32 handle;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

838

u32 handle, struct i915_vma *vma)

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

887

static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

1200

u32 handle,

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

1224

u32 handle,

sys/dev/pci/drm/i915/gem/i915_gem_mman.h

30

u32 handle, u64 *offset);

sys/dev/pci/drm/i915/gem/i915_gem_object.h

116

i915_gem_object_lookup(struct drm_file *file, u32 handle)

sys/dev/pci/drm/i915/gem/i915_gem_object.h

130

drm_gem_object_lookup(struct drm_file *file, u32 handle);

sys/dev/pci/drm/i915/gem/i915_gem_object.h

785

u32 alignment, unsigned int guard,

sys/dev/pci/drm/i915/gem/i915_gem_object.h

98

i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle)

sys/dev/pci/drm/i915/gem/i915_gem_object_types.h

34

u32 handle;

sys/dev/pci/drm/i915/gem/i915_gem_object_types.h

695

u32 tlb[I915_MAX_GT];

sys/dev/pci/drm/i915/gem/i915_gem_object_types.h

710

u32 pxp_key_instance;

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

396

unsigned int y, u32 color)

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

401

iosys_map_wr(&sb->map[0], offset, u32, color);

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

410

unsigned int y, u32 color)

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

431

u32 *pix = panic->vaddr + offset;

sys/dev/pci/drm/i915/gem/i915_gem_pm.c

54

static int lmem_restore(struct drm_i915_private *i915, u32 flags)

sys/dev/pci/drm/i915/gem/i915_gem_pm.c

70

static int lmem_suspend(struct drm_i915_private *i915, u32 flags)

sys/dev/pci/drm/i915/gem/i915_gem_region.c

64

GEM_BUG_ON(overflows_type(default_page_size, u32));

sys/dev/pci/drm/i915/gem/i915_gem_region.h

47

u32 interruptible:1;

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

209

u32 reg_val = intel_uncore_read(uncore,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

244

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

277

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

306

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

333

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

366

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

164

u32 size, alignment;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

54

u32 i915_gem_fence_size(struct drm_i915_private *i915,

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

55

u32 size, unsigned int tiling, unsigned int stride)

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

57

u32 ggtt_size;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

94

u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,

sys/dev/pci/drm/i915/gem/i915_gem_tiling.h

15

u32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size,

sys/dev/pci/drm/i915/gem/i915_gem_tiling.h

17

u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

595

u32 page_alignment;

sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.c

154

int i915_ttm_backup_region(struct intel_memory_region *mr, u32 flags)

sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.c

221

int i915_ttm_restore_region(struct intel_memory_region *mr, u32 flags)

sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.h

17

int i915_ttm_backup_region(struct intel_memory_region *mr, u32 flags);

sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.h

21

int i915_ttm_restore_region(struct intel_memory_region *mr, u32 flags);

sys/dev/pci/drm/i915/gem/i915_gem_userptr.c

472

u32 __maybe_unused handle;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1057

u32 dw,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1058

u32 val)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1068

return igt_gpu_fill_dw(ce, vma, dw * sizeof(u32),

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1073

__cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1085

u32 *ptr = kmap_local_page(i915_gem_object_get_page(obj, n));

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1108

static int __cpu_check_vmap(struct drm_i915_gem_object *obj, u32 dword, u32 val)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1111

u32 *ptr;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1138

static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1149

u32 dword, u32 val)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1267

u32 dword = offset_in_page(num) / 4;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1323

igt_create_shmem(struct drm_i915_private *i915, u32 size, u32 flags)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1334

igt_create_internal(struct drm_i915_private *i915, u32 size, u32 flags)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1340

igt_create_system(struct drm_i915_private *i915, u32 size, u32 flags)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1346

igt_create_local(struct drm_i915_private *i915, u32 size, u32 flags)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1351

static u32 igt_random_size(struct rnd_state *prng,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1352

u32 min_page_size,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1353

u32 max_page_size)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1356

u32 size;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1378

u32 min;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1379

u32 max;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1394

u32 min = backends[i].min;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1395

u32 max = backends[i].max;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1396

u32 size = max;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1470

u32 size;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1471

u32 pages;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1500

u32 size = combos[j].size;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1501

u32 pages = combos[j].pages;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1627

u32 i, addr;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1655

u32 sz;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1658

sz = max_t(u32, sz, SZ_4K);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1716

u32 rnd = i915_prandom_u32_max_state(UINT_MAX, &prng);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1730

offset_in_page(rnd) / sizeof(u32), rnd + 1);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1735

(PAGE_SIZE / sizeof(u32)) - 1,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1768

u32 *vaddr;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

107

u32 width;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

108

u32 height;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

148

u32 src_pitch, dst_pitch;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

149

u32 cmd, *cs;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

157

u32 src_tiles = 0, dst_tiles = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

158

u32 src_4t = 0, dst_4t = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

31

static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

333

static void fill_scratch(struct tiled_blits *t, u32 *vaddr, u32 val)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

420

const u32 *vaddr;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

602

u32 *map;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

96

u32 start_val;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

116

static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

120

u32 __iomem *map;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

150

static int wc_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

152

u32 *map;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

173

static int wc_get(struct context *ctx, unsigned long offset, u32 *v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

175

u32 *map;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

194

static int gpu_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

198

u32 *cs;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

23

static int cpu_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

27

u32 *cpu;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

277

int (*set)(struct context *ctx, unsigned long offset, u32 v);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

278

int (*get)(struct context *ctx, unsigned long offset, u32 *v);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

312

u32 *offsets, *values;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

324

offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

391

u32 found;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

54

static int cpu_get(struct context *ctx, unsigned long offset, u32 *v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

58

u32 *cpu;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

82

static int gtt_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

86

u32 __iomem *map;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1093

u32 *rpcs)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1096

u32 s_mask, s_shift;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1098

u32 *buf, val;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1137

__check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1170

u32 rpcs = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1496

offset, offset + sizeof(u32) - 1);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1511

u64 offset, u32 value)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1517

u32 *cmd;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1599

u64 offset, u32 *value)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1603

const u32 result = 0x100;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1607

u32 *cmd;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1617

const u32 GPR0 = engine->mmio_base + 0x600;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1652

const u32 reg = engine->mmio_base + 0x420;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1744

static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1747

u32 *vaddr;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1781

u32 expected;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1854

u32 value = 0xc5c5c5c5;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1860

sizeof(u32), alignof_dword);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

31

#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

469

(dw * sizeof(u32)),

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

477

static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

490

u32 *map;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

521

u32 *map, m;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

917

u32 *cmd;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

157

u32 *vaddr;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

206

for (i = 0; i < native_obj->base.size / sizeof(u32); i += PAGE_SIZE / sizeof(u32)) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

351

u32 pattern[] = { 0, 0xaa, 0xcc, 0x55, 0xff };

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

19

unsigned int i, count = obj->base.size / sizeof(u32);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

22

u32 *cur;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

102

u32 __iomem *io;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

105

u32 *cpu;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1104

for (i = 0; i < obj->base.size / sizeof(u32); i++) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1105

u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1106

u32 x;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1542

u32 __user *ux;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1543

u32 bbe;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

160

if (*cpu != (u32)page) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

171

(u32)page, *cpu);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

218

u32 __iomem *io;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

221

u32 *cpu;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

256

if (*cpu != (u32)page) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

267

(u32)page, *cpu);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

933

for (i = 0; i < obj->base.size / sizeof(u32); i++) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

934

u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

935

u32 x;

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

113

unsigned long count, u32 val)

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

45

u32 val)

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

50

u32 *cmd;

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

53

size = (4 * count + 1) * sizeof(u32);

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h

28

u32 val);

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h

32

unsigned long count, u32 val);

sys/dev/pci/drm/i915/gem/selftests/mock_context.c

84

u32 id;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

129

int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

131

u32 *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

144

static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

154

*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

16

int gen2_emit_flush(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

172

u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

177

u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

187

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

19

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

190

u32 *cs, cs_offset =

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

252

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

255

u32 *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

272

u64 offset, u32 length,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

275

u32 security;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

276

u32 *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

32

*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

43

int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

45

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

14

int gen2_emit_flush(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

15

int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

16

int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

18

u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

19

u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

22

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

25

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

28

u64 offset, u32 length,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

143

u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

15

#define HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

178

static int mi_flush_dw(struct i915_request *rq, u32 flags)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

180

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

214

static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

219

int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

224

int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

230

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

233

u32 security;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

234

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

252

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

255

u32 security;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

256

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

274

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

289

int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

291

u32 scratch_addr =

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

294

u32 *cs, flags = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

353

u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

375

u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

393

u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

57

u32 scratch_addr =

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

60

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

89

int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

91

u32 scratch_addr =

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

94

u32 *cs, flags = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

16

int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

17

int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

18

int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

19

u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

20

u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

22

int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

23

u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

24

u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

27

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

30

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

113

u32 flags)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

120

const u32 pte_encode = vm->pte_encode(0, pat_index, flags);

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

260

u32 pde;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

284

u32 unused)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

288

u32 ggtt_offset = vma_res->start / I915_GTT_PAGE_SIZE;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

34

u32 ecochk;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

19

u32 pp_dir;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

26

static inline u32 gen6_pte_index(u32 addr)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

31

static inline u32 gen6_pte_count(u32 addr, u32 length)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

36

static inline u32 gen6_pde_index(u32 addr)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

61

({ u32 temp = ALIGN(start + 1, 1 << GEN6_PDE_SHIFT); \

sys/dev/pci/drm/i915/gt/gen6_renderstate.c

10

static const u32 gen6_null_state_relocs[] = {

sys/dev/pci/drm/i915/gt/gen6_renderstate.c

19

static const u32 gen6_null_state_batch[] = {

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

102

static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

107

static u32 batch_addr(const struct batch_chunk *bc)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

112

static void batch_add(struct batch_chunk *bc, const u32 d)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

118

static u32 *batch_alloc_items(struct batch_chunk *bc, u32 align, u32 items)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

120

u32 *map;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

123

u32 *end = PTR_ALIGN(bc->end, align);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

135

static u32 *batch_alloc_bytes(struct batch_chunk *bc, u32 align, u32 bytes)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

141

static u32

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

143

const u32 dst_offset,

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

146

u32 surface_h = bv->surface_height;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

147

u32 surface_w = bv->surface_width;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

148

u32 *cs = batch_alloc_items(state, 32, 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

149

u32 offset = batch_offset(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

16

u32 size;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

174

static u32

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

178

u32 surface_start =

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

180

u32 *cs = batch_alloc_items(state, 32, 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

181

u32 offset = batch_offset(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

196

static u32

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

198

const u32 *data,

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

199

const u32 size)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

206

static u32

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

212

u32 kernel_offset =

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

214

u32 binding_table = gen7_fill_binding_table(state, bv);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

215

u32 *cs = batch_alloc_items(state, 32, 8 * count);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

216

u32 offset = batch_offset(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

236

u32 surface_state_base)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

238

u32 *cs = batch_alloc_items(batch, 0, 10);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

263

u32 urb_size, u32 curbe_size,

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

264

u32 mode)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

266

u32 threads = bv->max_threads - 1;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

267

u32 *cs = batch_alloc_items(batch, 32, 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

29

u32 offset;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

291

const u32 interface_descriptor,

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

294

u32 *cs = batch_alloc_items(batch, 8, 4);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

30

u32 *start;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

31

u32 *end;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

315

u32 *cs;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

32

u32 max_items;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

342

u32 *cs = batch_alloc_items(batch, 0, 4);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

357

u32 *cs = batch_alloc_items(batch, 0, 10);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

36

u32 max_threads;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

37

u32 state_start;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

377

u32 *start,

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

38

u32 surface_start;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

384

u32 descriptors;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

39

u32 surface_height;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

40

u32 surface_width;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

41

u32 size;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

436

u32 *batch;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

93

u32 *start, u32 offset, u32 max_bytes)

sys/dev/pci/drm/i915/gt/gen7_renderstate.c

10

static const u32 gen7_null_state_relocs[] = {

sys/dev/pci/drm/i915/gt/gen7_renderstate.c

18

static const u32 gen7_null_state_batch[] = {

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

112

int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

115

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

116

u32 flags = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

13

int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

137

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

138

u32 flags = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

16

u32 *cs, flags = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

163

static u32 preparser_disable(bool state)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

199

u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

202

u32 gsi_offset = engine->gt->uncore->gsi_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

228

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

244

int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

253

u32 bit_group_0 = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

254

u32 bit_group_1 = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

256

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

310

u32 flags = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

311

u32 *cs, count;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

362

int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

364

u32 cmd = 4;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

365

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

416

static u32 preempt_address(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

422

static u32 hwsp_offset(const struct i915_request *rq)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

436

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

482

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

484

u32 arb)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

487

u32 wa_offset = lrc_indirect_bb(ce);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

488

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

523

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

530

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

537

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

540

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

573

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

576

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

613

static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

626

static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

641

static __always_inline u32*

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

642

gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

657

static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

662

u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

667

u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

687

u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

727

static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

746

static u32 hold_switchout_semaphore_offset(struct i915_request *rq)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

755

static u32 *hold_switchout_emit_wa_busywait(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

783

static __always_inline u32*

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

784

gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

79

int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

805

u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

81

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

812

u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

816

u32 flags = (PIPE_CONTROL_CS_STALL |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

104

static inline u32*

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

105

gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

117

static inline u32 *

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

118

__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

128

static inline u32 *

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

129

gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

20

int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

21

int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

22

int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

24

int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

25

int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

30

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

33

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

37

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

40

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

43

u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

44

u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

46

u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

47

u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

48

u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

50

u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

52

static inline u32 *

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

53

__gen8_emit_pipe_control(u32 *batch, u32 bit_group_0,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

54

u32 bit_group_1, u32 offset)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

56

memset(batch, 0, 6 * sizeof(u32));

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

65

static inline u32 *gen8_emit_pipe_control(u32 *batch,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

66

u32 bit_group_1, u32 offset)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

71

static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 bit_group_0,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

72

u32 bit_group_1, u32 offset)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

78

static inline u32 *

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

79

__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

91

static inline u32*

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

92

gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

34

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

460

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

507

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

615

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

63

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

738

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

767

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

788

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

817

u32 flags)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

828

u32 pte_flags;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.h

19

u32 flags);

sys/dev/pci/drm/i915/gt/gen8_renderstate.c

10

static const u32 gen8_null_state_relocs[] = {

sys/dev/pci/drm/i915/gt/gen8_renderstate.c

18

static const u32 gen8_null_state_batch[] = {

sys/dev/pci/drm/i915/gt/gen9_renderstate.c

10

static const u32 gen9_null_state_relocs[] = {

sys/dev/pci/drm/i915/gt/gen9_renderstate.c

18

static const u32 gen9_null_state_batch[] = {

sys/dev/pci/drm/i915/gt/hsw_clear_kernel.c

8

static const u32 hsw_clear_kernel[] = {

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

21

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_context_types.h

114

u32 ring_size;

sys/dev/pci/drm/i915/gt/intel_context_types.h

141

u32 *lrc_reg_state;

sys/dev/pci/drm/i915/gt/intel_context_types.h

144

u32 lrca;

sys/dev/pci/drm/i915/gt/intel_context_types.h

145

u32 ccid;

sys/dev/pci/drm/i915/gt/intel_context_types.h

149

u32 tag; /* cookie passed to HW to track this context on submission */

sys/dev/pci/drm/i915/gt/intel_context_types.h

159

u32 last;

sys/dev/pci/drm/i915/gt/intel_context_types.h

160

I915_SELFTEST_DECLARE(u32 num_underflow);

sys/dev/pci/drm/i915/gt/intel_context_types.h

161

I915_SELFTEST_DECLARE(u32 max_underflow);

sys/dev/pci/drm/i915/gt/intel_context_types.h

198

u32 sched_state;

sys/dev/pci/drm/i915/gt/intel_context_types.h

217

u32 prio_count[GUC_CLIENT_PRIORITY_NUM];

sys/dev/pci/drm/i915/gt/intel_context_types.h

283

u32 seqno;

sys/dev/pci/drm/i915/gt/intel_context_types.h

295

u32 *wq_head;

sys/dev/pci/drm/i915/gt/intel_context_types.h

297

u32 *wq_tail;

sys/dev/pci/drm/i915/gt/intel_context_types.h

299

u32 *wq_status;

sys/dev/pci/drm/i915/gt/intel_engine.h

113

u32 __val; \

sys/dev/pci/drm/i915/gt/intel_engine.h

152

static inline u32

sys/dev/pci/drm/i915/gt/intel_engine.h

160

intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)

sys/dev/pci/drm/i915/gt/intel_engine.h

189

#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine.h

191

#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine.h

192

#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine.h

194

#define I915_GEM_HWS_GGTT_BIND_ADDR (I915_GEM_HWS_GGTT_BIND * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine.h

196

#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine.h

198

#define I915_GEM_HWS_GSC_ADDR (I915_GEM_HWS_GSC * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine.h

230

void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);

sys/dev/pci/drm/i915/gt/intel_engine.h

278

u32 intel_engine_context_size(struct intel_gt *gt, u8 class);

sys/dev/pci/drm/i915/gt/intel_engine.h

33

#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1168

u32 val;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1309

u32 cs[2048];

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1704

static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1726

u32 val;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1737

static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1767

u32 fw_pending = __cs_pending_mi_force_wakes(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1779

u32 mmio_base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2045

const size_t rowsize = 8 * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2062

rowsize, sizeof(u32),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2151

const u32 *hws =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

273

u32 intel_engine_context_size(struct intel_gt *gt, u8 class)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

276

u32 cxt_size;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

343

static u32 __engine_mmio_base(struct drm_i915_private *i915,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

370

void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

396

static u32 get_reset_domain(u8 ver, enum intel_engine_id id)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

398

u32 reset_domain;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

401

static const u32 engine_reset_domains[] = {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

434

static const u32 engine_reset_domains[] = {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

58

u32 graphics_ver : 8;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

59

u32 base : 24;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

760

u32 media_fuse, fuse1;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

190

u32 ccid;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

199

u32 yield;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

212

u32 error_interrupt;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

219

u32 reset_ccid;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

226

u32 __iomem *submit_reg;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

232

u32 __iomem *ctrl_reg;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

274

u32 *csb_write;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

335

u32 prev_total;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

361

u32 request;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

362

u32 done;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

377

u32 reset_domain;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

392

u32 uabi_capabilities;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

393

u32 context_size;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

394

u32 mmio_base;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

485

u32 enable;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

508

u32 irq_keep_mask; /* always keep these interrupts */

sys/dev/pci/drm/i915/gt/intel_engine_types.h

509

u32 irq_enable_mask; /* bitmask to enable ring interrupt */

sys/dev/pci/drm/i915/gt/intel_engine_types.h

537

int (*emit_flush)(struct i915_request *request, u32 mode);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

542

u64 offset, u32 length,

sys/dev/pci/drm/i915/gt/intel_engine_types.h

547

u32 *(*emit_fini_breadcrumb)(struct i915_request *rq,

sys/dev/pci/drm/i915/gt/intel_engine_types.h

548

u32 *cs);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

59

typedef u32 intel_engine_mask_t;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

625

u32 (*get_cmd_length_mask)(u32 cmd_header);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

66

u32 *addr;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

70

u32 instdone;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

72

u32 slice_common;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

73

u32 slice_common_extra[2];

sys/dev/pci/drm/i915/gt/intel_engine_types.h

74

u32 sampler[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];

sys/dev/pci/drm/i915/gt/intel_engine_types.h

75

u32 row[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];

sys/dev/pci/drm/i915/gt/intel_engine_types.h

78

u32 geom_svg[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];

sys/dev/pci/drm/i915/gt/intel_engine_types.h

94

u32 offset;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

95

u32 size;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

108

u32 enabled, disabled;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

152

u32 enabled, disabled;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1967

const u32 *regs __maybe_unused =

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2288

active_context(struct intel_engine_cs *engine, u32 ccid)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2321

static u32 active_ccid(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2492

u32 eir;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2719

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2756

u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2890

u32 status;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2933

u32 mode;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3031

u32 head;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3541

u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

433

u32 head;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

663

static u32 map_i915_prio_to_lrc_desc_prio(int prio)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

677

u32 tail, prev;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

724

static void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

784

u32 ccid = -1;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1234

u32 pte_flags;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1290

u32 pte_flags;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1476

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1497

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1520

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1535

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1547

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

292

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

312

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

369

static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

370

struct sg_table *pages, u32 num_entries,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

380

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

399

u32 n_ptes = min_t(u32, 511, num_entries);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

485

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

508

unsigned int pat_index, u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

524

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

562

unsigned int pat_index, u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

593

unsigned int pat_index, u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

650

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

681

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

750

u32 unused)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

761

u32 flags;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

778

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

810

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

812

u32 pte_flags;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

912

ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

995

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

997

u32 pte_flags;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

115

u32 val;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

149

u32 val;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

576

u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

577

u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

600

u32 dimm_c0, dimm_c1;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

669

u32 dcc = intel_uncore_read(uncore, DCC);

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.h

38

u32 start;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.h

39

u32 size;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.h

40

u32 tiling;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.h

41

u32 stride;

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

22

u32 unused)

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

40

u32 unused)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

467

static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags)

sys/dev/pci/drm/i915/gt/intel_gsc.c

310

void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir)

sys/dev/pci/drm/i915/gt/intel_gsc.h

41

void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);

sys/dev/pci/drm/i915/gt/intel_gt.c

142

static void init_unused_ring(struct intel_gt *gt, u32 base)

sys/dev/pci/drm/i915/gt/intel_gt.c

248

u32 eir;

sys/dev/pci/drm/i915/gt/intel_gt.c

307

u32 fault;

sys/dev/pci/drm/i915/gt/intel_gt.c

326

static void gen8_report_fault(struct intel_gt *gt, u32 fault,

sys/dev/pci/drm/i915/gt/intel_gt.c

327

u32 fault_data0, u32 fault_data1)

sys/dev/pci/drm/i915/gt/intel_gt.c

349

u32 fault;

sys/dev/pci/drm/i915/gt/intel_gt.c

369

u32 fault;

sys/dev/pci/drm/i915/gt/intel_gt.h

155

static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool_types.h

33

u32 pinned;

sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c

14

u32 mode = 0;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

108

static u32 gen6_read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

120

static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

129

static u32 g4x_read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

14

static u32 read_reference_ts_freq(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

140

static u32 gen4_read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

154

static u32 read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

16

u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

17

u32 base_freq, frac_freq;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

201

static u64 div_u64_roundup(u64 nom, u32 den)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

31

static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

32

u32 rpm_config_reg)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

34

u32 f19_2_mhz = 19200000;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

35

u32 f24_mhz = 24000000;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

36

u32 f25_mhz = 25000000;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

37

u32 f38_4_mhz = 38400000;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

38

u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

55

static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

57

u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

58

u32 freq = 0;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

72

u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

87

static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

89

u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

90

u32 freq = 0;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

120

gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

160

const u32 ident = gen11_gt_engine_identity(gt, bank, bit);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

169

void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

187

u32 dw;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

264

u32 irqs = GT_RENDER_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

265

u32 guc_mask = intel_uc_wants_guc(&gt->uc) ? GUC_INTR_GUC2HOST : 0;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

266

u32 gsc_mask = 0;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

267

u32 heci_mask = 0;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

268

u32 dmask;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

269

u32 smask;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

30

static u32

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

334

u32 mask = gt->type == GT_MEDIA ?

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

35

u32 timeout_ts;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

355

void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

36

u32 ident;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

366

static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

384

void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

407

void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

410

u32 iir;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

466

const u32 irqs =

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

471

const u32 gt_interrupts[] = {

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

492

u32 interrupt_mask,

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

493

u32 enabled_irq_mask)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

504

void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

510

void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

527

u32 pm_irqs = 0;

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

528

u32 gt_irqs = 0;

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

25

void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

31

void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

35

void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

36

void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

38

void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

40

void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

207

static u32 rw_with_mcr_steering_fw(struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

209

int group, int instance, u32 value)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

212

u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

284

static u32 rw_with_mcr_steering(struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

287

u32 value)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

292

u32 val;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

436

u32 intel_gt_mcr_read(struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

456

void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

473

i915_mcr_reg_t reg, u32 value)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

504

void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

538

u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

539

u32 clear, u32 set)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

541

u32 val = intel_gt_mcr_read_any(gt, reg);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

566

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

597

u32 dss;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

694

u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

725

u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

846

u32 mask,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

847

u32 value,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

16

u32 intel_gt_mcr_read(struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

19

u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

20

u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

23

i915_mcr_reg_t reg, u32 value,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

26

i915_mcr_reg_t reg, u32 value);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

28

i915_mcr_reg_t reg, u32 value);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

30

u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

31

u32 clear, u32 set);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

45

u32 mask,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

46

u32 value,

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

122

u32 gt_core_status, mt_fwake_req, rcctl1, rc6vids = 0;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

123

u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

210

u32 rgvmodectl, rstdbyctl;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

269

u32 gt_core_status, rcctl1, mt_fwake_req;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

270

u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

361

u32 rpmodectl, freq_sts;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

513

u32 rpup, rpupei;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

514

u32 rpdown, rpdownei;

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

96

u32 rcctl1, pw_status, mt_fwake_req;

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

102

void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

17

u32 mask = gt->pm_imr;

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

33

u32 interrupt_mask,

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

34

u32 enabled_irq_mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

36

u32 new_val;

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

52

void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

57

void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

62

void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

78

u32 mask = gt->pm_ier;

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

93

void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

13

void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

14

void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

16

void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

17

void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

19

void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask);

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

104

u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

126

u32 val; \

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

170

static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

199

static u32 __rc6_residency_ms_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

204

static u32 __rc6p_residency_ms_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

209

static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

214

static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

31

int (func)(struct intel_gt *gt, u32 val), u32 val)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

315

static u32 __act_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

320

static u32 __cur_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

325

static u32 __boost_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

330

static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

335

static u32 __RP0_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

340

static u32 __RPn_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

345

static u32 __RP1_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

350

static u32 __max_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

355

static int __set_max_freq(struct intel_gt *gt, u32 val)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

360

static u32 __min_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

365

static int __set_min_freq(struct intel_gt *gt, u32 val)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

370

static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

437

u32 preq = intel_rps_read_punit_req_frequency(&gt->rps);

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

459

u32 val;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

495

u32 val;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

513

u32 mask;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

54

static u32

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

56

u32 (func)(struct intel_gt *gt),

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

60

u32 ret;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

606

static u32 media_ratio_mode_to_factor(u32 mode)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

618

u32 mode;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

62

ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

640

u32 factor, mode;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

668

u32 val;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

689

u32 val;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

70

u32 val = func(gt);

sys/dev/pci/drm/i915/gt/intel_gt_types.h

167

u32 clock_frequency;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

168

u32 clock_period_ns;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

175

u32 gt_imr;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

176

u32 pm_ier;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

177

u32 pm_imr;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

179

u32 pm_guc_events;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

264

u32 l3bank_mask;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

306

u32 mapping_base;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

307

u32 gsi_offset;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

41

u32 start;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

42

u32 end;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

84

u32 min_freq;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

85

u32 max_freq;

sys/dev/pci/drm/i915/gt/intel_gtt.h

237

u32 flags);

sys/dev/pci/drm/i915/gt/intel_gtt.h

314

u32 flags); /* Create a valid PTE */

sys/dev/pci/drm/i915/gt/intel_gtt.h

330

u32 flags);

sys/dev/pci/drm/i915/gt/intel_gtt.h

334

u32 flags);

sys/dev/pci/drm/i915/gt/intel_gtt.h

339

u32 flags);

sys/dev/pci/drm/i915/gt/intel_gtt.h

343

u32 flags);

sys/dev/pci/drm/i915/gt/intel_gtt.h

390

u32 bit_6_swizzle_x;

sys/dev/pci/drm/i915/gt/intel_gtt.h

392

u32 bit_6_swizzle_y;

sys/dev/pci/drm/i915/gt/intel_gtt.h

394

u32 pin_bias;

sys/dev/pci/drm/i915/gt/intel_gtt.h

533

static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)

sys/dev/pci/drm/i915/gt/intel_gtt.h

535

const u32 mask = NUM_PTE(pde_shift) - 1;

sys/dev/pci/drm/i915/gt/intel_gtt.h

545

static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)

sys/dev/pci/drm/i915/gt/intel_gtt.h

561

static inline u32 i915_pde_index(u64 addr, u32 shift)

sys/dev/pci/drm/i915/gt/intel_gtt.h

594

u32 flags);

sys/dev/pci/drm/i915/gt/intel_gtt.h

61

typedef u32 gen6_pte_t;

sys/dev/pci/drm/i915/gt/intel_gtt.h

675

u32 flags);

sys/dev/pci/drm/i915/gt/intel_hwconfig.h

14

u32 size;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1000

static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1046

u32 lrc_indirect_bb(const struct intel_context *ce)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1051

static u32 *setup_predicate_disable_wa(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1080

u32 context_size;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1263

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1264

gen12_emit_timestamp_wa(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1271

CTX_TIMESTAMP * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1289

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1290

gen12_emit_restore_scratch(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1299

(lrc_ring_gpr0(ce->engine) + 1) * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1305

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1306

gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1315

(lrc_ring_cmd_buf_cctl(ce->engine) + 1) * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1334

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1335

dg2_emit_draw_watermark_setting(u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1344

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1345

gen12_invalidate_state_cache(u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1353

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1354

gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1379

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1380

gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1395

static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1439

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1440

xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1452

u32 *(*emit)(const struct intel_context *, u32 *))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1455

u32 * const start = context_wabb(ce, true);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1456

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1471

u32 *(*emit)(const struct intel_context *, u32 *))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1473

u32 * const start = context_wabb(ce, false);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1474

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1523

static u32 lrc_descriptor(const struct intel_context *ce)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1525

u32 desc;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1539

u32 lrc_update_regs(const struct intel_context *ce,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1541

u32 head)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1544

u32 *regs = ce->lrc_reg_state;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1563

u32 *(*fn)(const struct intel_context *ce, u32 *cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1589

u32 *regs = ce->lrc_reg_state;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1607

(u32)(RING_CTL_SIZE(ring->size) | RING_VALID));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1640

static u32 *

sys/dev/pci/drm/i915/gt/intel_lrc.c

1641

gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1683

static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1718

u32 value;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1721

static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1735

static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1838

typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1944

max_t(u32, stats->runtime.max_underflow, -dt);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1948

static u32 lrc_get_runtime(const struct intel_context *ce)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1962

u32 old;

sys/dev/pci/drm/i915/gt/intel_lrc.c

47

static void set_offsets(u32 *regs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

60

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_lrc.c

770

static u32

sys/dev/pci/drm/i915/gt/intel_lrc.c

788

lrc_setup_bb_per_ctx(u32 *regs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

790

u32 ctx_bb_ggtt_addr)

sys/dev/pci/drm/i915/gt/intel_lrc.c

800

lrc_setup_indirect_ctx(u32 *regs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

802

u32 ctx_bb_ggtt_addr,

sys/dev/pci/drm/i915/gt/intel_lrc.c

803

u32 size)

sys/dev/pci/drm/i915/gt/intel_lrc.c

839

static void init_common_regs(u32 * const regs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

84

u32 offset = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

844

u32 ctl;

sys/dev/pci/drm/i915/gt/intel_lrc.c

866

static void init_wa_bb_regs(u32 * const regs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

872

const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);

sys/dev/pci/drm/i915/gt/intel_lrc.c

887

static void init_ppgtt_regs(u32 *regs, const struct i915_ppgtt *ppgtt)

sys/dev/pci/drm/i915/gt/intel_lrc.c

911

static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

922

static void __lrc_init_regs(u32 *regs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

989

static u32 context_wa_bb_offset(const struct intel_context *ce)

sys/dev/pci/drm/i915/gt/intel_lrc.h

143

u32 lrc_indirect_bb(const struct intel_context *ce);

sys/dev/pci/drm/i915/gt/intel_lrc.h

31

#define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_lrc.h

64

u32 lrc_update_regs(const struct intel_context *ce,

sys/dev/pci/drm/i915/gt/intel_lrc.h

66

u32 head);

sys/dev/pci/drm/i915/gt/intel_lrc_reg.h

34

u32 *reg_state__ = (reg_state); \

sys/dev/pci/drm/i915/gt/intel_lrc_reg.h

41

u32 *reg_state__ = (reg_state); \

sys/dev/pci/drm/i915/gt/intel_migrate.c

1123

u32 value,

sys/dev/pci/drm/i915/gt/intel_migrate.c

336

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

354

pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32) + 5);

sys/dev/pci/drm/i915/gt/intel_migrate.c

355

pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);

sys/dev/pci/drm/i915/gt/intel_migrate.c

374

u32 total = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

375

u32 page_size;

sys/dev/pci/drm/i915/gt/intel_migrate.c

376

u32 *hdr, *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

478

static bool wa_1209644611_applies(int ver, u32 size)

sys/dev/pci/drm/i915/gt/intel_migrate.c

480

u32 height = size >> PAGE_SHIFT;

sys/dev/pci/drm/i915/gt/intel_migrate.c

521

static inline u32 *i915_flush_dw(u32 *cmd, u32 flags)

sys/dev/pci/drm/i915/gt/intel_migrate.c

531

u32 dst_offset, u8 dst_access,

sys/dev/pci/drm/i915/gt/intel_migrate.c

532

u32 src_offset, u8 src_access, int size)

sys/dev/pci/drm/i915/gt/intel_migrate.c

536

u32 num_ccs_blks;

sys/dev/pci/drm/i915/gt/intel_migrate.c

537

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

582

u32 dst_offset, u32 src_offset, int size)

sys/dev/pci/drm/i915/gt/intel_migrate.c

585

u32 instance = rq->engine->instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

586

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

692

u32 src_offset, dst_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

917

static int emit_clear(struct i915_request *rq, u32 offset, int size,

sys/dev/pci/drm/i915/gt/intel_migrate.c

918

u32 value, bool is_lmem)

sys/dev/pci/drm/i915/gt/intel_migrate.c

924

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

989

u32 value,

sys/dev/pci/drm/i915/gt/intel_migrate.c

995

u32 offset;

sys/dev/pci/drm/i915/gt/intel_migrate.h

52

u32 value,

sys/dev/pci/drm/i915/gt/intel_migrate.h

60

u32 value,

sys/dev/pci/drm/i915/gt/intel_mocs.c

17

u32 control_value;

sys/dev/pci/drm/i915/gt/intel_mocs.c

540

static u32 get_entry_control(const struct drm_i915_mocs_table *table,

sys/dev/pci/drm/i915/gt/intel_mocs.c

555

u32 addr)

sys/dev/pci/drm/i915/gt/intel_mocs.c

558

u32 mocs;

sys/dev/pci/drm/i915/gt/intel_mocs.c

566

static u32 mocs_offset(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_mocs.c

568

static const u32 offset[] = {

sys/dev/pci/drm/i915/gt/intel_mocs.c

600

static u32 l3cc_combine(u16 low, u16 high)

sys/dev/pci/drm/i915/gt/intel_mocs.c

602

return low | (u32)high << 16;

sys/dev/pci/drm/i915/gt/intel_mocs.c

618

u32 l3cc;

sys/dev/pci/drm/i915/gt/intel_mocs.c

649

static u32 global_mocs_offset(void)

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

186

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

188

u32 pte_flags;

sys/dev/pci/drm/i915/gt/intel_rc6.c

233

u32 rc6vids, rc6_mask;

sys/dev/pci/drm/i915/gt/intel_rc6.c

287

u32 pcbr;

sys/dev/pci/drm/i915/gt/intel_rc6.c

309

u32 pcbr;

sys/dev/pci/drm/i915/gt/intel_rc6.c

430

u32 rc6_ctx_base, rc_ctl, rc_sw_target;

sys/dev/pci/drm/i915/gt/intel_rc6.c

62

u32 pg_enable;

sys/dev/pci/drm/i915/gt/intel_rc6.c

741

u32 lower, upper, tmp;

sys/dev/pci/drm/i915/gt/intel_rc6.c

792

u32 mul, div;

sys/dev/pci/drm/i915/gt/intel_rc6_types.h

31

u32 ctl_enable;

sys/dev/pci/drm/i915/gt/intel_rc6_types.h

32

u32 bios_rc_state;

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

208

u64 *start, u32 *size)

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

226

u32 reserve_size;

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

66

u32 pci_cmd;

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

72

u32 bar_sizes;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

114

u32 eu_pool_config = 0x00777000;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

125

so->aux_size = i * sizeof(u32) - so->aux_offset;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

135

__i915_gem_object_flush_map(so->vma->obj, 0, i * sizeof(u32));

sys/dev/pci/drm/i915/gt/intel_renderstate.c

45

if ((i) >= PAGE_SIZE / sizeof(u32)) \

sys/dev/pci/drm/i915/gt/intel_renderstate.c

56

u32 *d;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

63

u32 s = rodata->batch[i];

sys/dev/pci/drm/i915/gt/intel_renderstate.c

90

so->batch_size = rodata->batch_items * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

95

so->aux_offset = i * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_renderstate.h

18

const u32 *reloc;

sys/dev/pci/drm/i915/gt/intel_renderstate.h

19

const u32 *batch;

sys/dev/pci/drm/i915/gt/intel_renderstate.h

20

const u32 batch_items;

sys/dev/pci/drm/i915/gt/intel_renderstate.h

39

u32 batch_offset;

sys/dev/pci/drm/i915/gt/intel_renderstate.h

40

u32 batch_size;

sys/dev/pci/drm/i915/gt/intel_renderstate.h

41

u32 aux_offset;

sys/dev/pci/drm/i915/gt/intel_renderstate.h

42

u32 aux_size;

sys/dev/pci/drm/i915/gt/intel_reset.c

1419

u32 engine_mask,

sys/dev/pci/drm/i915/gt/intel_reset.c

267

static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)

sys/dev/pci/drm/i915/gt/intel_reset.c

324

u32 hw_mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

369

u32 lock_bit;

sys/dev/pci/drm/i915/gt/intel_reset.c

370

u32 ack_bit;

sys/dev/pci/drm/i915/gt/intel_reset.c

371

u32 usage_bit;

sys/dev/pci/drm/i915/gt/intel_reset.c

372

u32 reset_bit;

sys/dev/pci/drm/i915/gt/intel_reset.c

410

u32 *reset_mask,

sys/dev/pci/drm/i915/gt/intel_reset.c

411

u32 *unlock_mask)

sys/dev/pci/drm/i915/gt/intel_reset.c

526

u32 reset_mask, unlock_mask = 0;

sys/dev/pci/drm/i915/gt/intel_reset.c

565

u32 request, mask, ack;

sys/dev/pci/drm/i915/gt/intel_reset.c

699

u32 guc_domain =

sys/dev/pci/drm/i915/gt/intel_ring.c

230

u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)

sys/dev/pci/drm/i915/gt/intel_ring.c

234

const unsigned int bytes = num_dwords * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_ring.c

237

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ring.c

85

void intel_ring_reset(struct intel_ring *ring, u32 tail)

sys/dev/pci/drm/i915/gt/intel_ring.h

18

u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords);

sys/dev/pci/drm/i915/gt/intel_ring.h

25

void intel_ring_reset(struct intel_ring *ring, u32 tail);

sys/dev/pci/drm/i915/gt/intel_ring.h

40

static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_ring.h

54

static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)

sys/dev/pci/drm/i915/gt/intel_ring.h

60

u32 next, u32 prev)

sys/dev/pci/drm/i915/gt/intel_ring.h

80

static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)

sys/dev/pci/drm/i915/gt/intel_ring.h

83

u32 offset = addr - rq->ring->vaddr;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

155

static u32 pp_dir(struct i915_address_space *vm)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

37

static void set_hwstam(struct intel_engine_cs *engine, u32 mask)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

392

u32 head;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

55

u32 addr;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

699

u32 valid)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

702

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

733

u32 flags)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

742

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

78

static void set_hwsp(struct intel_engine_cs *engine, u32 offset)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

850

#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

851

u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

981

u32 flags;

sys/dev/pci/drm/i915/gt/intel_ring_types.h

20

#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))

sys/dev/pci/drm/i915/gt/intel_ring_types.h

41

u32 head; /* updated during retire, loosely tracks RING_HEAD */

sys/dev/pci/drm/i915/gt/intel_ring_types.h

42

u32 tail; /* updated on submission, used for RING_TAIL */

sys/dev/pci/drm/i915/gt/intel_ring_types.h

43

u32 emit; /* updated during request construction */

sys/dev/pci/drm/i915/gt/intel_ring_types.h

45

u32 space;

sys/dev/pci/drm/i915/gt/intel_ring_types.h

46

u32 size;

sys/dev/pci/drm/i915/gt/intel_ring_types.h

47

u32 wrap;

sys/dev/pci/drm/i915/gt/intel_ring_types.h

48

u32 effective_size;

sys/dev/pci/drm/i915/gt/intel_rps.c

1108

static u32 intel_rps_read_state_cap(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

1123

u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ?

sys/dev/pci/drm/i915/gt/intel_rps.c

1126

u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ?

sys/dev/pci/drm/i915/gt/intel_rps.c

1140

u32 rp_state_cap;

sys/dev/pci/drm/i915/gt/intel_rps.c

1206

u32 ddcc_status = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

1207

u32 mult = 1;

sys/dev/pci/drm/i915/gt/intel_rps.c

1215

clamp_t(u32,

sys/dev/pci/drm/i915/gt/intel_rps.c

1290

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1317

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1328

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1335

static u32 chv_rps_min_freq(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

1338

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1350

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1397

u32 val, rp1;

sys/dev/pci/drm/i915/gt/intel_rps.c

1410

u32 val, rp0;

sys/dev/pci/drm/i915/gt/intel_rps.c

1416

rp0 = min_t(u32, rp0, 0xea);

sys/dev/pci/drm/i915/gt/intel_rps.c

1424

u32 val, rpe;

sys/dev/pci/drm/i915/gt/intel_rps.c

1437

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1447

return max_t(u32, val, 0xc0);

sys/dev/pci/drm/i915/gt/intel_rps.c

1454

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

1501

u32 pxvid, ext_v;

sys/dev/pci/drm/i915/gt/intel_rps.c

174

static u32 rps_pm_mask(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

176

u32 mask = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

1783

static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)

sys/dev/pci/drm/i915/gt/intel_rps.c

1788

u32 events = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

1797

u32 render, media;

sys/dev/pci/drm/i915/gt/intel_rps.c

1830

u32 pm_iir = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

1913

void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)

sys/dev/pci/drm/i915/gt/intel_rps.c

1916

const u32 events = rps->pm_events & pm_iir;

sys/dev/pci/drm/i915/gt/intel_rps.c

1931

void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)

sys/dev/pci/drm/i915/gt/intel_rps.c

1934

u32 events;

sys/dev/pci/drm/i915/gt/intel_rps.c

1963

u32 busy_up, busy_down, max_avg, min_avg;

sys/dev/pci/drm/i915/gt/intel_rps.c

2033

u32 params = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

2086

u32 intel_rps_read_rpstat(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2096

static u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)

sys/dev/pci/drm/i915/gt/intel_rps.c

2099

u32 cagf;

sys/dev/pci/drm/i915/gt/intel_rps.c

2119

static u32 __read_cagf(struct intel_rps *rps, bool take_fw)

sys/dev/pci/drm/i915/gt/intel_rps.c

2124

u32 freq;

sys/dev/pci/drm/i915/gt/intel_rps.c

2150

static u32 read_cagf(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2155

u32 intel_rps_read_actual_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2159

u32 freq = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

2167

u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2172

static u32 intel_rps_read_punit_req(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2177

u32 freq = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

2185

static u32 intel_rps_get_req(u32 pureq)

sys/dev/pci/drm/i915/gt/intel_rps.c

2187

u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;

sys/dev/pci/drm/i915/gt/intel_rps.c

2192

u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2194

u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps));

sys/dev/pci/drm/i915/gt/intel_rps.c

2199

u32 intel_rps_get_requested_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2207

u32 intel_rps_get_max_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2224

u32 intel_rps_get_max_raw_freq(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2227

u32 freq;

sys/dev/pci/drm/i915/gt/intel_rps.c

2242

u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2252

u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2262

u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2278

u32 rp_state_limits;

sys/dev/pci/drm/i915/gt/intel_rps.c

2279

u32 gt_perf_status;

sys/dev/pci/drm/i915/gt/intel_rps.c

2280

u32 rpmodectl, rpinclimit, rpdeclimit;

sys/dev/pci/drm/i915/gt/intel_rps.c

2281

u32 rpstat, cagf, reqf;

sys/dev/pci/drm/i915/gt/intel_rps.c

2282

u32 rpcurupei, rpcurup, rpprevup;

sys/dev/pci/drm/i915/gt/intel_rps.c

2283

u32 rpcurdownei, rpcurdown, rpprevdown;

sys/dev/pci/drm/i915/gt/intel_rps.c

2284

u32 rpupei, rpupt, rpdownei, rpdownt;

sys/dev/pci/drm/i915/gt/intel_rps.c

2285

u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;

sys/dev/pci/drm/i915/gt/intel_rps.c

2440

u32 pm_mask;

sys/dev/pci/drm/i915/gt/intel_rps.c

2479

static int set_max_freq(struct intel_rps *rps, u32 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

2517

int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

2527

u32 intel_rps_get_min_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2544

u32 intel_rps_get_min_raw_freq(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2547

u32 freq;

sys/dev/pci/drm/i915/gt/intel_rps.c

2562

static int set_min_freq(struct intel_rps *rps, u32 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

2595

int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

2660

u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE;

sys/dev/pci/drm/i915/gt/intel_rps.c

2716

static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)

sys/dev/pci/drm/i915/gt/intel_rps.c

2720

u32 val;

sys/dev/pci/drm/i915/gt/intel_rps.c

2729

i915_reg_t reg32, u32 mask)

sys/dev/pci/drm/i915/gt/intel_rps.c

286

u32 rgvmodectl;

sys/dev/pci/drm/i915/gt/intel_rps.c

364

u32 tsfs;

sys/dev/pci/drm/i915/gt/intel_rps.c

386

static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid)

sys/dev/pci/drm/i915/gt/intel_rps.c

401

u32 count;

sys/dev/pci/drm/i915/gt/intel_rps.c

481

static unsigned long intel_pxfreq(u32 vidfreq)

sys/dev/pci/drm/i915/gt/intel_rps.c

515

u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i));

sys/dev/pci/drm/i915/gt/intel_rps.c

565

u32 rgvmodectl;

sys/dev/pci/drm/i915/gt/intel_rps.c

656

static u32 rps_limits(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

658

u32 limits;

sys/dev/pci/drm/i915/gt/intel_rps.c

685

u32 ei_up = 0, ei_down = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

70

static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)

sys/dev/pci/drm/i915/gt/intel_rps.c

75

static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

807

u32 swreq;

sys/dev/pci/drm/i915/gt/intel_rps.c

957

u32 intel_rps_get_boost_frequency(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

970

static int rps_set_boost_freq(struct intel_rps *rps, u32 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

991

int intel_rps_set_boost_frequency(struct intel_rps *rps, u32 freq)

sys/dev/pci/drm/i915/gt/intel_rps.h

32

u32 intel_rps_get_boost_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

33

int intel_rps_set_boost_frequency(struct intel_rps *rps, u32 freq);

sys/dev/pci/drm/i915/gt/intel_rps.h

44

u32 intel_rps_read_actual_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

45

u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

46

u32 intel_rps_get_requested_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

47

u32 intel_rps_get_min_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

48

u32 intel_rps_get_min_raw_freq(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

49

int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);

sys/dev/pci/drm/i915/gt/intel_rps.h

50

u32 intel_rps_get_max_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

51

u32 intel_rps_get_max_raw_freq(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

52

int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);

sys/dev/pci/drm/i915/gt/intel_rps.h

53

u32 intel_rps_get_rp0_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

54

u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

55

u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

56

u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

57

u32 intel_rps_read_rpstat(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

62

u32 intel_rps_read_throttle_reason(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

63

bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);

sys/dev/pci/drm/i915/gt/intel_rps.h

68

void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);

sys/dev/pci/drm/i915/gt/intel_rps.h

69

void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);

sys/dev/pci/drm/i915/gt/intel_rps_types.h

29

u32 render_c0;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

30

u32 media_c0;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

67

u32 pm_interval;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

68

u32 pm_iir;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

71

u32 pm_intrmsk_mbz;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

72

u32 pm_events;

sys/dev/pci/drm/i915/gt/intel_sa_media.c

13

u32 gsi_offset)

sys/dev/pci/drm/i915/gt/intel_sa_media.h

13

u32 gsi_offset);

sys/dev/pci/drm/i915/gt/intel_sseu.c

151

u32 ss_en, u16 eu_en)

sys/dev/pci/drm/i915/gt/intel_sseu.c

153

u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);

sys/dev/pci/drm/i915/gt/intel_sseu.c

194

u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};

sys/dev/pci/drm/i915/gt/intel_sseu.c

256

u32 g_dss_en;

sys/dev/pci/drm/i915/gt/intel_sseu.c

297

u32 ss_en;

sys/dev/pci/drm/i915/gt/intel_sseu.c

330

u32 fuse;

sys/dev/pci/drm/i915/gt/intel_sseu.c

380

u32 fuse2, eu_disable, subslice_mask;

sys/dev/pci/drm/i915/gt/intel_sseu.c

485

u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */

sys/dev/pci/drm/i915/gt/intel_sseu.c

486

u32 eu_disable0, eu_disable1, eu_disable2;

sys/dev/pci/drm/i915/gt/intel_sseu.c

523

u32 n_disabled;

sys/dev/pci/drm/i915/gt/intel_sseu.c

569

u32 fuse1;

sys/dev/pci/drm/i915/gt/intel_sseu.c

652

u32 intel_sseu_make_rpcs(struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_sseu.c

659

u32 rpcs = 0;

sys/dev/pci/drm/i915/gt/intel_sseu.c

719

u32 mask, val = slices;

sys/dev/pci/drm/i915/gt/intel_sseu.c

736

u32 val = subslices;

sys/dev/pci/drm/i915/gt/intel_sseu.c

747

u32 val;

sys/dev/pci/drm/i915/gt/intel_sseu.h

163

u32 intel_sseu_make_rpcs(struct intel_gt *gt,

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

115

u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

172

u32 slice_info = intel_uncore_read(gt->uncore, GEN8_GT_SLICE_INFO);

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

21

u32 sig1[SS_MAX], sig2[SS_MAX];

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

55

u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];

sys/dev/pci/drm/i915/gt/intel_timeline.c

225

u32 *hwsp_seqno = (u32 *)tl->hwsp_seqno;

sys/dev/pci/drm/i915/gt/intel_timeline.c

299

static u32 timeline_advance(struct intel_timeline *tl)

sys/dev/pci/drm/i915/gt/intel_timeline.c

309

u32 *seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.c

311

u32 next_ofs = offset_in_page(tl->hwsp_offset + TIMELINE_SEQNO_BYTES);

sys/dev/pci/drm/i915/gt/intel_timeline.c

328

u32 *seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.c

341

u32 *hwsp)

sys/dev/pci/drm/i915/gt/intel_timeline.c

61

u32 ofs = offset_in_page(timeline->hwsp_offset);

sys/dev/pci/drm/i915/gt/intel_timeline.h

47

u64 context, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.h

59

u64 context, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.h

75

u32 *seqno);

sys/dev/pci/drm/i915/gt/intel_timeline.h

83

u32 *hwsp_offset);

sys/dev/pci/drm/i915/gt/intel_timeline_types.h

23

u32 seqno;

sys/dev/pci/drm/i915/gt/intel_timeline_types.h

47

const u32 *hwsp_seqno;

sys/dev/pci/drm/i915/gt/intel_timeline_types.h

49

u32 hwsp_offset;

sys/dev/pci/drm/i915/gt/intel_tlb.c

113

static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_tlb.c

115

u32 cur = intel_gt_tlb_seqno(gt);

sys/dev/pci/drm/i915/gt/intel_tlb.c

121

void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_tlb.h

14

void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno);

sys/dev/pci/drm/i915/gt/intel_tlb.h

19

static inline u32 intel_gt_tlb_seqno(const struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_tlb.h

24

static inline u32 intel_gt_next_invalidate_tlb_full(const struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/intel_wopcm.c

105

u32 guc_wopcm_base, u32 guc_wopcm_size)

sys/dev/pci/drm/i915/gt/intel_wopcm.c

107

u32 offset;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

116

(guc_wopcm_size - offset) < sizeof(u32)) {

sys/dev/pci/drm/i915/gt/intel_wopcm.c

120

(u32)(offset + sizeof(u32)) / SZ_1K);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

128

u32 guc_wopcm_size, u32 huc_fw_size)

sys/dev/pci/drm/i915/gt/intel_wopcm.c

147

u32 guc_wopcm_base, u32 guc_wopcm_size,

sys/dev/pci/drm/i915/gt/intel_wopcm.c

148

u32 huc_fw_size)

sys/dev/pci/drm/i915/gt/intel_wopcm.c

161

static bool __check_layout(struct intel_gt *gt, u32 wopcm_size,

sys/dev/pci/drm/i915/gt/intel_wopcm.c

162

u32 guc_wopcm_base, u32 guc_wopcm_size,

sys/dev/pci/drm/i915/gt/intel_wopcm.c

163

u32 guc_fw_size, u32 huc_fw_size)

sys/dev/pci/drm/i915/gt/intel_wopcm.c

166

const u32 ctx_rsvd = context_reserved_size(i915);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

167

u32 size;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

201

u32 *guc_wopcm_base, u32 *guc_wopcm_size)

sys/dev/pci/drm/i915/gt/intel_wopcm.c

203

u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

204

u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

237

u32 guc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.guc.fw);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

238

u32 huc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.huc.fw);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

239

u32 ctx_rsvd = context_reserved_size(i915);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

240

u32 wopcm_size = wopcm->size;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

241

u32 guc_wopcm_base;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

242

u32 guc_wopcm_size;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

94

static u32 context_reserved_size(struct drm_i915_private *i915)

sys/dev/pci/drm/i915/gt/intel_wopcm.h

19

u32 size;

sys/dev/pci/drm/i915/gt/intel_wopcm.h

21

u32 base;

sys/dev/pci/drm/i915/gt/intel_wopcm.h

22

u32 size;

sys/dev/pci/drm/i915/gt/intel_wopcm.h

36

static inline u32 intel_wopcm_guc_base(struct intel_wopcm *wopcm)

sys/dev/pci/drm/i915/gt/intel_wopcm.h

51

static inline u32 intel_wopcm_guc_size(struct intel_wopcm *wopcm)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1025

u32 val;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1144

u32 mcr, mcr_mask;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1273

u32 mcr, mcr_mask;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1337

u32 lncf_mask = 0;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1742

wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1776

u32 val, old = 0;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1792

u32 val = wa->is_mcr ?

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1846

static bool is_nonpriv_flags_valid(u32 flags)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1861

whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1878

whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2169

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

217

u32 clear, u32 set, u32 read_mask, bool masked_reg)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

231

u32 clear, u32 set, u32 read_mask, bool masked_reg)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

246

wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

252

wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

258

wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

264

wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

270

wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2746

u32 mode;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

276

wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

282

wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2961

static bool mcr_range(struct drm_i915_private *i915, u32 offset)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

299

wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2996

u32 srm, *cs;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3012

u32 offset = i915_mmio_reg_offset(wa->reg);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3019

*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3036

u32 *results;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3043

wal->count * sizeof(u32));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

305

wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

311

wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

317

wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

324

u32 mask, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

331

u32 mask, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

998

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_workarounds_types.h

20

u32 clr;

sys/dev/pci/drm/i915/gt/intel_workarounds_types.h

21

u32 set;

sys/dev/pci/drm/i915/gt/intel_workarounds_types.h

22

u32 read;

sys/dev/pci/drm/i915/gt/intel_workarounds_types.h

24

u32 masked_reg:1;

sys/dev/pci/drm/i915/gt/intel_workarounds_types.h

25

u32 is_mcr:1;

sys/dev/pci/drm/i915/gt/ivb_clear_kernel.c

8

static const u32 ivb_clear_kernel[] = {

sys/dev/pci/drm/i915/gt/mock_engine.c

231

static u32 *mock_emit_breadcrumb(struct i915_request *request, u32 *cs)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1053

const u32 offset =

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1057

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1089

*cs++ = offset + idx * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1134

u32 *slot;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1533

u32 *map;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1584

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1718

u32 arb)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2708

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2828

tmp->ring->vma->size / sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2980

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3053

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3216

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3253

u32 *result;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3302

NUM_GPR * i * sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3645

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

377

tmp->ring->vma->size / sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4198

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4246

*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

524

memset32(ring->vaddr, STACK_MAGIC, ring->size / sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

714

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

822

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

896

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

100

u32 expected;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

29

const u32 *a = A, *b = B;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

39

static u32 read_timestamp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

53

u32 *out_cycles, ktime_t *out_dt)

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

56

u32 cycles[5];

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

99

u32 cycles;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

100

offset_in_page(sizeof(u32) * rq->fence.context);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

113

u32 *batch;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1286

static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1288

u32 count = i915_reset_count(&gt->i915->gpu_error);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

253

static u32 hws_seqno(const struct hang *h, const struct i915_request *rq)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

255

return READ_ONCE(h->seqno[rq->fence.context % (PAGE_SIZE/sizeof(u32))]);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

37

u32 *seqno;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

38

u32 *batch;

sys/dev/pci/drm/i915/gt/selftest_llc.c

28

u32 val;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1001

u32 len = hw[dw] & LRI_LENGTH_MASK;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1046

} while (dw < PAGE_SIZE / sizeof(u32) &&

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1063

u32 *sema)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1067

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1144

static struct i915_vma *load_context(struct intel_context *ce, u32 poison)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1147

u32 dw, *cs, *hw;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1148

u32 *defaults;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1171

u32 len = hw[dw] & LRI_LENGTH_MASK;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1204

} while (dw < PAGE_SIZE / sizeof(u32) &&

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1217

static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1221

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1265

static bool is_moving(u32 a, u32 b)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1274

u32 poison)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1276

u32 x, dw, *hw, *lrc;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1277

u32 *A[2], *B[2];

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1278

u32 *defaults;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1324

u32 len = hw[dw] & LRI_LENGTH_MASK;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

135

static int get_lri_mask(struct intel_engine_cs *engine, u32 lri)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1369

} while (dw < PAGE_SIZE / sizeof(u32) &&

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1410

static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1412

u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1520

const u32 poison[] = {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1588

#define CTX_BB_CANARY_INDEX (CTX_BB_CANARY_OFFSET / sizeof(u32))

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1590

static u32 *

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1592

u32 *cs, bool per_ctx)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1607

static u32 *

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1608

emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

161

u32 *lrc;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1613

static u32 *

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1614

emit_per_ctx_bb_canary(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1622

u32 *cs = context_wabb(ce, per_ctx);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1634

const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) -

sys/dev/pci/drm/i915/gt/selftest_lrc.c

169

lrc = (u32 *)__get_free_page(GFP_KERNEL); /* requires page alignment */

sys/dev/pci/drm/i915/gt/selftest_lrc.c

176

u32 *hw;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

194

u32 lri = READ_ONCE(hw[dw]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

195

u32 lri_mask;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

240

u32 offset = READ_ONCE(hw[dw]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

275

static int find_offset(const u32 *lri, u32 offset)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

279

for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

300

u32 reg;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

301

u32 offset;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

371

u32 *hw;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

414

u32 expected[MAX_IDX];

sys/dev/pci/drm/i915/gt/selftest_lrc.c

415

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

446

*cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

453

*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

536

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

565

__gpr_read(struct intel_context *ce, struct i915_vma *scratch, u32 *slot)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

567

const u32 offset =

sys/dev/pci/drm/i915/gt/selftest_lrc.c

571

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

599

*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

619

u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

622

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

740

const u32 offset =

sys/dev/pci/drm/i915/gt/selftest_lrc.c

744

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

770

*cs++ = offset + idx * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

790

u32 poison;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

793

static bool timestamp_advanced(u32 start, u32 end)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

800

u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

802

u32 timestamp;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

81

const u32 offset =

sys/dev/pci/drm/i915/gt/selftest_lrc.c

85

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

855

const u32 poison[] = {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

858

(u32)S32_MAX + 1,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

959

static u32 safe_poison(u32 offset, u32 poison)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

976

u32 dw, x, *cs, *hw;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

977

u32 *defaults;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

120

fn, sz, x * sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_migrate.c

148

u32 offset;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

259

u32 value,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

261

u32 sz, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

267

u32 *vaddr, val = 0;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

295

for (i = 0; i < sz / sizeof(u32); i++)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

339

fn, vaddr[x], val, x * sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_migrate.c

348

for (i = 0; i < sz / sizeof(u32); i++)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

374

ccs_bytes_per_chunk) * CHUNK_SZ / sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

375

int ccs_bytes_left = (ccs_bytes - i * PAGE_SIZE) / sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

381

fn, i * PAGE_SIZE + x * sizeof(u32), ccs_bytes);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

384

ccs_bytes_left * sizeof(u32)));

sys/dev/pci/drm/i915/gt/selftest_migrate.c

42

u32 sz, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

439

migrate_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

445

global_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

453

u32 value,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

466

u32 value,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

477

migrate_clear(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

48

u32 *vaddr;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

483

global_clear(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

557

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

622

sz = (rq->ring->space - rq->reserved_space) / sizeof(u32) -

sys/dev/pci/drm/i915/gt/selftest_migrate.c

624

sz = min_t(u32, sz, (SZ_1K - rq->reserved_space) / sizeof(u32) -

sys/dev/pci/drm/i915/gt/selftest_migrate.c

640

I915_EMIT_PTE_NUM_DWORDS * sizeof(u32)));

sys/dev/pci/drm/i915/gt/selftest_migrate.c

76

for (i = 0; i < sz / sizeof(u32); i++)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

86

for (i = 0; i < sz / sizeof(u32); i++)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

103

u32 addr, unsigned int count,

sys/dev/pci/drm/i915/gt/selftest_mocs.c

104

u32 *offset)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

107

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

109

GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));

sys/dev/pci/drm/i915/gt/selftest_mocs.c

121

addr += sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

122

*offset += sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

132

u32 *offset)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

135

u32 addr;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

150

u32 *offset)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

152

u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));

sys/dev/pci/drm/i915/gt/selftest_mocs.c

162

u32 **vaddr)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

165

u32 expect;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

182

static bool mcr_range(struct drm_i915_private *i915, u32 offset)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

194

u32 **vaddr)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

197

u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));

sys/dev/pci/drm/i915/gt/selftest_mocs.c

199

u32 expect;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

222

u32 offset;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

223

u32 *vaddr;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

226

memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));

sys/dev/pci/drm/i915/gt/selftest_rc6.c

156

static const u32 *__live_rc6_ctx(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/selftest_rc6.c

159

const u32 *result;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

160

u32 cmd;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

161

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

243

const u32 *res;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

41

u32 rc0_freq = 0;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

42

u32 rc6_freq = 0;

sys/dev/pci/drm/i915/gt/selftest_reset.c

128

u32 x;

sys/dev/pci/drm/i915/gt/selftest_reset.c

31

u32 *crc;

sys/dev/pci/drm/i915/gt/selftest_reset.c

41

crc = kmalloc_array(num_pages, sizeof(u32), GFP_KERNEL);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

104

static int mixed_contexts_sync(struct intel_engine_cs *engine, u32 *result)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

13

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

147

static int double_context_sync_00(struct intel_engine_cs *engine, u32 *result)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

174

static int kernel_context_sync_00(struct intel_engine_cs *engine, u32 *result)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

208

u32 *result;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1030

u32 pm_events;

sys/dev/pci/drm/i915/gt/selftest_rps.c

247

u32 cycles;

sys/dev/pci/drm/i915/gt/selftest_rps.c

298

u32 cycles_[5];

sys/dev/pci/drm/i915/gt/selftest_rps.c

330

u32 expected =

sys/dev/pci/drm/i915/gt/selftest_rps.c

46

const u32 *a = A, *b = B;

sys/dev/pci/drm/i915/gt/selftest_rps.c

481

u32 throttle = intel_uncore_read(gt->uncore,

sys/dev/pci/drm/i915/gt/selftest_rps.c

540

static u64 __measure_frequency(u32 *cntr, int duration_ms)

sys/dev/pci/drm/i915/gt/selftest_rps.c

553

static u64 measure_frequency_at(struct intel_rps *rps, u32 *cntr, int *freq)

sys/dev/pci/drm/i915/gt/selftest_rps.c

599

static bool scaled_within(u64 x, u64 y, u32 f_n, u32 f_d)

sys/dev/pci/drm/i915/gt/selftest_rps.c

60

u32 **cancel,

sys/dev/pci/drm/i915/gt/selftest_rps.c

61

u32 **counter)

sys/dev/pci/drm/i915/gt/selftest_rps.c

636

u32 *cancel, *cntr;

sys/dev/pci/drm/i915/gt/selftest_rps.c

72

u32 *base, *cs;

sys/dev/pci/drm/i915/gt/selftest_rps.c

775

u32 *cancel, *cntr;

sys/dev/pci/drm/i915/gt/selftest_rps.c

80

end = obj->base.size / sizeof(u32) - 1;

sys/dev/pci/drm/i915/gt/selftest_rps.c

901

u32 timeout;

sys/dev/pci/drm/i915/gt/selftest_rps.c

977

u32 timeout;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

127

u32 *max_act_freq)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

129

u32 step, max_freq, req_freq;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

130

u32 act_freq;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

163

u32 *max_act_freq)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

165

u32 step, min_freq, req_freq;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

166

u32 act_freq;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

250

static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

253

u32 perf_limit_reasons;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

26

static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

286

u32 slpc_min_freq, slpc_max_freq;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

333

u32 max_act_freq;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

39

static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

53

static int slpc_set_freq(struct intel_gt *gt, u32 freq)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

73

static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1032

u32 hwsp, dummy;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1205

WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1292

WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

199

u32 seqno;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

239

{ "INT_MAX+1", (u32)INT_MAX+1, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

308

u32 x;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

395

u32 id = random_engine(&prng);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

396

u32 seqno = prandom_u32_state(&prng);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

454

static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

456

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

485

checked_tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

695

const u32 *hwsp_seqno[2];

sys/dev/pci/drm/i915/gt/selftest_timeline.c

697

u32 seqno[2];

sys/dev/pci/drm/i915/gt/selftest_timeline.c

779

u32 seqno, u32 hwsp,

sys/dev/pci/drm/i915/gt/selftest_timeline.c

780

u32 *addr)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

782

const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));

sys/dev/pci/drm/i915/gt/selftest_timeline.c

783

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

814

u32 addr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

815

u32 *map;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

818

static bool cmp_lt(u32 a, u32 b)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

823

static bool cmp_gte(u32 a, u32 b)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

897

bool (*op)(u32 hwsp, u32 seqno))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

900

u32 offset, end;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

960

u32 seqno = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

48

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1007

u32 a, u32 b, i915_reg_t reg)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

102

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1023

u32 a, u32 b,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1026

u32 *a, *b;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

106

u32 srm, *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

158

*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

177

static u32

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

188

print_results(const struct intel_engine_cs *engine, const u32 *results)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

193

u32 expected = get_whitelist_reg(engine, i);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

194

u32 actual = results[i];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

206

u32 *vaddr;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

231

u32 expected = get_whitelist_reg(engine, i);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

232

u32 actual = vaddr[i];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

24

u32 reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

405

static u32 reg_write(u32 old, u32 new, u32 rsvd)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

418

static bool wo_register(struct intel_engine_cs *engine, u32 reg)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

436

static bool timestamp(const struct intel_engine_cs *engine, u32 reg)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

450

static bool ro_register(u32 reg)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

465

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

476

const u32 values[] = {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

506

u32 *cs, *results;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

508

sz = (2 * ARRAY_SIZE(values) + 1) * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

520

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

524

u32 srm, lrm, rsvd;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

525

u32 expect;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

587

*cs++ = lower_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

588

*cs++ = upper_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

600

*cs++ = lower_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

601

*cs++ = upper_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

604

GEM_BUG_ON(idx * sizeof(u32) > scratch->size);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

705

u32 w = values[v];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

716

u32 w = ~values[v];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

848

u32 srm, *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

869

u64 offset = i915_vma_offset(results) + sizeof(u32) * i;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

870

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

892

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

906

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

961

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

985

u32 a, u32 b, i915_reg_t reg)

sys/dev/pci/drm/i915/gt/st_shmem_utils.c

10

u32 datum = 0xdeadbeef, result;

sys/dev/pci/drm/i915/gt/st_shmem_utils.c

12

u32 *map;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

153

u32 task_status_padding;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

155

u32 status;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

166

u32 freq_padding;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

172

u32 freq;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

179

u32 size;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

180

u32 global_state;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

181

u32 display_data_addr;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

185

u32 bits[SLPC_OVERRIDE_BITFIELD_SIZE];

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

186

u32 values[SLPC_MAX_OVERRIDE_PARAMETERS];

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

211

u32 frequency_request:16;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

212

u32 reserved:12;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

213

u32 is_compute:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

214

u32 ignore_busyness:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

215

u32 is_minimum:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

216

u32 is_predefined:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

222

u32 compute:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

223

u32 async_flip:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

224

u32 media:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

225

u32 vsync_flip:1;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

226

u32 reserved:28;

sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

49

u32 head;

sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

50

u32 tail;

sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

51

u32 status;

sys/dev/pci/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

57

u32 reserved[13];

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

100

u32 engine; /* as per MAX_ENGINE_CLASS */

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

114

u32 owner;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

116

u32 info;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

120

u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

121

u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

122

u32 num_mmios;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

138

u32 owner;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

140

u32 info;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

23

u32 size;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

25

u32 rd;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

26

u32 wr;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

47

u32 eng_class;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

48

u32 eng_inst;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

49

u32 guc_id;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

50

u32 lrca;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

52

u32 vfid;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

53

u32 num_regs;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

70

u32 info;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

90

u32 flags;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

91

u32 mask;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

97

u32 num_regs;

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

98

u32 owner; /* see enum guc_capture_owner */

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

99

u32 type; /* see enum guc_capture_type */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

101

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

110

u32 length;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

116

u32 header_type; /* 0x4 for manifest type */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

117

u32 header_length; /* in dwords */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

118

u32 header_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

119

u32 flags;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

120

u32 vendor;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

121

u32 date;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

122

u32 size; /* In dwords, size of entire manifest (header + extensions) */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

123

u32 header_id;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

124

u32 internal_data;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

126

u32 security_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

128

u32 meu_manifest_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

131

u32 modulus_size; /* in dwords */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

132

u32 exponent_size; /* in dwords */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

19

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

20

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

37

u32 crc32;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

50

u32 signature;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

58

u32 crc32;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

60

u32 build_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

71

u32 type;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

75

u32 sub_partition_offset; /* from the base of the BPDT header */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

76

u32 sub_partition_size;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

81

u32 header_marker;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

84

u32 num_of_entries;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

89

u32 partition_name;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

90

u32 crc32;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

19

u32 fw_status = intel_uncore_read(uncore, HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

25

static u32 gsc_uc_get_fw_status(struct intel_uncore *uncore, bool needs_wakeref)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

265

u32 offset = i915_ggtt_offset(gsc->local);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

266

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

28

u32 fw_status = 0;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

68

static inline u32 cpd_entry_offset(const struct intel_gsc_cpd_entry *entry)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

128

u32 *marker = gsc->proxy.to_csme; /* first dw of the reply header */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

131

u32 size = ((struct gsc_proxy_msg *)gsc->proxy.to_gsc)->header.message_size;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

161

u32 source, u32 dest)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

163

u32 type = FIELD_GET(GSC_PROXY_TYPE, header->hdr);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

164

u32 length = FIELD_GET(GSC_PROXY_PAYLOAD_LENGTH, header->hdr);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

292

void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

59

u32 hdr;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

63

u32 source; /* Source of the Proxy message */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

64

u32 destination; /* Destination of the Proxy message */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

69

u32 status; /* Command status */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

93

u32 in_size;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.h

16

void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

146

static int gsc_allocate_and_map_vma(struct intel_gsc_uc *gsc, u32 size)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

21

u32 actions;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

350

u32 i;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

353

u32 status = intel_uncore_read(uncore,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h

37

u32 security_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h

46

u32 gsc_work_actions; /* protected by gt->irq_lock */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

109

u8 heci_client_id, u32 message_size,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

124

emit_gsc_heci_pkt_nonpriv(u32 *cmd, struct intel_gsc_heci_non_priv_pkt *pkt)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

141

u32 *cmd, int timeout_ms)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

17

u32 size_in;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

19

u32 size_out;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

24

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

45

u32 size_in, u64 addr_out,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

46

u32 size_out)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

22

u32 validity_marker;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

49

u32 message_size; /* lower 20 bits only, upper 12 are reserved */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

60

u32 flags;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

64

u32 status;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

68

u64 addr_in, u32 size_in,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

69

u64 addr_out, u32 size_out);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

71

u8 heci_client_id, u32 message_size,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

76

u32 size_in;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

78

u32 size_out;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

85

u8 heci_client_id, u32 msg_size,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

92

u32 *cs, int timeout_ms);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

128

u32 irq = gt->type == GT_MEDIA ? MTL_MGUC : GEN11_GUC;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

228

static u32 guc_ctl_debug_flags(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

230

u32 level = intel_guc_log_get_level(&guc->log);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

231

u32 flags = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

242

static u32 guc_ctl_feature_flags(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

245

u32 flags = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

263

static u32 guc_ctl_log_params_flags(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

266

u32 offset, flags;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

284

static u32 guc_ctl_ads_flags(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

286

u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

287

u32 flags = ads << GUC_ADS_ADDR_SHIFT;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

292

static u32 guc_ctl_wa_flags(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

295

u32 flags = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

348

static u32 guc_ctl_devid(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

362

u32 *params = guc->params;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

365

BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

407

u32 stamp = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

511

int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

512

u32 *response_buf, u32 response_buf_size)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

515

u32 header;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

568

u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

57

static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

576

u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

577

u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

618

int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

633

const u32 *payload, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

635

u32 msg;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

665

int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

667

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

682

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

777

struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

834

int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

860

u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

897

int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

933

u32 status = intel_uncore_read(uncore, GUC_STATUS);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

934

u32 i;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

197

u32 ads_regset_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

202

u32 ads_regset_count[I915_NUM_ENGINES];

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

206

u32 ads_golden_ctxt_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

208

u32 ads_waklv_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

210

u32 ads_capture_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

224

u32 params[GUC_CTL_MAX_DWORDS];

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

228

u32 base;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

241

u32 mmio_msg;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

278

u32 shift;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

312

u32 fast_response_selftest;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

336

inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

342

inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

343

u32 g2h_len_dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

350

intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

351

u32 *response_buf, u32 response_buf_size)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

358

const u32 *action,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

359

u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

360

u32 g2h_len_dw,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

416

static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

419

u32 offset = i915_ggtt_offset(vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

434

int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

435

u32 *response_buf, u32 response_buf_size);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

437

const u32 *payload, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

438

int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

441

struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

442

int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

444

int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

498

static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

505

static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

515

const u32 *msg, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

517

const u32 *msg, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

519

const u32 *msg, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

521

const u32 *msg, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

523

const u32 *msg, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

524

int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

552

const u32 *payload, u32 len);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

89

u32 serial_slot;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

92

u32 next_seqno;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

100

static u32 guc_ads_capture_size(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1035

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

105

static u32 guc_ads_private_data_size(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1063

u32 intel_guc_engine_usage_offset(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

110

static u32 guc_ads_regset_offset(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

115

static u32 guc_ads_golden_ctxt_offset(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

117

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

125

static u32 guc_ads_waklv_offset(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

127

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

135

static u32 guc_ads_capture_offset(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

137

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

145

static u32 guc_ads_private_data_offset(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

147

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

155

static u32 guc_ads_blob_size(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

165

u32 global_flags = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

194

static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

196

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

207

u32 scheduler_policies;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

261

u32 storage_used;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

262

u32 storage_max;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

276

u32 pos = regset->storage_used;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

315

u32 offset, u32 flags)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

317

u32 count = regset->storage_used - (regset->registers - regset->storage);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

363

i915_mcr_reg_t reg, u32 flags)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

391

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

455

u32 used = temp_set.storage_used;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

482

u32 addr_ggtt, offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

491

u32 count = guc->ads_regset_count[id];

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

535

#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

536

#define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

544

u32 addr_ggtt, offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

545

u32 total_size = 0, alloc_size, real_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

635

u32 addr_ggtt, total_size = 0, alloc_size, real_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

682

static u32 guc_get_capture_engine_mask(struct iosys_map *info_map, u32 capture_class)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

684

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

719

u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

750

u32 engine_mask = guc_get_capture_engine_mask(&info_map, j);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

830

static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, u32 *remain, u32 klv_id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

832

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

833

u32 klv_entry[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

84

static u32 guc_ads_regset_size(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

851

u32 offset, addr_ggtt, remain, size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

90

static u32 guc_ads_golden_ctxt_size(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

903

u32 base;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

917

u32 distdbreg = intel_uncore_read(gt->uncore,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

95

static u32 guc_ads_waklv_size(struct intel_guc *guc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

964

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.h

23

u32 intel_guc_engine_usage_offset(struct intel_guc *guc);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1008

u32 keep_reglist_mask)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1112

if (i % sizeof(u32)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1284

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1359

guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type,

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1360

u32 class, u32 id, u32 offset, u32 *is_ext)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1432

u32 is_ext;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

203

u32 owner, u32 type, u32 id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

221

u32 owner, u32 type, u32 id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

374

__stringify_type(u32 type)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

391

__stringify_engclass(u32 class)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

412

guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

415

u32 i = 0, j = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

453

guc_cap_list_num_regs(struct intel_guc_state_capture *gc, u32 owner, u32 type, u32 classid)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

473

guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

514

intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

523

intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid,

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

566

listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

588

int tmp = sizeof(u32) * 4;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

663

u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

779

u32 *dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

783

u32 *src_data;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

790

if (avail >= sizeof(u32)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

791

src_data = (u32 *)(buf->data + buf->rd);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.h

27

int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid,

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.h

29

int intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

100

u32 msg[] __counted_by(size);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1004

static bool ct_check_lost_and_found(struct intel_guc_ct *ct, u32 fence)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1034

static bool ct_check_lost_and_found(struct intel_guc_ct *ct, u32 fence)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1042

u32 len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, response->msg[0]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1043

u32 fence = FIELD_GET(GUC_CTB_MSG_0_FENCE, response->msg[0]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1044

const u32 *hxg = &response->msg[GUC_CTB_MSG_MIN_LEN];

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1045

const u32 *data = &hxg[GUC_HXG_MSG_MIN_LEN];

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1046

u32 datalen = len - GUC_HXG_MSG_MIN_LEN;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1111

const u32 *hxg;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1112

const u32 *payload;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1113

u32 hxg_len, action, len;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1215

const u32 *hxg = &request->msg[GUC_CTB_MSG_MIN_LEN];

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1216

u32 action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1250

u32 origin, type;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1251

u32 *hxg;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1289

u32 format = FIELD_GET(GUC_CTB_MSG_0_FORMAT, msg->msg[0]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

163

u32 space;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

176

u32 *cmds, u32 size_in_bytes, u32 resv_space)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

188

static int guc_action_control_ctb(struct intel_guc *guc, u32 control)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

190

u32 request[HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

220

u32 desc_addr, u32 buff_addr, u32 size)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

262

u32 blob_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

263

u32 cmds_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

264

u32 resv_space;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

266

u32 *cmds;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

334

u32 base, desc, cmds, size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

408

static void ct_track_lost_and_found(struct intel_guc_ct *ct, u32 fence, u32 action)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

425

static u32 ct_get_next_fence(struct intel_guc_ct *ct)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

432

const u32 *action,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

433

u32 len /* in dwords */,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

434

u32 fence, u32 flags)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

438

u32 tail = ctb->tail;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

439

u32 size = ctb->size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

440

u32 header;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

441

u32 hxg;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

442

u32 type;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

443

u32 *cmds = ctb->cmds;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

540

static int wait_for_ct_request_update(struct intel_guc_ct *ct, struct ct_request *req, u32 *status)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

598

static inline bool g2h_has_room(struct intel_guc_ct *ct, u32 g2h_len_dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

609

static inline void g2h_reserve_space(struct intel_guc_ct *ct, u32 g2h_len_dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

619

static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

624

static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

628

u32 head;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

629

u32 space;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

650

static int has_room_nb(struct intel_guc_ct *ct, u32 h2g_dw, u32 g2h_dw)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

682

const u32 *action,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

683

u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

684

u32 flags)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

688

u32 g2h_len_dw = G2H_LEN_DW(flags);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

689

u32 fence;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

713

const u32 *action,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

714

u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

715

u32 *response_buf,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

716

u32 response_buf_size,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

717

u32 *status)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

724

u32 fence;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

835

int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

836

u32 *response_buf, u32 response_buf_size, u32 flags)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

838

u32 status = ~0; /* undefined */

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

868

static struct ct_incoming_msg *ct_alloc_msg(u32 num_dwords)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

891

u32 head = ctb->head;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

892

u32 tail = READ_ONCE(desc->tail);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

893

u32 size = ctb->size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

894

u32 *cmds = ctb->cmds;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

898

u32 header;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

904

u32 status = desc->status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

91

u32 fence;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

92

u32 status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

93

u32 response_len;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

94

u32 *response_buf;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

955

if (unlikely(len > (u32)available)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

99

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

133

int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

134

u32 *response_buf, u32 response_buf_size, u32 flags);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

48

u32 *cmds;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

49

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

50

u32 resv_space;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

51

u32 tail;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h

52

u32 head;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

107

static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool *success)

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

109

u32 val = intel_uncore_read(uncore, GUC_STATUS);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

110

u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

111

u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

170

u32 status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

173

u32 before_freq;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

214

u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

215

u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

26

u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

64

u32 rsa[UOS_RSA_SCRATCH_COUNT];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

201

u32 header;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

202

u32 context_desc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

203

u32 submit_element_info;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

204

u32 fence_id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

208

u32 stage_id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

210

u32 head;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

211

u32 tail;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

212

u32 error_offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

214

u32 wq_size_bytes;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

215

u32 wq_status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

216

u32 engine_presence;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

217

u32 priority;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

218

u32 reserved[36];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

222

u32 head;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

223

u32 tail;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

224

u32 error_offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

225

u32 wq_status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

226

u32 reserved[28];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

231

u32 flags;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

232

u32 context_idx;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

233

u32 engine_class;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

234

u32 engine_submit_mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

235

u32 wq_desc_lo;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

236

u32 wq_desc_hi;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

237

u32 wq_base_lo;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

238

u32 wq_base_hi;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

239

u32 wq_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

240

u32 hwlrca_lo;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

241

u32 hwlrca_hi;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

255

u32 hw_context_desc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

256

u32 slpm_perf_mode_hint; /* SPLC v1 only */

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

257

u32 slpm_freq_hint;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

258

u32 engine_submit_mask; /* In logical space */

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

261

u32 priority;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

262

u32 process_desc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

263

u32 wq_addr;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

264

u32 wq_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

265

u32 context_flags; /* CONTEXT_REGISTRATION_* */

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

267

u32 execution_quantum;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

271

u32 preemption_timeout;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

272

u32 policy_flags; /* CONTEXT_POLICY_* */

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

273

u32 reserved1[19];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

278

u32 kl;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

279

u32 value;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

284

u32 action;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

285

u32 ctx_id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

295

u32 action;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

309

u32 data[MAX_SCHEDULING_POLICY_SIZE];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

339

static inline u32 guc_policy_max_exec_quantum_ms(void)

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

345

static inline u32 guc_policy_max_preempt_timeout_ms(void)

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

352

u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

356

u32 dpc_promote_time;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

359

u32 is_valid;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

363

u32 max_num_work_items;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

365

u32 global_flags;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

366

u32 reserved[4];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

371

u32 offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

372

u32 value;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

373

u32 flags;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

380

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

385

u32 address;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

393

u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

394

u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

423

u32 reserved0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

424

u32 scheduler_policies;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

425

u32 gt_system_info;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

426

u32 reserved1;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

427

u32 control_data;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

428

u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

429

u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

430

u32 private_data;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

431

u32 reserved2;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

432

u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

433

u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

434

u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

435

u32 wa_klv_addr_lo;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

436

u32 wa_klv_addr_hi;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

437

u32 wa_klv_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

438

u32 reserved[11];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

443

u32 current_context_index;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

444

u32 last_switch_in_stamp;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

445

u32 reserved0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

446

u32 total_runtime;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

447

u32 reserved1[4];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

485

u32 marker[2];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

486

u32 read_ptr;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

487

u32 write_ptr;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

488

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

489

u32 sampled_write_ptr;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

490

u32 wrap_offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

493

u32 flush_to_file:1;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

494

u32 buffer_full_cnt:4;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

495

u32 reserved:27;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

497

u32 flags;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

499

u32 version;

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

36

u32 ggtt_offset, u32 ggtt_size)

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

38

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

77

u32 ggtt_offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

125

static u32 intel_guc_log_section_size_crash(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

132

static u32 intel_guc_log_section_size_debug(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

139

u32 intel_guc_log_section_size_capture(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

146

static u32 intel_guc_log_size(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

186

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

196

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

205

bool default_logging, u32 verbosity)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

207

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

36

u32 max;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

37

u32 flag;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

38

u32 default_val;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

612

static u32 __get_default_log_level(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

642

u32 guc_log_size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

687

int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

911

u32 *page;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

925

page = (u32 *)__get_free_page(GFP_KERNEL);

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

943

for (j = 0; j < PAGE_SIZE / sizeof(u32); j += 4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

102

static inline u32 intel_guc_log_get_level(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

111

u32 intel_guc_log_section_size_capture(struct intel_guc_log *log);

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

43

u32 level;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

58

u32 flag; /* GuC API units flag */

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

73

u32 full_count;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

78

u32 sampled_overflow;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

79

u32 overflow;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

80

u32 flush;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h

93

int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

15

static u32 obj_to_guc_log_dump_size(struct drm_i915_gem_object *obj)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

17

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

31

static u32 guc_log_dump_size(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

61

static u32 guc_load_err_dump_size(struct intel_guc_log *log)

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

36

u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL :

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

38

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

116

u32 db_status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

120

u32 cookie;

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

121

u32 reserved[14];

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

121

static u32 slpc_get_state(struct intel_guc_slpc *slpc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

127

drm_clflush_virt_range(slpc->vaddr, sizeof(u32));

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

133

static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

135

u32 request[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

148

static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

157

static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

159

u32 request[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

177

static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

179

u32 request[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

195

u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

207

static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

222

static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

278

u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

332

static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

334

u32 request[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

350

u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

371

static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

382

static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

428

int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

465

int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

522

int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

564

int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

581

int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

595

int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

611

int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

641

u32 pm_intrmsk_mbz = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

810

int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

88

u32 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

37

int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

38

int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

39

int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

40

int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

41

int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

43

int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

48

int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h

49

int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

26

u32 min_freq;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

27

u32 rp0_freq;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

28

u32 rp1_freq;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

29

u32 boost_freq;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

32

u32 min_freq_softlimit;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

33

u32 max_freq_softlimit;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

37

u32 power_profile;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

40

u32 media_ratio_mode;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h

49

u32 num_boosts;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1182

__extend_last_switch(struct intel_guc *guc, u64 *prev_start, u32 new_start)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1184

u32 gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1185

u32 gt_stamp_last = lower_32_bits(guc->timestamp.gt_stamp);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1229

u32 *last_in, u32 *id, u32 *total)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1247

u32 last_in, u32 id, u32 total)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1265

u32 last_switch, ctx_id, total;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1280

stats->total_gt_clks += (u32)(total - stats->prev_total);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1285

static u32 gpm_timestamp_shift(struct intel_gt *gt)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1288

u32 reg;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1299

u32 gt_stamp_lo, gt_stamp_hi;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1329

u32 reset_count;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1590

u32 offset = intel_guc_engine_usage_offset(guc);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1591

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1777

static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1862

u32 head;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2459

u32 guc_id,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2460

u32 offset,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2464

u32 action[4 + MAX_ENGINE_INSTANCE];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2487

u32 action[13 + (MAX_ENGINE_INSTANCE * 2)];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2489

u32 next_id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2525

u32 guc_id,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2526

u32 offset,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2529

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2543

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2569

u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool_v69) +

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2623

u32 guc_id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2625

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2635

static int deregister_context(struct intel_context *ce, u32 guc_id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2655

static inline u32 get_children_go_value(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2660

static inline u32 get_children_join_value(struct intel_context *ce,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2667

u32 count;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2671

static u32 __guc_context_policy_action_size(struct context_policy *policy)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2676

return bytes / sizeof(u32);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2687

static void __guc_context_policy_add_##func(struct context_policy *policy, u32 data) \

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2709

return guc_submission_send_busy_loop(guc, (u32 *)&policy->h2g,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2719

u32 execution_quantum;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2720

u32 preemption_timeout;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2721

u32 slpc_ctx_freq_req = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2775

static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2799

u32 ctx_id = ce->guc_id.id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2868

u32 ctx_id = ce->guc_id.id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2932

u32 ctx_id = ce->guc_id.id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3054

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3070

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3235

u32 preemption_timeout)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3244

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

359

static inline u32 context_blocked(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3632

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4204

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4207

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4209

static u32 *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4211

u32 *cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4212

static u32 *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4214

u32 *cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

430

u32 semaphore;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

431

u8 unused[CACHELINE_BYTES - sizeof(u32)];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

446

u32 wq[WQ_SIZE / sizeof(u32)];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

449

static u32 __get_parent_scratch_offset(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

456

static u32 __get_wq_offset(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4678

u32 max_words, num_words;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4679

u32 count;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4684

static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4686

u32 *start = (void *)&policy->h2g;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4687

u32 *end = policy->h2g.data + policy->num_words;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4704

u32 action, u32 *data, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4706

u32 *klv_ptr = policy->h2g.data + policy->num_words;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4711

memcpy(klv_ptr, data, sizeof(u32) * len);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4721

ret = intel_guc_send(guc, (u32 *)&policy->h2g,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4752

u32 yield[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

477

LRC_STATE_OFFSET) / sizeof(u32)));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4770

u32 val;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4882

g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4905

static void wait_wake_outstanding_tlb_g2h(struct intel_guc *guc, u32 seqno)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4923

const u32 *payload, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

496

static u32 *get_wq_pointer(struct intel_context *ce, u32 wqi_size)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4971

u32 seqno;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4972

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4980

u32 size = ARRAY_SIZE(action);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5054

const u32 *msg,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5055

u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5058

u32 ctx_id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5105

const u32 *msg,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5106

u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5110

u32 ctx_id;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

513

return &__get_parent_scratch(ce)->wq[ce->parallel.guc.wqi_tail / sizeof(u32)];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

516

static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5249

const u32 *msg, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

525

static struct guc_lrc_desc_v69 *__get_lrc_desc_v69(struct intel_guc *guc, u32 index)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5284

const u32 *msg, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5286

u32 status;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5348

const u32 *msg, u32 len)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5352

u32 reason;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

539

u32 size;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5615

static inline u32 get_children_go_addr(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5624

static inline u32 get_children_join_addr(struct intel_context *ce,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5639

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5643

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

566

static inline void _reset_lrc_desc_v69(struct intel_guc *guc, u32 id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5686

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5691

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5729

static u32 *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5731

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

574

static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5779

static u32 *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5781

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5784

__maybe_unused u32 *before_fini_breadcrumb_user_interrupt_cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5785

__maybe_unused u32 *start_fini_breadcrumb_cs = cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

579

static inline void set_ctx_id_mapping(struct intel_guc *guc, u32 id,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5794

memset(cs, 0, sizeof(u32) *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5823

static u32 *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5825

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5855

static u32 *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5857

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5860

__maybe_unused u32 *before_fini_breadcrumb_user_interrupt_cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5861

__maybe_unused u32 *start_fini_breadcrumb_cs = cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5870

memset(cs, 0, sizeof(u32) *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

593

static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

618

const u32 *action,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

619

u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

620

u32 g2h_len_dw,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

700

u32 action[3];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

702

u32 g2h_len_dw = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

814

static u32 wq_space_until_wrap(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

819

static void write_wqi(struct intel_context *ce, u32 wqi_size)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

835

u32 *wqi = get_wq_pointer(ce, wq_space_until_wrap(ce));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

836

u32 len_dw = wq_space_until_wrap(ce) / sizeof(u32) - 1;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

855

sizeof(u32);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

856

u32 *wqi;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

857

u32 len_dw = (wqi_size / sizeof(u32)) - 1;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

473

u32 before_freq;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

595

u32 status = 0;

sys/dev/pci/drm/i915/gt/uc/intel_huc.h

39

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_huc.h

40

u32 value;

sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c

125

static inline u32 entry_offset(const struct intel_gsc_cpd_entry *entry)

sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c

224

u32 offset = entry_offset(entry);

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

190

u32 val;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

367

u32 base = intel_wopcm_guc_base(&gt->wopcm);

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

368

u32 size = intel_wopcm_guc_size(&gt->wopcm);

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

369

u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

370

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

61

u32 guc_status;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1014

static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1019

u32 offset = uc_fw->type * INTEL_UC_RSVD_GGTT_PER_FW;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1047

u32 pte_flags = 0;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1088

static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1160

int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1337

size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1340

u32 size = min_t(u32, uc_fw->rsa_size, max_len);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1341

u32 offset = uc_fw->dma_start_offset + sizeof(struct uc_css_header) + uc_fw->ucode_size;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1355

u32 len = min_t(u32, size, PAGE_SIZE - offset);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1375

u32 len = min_t(u32, size, PAGE_SIZE - offset);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

262

u32 count;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

288

u32 fw_count;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

347

u32 fw_count;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

582

static void uc_unpack_css_version(struct intel_uc_fw_ver *ver, u32 css_value)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

657

css->exponent_size_dw) * sizeof(u32);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

666

uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

669

uc_fw->rsa_size = css->key_size_dw * sizeof(u32);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

720

u32 delta = uc_fw->dma_start_offset;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

118

u32 rsa_size;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

119

u32 ucode_size;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

120

u32 private_data_size;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

122

u32 dma_start_offset;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

277

static inline u32 __intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

290

static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

306

int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 offset, u32 dma_flags);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

310

size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

70

u32 major;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

71

u32 minor;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

72

u32 patch;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h

73

u32 build;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

50

u32 module_type;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

55

u32 header_size_dw;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

56

u32 header_version;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

57

u32 module_id;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

58

u32 module_vendor;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

59

u32 date;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

63

u32 size_dw; /* uCode plus header_size_dw */

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

64

u32 key_size_dw;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

65

u32 modulus_size_dw;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

66

u32 exponent_size_dw;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

67

u32 time;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

73

u32 sw_version;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

77

u32 vf_version;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

78

u32 reserved0[12];

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

80

u32 private_data_size; /* only applies to GuC */

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

81

u32 reserved1;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw_abi.h

83

u32 header_info;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

295

u32 action[] = {

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

41

u32 guc_status;

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

42

u32 old_beat;

sys/dev/pci/drm/i915/gvt/aperture_gm.c

131

u32 fence, u64 value)

sys/dev/pci/drm/i915/gvt/aperture_gm.c

173

u32 i;

sys/dev/pci/drm/i915/gvt/cfg_space.c

170

u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);

sys/dev/pci/drm/i915/gvt/cfg_space.c

171

u32 new = *(u32 *)(p_data);

sys/dev/pci/drm/i915/gvt/cfg_space.c

184

u32 new = *(u32 *)(p_data);

sys/dev/pci/drm/i915/gvt/cfg_space.c

290

ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);

sys/dev/pci/drm/i915/gvt/cfg_space.c

299

*(u32 *)p_data);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1023

u32 data = cmd_val(s, index + 1);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1115

ret |= cmd_address_audit(s, gma, sizeof(u32), false);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1139

ret |= cmd_address_audit(s, gma, sizeof(u32), false);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1189

u32 hws_pga, val;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1300

u32 dword0, dword1, dword2;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1301

u32 v;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1340

u32 dword0 = cmd_val(s, 0);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1341

u32 dword1 = cmd_val(s, 1);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1342

u32 dword2 = cmd_val(s, 2);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1343

u32 plane = (dword0 & GENMASK(12, 8)) >> 8;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1397

u32 stride, tile;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1485

u32 valid_len = CMD_LEN(1);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1518

static bool is_wait_for_flip_pending(u32 cmd)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1530

u32 cmd = cmd_val(s, 0);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1565

u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1610

int op_size = (cmd_length(s) - 3) * sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1613

u32 valid_len = CMD_LEN(2);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1668

sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1670

u32 valid_len = CMD_LEN(1);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1720

u32 hws_pga, val;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1721

u32 valid_len = CMD_LEN(2);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1820

u32 cmd_len = 0;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1823

u32 cmd;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1879

u32 cmd = *(u32 *)va;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2019

s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2023

s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2024

s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2733

u32 cmd;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2895

ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3057

u32 per_ctx_start[CACHELINE_DWORDS] = {};

sys/dev/pci/drm/i915/gvt/cmd_parser.c

413

u32 opcode;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

426

u32 flag;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

455

u32 len;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

460

u32 valid_len;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

656

static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

682

get_cmd_info(struct intel_gvt *gvt, u32 cmd,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

685

u32 opcode;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

694

static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

699

static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

718

static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

723

static inline u32 cmd_val(struct parser_exec_state *s, int index)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

762

s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

770

s->ip_va += 8 * sizeof(u32);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

828

static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

856

u32 base = s->workload->engine->mmio_base;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

899

u32 ctx_sr_ctl;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

900

u32 *vreg, vreg_old;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

975

u32 cmdval_new, cmdval;

sys/dev/pci/drm/i915/gvt/debugfs.c

114

u32 diff = node->preg ^ node->vreg;

sys/dev/pci/drm/i915/gvt/debugfs.c

37

u32 offset;

sys/dev/pci/drm/i915/gvt/debugfs.c

38

u32 preg;

sys/dev/pci/drm/i915/gvt/debugfs.c

39

u32 vreg;

sys/dev/pci/drm/i915/gvt/debugfs.c

59

u32 offset, void *data)

sys/dev/pci/drm/i915/gvt/debugfs.c

63

u32 preg, vreg;

sys/dev/pci/drm/i915/gvt/display.c

53

u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);

sys/dev/pci/drm/i915/gvt/display.h

115

u32 vrefresh_k;

sys/dev/pci/drm/i915/gvt/display.h

120

u32 vrefresh_k;

sys/dev/pci/drm/i915/gvt/display.h

68

u32 value;

sys/dev/pci/drm/i915/gvt/dmabuf.c

371

pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id)

sys/dev/pci/drm/i915/gvt/edid.c

102

static inline int bxt_get_port_from_gmbus0(u32 gmbus0)

sys/dev/pci/drm/i915/gvt/edid.c

116

static inline int get_port_from_gmbus0(u32 gmbus0)

sys/dev/pci/drm/i915/gvt/edid.c

185

u32 target_addr;

sys/dev/pci/drm/i915/gvt/edid.c

186

u32 wvalue = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/edid.c

300

u32 reg_data = 0;

sys/dev/pci/drm/i915/gvt/edid.c

347

u32 value = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/edid.c

358

u32 wvalue = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/edid.c

488

u32 value = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/edid.c

86

static inline int cnp_get_port_from_gmbus0(u32 gmbus0)

sys/dev/pci/drm/i915/gvt/execlist.c

130

u32 write_pointer;

sys/dev/pci/drm/i915/gvt/execlist.c

131

u32 ctx_status_ptr_reg, ctx_status_buf_reg, offset;

sys/dev/pci/drm/i915/gvt/execlist.c

258

u32 status_reg =

sys/dev/pci/drm/i915/gvt/execlist.c

506

u32 ctx_status_ptr_reg;

sys/dev/pci/drm/i915/gvt/execlist.c

95

u32 status_reg =

sys/dev/pci/drm/i915/gvt/execlist.h

101

u32 idle_to_active :1;

sys/dev/pci/drm/i915/gvt/execlist.h

102

u32 preempted :1;

sys/dev/pci/drm/i915/gvt/execlist.h

103

u32 element_switch :1;

sys/dev/pci/drm/i915/gvt/execlist.h

104

u32 active_to_idle :1;

sys/dev/pci/drm/i915/gvt/execlist.h

105

u32 context_complete :1;

sys/dev/pci/drm/i915/gvt/execlist.h

106

u32 wait_on_sync_flip :1;

sys/dev/pci/drm/i915/gvt/execlist.h

107

u32 wait_on_vblank :1;

sys/dev/pci/drm/i915/gvt/execlist.h

108

u32 wait_on_semaphore :1;

sys/dev/pci/drm/i915/gvt/execlist.h

109

u32 wait_on_scanline :1;

sys/dev/pci/drm/i915/gvt/execlist.h

110

u32 reserved :2;

sys/dev/pci/drm/i915/gvt/execlist.h

111

u32 semaphore_wait_mode :1;

sys/dev/pci/drm/i915/gvt/execlist.h

112

u32 display_plane :3;

sys/dev/pci/drm/i915/gvt/execlist.h

113

u32 lite_restore :1;

sys/dev/pci/drm/i915/gvt/execlist.h

114

u32 reserved_2 :16;

sys/dev/pci/drm/i915/gvt/execlist.h

118

u32 udw;

sys/dev/pci/drm/i915/gvt/execlist.h

119

u32 context_id;

sys/dev/pci/drm/i915/gvt/execlist.h

124

u32 addr;

sys/dev/pci/drm/i915/gvt/execlist.h

125

u32 val;

sys/dev/pci/drm/i915/gvt/execlist.h

130

u32 nop1;

sys/dev/pci/drm/i915/gvt/execlist.h

131

u32 lri_cmd_1;

sys/dev/pci/drm/i915/gvt/execlist.h

146

u32 nop2;

sys/dev/pci/drm/i915/gvt/execlist.h

147

u32 nop3;

sys/dev/pci/drm/i915/gvt/execlist.h

148

u32 nop4;

sys/dev/pci/drm/i915/gvt/execlist.h

149

u32 lri_cmd_2;

sys/dev/pci/drm/i915/gvt/execlist.h

159

u32 data[4];

sys/dev/pci/drm/i915/gvt/execlist.h

160

u32 index;

sys/dev/pci/drm/i915/gvt/execlist.h

165

u32 index;

sys/dev/pci/drm/i915/gvt/execlist.h

42

u32 ldw;

sys/dev/pci/drm/i915/gvt/execlist.h

44

u32 valid : 1;

sys/dev/pci/drm/i915/gvt/execlist.h

45

u32 force_pd_restore : 1;

sys/dev/pci/drm/i915/gvt/execlist.h

46

u32 force_restore : 1;

sys/dev/pci/drm/i915/gvt/execlist.h

47

u32 addressing_mode : 2;

sys/dev/pci/drm/i915/gvt/execlist.h

48

u32 llc_coherency : 1;

sys/dev/pci/drm/i915/gvt/execlist.h

49

u32 fault_handling : 2;

sys/dev/pci/drm/i915/gvt/execlist.h

50

u32 privilege_access : 1;

sys/dev/pci/drm/i915/gvt/execlist.h

51

u32 reserved : 3;

sys/dev/pci/drm/i915/gvt/execlist.h

52

u32 lrca : 20;

sys/dev/pci/drm/i915/gvt/execlist.h

56

u32 udw;

sys/dev/pci/drm/i915/gvt/execlist.h

57

u32 context_id;

sys/dev/pci/drm/i915/gvt/execlist.h

63

u32 ldw;

sys/dev/pci/drm/i915/gvt/execlist.h

65

u32 current_execlist_pointer :1;

sys/dev/pci/drm/i915/gvt/execlist.h

66

u32 execlist_write_pointer :1;

sys/dev/pci/drm/i915/gvt/execlist.h

67

u32 execlist_queue_full :1;

sys/dev/pci/drm/i915/gvt/execlist.h

68

u32 execlist_1_valid :1;

sys/dev/pci/drm/i915/gvt/execlist.h

69

u32 execlist_0_valid :1;

sys/dev/pci/drm/i915/gvt/execlist.h

70

u32 last_ctx_switch_reason :9;

sys/dev/pci/drm/i915/gvt/execlist.h

71

u32 current_active_elm_status :2;

sys/dev/pci/drm/i915/gvt/execlist.h

72

u32 arbitration_enable :1;

sys/dev/pci/drm/i915/gvt/execlist.h

73

u32 execlist_1_active :1;

sys/dev/pci/drm/i915/gvt/execlist.h

74

u32 execlist_0_active :1;

sys/dev/pci/drm/i915/gvt/execlist.h

75

u32 reserved :13;

sys/dev/pci/drm/i915/gvt/execlist.h

79

u32 udw;

sys/dev/pci/drm/i915/gvt/execlist.h

80

u32 context_id;

sys/dev/pci/drm/i915/gvt/execlist.h

86

u32 dw;

sys/dev/pci/drm/i915/gvt/execlist.h

88

u32 write_ptr :3;

sys/dev/pci/drm/i915/gvt/execlist.h

89

u32 reserved :5;

sys/dev/pci/drm/i915/gvt/execlist.h

90

u32 read_ptr :3;

sys/dev/pci/drm/i915/gvt/execlist.h

91

u32 reserved2 :5;

sys/dev/pci/drm/i915/gvt/execlist.h

92

u32 mask :16;

sys/dev/pci/drm/i915/gvt/execlist.h

99

u32 ldw;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

155

static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,

sys/dev/pci/drm/i915/gvt/fb_decoder.c

156

u32 tiled, int stride_mask, int bpp)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

161

u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

162

u32 stride = stride_reg;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

217

u32 val, fmt;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

294

u32 width; /* In pixel */

sys/dev/pci/drm/i915/gvt/fb_decoder.c

295

u32 height; /* In lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.c

348

u32 val, mode, index;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

349

u32 alpha_plane, alpha_force;

sys/dev/pci/drm/i915/gvt/fb_decoder.h

108

u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

110

u32 hw_format; /* format field in the PRI_CTL register */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

111

u32 drm_format; /* format in DRM definition */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

112

u32 base; /* framebuffer base in graphics memory */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

114

u32 x_offset; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

115

u32 y_offset; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

116

u32 width; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

117

u32 height; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

118

u32 stride; /* in bytes */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

125

u32 hw_format; /* format field in the SPR_CTL register */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

126

u32 drm_format; /* format in DRM definition */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

127

u32 base; /* sprite base in graphics memory */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

129

u32 x_pos; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

130

u32 y_pos; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

131

u32 x_offset; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

132

u32 y_offset; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

133

u32 width; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

134

u32 height; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

135

u32 stride; /* in bytes */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

142

u32 drm_format; /* format in DRM definition */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

143

u32 base; /* cursor base in graphics memory */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

145

u32 x_pos; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

146

u32 y_pos; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

149

u32 width; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

150

u32 height; /* in lines */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

151

u32 x_hot; /* in pixels */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

152

u32 y_hot; /* in pixels */

sys/dev/pci/drm/i915/gvt/firmware.c

43

u32 crc32; /* protect the data after this field */

sys/dev/pci/drm/i915/gvt/firmware.c

44

u32 version;

sys/dev/pci/drm/i915/gvt/gtt.c

2728

u32 index;

sys/dev/pci/drm/i915/gvt/gtt.c

2729

u32 num_entries;

sys/dev/pci/drm/i915/gvt/gtt.c

2771

u32 idx, num_low, num_hi, offset;

sys/dev/pci/drm/i915/gvt/gtt.c

57

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)

sys/dev/pci/drm/i915/gvt/gtt.c

993

u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &

sys/dev/pci/drm/i915/gvt/gvt.h

109

u32 pmcsr_off;

sys/dev/pci/drm/i915/gvt/gvt.h

122

u32 gfn[INTEL_GVT_OPREGION_PAGES];

sys/dev/pci/drm/i915/gvt/gvt.h

168

u32 lrca;

sys/dev/pci/drm/i915/gvt/gvt.h

209

u32 hws_pga[I915_NUM_ENGINES];

sys/dev/pci/drm/i915/gvt/gvt.h

220

u32 scan_nonprivbb;

sys/dev/pci/drm/i915/gvt/gvt.h

359

u32 *tlb_mmio_offset_list;

sys/dev/pci/drm/i915/gvt/gvt.h

360

u32 tlb_mmio_offset_list_cnt;

sys/dev/pci/drm/i915/gvt/gvt.h

361

u32 *mocs_mmio_offset_list;

sys/dev/pci/drm/i915/gvt/gvt.h

362

u32 mocs_mmio_offset_list_cnt;

sys/dev/pci/drm/i915/gvt/gvt.h

453

u32 fence, u64 value);

sys/dev/pci/drm/i915/gvt/gvt.h

460

(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

sys/dev/pci/drm/i915/gvt/gvt.h

462

(*(u32 *)(vgpu->mmio.vreg + (offset)))

sys/dev/pci/drm/i915/gvt/gvt.h

473

u32 offset, u32 val, bool low)

sys/dev/pci/drm/i915/gvt/gvt.h

475

u32 *pval;

sys/dev/pci/drm/i915/gvt/gvt.h

479

pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);

sys/dev/pci/drm/i915/gvt/gvt.h

535

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);

sys/dev/pci/drm/i915/gvt/gvt.h

558

int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);

sys/dev/pci/drm/i915/gvt/gvt.h

560

int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);

sys/dev/pci/drm/i915/gvt/gvt.h

67

u32 max_support_vgpus;

sys/dev/pci/drm/i915/gvt/gvt.h

68

u32 cfg_space_size;

sys/dev/pci/drm/i915/gvt/gvt.h

69

u32 mmio_size;

sys/dev/pci/drm/i915/gvt/gvt.h

70

u32 mmio_bar;

sys/dev/pci/drm/i915/gvt/gvt.h

72

u32 gtt_start_offset;

sys/dev/pci/drm/i915/gvt/gvt.h

73

u32 gtt_entry_size;

sys/dev/pci/drm/i915/gvt/gvt.h

74

u32 gtt_entry_size_shift;

sys/dev/pci/drm/i915/gvt/gvt.h

76

u32 max_surface_size;

sys/dev/pci/drm/i915/gvt/gvt.h

92

u32 size;

sys/dev/pci/drm/i915/gvt/handlers.c

1009

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

1029

u32 pipe = DSPSURF_TO_PIPE(display, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1051

u32 pipe = SPRSURF_TO_PIPE(offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1117

static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,

sys/dev/pci/drm/i915/gvt/handlers.c

1189

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

124

static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,

sys/dev/pci/drm/i915/gvt/handlers.c

125

u16 flags, u32 addr_mask, u32 ro_mask, u32 device,

sys/dev/pci/drm/i915/gvt/handlers.c

1258

u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);

sys/dev/pci/drm/i915/gvt/handlers.c

129

u32 start, end, i;

sys/dev/pci/drm/i915/gvt/handlers.c

1356

*(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);

sys/dev/pci/drm/i915/gvt/handlers.c

1374

static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,

sys/dev/pci/drm/i915/gvt/handlers.c

1392

unsigned int offset, u32 value)

sys/dev/pci/drm/i915/gvt/handlers.c

1432

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

1485

offset, bytes, *(u32 *)p_data);

sys/dev/pci/drm/i915/gvt/handlers.c

1537

u32 data = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1582

u32 val = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1638

u32 mode;

sys/dev/pci/drm/i915/gvt/handlers.c

1657

u32 trtte = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1680

u32 v = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

1702

u32 value = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1703

u32 cmd = value & 0xff;

sys/dev/pci/drm/i915/gvt/handlers.c

1704

u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);

sys/dev/pci/drm/i915/gvt/handlers.c

1760

u32 value = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1791

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1806

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1820

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1833

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1846

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1847

u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;

sys/dev/pci/drm/i915/gvt/handlers.c

1867

u32 v = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1879

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1897

u32 v = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

1999

u32 data = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

2038

u32 data = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

2044

(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);

sys/dev/pci/drm/i915/gvt/handlers.c

2047

(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);

sys/dev/pci/drm/i915/gvt/handlers.c

2129

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

2147

u32 data = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

2149

(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);

sys/dev/pci/drm/i915/gvt/handlers.c

231

u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;

sys/dev/pci/drm/i915/gvt/handlers.c

2864

static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,

sys/dev/pci/drm/i915/gvt/handlers.c

2865

u32 size)

sys/dev/pci/drm/i915/gvt/handlers.c

2869

u32 start, end, i;

sys/dev/pci/drm/i915/gvt/handlers.c

2904

u32 offset, u32 size)

sys/dev/pci/drm/i915/gvt/handlers.c

2930

static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset,

sys/dev/pci/drm/i915/gvt/handlers.c

2931

u32 size)

sys/dev/pci/drm/i915/gvt/handlers.c

294

u32 old, new;

sys/dev/pci/drm/i915/gvt/handlers.c

295

u32 ack_reg_offset;

sys/dev/pci/drm/i915/gvt/handlers.c

298

new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);

sys/dev/pci/drm/i915/gvt/handlers.c

3042

int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),

sys/dev/pci/drm/i915/gvt/handlers.c

3116

u32 mask, old_vreg;

sys/dev/pci/drm/i915/gvt/handlers.c

3175

u32 old_vreg = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

3197

u32 mask = vgpu_vreg(vgpu, offset) >> 16;

sys/dev/pci/drm/i915/gvt/handlers.c

3227

static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data)

sys/dev/pci/drm/i915/gvt/handlers.c

329

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

474

static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)

sys/dev/pci/drm/i915/gvt/handlers.c

476

u32 dp_br = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

477

u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));

sys/dev/pci/drm/i915/gvt/handlers.c

511

u32 wrpll_ctl;

sys/dev/pci/drm/i915/gvt/handlers.c

549

static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)

sys/dev/pci/drm/i915/gvt/handlers.c

551

u32 dp_br = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

556

u32 temp;

sys/dev/pci/drm/i915/gvt/handlers.c

613

static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)

sys/dev/pci/drm/i915/gvt/handlers.c

615

u32 dp_br = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

666

u32 dp_br, link_m, link_n, htotal, vtotal;

sys/dev/pci/drm/i915/gvt/handlers.c

694

u32 new_rate = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

695

u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);

sys/dev/pci/drm/i915/gvt/handlers.c

715

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

767

static inline bool in_whitelist(u32 reg)

sys/dev/pci/drm/i915/gvt/handlers.c

788

u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);

sys/dev/pci/drm/i915/gvt/handlers.c

827

vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/handlers.c

836

u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/gvt/handlers.c

837

u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);

sys/dev/pci/drm/i915/gvt/handlers.c

838

u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));

sys/dev/pci/drm/i915/gvt/handlers.c

896

u32 start = i915_mmio_reg_offset(_start);

sys/dev/pci/drm/i915/gvt/handlers.c

897

u32 next = i915_mmio_reg_offset(_next);

sys/dev/pci/drm/i915/gvt/handlers.c

898

u32 end = i915_mmio_reg_offset(_end);

sys/dev/pci/drm/i915/gvt/handlers.c

899

u32 stride = next - start;

sys/dev/pci/drm/i915/gvt/handlers.c

965

u32 data;

sys/dev/pci/drm/i915/gvt/handlers.c

981

u32 reg_val;

sys/dev/pci/drm/i915/gvt/handlers.c

982

u32 sticky_mask;

sys/dev/pci/drm/i915/gvt/handlers.c

984

reg_val = *((u32 *)p_data);

sys/dev/pci/drm/i915/gvt/handlers.c

996

u32 data;

sys/dev/pci/drm/i915/gvt/interrupt.c

200

u32 imr = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/interrupt.c

230

u32 ier = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/interrupt.c

231

u32 virtual_ier = vgpu_vreg(vgpu, reg);

sys/dev/pci/drm/i915/gvt/interrupt.c

271

u32 ier = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/interrupt.c

309

u32 iir = *(u32 *)p_data;

sys/dev/pci/drm/i915/gvt/interrupt.c

348

u32 set_bits = 0;

sys/dev/pci/drm/i915/gvt/interrupt.c

349

u32 clear_bits = 0;

sys/dev/pci/drm/i915/gvt/interrupt.c

351

u32 val = vgpu_vreg(vgpu,

sys/dev/pci/drm/i915/gvt/interrupt.c

381

u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);

sys/dev/pci/drm/i915/gvt/interrupt.c

386

u32 iir = regbase_to_iir(

sys/dev/pci/drm/i915/gvt/interrupt.c

388

u32 imr = regbase_to_imr(

sys/dev/pci/drm/i915/gvt/interrupt.c

429

u32 addr;

sys/dev/pci/drm/i915/gvt/interrupt.c

432

addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));

sys/dev/pci/drm/i915/gvt/interrupt.c

53

u32 down_irq_bitmask;

sys/dev/pci/drm/i915/gvt/interrupt.c

534

u32 reg_base;

sys/dev/pci/drm/i915/gvt/kvmgt.c

1061

unsigned int count, u32 flags,

sys/dev/pci/drm/i915/gvt/kvmgt.c

1069

unsigned int count, u32 flags, void *data)

sys/dev/pci/drm/i915/gvt/kvmgt.c

1076

u32 flags, void *data)

sys/dev/pci/drm/i915/gvt/kvmgt.c

1083

u32 flags, void *data)

sys/dev/pci/drm/i915/gvt/kvmgt.c

1102

static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags,

sys/dev/pci/drm/i915/gvt/kvmgt.c

1107

unsigned int start, unsigned int count, u32 flags,

sys/dev/pci/drm/i915/gvt/kvmgt.c

543

size_t size, u32 flags, void *data)

sys/dev/pci/drm/i915/gvt/kvmgt.c

726

u32 start_lo, start_hi;

sys/dev/pci/drm/i915/gvt/kvmgt.c

727

u32 mem_type;

sys/dev/pci/drm/i915/gvt/kvmgt.c

729

start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &

sys/dev/pci/drm/i915/gvt/kvmgt.c

731

mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &

sys/dev/pci/drm/i915/gvt/kvmgt.c

736

start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space

sys/dev/pci/drm/i915/gvt/kvmgt.c

78

u32 type;

sys/dev/pci/drm/i915/gvt/kvmgt.c

79

u32 subtype;

sys/dev/pci/drm/i915/gvt/kvmgt.c

81

u32 flags;

sys/dev/pci/drm/i915/gvt/kvmgt.c

890

u32 val;

sys/dev/pci/drm/i915/gvt/kvmgt.c

965

u32 val;

sys/dev/pci/drm/i915/gvt/mmio.h

63

u32 offset;

sys/dev/pci/drm/i915/gvt/mmio.h

77

int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),

sys/dev/pci/drm/i915/gvt/mmio_context.c

164

u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];

sys/dev/pci/drm/i915/gvt/mmio_context.c

165

u32 l3cc_table[GEN9_MOCS_SIZE / 2];

sys/dev/pci/drm/i915/gvt/mmio_context.c

168

static u32 gen9_mocs_mmio_offset_list[] = {

sys/dev/pci/drm/i915/gvt/mmio_context.c

180

u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;

sys/dev/pci/drm/i915/gvt/mmio_context.c

181

u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;

sys/dev/pci/drm/i915/gvt/mmio_context.c

214

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

259

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

286

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

317

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

355

static u32 gen8_tlb_mmio_offset_list[] = {

sys/dev/pci/drm/i915/gvt/mmio_context.c

368

u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list;

sys/dev/pci/drm/i915/gvt/mmio_context.c

369

u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt;

sys/dev/pci/drm/i915/gvt/mmio_context.c

412

u32 regs[] = {

sys/dev/pci/drm/i915/gvt/mmio_context.c

421

u32 old_v, new_v;

sys/dev/pci/drm/i915/gvt/mmio_context.c

474

const u32 *reg_state = ce->lrc_reg_state;

sys/dev/pci/drm/i915/gvt/mmio_context.c

475

u32 inhibit_mask =

sys/dev/pci/drm/i915/gvt/mmio_context.c

490

u32 old_v, new_v;

sys/dev/pci/drm/i915/gvt/mmio_context.c

53

u32 mask;

sys/dev/pci/drm/i915/gvt/mmio_context.c

55

u32 value;

sys/dev/pci/drm/i915/gvt/opregion.c

268

int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa)

sys/dev/pci/drm/i915/gvt/opregion.c

303

u32 __ret; \

sys/dev/pci/drm/i915/gvt/opregion.c

311

u32 __ret; \

sys/dev/pci/drm/i915/gvt/opregion.c

317

static const char *opregion_func_name(u32 func)

sys/dev/pci/drm/i915/gvt/opregion.c

343

static const char *opregion_subfunc_name(u32 subfunc)

sys/dev/pci/drm/i915/gvt/opregion.c

388

static bool querying_capabilities(u32 scic)

sys/dev/pci/drm/i915/gvt/opregion.c

390

u32 func, subfunc;

sys/dev/pci/drm/i915/gvt/opregion.c

414

int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci)

sys/dev/pci/drm/i915/gvt/opregion.c

416

u32 scic, parm;

sys/dev/pci/drm/i915/gvt/opregion.c

417

u32 func, subfunc;

sys/dev/pci/drm/i915/gvt/opregion.c

47

u32 size;

sys/dev/pci/drm/i915/gvt/opregion.c

48

u32 opregion_ver;

sys/dev/pci/drm/i915/gvt/opregion.c

52

u32 mboxes;

sys/dev/pci/drm/i915/gvt/opregion.c

53

u32 driver_model;

sys/dev/pci/drm/i915/gvt/opregion.c

54

u32 pcon;

sys/dev/pci/drm/i915/gvt/scheduler.c

108

u32 state_offset = ctx_flexeu0 + i * 2;

sys/dev/pci/drm/i915/gvt/scheduler.c

118

u32 state_offset = ctx_flexeu0 + i * 2;

sys/dev/pci/drm/i915/gvt/scheduler.c

119

u32 mmio = flex_mmio[i];

sys/dev/pci/drm/i915/gvt/scheduler.c

151

sr_oa_regs(workload, (u32 *)shadow_ring_context, true);

sys/dev/pci/drm/i915/gvt/scheduler.c

1569

u64 ring_context_gpa, u32 pdp[8])

sys/dev/pci/drm/i915/gvt/scheduler.c

1637

u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;

sys/dev/pci/drm/i915/gvt/scheduler.c

1638

u32 guest_head;

sys/dev/pci/drm/i915/gvt/scheduler.c

1642

(u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));

sys/dev/pci/drm/i915/gvt/scheduler.c

188

sr_oa_regs(workload, (u32 *)shadow_ring_context, false);

sys/dev/pci/drm/i915/gvt/scheduler.c

227

(u32)((workload->ctx_desc.lrca + i) <<

sys/dev/pci/drm/i915/gvt/scheduler.c

366

u32 *cs;

sys/dev/pci/drm/i915/gvt/scheduler.c

391

cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));

sys/dev/pci/drm/i915/gvt/scheduler.c

406

cs += workload->rb_len / sizeof(u32);

sys/dev/pci/drm/i915/gvt/scheduler.c

55

u32 pdp[8])

sys/dev/pci/drm/i915/gvt/scheduler.c

85

u32 *reg_state, bool save)

sys/dev/pci/drm/i915/gvt/scheduler.c

88

u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;

sys/dev/pci/drm/i915/gvt/scheduler.c

89

u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;

sys/dev/pci/drm/i915/gvt/scheduler.c

908

u64 ring_context_gpa, u32 pdp[8])

sys/dev/pci/drm/i915/gvt/scheduler.c

91

u32 flex_mmio[] = {

sys/dev/pci/drm/i915/gvt/scheduler.c

949

u32 ring_base;

sys/dev/pci/drm/i915/gvt/scheduler.c

950

u32 head, tail;

sys/dev/pci/drm/i915/gvt/scheduler.c

990

(u32)((workload->ctx_desc.lrca + i) <<

sys/dev/pci/drm/i915/gvt/scheduler.h

120

u32 oactxctrl;

sys/dev/pci/drm/i915/gvt/scheduler.h

121

u32 flex_mmio[7];

sys/dev/pci/drm/i915/gvt/scheduler.h

129

u32 *bb_start_cmd_va;

sys/dev/pci/drm/i915/gvt/scheduler.h

69

u32 size;

sys/dev/pci/drm/i915/gvt/trace.h

229

TP_PROTO(u8 vgpu_id, u8 ring_id, u32 ip_gma, u32 *cmd_va,

sys/dev/pci/drm/i915/gvt/trace.h

230

u32 cmd_len, u32 buf_type, u32 buf_addr_type,

sys/dev/pci/drm/i915/gvt/trace.h

239

__field(u32, ip_gma)

sys/dev/pci/drm/i915/gvt/trace.h

240

__field(u32, buf_type)

sys/dev/pci/drm/i915/gvt/trace.h

241

__field(u32, buf_addr_type)

sys/dev/pci/drm/i915/gvt/trace.h

242

__field(u32, cmd_len)

sys/dev/pci/drm/i915/gvt/trace.h

244

__dynamic_array(u32, raw_cmd, cmd_len)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1078

u32 cmd_header)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1102

u32 cmd_header,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1106

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1127

__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1144

find_reg(const struct intel_engine_cs *engine, u32 addr)

sys/dev/pci/drm/i915/i915_cmd_parser.c

115

u32 flags;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1157

static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1233

memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));

sys/dev/pci/drm/i915/i915_cmd_parser.c

1242

const u32 cmd)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1249

const u32 *cmd, u32 length)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1265

const u32 step = desc->reg.step ? desc->reg.step : length;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1266

u32 offset;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1270

const u32 reg_addr = cmd[offset] & desc->reg.mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

128

u32 value;

sys/dev/pci/drm/i915/i915_cmd_parser.c

129

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1312

u32 dword;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1318

u32 offset =

sys/dev/pci/drm/i915/i915_cmd_parser.c

1320

u32 condition = cmd[offset] &

sys/dev/pci/drm/i915/i915_cmd_parser.c

1350

static int check_bbstart(u32 *cmd, u32 offset, u32 length,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1351

u32 batch_length,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1357

u32 target_cmd_offset, target_cmd_index;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1389

target_cmd_index = target_cmd_offset / sizeof(u32);

sys/dev/pci/drm/i915/i915_cmd_parser.c

140

u32 fixed;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1408

static unsigned long *alloc_whitelist(u32 batch_length)

sys/dev/pci/drm/i915/i915_cmd_parser.c

141

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1419

jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)),

sys/dev/pci/drm/i915/i915_cmd_parser.c

1452

u32 *cmd, *batch_end, offset = 0;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1489

u32 length;

sys/dev/pci/drm/i915/i915_cmd_parser.c

154

u32 offset;

sys/dev/pci/drm/i915/i915_cmd_parser.c

155

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

156

u32 step;

sys/dev/pci/drm/i915/i915_cmd_parser.c

172

u32 offset;

sys/dev/pci/drm/i915/i915_cmd_parser.c

173

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

174

u32 expected;

sys/dev/pci/drm/i915/i915_cmd_parser.c

175

u32 condition_offset;

sys/dev/pci/drm/i915/i915_cmd_parser.c

176

u32 condition_mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

576

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

577

u32 value;

sys/dev/pci/drm/i915/i915_cmd_parser.c

736

static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)

sys/dev/pci/drm/i915/i915_cmd_parser.c

738

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/pci/drm/i915/i915_cmd_parser.c

739

u32 subclient =

sys/dev/pci/drm/i915/i915_cmd_parser.c

755

static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)

sys/dev/pci/drm/i915/i915_cmd_parser.c

757

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/pci/drm/i915/i915_cmd_parser.c

758

u32 subclient =

sys/dev/pci/drm/i915/i915_cmd_parser.c

760

u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;

sys/dev/pci/drm/i915/i915_cmd_parser.c

778

static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)

sys/dev/pci/drm/i915/i915_cmd_parser.c

780

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/pci/drm/i915/i915_cmd_parser.c

791

static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header)

sys/dev/pci/drm/i915/i915_cmd_parser.c

793

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/pci/drm/i915/i915_cmd_parser.c

814

u32 previous = 0;

sys/dev/pci/drm/i915/i915_cmd_parser.c

820

u32 curr = desc->cmd.value & desc->cmd.mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

843

u32 previous = 0;

sys/dev/pci/drm/i915/i915_cmd_parser.c

847

u32 curr = i915_mmio_reg_offset(reg_table[i].addr);

sys/dev/pci/drm/i915/i915_cmd_parser.c

893

static inline u32 cmd_header_key(u32 x)

sys/dev/pci/drm/i915/i915_drv.h

117

u32 *remap_info[MAX_L3_SLICES];

sys/dev/pci/drm/i915/i915_drv.h

172

u32 shrink_count;

sys/dev/pci/drm/i915/i915_drv.h

178

u32 caps;

sys/dev/pci/drm/i915/i915_drv.h

179

u32 *initial_mmio;

sys/dev/pci/drm/i915/i915_drv.h

305

u32 irq_mask;

sys/dev/pci/drm/i915/i915_drv.h

344

u32 edram_size_mb;

sys/dev/pci/drm/i915/i915_drv.h

348

u32 suspend_count;

sys/dev/pci/drm/i915/i915_drv.h

479

static inline u32

sys/dev/pci/drm/i915/i915_drv.h

509

const u32 mask = info->platform_mask[pi];

sys/dev/pci/drm/i915/i915_gem.c

414

u32 page_base = node.start;

sys/dev/pci/drm/i915/i915_gem.c

593

u32 page_base = node.start;

sys/dev/pci/drm/i915/i915_gem.c

61

insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)

sys/dev/pci/drm/i915/i915_gpu_error.c

1454

u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/i915_gpu_error.c

1656

intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

1754

u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

1806

u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

1853

static u32 read_guc_state_reg(struct intel_uncore *uncore, int range, int count)

sys/dev/pci/drm/i915/i915_gpu_error.c

1859

_MMIO(guc_hw_reg_state[range].start + count * sizeof(u32)));

sys/dev/pci/drm/i915/i915_gpu_error.c

1865

u32 *hw_state;

sys/dev/pci/drm/i915/i915_gpu_error.c

1866

u32 count = 0;

sys/dev/pci/drm/i915/i915_gpu_error.c

1872

hw_state = kcalloc(count, sizeof(u32), ALLOW_FAIL);

sys/dev/pci/drm/i915/i915_gpu_error.c

2076

static u32 generate_ecode(const struct intel_engine_coredump *ee)

sys/dev/pci/drm/i915/i915_gpu_error.c

2170

intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

2228

__i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

2281

i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

2327

intel_engine_mask_t engine_mask, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

575

(u32)(ee->acthd>>32), (u32)ee->acthd);

sys/dev/pci/drm/i915/i915_gpu_error.c

593

(u32)(ee->bbaddr>>32), (u32)ee->bbaddr);

sys/dev/pci/drm/i915/i915_gpu_error.c

665

const u32 *addr = page_address(page);

sys/dev/pci/drm/i915/i915_gpu_error.c

722

u32 start;

sys/dev/pci/drm/i915/i915_gpu_error.c

723

u32 count;

sys/dev/pci/drm/i915/i915_gpu_error.c

742

static u32 print_range_line(struct drm_i915_error_state_buf *m, u32 start, u32 *dump, u32 count)

sys/dev/pci/drm/i915/i915_gpu_error.c

762

static void err_print_guc_hw_state(struct drm_i915_error_state_buf *m, u32 *hw_state)

sys/dev/pci/drm/i915/i915_gpu_error.c

764

u32 total = 0;

sys/dev/pci/drm/i915/i915_gpu_error.c

773

u32 entry = 0;

sys/dev/pci/drm/i915/i915_gpu_error.c

776

u32 start = guc_hw_reg_state[i].start + entry * sizeof(u32);

sys/dev/pci/drm/i915/i915_gpu_error.c

777

u32 count = guc_hw_reg_state[i].count - entry;

sys/dev/pci/drm/i915/i915_gpu_error.c

778

u32 *values = hw_state + total + entry;

sys/dev/pci/drm/i915/i915_gpu_error.h

111

u32 hwsp_seqno;

sys/dev/pci/drm/i915/i915_gpu_error.h

120

u32 gfx_mode;

sys/dev/pci/drm/i915/i915_gpu_error.h

123

u32 pp_dir_base;

sys/dev/pci/drm/i915/i915_gpu_error.h

131

u32 raw_head, head;

sys/dev/pci/drm/i915/i915_gpu_error.h

132

u32 raw_tail, tail;

sys/dev/pci/drm/i915/i915_gpu_error.h

133

u32 raw_status;

sys/dev/pci/drm/i915/i915_gpu_error.h

134

u32 desc_offset;

sys/dev/pci/drm/i915/i915_gpu_error.h

135

u32 cmds_offset;

sys/dev/pci/drm/i915/i915_gpu_error.h

136

u32 size;

sys/dev/pci/drm/i915/i915_gpu_error.h

147

u32 eir;

sys/dev/pci/drm/i915/i915_gpu_error.h

148

u32 pgtbl_er;

sys/dev/pci/drm/i915/i915_gpu_error.h

149

u32 gtier[6], ngtier;

sys/dev/pci/drm/i915/i915_gpu_error.h

150

u32 forcewake;

sys/dev/pci/drm/i915/i915_gpu_error.h

151

u32 error; /* gen6+ */

sys/dev/pci/drm/i915/i915_gpu_error.h

152

u32 err_int; /* gen7 */

sys/dev/pci/drm/i915/i915_gpu_error.h

153

u32 fault_data0; /* gen8, gen9 */

sys/dev/pci/drm/i915/i915_gpu_error.h

154

u32 fault_data1; /* gen8, gen9 */

sys/dev/pci/drm/i915/i915_gpu_error.h

155

u32 done_reg;

sys/dev/pci/drm/i915/i915_gpu_error.h

156

u32 gac_eco;

sys/dev/pci/drm/i915/i915_gpu_error.h

157

u32 gam_ecochk;

sys/dev/pci/drm/i915/i915_gpu_error.h

158

u32 gab_ctl;

sys/dev/pci/drm/i915/i915_gpu_error.h

159

u32 gfx_mode;

sys/dev/pci/drm/i915/i915_gpu_error.h

160

u32 gtt_cache;

sys/dev/pci/drm/i915/i915_gpu_error.h

161

u32 aux_err; /* gen12 */

sys/dev/pci/drm/i915/i915_gpu_error.h

162

u32 gam_done; /* gen12 */

sys/dev/pci/drm/i915/i915_gpu_error.h

163

u32 clock_frequency;

sys/dev/pci/drm/i915/i915_gpu_error.h

164

u32 clock_period_ns;

sys/dev/pci/drm/i915/i915_gpu_error.h

166

u32 sfc_done[I915_MAX_SFC]; /* gen12 */

sys/dev/pci/drm/i915/i915_gpu_error.h

168

u32 nfence;

sys/dev/pci/drm/i915/i915_gpu_error.h

180

u32 *hw_state;

sys/dev/pci/drm/i915/i915_gpu_error.h

181

u32 timestamp;

sys/dev/pci/drm/i915/i915_gpu_error.h

206

u32 reset_count;

sys/dev/pci/drm/i915/i915_gpu_error.h

207

u32 suspend_count;

sys/dev/pci/drm/i915/i915_gpu_error.h

244

static inline u32 i915_reset_count(struct i915_gpu_error *error)

sys/dev/pci/drm/i915/i915_gpu_error.h

249

static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,

sys/dev/pci/drm/i915/i915_gpu_error.h

281

intel_engine_mask_t engine_mask, u32 dump_flags);

sys/dev/pci/drm/i915/i915_gpu_error.h

287

intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags);

sys/dev/pci/drm/i915/i915_gpu_error.h

290

intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);

sys/dev/pci/drm/i915/i915_gpu_error.h

343

i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.h

354

intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.h

360

intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.h

41

u32 gtt_page_sizes;

sys/dev/pci/drm/i915/i915_gpu_error.h

50

u32 context;

sys/dev/pci/drm/i915/i915_gpu_error.h

51

u32 seqno;

sys/dev/pci/drm/i915/i915_gpu_error.h

52

u32 head;

sys/dev/pci/drm/i915/i915_gpu_error.h

53

u32 tail;

sys/dev/pci/drm/i915/i915_gpu_error.h

64

u32 reset_count;

sys/dev/pci/drm/i915/i915_gpu_error.h

67

u32 rq_head, rq_post, rq_tail;

sys/dev/pci/drm/i915/i915_gpu_error.h

70

u32 ccid;

sys/dev/pci/drm/i915/i915_gpu_error.h

71

u32 start;

sys/dev/pci/drm/i915/i915_gpu_error.h

72

u32 tail;

sys/dev/pci/drm/i915/i915_gpu_error.h

73

u32 head;

sys/dev/pci/drm/i915/i915_gpu_error.h

74

u32 ctl;

sys/dev/pci/drm/i915/i915_gpu_error.h

75

u32 mode;

sys/dev/pci/drm/i915/i915_gpu_error.h

76

u32 hws;

sys/dev/pci/drm/i915/i915_gpu_error.h

77

u32 ipeir;

sys/dev/pci/drm/i915/i915_gpu_error.h

78

u32 ipehr;

sys/dev/pci/drm/i915/i915_gpu_error.h

79

u32 esr;

sys/dev/pci/drm/i915/i915_gpu_error.h

80

u32 bbstate;

sys/dev/pci/drm/i915/i915_gpu_error.h

81

u32 instpm;

sys/dev/pci/drm/i915/i915_gpu_error.h

82

u32 instps;

sys/dev/pci/drm/i915/i915_gpu_error.h

85

u32 fault_reg;

sys/dev/pci/drm/i915/i915_gpu_error.h

87

u32 rc_psmi; /* sleep state */

sys/dev/pci/drm/i915/i915_gpu_error.h

88

u32 nopid;

sys/dev/pci/drm/i915/i915_gpu_error.h

89

u32 excc;

sys/dev/pci/drm/i915/i915_gpu_error.h

90

u32 cmd_cctl;

sys/dev/pci/drm/i915/i915_gpu_error.h

91

u32 cscmdop;

sys/dev/pci/drm/i915/i915_gpu_error.h

92

u32 ctx_sr_ctl;

sys/dev/pci/drm/i915/i915_gpu_error.h

93

u32 dma_faddr_hi;

sys/dev/pci/drm/i915/i915_gpu_error.h

94

u32 dma_faddr_lo;

sys/dev/pci/drm/i915/i915_gtt_view_types.h

11

u32 offset:31;

sys/dev/pci/drm/i915/i915_gtt_view_types.h

12

u32 linear:1;

sys/dev/pci/drm/i915/i915_gtt_view_types.h

23

u32 size;

sys/dev/pci/drm/i915/i915_gtt_view_types.h

39

u32 plane_alignment;

sys/dev/pci/drm/i915/i915_hwmon.c

101

u32 field_msk, int nshift, u32 scale_factor)

sys/dev/pci/drm/i915/i915_hwmon.c

105

u32 reg_value;

sys/dev/pci/drm/i915/i915_hwmon.c

143

u32 reg_val;

sys/dev/pci/drm/i915/i915_hwmon.c

174

u32 r, x, y, x_w = 2; /* 2 bits */

sys/dev/pci/drm/i915/i915_hwmon.c

204

u32 x, y, rxy, x_w = 2; /* 2 bits */

sys/dev/pci/drm/i915/i915_hwmon.c

300

static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)

sys/dev/pci/drm/i915/i915_hwmon.c

310

static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)

sys/dev/pci/drm/i915/i915_hwmon.c

317

hwm_temp_is_visible(const struct hwm_drvdata *ddat, u32 attr)

sys/dev/pci/drm/i915/i915_hwmon.c

328

hwm_temp_read(struct hwm_drvdata *ddat, u32 attr, long *val)

sys/dev/pci/drm/i915/i915_hwmon.c

332

u32 reg_val;

sys/dev/pci/drm/i915/i915_hwmon.c

348

hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)

sys/dev/pci/drm/i915/i915_hwmon.c

361

hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)

sys/dev/pci/drm/i915/i915_hwmon.c

365

u32 reg_value;

sys/dev/pci/drm/i915/i915_hwmon.c

380

hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)

sys/dev/pci/drm/i915/i915_hwmon.c

384

u32 uval;

sys/dev/pci/drm/i915/i915_hwmon.c

448

u32 nval;

sys/dev/pci/drm/i915/i915_hwmon.c

46

u32 reg_val_prev;

sys/dev/pci/drm/i915/i915_hwmon.c

498

hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)

sys/dev/pci/drm/i915/i915_hwmon.c

502

u32 uval;

sys/dev/pci/drm/i915/i915_hwmon.c

51

u32 reg_val_prev;

sys/dev/pci/drm/i915/i915_hwmon.c

529

hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)

sys/dev/pci/drm/i915/i915_hwmon.c

531

u32 uval;

sys/dev/pci/drm/i915/i915_hwmon.c

547

u32 r;

sys/dev/pci/drm/i915/i915_hwmon.c

580

hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)

sys/dev/pci/drm/i915/i915_hwmon.c

598

hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)

sys/dev/pci/drm/i915/i915_hwmon.c

610

hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr)

sys/dev/pci/drm/i915/i915_hwmon.c

613

u32 uval;

sys/dev/pci/drm/i915/i915_hwmon.c

625

hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)

sys/dev/pci/drm/i915/i915_hwmon.c

628

u32 uval;

sys/dev/pci/drm/i915/i915_hwmon.c

646

hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)

sys/dev/pci/drm/i915/i915_hwmon.c

648

u32 uval;

sys/dev/pci/drm/i915/i915_hwmon.c

660

hwm_fan_is_visible(const struct hwm_drvdata *ddat, u32 attr)

sys/dev/pci/drm/i915/i915_hwmon.c

677

u32 reg_val;

sys/dev/pci/drm/i915/i915_hwmon.c

714

hwm_fan_read(struct hwm_drvdata *ddat, u32 attr, long *val)

sys/dev/pci/drm/i915/i915_hwmon.c

724

u32 attr, int channel)

sys/dev/pci/drm/i915/i915_hwmon.c

747

hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,

sys/dev/pci/drm/i915/i915_hwmon.c

771

hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,

sys/dev/pci/drm/i915/i915_hwmon.c

79

i915_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/i915_hwmon.c

799

u32 attr, int channel)

sys/dev/pci/drm/i915/i915_hwmon.c

812

hwm_gt_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,

sys/dev/pci/drm/i915/i915_hwmon.c

842

u32 val_sku_unit = 0;

sys/dev/pci/drm/i915/i915_ioc32.c

44

u32 value;

sys/dev/pci/drm/i915/i915_ioctl.c

55

u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);

sys/dev/pci/drm/i915/i915_irq.c

100

u32 val = intel_uncore_read(uncore, reg);

sys/dev/pci/drm/i915/i915_irq.c

1005

static u32 i965_error_mask(struct drm_i915_private *i915)

sys/dev/pci/drm/i915/i915_irq.c

1028

u32 enable_mask;

sys/dev/pci/drm/i915/i915_irq.c

1068

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/pci/drm/i915/i915_irq.c

1069

u32 eir = 0, eir_stuck = 0;

sys/dev/pci/drm/i915/i915_irq.c

1070

u32 hotplug_status = 0;

sys/dev/pci/drm/i915/i915_irq.c

1071

u32 iir;

sys/dev/pci/drm/i915/i915_irq.c

115

u32 imr_val, u32 ier_val)

sys/dev/pci/drm/i915/i915_irq.c

136

u32 emr_val)

sys/dev/pci/drm/i915/i915_irq.c

161

u32 error_status, row, bank, subbank;

sys/dev/pci/drm/i915/i915_irq.c

163

u32 misccpctl;

sys/dev/pci/drm/i915/i915_irq.c

238

u32 iir, gt_iir, pm_iir;

sys/dev/pci/drm/i915/i915_irq.c

239

u32 eir = 0, dpinvgtt = 0;

sys/dev/pci/drm/i915/i915_irq.c

240

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/pci/drm/i915/i915_irq.c

241

u32 hotplug_status = 0;

sys/dev/pci/drm/i915/i915_irq.c

242

u32 ier = 0;

sys/dev/pci/drm/i915/i915_irq.c

332

u32 master_ctl, iir;

sys/dev/pci/drm/i915/i915_irq.c

333

u32 eir = 0, dpinvgtt = 0;

sys/dev/pci/drm/i915/i915_irq.c

334

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/pci/drm/i915/i915_irq.c

335

u32 hotplug_status = 0;

sys/dev/pci/drm/i915/i915_irq.c

336

u32 ier = 0;

sys/dev/pci/drm/i915/i915_irq.c

418

u32 de_iir, gt_iir, de_ier, sde_ier = 0;

sys/dev/pci/drm/i915/i915_irq.c

464

u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);

sys/dev/pci/drm/i915/i915_irq.c

484

static inline u32 gen8_master_intr_disable(void __iomem * const regs)

sys/dev/pci/drm/i915/i915_irq.c

507

u32 master_ctl;

sys/dev/pci/drm/i915/i915_irq.c

535

static inline u32 gen11_master_intr_disable(void __iomem * const regs)

sys/dev/pci/drm/i915/i915_irq.c

559

u32 master_ctl;

sys/dev/pci/drm/i915/i915_irq.c

560

u32 gu_misc_iir;

sys/dev/pci/drm/i915/i915_irq.c

589

static inline u32 dg1_master_intr_disable(void __iomem * const regs)

sys/dev/pci/drm/i915/i915_irq.c

591

u32 val;

sys/dev/pci/drm/i915/i915_irq.c

617

u32 master_tile_ctl, master_ctl;

sys/dev/pci/drm/i915/i915_irq.c

618

u32 gu_misc_iir;

sys/dev/pci/drm/i915/i915_irq.c

787

u32 gu_misc_masked = GEN11_GU_MISC_GSE;

sys/dev/pci/drm/i915/i915_irq.c

802

u32 gu_misc_masked = GEN11_GU_MISC_GSE;

sys/dev/pci/drm/i915/i915_irq.c

829

static u32 i9xx_error_mask(struct drm_i915_private *i915)

sys/dev/pci/drm/i915/i915_irq.c

852

u32 *eir, u32 *eir_stuck)

sys/dev/pci/drm/i915/i915_irq.c

854

u32 emr;

sys/dev/pci/drm/i915/i915_irq.c

879

u32 eir, u32 eir_stuck)

sys/dev/pci/drm/i915/i915_irq.c

907

u32 enable_mask;

sys/dev/pci/drm/i915/i915_irq.c

950

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/pci/drm/i915/i915_irq.c

951

u32 eir = 0, eir_stuck = 0;

sys/dev/pci/drm/i915/i915_irq.c

952

u32 hotplug_status = 0;

sys/dev/pci/drm/i915/i915_irq.c

953

u32 iir;

sys/dev/pci/drm/i915/i915_irq.h

28

void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);

sys/dev/pci/drm/i915/i915_irq.h

29

void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);

sys/dev/pci/drm/i915/i915_irq.h

35

u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);

sys/dev/pci/drm/i915/i915_irq.h

48

u32 imr_val, u32 ier_val);

sys/dev/pci/drm/i915/i915_irq.h

52

u32 emr_val);

sys/dev/pci/drm/i915/i915_perf.c

1055

u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);

sys/dev/pci/drm/i915/i915_perf.c

1056

u32 mask = (OA_BUFFER_SIZE - 1);

sys/dev/pci/drm/i915/i915_perf.c

1059

u32 head, tail;

sys/dev/pci/drm/i915/i915_perf.c

1090

u32 *report32 = (void *)report;

sys/dev/pci/drm/i915/i915_perf.c

1167

u32 oastatus1;

sys/dev/pci/drm/i915/i915_perf.c

1335

__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)

sys/dev/pci/drm/i915/i915_perf.c

1337

u32 *cs, cmd;

sys/dev/pci/drm/i915/i915_perf.c

1358

__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)

sys/dev/pci/drm/i915/i915_perf.c

1381

gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)

sys/dev/pci/drm/i915/i915_perf.c

1384

u32 *val;

sys/dev/pci/drm/i915/i915_perf.c

1427

u32 ctx_id, mask;

sys/dev/pci/drm/i915/i915_perf.c

1456

static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)

sys/dev/pci/drm/i915/i915_perf.c

1458

u32 idx = *offset;

sys/dev/pci/drm/i915/i915_perf.c

1459

u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);

sys/dev/pci/drm/i915/i915_perf.c

1474

static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)

sys/dev/pci/drm/i915/i915_perf.c

1476

u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;

sys/dev/pci/drm/i915/i915_perf.c

1477

u32 *state = ce->lrc_reg_state;

sys/dev/pci/drm/i915/i915_perf.c

1505

u32 offset = perf->ctx_oactxctrl_offset;

sys/dev/pci/drm/i915/i915_perf.c

1720

u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);

sys/dev/pci/drm/i915/i915_perf.c

1765

u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);

sys/dev/pci/drm/i915/i915_perf.c

1818

u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);

sys/dev/pci/drm/i915/i915_perf.c

1933

static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,

sys/dev/pci/drm/i915/i915_perf.c

1934

bool save, i915_reg_t reg, u32 offset,

sys/dev/pci/drm/i915/i915_perf.c

1935

u32 dword_count)

sys/dev/pci/drm/i915/i915_perf.c

1937

u32 cmd;

sys/dev/pci/drm/i915/i915_perf.c

1938

u32 d;

sys/dev/pci/drm/i915/i915_perf.c

1964

const u32 base = stream->engine->mmio_base;

sys/dev/pci/drm/i915/i915_perf.c

1966

u32 *batch, *ts0, *cs, *jump;

sys/dev/pci/drm/i915/i915_perf.c

2180

static u32 *write_cs_mi_lri(u32 *cs,

sys/dev/pci/drm/i915/i915_perf.c

2182

u32 n_regs)

sys/dev/pci/drm/i915/i915_perf.c

2184

u32 i;

sys/dev/pci/drm/i915/i915_perf.c

2188

u32 n_lri = min_t(u32,

sys/dev/pci/drm/i915/i915_perf.c

2221

u32 *cs;

sys/dev/pci/drm/i915/i915_perf.c

2232

config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);

sys/dev/pci/drm/i915/i915_perf.c

2440

static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,

sys/dev/pci/drm/i915/i915_perf.c

2443

u32 mmio = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/i915_perf.c

2472

u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;

sys/dev/pci/drm/i915/i915_perf.c

2473

u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;

sys/dev/pci/drm/i915/i915_perf.c

2484

u32 *reg_state = ce->lrc_reg_state;

sys/dev/pci/drm/i915/i915_perf.c

2499

u32 offset;

sys/dev/pci/drm/i915/i915_perf.c

2500

u32 value;

sys/dev/pci/drm/i915/i915_perf.c

2508

u32 offset;

sys/dev/pci/drm/i915/i915_perf.c

2509

u32 *cs;

sys/dev/pci/drm/i915/i915_perf.c

2518

*cs++ = offset + flex->offset * sizeof(u32);

sys/dev/pci/drm/i915/i915_perf.c

2533

u32 *cs;

sys/dev/pci/drm/i915/i915_perf.c

2636

u32 format = stream->oa_buffer.format->format;

sys/dev/pci/drm/i915/i915_perf.c

2637

u32 offset = stream->perf->ctx_oactxctrl_offset;

sys/dev/pci/drm/i915/i915_perf.c

273

static u32 i915_perf_stream_paranoid = true;

sys/dev/pci/drm/i915/i915_perf.c

2781

u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;

sys/dev/pci/drm/i915/i915_perf.c

2783

const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;

sys/dev/pci/drm/i915/i915_perf.c

2869

static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)

sys/dev/pci/drm/i915/i915_perf.c

2883

u32 period_exponent = stream->period_exponent;

sys/dev/pci/drm/i915/i915_perf.c

2884

u32 sqcnt1;

sys/dev/pci/drm/i915/i915_perf.c

2966

u32 sqcnt1;

sys/dev/pci/drm/i915/i915_perf.c

2996

u32 ctx_id = stream->specific_ctx_id;

sys/dev/pci/drm/i915/i915_perf.c

2998

u32 period_exponent = stream->period_exponent;

sys/dev/pci/drm/i915/i915_perf.c

2999

u32 report_format = stream->oa_buffer.format->format;

sys/dev/pci/drm/i915/i915_perf.c

3025

u32 report_format = stream->oa_buffer.format->format;

sys/dev/pci/drm/i915/i915_perf.c

3051

u32 val;

sys/dev/pci/drm/i915/i915_perf.c

312

static u32 i915_oa_max_sample_rate = 100000;

sys/dev/pci/drm/i915/i915_perf.c

3222

u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)

sys/dev/pci/drm/i915/i915_perf.c

3229

u32 reg, shift;

sys/dev/pci/drm/i915/i915_perf.c

336

static const u32 mtl_oa_base[] = {

sys/dev/pci/drm/i915/i915_perf.c

366

u32 sample_flags;

sys/dev/pci/drm/i915/i915_perf.c

3845

u32 ctx_handle = props->ctx_handle;

sys/dev/pci/drm/i915/i915_perf.c

3974

u32 den = i915_perf_oa_timestamp_frequency(perf->i915);

sys/dev/pci/drm/i915/i915_perf.c

4008

u32 n_props,

sys/dev/pci/drm/i915/i915_perf.c

4018

u32 i;

sys/dev/pci/drm/i915/i915_perf.c

4264

u32 known_open_flags;

sys/dev/pci/drm/i915/i915_perf.c

4346

static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4366

static bool reg_in_range_table(u32 addr, const struct i915_range *table)

sys/dev/pci/drm/i915/i915_perf.c

442

static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)

sys/dev/pci/drm/i915/i915_perf.c

4465

static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4470

static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4476

static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4483

static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4489

static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4495

static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

450

static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)

sys/dev/pci/drm/i915/i915_perf.c

4500

static bool mtl_is_valid_oam_b_counter_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4509

static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4516

static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

sys/dev/pci/drm/i915/i915_perf.c

4526

static u32 mask_reg_value(u32 reg, u32 val)

sys/dev/pci/drm/i915/i915_perf.c

4548

bool (*is_valid)(struct i915_perf *perf, u32 addr),

sys/dev/pci/drm/i915/i915_perf.c

4549

u32 __user *regs,

sys/dev/pci/drm/i915/i915_perf.c

4550

u32 n_regs)

sys/dev/pci/drm/i915/i915_perf.c

4554

u32 i;

sys/dev/pci/drm/i915/i915_perf.c

4569

u32 addr, value;

sys/dev/pci/drm/i915/i915_perf.c

457

static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)

sys/dev/pci/drm/i915/i915_perf.c

460

u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);

sys/dev/pci/drm/i915/i915_perf.c

470

return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report;

sys/dev/pci/drm/i915/i915_perf.c

481

static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report)

sys/dev/pci/drm/i915/i915_perf.c

4883

static u32 num_perf_groups_per_gt(struct intel_gt *gt)

sys/dev/pci/drm/i915/i915_perf.c

4888

static u32 __oam_engine_group(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

4904

static u32 __oa_engine_group(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

4919

static struct i915_perf_regs __oam_regs(u32 base)

sys/dev/pci/drm/i915/i915_perf.c

4972

u32 num_groups = num_perf_groups_per_gt(gt);

sys/dev/pci/drm/i915/i915_perf.c

4982

u32 index = __oa_engine_group(engine);

sys/dev/pci/drm/i915/i915_perf.c

499

*((u32 *)report + 1);

sys/dev/pci/drm/i915/i915_perf.c

502

static void oa_timestamp_clear(struct i915_perf_stream *stream, u32 *report)

sys/dev/pci/drm/i915/i915_perf.c

510

static u32 oa_context_id(struct i915_perf_stream *stream, u32 *report)

sys/dev/pci/drm/i915/i915_perf.c

512

u32 ctx_id = oa_report_header_64bit(stream) ? report[4] : report[2];

sys/dev/pci/drm/i915/i915_perf.c

517

static void oa_context_id_squash(struct i915_perf_stream *stream, u32 *report)

sys/dev/pci/drm/i915/i915_perf.c

552

u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);

sys/dev/pci/drm/i915/i915_perf.c

554

u32 tail, hw_tail;

sys/dev/pci/drm/i915/i915_perf.c

557

u32 partial_report_size;

sys/dev/pci/drm/i915/i915_perf.c

745

u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);

sys/dev/pci/drm/i915/i915_perf.c

746

u32 mask = (OA_BUFFER_SIZE - 1);

sys/dev/pci/drm/i915/i915_perf.c

749

u32 head, tail;

sys/dev/pci/drm/i915/i915_perf.c

780

u32 *report32 = (void *)report;

sys/dev/pci/drm/i915/i915_perf.c

781

u32 ctx_id;

sys/dev/pci/drm/i915/i915_perf.c

901

u32 part = oa_buf_end - (u8 *)report32;

sys/dev/pci/drm/i915/i915_perf.c

962

u32 oastatus;

sys/dev/pci/drm/i915/i915_perf.h

60

u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915);

sys/dev/pci/drm/i915/i915_perf_types.h

195

u32 sample_flags;

sys/dev/pci/drm/i915/i915_perf_types.h

250

u32 specific_ctx_id;

sys/dev/pci/drm/i915/i915_perf_types.h

255

u32 specific_ctx_id_mask;

sys/dev/pci/drm/i915/i915_perf_types.h

292

u32 last_ctx_id;

sys/dev/pci/drm/i915/i915_perf_types.h

325

u32 head;

sys/dev/pci/drm/i915/i915_perf_types.h

331

u32 tail;

sys/dev/pci/drm/i915/i915_perf_types.h

355

bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr);

sys/dev/pci/drm/i915/i915_perf_types.h

361

bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr);

sys/dev/pci/drm/i915/i915_perf_types.h

367

bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr);

sys/dev/pci/drm/i915/i915_perf_types.h

410

u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);

sys/dev/pci/drm/i915/i915_perf_types.h

424

u32 num_engines;

sys/dev/pci/drm/i915/i915_perf_types.h

452

u32 num_perf_groups;

sys/dev/pci/drm/i915/i915_perf_types.h

489

u32 gen7_latched_oastatus1;

sys/dev/pci/drm/i915/i915_perf_types.h

49

u32 base;

sys/dev/pci/drm/i915/i915_perf_types.h

490

u32 ctx_oactxctrl_offset;

sys/dev/pci/drm/i915/i915_perf_types.h

491

u32 ctx_flexeu0_offset;

sys/dev/pci/drm/i915/i915_perf_types.h

498

u32 gen8_valid_ctx_bit;

sys/dev/pci/drm/i915/i915_perf_types.h

57

u32 oa_ctrl_counter_format_shift;

sys/dev/pci/drm/i915/i915_perf_types.h

66

u32 format;

sys/dev/pci/drm/i915/i915_perf_types.h

74

u32 value;

sys/dev/pci/drm/i915/i915_perf_types.h

84

u32 mux_regs_len;

sys/dev/pci/drm/i915/i915_perf_types.h

86

u32 b_counter_regs_len;

sys/dev/pci/drm/i915/i915_perf_types.h

88

u32 flex_regs_len;

sys/dev/pci/drm/i915/i915_pmu.c

111

static __always_inline u32 config_mask(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

137

static u32 frequency_enabled_mask(void)

sys/dev/pci/drm/i915/i915_pmu.c

140

u32 mask = 0;

sys/dev/pci/drm/i915/i915_pmu.c

152

u32 enable;

sys/dev/pci/drm/i915/i915_pmu.c

213

add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul)

sys/dev/pci/drm/i915/i915_pmu.c

341

add_sample(struct i915_pmu_sample *sample, u32 val)

sys/dev/pci/drm/i915/i915_pmu.c

360

u32 val;

sys/dev/pci/drm/i915/i915_pmu.c

394

u32 tail, head, acthd;

sys/dev/pci/drm/i915/i915_pmu.c

475

u32 val;

sys/dev/pci/drm/i915/i915_pmu.h

94

u32 enable;

sys/dev/pci/drm/i915/i915_pvinfo.h

101

u32 cursor_x_hot;

sys/dev/pci/drm/i915/i915_pvinfo.h

102

u32 cursor_y_hot;

sys/dev/pci/drm/i915/i915_pvinfo.h

105

u32 lo;

sys/dev/pci/drm/i915/i915_pvinfo.h

106

u32 hi;

sys/dev/pci/drm/i915/i915_pvinfo.h

109

u32 execlist_context_descriptor_lo;

sys/dev/pci/drm/i915/i915_pvinfo.h

110

u32 execlist_context_descriptor_hi;

sys/dev/pci/drm/i915/i915_pvinfo.h

112

u32 rsv7[0x200 - 24]; /* pad to one page */

sys/dev/pci/drm/i915/i915_pvinfo.h

65

u32 vgt_id; /* ID of vGT instance */

sys/dev/pci/drm/i915/i915_pvinfo.h

66

u32 vgt_caps; /* VGT capabilities */

sys/dev/pci/drm/i915/i915_pvinfo.h

67

u32 rsv1[11]; /* pad to offset 0x40 */

sys/dev/pci/drm/i915/i915_pvinfo.h

77

u32 base;

sys/dev/pci/drm/i915/i915_pvinfo.h

78

u32 size;

sys/dev/pci/drm/i915/i915_pvinfo.h

82

u32 base;

sys/dev/pci/drm/i915/i915_pvinfo.h

83

u32 size;

sys/dev/pci/drm/i915/i915_pvinfo.h

86

u32 fence_num;

sys/dev/pci/drm/i915/i915_pvinfo.h

87

u32 rsv2[3];

sys/dev/pci/drm/i915/i915_pvinfo.h

89

u32 rsv3[0x200 - 24]; /* pad to half page */

sys/dev/pci/drm/i915/i915_pvinfo.h

93

u32 rsv4;

sys/dev/pci/drm/i915/i915_pvinfo.h

94

u32 display_ready; /* ready for display owner switch */

sys/dev/pci/drm/i915/i915_pvinfo.h

96

u32 rsv5[4];

sys/dev/pci/drm/i915/i915_pvinfo.h

98

u32 g2v_notify;

sys/dev/pci/drm/i915/i915_pvinfo.h

99

u32 rsv6[5];

sys/dev/pci/drm/i915/i915_query.c

16

u32 total_length,

sys/dev/pci/drm/i915/i915_query.c

178

static int can_copy_perf_config_registers_or_number(u32 user_n_regs,

sys/dev/pci/drm/i915/i915_query.c

180

u32 kernel_n_regs)

sys/dev/pci/drm/i915/i915_query.c

196

u32 kernel_n_regs,

sys/dev/pci/drm/i915/i915_query.c

198

u32 *user_n_regs)

sys/dev/pci/drm/i915/i915_query.c

200

u32 __user *p = u64_to_user_ptr(user_regs_ptr);

sys/dev/pci/drm/i915/i915_query.c

201

u32 r;

sys/dev/pci/drm/i915/i915_query.c

210

if (!user_write_access_begin(p, 2 * sizeof(u32) * kernel_n_regs))

sys/dev/pci/drm/i915/i915_query.c

239

u32 flags, total_size;

sys/dev/pci/drm/i915/i915_query.c

37

u32 slice_length, subslice_length, eu_length, total_length;

sys/dev/pci/drm/i915/i915_query.c

380

u32 flags;

sys/dev/pci/drm/i915/i915_query.c

481

u32 total_length;

sys/dev/pci/drm/i915/i915_query.c

614

u32 i;

sys/dev/pci/drm/i915/i915_reg_defs.h

163

#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])

sys/dev/pci/drm/i915/i915_reg_defs.h

178

u32 reg;

sys/dev/pci/drm/i915/i915_reg_defs.h

184

u32 reg;

sys/dev/pci/drm/i915/i915_reg_defs.h

42

((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \

sys/dev/pci/drm/i915/i915_reg_defs.h

75

#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))

sys/dev/pci/drm/i915/i915_request.c

1072

2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);

sys/dev/pci/drm/i915/i915_request.c

1229

u32 seqno)

sys/dev/pci/drm/i915/i915_request.c

1232

u32 hwsp_offset;

sys/dev/pci/drm/i915/i915_request.c

1234

u32 *cs;

sys/dev/pci/drm/i915/i915_request.c

1874

u32 *cs;

sys/dev/pci/drm/i915/i915_request.c

2331

u32 ring = ENGINE_READ(engine, RING_START);

sys/dev/pci/drm/i915/i915_request.c

242

u32 head;

sys/dev/pci/drm/i915/i915_request.c

971

u32 seqno;

sys/dev/pci/drm/i915/i915_request.h

279

const u32 *hwsp_seqno;

sys/dev/pci/drm/i915/i915_request.h

282

u32 head;

sys/dev/pci/drm/i915/i915_request.h

285

u32 infix;

sys/dev/pci/drm/i915/i915_request.h

292

u32 postfix;

sys/dev/pci/drm/i915/i915_request.h

295

u32 tail;

sys/dev/pci/drm/i915/i915_request.h

298

u32 wa_tail;

sys/dev/pci/drm/i915/i915_request.h

301

u32 reserved_space;

sys/dev/pci/drm/i915/i915_request.h

484

static inline bool i915_seqno_passed(u32 seq1, u32 seq2)

sys/dev/pci/drm/i915/i915_request.h

489

static inline u32 __hwsp_seqno(const struct i915_request *rq)

sys/dev/pci/drm/i915/i915_request.h

491

const u32 *hwsp = READ_ONCE(rq->hwsp_seqno);

sys/dev/pci/drm/i915/i915_request.h

509

static inline u32 hwsp_seqno(const struct i915_request *rq)

sys/dev/pci/drm/i915/i915_request.h

511

u32 seqno;

sys/dev/pci/drm/i915/i915_request.h

635

(u32 *)&rq->fence.seqno);

sys/dev/pci/drm/i915/i915_request.h

697

static inline u32

sys/dev/pci/drm/i915/i915_request.h

700

u32 hwsp_phys_base =

sys/dev/pci/drm/i915/i915_request.h

702

u32 hwsp_relative_offset = offset_in_page(rq->hwsp_seqno);

sys/dev/pci/drm/i915/i915_scatterlist.c

167

u32 page_alignment)

sys/dev/pci/drm/i915/i915_scatterlist.c

171

const u32 max_segment = round_down(UINT_MAX, page_alignment);

sys/dev/pci/drm/i915/i915_scatterlist.c

82

u32 page_alignment)

sys/dev/pci/drm/i915/i915_scatterlist.c

84

const u32 max_segment = round_down(UINT_MAX, page_alignment);

sys/dev/pci/drm/i915/i915_scatterlist.c

85

const u32 segment_pages = max_segment >> PAGE_SHIFT;

sys/dev/pci/drm/i915/i915_scatterlist.h

241

u32 page_alignment);

sys/dev/pci/drm/i915/i915_scatterlist.h

245

u32 page_alignment);

sys/dev/pci/drm/i915/i915_syncmap.c

132

static inline bool seqno_later(u32 a, u32 b)

sys/dev/pci/drm/i915/i915_syncmap.c

151

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

211

static inline void __sync_set_seqno(struct i915_syncmap *p, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

227

static noinline int __sync_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

350

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

79

DECLARE_FLEX_ARRAY(u32, seqno);

sys/dev/pci/drm/i915/i915_syncmap.c

96

static inline u32 *__sync_seqno(struct i915_syncmap *p)

sys/dev/pci/drm/i915/i915_syncmap.h

34

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/pci/drm/i915/i915_syncmap.h

35

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/pci/drm/i915/i915_sysfs.c

107

if (count < sizeof(u32))

sys/dev/pci/drm/i915/i915_sysfs.c

123

count = round_down(count, sizeof(u32));

sys/dev/pci/drm/i915/i915_sysfs.c

124

memcpy(remap_info + offset / sizeof(u32), buf, count);

sys/dev/pci/drm/i915/i915_sysfs.c

54

if (!IS_ALIGNED(offset, sizeof(u32)))

sys/dev/pci/drm/i915/i915_sysfs.c

77

count = round_down(count, sizeof(u32));

sys/dev/pci/drm/i915/i915_sysfs.c

84

i915->l3_parity.remap_info[slice] + offset / sizeof(u32),

sys/dev/pci/drm/i915/i915_sysfs.c

99

u32 *remap_info, *freeme = NULL;

sys/dev/pci/drm/i915/i915_user_extensions.c

25

u32 name;

sys/dev/pci/drm/i915/i915_vma.c

1383

void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)

sys/dev/pci/drm/i915/i915_vma.c

1664

u32 align, unsigned int flags)

sys/dev/pci/drm/i915/i915_vma.c

1699

u32 align, unsigned int flags)

sys/dev/pci/drm/i915/i915_vma.c

225

if (unlikely(overflows_type(vma->size, u32)))

sys/dev/pci/drm/i915/i915_vma.c

484

u32 flags,

sys/dev/pci/drm/i915/i915_vma.c

488

u32 bind_flags;

sys/dev/pci/drm/i915/i915_vma.c

489

u32 vma_flags;

sys/dev/pci/drm/i915/i915_vma.c

823

GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));

sys/dev/pci/drm/i915/i915_vma.c

824

guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);

sys/dev/pci/drm/i915/i915_vma.h

177

static inline u32 i915_ggtt_offset(const struct i915_vma *vma)

sys/dev/pci/drm/i915/i915_vma.h

187

static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)

sys/dev/pci/drm/i915/i915_vma.h

258

u32 flags,

sys/dev/pci/drm/i915/i915_vma.h

267

void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);

sys/dev/pci/drm/i915/i915_vma.h

300

u32 align, unsigned int flags);

sys/dev/pci/drm/i915/i915_vma_resource.c

301

u32 *tlb)

sys/dev/pci/drm/i915/i915_vma_resource.h

129

u32 guard;

sys/dev/pci/drm/i915/i915_vma_resource.h

130

u32 page_sizes_gtt;

sys/dev/pci/drm/i915/i915_vma_resource.h

132

u32 bound_flags;

sys/dev/pci/drm/i915/i915_vma_resource.h

138

u32 *tlb;

sys/dev/pci/drm/i915/i915_vma_resource.h

152

u32 *tlb);

sys/dev/pci/drm/i915/i915_vma_resource.h

214

u32 guard)

sys/dev/pci/drm/i915/i915_vma_types.h

102

BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 2 * sizeof(u32) + 8 * sizeof(u16));

sys/dev/pci/drm/i915/i915_vma_types.h

104

BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 5 * sizeof(u32) + 16 * sizeof(u16));

sys/dev/pci/drm/i915/i915_vma_types.h

158

u32 guard; /* padding allocated around vma->pages within the node */

sys/dev/pci/drm/i915/i915_vma_types.h

159

u32 fence_size;

sys/dev/pci/drm/i915/i915_vma_types.h

160

u32 fence_alignment;

sys/dev/pci/drm/i915/i915_vma_types.h

161

u32 display_alignment;

sys/dev/pci/drm/i915/intel_clock_gating.c

151

u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;

sys/dev/pci/drm/i915/intel_clock_gating.c

208

u32 val;

sys/dev/pci/drm/i915/intel_clock_gating.c

241

u32 tmp;

sys/dev/pci/drm/i915/intel_clock_gating.c

252

u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;

sys/dev/pci/drm/i915/intel_clock_gating.c

330

u32 misccpctl;

sys/dev/pci/drm/i915/intel_clock_gating.c

331

u32 val;

sys/dev/pci/drm/i915/intel_clock_gating.c

611

u32 dspclk_gate;

sys/dev/pci/drm/i915/intel_clock_gating.c

656

u32 dstate = intel_uncore_read(&i915->uncore, D_STATE);

sys/dev/pci/drm/i915/intel_device_info.c

236

u32 mask = 0;

sys/dev/pci/drm/i915/intel_device_info.c

297

static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)

sys/dev/pci/drm/i915/intel_device_info.c

303

u32 val;

sys/dev/pci/drm/i915/intel_device_info.c

308

addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));

sys/dev/pci/drm/i915/intel_device_info.h

210

u32 platform_mask[2];

sys/dev/pci/drm/i915/intel_device_info.h

234

u32 memory_regions; /* regions supported by the HW */

sys/dev/pci/drm/i915/intel_device_info.h

245

u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];

sys/dev/pci/drm/i915/intel_device_info.h

246

u32 max_pat_index;

sys/dev/pci/drm/i915/intel_gvt.c

81

static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,

sys/dev/pci/drm/i915/intel_gvt.c

82

u32 size)

sys/dev/pci/drm/i915/intel_gvt.c

85

u32 *mmio, i;

sys/dev/pci/drm/i915/intel_gvt.c

95

u32 offset, u32 size)

sys/dev/pci/drm/i915/intel_gvt.h

37

u32 offset, u32 size);

sys/dev/pci/drm/i915/intel_pcode.c

11

static int gen6_check_mailbox_status(u32 mbox)

sys/dev/pci/drm/i915/intel_pcode.c

113

int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,

sys/dev/pci/drm/i915/intel_pcode.c

131

static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,

sys/dev/pci/drm/i915/intel_pcode.c

132

u32 request, u32 reply_mask, u32 reply,

sys/dev/pci/drm/i915/intel_pcode.c

133

u32 *status)

sys/dev/pci/drm/i915/intel_pcode.c

159

int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,

sys/dev/pci/drm/i915/intel_pcode.c

160

u32 reply_mask, u32 reply, int timeout_base_ms)

sys/dev/pci/drm/i915/intel_pcode.c

162

u32 status;

sys/dev/pci/drm/i915/intel_pcode.c

245

int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)

sys/dev/pci/drm/i915/intel_pcode.c

248

u32 mbox;

sys/dev/pci/drm/i915/intel_pcode.c

261

int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)

sys/dev/pci/drm/i915/intel_pcode.c

264

u32 mbox;

sys/dev/pci/drm/i915/intel_pcode.c

278

int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)

sys/dev/pci/drm/i915/intel_pcode.c

285

int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)

sys/dev/pci/drm/i915/intel_pcode.c

292

int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,

sys/dev/pci/drm/i915/intel_pcode.c

293

u32 reply_mask, u32 reply, int timeout_base_ms)

sys/dev/pci/drm/i915/intel_pcode.c

31

static int gen7_check_mailbox_status(u32 mbox)

sys/dev/pci/drm/i915/intel_pcode.c

56

static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,

sys/dev/pci/drm/i915/intel_pcode.c

57

u32 *val, u32 *val1,

sys/dev/pci/drm/i915/intel_pcode.c

96

int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)

sys/dev/pci/drm/i915/intel_pcode.h

14

int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);

sys/dev/pci/drm/i915/intel_pcode.h

15

int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms);

sys/dev/pci/drm/i915/intel_pcode.h

19

int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,

sys/dev/pci/drm/i915/intel_pcode.h

20

u32 reply_mask, u32 reply, int timeout_base_ms);

sys/dev/pci/drm/i915/intel_pcode.h

27

int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);

sys/dev/pci/drm/i915/intel_pcode.h

28

int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);

sys/dev/pci/drm/i915/intel_pcode.h

31

int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);

sys/dev/pci/drm/i915/intel_pcode.h

32

int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);

sys/dev/pci/drm/i915/intel_pcode.h

36

int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,

sys/dev/pci/drm/i915/intel_pcode.h

37

u32 reply_mask, u32 reply, int timeout_base_ms);

sys/dev/pci/drm/i915/intel_region_ttm.c

171

u32 page_alignment)

sys/dev/pci/drm/i915/intel_region_ttm.h

28

u32 page_alignment);

sys/dev/pci/drm/i915/intel_uncore.c

1192

static int mmio_range_cmp(u32 key, const struct i915_range *range)

sys/dev/pci/drm/i915/intel_uncore.c

1202

static bool is_shadowed(struct intel_uncore *uncore, u32 offset)

sys/dev/pci/drm/i915/intel_uncore.c

1233

const u32 __offset = (offset); \

sys/dev/pci/drm/i915/intel_uncore.c

169

const u32 ack,

sys/dev/pci/drm/i915/intel_uncore.c

170

const u32 value)

sys/dev/pci/drm/i915/intel_uncore.c

178

const u32 ack)

sys/dev/pci/drm/i915/intel_uncore.c

185

const u32 ack)

sys/dev/pci/drm/i915/intel_uncore.c

1901

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.c

2007

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.c

219

const u32 ack_bit = FORCEWAKE_KERNEL;

sys/dev/pci/drm/i915/intel_uncore.c

220

const u32 value = type == ACK_SET ? ack_bit : 0;

sys/dev/pci/drm/i915/intel_uncore.c

2268

u32 ecobus;

sys/dev/pci/drm/i915/intel_uncore.c

2769

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.c

2770

u32 value,

sys/dev/pci/drm/i915/intel_uncore.c

2773

u32 *out_value)

sys/dev/pci/drm/i915/intel_uncore.c

2775

u32 reg_value = 0;

sys/dev/pci/drm/i915/intel_uncore.c

2818

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.c

2819

u32 value,

sys/dev/pci/drm/i915/intel_uncore.c

2822

u32 *out_value)

sys/dev/pci/drm/i915/intel_uncore.c

2826

u32 reg_value;

sys/dev/pci/drm/i915/intel_uncore.c

374

static inline u32 gt_thread_status(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/intel_uncore.c

376

u32 val;

sys/dev/pci/drm/i915/intel_uncore.c

404

static inline u32 fifo_free_entries(struct intel_uncore *uncore)

sys/dev/pci/drm/i915/intel_uncore.c

406

u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);

sys/dev/pci/drm/i915/intel_uncore.c

413

u32 n;

sys/dev/pci/drm/i915/intel_uncore.c

554

u32 dbg;

sys/dev/pci/drm/i915/intel_uncore.c

584

u32 cer;

sys/dev/pci/drm/i915/intel_uncore.c

598

u32 fifodbg;

sys/dev/pci/drm/i915/intel_uncore.c

951

u32 __reg = (reg); \

sys/dev/pci/drm/i915/intel_uncore.c

955

static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)

sys/dev/pci/drm/i915/intel_uncore.c

985

find_fw_domain(struct intel_uncore *uncore, u32 offset)

sys/dev/pci/drm/i915/intel_uncore.h

106

u32 (*mmio_readl)(struct intel_uncore *uncore,

sys/dev/pci/drm/i915/intel_uncore.h

116

i915_reg_t r, u32 val, bool trace);

sys/dev/pci/drm/i915/intel_uncore.h

120

u32 start;

sys/dev/pci/drm/i915/intel_uncore.h

121

u32 end;

sys/dev/pci/drm/i915/intel_uncore.h

128

u32 start;

sys/dev/pci/drm/i915/intel_uncore.h

129

u32 end;

sys/dev/pci/drm/i915/intel_uncore.h

149

u32 gsi_offset;

sys/dev/pci/drm/i915/intel_uncore.h

186

u32 __iomem *reg_set;

sys/dev/pci/drm/i915/intel_uncore.h

187

u32 __iomem *reg_ack;

sys/dev/pci/drm/i915/intel_uncore.h

288

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

289

u32 value,

sys/dev/pci/drm/i915/intel_uncore.h

292

u32 *out_value);

sys/dev/pci/drm/i915/intel_uncore.h

296

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

297

u32 value,

sys/dev/pci/drm/i915/intel_uncore.h

306

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

307

u32 value,

sys/dev/pci/drm/i915/intel_uncore.h

310

u32 *out_value);

sys/dev/pci/drm/i915/intel_uncore.h

314

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

315

u32 value,

sys/dev/pci/drm/i915/intel_uncore.h

317

u32 *out_value)

sys/dev/pci/drm/i915/intel_uncore.h

330

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.h

340

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.h

436

static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,

sys/dev/pci/drm/i915/intel_uncore.h

437

i915_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/intel_uncore.h

439

u32 old, val;

sys/dev/pci/drm/i915/intel_uncore.h

448

i915_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/intel_uncore.h

450

u32 old, val;

sys/dev/pci/drm/i915/intel_uncore.h

46

u32 suspend_count;

sys/dev/pci/drm/i915/intel_uncore.h

462

u32 upper, lower, old_upper, loop = 0;

sys/dev/pci/drm/i915/intel_uncore.h

489

i915_reg_t reg, u32 val,

sys/dev/pci/drm/i915/intel_uncore.h

490

u32 mask, u32 expected_val)

sys/dev/pci/drm/i915/intel_uncore.h

492

u32 reg_val;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

67

u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :

sys/dev/pci/drm/i915/pxp/intel_pxp.h

27

void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

101

u32 *cs;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

23

static u32 *pxp_emit_session_selection(u32 *cs, u32 idx)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

48

static u32 *pxp_emit_inline_termination(u32 *cs)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

57

static u32 *pxp_emit_session_termination(u32 *cs, u32 idx)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

65

static u32 *pxp_emit_wait(u32 *cs)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

97

int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.h

13

int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 idx);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_42.h

21

u32 protection_mode;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_42.h

23

u32 session_id;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_42.h

34

u32 rsvd[3];

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_42.h

40

u32 rsvd;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

33

u32 huc_size;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

48

u32 protection_mode;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

50

u32 sub_session_id;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

51

u32 init_flags;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

52

u32 rsvd[12];

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

58

u32 rsvd[8];

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

29

u32 api_version;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

30

u32 command_id;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

32

u32 status; /* out */

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

33

u32 stream_id; /* in */

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

39

u32 buffer_len;

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

21

is_fw_err_platform_config(struct intel_pxp *pxp, u32 type)

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

247

void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id)

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

36

fw_err_to_string(u32 type)

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

65

u32 reply_size;

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h

25

void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);

sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c

54

static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts)

sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c

57

const u32 mask = interrupts << 16;

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

153

u32 events = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

18

static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

22

u32 sip = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

31

static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

35

u32 mask = BIT(id);

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

109

u8 client_id, u32 fence_id,

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

27

is_fw_err_platform_config(struct intel_pxp *pxp, u32 type)

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

376

void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id)

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

42

fw_err_to_string(u32 type)

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

59

void *msg_in, u32 msg_in_size,

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

60

void *msg_out, u32 msg_out_max_size,

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

61

u32 *msg_out_rcv_size)

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.h

18

u8 client_id, u32 fence_id,

sys/dev/pci/drm/i915/pxp/intel_pxp_types.h

123

u32 session_events;

sys/dev/pci/drm/i915/pxp/intel_pxp_types.h

42

u32 kcr_base;

sys/dev/pci/drm/i915/pxp/intel_pxp_types.h

93

u32 key_instance;

sys/dev/pci/drm/i915/selftests/i915_gem.c

59

u32 __iomem *s;

sys/dev/pci/drm/i915/selftests/i915_gem.c

68

for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1346

const unsigned int count = PAGE_SIZE/sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1399

u32 __iomem *vaddr;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1410

u32 __iomem *vaddr;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1411

u32 val;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

265

aligned_size = max_t(u32, ilog2(min_alignment), size);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

267

if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

268

hole_size = KMALLOC_MAX_SIZE / sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

816

aligned_size = max_t(u32, ilog2(min_alignment), size);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

818

if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

819

hole_size = KMALLOC_MAX_SIZE / sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

163

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_perf.c

178

*cs++ = slot * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

204

u32 delay;

sys/dev/pci/drm/i915/selftests/i915_perf.c

295

u32 *cs, *store;

sys/dev/pci/drm/i915/selftests/i915_perf.c

297

u32 gpr0;

sys/dev/pci/drm/i915/selftests/i915_perf.c

344

*cs++ = gpr0 + i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

362

u32 cmd;

sys/dev/pci/drm/i915/selftests/i915_perf.c

377

*cs++ = gpr0 + i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

380

i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_random.h

47

static inline u32 i915_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)

sys/dev/pci/drm/i915/selftests/i915_request.c

1122

u32 *cmd;

sys/dev/pci/drm/i915/selftests/i915_request.c

1172

u32 *cmd;

sys/dev/pci/drm/i915/selftests/i915_request.c

1430

u32 *cmd;

sys/dev/pci/drm/i915/selftests/i915_request.c

1931

const u32 *a = A, *b = B;

sys/dev/pci/drm/i915/selftests/i915_request.c

1936

static u32 trifilter(u32 *a)

sys/dev/pci/drm/i915/selftests/i915_request.c

1952

static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles)

sys/dev/pci/drm/i915/selftests/i915_request.c

1959

static u32 *emit_timestamp_store(u32 *cs, struct intel_context *ce, u32 offset)

sys/dev/pci/drm/i915/selftests/i915_request.c

1969

static u32 *emit_store_dw(u32 *cs, u32 offset, u32 value)

sys/dev/pci/drm/i915/selftests/i915_request.c

1979

static u32 *emit_semaphore_poll(u32 *cs, u32 mode, u32 value, u32 offset)

sys/dev/pci/drm/i915/selftests/i915_request.c

1992

static u32 *emit_semaphore_poll_until(u32 *cs, u32 offset, u32 value)

sys/dev/pci/drm/i915/selftests/i915_request.c

1997

static void semaphore_set(u32 *sema, u32 value)

sys/dev/pci/drm/i915/selftests/i915_request.c

2003

static u32 *hwsp_scratch(const struct intel_context *ce)

sys/dev/pci/drm/i915/selftests/i915_request.c

2008

static u32 hwsp_offset(const struct intel_context *ce, u32 *dw)

sys/dev/pci/drm/i915/selftests/i915_request.c

2016

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2017

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2018

u32 elapsed[TF_COUNT], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2020

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2051

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2091

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2092

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2093

u32 elapsed[TF_COUNT], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2094

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2129

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2162

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2163

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2164

u32 elapsed[TF_COUNT + 1], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2165

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2197

cs = emit_store_dw(cs, offset + i * sizeof(u32), -1);

sys/dev/pci/drm/i915/selftests/i915_request.c

2199

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2237

static int plug(struct intel_engine_cs *engine, u32 *sema, u32 mode, int value)

sys/dev/pci/drm/i915/selftests/i915_request.c

2239

const u32 offset =

sys/dev/pci/drm/i915/selftests/i915_request.c

2243

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2265

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2266

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2267

u32 elapsed[TF_COUNT + 1], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2298

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2321

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2356

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2357

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2359

u32 elapsed[TF_COUNT + 1], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2361

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2384

u32 addr = offset + ARRAY_SIZE(arr) * i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_request.c

2412

addr += sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_request.c

2450

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2451

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2452

u32 elapsed[TF_COUNT], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2453

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2477

u32 addr = offset + 2 * i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_request.c

2495

cs = emit_timestamp_store(cs, ce, addr + sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2570

u32 *sema = hwsp_scratch(ce);

sys/dev/pci/drm/i915/selftests/i915_request.c

2571

const u32 offset = hwsp_offset(ce, sema);

sys/dev/pci/drm/i915/selftests/i915_request.c

2572

u32 elapsed[TF_COUNT], cycles;

sys/dev/pci/drm/i915/selftests/i915_request.c

2573

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2605

cs = emit_store_dw(cs, offset + i * sizeof(u32), -1);

sys/dev/pci/drm/i915/selftests/i915_request.c

2607

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

963

u32 *cmd;

sys/dev/pci/drm/i915/selftests/i915_selftest.c

260

u32 pg_enable;

sys/dev/pci/drm/i915/selftests/i915_selftest.c

479

const size_t rowsize = 8 * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_selftest.c

496

rowsize, sizeof(u32),

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

146

static int check_seqno(struct i915_syncmap *leaf, unsigned int idx, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

163

static int check_one(struct i915_syncmap **sync, u64 context, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

238

static int check_leaf(struct i915_syncmap **sync, u64 context, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

548

u32 seqno;

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

575

u32 last_seqno = seqno;

sys/dev/pci/drm/i915/selftests/i915_vma.c

1010

u32 __iomem *map;

sys/dev/pci/drm/i915/selftests/i915_vma.c

1041

u32 val = y << 16 | x;

sys/dev/pci/drm/i915/selftests/i915_vma.c

1072

u32 exp = y << 16 | x;

sys/dev/pci/drm/i915/selftests/i915_vma.c

1073

u32 val;

sys/dev/pci/drm/i915/selftests/igt_spinner.c

114

return offset_in_page(sizeof(u32) * fence);

sys/dev/pci/drm/i915/selftests/igt_spinner.c

126

u32 arbitration_command)

sys/dev/pci/drm/i915/selftests/igt_spinner.c

132

u32 *batch;

sys/dev/pci/drm/i915/selftests/igt_spinner.c

220

static u32

sys/dev/pci/drm/i915/selftests/igt_spinner.c

223

u32 *seqno = spin->seqno + seqno_offset(rq->fence.context);

sys/dev/pci/drm/i915/selftests/igt_spinner.h

25

u32 *batch;

sys/dev/pci/drm/i915/selftests/igt_spinner.h

38

u32 arbitration_command);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1016

u32 bytes[] = {

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1018

sizeof(u32),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1022

PAGE_SIZE - sizeof(u32),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1028

u32 *vaddr;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1029

u32 sz;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1030

u32 i;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1042

sz = max_t(u32, 2 * PAGE_SIZE, sz);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1090

bytes[0] = igt_random_offset(&prng, 64, PAGE_SIZE - 64, 0, sizeof(u32));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1091

GEM_BUG_ON(!IS_ALIGNED(bytes[0], sizeof(u32)));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1095

u32 offset;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1096

u32 align;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1097

u32 dword;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1098

u32 size;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1099

u32 val;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1107

align = max_t(u32, sizeof(u32), rounddown_pow_of_two(align));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1113

memset32(vaddr + offset / sizeof(u32), val ^ 0xdeadbeaf,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1114

size / sizeof(u32));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1122

sizeof(u32), sizeof(u32));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1123

dword /= sizeof(u32);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1141

static const char *repr_type(u32 type)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1154

create_region_for_mapping(struct intel_memory_region *mr, u64 size, u32 type,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1208

u64 size, u32 src_type, u32 dst_type)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1306

static const u32 types[] = {

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1310

static const u32 sizes[] = {

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

162

const u32 chunk_size = SZ_32M;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

163

u32 i, offset, count, *order;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

208

u32 size = i915_prandom_u32_max_state(cur_avail, &prng);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

210

size = max_t(u32, round_up(size, PAGE_SIZE), PAGE_SIZE);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

668

u32 dword,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

669

u32 value)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

671

return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

675

static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

678

u32 *ptr;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

753

u32 rng = prandom_u32_state(&prng);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

754

u32 dword = offset_in_page(rng) / 4;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

807

u32 ps;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

870

u32 size, i;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

875

size = max_t(u32, PAGE_SIZE, i915_prandom_u32_max_state(SZ_32M, &prng));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

882

u32 dword, val;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

906

dword = i915_prandom_u32_max_state(PAGE_SIZE / sizeof(u32),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

926

memset32(vaddr, val, obj->base.size / sizeof(u32));

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

954

u32 sz;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.h

16

u32 flags;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.h

17

u32 reset;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

212

u32 __iomem *reg = intel_uncore_regs(uncore) + engine->mmio_base + r->offset;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

214

u32 val;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

283

u32 offset;

sys/dev/pci/drm/i915/selftests/librapl.c

23

u32 units;

sys/dev/pci/drm/i915/selftests/mock_gtt.c

31

u32 flags)

sys/dev/pci/drm/i915/selftests/mock_gtt.c

37

unsigned int pat_index, u32 flags)

sys/dev/pci/drm/i915/selftests/mock_gtt.c

45

u32 flags)

sys/dev/pci/drm/i915/selftests/mock_gtt.c

98

u32 flags)

sys/dev/pci/drm/i915/soc/intel_dram.c

106

u32 val;

sys/dev/pci/drm/i915/soc/intel_dram.c

122

u32 val;

sys/dev/pci/drm/i915/soc/intel_dram.c

157

u32 fsb;

sys/dev/pci/drm/i915/soc/intel_dram.c

365

int channel, u32 val)

sys/dev/pci/drm/i915/soc/intel_dram.c

406

u32 val;

sys/dev/pci/drm/i915/soc/intel_dram.c

450

u32 val;

sys/dev/pci/drm/i915/soc/intel_dram.c

485

static int bxt_get_dimm_size(u32 val)

sys/dev/pci/drm/i915/soc/intel_dram.c

504

static int bxt_get_dimm_width(u32 val)

sys/dev/pci/drm/i915/soc/intel_dram.c

514

static int bxt_get_dimm_ranks(u32 val)

sys/dev/pci/drm/i915/soc/intel_dram.c

530

static enum intel_dram_type bxt_get_dimm_type(u32 val)

sys/dev/pci/drm/i915/soc/intel_dram.c

550

static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)

sys/dev/pci/drm/i915/soc/intel_dram.c

564

u32 val;

sys/dev/pci/drm/i915/soc/intel_dram.c

611

u32 val = 0;

sys/dev/pci/drm/i915/soc/intel_dram.c

67

u32 tmp;

sys/dev/pci/drm/i915/soc/intel_dram.c

688

u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);

sys/dev/pci/drm/i915/soc/intel_dram.c

784

static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)

sys/dev/pci/drm/i915/soc/intel_dram.c

796

u32 edram_cap = 0;

sys/dev/pci/drm/i915/soc/intel_gmch.c

116

u32 temp;

sys/dev/pci/drm/i915/soc/intel_gmch.c

155

u32 deven_val;

sys/dev/pci/drm/i915/soc/intel_gmch.c

163

u32 mchbar_val;

sys/dev/pci/drm/i915/soc/intel_gmch.c

66

u32 temp_lo, temp_hi = 0;

sys/dev/pci/drm/i915/soc/intel_rom.c

125

u32 intel_rom_read32(struct intel_rom *rom, loff_t offset)

sys/dev/pci/drm/i915/soc/intel_rom.c

138

u32 *ptr = data;

sys/dev/pci/drm/i915/soc/intel_rom.c

150

loff_t intel_rom_find(struct intel_rom *rom, u32 needle)

sys/dev/pci/drm/i915/soc/intel_rom.c

29

u32 (*read32)(struct intel_rom *rom, loff_t offset);

sys/dev/pci/drm/i915/soc/intel_rom.c

35

static u32 spi_read32(struct intel_rom *rom, loff_t offset)

sys/dev/pci/drm/i915/soc/intel_rom.c

51

u32 static_region;

sys/dev/pci/drm/i915/soc/intel_rom.c

73

static u32 pci_read32(struct intel_rom *rom, loff_t offset)

sys/dev/pci/drm/i915/soc/intel_rom.h

17

u32 intel_rom_read32(struct intel_rom *rom, loff_t offset);

sys/dev/pci/drm/i915/soc/intel_rom.h

21

loff_t intel_rom_find(struct intel_rom *rom, u32 needle);

sys/dev/pci/drm/i915/vlv_iosf_sb.c

136

static u32 unit_to_devfn(enum vlv_iosf_sb_unit unit)

sys/dev/pci/drm/i915/vlv_iosf_sb.c

145

static u32 unit_to_port(enum vlv_iosf_sb_unit unit)

sys/dev/pci/drm/i915/vlv_iosf_sb.c

171

static u32 unit_to_opcode(enum vlv_iosf_sb_unit unit, bool write)

sys/dev/pci/drm/i915/vlv_iosf_sb.c

179

u32 vlv_iosf_sb_read(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr)

sys/dev/pci/drm/i915/vlv_iosf_sb.c

182

u32 devfn, port, opcode, val = 0;

sys/dev/pci/drm/i915/vlv_iosf_sb.c

198

int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val)

sys/dev/pci/drm/i915/vlv_iosf_sb.c

201

u32 devfn, port, opcode;

sys/dev/pci/drm/i915/vlv_iosf_sb.c

87

u32 devfn, u32 port, u32 opcode,

sys/dev/pci/drm/i915/vlv_iosf_sb.c

88

u32 addr, u32 *val)

sys/dev/pci/drm/i915/vlv_iosf_sb.h

34

u32 vlv_iosf_sb_read(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr);

sys/dev/pci/drm/i915/vlv_iosf_sb.h

35

int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val);

sys/dev/pci/drm/i915/vlv_suspend.c

24

u32 wr_watermark;

sys/dev/pci/drm/i915/vlv_suspend.c

25

u32 gfx_prio_ctrl;

sys/dev/pci/drm/i915/vlv_suspend.c

26

u32 arb_mode;

sys/dev/pci/drm/i915/vlv_suspend.c

27

u32 gfx_pend_tlb0;

sys/dev/pci/drm/i915/vlv_suspend.c

28

u32 gfx_pend_tlb1;

sys/dev/pci/drm/i915/vlv_suspend.c

282

u32 mask, u32 val)

sys/dev/pci/drm/i915/vlv_suspend.c

285

u32 reg_value;

sys/dev/pci/drm/i915/vlv_suspend.c

29

u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];

sys/dev/pci/drm/i915/vlv_suspend.c

30

u32 media_max_req_count;

sys/dev/pci/drm/i915/vlv_suspend.c

31

u32 gfx_max_req_count;

sys/dev/pci/drm/i915/vlv_suspend.c

32

u32 render_hwsp;

sys/dev/pci/drm/i915/vlv_suspend.c

33

u32 ecochk;

sys/dev/pci/drm/i915/vlv_suspend.c

332

u32 mask;

sys/dev/pci/drm/i915/vlv_suspend.c

333

u32 val;

sys/dev/pci/drm/i915/vlv_suspend.c

34

u32 bsd_hwsp;

sys/dev/pci/drm/i915/vlv_suspend.c

35

u32 blt_hwsp;

sys/dev/pci/drm/i915/vlv_suspend.c

353

u32 mask;

sys/dev/pci/drm/i915/vlv_suspend.c

354

u32 val;

sys/dev/pci/drm/i915/vlv_suspend.c

36

u32 tlb_rd_addr;

sys/dev/pci/drm/i915/vlv_suspend.c

385

u32 mask;

sys/dev/pci/drm/i915/vlv_suspend.c

39

u32 g3dctl;

sys/dev/pci/drm/i915/vlv_suspend.c

40

u32 gsckgctl;

sys/dev/pci/drm/i915/vlv_suspend.c

41

u32 mbctl;

sys/dev/pci/drm/i915/vlv_suspend.c

44

u32 ucgctl1;

sys/dev/pci/drm/i915/vlv_suspend.c

45

u32 ucgctl3;

sys/dev/pci/drm/i915/vlv_suspend.c

46

u32 rcgctl1;

sys/dev/pci/drm/i915/vlv_suspend.c

47

u32 rcgctl2;

sys/dev/pci/drm/i915/vlv_suspend.c

48

u32 rstctl;

sys/dev/pci/drm/i915/vlv_suspend.c

49

u32 misccpctl;

sys/dev/pci/drm/i915/vlv_suspend.c

52

u32 gfxpause;

sys/dev/pci/drm/i915/vlv_suspend.c

53

u32 rpdeuhwtc;

sys/dev/pci/drm/i915/vlv_suspend.c

54

u32 rpdeuc;

sys/dev/pci/drm/i915/vlv_suspend.c

55

u32 ecobus;

sys/dev/pci/drm/i915/vlv_suspend.c

56

u32 pwrdwnupctl;

sys/dev/pci/drm/i915/vlv_suspend.c

57

u32 rp_down_timeout;

sys/dev/pci/drm/i915/vlv_suspend.c

58

u32 rp_deucsw;

sys/dev/pci/drm/i915/vlv_suspend.c

59

u32 rcubmabdtmr;

sys/dev/pci/drm/i915/vlv_suspend.c

60

u32 rcedata;

sys/dev/pci/drm/i915/vlv_suspend.c

61

u32 spare2gh;

sys/dev/pci/drm/i915/vlv_suspend.c

64

u32 gt_imr;

sys/dev/pci/drm/i915/vlv_suspend.c

65

u32 gt_ier;

sys/dev/pci/drm/i915/vlv_suspend.c

66

u32 pm_imr;

sys/dev/pci/drm/i915/vlv_suspend.c

67

u32 pm_ier;

sys/dev/pci/drm/i915/vlv_suspend.c

68

u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

sys/dev/pci/drm/i915/vlv_suspend.c

71

u32 tilectl;

sys/dev/pci/drm/i915/vlv_suspend.c

72

u32 gt_fifoctl;

sys/dev/pci/drm/i915/vlv_suspend.c

73

u32 gtlc_wake_ctrl;

sys/dev/pci/drm/i915/vlv_suspend.c

74

u32 gtlc_survive;

sys/dev/pci/drm/i915/vlv_suspend.c

75

u32 pmwgicz;

sys/dev/pci/drm/i915/vlv_suspend.c

78

u32 gu_ctl0;

sys/dev/pci/drm/i915/vlv_suspend.c

79

u32 gu_ctl1;

sys/dev/pci/drm/i915/vlv_suspend.c

80

u32 pcbr;

sys/dev/pci/drm/i915/vlv_suspend.c

81

u32 clock_gate_dis2;

sys/dev/pci/drm/include/drm/amd/isp.h

37

u32 asic_type;

sys/dev/pci/drm/include/drm/clients/drm_client_setup.h

14

void drm_client_setup_with_fourcc(struct drm_device *dev, u32 fourcc);

sys/dev/pci/drm/include/drm/clients/drm_client_setup.h

20

static inline void drm_client_setup_with_fourcc(struct drm_device *dev, u32 fourcc)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

222

static inline u32

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

764

u32 quirks;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

854

u32 max;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

864

u32 max_luminance,

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

866

u32 *current_level, u8 *current_mode, bool need_luminance);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

868

u32 level);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

870

u32 level);

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

369

u32 dpcd_address;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

375

u32 dpcd_address;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

604

u32 pending_crtc_mask;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

614

u32 payload_mask;

sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h

219

u32 *stream_mask)

sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h

226

u32 *failed_stream_mask)

sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h

88

u32 *stream_mask);

sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h

91

u32 *failed_stream_mask);

sys/dev/pci/drm/include/drm/display/drm_dsc.h

539

u32 pps_long_94_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

544

u32 pps_long_98_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

549

u32 pps_long_102_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

554

u32 pps_long_106_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

559

u32 pps_long_110_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

564

u32 pps_long_114_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

569

u32 pps_long_118_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

574

u32 pps_long_122_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc_helper.h

31

u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);

sys/dev/pci/drm/include/drm/display/drm_dsc_helper.h

32

u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg);

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

261

u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

263

return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

267

void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)

sys/dev/pci/drm/include/drm/display/drm_hdcp_helper.h

17

int drm_hdcp_check_ksvs_revoked(struct drm_device *dev, u8 *ksvs, u32 ksv_count);

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

39

u32 signal_free_time, struct cec_msg *msg);

sys/dev/pci/drm/include/drm/drm_atomic.h

1202

u32 format;

sys/dev/pci/drm/include/drm/drm_atomic.h

1207

u32 flags;

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

290

u32 *

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

295

u32 output_fmt,

sys/dev/pci/drm/include/drm/drm_bridge.h

1350

u32 *

sys/dev/pci/drm/include/drm/drm_bridge.h

1355

u32 output_fmt,

sys/dev/pci/drm/include/drm/drm_bridge.h

1376

u32 connector_type);

sys/dev/pci/drm/include/drm/drm_bridge.h

1384

u32 connector_type);

sys/dev/pci/drm/include/drm/drm_bridge.h

1403

u32 port, u32 endpoint);

sys/dev/pci/drm/include/drm/drm_bridge.h

1405

u32 port, u32 endpoint);

sys/dev/pci/drm/include/drm/drm_bridge.h

1409

u32 port,

sys/dev/pci/drm/include/drm/drm_bridge.h

1410

u32 endpoint)

sys/dev/pci/drm/include/drm/drm_bridge.h

1417

u32 port,

sys/dev/pci/drm/include/drm/drm_bridge.h

1418

u32 endpoint)

sys/dev/pci/drm/include/drm/drm_bridge.h

429

u32 *(*atomic_get_output_bus_fmts)(struct drm_bridge *bridge,

sys/dev/pci/drm/include/drm/drm_bridge.h

469

u32 *(*atomic_get_input_bus_fmts)(struct drm_bridge *bridge,

sys/dev/pci/drm/include/drm/drm_bridge.h

473

u32 output_fmt,

sys/dev/pci/drm/include/drm/drm_bridge.h

809

u32 signal_free_time, struct cec_msg *msg);

sys/dev/pci/drm/include/drm/drm_bridge.h

889

u32 input_bus_flags;

sys/dev/pci/drm/include/drm/drm_bridge.h

896

u32 setup_time_ps;

sys/dev/pci/drm/include/drm/drm_bridge.h

903

u32 hold_time_ps;

sys/dev/pci/drm/include/drm/drm_client.h

179

u32 pitch;

sys/dev/pci/drm/include/drm/drm_client.h

205

drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format);

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

120

int drm_color_lut_check(const struct drm_property_blob *lut, u32 tests);

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

43

static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

53

u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n);

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

89

u32 supported_encodings,

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

90

u32 supported_ranges,

sys/dev/pci/drm/include/drm/drm_connector.h

2172

u32 possible_encoders;

sys/dev/pci/drm/include/drm/drm_connector.h

2361

static inline u32 drm_connector_mask(const struct drm_connector *connector)

sys/dev/pci/drm/include/drm/drm_connector.h

2455

u32 scaling_mode_mask);

sys/dev/pci/drm/include/drm/drm_connector.h

2465

u32 supported_colorspaces);

sys/dev/pci/drm/include/drm/drm_connector.h

2467

u32 supported_colorspaces);

sys/dev/pci/drm/include/drm/drm_connector.h

437

u32 min_luminance;

sys/dev/pci/drm/include/drm/drm_connector.h

438

u32 max_luminance;

sys/dev/pci/drm/include/drm/drm_connector.h

722

u32 color_formats;

sys/dev/pci/drm/include/drm/drm_connector.h

729

const u32 *bus_formats;

sys/dev/pci/drm/include/drm/drm_connector.h

740

u32 bus_flags;

sys/dev/pci/drm/include/drm/drm_connector.h

838

u32 max_dsc_bpp;

sys/dev/pci/drm/include/drm/drm_connector.h

855

u32 quirks;

sys/dev/pci/drm/include/drm/drm_connector.h

867

const u32 *formats,

sys/dev/pci/drm/include/drm/drm_crtc.h

195

u32 plane_mask;

sys/dev/pci/drm/include/drm/drm_crtc.h

201

u32 connector_mask;

sys/dev/pci/drm/include/drm/drm_crtc.h

207

u32 encoder_mask;

sys/dev/pci/drm/include/drm/drm_crtc.h

283

u32 target_vblank;

sys/dev/pci/drm/include/drm/drm_crtc.h

861

u32 (*get_vblank_counter)(struct drm_crtc *crtc);

sys/dev/pci/drm/include/drm/drm_debugfs.h

118

u32 driver_features;

sys/dev/pci/drm/include/drm/drm_debugfs.h

71

u32 driver_features;

sys/dev/pci/drm/include/drm/drm_device.h

222

u32 driver_features;

sys/dev/pci/drm/include/drm/drm_device.h

347

u32 max_vblank_count;

sys/dev/pci/drm/include/drm/drm_drv.h

425

u32 driver_features;

sys/dev/pci/drm/include/drm/drm_drv.h

545

u32 features)

sys/dev/pci/drm/include/drm/drm_drv.h

547

u32 supported = dev->driver->driver_features & dev->driver_features;

sys/dev/pci/drm/include/drm/drm_edid.h

299

u32 serial; /* FIXME: byte order */

sys/dev/pci/drm/include/drm/drm_edid.h

339

u32 panel_id;

sys/dev/pci/drm/include/drm/drm_edid.h

411

((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \

sys/dev/pci/drm/include/drm/drm_edid.h

412

(((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \

sys/dev/pci/drm/include/drm/drm_edid.h

413

(((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \

sys/dev/pci/drm/include/drm/drm_edid.h

432

static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id)

sys/dev/pci/drm/include/drm/drm_edid.h

489

u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid);

sys/dev/pci/drm/include/drm/drm_encoder.h

284

static inline u32 drm_encoder_mask(const struct drm_encoder *encoder)

sys/dev/pci/drm/include/drm/drm_exec.h

138

void drm_exec_init(struct drm_exec *exec, u32 flags, unsigned nr);

sys/dev/pci/drm/include/drm/drm_exec.h

21

u32 flags;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

151

u32 pseudo_palette[17];

sys/dev/pci/drm/include/drm/drm_fb_helper.h

273

void drm_fb_helper_damage_area(struct fb_info *info, u32 x, u32 y, u32 width, u32 height);

sys/dev/pci/drm/include/drm/drm_fb_helper.h

58

u32 fb_width;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

59

u32 fb_height;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

60

u32 surface_width;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

61

u32 surface_height;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

62

u32 surface_bpp;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

63

u32 surface_depth;

sys/dev/pci/drm/include/drm/drm_fixed.h

170

u32 i = DRM_FIXED_POINT;

sys/dev/pci/drm/include/drm/drm_fixed.h

33

u32 full;

sys/dev/pci/drm/include/drm/drm_fixed.h

37

#define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */

sys/dev/pci/drm/include/drm/drm_fixed.h

38

#define dfixed_const_half(A) (u32)(((A) << 12) + 2048)

sys/dev/pci/drm/include/drm/drm_fixed.h

39

#define dfixed_const_666(A) (u32)(((A) << 12) + 2731)

sys/dev/pci/drm/include/drm/drm_fixed.h

40

#define dfixed_const_8(A) (u32)(((A) << 12) + 3277)

sys/dev/pci/drm/include/drm/drm_fixed.h

47

static inline u32 dfixed_floor(fixed20_12 A)

sys/dev/pci/drm/include/drm/drm_fixed.h

49

u32 non_frac = dfixed_trunc(A);

sys/dev/pci/drm/include/drm/drm_fixed.h

54

static inline u32 dfixed_ceil(fixed20_12 A)

sys/dev/pci/drm/include/drm/drm_fixed.h

56

u32 non_frac = dfixed_trunc(A);

sys/dev/pci/drm/include/drm/drm_fixed.h

64

static inline u32 dfixed_div(fixed20_12 A, fixed20_12 B)

sys/dev/pci/drm/include/drm/drm_fourcc.h

307

const struct drm_format_info *__drm_format_info(u32 format);

sys/dev/pci/drm/include/drm/drm_fourcc.h

308

const struct drm_format_info *drm_format_info(u32 format);

sys/dev/pci/drm/include/drm/drm_fourcc.h

311

u32 pixel_format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_fourcc.h

63

u32 format;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

303

u32 block_width;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

307

u32 block_height;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

311

u32 aligned_width;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

315

u32 aligned_height;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

319

u32 offset;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

323

u32 afbc_size;

sys/dev/pci/drm/include/drm/drm_gem.h

569

u32 *handlep);

sys/dev/pci/drm/include/drm/drm_gem.h

570

int drm_gem_handle_delete(struct drm_file *filp, u32 handle);

sys/dev/pci/drm/include/drm/drm_gem.h

589

struct drm_gem_object *drm_gem_object_lookup(struct drm_file *filp, u32 handle);

sys/dev/pci/drm/include/drm/drm_gem.h

590

long drm_gem_dma_resv_wait(struct drm_file *filep, u32 handle,

sys/dev/pci/drm/include/drm/drm_gem.h

597

u32 handle, u64 *offset);

sys/dev/pci/drm/include/drm/drm_gpusvm.h

104

u32 removed : 1;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

535

u32 flags;

sys/dev/pci/drm/include/drm/drm_ioctl.h

165

long drm_ioctl_kernel(struct file *, drm_ioctl_t, void *, u32);

sys/dev/pci/drm/include/drm/drm_mode_config.h

99

const struct drm_format_info *(*get_format_info)(u32 pixel_format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_modes.h

303

u32 flags;

sys/dev/pci/drm/include/drm/drm_modes.h

507

void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags);

sys/dev/pci/drm/include/drm/drm_modes.h

511

struct drm_display_mode *dmode, u32 *bus_flags,

sys/dev/pci/drm/include/drm/drm_modes.h

514

struct drm_display_mode *dmode, u32 *bus_flags);

sys/dev/pci/drm/include/drm/drm_modes.h

518

u32 *bus_flags, int index)

sys/dev/pci/drm/include/drm/drm_modes.h

524

struct drm_display_mode *dmode, u32 *bus_flags)

sys/dev/pci/drm/include/drm/drm_panic.h

73

unsigned int y, u32 color);

sys/dev/pci/drm/include/drm/drm_plane.h

567

u32 format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_plane.h

927

static inline u32 drm_plane_mask(const struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_plane.h

993

u32 format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_plane.h

995

u32 format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_property.h

251

u32 flags, const char *name,

sys/dev/pci/drm/include/drm/drm_property.h

254

u32 flags, const char *name,

sys/dev/pci/drm/include/drm/drm_property.h

258

u32 flags, const char *name,

sys/dev/pci/drm/include/drm/drm_property.h

263

u32 flags, const char *name,

sys/dev/pci/drm/include/drm/drm_property.h

266

u32 flags, const char *name,

sys/dev/pci/drm/include/drm/drm_property.h

269

u32 flags, const char *name,

sys/dev/pci/drm/include/drm/drm_property.h

272

u32 flags, const char *name);

sys/dev/pci/drm/include/drm/drm_syncobj.h

119

u32 handle);

sys/dev/pci/drm/include/drm/drm_syncobj.h

127

u32 handle, u64 point, u64 flags,

sys/dev/pci/drm/include/drm/drm_syncobj.h

133

struct drm_syncobj *syncobj, u32 *handle);

sys/dev/pci/drm/include/drm/drm_utils.h

21

u32 brightness_mask;

sys/dev/pci/drm/include/drm/drm_vblank.h

194

u32 last;

sys/dev/pci/drm/include/drm/drm_vblank.h

214

u32 max_vblank_count;

sys/dev/pci/drm/include/drm/drm_vblank.h

323

u32 max_vblank_count);

sys/dev/pci/drm/include/drm/gpu_scheduler.h

365

u32 credits;

sys/dev/pci/drm/include/drm/gpu_scheduler.h

579

u32 credit_limit;

sys/dev/pci/drm/include/drm/gpu_scheduler.h

583

u32 num_rqs;

sys/dev/pci/drm/include/drm/gpu_scheduler.h

625

u32 num_rqs;

sys/dev/pci/drm/include/drm/gpu_scheduler.h

626

u32 credit_limit;

sys/dev/pci/drm/include/drm/gpu_scheduler.h

661

u32 credits, void *owner,

sys/dev/pci/drm/include/drm/gpu_scheduler.h

669

u32 handle,

sys/dev/pci/drm/include/drm/gpu_scheduler.h

670

u32 point);

sys/dev/pci/drm/include/drm/intel/i915_pxp_tee_interface.h

35

ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,

sys/dev/pci/drm/include/drm/intel/intel_lb_mei_interface.h

66

int (*push_payload)(struct device *dev, u32 type, u32 flags,

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

245

u32 purge : 1;

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

246

u32 writeback : 1;

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

247

u32 allow_move : 1;

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

467

void ttm_move_memcpy(bool clear, u32 num_pages,

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

297

u32 purge : 1;

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

298

u32 writeback : 1;

sys/dev/pci/drm/include/linux/bits.h

19

((u32)(BIT(__n) + \

sys/dev/pci/drm/include/linux/bits.h

46

((u32)(GENMASK(__high, __low) + \

sys/dev/pci/drm/include/linux/io.h

118

static inline u32

sys/dev/pci/drm/include/linux/io.h

148

iowrite32(u32 val, volatile void __iomem *addr)

sys/dev/pci/drm/include/linux/io.h

62

static inline u32

sys/dev/pci/drm/include/linux/io.h

92

iowrite32(u32 val, volatile void __iomem *addr)

sys/dev/pci/drm/include/linux/pci.h

143

pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)

sys/dev/pci/drm/include/linux/pci.h

170

pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)

sys/dev/pci/drm/include/linux/pci.h

281

pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val)

sys/dev/pci/drm/include/linux/wordpart.h

6

#define lower_32_bits(n) ((u32)(n))

sys/dev/pci/drm/include/linux/wordpart.h

7

#define upper_32_bits(_val) ((u32)(((_val) >> 16) >> 16))

sys/dev/pci/drm/include/linux/xarray.h

133

xa_alloc(struct xarray *xa, u32 *id, void *entry, struct xarray_range xr,

sys/dev/pci/drm/include/linux/xarray.h

205

xa_alloc_cyclic_irq(struct xarray *xa, u32 *id, void *entry,

sys/dev/pci/drm/include/linux/xarray.h

206

struct xarray_range xr, u32 *next, gfp_t gfp)

sys/dev/pci/drm/include/linux/xarray.h

53

int __xa_alloc(struct xarray *, u32 *, void *, struct xarray_range, gfp_t);

sys/dev/pci/drm/include/linux/xarray.h

54

int __xa_alloc_cyclic(struct xarray *, u32 *, void *, struct xarray_range,

sys/dev/pci/drm/include/linux/xarray.h

55

u32 *, gfp_t);

sys/dev/pci/drm/radeon/atom.c

230

val = get_unaligned_le32((u32 *)&ctx->ps[idx]);

sys/dev/pci/drm/radeon/atom.h

162

u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);

sys/dev/pci/drm/radeon/atombios_crtc.c

1060

u32 pll_clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1061

u32 clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1062

u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

1113

u32 step_size;

sys/dev/pci/drm/radeon/atombios_crtc.c

1114

u32 amount = (((fb_div * 10) + frac_fb_div) *

sys/dev/pci/drm/radeon/atombios_crtc.c

1115

(u32)radeon_crtc->ss.percentage) /

sys/dev/pci/drm/radeon/atombios_crtc.c

1116

(100 * (u32)radeon_crtc->ss.percentage_divider);

sys/dev/pci/drm/radeon/atombios_crtc.c

1121

step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/radeon/atombios_crtc.c

1124

step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/radeon/atombios_crtc.c

1147

u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);

sys/dev/pci/drm/radeon/atombios_crtc.c

1148

u32 tmp, viewport_w, viewport_h;

sys/dev/pci/drm/radeon/atombios_crtc.c

1346

u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;

sys/dev/pci/drm/radeon/atombios_crtc.c

1390

(u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/radeon/atombios_crtc.c

1392

(u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);

sys/dev/pci/drm/radeon/atombios_crtc.c

1467

u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;

sys/dev/pci/drm/radeon/atombios_crtc.c

1468

u32 viewport_w, viewport_h;

sys/dev/pci/drm/radeon/atombios_crtc.c

1609

(u32) fb_location);

sys/dev/pci/drm/radeon/atombios_crtc.c

1611

radeon_crtc->crtc_offset, (u32) fb_location);

sys/dev/pci/drm/radeon/atombios_crtc.c

1698

u32 disp_merge_cntl;

sys/dev/pci/drm/radeon/atombios_crtc.c

1723

static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)

sys/dev/pci/drm/radeon/atombios_crtc.c

1728

u32 pll_in_use = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

1790

u32 adjusted_clock, test_adjusted_clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1869

u32 pll_in_use;

sys/dev/pci/drm/radeon/atombios_crtc.c

216

static const u32 vga_control_regs[6] =

sys/dev/pci/drm/radeon/atombios_crtc.c

233

u32 vga_control = 0;

sys/dev/pci/drm/radeon/atombios_crtc.c

397

u32 ss_cntl;

sys/dev/pci/drm/radeon/atombios_crtc.c

557

static u32 atombios_adjust_pll(struct drm_crtc *crtc,

sys/dev/pci/drm/radeon/atombios_crtc.c

566

u32 adjusted_clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

568

u32 dp_clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

569

u32 clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

767

u32 dispclk)

sys/dev/pci/drm/radeon/atombios_crtc.c

816

u32 crtc_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

818

u32 encoder_mode,

sys/dev/pci/drm/radeon/atombios_crtc.c

819

u32 encoder_id,

sys/dev/pci/drm/radeon/atombios_crtc.c

820

u32 clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

821

u32 ref_div,

sys/dev/pci/drm/radeon/atombios_crtc.c

822

u32 fb_div,

sys/dev/pci/drm/radeon/atombios_crtc.c

823

u32 frac_fb_div,

sys/dev/pci/drm/radeon/atombios_crtc.c

824

u32 post_div,

sys/dev/pci/drm/radeon/atombios_dp.c

60

u32 src_tmp[5], dst_tmp[5];

sys/dev/pci/drm/radeon/atombios_encoders.c

1438

u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;

sys/dev/pci/drm/radeon/atombios_encoders.c

1619

u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);

sys/dev/pci/drm/radeon/atombios_encoders.c

2369

u32 bios_0_scratch;

sys/dev/pci/drm/radeon/atombios_encoders.c

51

u32 bios_2_scratch;

sys/dev/pci/drm/radeon/atombios_encoders.c

68

u32 bios_2_scratch;

sys/dev/pci/drm/radeon/atombios_i2c.c

150

u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/radeon/btc_dpm.c

1013

#define BARTS_SYSLS_ENABLE_LENGTH sizeof(barts_sysls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

1016

static const u32 caicos_sysls_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1032

#define CAICOS_SYSLS_DEFAULT_LENGTH sizeof(caicos_sysls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

1034

static const u32 caicos_sysls_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1050

#define CAICOS_SYSLS_DISABLE_LENGTH sizeof(caicos_sysls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

1052

static const u32 caicos_sysls_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1068

#define CAICOS_SYSLS_ENABLE_LENGTH sizeof(caicos_sysls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

107

#define BARTS_CGCG_CGLS_DEFAULT_LENGTH sizeof(barts_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

1071

static const u32 turks_sysls_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1088

#define TURKS_SYSLS_DEFAULT_LENGTH sizeof(turks_sysls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

109

static const u32 barts_cgcg_cgls_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1090

static const u32 turks_sysls_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1107

#define TURKS_SYSLS_DISABLE_LENGTH sizeof(turks_sysls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

1109

static const u32 turks_sysls_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1126

#define TURKS_SYSLS_ENABLE_LENGTH sizeof(turks_sysls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

1130

u32 btc_valid_sclk[40] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1145

u32 *max_clock)

sys/dev/pci/drm/radeon/btc_dpm.c

1147

u32 i, clock = 0;

sys/dev/pci/drm/radeon/btc_dpm.c

1162

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/pci/drm/radeon/btc_dpm.c

1164

u32 i;

sys/dev/pci/drm/radeon/btc_dpm.c

1181

static u32 btc_find_valid_clock(struct radeon_clock_array *clocks,

sys/dev/pci/drm/radeon/btc_dpm.c

1182

u32 max_clock, u32 requested_clock)

sys/dev/pci/drm/radeon/btc_dpm.c

1198

static u32 btc_get_valid_mclk(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/btc_dpm.c

1199

u32 max_mclk, u32 requested_mclk)

sys/dev/pci/drm/radeon/btc_dpm.c

1205

static u32 btc_get_valid_sclk(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/btc_dpm.c

1206

u32 max_sclk, u32 requested_sclk)

sys/dev/pci/drm/radeon/btc_dpm.c

1213

const u32 max_sclk, const u32 max_mclk,

sys/dev/pci/drm/radeon/btc_dpm.c

1214

u32 *sclk, u32 *mclk)

sys/dev/pci/drm/radeon/btc_dpm.c

1307

u32 tmp, bif;

sys/dev/pci/drm/radeon/btc_dpm.c

1411

const u32 *sequence, u32 count)

sys/dev/pci/drm/radeon/btc_dpm.c

1413

u32 i, length = count * 3;

sys/dev/pci/drm/radeon/btc_dpm.c

1414

u32 tmp;

sys/dev/pci/drm/radeon/btc_dpm.c

1426

u32 count;

sys/dev/pci/drm/radeon/btc_dpm.c

1427

const u32 *p = NULL;

sys/dev/pci/drm/radeon/btc_dpm.c

1430

p = (const u32 *)&barts_cgcg_cgls_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1433

p = (const u32 *)&turks_cgcg_cgls_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1436

p = (const u32 *)&caicos_cgcg_cgls_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1447

u32 count;

sys/dev/pci/drm/radeon/btc_dpm.c

1448

const u32 *p = NULL;

sys/dev/pci/drm/radeon/btc_dpm.c

1452

p = (const u32 *)&barts_cgcg_cgls_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1455

p = (const u32 *)&turks_cgcg_cgls_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1458

p = (const u32 *)&caicos_cgcg_cgls_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1464

p = (const u32 *)&barts_cgcg_cgls_disable;

sys/dev/pci/drm/radeon/btc_dpm.c

1467

p = (const u32 *)&turks_cgcg_cgls_disable;

sys/dev/pci/drm/radeon/btc_dpm.c

1470

p = (const u32 *)&caicos_cgcg_cgls_disable;

sys/dev/pci/drm/radeon/btc_dpm.c

1481

u32 count;

sys/dev/pci/drm/radeon/btc_dpm.c

1482

const u32 *p = NULL;

sys/dev/pci/drm/radeon/btc_dpm.c

1485

p = (const u32 *)&barts_mgcg_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1488

p = (const u32 *)&turks_mgcg_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1491

p = (const u32 *)&caicos_mgcg_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1502

u32 count;

sys/dev/pci/drm/radeon/btc_dpm.c

1503

const u32 *p = NULL;

sys/dev/pci/drm/radeon/btc_dpm.c

1507

p = (const u32 *)&barts_mgcg_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1510

p = (const u32 *)&turks_mgcg_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1513

p = (const u32 *)&caicos_mgcg_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1519

p = (const u32 *)&barts_mgcg_disable[0];

sys/dev/pci/drm/radeon/btc_dpm.c

1522

p = (const u32 *)&turks_mgcg_disable[0];

sys/dev/pci/drm/radeon/btc_dpm.c

1525

p = (const u32 *)&caicos_mgcg_disable[0];

sys/dev/pci/drm/radeon/btc_dpm.c

1536

u32 count;

sys/dev/pci/drm/radeon/btc_dpm.c

1537

const u32 *p = NULL;

sys/dev/pci/drm/radeon/btc_dpm.c

1540

p = (const u32 *)&barts_sysls_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1543

p = (const u32 *)&turks_sysls_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1546

p = (const u32 *)&caicos_sysls_default;

sys/dev/pci/drm/radeon/btc_dpm.c

1557

u32 count;

sys/dev/pci/drm/radeon/btc_dpm.c

1558

const u32 *p = NULL;

sys/dev/pci/drm/radeon/btc_dpm.c

1562

p = (const u32 *)&barts_sysls_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1565

p = (const u32 *)&turks_sysls_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1568

p = (const u32 *)&caicos_sysls_enable;

sys/dev/pci/drm/radeon/btc_dpm.c

1574

p = (const u32 *)&barts_sysls_disable;

sys/dev/pci/drm/radeon/btc_dpm.c

1577

p = (const u32 *)&turks_sysls_disable;

sys/dev/pci/drm/radeon/btc_dpm.c

1580

p = (const u32 *)&caicos_sysls_disable;

sys/dev/pci/drm/radeon/btc_dpm.c

161

#define BARTS_CGCG_CGLS_DISABLE_LENGTH sizeof(barts_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

163

static const u32 barts_cgcg_cgls_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

1739

u32 val;

sys/dev/pci/drm/radeon/btc_dpm.c

1782

u32 val;

sys/dev/pci/drm/radeon/btc_dpm.c

1891

u32 tmp;

sys/dev/pci/drm/radeon/btc_dpm.c

1950

u32 i;

sys/dev/pci/drm/radeon/btc_dpm.c

2039

u32 tmp;

sys/dev/pci/drm/radeon/btc_dpm.c

2055

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/pci/drm/radeon/btc_dpm.c

2056

u32 switch_limit = pi->mem_gddr5 ? 450 : 100;

sys/dev/pci/drm/radeon/btc_dpm.c

2071

u32 mclk, sclk;

sys/dev/pci/drm/radeon/btc_dpm.c

215

#define BARTS_CGCG_CGLS_ENABLE_LENGTH sizeof(barts_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

217

static const u32 barts_mgcg_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

2712

u32 current_index =

sys/dev/pci/drm/radeon/btc_dpm.c

2731

u32 btc_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/btc_dpm.c

2737

u32 current_index =

sys/dev/pci/drm/radeon/btc_dpm.c

2754

u32 btc_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/btc_dpm.c

2760

u32 current_index =

sys/dev/pci/drm/radeon/btc_dpm.c

2777

u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/btc_dpm.c

2788

u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/btc_dpm.c

363

#define BARTS_MGCG_DEFAULT_LENGTH sizeof(barts_mgcg_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

365

static const u32 barts_mgcg_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

377

#define BARTS_MGCG_DISABLE_LENGTH sizeof(barts_mgcg_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

379

static const u32 barts_mgcg_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

391

#define BARTS_MGCG_ENABLE_LENGTH sizeof(barts_mgcg_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

394

static const u32 caicos_cgcg_cgls_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

444

#define CAICOS_CGCG_CGLS_DEFAULT_LENGTH sizeof(caicos_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

446

static const u32 caicos_cgcg_cgls_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

498

#define CAICOS_CGCG_CGLS_DISABLE_LENGTH sizeof(caicos_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

500

static const u32 caicos_cgcg_cgls_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

552

#define CAICOS_CGCG_CGLS_ENABLE_LENGTH sizeof(caicos_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

554

static const u32 caicos_mgcg_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

56

static const u32 barts_cgcg_cgls_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

631

#define CAICOS_MGCG_DEFAULT_LENGTH sizeof(caicos_mgcg_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

633

static const u32 caicos_mgcg_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

645

#define CAICOS_MGCG_DISABLE_LENGTH sizeof(caicos_mgcg_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

647

static const u32 caicos_mgcg_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

659

#define CAICOS_MGCG_ENABLE_LENGTH sizeof(caicos_mgcg_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

662

static const u32 turks_cgcg_cgls_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

712

#define TURKS_CGCG_CGLS_DEFAULT_LENGTH sizeof(turks_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

714

static const u32 turks_cgcg_cgls_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

766

#define TURKS_CGCG_CGLS_DISABLE_LENGTH sizeof(turks_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

768

static const u32 turks_cgcg_cgls_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

820

#define TURKS_CGCG_CGLS_ENABLE_LENGTH sizeof(turks_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

823

static const u32 turks_mgcg_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

920

#define TURKS_MGCG_DEFAULT_LENGTH sizeof(turks_mgcg_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

922

static const u32 turks_mgcg_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

934

#define TURKS_MGCG_DISABLE_LENGTH sizeof(turks_mgcg_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

936

static const u32 turks_mgcg_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

948

#define TURKS_MGCG_ENABLE_LENGTH sizeof(turks_mgcg_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

957

static const u32 barts_sysls_default[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

975

#define BARTS_SYSLS_DEFAULT_LENGTH sizeof(barts_sysls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

977

static const u32 barts_sysls_disable[] = {

sys/dev/pci/drm/radeon/btc_dpm.c

994

#define BARTS_SYSLS_DISABLE_LENGTH sizeof(barts_sysls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/btc_dpm.c

996

static const u32 barts_sysls_enable[] = {

sys/dev/pci/drm/radeon/btc_dpm.h

39

extern u32 btc_valid_sclk[40];

sys/dev/pci/drm/radeon/btc_dpm.h

43

const u32 *sequence, u32 count);

sys/dev/pci/drm/radeon/btc_dpm.h

45

const u32 max_sclk, const u32 max_mclk,

sys/dev/pci/drm/radeon/btc_dpm.h

46

u32 *sclk, u32 *mclk);

sys/dev/pci/drm/radeon/btc_dpm.h

51

u32 clock, u16 max_voltage, u16 *voltage);

sys/dev/pci/drm/radeon/btc_dpm.h

53

u32 *max_clock);

sys/dev/pci/drm/radeon/cayman_blit_shaders.h

317

static const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);

sys/dev/pci/drm/radeon/cayman_blit_shaders.h

39

static const u32 cayman_default_state[] = {

sys/dev/pci/drm/radeon/ci_dpm.c

1046

u32 *speed)

sys/dev/pci/drm/radeon/ci_dpm.c

1048

u32 duty, duty100;

sys/dev/pci/drm/radeon/ci_dpm.c

1062

*speed = (u32)tmp64;

sys/dev/pci/drm/radeon/ci_dpm.c

1071

u32 speed)

sys/dev/pci/drm/radeon/ci_dpm.c

1073

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1074

u32 duty, duty100;

sys/dev/pci/drm/radeon/ci_dpm.c

1094

duty = (u32)tmp64;

sys/dev/pci/drm/radeon/ci_dpm.c

1103

void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)

sys/dev/pci/drm/radeon/ci_dpm.c

1119

u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ci_dpm.c

1122

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1133

u32 *speed)

sys/dev/pci/drm/radeon/ci_dpm.c

1135

u32 tach_period;

sys/dev/pci/drm/radeon/ci_dpm.c

1136

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

1154

u32 speed)

sys/dev/pci/drm/radeon/ci_dpm.c

1156

u32 tach_period, tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1157

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

1186

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1210

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1252

u16 reg_offset, u32 *value)

sys/dev/pci/drm/radeon/ci_dpm.c

1263

u16 reg_offset, u32 value)

sys/dev/pci/drm/radeon/ci_dpm.c

1292

u32 low_sclk_interrupt_t = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

1301

sizeof(u32), pi->sram_end);

sys/dev/pci/drm/radeon/ci_dpm.c

1350

static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/pci/drm/radeon/ci_dpm.c

1354

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1489

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

151

u32 arb_freq_src, u32 arb_freq_dest);

sys/dev/pci/drm/radeon/ci_dpm.c

155

static int ci_set_power_limit(struct radeon_device *rdev, u32 n);

sys/dev/pci/drm/radeon/ci_dpm.c

1550

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

157

u32 target_tdp);

sys/dev/pci/drm/radeon/ci_dpm.c

1579

u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/pci/drm/radeon/ci_dpm.c

1595

u32 power_limit;

sys/dev/pci/drm/radeon/ci_dpm.c

1598

power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);

sys/dev/pci/drm/radeon/ci_dpm.c

1600

power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);

sys/dev/pci/drm/radeon/ci_dpm.c

1617

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

162

PPSMC_Msg msg, u32 parameter);

sys/dev/pci/drm/radeon/ci_dpm.c

1637

PPSMC_Msg msg, u32 parameter)

sys/dev/pci/drm/radeon/ci_dpm.c

1644

PPSMC_Msg msg, u32 *parameter)

sys/dev/pci/drm/radeon/ci_dpm.c

1656

static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)

sys/dev/pci/drm/radeon/ci_dpm.c

1670

static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)

sys/dev/pci/drm/radeon/ci_dpm.c

1684

static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)

sys/dev/pci/drm/radeon/ci_dpm.c

1698

static int ci_set_power_limit(struct radeon_device *rdev, u32 n)

sys/dev/pci/drm/radeon/ci_dpm.c

1713

u32 target_tdp)

sys/dev/pci/drm/radeon/ci_dpm.c

1729

static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ci_dpm.c

1731

u32 sclk_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

1742

static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ci_dpm.c

1744

u32 mclk_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

1777

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

1865

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/pci/drm/radeon/ci_dpm.c

1876

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/pci/drm/radeon/ci_dpm.c

1945

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/ci_dpm.c

1946

u32 pre_vbi_time_in_us;

sys/dev/pci/drm/radeon/ci_dpm.c

1947

u32 frame_time_in_us;

sys/dev/pci/drm/radeon/ci_dpm.c

1948

u32 ref_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

1949

u32 refresh_rate = r600_dpm_get_vrefresh(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

1950

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

1980

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2006

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/ci_dpm.c

2017

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2035

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2073

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

2263

static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/pci/drm/radeon/ci_dpm.c

2267

u32 i = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

2297

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/pci/drm/radeon/ci_dpm.c

2301

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/radeon/ci_dpm.c

2314

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/pci/drm/radeon/ci_dpm.c

2318

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/radeon/ci_dpm.c

2337

u32 sclk,

sys/dev/pci/drm/radeon/ci_dpm.c

2338

u32 *phase_shedding)

sys/dev/pci/drm/radeon/ci_dpm.c

2354

u32 mclk,

sys/dev/pci/drm/radeon/ci_dpm.c

2355

u32 *phase_shedding)

sys/dev/pci/drm/radeon/ci_dpm.c

2372

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2389

u32 clock, u32 *voltage)

sys/dev/pci/drm/radeon/ci_dpm.c

2391

u32 i = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

2409

u32 sclk, u32 min_sclk_in_sr)

sys/dev/pci/drm/radeon/ci_dpm.c

2411

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

2412

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2413

u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?

sys/dev/pci/drm/radeon/ci_dpm.c

2441

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2452

const u32 engine_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

2453

const u32 memory_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

2454

u32 *dram_timimg2)

sys/dev/pci/drm/radeon/ci_dpm.c

2457

u32 tmp, tmp2;

sys/dev/pci/drm/radeon/ci_dpm.c

2480

u32 sclk,

sys/dev/pci/drm/radeon/ci_dpm.c

2481

u32 mclk,

sys/dev/pci/drm/radeon/ci_dpm.c

2484

u32 dram_timing;

sys/dev/pci/drm/radeon/ci_dpm.c

2485

u32 dram_timing2;

sys/dev/pci/drm/radeon/ci_dpm.c

2486

u32 burst_time;

sys/dev/pci/drm/radeon/ci_dpm.c

2507

u32 i, j;

sys/dev/pci/drm/radeon/ci_dpm.c

252

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

2548

u32 level = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

2567

static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)

sys/dev/pci/drm/radeon/ci_dpm.c

2569

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

2570

u32 mask_value = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

2588

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

2608

u32 count;

sys/dev/pci/drm/radeon/ci_dpm.c

2651

u32 count;

sys/dev/pci/drm/radeon/ci_dpm.c

2684

u32 count;

sys/dev/pci/drm/radeon/ci_dpm.c

2716

u32 count;

sys/dev/pci/drm/radeon/ci_dpm.c

2746

u32 memory_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

2752

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2753

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2754

u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2755

u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2756

u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2757

u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;

sys/dev/pci/drm/radeon/ci_dpm.c

2758

u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;

sys/dev/pci/drm/radeon/ci_dpm.c

2759

u32 mpll_ss1 = pi->clock_registers.mpll_ss1;

sys/dev/pci/drm/radeon/ci_dpm.c

2760

u32 mpll_ss2 = pi->clock_registers.mpll_ss2;

sys/dev/pci/drm/radeon/ci_dpm.c

2786

u32 freq_nom;

sys/dev/pci/drm/radeon/ci_dpm.c

2787

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

2788

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

279

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

2799

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/pci/drm/radeon/ci_dpm.c

2800

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/pci/drm/radeon/ci_dpm.c

2833

u32 memory_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

2952

u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2953

u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/ci_dpm.c

2954

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

2955

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/ci_dpm.c

3117

u32 engine_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

3122

u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/ci_dpm.c

3123

u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/ci_dpm.c

3124

u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/ci_dpm.c

3125

u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/ci_dpm.c

3126

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

3127

u32 reference_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

3128

u32 fbdiv;

sys/dev/pci/drm/radeon/ci_dpm.c

3146

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/pci/drm/radeon/ci_dpm.c

3150

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/ci_dpm.c

3151

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/radeon/ci_dpm.c

3173

u32 engine_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

3237

u32 level_array_address = pi->dpm_table_start +

sys/dev/pci/drm/radeon/ci_dpm.c

3239

u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *

sys/dev/pci/drm/radeon/ci_dpm.c

3243

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

328

(u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,

sys/dev/pci/drm/radeon/ci_dpm.c

3285

u32 level_array_address = pi->dpm_table_start +

sys/dev/pci/drm/radeon/ci_dpm.c

3287

u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *

sys/dev/pci/drm/radeon/ci_dpm.c

3291

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3336

u32 count)

sys/dev/pci/drm/radeon/ci_dpm.c

3338

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3346

u32 index, u32 pcie_gen, u32 pcie_lanes)

sys/dev/pci/drm/radeon/ci_dpm.c

3410

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3492

u32 value, u32 *boot_level)

sys/dev/pci/drm/radeon/ci_dpm.c

3494

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3583

(u32 *)&pi->smc_state_table.GraphicsBootLevel);

sys/dev/pci/drm/radeon/ci_dpm.c

3587

(u32 *)&pi->smc_state_table.MemoryBootLevel);

sys/dev/pci/drm/radeon/ci_dpm.c

3657

u32 low_limit, u32 high_limit)

sys/dev/pci/drm/radeon/ci_dpm.c

3659

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3671

u32 speed_low, u32 lanes_low,

sys/dev/pci/drm/radeon/ci_dpm.c

3672

u32 speed_high, u32 lanes_high)

sys/dev/pci/drm/radeon/ci_dpm.c

3676

u32 i, j;

sys/dev/pci/drm/radeon/ci_dpm.c

3706

u32 high_limit_count;

sys/dev/pci/drm/radeon/ci_dpm.c

3741

u32 requested_voltage = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

3742

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3813

u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;

sys/dev/pci/drm/radeon/ci_dpm.c

3815

u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;

sys/dev/pci/drm/radeon/ci_dpm.c

3816

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

3854

u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;

sys/dev/pci/drm/radeon/ci_dpm.c

3855

u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;

sys/dev/pci/drm/radeon/ci_dpm.c

4032

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

4054

u32 min_evclk = 30000; /* ??? */

sys/dev/pci/drm/radeon/ci_dpm.c

4072

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

4105

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

4146

static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/ci_dpm.c

4147

u32 level_mask)

sys/dev/pci/drm/radeon/ci_dpm.c

4149

u32 level = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

4162

u32 tmp, levels, i;

sys/dev/pci/drm/radeon/ci_dpm.c

4293

u32 temp_reg;

sys/dev/pci/drm/radeon/ci_dpm.c

4449

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

4490

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

452

u32 pm_fuse_table_offset;

sys/dev/pci/drm/radeon/ci_dpm.c

4640

u32 i, j;

sys/dev/pci/drm/radeon/ci_dpm.c

4659

u32 num_entries, u32 valid_flag)

sys/dev/pci/drm/radeon/ci_dpm.c

4661

u32 i, j;

sys/dev/pci/drm/radeon/ci_dpm.c

4672

const u32 memory_clock,

sys/dev/pci/drm/radeon/ci_dpm.c

4676

u32 i = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

4695

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

4744

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/pci/drm/radeon/ci_dpm.c

4768

u32 speed_cntl = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

4778

u32 link_width = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

4911

u32 leakage_index;

sys/dev/pci/drm/radeon/ci_dpm.c

4925

u32 leakage_index;

sys/dev/pci/drm/radeon/ci_dpm.c

4938

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

4949

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

4960

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

4971

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

4982

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

499

u32 data;

sys/dev/pci/drm/radeon/ci_dpm.c

5002

u32 i;

sys/dev/pci/drm/radeon/ci_dpm.c

5043

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

542

u32 data;

sys/dev/pci/drm/radeon/ci_dpm.c

543

u32 cache = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

5571

u32 sclk, mclk;

sys/dev/pci/drm/radeon/ci_dpm.c

5807

u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);

sys/dev/pci/drm/radeon/ci_dpm.c

5905

u32 sclk = ci_get_average_sclk_freq(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

5906

u32 mclk = ci_get_average_mclk_freq(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

5932

u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ci_dpm.c

5934

u32 sclk = ci_get_average_sclk_freq(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

5939

u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ci_dpm.c

5941

u32 mclk = ci_get_average_mclk_freq(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

5946

u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/ci_dpm.c

5957

u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/ci_dpm.c

643

u32 default_pwr_limit =

sys/dev/pci/drm/radeon/ci_dpm.c

644

(u32)(cac_tdp_table->maximum_power_delivery_limit * 256);

sys/dev/pci/drm/radeon/ci_dpm.c

728

ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);

sys/dev/pci/drm/radeon/ci_dpm.c

749

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

750

u32 switch_limit = pi->mem_gddr5 ? 450 : 300;

sys/dev/pci/drm/radeon/ci_dpm.c

772

u32 sclk, mclk;

sys/dev/pci/drm/radeon/ci_dpm.c

845

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

879

u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/pci/drm/radeon/ci_dpm.c

905

static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)

sys/dev/pci/drm/radeon/ci_dpm.c

908

u32 tmp;

sys/dev/pci/drm/radeon/ci_dpm.c

931

u32 duty100;

sys/dev/pci/drm/radeon/ci_dpm.c

932

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/radeon/ci_dpm.c

934

u32 reference_clock, tmp;

sys/dev/pci/drm/radeon/ci_dpm.h

106

u32 uvd_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

107

u32 vce_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

108

u32 acp_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

109

u32 samu_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

110

u32 sclk_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

111

u32 mclk_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

112

u32 pcie_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

119

u32 sclk_bootup_value;

sys/dev/pci/drm/radeon/ci_dpm.h

120

u32 mclk_bootup_value;

sys/dev/pci/drm/radeon/ci_dpm.h

126

u32 cg_spll_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.h

127

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/ci_dpm.h

128

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/ci_dpm.h

129

u32 cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/ci_dpm.h

130

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/ci_dpm.h

131

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/ci_dpm.h

132

u32 dll_cntl;

sys/dev/pci/drm/radeon/ci_dpm.h

133

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/ci_dpm.h

134

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.h

135

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.h

136

u32 mpll_func_cntl;

sys/dev/pci/drm/radeon/ci_dpm.h

137

u32 mpll_func_cntl_1;

sys/dev/pci/drm/radeon/ci_dpm.h

138

u32 mpll_func_cntl_2;

sys/dev/pci/drm/radeon/ci_dpm.h

139

u32 mpll_ss1;

sys/dev/pci/drm/radeon/ci_dpm.h

140

u32 mpll_ss2;

sys/dev/pci/drm/radeon/ci_dpm.h

167

u32 offset;

sys/dev/pci/drm/radeon/ci_dpm.h

168

u32 mask;

sys/dev/pci/drm/radeon/ci_dpm.h

169

u32 shift;

sys/dev/pci/drm/radeon/ci_dpm.h

170

u32 value;

sys/dev/pci/drm/radeon/ci_dpm.h

181

u32 display_cac;

sys/dev/pci/drm/radeon/ci_dpm.h

182

u32 bapm_temp_gradient;

sys/dev/pci/drm/radeon/ci_dpm.h

194

u32 voltage_control;

sys/dev/pci/drm/radeon/ci_dpm.h

195

u32 mvdd_control;

sys/dev/pci/drm/radeon/ci_dpm.h

196

u32 vddci_control;

sys/dev/pci/drm/radeon/ci_dpm.h

197

u32 active_auto_throttle_sources;

sys/dev/pci/drm/radeon/ci_dpm.h

209

u32 mclk_strobe_mode_threshold;

sys/dev/pci/drm/radeon/ci_dpm.h

210

u32 mclk_stutter_mode_threshold;

sys/dev/pci/drm/radeon/ci_dpm.h

211

u32 mclk_edc_enable_threshold;

sys/dev/pci/drm/radeon/ci_dpm.h

212

u32 mclk_edc_wr_enable_threshold;

sys/dev/pci/drm/radeon/ci_dpm.h

215

u32 sram_end;

sys/dev/pci/drm/radeon/ci_dpm.h

216

u32 dpm_table_start;

sys/dev/pci/drm/radeon/ci_dpm.h

217

u32 soft_regs_start;

sys/dev/pci/drm/radeon/ci_dpm.h

218

u32 mc_reg_table_start;

sys/dev/pci/drm/radeon/ci_dpm.h

219

u32 fan_table_start;

sys/dev/pci/drm/radeon/ci_dpm.h

220

u32 arb_table_start;

sys/dev/pci/drm/radeon/ci_dpm.h

231

u32 power_containment_features;

sys/dev/pci/drm/radeon/ci_dpm.h

233

u32 dte_tj_offset;

sys/dev/pci/drm/radeon/ci_dpm.h

237

u32 need_update_smu7_dpm_table;

sys/dev/pci/drm/radeon/ci_dpm.h

238

u32 sclk_dpm_key_disabled;

sys/dev/pci/drm/radeon/ci_dpm.h

239

u32 mclk_dpm_key_disabled;

sys/dev/pci/drm/radeon/ci_dpm.h

240

u32 pcie_dpm_key_disabled;

sys/dev/pci/drm/radeon/ci_dpm.h

241

u32 thermal_sclk_dpm_enabled;

sys/dev/pci/drm/radeon/ci_dpm.h

246

u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];

sys/dev/pci/drm/radeon/ci_dpm.h

247

u32 mclk_activity_target;

sys/dev/pci/drm/radeon/ci_dpm.h

248

u32 low_sclk_interrupt_t;

sys/dev/pci/drm/radeon/ci_dpm.h

249

u32 last_mclk_dpm_enable_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

250

u32 sys_pcie_mask;

sys/dev/pci/drm/radeon/ci_dpm.h

294

u32 t_min;

sys/dev/pci/drm/radeon/ci_dpm.h

295

u32 fan_ctrl_default_mode;

sys/dev/pci/drm/radeon/ci_dpm.h

324

u32 smc_start_address,

sys/dev/pci/drm/radeon/ci_dpm.h

325

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/radeon/ci_dpm.h

333

int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);

sys/dev/pci/drm/radeon/ci_dpm.h

335

u32 smc_address, u32 *value, u32 limit);

sys/dev/pci/drm/radeon/ci_dpm.h

337

u32 smc_address, u32 value, u32 limit);

sys/dev/pci/drm/radeon/ci_dpm.h

40

u32 mclk;

sys/dev/pci/drm/radeon/ci_dpm.h

41

u32 sclk;

sys/dev/pci/drm/radeon/ci_dpm.h

49

u32 sclk_t;

sys/dev/pci/drm/radeon/ci_dpm.h

55

u32 value;

sys/dev/pci/drm/radeon/ci_dpm.h

56

u32 param1;

sys/dev/pci/drm/radeon/ci_dpm.h

64

u32 count;

sys/dev/pci/drm/radeon/ci_dpm.h

78

u32 mclk_max;

sys/dev/pci/drm/radeon/ci_dpm.h

79

u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/ci_dpm.h

92

u32 cg_ulv_parameter;

sys/dev/pci/drm/radeon/ci_dpm.h

93

u32 volt_change_delay;

sys/dev/pci/drm/radeon/ci_smc.c

116

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/pci/drm/radeon/ci_smc.c

124

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/pci/drm/radeon/ci_smc.c

139

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/ci_smc.c

148

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/ci_smc.c

158

u32 pc_c = RREG32_SMC(SMC_PC_C);

sys/dev/pci/drm/radeon/ci_smc.c

169

u32 tmp;

sys/dev/pci/drm/radeon/ci_smc.c

186

int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)

sys/dev/pci/drm/radeon/ci_smc.c

189

u32 ucode_start_address;

sys/dev/pci/drm/radeon/ci_smc.c

190

u32 ucode_size;

sys/dev/pci/drm/radeon/ci_smc.c

192

u32 data;

sys/dev/pci/drm/radeon/ci_smc.c

247

u32 smc_address, u32 *value, u32 limit)

sys/dev/pci/drm/radeon/ci_smc.c

262

u32 smc_address, u32 value, u32 limit)

sys/dev/pci/drm/radeon/ci_smc.c

34

u32 smc_address, u32 limit)

sys/dev/pci/drm/radeon/ci_smc.c

48

u32 smc_start_address,

sys/dev/pci/drm/radeon/ci_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/radeon/ci_smc.c

52

u32 data, original_data;

sys/dev/pci/drm/radeon/ci_smc.c

53

u32 addr;

sys/dev/pci/drm/radeon/ci_smc.c

54

u32 extra_shift;

sys/dev/pci/drm/radeon/cik.c

1034

static const u32 bonaire_golden_spm_registers[] =

sys/dev/pci/drm/radeon/cik.c

1039

static const u32 bonaire_golden_common_registers[] =

sys/dev/pci/drm/radeon/cik.c

1047

static const u32 bonaire_golden_registers[] =

sys/dev/pci/drm/radeon/cik.c

1092

static const u32 bonaire_mgcg_cgcg_init[] =

sys/dev/pci/drm/radeon/cik.c

1178

static const u32 spectre_golden_spm_registers[] =

sys/dev/pci/drm/radeon/cik.c

1183

static const u32 spectre_golden_common_registers[] =

sys/dev/pci/drm/radeon/cik.c

1191

static const u32 spectre_golden_registers[] =

sys/dev/pci/drm/radeon/cik.c

1220

static const u32 spectre_mgcg_cgcg_init[] =

sys/dev/pci/drm/radeon/cik.c

1311

static const u32 kalindi_golden_spm_registers[] =

sys/dev/pci/drm/radeon/cik.c

1316

static const u32 kalindi_golden_common_registers[] =

sys/dev/pci/drm/radeon/cik.c

132

static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);

sys/dev/pci/drm/radeon/cik.c

1324

static const u32 kalindi_golden_registers[] =

sys/dev/pci/drm/radeon/cik.c

1358

static const u32 kalindi_mgcg_cgcg_init[] =

sys/dev/pci/drm/radeon/cik.c

1417

static const u32 hawaii_golden_spm_registers[] =

sys/dev/pci/drm/radeon/cik.c

1422

static const u32 hawaii_golden_common_registers[] =

sys/dev/pci/drm/radeon/cik.c

1431

static const u32 hawaii_golden_registers[] =

sys/dev/pci/drm/radeon/cik.c

1471

static const u32 hawaii_mgcg_cgcg_init[] =

sys/dev/pci/drm/radeon/cik.c

154

u32 reg, u32 *val)

sys/dev/pci/drm/radeon/cik.c

1582

static const u32 godavari_golden_registers[] =

sys/dev/pci/drm/radeon/cik.c

1625

(const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/cik.c

1628

(const u32)ARRAY_SIZE(bonaire_golden_registers));

sys/dev/pci/drm/radeon/cik.c

1631

(const u32)ARRAY_SIZE(bonaire_golden_common_registers));

sys/dev/pci/drm/radeon/cik.c

1634

(const u32)ARRAY_SIZE(bonaire_golden_spm_registers));

sys/dev/pci/drm/radeon/cik.c

1639

(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/cik.c

1642

(const u32)ARRAY_SIZE(kalindi_golden_registers));

sys/dev/pci/drm/radeon/cik.c

1645

(const u32)ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/pci/drm/radeon/cik.c

1648

(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/pci/drm/radeon/cik.c

1653

(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/cik.c

1656

(const u32)ARRAY_SIZE(godavari_golden_registers));

sys/dev/pci/drm/radeon/cik.c

1659

(const u32)ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/pci/drm/radeon/cik.c

1662

(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/pci/drm/radeon/cik.c

1667

(const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/cik.c

1670

(const u32)ARRAY_SIZE(spectre_golden_registers));

sys/dev/pci/drm/radeon/cik.c

1673

(const u32)ARRAY_SIZE(spectre_golden_common_registers));

sys/dev/pci/drm/radeon/cik.c

1676

(const u32)ARRAY_SIZE(spectre_golden_spm_registers));

sys/dev/pci/drm/radeon/cik.c

1681

(const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/cik.c

1684

(const u32)ARRAY_SIZE(hawaii_golden_registers));

sys/dev/pci/drm/radeon/cik.c

1687

(const u32)ARRAY_SIZE(hawaii_golden_common_registers));

sys/dev/pci/drm/radeon/cik.c

1690

(const u32)ARRAY_SIZE(hawaii_golden_spm_registers));

sys/dev/pci/drm/radeon/cik.c

1705

u32 cik_get_xclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/cik.c

1707

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/cik.c

1728

u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)

sys/dev/pci/drm/radeon/cik.c

1748

void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)

sys/dev/pci/drm/radeon/cik.c

1759

static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =

sys/dev/pci/drm/radeon/cik.c

179

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/cik.c

1801

static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =

sys/dev/pci/drm/radeon/cik.c

182

u32 r;

sys/dev/pci/drm/radeon/cik.c

1842

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/radeon/cik.c

1844

u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |

sys/dev/pci/drm/radeon/cik.c

1864

u32 running, tmp;

sys/dev/pci/drm/radeon/cik.c

1865

u32 *io_mc_regs = NULL;

sys/dev/pci/drm/radeon/cik.c

1889

io_mc_regs = (u32 *)&bonaire_io_mc_regs;

sys/dev/pci/drm/radeon/cik.c

1893

io_mc_regs = (u32 *)&hawaii_io_mc_regs;

sys/dev/pci/drm/radeon/cik.c

191

void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/cik.c

204

u32 temp;

sys/dev/pci/drm/radeon/cik.c

221

u32 temp;

sys/dev/pci/drm/radeon/cik.c

2322

u32 *tile = rdev->config.cik.tile_mode_array;

sys/dev/pci/drm/radeon/cik.c

2323

u32 *macrotile = rdev->config.cik.macrotile_mode_array;

sys/dev/pci/drm/radeon/cik.c

2324

const u32 num_tile_mode_states =

sys/dev/pci/drm/radeon/cik.c

2326

const u32 num_secondary_tile_mode_states =

sys/dev/pci/drm/radeon/cik.c

2328

u32 reg_offset, split_equal_to_row_size;

sys/dev/pci/drm/radeon/cik.c

2329

u32 num_pipe_configs;

sys/dev/pci/drm/radeon/cik.c

2330

u32 num_rbs = rdev->config.cik.max_backends_per_se *

sys/dev/pci/drm/radeon/cik.c

237

u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/cik.c

240

u32 r;

sys/dev/pci/drm/radeon/cik.c

250

void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/cik.c

262

static const u32 spectre_rlc_save_restore_register_list[] =

sys/dev/pci/drm/radeon/cik.c

3027

u32 se_num, u32 sh_num)

sys/dev/pci/drm/radeon/cik.c

3029

u32 data = INSTANCE_BROADCAST_WRITES;

sys/dev/pci/drm/radeon/cik.c

3050

static u32 cik_create_bitmask(u32 bit_width)

sys/dev/pci/drm/radeon/cik.c

3052

u32 i, mask = 0;

sys/dev/pci/drm/radeon/cik.c

3071

static u32 cik_get_rb_disabled(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik.c

3072

u32 max_rb_num_per_se,

sys/dev/pci/drm/radeon/cik.c

3073

u32 sh_per_se)

sys/dev/pci/drm/radeon/cik.c

3075

u32 data, mask;

sys/dev/pci/drm/radeon/cik.c

3102

u32 se_num, u32 sh_per_se,

sys/dev/pci/drm/radeon/cik.c

3103

u32 max_rb_num_per_se)

sys/dev/pci/drm/radeon/cik.c

3106

u32 data, mask;

sys/dev/pci/drm/radeon/cik.c

3107

u32 disabled_rbs = 0;

sys/dev/pci/drm/radeon/cik.c

3108

u32 enabled_rbs = 0;

sys/dev/pci/drm/radeon/cik.c

3170

u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);

sys/dev/pci/drm/radeon/cik.c

3171

u32 mc_arb_ramcfg;

sys/dev/pci/drm/radeon/cik.c

3172

u32 hdp_host_path_cntl;

sys/dev/pci/drm/radeon/cik.c

3173

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

3498

u32 ref_and_mask;

sys/dev/pci/drm/radeon/cik.c

3654

u32 size_in_bytes, cur_size_in_bytes, control;

sys/dev/pci/drm/radeon/cik.c

3723

u32 header, control = INDIRECT_BUFFER_VALID;

sys/dev/pci/drm/radeon/cik.c

3732

u32 next_rptr;

sys/dev/pci/drm/radeon/cik.c

3901

u32 fw_size;

sys/dev/pci/drm/radeon/cik.c

4049

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

4050

u32 rb_bufsz;

sys/dev/pci/drm/radeon/cik.c

4113

u32 cik_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik.c

4116

u32 rptr;

sys/dev/pci/drm/radeon/cik.c

4126

u32 cik_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik.c

4139

u32 cik_compute_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik.c

4142

u32 rptr;

sys/dev/pci/drm/radeon/cik.c

4157

u32 cik_compute_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik.c

4160

u32 wptr;

sys/dev/pci/drm/radeon/cik.c

4187

u32 j, tmp;

sys/dev/pci/drm/radeon/cik.c

4259

u32 fw_size;

sys/dev/pci/drm/radeon/cik.c

4379

u32 *hpd;

sys/dev/pci/drm/radeon/cik.c

4434

u32 cp_mqd_base_addr;

sys/dev/pci/drm/radeon/cik.c

4435

u32 cp_mqd_base_addr_hi;

sys/dev/pci/drm/radeon/cik.c

4436

u32 cp_hqd_active;

sys/dev/pci/drm/radeon/cik.c

4437

u32 cp_hqd_vmid;

sys/dev/pci/drm/radeon/cik.c

4438

u32 cp_hqd_persistent_state;

sys/dev/pci/drm/radeon/cik.c

4439

u32 cp_hqd_pipe_priority;

sys/dev/pci/drm/radeon/cik.c

4440

u32 cp_hqd_queue_priority;

sys/dev/pci/drm/radeon/cik.c

4441

u32 cp_hqd_quantum;

sys/dev/pci/drm/radeon/cik.c

4442

u32 cp_hqd_pq_base;

sys/dev/pci/drm/radeon/cik.c

4443

u32 cp_hqd_pq_base_hi;

sys/dev/pci/drm/radeon/cik.c

4444

u32 cp_hqd_pq_rptr;

sys/dev/pci/drm/radeon/cik.c

4445

u32 cp_hqd_pq_rptr_report_addr;

sys/dev/pci/drm/radeon/cik.c

4446

u32 cp_hqd_pq_rptr_report_addr_hi;

sys/dev/pci/drm/radeon/cik.c

4447

u32 cp_hqd_pq_wptr_poll_addr;

sys/dev/pci/drm/radeon/cik.c

4448

u32 cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/pci/drm/radeon/cik.c

4449

u32 cp_hqd_pq_doorbell_control;

sys/dev/pci/drm/radeon/cik.c

4450

u32 cp_hqd_pq_wptr;

sys/dev/pci/drm/radeon/cik.c

4451

u32 cp_hqd_pq_control;

sys/dev/pci/drm/radeon/cik.c

4452

u32 cp_hqd_ib_base_addr;

sys/dev/pci/drm/radeon/cik.c

4453

u32 cp_hqd_ib_base_addr_hi;

sys/dev/pci/drm/radeon/cik.c

4454

u32 cp_hqd_ib_rptr;

sys/dev/pci/drm/radeon/cik.c

4455

u32 cp_hqd_ib_control;

sys/dev/pci/drm/radeon/cik.c

4456

u32 cp_hqd_iq_timer;

sys/dev/pci/drm/radeon/cik.c

4457

u32 cp_hqd_iq_rptr;

sys/dev/pci/drm/radeon/cik.c

4458

u32 cp_hqd_dequeue_request;

sys/dev/pci/drm/radeon/cik.c

4459

u32 cp_hqd_dma_offload;

sys/dev/pci/drm/radeon/cik.c

4460

u32 cp_hqd_sema_cmd;

sys/dev/pci/drm/radeon/cik.c

4461

u32 cp_hqd_msg_type;

sys/dev/pci/drm/radeon/cik.c

4462

u32 cp_hqd_atomic0_preop_lo;

sys/dev/pci/drm/radeon/cik.c

4463

u32 cp_hqd_atomic0_preop_hi;

sys/dev/pci/drm/radeon/cik.c

4464

u32 cp_hqd_atomic1_preop_lo;

sys/dev/pci/drm/radeon/cik.c

4465

u32 cp_hqd_atomic1_preop_hi;

sys/dev/pci/drm/radeon/cik.c

4466

u32 cp_hqd_hq_scheduler0;

sys/dev/pci/drm/radeon/cik.c

4467

u32 cp_hqd_hq_scheduler1;

sys/dev/pci/drm/radeon/cik.c

4468

u32 cp_mqd_control;

sys/dev/pci/drm/radeon/cik.c

4473

u32 header;

sys/dev/pci/drm/radeon/cik.c

4474

u32 dispatch_initiator;

sys/dev/pci/drm/radeon/cik.c

4475

u32 dimensions[3];

sys/dev/pci/drm/radeon/cik.c

4476

u32 start_idx[3];

sys/dev/pci/drm/radeon/cik.c

4477

u32 num_threads[3];

sys/dev/pci/drm/radeon/cik.c

4478

u32 pipeline_stat_enable;

sys/dev/pci/drm/radeon/cik.c

4479

u32 perf_counter_enable;

sys/dev/pci/drm/radeon/cik.c

4480

u32 pgm[2];

sys/dev/pci/drm/radeon/cik.c

4481

u32 tba[2];

sys/dev/pci/drm/radeon/cik.c

4482

u32 tma[2];

sys/dev/pci/drm/radeon/cik.c

4483

u32 pgm_rsrc[2];

sys/dev/pci/drm/radeon/cik.c

4484

u32 vmid;

sys/dev/pci/drm/radeon/cik.c

4485

u32 resource_limits;

sys/dev/pci/drm/radeon/cik.c

4486

u32 static_thread_mgmt01[2];

sys/dev/pci/drm/radeon/cik.c

4487

u32 tmp_ring_size;

sys/dev/pci/drm/radeon/cik.c

4488

u32 static_thread_mgmt23[2];

sys/dev/pci/drm/radeon/cik.c

4489

u32 restart[3];

sys/dev/pci/drm/radeon/cik.c

4490

u32 thread_trace_enable;

sys/dev/pci/drm/radeon/cik.c

4491

u32 reserved1;

sys/dev/pci/drm/radeon/cik.c

4492

u32 user_data[16];

sys/dev/pci/drm/radeon/cik.c

4493

u32 vgtcs_invoke_count[2];

sys/dev/pci/drm/radeon/cik.c

4495

u32 dequeue_cntr;

sys/dev/pci/drm/radeon/cik.c

4496

u32 interrupt_queue[64];

sys/dev/pci/drm/radeon/cik.c

4511

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

4517

u32 *buf;

sys/dev/pci/drm/radeon/cik.c

4842

u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/cik.c

4844

u32 reset_mask = 0;

sys/dev/pci/drm/radeon/cik.c

4845

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

4922

static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/pci/drm/radeon/cik.c

4925

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/radeon/cik.c

4926

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

5046

u32 gmcon_reng_execute;

sys/dev/pci/drm/radeon/cik.c

5047

u32 gmcon_misc;

sys/dev/pci/drm/radeon/cik.c

5048

u32 gmcon_misc3;

sys/dev/pci/drm/radeon/cik.c

5140

u32 tmp, i;

sys/dev/pci/drm/radeon/cik.c

5211

u32 reset_mask;

sys/dev/pci/drm/radeon/cik.c

5251

u32 reset_mask = cik_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/cik.c

5274

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

5330

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

5454

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/cik.c

5478

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/cik.c

5496

u32 tmp = RREG32(CHUB_CONTROL);

sys/dev/pci/drm/radeon/cik.c

5652

u32 status, u32 addr, u32 mc_client)

sys/dev/pci/drm/radeon/cik.c

5654

u32 mc_id;

sys/dev/pci/drm/radeon/cik.c

5655

u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

sys/dev/pci/drm/radeon/cik.c

5656

u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

sys/dev/pci/drm/radeon/cik.c

5760

u32 tmp = RREG32(CP_INT_CNTL_RING0);

sys/dev/pci/drm/radeon/cik.c

5771

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

5783

u32 i, j, k;

sys/dev/pci/drm/radeon/cik.c

5784

u32 mask;

sys/dev/pci/drm/radeon/cik.c

5806

static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)

sys/dev/pci/drm/radeon/cik.c

5808

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

5815

static u32 cik_halt_rlc(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/cik.c

5817

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

5822

u32 i;

sys/dev/pci/drm/radeon/cik.c

5841

u32 tmp, i, mask;

sys/dev/pci/drm/radeon/cik.c

5862

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

5911

u32 i, size, tmp;

sys/dev/pci/drm/radeon/cik.c

5992

u32 data, orig, tmp, tmp2;

sys/dev/pci/drm/radeon/cik.c

6028

u32 data, orig, tmp = 0;

sys/dev/pci/drm/radeon/cik.c

6106

static const u32 mc_cg_registers[] =

sys/dev/pci/drm/radeon/cik.c

6123

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6140

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6156

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6177

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6205

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6231

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6249

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6265

u32 orig, data;

sys/dev/pci/drm/radeon/cik.c

6279

u32 block, bool enable)

sys/dev/pci/drm/radeon/cik.c

6355

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6369

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6382

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6395

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6412

volatile u32 *dst_ptr;

sys/dev/pci/drm/radeon/cik.c

6414

u32 bo_offset = 0;

sys/dev/pci/drm/radeon/cik.c

6415

u32 table_offset, table_size;

sys/dev/pci/drm/radeon/cik.c

6497

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6524

static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)

sys/dev/pci/drm/radeon/cik.c

6526

u32 mask = 0, tmp, tmp1;

sys/dev/pci/drm/radeon/cik.c

6549

u32 i, j, k, active_cu_number = 0;

sys/dev/pci/drm/radeon/cik.c

6550

u32 mask, counter, cu_bitmap;

sys/dev/pci/drm/radeon/cik.c

6551

u32 tmp = 0;

sys/dev/pci/drm/radeon/cik.c

6583

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6597

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6613

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

6614

u32 i;

sys/dev/pci/drm/radeon/cik.c

6667

u32 cik_get_csb_size(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/cik.c

6669

u32 count = 0;

sys/dev/pci/drm/radeon/cik.c

6699

void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)

sys/dev/pci/drm/radeon/cik.c

6701

u32 count = 0, i;

sys/dev/pci/drm/radeon/cik.c

6814

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/radeon/cik.c

6815

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/radeon/cik.c

6833

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/radeon/cik.c

6834

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/radeon/cik.c

6856

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

6939

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/radeon/cik.c

7017

u32 cp_int_cntl;

sys/dev/pci/drm/radeon/cik.c

7018

u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;

sys/dev/pci/drm/radeon/cik.c

7019

u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;

sys/dev/pci/drm/radeon/cik.c

7020

u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;

sys/dev/pci/drm/radeon/cik.c

7021

u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;

sys/dev/pci/drm/radeon/cik.c

7022

u32 grbm_int_cntl = 0;

sys/dev/pci/drm/radeon/cik.c

7023

u32 dma_cntl, dma_cntl1;

sys/dev/pci/drm/radeon/cik.c

709

static const u32 kalindi_rlc_save_restore_register_list[] =

sys/dev/pci/drm/radeon/cik.c

7287

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

7481

static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/cik.c

7483

u32 wptr, tmp;

sys/dev/pci/drm/radeon/cik.c

7542

u32 wptr;

sys/dev/pci/drm/radeon/cik.c

7543

u32 rptr;

sys/dev/pci/drm/radeon/cik.c

7544

u32 src_id, src_data, ring_id;

sys/dev/pci/drm/radeon/cik.c

7546

u32 ring_index;

sys/dev/pci/drm/radeon/cik.c

7550

u32 addr, status, mc_client;

sys/dev/pci/drm/radeon/cik.c

8281

u32 nop;

sys/dev/pci/drm/radeon/cik.c

8314

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/pci/drm/radeon/cik.c

8318

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/pci/drm/radeon/cik.c

8751

u32 tmp = 0;

sys/dev/pci/drm/radeon/cik.c

8820

static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik.c

8824

u32 tmp, buffer_alloc, i;

sys/dev/pci/drm/radeon/cik.c

8825

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/pci/drm/radeon/cik.c

8891

static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/cik.c

8893

u32 tmp = RREG32(MC_SHARED_CHMAP);

sys/dev/pci/drm/radeon/cik.c

8919

u32 dram_channels; /* number of dram channels */

sys/dev/pci/drm/radeon/cik.c

8920

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/pci/drm/radeon/cik.c

8921

u32 sclk; /* engine clock in kHz */

sys/dev/pci/drm/radeon/cik.c

8922

u32 disp_clk; /* display clock in kHz */

sys/dev/pci/drm/radeon/cik.c

8923

u32 src_width; /* viewport width */

sys/dev/pci/drm/radeon/cik.c

8924

u32 active_time; /* active display time in ns */

sys/dev/pci/drm/radeon/cik.c

8925

u32 blank_time; /* blank time in ns */

sys/dev/pci/drm/radeon/cik.c

8928

u32 num_heads; /* number of active crtcs */

sys/dev/pci/drm/radeon/cik.c

8929

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/pci/drm/radeon/cik.c

8930

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/pci/drm/radeon/cik.c

8931

u32 vtaps; /* vertical scaler taps */

sys/dev/pci/drm/radeon/cik.c

8943

static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

8972

static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

9001

static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

9030

static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

9061

static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

9064

u32 dram_bandwidth = dce8_dram_bandwidth(wm);

sys/dev/pci/drm/radeon/cik.c

9065

u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);

sys/dev/pci/drm/radeon/cik.c

9066

u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);

sys/dev/pci/drm/radeon/cik.c

9080

static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

9113

static u32 dce8_latency_watermark(struct dce8_wm_params *wm)

sys/dev/pci/drm/radeon/cik.c

9116

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/pci/drm/radeon/cik.c

9117

u32 available_bandwidth = dce8_available_bandwidth(wm);

sys/dev/pci/drm/radeon/cik.c

9118

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/pci/drm/radeon/cik.c

9119

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/pci/drm/radeon/cik.c

9120

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/pci/drm/radeon/cik.c

9121

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/pci/drm/radeon/cik.c

9123

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/pci/drm/radeon/cik.c

9124

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/pci/drm/radeon/cik.c

9125

u32 tmp, dmif_size = 12288;

sys/dev/pci/drm/radeon/cik.c

9214

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/pci/drm/radeon/cik.c

9215

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/pci/drm/radeon/cik.c

9216

u32 latency_tolerant_lines;

sys/dev/pci/drm/radeon/cik.c

9217

u32 latency_hiding;

sys/dev/pci/drm/radeon/cik.c

9251

u32 lb_size, u32 num_heads)

sys/dev/pci/drm/radeon/cik.c

9255

u32 active_time;

sys/dev/pci/drm/radeon/cik.c

9256

u32 line_time = 0;

sys/dev/pci/drm/radeon/cik.c

9257

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/pci/drm/radeon/cik.c

9258

u32 tmp, wm_mask;

sys/dev/pci/drm/radeon/cik.c

9261

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/radeon/cik.c

9262

(u32)mode->clock);

sys/dev/pci/drm/radeon/cik.c

9263

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/radeon/cik.c

9264

(u32)mode->clock);

sys/dev/pci/drm/radeon/cik.c

9265

line_time = min(line_time, (u32)65535);

sys/dev/pci/drm/radeon/cik.c

9296

latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);

sys/dev/pci/drm/radeon/cik.c

9336

latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);

sys/dev/pci/drm/radeon/cik.c

9388

u32 num_heads = 0, lb_size;

sys/dev/pci/drm/radeon/cik.c

9427

static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/pci/drm/radeon/cik.c

9428

u32 cntl_reg, u32 status_reg)

sys/dev/pci/drm/radeon/cik.c

9455

int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/pci/drm/radeon/cik.c

9467

int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/radeon/cik.c

9471

u32 tmp;

sys/dev/pci/drm/radeon/cik.c

9506

u32 speed_cntl, current_data_rate;

sys/dev/pci/drm/radeon/cik.c

9555

u32 max_lw, current_lw, tmp;

sys/dev/pci/drm/radeon/cik.c

9664

u32 data, orig;

sys/dev/pci/drm/radeon/cik.c

9742

u32 lnkcap;

sys/dev/pci/drm/radeon/cik.h

31

void cik_update_cg(struct radeon_device *rdev, u32 block, bool enable);

sys/dev/pci/drm/radeon/cik.h

32

u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/cik.h

34

u32 cik_get_csb_size(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/cik.h

35

void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);

sys/dev/pci/drm/radeon/cik_blit_shaders.h

245

static const u32 cik_default_size = ARRAY_SIZE(cik_default_state);

sys/dev/pci/drm/radeon/cik_blit_shaders.h

30

static const u32 cik_default_state[] =

sys/dev/pci/drm/radeon/cik_sdma.c

113

u32 reg;

sys/dev/pci/drm/radeon/cik_sdma.c

136

u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;

sys/dev/pci/drm/radeon/cik_sdma.c

139

u32 next_rptr = ring->wptr + 5;

sys/dev/pci/drm/radeon/cik_sdma.c

172

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

sys/dev/pci/drm/radeon/cik_sdma.c

174

u32 ref_and_mask;

sys/dev/pci/drm/radeon/cik_sdma.c

233

u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;

sys/dev/pci/drm/radeon/cik_sdma.c

251

u32 rb_cntl, reg_offset;

sys/dev/pci/drm/radeon/cik_sdma.c

332

u32 me_cntl, reg_offset;

sys/dev/pci/drm/radeon/cik_sdma.c

367

u32 rb_cntl, ib_cntl;

sys/dev/pci/drm/radeon/cik_sdma.c

368

u32 rb_bufsz;

sys/dev/pci/drm/radeon/cik_sdma.c

369

u32 reg_offset, wb_offset;

sys/dev/pci/drm/radeon/cik_sdma.c

475

u32 fw_size;

sys/dev/pci/drm/radeon/cik_sdma.c

587

u32 size_in_bytes, cur_size_in_bytes;

sys/dev/pci/drm/radeon/cik_sdma.c

65

u32 rptr, reg;

sys/dev/pci/drm/radeon/cik_sdma.c

650

u32 tmp;

sys/dev/pci/drm/radeon/cik_sdma.c

707

u32 tmp = 0;

sys/dev/pci/drm/radeon/cik_sdma.c

776

u32 reset_mask = cik_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/cik_sdma.c

777

u32 mask;

sys/dev/pci/drm/radeon/cik_sdma.c

92

u32 reg;

sys/dev/pci/drm/radeon/cik_sdma.c

947

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |

sys/dev/pci/drm/radeon/clearstate_cayman.h

1054

static const u32 SECT_CLEAR_def_1[] =

sys/dev/pci/drm/radeon/clearstate_cayman.h

1065

static const u32 SECT_CTRLCONST_def_1[] =

sys/dev/pci/drm/radeon/clearstate_cayman.h

26

static const u32 SECT_CONTEXT_def_1[] = {

sys/dev/pci/drm/radeon/clearstate_cayman.h

516

static const u32 SECT_CONTEXT_def_2[] = {

sys/dev/pci/drm/radeon/clearstate_cayman.h

524

static const u32 SECT_CONTEXT_def_3[] = {

sys/dev/pci/drm/radeon/clearstate_cayman.h

581

static const u32 SECT_CONTEXT_def_4[] =

sys/dev/pci/drm/radeon/clearstate_cayman.h

683

static const u32 SECT_CONTEXT_def_5[] =

sys/dev/pci/drm/radeon/clearstate_cayman.h

691

static const u32 SECT_CONTEXT_def_6[] =

sys/dev/pci/drm/radeon/clearstate_cayman.h

750

static const u32 SECT_CONTEXT_def_7[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

1054

static const u32 SECT_CLEAR_def_1[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

1065

static const u32 SECT_CTRLCONST_def_1[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

24

static const u32 SECT_CONTEXT_def_1[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

515

static const u32 SECT_CONTEXT_def_2[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

524

static const u32 SECT_CONTEXT_def_3[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

582

static const u32 SECT_CONTEXT_def_4[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

683

static const u32 SECT_CONTEXT_def_5[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

691

static const u32 SECT_CONTEXT_def_6[] =

sys/dev/pci/drm/radeon/clearstate_evergreen.h

750

static const u32 SECT_CONTEXT_def_7[] =

sys/dev/pci/drm/radeon/clearstate_si.h

240

static const u32 si_SECT_CONTEXT_def_2[] =

sys/dev/pci/drm/radeon/clearstate_si.h

26

static const u32 si_SECT_CONTEXT_def_1[] = {

sys/dev/pci/drm/radeon/clearstate_si.h

515

static const u32 si_SECT_CONTEXT_def_3[] =

sys/dev/pci/drm/radeon/clearstate_si.h

524

static const u32 si_SECT_CONTEXT_def_4[] =

sys/dev/pci/drm/radeon/clearstate_si.h

684

static const u32 si_SECT_CONTEXT_def_5[] =

sys/dev/pci/drm/radeon/clearstate_si.h

688

static const u32 si_SECT_CONTEXT_def_6[] =

sys/dev/pci/drm/radeon/clearstate_si.h

692

static const u32 si_SECT_CONTEXT_def_7[] =

sys/dev/pci/drm/radeon/cypress_dpm.c

1037

u32 i;

sys/dev/pci/drm/radeon/cypress_dpm.c

1049

u32 i, j;

sys/dev/pci/drm/radeon/cypress_dpm.c

1093

u32 i, j;

sys/dev/pci/drm/radeon/cypress_dpm.c

1094

u32 channels = 2;

sys/dev/pci/drm/radeon/cypress_dpm.c

1123

u32 strobe_mode;

sys/dev/pci/drm/radeon/cypress_dpm.c

1124

u32 mc_seq_cg;

sys/dev/pci/drm/radeon/cypress_dpm.c

1171

u32 value;

sys/dev/pci/drm/radeon/cypress_dpm.c

1172

u32 i;

sys/dev/pci/drm/radeon/cypress_dpm.c

1184

u32 strobe_mode;

sys/dev/pci/drm/radeon/cypress_dpm.c

1185

u32 mc_seq_cg;

sys/dev/pci/drm/radeon/cypress_dpm.c

1244

u32 a_t;

sys/dev/pci/drm/radeon/cypress_dpm.c

1338

u32 mpll_ad_func_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

1340

u32 mpll_ad_func_cntl_2 =

sys/dev/pci/drm/radeon/cypress_dpm.c

1342

u32 mpll_dq_func_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

1344

u32 mpll_dq_func_cntl_2 =

sys/dev/pci/drm/radeon/cypress_dpm.c

1346

u32 spll_func_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

1348

u32 spll_func_cntl_2 =

sys/dev/pci/drm/radeon/cypress_dpm.c

1350

u32 spll_func_cntl_3 =

sys/dev/pci/drm/radeon/cypress_dpm.c

1352

u32 mclk_pwrmgt_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

1354

u32 dll_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

1564

static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)

sys/dev/pci/drm/radeon/cypress_dpm.c

1579

u32 tmp = RREG32(GENERAL_PWRMGT);

sys/dev/pci/drm/radeon/cypress_dpm.c

1698

u32 tmp;

sys/dev/pci/drm/radeon/cypress_dpm.c

1733

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/cypress_dpm.c

1747

u32 tmp, pipe;

sys/dev/pci/drm/radeon/cypress_dpm.c

177

u32 cgts_sm_ctrl_reg;

sys/dev/pci/drm/radeon/cypress_dpm.c

2159

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/pci/drm/radeon/cypress_dpm.c

2161

u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

sys/dev/pci/drm/radeon/cypress_dpm.c

275

u32 reference_clock;

sys/dev/pci/drm/radeon/cypress_dpm.c

276

u32 mclk_switch_limit;

sys/dev/pci/drm/radeon/cypress_dpm.c

305

u32 tmp;

sys/dev/pci/drm/radeon/cypress_dpm.c

330

u32 tmp;

sys/dev/pci/drm/radeon/cypress_dpm.c

422

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/pci/drm/radeon/cypress_dpm.c

440

u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)

sys/dev/pci/drm/radeon/cypress_dpm.c

442

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/cypress_dpm.c

443

u32 vco = clkf * ref_clk;

sys/dev/pci/drm/radeon/cypress_dpm.c

473

u32 engine_clock, u32 memory_clock,

sys/dev/pci/drm/radeon/cypress_dpm.c

479

u32 mpll_ad_func_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

481

u32 mpll_ad_func_cntl_2 =

sys/dev/pci/drm/radeon/cypress_dpm.c

483

u32 mpll_dq_func_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

485

u32 mpll_dq_func_cntl_2 =

sys/dev/pci/drm/radeon/cypress_dpm.c

487

u32 mclk_pwrmgt_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

489

u32 dll_cntl =

sys/dev/pci/drm/radeon/cypress_dpm.c

491

u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;

sys/dev/pci/drm/radeon/cypress_dpm.c

492

u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;

sys/dev/pci/drm/radeon/cypress_dpm.c

494

u32 ibias;

sys/dev/pci/drm/radeon/cypress_dpm.c

495

u32 dll_speed;

sys/dev/pci/drm/radeon/cypress_dpm.c

497

u32 mc_seq_misc7;

sys/dev/pci/drm/radeon/cypress_dpm.c

52

u32 tmp, bif;

sys/dev/pci/drm/radeon/cypress_dpm.c

554

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/pci/drm/radeon/cypress_dpm.c

558

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/cypress_dpm.c

559

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/pci/drm/radeon/cypress_dpm.c

560

u32 clk_s, clk_v;

sys/dev/pci/drm/radeon/cypress_dpm.c

614

u32 memory_clock, bool strobe_mode)

sys/dev/pci/drm/radeon/cypress_dpm.c

655

u32 mclk,

sys/dev/pci/drm/radeon/cypress_dpm.c

818

u32 num_entries, u32 valid_flag)

sys/dev/pci/drm/radeon/cypress_dpm.c

820

u32 i, j;

sys/dev/pci/drm/radeon/cypress_dpm.c

835

u32 i = 0;

sys/dev/pci/drm/radeon/cypress_dpm.c

906

u32 cypress_calculate_burst_time(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cypress_dpm.c

907

u32 engine_clock, u32 memory_clock)

sys/dev/pci/drm/radeon/cypress_dpm.c

910

u32 multiplier = pi->mem_gddr5 ? 1 : 2;

sys/dev/pci/drm/radeon/cypress_dpm.c

911

u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);

sys/dev/pci/drm/radeon/cypress_dpm.c

912

u32 burst_time;

sys/dev/pci/drm/radeon/cypress_dpm.c

931

u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);

sys/dev/pci/drm/radeon/cypress_dpm.c

954

u32 i, j;

sys/dev/pci/drm/radeon/cypress_dpm.c

972

u32 i = 0;

sys/dev/pci/drm/radeon/cypress_dpm.h

124

u32 cypress_calculate_burst_time(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cypress_dpm.h

125

u32 engine_clock, u32 memory_clock);

sys/dev/pci/drm/radeon/cypress_dpm.h

155

u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);

sys/dev/pci/drm/radeon/cypress_dpm.h

157

u32 memory_clock, bool strobe_mode);

sys/dev/pci/drm/radeon/cypress_dpm.h

158

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);

sys/dev/pci/drm/radeon/cypress_dpm.h

30

u32 mclk_max;

sys/dev/pci/drm/radeon/cypress_dpm.h

31

u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/cypress_dpm.h

48

u32 mc_arb_dram_timing;

sys/dev/pci/drm/radeon/cypress_dpm.h

49

u32 mc_arb_dram_timing2;

sys/dev/pci/drm/radeon/cypress_dpm.h

50

u32 mc_arb_rfsh_rate;

sys/dev/pci/drm/radeon/cypress_dpm.h

51

u32 mc_arb_burst_time;

sys/dev/pci/drm/radeon/cypress_dpm.h

55

u32 rlp;

sys/dev/pci/drm/radeon/cypress_dpm.h

56

u32 rmp;

sys/dev/pci/drm/radeon/cypress_dpm.h

57

u32 lhp;

sys/dev/pci/drm/radeon/cypress_dpm.h

58

u32 lmp;

sys/dev/pci/drm/radeon/cypress_dpm.h

82

u32 mclk_edc_wr_enable_threshold;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

123

u32 dto_phase;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

124

u32 wallclock_ratio;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

125

u32 dto_cntl;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

203

void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/pci/drm/radeon/dce3_1_afmt.c

224

void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)

sys/dev/pci/drm/radeon/dce3_1_afmt.c

35

u32 tmp;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

53

u32 tmp;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

88

u32 value = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

132

u32 tmp = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

160

u32 tmp;

sys/dev/pci/drm/radeon/dce6_afmt.c

185

u32 tmp;

sys/dev/pci/drm/radeon/dce6_afmt.c

230

u32 value = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

274

u32 value = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

293

u32 value = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

34

u32 dce6_endpoint_rreg(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/dce6_afmt.c

35

u32 block_offset, u32 reg)

sys/dev/pci/drm/radeon/dce6_afmt.c

38

u32 r;

sys/dev/pci/drm/radeon/dce6_afmt.c

49

u32 block_offset, u32 reg, u32 v)

sys/dev/pci/drm/radeon/dce6_afmt.c

66

u32 offset, tmp;

sys/dev/pci/drm/radeon/dce6_afmt.h

35

u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);

sys/dev/pci/drm/radeon/dce6_afmt.h

36

void dce6_endpoint_wreg(struct radeon_device *rdev, u32 offset, u32 reg, u32 v);

sys/dev/pci/drm/radeon/evergreen.c

1004

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1007

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/pci/drm/radeon/evergreen.c

101

u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/evergreen.c

1010

(const u32)ARRAY_SIZE(cypress_mgcg_init));

sys/dev/pci/drm/radeon/evergreen.c

1015

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1018

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/pci/drm/radeon/evergreen.c

1021

(const u32)ARRAY_SIZE(juniper_mgcg_init));

sys/dev/pci/drm/radeon/evergreen.c

1026

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1029

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/pci/drm/radeon/evergreen.c

1032

(const u32)ARRAY_SIZE(redwood_mgcg_init));

sys/dev/pci/drm/radeon/evergreen.c

1037

(const u32)ARRAY_SIZE(cedar_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

104

u32 r;

sys/dev/pci/drm/radeon/evergreen.c

1040

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/pci/drm/radeon/evergreen.c

1043

(const u32)ARRAY_SIZE(cedar_mgcg_init));

sys/dev/pci/drm/radeon/evergreen.c

1048

(const u32)ARRAY_SIZE(wrestler_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1053

(const u32)ARRAY_SIZE(supersumo_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1058

(const u32)ARRAY_SIZE(supersumo_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1061

(const u32)ARRAY_SIZE(sumo_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1066

(const u32)ARRAY_SIZE(barts_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1071

(const u32)ARRAY_SIZE(turks_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1076

(const u32)ARRAY_SIZE(caicos_golden_registers));

sys/dev/pci/drm/radeon/evergreen.c

1094

u32 reg, u32 *val)

sys/dev/pci/drm/radeon/evergreen.c

113

void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/evergreen.c

1142

static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/pci/drm/radeon/evergreen.c

1143

u32 cntl_reg, u32 status_reg)

sys/dev/pci/drm/radeon/evergreen.c

1166

int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/pci/drm/radeon/evergreen.c

1169

u32 cg_scratch = RREG32(CG_SCRATCH1);

sys/dev/pci/drm/radeon/evergreen.c

1189

int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/pci/drm/radeon/evergreen.c

123

static const u32 crtc_offsets[6] =

sys/dev/pci/drm/radeon/evergreen.c

1300

u32 tmp = 0;

sys/dev/pci/drm/radeon/evergreen.c

135

static const u32 sumo_rlc_save_restore_register_list[] =

sys/dev/pci/drm/radeon/evergreen.c

1358

u32 pos1, pos2;

sys/dev/pci/drm/radeon/evergreen.c

1432

(u32)crtc_base);

sys/dev/pci/drm/radeon/evergreen.c

1457

u32 temp, toffset;

sys/dev/pci/drm/radeon/evergreen.c

1495

u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;

sys/dev/pci/drm/radeon/evergreen.c

1679

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

1704

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

1769

u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |

sys/dev/pci/drm/radeon/evergreen.c

1826

static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/evergreen.c

1831

u32 tmp, buffer_alloc, i;

sys/dev/pci/drm/radeon/evergreen.c

1832

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/pci/drm/radeon/evergreen.c

1917

u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/evergreen.c

1919

u32 tmp = RREG32(MC_SHARED_CHMAP);

sys/dev/pci/drm/radeon/evergreen.c

1935

u32 dram_channels; /* number of dram channels */

sys/dev/pci/drm/radeon/evergreen.c

1936

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/pci/drm/radeon/evergreen.c

1937

u32 sclk; /* engine clock in kHz */

sys/dev/pci/drm/radeon/evergreen.c

1938

u32 disp_clk; /* display clock in kHz */

sys/dev/pci/drm/radeon/evergreen.c

1939

u32 src_width; /* viewport width */

sys/dev/pci/drm/radeon/evergreen.c

1940

u32 active_time; /* active display time in ns */

sys/dev/pci/drm/radeon/evergreen.c

1941

u32 blank_time; /* blank time in ns */

sys/dev/pci/drm/radeon/evergreen.c

1944

u32 num_heads; /* number of active crtcs */

sys/dev/pci/drm/radeon/evergreen.c

1945

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/pci/drm/radeon/evergreen.c

1946

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/pci/drm/radeon/evergreen.c

1947

u32 vtaps; /* vertical scaler taps */

sys/dev/pci/drm/radeon/evergreen.c

1950

static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

1970

static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

1990

static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

2010

static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

2030

static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

2033

u32 dram_bandwidth = evergreen_dram_bandwidth(wm);

sys/dev/pci/drm/radeon/evergreen.c

2034

u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);

sys/dev/pci/drm/radeon/evergreen.c

2035

u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);

sys/dev/pci/drm/radeon/evergreen.c

2040

static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

2064

static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)

sys/dev/pci/drm/radeon/evergreen.c

2067

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/pci/drm/radeon/evergreen.c

2068

u32 available_bandwidth = evergreen_available_bandwidth(wm);

sys/dev/pci/drm/radeon/evergreen.c

2069

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/pci/drm/radeon/evergreen.c

2070

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/pci/drm/radeon/evergreen.c

2071

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/pci/drm/radeon/evergreen.c

2072

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/pci/drm/radeon/evergreen.c

2074

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/pci/drm/radeon/evergreen.c

2075

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/pci/drm/radeon/evergreen.c

2131

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/pci/drm/radeon/evergreen.c

2132

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/pci/drm/radeon/evergreen.c

2133

u32 latency_tolerant_lines;

sys/dev/pci/drm/radeon/evergreen.c

2134

u32 latency_hiding;

sys/dev/pci/drm/radeon/evergreen.c

2157

u32 lb_size, u32 num_heads)

sys/dev/pci/drm/radeon/evergreen.c

2161

u32 dram_channels;

sys/dev/pci/drm/radeon/evergreen.c

2162

u32 active_time;

sys/dev/pci/drm/radeon/evergreen.c

2163

u32 line_time = 0;

sys/dev/pci/drm/radeon/evergreen.c

2164

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/pci/drm/radeon/evergreen.c

2165

u32 priority_a_mark = 0, priority_b_mark = 0;

sys/dev/pci/drm/radeon/evergreen.c

2166

u32 priority_a_cnt = PRIORITY_OFF;

sys/dev/pci/drm/radeon/evergreen.c

2167

u32 priority_b_cnt = PRIORITY_OFF;

sys/dev/pci/drm/radeon/evergreen.c

2168

u32 pipe_offset = radeon_crtc->crtc_id * 16;

sys/dev/pci/drm/radeon/evergreen.c

2169

u32 tmp, arb_control3;

sys/dev/pci/drm/radeon/evergreen.c

2173

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/radeon/evergreen.c

2174

(u32)mode->clock);

sys/dev/pci/drm/radeon/evergreen.c

2175

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/radeon/evergreen.c

2176

(u32)mode->clock);

sys/dev/pci/drm/radeon/evergreen.c

2177

line_time = min(line_time, (u32)65535);

sys/dev/pci/drm/radeon/evergreen.c

2237

latency_watermark_a = min(evergreen_latency_watermark(&wm_high), (u32)65535);

sys/dev/pci/drm/radeon/evergreen.c

2239

latency_watermark_b = min(evergreen_latency_watermark(&wm_low), (u32)65535);

sys/dev/pci/drm/radeon/evergreen.c

225

static const u32 evergreen_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

2328

u32 num_heads = 0, lb_size;

sys/dev/pci/drm/radeon/evergreen.c

2362

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

2380

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

2402

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

2447

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/evergreen.c

2460

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

2493

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

2665

u32 crtc_enabled, tmp, frame_count, blackout;

sys/dev/pci/drm/radeon/evergreen.c

271

static const u32 evergreen_golden_registers2[] =

sys/dev/pci/drm/radeon/evergreen.c

2763

u32 tmp, frame_count;

sys/dev/pci/drm/radeon/evergreen.c

2773

(u32)rdev->mc.vram_start);

sys/dev/pci/drm/radeon/evergreen.c

2775

(u32)rdev->mc.vram_start);

sys/dev/pci/drm/radeon/evergreen.c

2780

WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

sys/dev/pci/drm/radeon/evergreen.c

2852

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

289

static const u32 cypress_mgcg_init[] =

sys/dev/pci/drm/radeon/evergreen.c

2932

u32 next_rptr;

sys/dev/pci/drm/radeon/evergreen.c

3065

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

3066

u32 rb_bufsz;

sys/dev/pci/drm/radeon/evergreen.c

3134

u32 gb_addr_config;

sys/dev/pci/drm/radeon/evergreen.c

3135

u32 mc_arb_ramcfg;

sys/dev/pci/drm/radeon/evergreen.c

3136

u32 sx_debug_1;

sys/dev/pci/drm/radeon/evergreen.c

3137

u32 smx_dc_ctl0;

sys/dev/pci/drm/radeon/evergreen.c

3138

u32 sq_config;

sys/dev/pci/drm/radeon/evergreen.c

3139

u32 sq_lds_resource_mgmt;

sys/dev/pci/drm/radeon/evergreen.c

3140

u32 sq_gpr_resource_mgmt_1;

sys/dev/pci/drm/radeon/evergreen.c

3141

u32 sq_gpr_resource_mgmt_2;

sys/dev/pci/drm/radeon/evergreen.c

3142

u32 sq_gpr_resource_mgmt_3;

sys/dev/pci/drm/radeon/evergreen.c

3143

u32 sq_thread_resource_mgmt;

sys/dev/pci/drm/radeon/evergreen.c

3144

u32 sq_thread_resource_mgmt_2;

sys/dev/pci/drm/radeon/evergreen.c

3145

u32 sq_stack_resource_mgmt_1;

sys/dev/pci/drm/radeon/evergreen.c

3146

u32 sq_stack_resource_mgmt_2;

sys/dev/pci/drm/radeon/evergreen.c

3147

u32 sq_stack_resource_mgmt_3;

sys/dev/pci/drm/radeon/evergreen.c

3148

u32 vgt_cache_invalidation;

sys/dev/pci/drm/radeon/evergreen.c

3149

u32 hdp_host_path_cntl, tmp;

sys/dev/pci/drm/radeon/evergreen.c

3150

u32 disabled_rb_mask;

sys/dev/pci/drm/radeon/evergreen.c

3452

u32 efuse_straps_4;

sys/dev/pci/drm/radeon/evergreen.c

3453

u32 efuse_straps_3;

sys/dev/pci/drm/radeon/evergreen.c

3462

u32 rb_disable_bitmap;

sys/dev/pci/drm/radeon/evergreen.c

3483

u32 simd_disable_bitmap;

sys/dev/pci/drm/radeon/evergreen.c

3711

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

3798

u32 crtc_hung = 0;

sys/dev/pci/drm/radeon/evergreen.c

3799

u32 crtc_status[6];

sys/dev/pci/drm/radeon/evergreen.c

3800

u32 i, j, tmp;

sys/dev/pci/drm/radeon/evergreen.c

3825

u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/evergreen.c

3827

u32 reset_mask = 0;

sys/dev/pci/drm/radeon/evergreen.c

3828

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

3894

static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/pci/drm/radeon/evergreen.c

3897

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/radeon/evergreen.c

3898

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

4011

u32 tmp, i;

sys/dev/pci/drm/radeon/evergreen.c

4052

u32 reset_mask;

sys/dev/pci/drm/radeon/evergreen.c

4092

u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/evergreen.c

4154

const u32 *src_ptr;

sys/dev/pci/drm/radeon/evergreen.c

4155

volatile u32 *dst_ptr;

sys/dev/pci/drm/radeon/evergreen.c

4156

u32 dws, data, i, j, k, reg_num;

sys/dev/pci/drm/radeon/evergreen.c

4157

u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index = 0;

sys/dev/pci/drm/radeon/evergreen.c

4371

u32 mask = RLC_ENABLE;

sys/dev/pci/drm/radeon/evergreen.c

4382

u32 i;

sys/dev/pci/drm/radeon/evergreen.c

4394

u32 always_on_bitmap =

sys/dev/pci/drm/radeon/evergreen.c

4397

u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

sys/dev/pci/drm/radeon/evergreen.c

442

static const u32 redwood_mgcg_init[] =

sys/dev/pci/drm/radeon/evergreen.c

4449

u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)

sys/dev/pci/drm/radeon/evergreen.c

4460

u32 tmp;

sys/dev/pci/drm/radeon/evergreen.c

4493

u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;

sys/dev/pci/drm/radeon/evergreen.c

4494

u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;

sys/dev/pci/drm/radeon/evergreen.c

4495

u32 grbm_int_cntl = 0;

sys/dev/pci/drm/radeon/evergreen.c

4496

u32 dma_cntl, dma_cntl1 = 0;

sys/dev/pci/drm/radeon/evergreen.c

4497

u32 thermal_int = 0;

sys/dev/pci/drm/radeon/evergreen.c

4614

u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;

sys/dev/pci/drm/radeon/evergreen.c

4615

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/pci/drm/radeon/evergreen.c

4616

u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;

sys/dev/pci/drm/radeon/evergreen.c

4675

static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/evergreen.c

4677

u32 wptr, tmp;

sys/dev/pci/drm/radeon/evergreen.c

4702

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/pci/drm/radeon/evergreen.c

4703

u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;

sys/dev/pci/drm/radeon/evergreen.c

4704

u32 crtc_idx, hpd_idx, afmt_idx;

sys/dev/pci/drm/radeon/evergreen.c

4705

u32 mask;

sys/dev/pci/drm/radeon/evergreen.c

4706

u32 wptr;

sys/dev/pci/drm/radeon/evergreen.c

4707

u32 rptr;

sys/dev/pci/drm/radeon/evergreen.c

4708

u32 src_id, src_data;

sys/dev/pci/drm/radeon/evergreen.c

4709

u32 ring_index;

sys/dev/pci/drm/radeon/evergreen.c

4714

u32 status, addr;

sys/dev/pci/drm/radeon/evergreen.c

5039

(u32)ARRAY_SIZE(sumo_rlc_save_restore_register_list);

sys/dev/pci/drm/radeon/evergreen.c

514

static const u32 cedar_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

5327

u32 link_width_cntl, speed_cntl;

sys/dev/pci/drm/radeon/evergreen.c

5392

u32 data, orig;

sys/dev/pci/drm/radeon/evergreen.c

5393

u32 pcie_lc_cntl, pcie_lc_cntl_old;

sys/dev/pci/drm/radeon/evergreen.c

557

static const u32 cedar_mgcg_init[] =

sys/dev/pci/drm/radeon/evergreen.c

57

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/evergreen.c

60

u32 r;

sys/dev/pci/drm/radeon/evergreen.c

611

static const u32 juniper_mgcg_init[] =

sys/dev/pci/drm/radeon/evergreen.c

69

void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/evergreen.c

709

static const u32 supersumo_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

784

static const u32 sumo_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

79

u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/evergreen.c

793

static const u32 wrestler_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

82

u32 r;

sys/dev/pci/drm/radeon/evergreen.c

846

static const u32 barts_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

895

static const u32 turks_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.c

91

void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/evergreen.c

946

static const u32 caicos_golden_registers[] =

sys/dev/pci/drm/radeon/evergreen.h

47

u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/evergreen.h

48

u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/evergreen_blit_shaders.h

301

static const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);

sys/dev/pci/drm/radeon/evergreen_blit_shaders.h

40

static const u32 evergreen_default_state[] = {

sys/dev/pci/drm/radeon/evergreen_cs.c

104

static u32 evergreen_cs_get_num_banks(u32 nbanks)

sys/dev/pci/drm/radeon/evergreen_cs.c

1095

static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/pci/drm/radeon/evergreen_cs.c

1099

u32 tmp, *ib;

sys/dev/pci/drm/radeon/evergreen_cs.c

1150

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1222

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1234

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1246

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1258

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1282

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1302

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1506

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1523

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1564

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1580

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1592

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1709

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1723

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1737

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

1757

static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg)

sys/dev/pci/drm/radeon/evergreen_cs.c

1760

u32 m, i;

sys/dev/pci/drm/radeon/evergreen_cs.c

1783

u32 idx_value;

sys/dev/pci/drm/radeon/evergreen_cs.c

2080

ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2115

u32 command, size, info;

sys/dev/pci/drm/radeon/evergreen_cs.c

2233

ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2350

u32 toffset, moffset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2351

u32 size, offset, mip_address, tex_dim;

sys/dev/pci/drm/radeon/evergreen_cs.c

2379

toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2398

moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

2767

u32 tmp;

sys/dev/pci/drm/radeon/evergreen_cs.c

2892

u32 header, cmd, count, sub_cmd;

sys/dev/pci/drm/radeon/evergreen_cs.c

2894

u32 idx;

sys/dev/pci/drm/radeon/evergreen_cs.c

2923

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

2931

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

2974

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

2975

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

2987

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

2991

ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

2997

ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3002

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3033

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

3034

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

3046

ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

3048

ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff);

sys/dev/pci/drm/radeon/evergreen_cs.c

3082

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3083

ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3084

ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3122

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3123

ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3124

ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3138

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3140

ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3144

ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3147

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3184

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3185

ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3186

ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3198

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3202

ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3208

ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3213

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3234

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3235

ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3271

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3272

ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3273

ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3295

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/evergreen_cs.c

3317

static bool evergreen_vm_reg_valid(u32 reg)

sys/dev/pci/drm/radeon/evergreen_cs.c

3440

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/pci/drm/radeon/evergreen_cs.c

3442

u32 idx = pkt->idx + 1;

sys/dev/pci/drm/radeon/evergreen_cs.c

3443

u32 idx_value = ib[idx];

sys/dev/pci/drm/radeon/evergreen_cs.c

3444

u32 start_reg, end_reg, reg, i;

sys/dev/pci/drm/radeon/evergreen_cs.c

3445

u32 command, info;

sys/dev/pci/drm/radeon/evergreen_cs.c

3620

u32 idx = 0;

sys/dev/pci/drm/radeon/evergreen_cs.c

3664

u32 idx = 0;

sys/dev/pci/drm/radeon/evergreen_cs.c

3665

u32 header, cmd, count, sub_cmd;

sys/dev/pci/drm/radeon/evergreen_cs.c

44

u32 group_size;

sys/dev/pci/drm/radeon/evergreen_cs.c

45

u32 nbanks;

sys/dev/pci/drm/radeon/evergreen_cs.c

46

u32 npipes;

sys/dev/pci/drm/radeon/evergreen_cs.c

47

u32 row_size;

sys/dev/pci/drm/radeon/evergreen_cs.c

49

u32 nsamples; /* unused */

sys/dev/pci/drm/radeon/evergreen_cs.c

51

u32 cb_color_bo_offset[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

54

u32 cb_color_info[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

55

u32 cb_color_view[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

56

u32 cb_color_pitch[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

57

u32 cb_color_slice[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

58

u32 cb_color_slice_idx[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

59

u32 cb_color_attrib[12];

sys/dev/pci/drm/radeon/evergreen_cs.c

60

u32 cb_color_cmask_slice[8];/* unused */

sys/dev/pci/drm/radeon/evergreen_cs.c

61

u32 cb_color_fmask_slice[8];/* unused */

sys/dev/pci/drm/radeon/evergreen_cs.c

62

u32 cb_target_mask;

sys/dev/pci/drm/radeon/evergreen_cs.c

63

u32 cb_shader_mask; /* unused */

sys/dev/pci/drm/radeon/evergreen_cs.c

64

u32 vgt_strmout_config;

sys/dev/pci/drm/radeon/evergreen_cs.c

65

u32 vgt_strmout_buffer_config;

sys/dev/pci/drm/radeon/evergreen_cs.c

67

u32 vgt_strmout_bo_offset[4];

sys/dev/pci/drm/radeon/evergreen_cs.c

68

u32 vgt_strmout_size[4];

sys/dev/pci/drm/radeon/evergreen_cs.c

69

u32 db_depth_control;

sys/dev/pci/drm/radeon/evergreen_cs.c

70

u32 db_depth_view;

sys/dev/pci/drm/radeon/evergreen_cs.c

71

u32 db_depth_slice;

sys/dev/pci/drm/radeon/evergreen_cs.c

72

u32 db_depth_size;

sys/dev/pci/drm/radeon/evergreen_cs.c

73

u32 db_z_info;

sys/dev/pci/drm/radeon/evergreen_cs.c

74

u32 db_z_read_offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

75

u32 db_z_write_offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

762

u32 texdw[8];

sys/dev/pci/drm/radeon/evergreen_cs.c

78

u32 db_s_info;

sys/dev/pci/drm/radeon/evergreen_cs.c

79

u32 db_s_read_offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

80

u32 db_s_write_offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

87

u32 htile_offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

88

u32 htile_surface;

sys/dev/pci/drm/radeon/evergreen_cs.c

94

static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)

sys/dev/pci/drm/radeon/evergreen_cs.c

976

u32 format = G_028C70_FORMAT(track->cb_color_info[i]);

sys/dev/pci/drm/radeon/evergreen_dma.c

116

u32 size_in_dw, cur_size_in_dw;

sys/dev/pci/drm/radeon/evergreen_dma.c

172

u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/evergreen_dma.c

72

u32 next_rptr = ring->wptr + 4;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

103

u32 tmp = 0;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

125

u32 tmp;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

143

u32 tmp;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

178

u32 value = 0;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

210

void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/evergreen_hdmi.c

233

u32 dto_phase;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

234

u32 wallclock_ratio;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

235

u32 value;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

275

u32 value;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

308

void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

319

void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

356

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

391

void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

43

u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

43

void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/evergreen_hdmi.h

63

void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

65

u32 offset, int bpc);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

66

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

67

void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/pci/drm/radeon/kv_dpm.c

1016

u32 thermal_int;

sys/dev/pci/drm/radeon/kv_dpm.c

1249

u32 mask;

sys/dev/pci/drm/radeon/kv_dpm.c

1279

static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)

sys/dev/pci/drm/radeon/kv_dpm.c

1530

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

161

u32 data;

sys/dev/pci/drm/radeon/kv_dpm.c

162

u32 cache = 0;

sys/dev/pci/drm/radeon/kv_dpm.c

1839

u32 enable_mask, i;

sys/dev/pci/drm/radeon/kv_dpm.c

1859

u32 enable_mask, i;

sys/dev/pci/drm/radeon/kv_dpm.c

1877

u32 sclk, u32 min_sclk_in_sr)

sys/dev/pci/drm/radeon/kv_dpm.c

1880

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

1881

u32 temp;

sys/dev/pci/drm/radeon/kv_dpm.c

1882

u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?

sys/dev/pci/drm/radeon/kv_dpm.c

1940

u32 min_sclk = 10000; /* ??? */

sys/dev/pci/drm/radeon/kv_dpm.c

1941

u32 sclk, mclk = 0;

sys/dev/pci/drm/radeon/kv_dpm.c

1946

u32 stable_p_state_sclk = 0;

sys/dev/pci/drm/radeon/kv_dpm.c

2051

u32 index, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

2061

u32 sclk_in_sr = 10000; /* ??? */

sys/dev/pci/drm/radeon/kv_dpm.c

2062

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

2079

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

2083

u32 mclk = max_limits->mclk;

sys/dev/pci/drm/radeon/kv_dpm.c

209

u32 data;

sys/dev/pci/drm/radeon/kv_dpm.c

2133

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

2147

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

2152

u32 vid_2bit;

sys/dev/pci/drm/radeon/kv_dpm.c

2196

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

2204

static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)

sys/dev/pci/drm/radeon/kv_dpm.c

2206

u32 new_mask = (1 << level);

sys/dev/pci/drm/radeon/kv_dpm.c

2216

u32 i, new_mask = 0;

sys/dev/pci/drm/radeon/kv_dpm.c

2231

u32 nbdpmconfig1;

sys/dev/pci/drm/radeon/kv_dpm.c

2253

u32 tmp;

sys/dev/pci/drm/radeon/kv_dpm.c

2413

u32 sclk;

sys/dev/pci/drm/radeon/kv_dpm.c

2505

u32 sclk;

sys/dev/pci/drm/radeon/kv_dpm.c

2601

u32 current_index =

sys/dev/pci/drm/radeon/kv_dpm.c

2604

u32 sclk, tmp;

sys/dev/pci/drm/radeon/kv_dpm.c

2621

u32 kv_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/kv_dpm.c

2624

u32 current_index =

sys/dev/pci/drm/radeon/kv_dpm.c

2627

u32 sclk;

sys/dev/pci/drm/radeon/kv_dpm.c

2637

u32 kv_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/kv_dpm.c

2679

u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/kv_dpm.c

2690

u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/kv_dpm.c

299

u32 tmp;

sys/dev/pci/drm/radeon/kv_dpm.c

376

u32 index, u32 sclk)

sys/dev/pci/drm/radeon/kv_dpm.c

393

static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/kv_dpm.c

395

u32 vid_2bit)

sys/dev/pci/drm/radeon/kv_dpm.c

399

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

415

static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/kv_dpm.c

417

u32 vid_7bit)

sys/dev/pci/drm/radeon/kv_dpm.c

421

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

446

u32 vid_2bit)

sys/dev/pci/drm/radeon/kv_dpm.c

449

u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,

sys/dev/pci/drm/radeon/kv_dpm.c

457

static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)

sys/dev/pci/drm/radeon/kv_dpm.c

46

static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);

sys/dev/pci/drm/radeon/kv_dpm.c

468

static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)

sys/dev/pci/drm/radeon/kv_dpm.c

478

u32 index, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

487

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/pci/drm/radeon/kv_dpm.c

502

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/pci/drm/radeon/kv_dpm.c

512

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/pci/drm/radeon/kv_dpm.c

541

u32 low_sclk_interrupt_t = 0;

sys/dev/pci/drm/radeon/kv_dpm.c

551

sizeof(u32), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

559

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

629

static u32 kv_get_clock_difference(u32 a, u32 b)

sys/dev/pci/drm/radeon/kv_dpm.c

634

static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)

sys/dev/pci/drm/radeon/kv_dpm.c

637

u32 value;

sys/dev/pci/drm/radeon/kv_dpm.c

65

u32 block, bool enable);

sys/dev/pci/drm/radeon/kv_dpm.c

666

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

734

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

800

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

866

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.c

920

u32 i;

sys/dev/pci/drm/radeon/kv_dpm.h

103

u32 uma_channel_number;

sys/dev/pci/drm/radeon/kv_dpm.h

107

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/pci/drm/radeon/kv_dpm.h

108

u32 voltage_drop_t;

sys/dev/pci/drm/radeon/kv_dpm.h

115

u32 lowest_valid;

sys/dev/pci/drm/radeon/kv_dpm.h

116

u32 highest_valid;

sys/dev/pci/drm/radeon/kv_dpm.h

121

u32 sram_end;

sys/dev/pci/drm/radeon/kv_dpm.h

122

u32 dpm_table_start;

sys/dev/pci/drm/radeon/kv_dpm.h

123

u32 soft_regs_start;

sys/dev/pci/drm/radeon/kv_dpm.h

152

u32 low_sclk_interrupt_t;

sys/dev/pci/drm/radeon/kv_dpm.h

188

int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);

sys/dev/pci/drm/radeon/kv_dpm.h

189

int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);

sys/dev/pci/drm/radeon/kv_dpm.h

191

PPSMC_Msg msg, u32 parameter);

sys/dev/pci/drm/radeon/kv_dpm.h

192

int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/pci/drm/radeon/kv_dpm.h

193

u32 *value, u32 limit);

sys/dev/pci/drm/radeon/kv_dpm.h

197

u32 smc_start_address,

sys/dev/pci/drm/radeon/kv_dpm.h

198

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/radeon/kv_dpm.h

45

u32 offset;

sys/dev/pci/drm/radeon/kv_dpm.h

46

u32 mask;

sys/dev/pci/drm/radeon/kv_dpm.h

47

u32 shift;

sys/dev/pci/drm/radeon/kv_dpm.h

48

u32 value;

sys/dev/pci/drm/radeon/kv_dpm.h

53

u32 block_id;

sys/dev/pci/drm/radeon/kv_dpm.h

54

u32 signal_id;

sys/dev/pci/drm/radeon/kv_dpm.h

55

u32 t;

sys/dev/pci/drm/radeon/kv_dpm.h

59

u32 cntl;

sys/dev/pci/drm/radeon/kv_dpm.h

60

u32 block_mask;

sys/dev/pci/drm/radeon/kv_dpm.h

61

u32 block_shift;

sys/dev/pci/drm/radeon/kv_dpm.h

62

u32 signal_mask;

sys/dev/pci/drm/radeon/kv_dpm.h

63

u32 signal_shift;

sys/dev/pci/drm/radeon/kv_dpm.h

64

u32 t_mask;

sys/dev/pci/drm/radeon/kv_dpm.h

65

u32 t_shift;

sys/dev/pci/drm/radeon/kv_dpm.h

66

u32 enable_mask;

sys/dev/pci/drm/radeon/kv_dpm.h

67

u32 enable_shift;

sys/dev/pci/drm/radeon/kv_dpm.h

71

u32 sclk;

sys/dev/pci/drm/radeon/kv_dpm.h

83

u32 num_levels;

sys/dev/pci/drm/radeon/kv_dpm.h

92

u32 bootup_uma_clk;

sys/dev/pci/drm/radeon/kv_dpm.h

93

u32 bootup_sclk;

sys/dev/pci/drm/radeon/kv_dpm.h

94

u32 dentist_vco_freq;

sys/dev/pci/drm/radeon/kv_dpm.h

95

u32 nb_dpm_enable;

sys/dev/pci/drm/radeon/kv_dpm.h

96

u32 nbp_memory_clock[KV_NUM_NBPSTATES];

sys/dev/pci/drm/radeon/kv_dpm.h

97

u32 nbp_n_clock[KV_NUM_NBPSTATES];

sys/dev/pci/drm/radeon/kv_smc.c

118

u32 smc_start_address,

sys/dev/pci/drm/radeon/kv_smc.c

119

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/radeon/kv_smc.c

122

u32 data, original_data, addr, extra_shift, t_byte, count, mask;

sys/dev/pci/drm/radeon/kv_smc.c

29

int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id)

sys/dev/pci/drm/radeon/kv_smc.c

31

u32 i;

sys/dev/pci/drm/radeon/kv_smc.c

32

u32 tmp = 0;

sys/dev/pci/drm/radeon/kv_smc.c

53

int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask)

sys/dev/pci/drm/radeon/kv_smc.c

66

PPSMC_Msg msg, u32 parameter)

sys/dev/pci/drm/radeon/kv_smc.c

75

u32 smc_address, u32 limit)

sys/dev/pci/drm/radeon/kv_smc.c

88

int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/pci/drm/radeon/kv_smc.c

89

u32 *value, u32 limit)

sys/dev/pci/drm/radeon/ni.c

1067

u32 rb_disable_bitmap;

sys/dev/pci/drm/radeon/ni.c

1087

u32 simd_disable_bitmap;

sys/dev/pci/drm/radeon/ni.c

1283

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/ni.c

1307

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/ni.c

1367

int ring, u32 cp_int_cntl)

sys/dev/pci/drm/radeon/ni.c

1381

u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |

sys/dev/pci/drm/radeon/ni.c

1403

u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |

sys/dev/pci/drm/radeon/ni.c

1448

u32 cayman_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/ni.c

1451

u32 rptr;

sys/dev/pci/drm/radeon/ni.c

1467

u32 cayman_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/ni.c

1470

u32 wptr;

sys/dev/pci/drm/radeon/ni.c

1720

u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ni.c

1722

u32 reset_mask = 0;

sys/dev/pci/drm/radeon/ni.c

1723

u32 tmp;

sys/dev/pci/drm/radeon/ni.c

1798

static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/pci/drm/radeon/ni.c

1801

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/radeon/ni.c

1802

u32 tmp;

sys/dev/pci/drm/radeon/ni.c

1932

u32 reset_mask;

sys/dev/pci/drm/radeon/ni.c

1967

u32 reset_mask = cayman_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/ni.c

2166

(u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);

sys/dev/pci/drm/radeon/ni.c

218

static const u32 cayman_golden_registers2[] = {

sys/dev/pci/drm/radeon/ni.c

227

static const u32 cayman_golden_registers[] = {

sys/dev/pci/drm/radeon/ni.c

2506

u32 status, u32 addr)

sys/dev/pci/drm/radeon/ni.c

2508

u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;

sys/dev/pci/drm/radeon/ni.c

2509

u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

sys/dev/pci/drm/radeon/ni.c

2510

u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

sys/dev/pci/drm/radeon/ni.c

267

static const u32 dvst_golden_registers2[] = {

sys/dev/pci/drm/radeon/ni.c

2692

int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/radeon/ni.c

274

static const u32 dvst_golden_registers[] = {

sys/dev/pci/drm/radeon/ni.c

331

static const u32 scrapper_golden_registers[] = {

sys/dev/pci/drm/radeon/ni.c

443

(const u32)ARRAY_SIZE(cayman_golden_registers));

sys/dev/pci/drm/radeon/ni.c

446

(const u32)ARRAY_SIZE(cayman_golden_registers2));

sys/dev/pci/drm/radeon/ni.c

47

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/ni.c

470

(const u32)ARRAY_SIZE(dvst_golden_registers));

sys/dev/pci/drm/radeon/ni.c

473

(const u32)ARRAY_SIZE(dvst_golden_registers2));

sys/dev/pci/drm/radeon/ni.c

477

(const u32)ARRAY_SIZE(scrapper_golden_registers));

sys/dev/pci/drm/radeon/ni.c

480

(const u32)ARRAY_SIZE(dvst_golden_registers2));

sys/dev/pci/drm/radeon/ni.c

490

static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/ni.c

50

u32 r;

sys/dev/pci/drm/radeon/ni.c

522

static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/ni.c

554

static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/ni.c

586

static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/ni.c

59

void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/ni.c

621

u32 mem_type, running;

sys/dev/pci/drm/radeon/ni.c

622

u32 *io_mc_regs;

sys/dev/pci/drm/radeon/ni.c

630

io_mc_regs = (u32 *)&barts_io_mc_regs;

sys/dev/pci/drm/radeon/ni.c

635

io_mc_regs = (u32 *)&turks_io_mc_regs;

sys/dev/pci/drm/radeon/ni.c

641

io_mc_regs = (u32 *)&caicos_io_mc_regs;

sys/dev/pci/drm/radeon/ni.c

646

io_mc_regs = (u32 *)&cayman_io_mc_regs;

sys/dev/pci/drm/radeon/ni.c

69

static const u32 tn_rlc_save_restore_register_list[] = {

sys/dev/pci/drm/radeon/ni.c

836

u32 reg, u32 *val)

sys/dev/pci/drm/radeon/ni.c

856

u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;

sys/dev/pci/drm/radeon/ni.c

867

u32 gb_addr_config = 0;

sys/dev/pci/drm/radeon/ni.c

868

u32 mc_arb_ramcfg;

sys/dev/pci/drm/radeon/ni.c

869

u32 cgts_tcc_disable;

sys/dev/pci/drm/radeon/ni.c

870

u32 sx_debug_1;

sys/dev/pci/drm/radeon/ni.c

871

u32 smx_dc_ctl0;

sys/dev/pci/drm/radeon/ni.c

872

u32 cgts_sm_ctrl_reg;

sys/dev/pci/drm/radeon/ni.c

873

u32 hdp_host_path_cntl;

sys/dev/pci/drm/radeon/ni.c

874

u32 tmp;

sys/dev/pci/drm/radeon/ni.c

875

u32 disabled_rb_mask;

sys/dev/pci/drm/radeon/ni.h

32

int ring, u32 cp_int_cntl);

sys/dev/pci/drm/radeon/ni.h

34

u32 status, u32 addr);

sys/dev/pci/drm/radeon/ni.h

35

u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/ni_dma.c

103

u32 reg;

sys/dev/pci/drm/radeon/ni_dma.c

128

u32 next_rptr = ring->wptr + 4;

sys/dev/pci/drm/radeon/ni_dma.c

158

u32 rb_cntl;

sys/dev/pci/drm/radeon/ni_dma.c

189

u32 rb_cntl, dma_cntl, ib_cntl;

sys/dev/pci/drm/radeon/ni_dma.c

190

u32 rb_bufsz;

sys/dev/pci/drm/radeon/ni_dma.c

191

u32 reg_offset, wb_offset;

sys/dev/pci/drm/radeon/ni_dma.c

288

u32 reset_mask = cayman_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/ni_dma.c

289

u32 mask;

sys/dev/pci/drm/radeon/ni_dma.c

55

u32 rptr, reg;

sys/dev/pci/drm/radeon/ni_dma.c

82

u32 reg;

sys/dev/pci/drm/radeon/ni_dpm.c

1037

PPSMC_Msg msg, u32 parameter)

sys/dev/pci/drm/radeon/ni_dpm.c

1082

u32 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

1102

u32 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

1222

u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;

sys/dev/pci/drm/radeon/ni_dpm.c

1223

u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

1224

u32 reference_clock;

sys/dev/pci/drm/radeon/ni_dpm.c

1228

voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;

sys/dev/pci/drm/radeon/ni_dpm.c

1229

backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;

sys/dev/pci/drm/radeon/ni_dpm.c

1321

u32 mclk,

sys/dev/pci/drm/radeon/ni_dpm.c

1347

((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))

sys/dev/pci/drm/radeon/ni_dpm.c

1363

static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ni_dpm.c

1365

u32 xclk_period;

sys/dev/pci/drm/radeon/ni_dpm.c

1366

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/ni_dpm.c

1367

u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;

sys/dev/pci/drm/radeon/ni_dpm.c

1375

static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)

sys/dev/pci/drm/radeon/ni_dpm.c

1380

static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/ni_dpm.c

1382

u32 near_tdp_limit)

sys/dev/pci/drm/radeon/ni_dpm.c

1387

u32 power_boost_limit = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

1426

power_boost_limit = (u32)tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

1434

u32 tdp_adjustment,

sys/dev/pci/drm/radeon/ni_dpm.c

1435

u32 *tdp_limit,

sys/dev/pci/drm/radeon/ni_dpm.c

1436

u32 *near_tdp_limit)

sys/dev/pci/drm/radeon/ni_dpm.c

1438

if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)

sys/dev/pci/drm/radeon/ni_dpm.c

1460

u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);

sys/dev/pci/drm/radeon/ni_dpm.c

1461

u32 tdp_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

1462

u32 near_tdp_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

1463

u32 power_boost_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

1496

sizeof(u32) * 4, pi->sram_end);

sys/dev/pci/drm/radeon/ni_dpm.c

1505

u32 arb_freq_src, u32 arb_freq_dest)

sys/dev/pci/drm/radeon/ni_dpm.c

1507

u32 mc_arb_dram_timing;

sys/dev/pci/drm/radeon/ni_dpm.c

1508

u32 mc_arb_dram_timing2;

sys/dev/pci/drm/radeon/ni_dpm.c

1509

u32 burst_time;

sys/dev/pci/drm/radeon/ni_dpm.c

1510

u32 mc_cg_config;

sys/dev/pci/drm/radeon/ni_dpm.c

1573

u32 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

1582

tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;

sys/dev/pci/drm/radeon/ni_dpm.c

1597

u32 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

1617

u32 dram_timing;

sys/dev/pci/drm/radeon/ni_dpm.c

1618

u32 dram_timing2;

sys/dev/pci/drm/radeon/ni_dpm.c

1687

u32 reg;

sys/dev/pci/drm/radeon/ni_dpm.c

1796

u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

1797

u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.c

1798

u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

1799

u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.c

1800

u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

1801

u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.c

1802

u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/ni_dpm.c

1803

u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/ni_dpm.c

1804

u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

1805

u32 dll_cntl = ni_pi->clock_registers.dll_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

1806

u32 reg;

sys/dev/pci/drm/radeon/ni_dpm.c

1999

u32 engine_clock,

sys/dev/pci/drm/radeon/ni_dpm.c

2005

u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

2006

u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.c

2007

u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/ni_dpm.c

2008

u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/ni_dpm.c

2009

u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/ni_dpm.c

2010

u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/ni_dpm.c

2012

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ni_dpm.c

2013

u32 reference_divider;

sys/dev/pci/drm/radeon/ni_dpm.c

2014

u32 fbdiv;

sys/dev/pci/drm/radeon/ni_dpm.c

2027

fbdiv = (u32) tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

2042

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/pci/drm/radeon/ni_dpm.c

2046

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/ni_dpm.c

2047

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/radeon/ni_dpm.c

2070

u32 engine_clock,

sys/dev/pci/drm/radeon/ni_dpm.c

2096

u32 fb_div;

sys/dev/pci/drm/radeon/ni_dpm.c

2097

u32 p_div;

sys/dev/pci/drm/radeon/ni_dpm.c

2098

u32 clk_s;

sys/dev/pci/drm/radeon/ni_dpm.c

2099

u32 clk_v;

sys/dev/pci/drm/radeon/ni_dpm.c

2100

u32 sclk = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

2102

u32 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

2161

u32 engine_clock,

sys/dev/pci/drm/radeon/ni_dpm.c

2162

u32 memory_clock,

sys/dev/pci/drm/radeon/ni_dpm.c

2169

u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

2170

u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.c

2171

u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

2172

u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.c

2173

u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

2174

u32 dll_cntl = ni_pi->clock_registers.dll_cntl;

sys/dev/pci/drm/radeon/ni_dpm.c

2175

u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;

sys/dev/pci/drm/radeon/ni_dpm.c

2176

u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;

sys/dev/pci/drm/radeon/ni_dpm.c

2178

u32 ibias;

sys/dev/pci/drm/radeon/ni_dpm.c

2179

u32 dll_speed;

sys/dev/pci/drm/radeon/ni_dpm.c

2181

u32 mc_seq_misc7;

sys/dev/pci/drm/radeon/ni_dpm.c

2238

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/pci/drm/radeon/ni_dpm.c

2242

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/ni_dpm.c

2243

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/pci/drm/radeon/ni_dpm.c

2244

u32 clk_s, clk_v;

sys/dev/pci/drm/radeon/ni_dpm.c

2323

u32 tmp = RREG32(DC_STUTTER_CNTL);

sys/dev/pci/drm/radeon/ni_dpm.c

2401

u32 a_t;

sys/dev/pci/drm/radeon/ni_dpm.c

2402

u32 t_l, t_h;

sys/dev/pci/drm/radeon/ni_dpm.c

2403

u32 high_bsp;

sys/dev/pci/drm/radeon/ni_dpm.c

2462

u32 prev_sclk;

sys/dev/pci/drm/radeon/ni_dpm.c

2463

u32 max_sclk;

sys/dev/pci/drm/radeon/ni_dpm.c

2464

u32 min_sclk;

sys/dev/pci/drm/radeon/ni_dpm.c

2466

u32 tdp_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

2467

u32 near_tdp_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

2468

u32 power_boost_limit;

sys/dev/pci/drm/radeon/ni_dpm.c

2519

min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;

sys/dev/pci/drm/radeon/ni_dpm.c

253

static const u32 cayman_cgcg_cgls_default[] =

sys/dev/pci/drm/radeon/ni_dpm.c

2546

u32 sq_power_throttle;

sys/dev/pci/drm/radeon/ni_dpm.c

2547

u32 sq_power_throttle2;

sys/dev/pci/drm/radeon/ni_dpm.c

2636

u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100;

sys/dev/pci/drm/radeon/ni_dpm.c

2719

u32 temp_reg;

sys/dev/pci/drm/radeon/ni_dpm.c

2839

u32 i;

sys/dev/pci/drm/radeon/ni_dpm.c

2929

u32 i, j;

sys/dev/pci/drm/radeon/ni_dpm.c

2948

u32 num_entries, u32 valid_flag)

sys/dev/pci/drm/radeon/ni_dpm.c

2950

u32 i, j;

sys/dev/pci/drm/radeon/ni_dpm.c

2965

u32 i = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

304

#define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

3054

u32 leakage = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

3057

u32 smc_leakage, max_leakage = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

3058

u32 scaling_factor;

sys/dev/pci/drm/radeon/ni_dpm.c

306

static const u32 cayman_cgcg_cgls_disable[] =

sys/dev/pci/drm/radeon/ni_dpm.c

3102

u32 i, j, table_size;

sys/dev/pci/drm/radeon/ni_dpm.c

3103

u32 smc_leakage, max_leakage = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

3104

u32 scaling_factor;

sys/dev/pci/drm/radeon/ni_dpm.c

3145

u32 reg;

sys/dev/pci/drm/radeon/ni_dpm.c

3211

u32 reg;

sys/dev/pci/drm/radeon/ni_dpm.c

3442

u32 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

3462

u32 tmp, bif;

sys/dev/pci/drm/radeon/ni_dpm.c

359

#define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

361

static const u32 cayman_cgcg_cgls_enable[] =

sys/dev/pci/drm/radeon/ni_dpm.c

413

#define CAYMAN_CGCG_CGLS_ENABLE_LENGTH sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

415

static const u32 cayman_mgcg_default[] =

sys/dev/pci/drm/radeon/ni_dpm.c

4311

u32 current_index =

sys/dev/pci/drm/radeon/ni_dpm.c

4325

u32 ni_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ni_dpm.c

4331

u32 current_index =

sys/dev/pci/drm/radeon/ni_dpm.c

4343

u32 ni_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ni_dpm.c

4349

u32 current_index =

sys/dev/pci/drm/radeon/ni_dpm.c

4361

u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/ni_dpm.c

4372

u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/ni_dpm.c

618

#define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

620

static const u32 cayman_mgcg_disable[] =

sys/dev/pci/drm/radeon/ni_dpm.c

633

#define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

635

static const u32 cayman_mgcg_enable[] =

sys/dev/pci/drm/radeon/ni_dpm.c

649

#define CAYMAN_MGCG_ENABLE_LENGTH sizeof(cayman_mgcg_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

653

static const u32 cayman_sysls_default[] =

sys/dev/pci/drm/radeon/ni_dpm.c

674

#define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

676

static const u32 cayman_sysls_disable[] =

sys/dev/pci/drm/radeon/ni_dpm.c

699

#define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

701

static const u32 cayman_sysls_enable[] =

sys/dev/pci/drm/radeon/ni_dpm.c

722

#define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32))

sys/dev/pci/drm/radeon/ni_dpm.c

742

u32 ileakage,

sys/dev/pci/drm/radeon/ni_dpm.c

743

u32 *leakage)

sys/dev/pci/drm/radeon/ni_dpm.c

765

u32 i_leakage,

sys/dev/pci/drm/radeon/ni_dpm.c

766

u32 *leakage)

sys/dev/pci/drm/radeon/ni_dpm.c

774

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/pci/drm/radeon/ni_dpm.c

776

u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

sys/dev/pci/drm/radeon/ni_dpm.c

791

u32 mclk;

sys/dev/pci/drm/radeon/ni_dpm.c

906

u32 count;

sys/dev/pci/drm/radeon/ni_dpm.c

907

const u32 *ps = NULL;

sys/dev/pci/drm/radeon/ni_dpm.c

909

ps = (const u32 *)&cayman_cgcg_cgls_default;

sys/dev/pci/drm/radeon/ni_dpm.c

918

u32 count;

sys/dev/pci/drm/radeon/ni_dpm.c

919

const u32 *ps = NULL;

sys/dev/pci/drm/radeon/ni_dpm.c

922

ps = (const u32 *)&cayman_cgcg_cgls_enable;

sys/dev/pci/drm/radeon/ni_dpm.c

925

ps = (const u32 *)&cayman_cgcg_cgls_disable;

sys/dev/pci/drm/radeon/ni_dpm.c

934

u32 count;

sys/dev/pci/drm/radeon/ni_dpm.c

935

const u32 *ps = NULL;

sys/dev/pci/drm/radeon/ni_dpm.c

937

ps = (const u32 *)&cayman_mgcg_default;

sys/dev/pci/drm/radeon/ni_dpm.c

946

u32 count;

sys/dev/pci/drm/radeon/ni_dpm.c

947

const u32 *ps = NULL;

sys/dev/pci/drm/radeon/ni_dpm.c

950

ps = (const u32 *)&cayman_mgcg_enable;

sys/dev/pci/drm/radeon/ni_dpm.c

953

ps = (const u32 *)&cayman_mgcg_disable;

sys/dev/pci/drm/radeon/ni_dpm.c

962

u32 count;

sys/dev/pci/drm/radeon/ni_dpm.c

963

const u32 *ps = NULL;

sys/dev/pci/drm/radeon/ni_dpm.c

965

ps = (const u32 *)&cayman_sysls_default;

sys/dev/pci/drm/radeon/ni_dpm.c

974

u32 count;

sys/dev/pci/drm/radeon/ni_dpm.c

975

const u32 *ps = NULL;

sys/dev/pci/drm/radeon/ni_dpm.c

978

ps = (const u32 *)&cayman_sysls_enable;

sys/dev/pci/drm/radeon/ni_dpm.c

981

ps = (const u32 *)&cayman_sysls_disable;

sys/dev/pci/drm/radeon/ni_dpm.c

993

u32 i;

sys/dev/pci/drm/radeon/ni_dpm.h

101

u32 weight_tcp_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

102

u32 weight_tcp_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

103

u32 weight_ta_sig;

sys/dev/pci/drm/radeon/ni_dpm.h

104

u32 weight_tcc_en0;

sys/dev/pci/drm/radeon/ni_dpm.h

105

u32 weight_tcc_en1;

sys/dev/pci/drm/radeon/ni_dpm.h

106

u32 weight_tcc_en2;

sys/dev/pci/drm/radeon/ni_dpm.h

107

u32 weight_cb_en0;

sys/dev/pci/drm/radeon/ni_dpm.h

108

u32 weight_cb_en1;

sys/dev/pci/drm/radeon/ni_dpm.h

109

u32 weight_cb_en2;

sys/dev/pci/drm/radeon/ni_dpm.h

110

u32 weight_cb_en3;

sys/dev/pci/drm/radeon/ni_dpm.h

111

u32 weight_db_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

112

u32 weight_db_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

113

u32 weight_db_sig2;

sys/dev/pci/drm/radeon/ni_dpm.h

114

u32 weight_db_sig3;

sys/dev/pci/drm/radeon/ni_dpm.h

115

u32 weight_sxm_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

116

u32 weight_sxm_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

117

u32 weight_sxm_sig2;

sys/dev/pci/drm/radeon/ni_dpm.h

118

u32 weight_sxs_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

119

u32 weight_sxs_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

120

u32 weight_xbr_0;

sys/dev/pci/drm/radeon/ni_dpm.h

121

u32 weight_xbr_1;

sys/dev/pci/drm/radeon/ni_dpm.h

122

u32 weight_xbr_2;

sys/dev/pci/drm/radeon/ni_dpm.h

123

u32 weight_spi_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

124

u32 weight_spi_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

125

u32 weight_spi_sig2;

sys/dev/pci/drm/radeon/ni_dpm.h

126

u32 weight_spi_sig3;

sys/dev/pci/drm/radeon/ni_dpm.h

127

u32 weight_spi_sig4;

sys/dev/pci/drm/radeon/ni_dpm.h

128

u32 weight_spi_sig5;

sys/dev/pci/drm/radeon/ni_dpm.h

129

u32 weight_lds_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

130

u32 weight_lds_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

131

u32 weight_sc;

sys/dev/pci/drm/radeon/ni_dpm.h

132

u32 weight_bif;

sys/dev/pci/drm/radeon/ni_dpm.h

133

u32 weight_cp;

sys/dev/pci/drm/radeon/ni_dpm.h

134

u32 weight_pa_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

135

u32 weight_pa_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

136

u32 weight_vgt_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

137

u32 weight_vgt_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

138

u32 weight_vgt_sig2;

sys/dev/pci/drm/radeon/ni_dpm.h

139

u32 weight_dc_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

140

u32 weight_dc_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

141

u32 weight_dc_sig2;

sys/dev/pci/drm/radeon/ni_dpm.h

142

u32 weight_dc_sig3;

sys/dev/pci/drm/radeon/ni_dpm.h

143

u32 weight_uvd_sig0;

sys/dev/pci/drm/radeon/ni_dpm.h

144

u32 weight_uvd_sig1;

sys/dev/pci/drm/radeon/ni_dpm.h

145

u32 weight_spare0;

sys/dev/pci/drm/radeon/ni_dpm.h

146

u32 weight_spare1;

sys/dev/pci/drm/radeon/ni_dpm.h

147

u32 weight_sq_vsp;

sys/dev/pci/drm/radeon/ni_dpm.h

148

u32 weight_sq_vsp0;

sys/dev/pci/drm/radeon/ni_dpm.h

149

u32 weight_sq_gpr;

sys/dev/pci/drm/radeon/ni_dpm.h

150

u32 ovr_mode_spare_0;

sys/dev/pci/drm/radeon/ni_dpm.h

151

u32 ovr_val_spare_0;

sys/dev/pci/drm/radeon/ni_dpm.h

152

u32 ovr_mode_spare_1;

sys/dev/pci/drm/radeon/ni_dpm.h

153

u32 ovr_val_spare_1;

sys/dev/pci/drm/radeon/ni_dpm.h

154

u32 vsp;

sys/dev/pci/drm/radeon/ni_dpm.h

155

u32 vsp0;

sys/dev/pci/drm/radeon/ni_dpm.h

156

u32 gpr;

sys/dev/pci/drm/radeon/ni_dpm.h

159

u32 tid_cnt;

sys/dev/pci/drm/radeon/ni_dpm.h

160

u32 tid_unit;

sys/dev/pci/drm/radeon/ni_dpm.h

161

u32 l2_lta_window_size;

sys/dev/pci/drm/radeon/ni_dpm.h

162

u32 lts_truncate;

sys/dev/pci/drm/radeon/ni_dpm.h

163

u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/pci/drm/radeon/ni_dpm.h

164

u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];

sys/dev/pci/drm/radeon/ni_dpm.h

179

u32 mclk_rtt_mode_threshold;

sys/dev/pci/drm/radeon/ni_dpm.h

197

u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/pci/drm/radeon/ni_dpm.h

231

u32 arb_freq_src, u32 arb_freq_dest);

sys/dev/pci/drm/radeon/ni_dpm.h

31

u32 cg_spll_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.h

32

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.h

33

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/ni_dpm.h

34

u32 cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/ni_dpm.h

35

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/ni_dpm.h

36

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/ni_dpm.h

37

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/ni_dpm.h

38

u32 dll_cntl;

sys/dev/pci/drm/radeon/ni_dpm.h

39

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.h

40

u32 mpll_ad_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.h

41

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/ni_dpm.h

42

u32 mpll_dq_func_cntl_2;

sys/dev/pci/drm/radeon/ni_dpm.h

43

u32 mpll_ss1;

sys/dev/pci/drm/radeon/ni_dpm.h

44

u32 mpll_ss2;

sys/dev/pci/drm/radeon/ni_dpm.h

48

u32 mclk_max;

sys/dev/pci/drm/radeon/ni_dpm.h

49

u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/ni_dpm.h

75

u32 at;

sys/dev/pci/drm/radeon/ni_dpm.h

76

u32 bt;

sys/dev/pci/drm/radeon/ni_dpm.h

77

u32 av;

sys/dev/pci/drm/radeon/ni_dpm.h

78

u32 bv;

sys/dev/pci/drm/radeon/ni_dpm.h

81

u32 t_ref;

sys/dev/pci/drm/radeon/ni_dpm.h

86

u32 i_leakage;

sys/dev/pci/drm/radeon/ni_dpm.h

88

u32 pwr_const;

sys/dev/pci/drm/radeon/ni_dpm.h

89

u32 dc_cac_value;

sys/dev/pci/drm/radeon/ni_dpm.h

90

u32 bif_cac_value;

sys/dev/pci/drm/radeon/ni_dpm.h

91

u32 lkge_pwr;

sys/dev/pci/drm/radeon/r100.c

1093

u32 r100_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r100.c

1096

u32 rptr;

sys/dev/pci/drm/radeon/r100.c

1106

u32 r100_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r100.c

1294

u32 tile_flags = 0;

sys/dev/pci/drm/radeon/r100.c

1295

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

1297

u32 value;

sys/dev/pci/drm/radeon/r100.c

1309

tmp += (((u32)reloc->gpu_offset) >> 10);

sys/dev/pci/drm/radeon/r100.c

1339

u32 idx_value;

sys/dev/pci/drm/radeon/r100.c

1360

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1372

ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1386

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1590

u32 tile_flags = 0;

sys/dev/pci/drm/radeon/r100.c

1591

u32 idx_value;

sys/dev/pci/drm/radeon/r100.c

1627

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1640

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1661

ib[idx] = tmp + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1663

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1681

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

169

u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;

sys/dev/pci/drm/radeon/r100.c

1699

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1717

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1805

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1926

u32 value;

sys/dev/pci/drm/radeon/r100.c

1964

ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1978

ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

2550

u32 rbbm_status;

sys/dev/pci/drm/radeon/r100.c

2571

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

2589

u32 status, tmp;

sys/dev/pci/drm/radeon/r100.c

2645

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

2687

u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);

sys/dev/pci/drm/radeon/r100.c

2688

u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

sys/dev/pci/drm/radeon/r100.c

2689

u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);

sys/dev/pci/drm/radeon/r100.c

2763

static u32 r100_get_accessible_vram(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r100.c

2765

u32 aper_size;

sys/dev/pci/drm/radeon/r100.c

3239

u32 lb_size = 8192;

sys/dev/pci/drm/radeon/r100.c

3568

u32 grph2_cntl;

sys/dev/pci/drm/radeon/r100.c

367

u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;

sys/dev/pci/drm/radeon/r100.c

3715

u32 next_rptr = ring->wptr + 2 + 3;

sys/dev/pci/drm/radeon/r100.c

3850

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

3888

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

4023

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

4144

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/r100.c

4146

u32 val;

sys/dev/pci/drm/radeon/r100.c

4166

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/r100.c

465

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

496

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

571

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

712

u32 *gtt = rdev->gart.ptr;

sys/dev/pci/drm/radeon/r100.c

759

u32 tmp;

sys/dev/pci/drm/radeon/r100.c

845

u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)

sys/dev/pci/drm/radeon/r100.c

95

u32 vline1, vline2;

sys/dev/pci/drm/radeon/r100.c

981

u32 tmp;

sys/dev/pci/drm/radeon/r200.c

156

u32 tile_flags = 0;

sys/dev/pci/drm/radeon/r200.c

157

u32 idx_value;

sys/dev/pci/drm/radeon/r200.c

191

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r200.c

204

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r200.c

228

ib[idx] = tmp + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r200.c

230

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r200.c

274

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r200.c

368

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

1087

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

1132

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

1198

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

1359

u32 tmp;

sys/dev/pci/drm/radeon/r300.c

193

u32 tmp;

sys/dev/pci/drm/radeon/r300.c

418

u32 status, tmp;

sys/dev/pci/drm/radeon/r300.c

478

u32 tmp;

sys/dev/pci/drm/radeon/r300.c

562

u32 link_width_cntl;

sys/dev/pci/drm/radeon/r300.c

637

u32 idx_value;

sys/dev/pci/drm/radeon/r300.c

675

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

688

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

717

((idx_value & ~31) + (u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

726

tmp = idx_value + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r420.c

165

u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/r420.c

168

u32 r;

sys/dev/pci/drm/radeon/r420.c

177

void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/r420.c

196

u32 sclk_cntl;

sys/dev/pci/drm/radeon/r600.c

103

static const u32 crtc_offsets[2] = {

sys/dev/pci/drm/radeon/r600.c

1077

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

1130

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

1174

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/r600.c

1188

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

120

u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/r600.c

123

u32 r;

sys/dev/pci/drm/radeon/r600.c

1230

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

1265

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

1305

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

132

void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/r600.c

142

u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/r600.c

1435

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

145

u32 r;

sys/dev/pci/drm/radeon/r600.c

154

void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/r600.c

1556

u32 tmp = RREG32(R600_BIOS_3_SCRATCH);

sys/dev/pci/drm/radeon/r600.c

1588

u32 crtc_hung = 0;

sys/dev/pci/drm/radeon/r600.c

1589

u32 crtc_status[2];

sys/dev/pci/drm/radeon/r600.c

1590

u32 i, j, tmp;

sys/dev/pci/drm/radeon/r600.c

1615

u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r600.c

1617

u32 reset_mask = 0;

sys/dev/pci/drm/radeon/r600.c

1618

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

1684

static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/pci/drm/radeon/r600.c

1687

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/radeon/r600.c

1688

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

175

u32 reg, u32 *val)

sys/dev/pci/drm/radeon/r600.c

1823

u32 tmp, i;

sys/dev/pci/drm/radeon/r600.c

1883

u32 reset_mask;

sys/dev/pci/drm/radeon/r600.c

1923

u32 reset_mask = r600_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/r600.c

1934

u32 r6xx_remap_render_backend(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r600.c

1935

u32 tiling_pipe_num,

sys/dev/pci/drm/radeon/r600.c

1936

u32 max_rb_num,

sys/dev/pci/drm/radeon/r600.c

1937

u32 total_max_rb_num,

sys/dev/pci/drm/radeon/r600.c

1938

u32 disabled_rb_mask)

sys/dev/pci/drm/radeon/r600.c

1940

u32 rendering_pipe_num, rb_num_width, req_rb_num;

sys/dev/pci/drm/radeon/r600.c

1941

u32 pipe_rb_ratio, pipe_rb_remain, tmp;

sys/dev/pci/drm/radeon/r600.c

1942

u32 data = 0, mask = 1 << (max_rb_num - 1);

sys/dev/pci/drm/radeon/r600.c

198

u32 r600_get_xclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r600.c

1991

u32 tiling_config;

sys/dev/pci/drm/radeon/r600.c

1992

u32 ramcfg;

sys/dev/pci/drm/radeon/r600.c

1993

u32 cc_gc_shader_pipe_config;

sys/dev/pci/drm/radeon/r600.c

1994

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

1996

u32 sq_config;

sys/dev/pci/drm/radeon/r600.c

1997

u32 sq_gpr_resource_mgmt_1 = 0;

sys/dev/pci/drm/radeon/r600.c

1998

u32 sq_gpr_resource_mgmt_2 = 0;

sys/dev/pci/drm/radeon/r600.c

1999

u32 sq_thread_resource_mgmt = 0;

sys/dev/pci/drm/radeon/r600.c

2000

u32 sq_stack_resource_mgmt_1 = 0;

sys/dev/pci/drm/radeon/r600.c

2001

u32 sq_stack_resource_mgmt_2 = 0;

sys/dev/pci/drm/radeon/r600.c

2002

u32 disabled_rb_mask;

sys/dev/pci/drm/radeon/r600.c

203

int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/pci/drm/radeon/r600.c

2395

u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/pci/drm/radeon/r600.c

2398

u32 r;

sys/dev/pci/drm/radeon/r600.c

2408

void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/pci/drm/radeon/r600.c

2618

u32 r600_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r600.c

2621

u32 rptr;

sys/dev/pci/drm/radeon/r600.c

2631

u32 r600_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r600.c

2719

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

2720

u32 rb_bufsz;

sys/dev/pci/drm/radeon/r600.c

2782

u32 rb_bufsz;

sys/dev/pci/drm/radeon/r600.c

2871

u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |

sys/dev/pci/drm/radeon/r600.c

2973

u32 size_in_bytes, cur_size_in_bytes, tmp;

sys/dev/pci/drm/radeon/r600.c

304

u32 tmp = 0;

sys/dev/pci/drm/radeon/r600.c

3369

u32 next_rptr;

sys/dev/pci/drm/radeon/r600.c

3468

u32 rb_bufsz;

sys/dev/pci/drm/radeon/r600.c

352

u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>

sys/dev/pci/drm/radeon/r600.c

3553

u32 i;

sys/dev/pci/drm/radeon/r600.c

3592

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/radeon/r600.c

3593

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/radeon/r600.c

3604

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/radeon/r600.c

3605

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/radeon/r600.c

3620

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

3675

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/radeon/r600.c

3763

u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;

sys/dev/pci/drm/radeon/r600.c

3764

u32 mode_int = 0;

sys/dev/pci/drm/radeon/r600.c

3765

u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;

sys/dev/pci/drm/radeon/r600.c

3766

u32 grbm_int_cntl = 0;

sys/dev/pci/drm/radeon/r600.c

3767

u32 hdmi0, hdmi1;

sys/dev/pci/drm/radeon/r600.c

3768

u32 dma_cntl;

sys/dev/pci/drm/radeon/r600.c

3769

u32 thermal_int = 0;

sys/dev/pci/drm/radeon/r600.c

3914

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

4037

static u32 r600_get_ih_wptr(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r600.c

4039

u32 wptr, tmp;

sys/dev/pci/drm/radeon/r600.c

4094

u32 wptr;

sys/dev/pci/drm/radeon/r600.c

4095

u32 rptr;

sys/dev/pci/drm/radeon/r600.c

4096

u32 src_id, src_data;

sys/dev/pci/drm/radeon/r600.c

4097

u32 ring_index;

sys/dev/pci/drm/radeon/r600.c

4399

u32 link_width_cntl, mask;

sys/dev/pci/drm/radeon/r600.c

4452

u32 link_width_cntl;

sys/dev/pci/drm/radeon/r600.c

4489

u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;

sys/dev/pci/drm/radeon/r600.c

862

u32 tmp;

sys/dev/pci/drm/radeon/r600.c

969

u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);

sys/dev/pci/drm/radeon/r600.h

38

u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/r600.h

44

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/r600.h

45

void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/pci/drm/radeon/r600.h

48

void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/r600.h

52

void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/r600_cs.c

1025

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1087

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1108

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1217

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1248

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1284

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1298

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1311

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1380

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1389

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1474

static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,

sys/dev/pci/drm/radeon/r600_cs.c

1479

u32 tiling_flags)

sys/dev/pci/drm/radeon/r600_cs.c

1482

u32 dim, nfaces, llevel, blevel, w0, h0, d0;

sys/dev/pci/drm/radeon/r600_cs.c

1483

u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;

sys/dev/pci/drm/radeon/r600_cs.c

1484

u32 height_align, pitch, pitch_align, depth_align;

sys/dev/pci/drm/radeon/r600_cs.c

1485

u32 barray, larray;

sys/dev/pci/drm/radeon/r600_cs.c

1488

u32 format;

sys/dev/pci/drm/radeon/r600_cs.c

1615

static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/pci/drm/radeon/r600_cs.c

1617

u32 m, i;

sys/dev/pci/drm/radeon/r600_cs.c

1636

volatile u32 *ib;

sys/dev/pci/drm/radeon/r600_cs.c

1641

u32 idx_value;

sys/dev/pci/drm/radeon/r600_cs.c

177

bool r600_fmt_is_valid_color(u32 format)

sys/dev/pci/drm/radeon/r600_cs.c

1784

u32 command, size;

sys/dev/pci/drm/radeon/r600_cs.c

1867

ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

188

bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)

sys/dev/pci/drm/radeon/r600_cs.c

1960

u32 size, offset, base_offset, mip_offset;

sys/dev/pci/drm/radeon/r600_cs.c

1970

base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

1984

mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

202

int r600_fmt_get_blocksize(u32 format)

sys/dev/pci/drm/radeon/r600_cs.c

210

int r600_fmt_get_nblocksx(u32 format, u32 w)

sys/dev/pci/drm/radeon/r600_cs.c

2126

ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/pci/drm/radeon/r600_cs.c

224

int r600_fmt_get_nblocksy(u32 format, u32 h)

sys/dev/pci/drm/radeon/r600_cs.c

2389

u32 header, cmd, count, tiled;

sys/dev/pci/drm/radeon/r600_cs.c

2390

volatile u32 *ib = p->ib.ptr;

sys/dev/pci/drm/radeon/r600_cs.c

2391

u32 idx, idx_value;

sys/dev/pci/drm/radeon/r600_cs.c

240

u32 group_size;

sys/dev/pci/drm/radeon/r600_cs.c

241

u32 nbanks;

sys/dev/pci/drm/radeon/r600_cs.c

2418

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/r600_cs.c

242

u32 npipes;

sys/dev/pci/drm/radeon/r600_cs.c

2424

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

243

u32 nsamples;

sys/dev/pci/drm/radeon/r600_cs.c

244

u32 blocksize;

sys/dev/pci/drm/radeon/r600_cs.c

2452

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/r600_cs.c

2456

ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

2462

ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

2467

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/pci/drm/radeon/r600_cs.c

2477

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

2478

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

2488

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

2489

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

249

u32 *pitch_align,

sys/dev/pci/drm/radeon/r600_cs.c

250

u32 *height_align,

sys/dev/pci/drm/radeon/r600_cs.c

251

u32 *depth_align,

sys/dev/pci/drm/radeon/r600_cs.c

2523

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/pci/drm/radeon/r600_cs.c

254

u32 tile_width = 8;

sys/dev/pci/drm/radeon/r600_cs.c

255

u32 tile_height = 8;

sys/dev/pci/drm/radeon/r600_cs.c

256

u32 macro_tile_width = values->nbanks;

sys/dev/pci/drm/radeon/r600_cs.c

257

u32 macro_tile_height = values->npipes;

sys/dev/pci/drm/radeon/r600_cs.c

258

u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;

sys/dev/pci/drm/radeon/r600_cs.c

259

u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;

sys/dev/pci/drm/radeon/r600_cs.c

270

*pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));

sys/dev/pci/drm/radeon/r600_cs.c

276

*pitch_align = max((u32)tile_width,

sys/dev/pci/drm/radeon/r600_cs.c

277

(u32)(values->group_size /

sys/dev/pci/drm/radeon/r600_cs.c

284

*pitch_align = max((u32)macro_tile_width * tile_width,

sys/dev/pci/drm/radeon/r600_cs.c

285

(u32)((values->group_size * values->nbanks) /

sys/dev/pci/drm/radeon/r600_cs.c

352

u32 slice_tile_max, tmp;

sys/dev/pci/drm/radeon/r600_cs.c

353

u32 height, height_align, pitch, pitch_align, depth_align;

sys/dev/pci/drm/radeon/r600_cs.c

356

volatile u32 *ib = p->ib.ptr;

sys/dev/pci/drm/radeon/r600_cs.c

358

u32 format;

sys/dev/pci/drm/radeon/r600_cs.c

40

u32 group_size;

sys/dev/pci/drm/radeon/r600_cs.c

41

u32 nbanks;

sys/dev/pci/drm/radeon/r600_cs.c

42

u32 npipes;

sys/dev/pci/drm/radeon/r600_cs.c

44

u32 sq_config;

sys/dev/pci/drm/radeon/r600_cs.c

45

u32 log_nsamples;

sys/dev/pci/drm/radeon/r600_cs.c

46

u32 nsamples;

sys/dev/pci/drm/radeon/r600_cs.c

47

u32 cb_color_base_last[8];

sys/dev/pci/drm/radeon/r600_cs.c

520

u32 nviews, bpe, ntiles, slice_tile_max, tmp;

sys/dev/pci/drm/radeon/r600_cs.c

521

u32 height_align, pitch_align, depth_align;

sys/dev/pci/drm/radeon/r600_cs.c

522

u32 pitch = 8192;

sys/dev/pci/drm/radeon/r600_cs.c

523

u32 height = 8192;

sys/dev/pci/drm/radeon/r600_cs.c

527

volatile u32 *ib = p->ib.ptr;

sys/dev/pci/drm/radeon/r600_cs.c

55

u32 cb_color_mask[8];

sys/dev/pci/drm/radeon/r600_cs.c

56

u32 cb_color_info[8];

sys/dev/pci/drm/radeon/r600_cs.c

57

u32 cb_color_view[8];

sys/dev/pci/drm/radeon/r600_cs.c

58

u32 cb_color_size_idx[8]; /* unused */

sys/dev/pci/drm/radeon/r600_cs.c

59

u32 cb_target_mask;

sys/dev/pci/drm/radeon/r600_cs.c

60

u32 cb_shader_mask; /* unused */

sys/dev/pci/drm/radeon/r600_cs.c

62

u32 cb_color_size[8];

sys/dev/pci/drm/radeon/r600_cs.c

63

u32 vgt_strmout_en;

sys/dev/pci/drm/radeon/r600_cs.c

64

u32 vgt_strmout_buffer_en;

sys/dev/pci/drm/radeon/r600_cs.c

67

u32 vgt_strmout_bo_offset[4];

sys/dev/pci/drm/radeon/r600_cs.c

68

u32 vgt_strmout_size[4];

sys/dev/pci/drm/radeon/r600_cs.c

69

u32 db_depth_control;

sys/dev/pci/drm/radeon/r600_cs.c

70

u32 db_depth_info;

sys/dev/pci/drm/radeon/r600_cs.c

71

u32 db_depth_size_idx;

sys/dev/pci/drm/radeon/r600_cs.c

711

u32 tmp;

sys/dev/pci/drm/radeon/r600_cs.c

72

u32 db_depth_view;

sys/dev/pci/drm/radeon/r600_cs.c

73

u32 db_depth_size;

sys/dev/pci/drm/radeon/r600_cs.c

74

u32 db_offset;

sys/dev/pci/drm/radeon/r600_cs.c

755

u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);

sys/dev/pci/drm/radeon/r600_cs.c

83

u32 htile_surface;

sys/dev/pci/drm/radeon/r600_cs.c

971

static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/pci/drm/radeon/r600_cs.c

975

u32 m, i, tmp, *ib;

sys/dev/pci/drm/radeon/r600_dma.c

100

u32 rb_cntl = RREG32(DMA_RB_CNTL);

sys/dev/pci/drm/radeon/r600_dma.c

122

u32 rb_cntl, dma_cntl, ib_cntl;

sys/dev/pci/drm/radeon/r600_dma.c

123

u32 rb_bufsz;

sys/dev/pci/drm/radeon/r600_dma.c

209

u32 reset_mask = r600_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/r600_dma.c

235

u32 tmp;

sys/dev/pci/drm/radeon/r600_dma.c

318

u32 s = emit_wait ? 0 : 1;

sys/dev/pci/drm/radeon/r600_dma.c

342

u32 tmp = 0;

sys/dev/pci/drm/radeon/r600_dma.c

409

u32 next_rptr = ring->wptr + 4;

sys/dev/pci/drm/radeon/r600_dma.c

452

u32 size_in_dw, cur_size_in_dw;

sys/dev/pci/drm/radeon/r600_dma.c

53

u32 rptr;

sys/dev/pci/drm/radeon/r600_dpm.c

1036

u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table);

sys/dev/pci/drm/radeon/r600_dpm.c

1089

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1143

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1175

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1233

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

129

void r600_dpm_print_cap_info(u32 caps)

sys/dev/pci/drm/radeon/r600_dpm.c

1315

u32 sys_mask,

sys/dev/pci/drm/radeon/r600_dpm.c

1360

u8 r600_encode_pci_lane_width(u32 lanes)

sys/dev/pci/drm/radeon/r600_dpm.c

154

u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r600_dpm.c

159

u32 vblank_in_pixels;

sys/dev/pci/drm/radeon/r600_dpm.c

160

u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */

sys/dev/pci/drm/radeon/r600_dpm.c

181

u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r600_dpm.c

186

u32 vrefresh = 0;

sys/dev/pci/drm/radeon/r600_dpm.c

200

void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/pci/drm/radeon/r600_dpm.c

201

u32 *p, u32 *u)

sys/dev/pci/drm/radeon/r600_dpm.c

203

u32 b_c = 0;

sys/dev/pci/drm/radeon/r600_dpm.c

204

u32 i_c;

sys/dev/pci/drm/radeon/r600_dpm.c

205

u32 tmp;

sys/dev/pci/drm/radeon/r600_dpm.c

219

int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)

sys/dev/pci/drm/radeon/r600_dpm.c

221

u32 k, a, ah, al;

sys/dev/pci/drm/radeon/r600_dpm.c

222

u32 t1;

sys/dev/pci/drm/radeon/r600_dpm.c

31

const u32 r600_utc[R600_PM_NUMBER_OF_TC] = {

sys/dev/pci/drm/radeon/r600_dpm.c

336

void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)

sys/dev/pci/drm/radeon/r600_dpm.c

342

u32 l_to_m, u32 m_to_h,

sys/dev/pci/drm/radeon/r600_dpm.c

343

u32 h_to_m, u32 m_to_l)

sys/dev/pci/drm/radeon/r600_dpm.c

350

u32 index, u32 u_t, u32 d_t)

sys/dev/pci/drm/radeon/r600_dpm.c

368

void r600_set_vrc(struct radeon_device *rdev, u32 vrv)

sys/dev/pci/drm/radeon/r600_dpm.c

373

void r600_set_tpu(struct radeon_device *rdev, u32 u)

sys/dev/pci/drm/radeon/r600_dpm.c

378

void r600_set_tpc(struct radeon_device *rdev, u32 c)

sys/dev/pci/drm/radeon/r600_dpm.c

383

void r600_set_sstu(struct radeon_device *rdev, u32 u)

sys/dev/pci/drm/radeon/r600_dpm.c

388

void r600_set_sst(struct radeon_device *rdev, u32 t)

sys/dev/pci/drm/radeon/r600_dpm.c

393

void r600_set_git(struct radeon_device *rdev, u32 t)

sys/dev/pci/drm/radeon/r600_dpm.c

398

void r600_set_fctu(struct radeon_device *rdev, u32 u)

sys/dev/pci/drm/radeon/r600_dpm.c

403

void r600_set_fct(struct radeon_device *rdev, u32 t)

sys/dev/pci/drm/radeon/r600_dpm.c

408

void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)

sys/dev/pci/drm/radeon/r600_dpm.c

413

void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)

sys/dev/pci/drm/radeon/r600_dpm.c

418

void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)

sys/dev/pci/drm/radeon/r600_dpm.c

423

void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)

sys/dev/pci/drm/radeon/r600_dpm.c

428

void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)

sys/dev/pci/drm/radeon/r600_dpm.c

433

void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)

sys/dev/pci/drm/radeon/r600_dpm.c

438

void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)

sys/dev/pci/drm/radeon/r600_dpm.c

444

u32 index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

455

u32 index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

466

u32 index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

477

u32 index, u32 divider)

sys/dev/pci/drm/radeon/r600_dpm.c

484

u32 index, u32 divider)

sys/dev/pci/drm/radeon/r600_dpm.c

49

const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = {

sys/dev/pci/drm/radeon/r600_dpm.c

491

u32 index, u32 divider)

sys/dev/pci/drm/radeon/r600_dpm.c

498

u32 index, u32 step_time)

sys/dev/pci/drm/radeon/r600_dpm.c

504

void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)

sys/dev/pci/drm/radeon/r600_dpm.c

509

void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)

sys/dev/pci/drm/radeon/r600_dpm.c

514

void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)

sys/dev/pci/drm/radeon/r600_dpm.c

530

u32 tmp, mask;

sys/dev/pci/drm/radeon/r600_dpm.c

531

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

544

u32 gpio;

sys/dev/pci/drm/radeon/r600_dpm.c

562

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

573

enum r600_power_level index, u32 voltage_index)

sys/dev/pci/drm/radeon/r600_dpm.c

575

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

582

enum r600_power_level index, u32 mem_clock_index)

sys/dev/pci/drm/radeon/r600_dpm.c

584

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

591

enum r600_power_level index, u32 eng_clock_index)

sys/dev/pci/drm/radeon/r600_dpm.c

593

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

603

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

604

u32 tmp = 0;

sys/dev/pci/drm/radeon/r600_dpm.c

614

u32 ix = 3 - (3 & index);

sys/dev/pci/drm/radeon/r600_dpm.c

615

u32 tmp = 0;

sys/dev/pci/drm/radeon/r600_dpm.c

624

u32 tmp;

sys/dev/pci/drm/radeon/r600_dpm.c

633

u32 tmp;

sys/dev/pci/drm/radeon/r600_dpm.c

67

void r600_dpm_print_class_info(u32 class, u32 class2)

sys/dev/pci/drm/radeon/r600_dpm.c

722

bool r600_is_uvd_state(u32 class, u32 class2)

sys/dev/pci/drm/radeon/r600_dpm.h

129

extern const u32 r600_utc[R600_PM_NUMBER_OF_TC];

sys/dev/pci/drm/radeon/r600_dpm.h

130

extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC];

sys/dev/pci/drm/radeon/r600_dpm.h

132

void r600_dpm_print_class_info(u32 class, u32 class2);

sys/dev/pci/drm/radeon/r600_dpm.h

133

void r600_dpm_print_cap_info(u32 caps);

sys/dev/pci/drm/radeon/r600_dpm.h

136

u32 r600_dpm_get_vblank_time(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/r600_dpm.h

137

u32 r600_dpm_get_vrefresh(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/r600_dpm.h

138

bool r600_is_uvd_state(u32 class, u32 class2);

sys/dev/pci/drm/radeon/r600_dpm.h

139

void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/pci/drm/radeon/r600_dpm.h

140

u32 *p, u32 *u);

sys/dev/pci/drm/radeon/r600_dpm.h

141

int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);

sys/dev/pci/drm/radeon/r600_dpm.h

152

void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p);

sys/dev/pci/drm/radeon/r600_dpm.h

154

u32 l_to_m, u32 m_to_h,

sys/dev/pci/drm/radeon/r600_dpm.h

155

u32 h_to_m, u32 m_to_l);

sys/dev/pci/drm/radeon/r600_dpm.h

156

void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t);

sys/dev/pci/drm/radeon/r600_dpm.h

158

void r600_set_vrc(struct radeon_device *rdev, u32 vrv);

sys/dev/pci/drm/radeon/r600_dpm.h

159

void r600_set_tpu(struct radeon_device *rdev, u32 u);

sys/dev/pci/drm/radeon/r600_dpm.h

160

void r600_set_tpc(struct radeon_device *rdev, u32 c);

sys/dev/pci/drm/radeon/r600_dpm.h

161

void r600_set_sstu(struct radeon_device *rdev, u32 u);

sys/dev/pci/drm/radeon/r600_dpm.h

162

void r600_set_sst(struct radeon_device *rdev, u32 t);

sys/dev/pci/drm/radeon/r600_dpm.h

163

void r600_set_git(struct radeon_device *rdev, u32 t);

sys/dev/pci/drm/radeon/r600_dpm.h

164

void r600_set_fctu(struct radeon_device *rdev, u32 u);

sys/dev/pci/drm/radeon/r600_dpm.h

165

void r600_set_fct(struct radeon_device *rdev, u32 t);

sys/dev/pci/drm/radeon/r600_dpm.h

166

void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p);

sys/dev/pci/drm/radeon/r600_dpm.h

167

void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s);

sys/dev/pci/drm/radeon/r600_dpm.h

168

void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u);

sys/dev/pci/drm/radeon/r600_dpm.h

169

void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p);

sys/dev/pci/drm/radeon/r600_dpm.h

170

void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s);

sys/dev/pci/drm/radeon/r600_dpm.h

171

void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time);

sys/dev/pci/drm/radeon/r600_dpm.h

172

void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time);

sys/dev/pci/drm/radeon/r600_dpm.h

174

u32 index, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

176

u32 index, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

178

u32 index, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

180

u32 index, u32 divider);

sys/dev/pci/drm/radeon/r600_dpm.h

182

u32 index, u32 divider);

sys/dev/pci/drm/radeon/r600_dpm.h

184

u32 index, u32 divider);

sys/dev/pci/drm/radeon/r600_dpm.h

186

u32 index, u32 step_time);

sys/dev/pci/drm/radeon/r600_dpm.h

187

void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u);

sys/dev/pci/drm/radeon/r600_dpm.h

188

void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u);

sys/dev/pci/drm/radeon/r600_dpm.h

189

void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt);

sys/dev/pci/drm/radeon/r600_dpm.h

199

enum r600_power_level index, u32 voltage_index);

sys/dev/pci/drm/radeon/r600_dpm.h

201

enum r600_power_level index, u32 mem_clock_index);

sys/dev/pci/drm/radeon/r600_dpm.h

203

enum r600_power_level index, u32 eng_clock_index);

sys/dev/pci/drm/radeon/r600_dpm.h

228

u32 sys_mask,

sys/dev/pci/drm/radeon/r600_dpm.h

235

u8 r600_encode_pci_lane_width(u32 lanes);

sys/dev/pci/drm/radeon/r600_hdmi.c

146

u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

sys/dev/pci/drm/radeon/r600_hdmi.c

218

void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/r600_hdmi.c

319

void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/pci/drm/radeon/r600_hdmi.c

330

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/pci/drm/radeon/r600_hdmi.c

372

void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)

sys/dev/pci/drm/radeon/r600_hdmi.c

454

u32 hdmi = HDMI0_ERROR_ACK;

sys/dev/pci/drm/radeon/radeon.h

1006

unsigned rptr_offs, u32 nop);

sys/dev/pci/drm/radeon/radeon.h

1055

u32 cs_flags;

sys/dev/pci/drm/radeon/radeon.h

1056

u32 ring;

sys/dev/pci/drm/radeon/radeon.h

1060

static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)

sys/dev/pci/drm/radeon/radeon.h

1272

u32 delay; /* delay in usec from voltage drop to sclk change */

sys/dev/pci/drm/radeon/radeon.h

1289

u32 mclk;

sys/dev/pci/drm/radeon/radeon.h

1291

u32 sclk;

sys/dev/pci/drm/radeon/radeon.h

1295

u32 flags;

sys/dev/pci/drm/radeon/radeon.h

1308

u32 flags;

sys/dev/pci/drm/radeon/radeon.h

1309

u32 misc; /* vbios specific flags */

sys/dev/pci/drm/radeon/radeon.h

1310

u32 misc2; /* vbios specific flags */

sys/dev/pci/drm/radeon/radeon.h

1344

u32 caps; /* vbios flags */

sys/dev/pci/drm/radeon/radeon.h

1345

u32 class; /* vbios flags */

sys/dev/pci/drm/radeon/radeon.h

1346

u32 class2; /* vbios flags */

sys/dev/pci/drm/radeon/radeon.h

1348

u32 vclk;

sys/dev/pci/drm/radeon/radeon.h

1349

u32 dclk;

sys/dev/pci/drm/radeon/radeon.h

1351

u32 evclk;

sys/dev/pci/drm/radeon/radeon.h

1352

u32 ecclk;

sys/dev/pci/drm/radeon/radeon.h

1376

u32 sclk;

sys/dev/pci/drm/radeon/radeon.h

1377

u32 mclk;

sys/dev/pci/drm/radeon/radeon.h

1382

u32 sclk;

sys/dev/pci/drm/radeon/radeon.h

1383

u32 mclk;

sys/dev/pci/drm/radeon/radeon.h

1389

u32 count;

sys/dev/pci/drm/radeon/radeon.h

1390

u32 *values;

sys/dev/pci/drm/radeon/radeon.h

1394

u32 clk;

sys/dev/pci/drm/radeon/radeon.h

1399

u32 count;

sys/dev/pci/drm/radeon/radeon.h

1406

u32 leakage;

sys/dev/pci/drm/radeon/radeon.h

1416

u32 count;

sys/dev/pci/drm/radeon/radeon.h

1422

u32 sclk;

sys/dev/pci/drm/radeon/radeon.h

1423

u32 mclk;

sys/dev/pci/drm/radeon/radeon.h

1427

u32 count;

sys/dev/pci/drm/radeon/radeon.h

1432

u32 vclk;

sys/dev/pci/drm/radeon/radeon.h

1433

u32 dclk;

sys/dev/pci/drm/radeon/radeon.h

1443

u32 ecclk;

sys/dev/pci/drm/radeon/radeon.h

1444

u32 evclk;

sys/dev/pci/drm/radeon/radeon.h

1456

u32 platform_tdp;

sys/dev/pci/drm/radeon/radeon.h

1457

u32 small_ac_platform_tdp;

sys/dev/pci/drm/radeon/radeon.h

1458

u32 platform_tdc;

sys/dev/pci/drm/radeon/radeon.h

1459

u32 small_ac_platform_tdc;

sys/dev/pci/drm/radeon/radeon.h

1460

u32 apu_tdp;

sys/dev/pci/drm/radeon/radeon.h

1461

u32 dgpu_tdp;

sys/dev/pci/drm/radeon/radeon.h

1462

u32 dgpu_ulv_power;

sys/dev/pci/drm/radeon/radeon.h

1463

u32 tj_max;

sys/dev/pci/drm/radeon/radeon.h

1491

u32 mclk_sclk_ratio;

sys/dev/pci/drm/radeon/radeon.h

1492

u32 sclk_mclk_delta;

sys/dev/pci/drm/radeon/radeon.h

1509

u32 cycle_delay;

sys/dev/pci/drm/radeon/radeon.h

1533

u32 evclk;

sys/dev/pci/drm/radeon/radeon.h

1534

u32 ecclk;

sys/dev/pci/drm/radeon/radeon.h

1536

u32 sclk;

sys/dev/pci/drm/radeon/radeon.h

1537

u32 mclk;

sys/dev/pci/drm/radeon/radeon.h

1559

u32 platform_caps;

sys/dev/pci/drm/radeon/radeon.h

1560

u32 voltage_response_time;

sys/dev/pci/drm/radeon/radeon.h

1561

u32 backbias_response_time;

sys/dev/pci/drm/radeon/radeon.h

1563

u32 new_active_crtcs;

sys/dev/pci/drm/radeon/radeon.h

1566

u32 current_active_crtcs;

sys/dev/pci/drm/radeon/radeon.h

1571

u32 tdp_limit;

sys/dev/pci/drm/radeon/radeon.h

1572

u32 near_tdp_limit;

sys/dev/pci/drm/radeon/radeon.h

1573

u32 near_tdp_limit_adjusted;

sys/dev/pci/drm/radeon/radeon.h

1574

u32 sq_ramping_threshold;

sys/dev/pci/drm/radeon/radeon.h

1575

u32 cac_leakage;

sys/dev/pci/drm/radeon/radeon.h

1577

u32 tdp_adjustment;

sys/dev/pci/drm/radeon/radeon.h

1601

u32 active_crtcs;

sys/dev/pci/drm/radeon/radeon.h

1625

u32 current_sclk;

sys/dev/pci/drm/radeon/radeon.h

1626

u32 current_mclk;

sys/dev/pci/drm/radeon/radeon.h

1629

u32 default_sclk;

sys/dev/pci/drm/radeon/radeon.h

1630

u32 default_mclk;

sys/dev/pci/drm/radeon/radeon.h

1760

u32 offset;

sys/dev/pci/drm/radeon/radeon.h

1762

u32 id;

sys/dev/pci/drm/radeon/radeon.h

1817

u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);

sys/dev/pci/drm/radeon/radeon.h

1818

u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);

sys/dev/pci/drm/radeon/radeon.h

1860

u32 (*get_xclk)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

1864

int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);

sys/dev/pci/drm/radeon/radeon.h

1903

u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);

sys/dev/pci/drm/radeon/radeon.h

1921

u32 blit_ring_index;

sys/dev/pci/drm/radeon/radeon.h

1927

u32 dma_ring_index;

sys/dev/pci/drm/radeon/radeon.h

1935

u32 copy_ring_index;

sys/dev/pci/drm/radeon/radeon.h

1965

int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon.h

1966

int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/pci/drm/radeon/radeon.h

1981

u32 (*get_sclk)(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon.h

1982

u32 (*get_mclk)(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon.h

1989

void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);

sys/dev/pci/drm/radeon/radeon.h

1990

u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

1991

int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);

sys/dev/pci/drm/radeon/radeon.h

1992

int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);

sys/dev/pci/drm/radeon/radeon.h

1993

u32 (*get_current_sclk)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

1994

u32 (*get_current_mclk)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

2010

u32 hdp_cntl;

sys/dev/pci/drm/radeon/radeon.h

2016

u32 resync_scratch;

sys/dev/pci/drm/radeon/radeon.h

2017

u32 hdp_cntl;

sys/dev/pci/drm/radeon/radeon.h

2475

u32 cg_flags;

sys/dev/pci/drm/radeon/radeon.h

2476

u32 pg_flags;

sys/dev/pci/drm/radeon/radeon.h

2480

u32 px_quirk_flags;

sys/dev/pci/drm/radeon/radeon.h

2517

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2518

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2520

u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);

sys/dev/pci/drm/radeon/radeon.h

2521

void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2620

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2621

void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2622

u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2623

void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2624

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2625

void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2626

u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2627

void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2628

u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2629

void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2630

u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2631

void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2632

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon.h

2633

void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon.h

2849

extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);

sys/dev/pci/drm/radeon/radeon.h

2864

const u32 *registers,

sys/dev/pci/drm/radeon/radeon.h

2865

const u32 array_size);

sys/dev/pci/drm/radeon/radeon.h

2870

u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);

sys/dev/pci/drm/radeon/radeon.h

2937

bool r600_fmt_is_valid_color(u32 format);

sys/dev/pci/drm/radeon/radeon.h

2938

bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);

sys/dev/pci/drm/radeon/radeon.h

2939

int r600_fmt_get_blocksize(u32 format);

sys/dev/pci/drm/radeon/radeon.h

2940

int r600_fmt_get_nblocksx(u32 format, u32 w);

sys/dev/pci/drm/radeon/radeon.h

2941

int r600_fmt_get_nblocksy(u32 format, u32 h);

sys/dev/pci/drm/radeon/radeon.h

2947

u32 clock;

sys/dev/pci/drm/radeon/radeon.h

2960

extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon.h

2961

u32 tiling_pipe_num,

sys/dev/pci/drm/radeon/radeon.h

2962

u32 max_rb_num,

sys/dev/pci/drm/radeon/radeon.h

2963

u32 total_max_rb_num,

sys/dev/pci/drm/radeon/radeon.h

2964

u32 enabled_rb_mask);

sys/dev/pci/drm/radeon/radeon.h

3001

u32 reg, u32 mask,

sys/dev/pci/drm/radeon/radeon.h

306

u32 clock,

sys/dev/pci/drm/radeon/radeon.h

310

u32 clock,

sys/dev/pci/drm/radeon/radeon.h

316

u32 *gpio_value, u32 *gpio_mask);

sys/dev/pci/drm/radeon/radeon.h

318

u32 eng_clock, u32 mem_clock);

sys/dev/pci/drm/radeon/radeon.h

352

u32 mem_clock);

sys/dev/pci/drm/radeon/radeon.h

354

u32 mem_clock);

sys/dev/pci/drm/radeon/radeon.h

497

u32 initial_domain;

sys/dev/pci/drm/radeon/radeon.h

502

u32 flags;

sys/dev/pci/drm/radeon/radeon.h

504

u32 tiling_flags;

sys/dev/pci/drm/radeon/radeon.h

505

u32 pitch;

sys/dev/pci/drm/radeon/radeon.h

528

u32 domain;

sys/dev/pci/drm/radeon/radeon.h

547

u32 flags, bool kernel,

sys/dev/pci/drm/radeon/radeon.h

692

u32 __iomem *ptr;

sys/dev/pci/drm/radeon/radeon.h

694

u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */

sys/dev/pci/drm/radeon/radeon.h

698

int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);

sys/dev/pci/drm/radeon/radeon.h

699

void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);

sys/dev/pci/drm/radeon/radeon.h

710

u32 target_vblank;

sys/dev/pci/drm/radeon/radeon.h

719

u32 disp_int;

sys/dev/pci/drm/radeon/radeon.h

720

u32 hdmi0_status;

sys/dev/pci/drm/radeon/radeon.h

724

u32 disp_int;

sys/dev/pci/drm/radeon/radeon.h

725

u32 disp_int_cont;

sys/dev/pci/drm/radeon/radeon.h

726

u32 disp_int_cont2;

sys/dev/pci/drm/radeon/radeon.h

727

u32 d1grph_int;

sys/dev/pci/drm/radeon/radeon.h

728

u32 d2grph_int;

sys/dev/pci/drm/radeon/radeon.h

729

u32 hdmi0_status;

sys/dev/pci/drm/radeon/radeon.h

730

u32 hdmi1_status;

sys/dev/pci/drm/radeon/radeon.h

734

u32 disp_int[6];

sys/dev/pci/drm/radeon/radeon.h

735

u32 grph_int[6];

sys/dev/pci/drm/radeon/radeon.h

736

u32 afmt_status[6];

sys/dev/pci/drm/radeon/radeon.h

740

u32 disp_int;

sys/dev/pci/drm/radeon/radeon.h

741

u32 disp_int_cont;

sys/dev/pci/drm/radeon/radeon.h

742

u32 disp_int_cont2;

sys/dev/pci/drm/radeon/radeon.h

743

u32 disp_int_cont3;

sys/dev/pci/drm/radeon/radeon.h

744

u32 disp_int_cont4;

sys/dev/pci/drm/radeon/radeon.h

745

u32 disp_int_cont5;

sys/dev/pci/drm/radeon/radeon.h

746

u32 disp_int_cont6;

sys/dev/pci/drm/radeon/radeon.h

747

u32 d1grph_int;

sys/dev/pci/drm/radeon/radeon.h

748

u32 d2grph_int;

sys/dev/pci/drm/radeon/radeon.h

749

u32 d3grph_int;

sys/dev/pci/drm/radeon/radeon.h

750

u32 d4grph_int;

sys/dev/pci/drm/radeon/radeon.h

751

u32 d5grph_int;

sys/dev/pci/drm/radeon/radeon.h

752

u32 d6grph_int;

sys/dev/pci/drm/radeon/radeon.h

810

volatile u32 *next_rptr_cpu_addr;

sys/dev/pci/drm/radeon/radeon.h

822

u32 nop;

sys/dev/pci/drm/radeon/radeon.h

823

u32 idx;

sys/dev/pci/drm/radeon/radeon.h

827

u32 me;

sys/dev/pci/drm/radeon/radeon.h

828

u32 pipe;

sys/dev/pci/drm/radeon/radeon.h

829

u32 queue;

sys/dev/pci/drm/radeon/radeon.h

831

u32 doorbell_index;

sys/dev/pci/drm/radeon/radeon.h

838

u32 num_pipe;

sys/dev/pci/drm/radeon/radeon.h

839

u32 num_mec;

sys/dev/pci/drm/radeon/radeon.h

840

u32 num_queue;

sys/dev/pci/drm/radeon/radeon.h

961

const u32 *reg_list;

sys/dev/pci/drm/radeon/radeon.h

962

u32 reg_list_size;

sys/dev/pci/drm/radeon/radeon.h

968

u32 clear_state_size;

sys/dev/pci/drm/radeon/radeon.h

973

u32 cp_table_size;

sys/dev/pci/drm/radeon/radeon_acpi.c

161

static void radeon_atif_parse_notification(struct radeon_atif_notifications *n, u32 mask)

sys/dev/pci/drm/radeon/radeon_acpi.c

184

static void radeon_atif_parse_functions(struct radeon_atif_functions *f, u32 mask)

sys/dev/pci/drm/radeon/radeon_acpi.c

484

static void radeon_atcs_parse_functions(struct radeon_atcs_functions *f, u32 mask)

sys/dev/pci/drm/radeon/radeon_acpi.c

52

u32 notification_mask; /* supported notifications mask */

sys/dev/pci/drm/radeon/radeon_acpi.c

53

u32 function_bits; /* supported functions bit vector */

sys/dev/pci/drm/radeon/radeon_acpi.c

58

u32 valid_mask; /* valid flags mask */

sys/dev/pci/drm/radeon/radeon_acpi.c

59

u32 flags; /* flags */

sys/dev/pci/drm/radeon/radeon_acpi.c

609

u32 retry = 3;

sys/dev/pci/drm/radeon/radeon_acpi.c

65

u32 pending; /* pending sbios requests */

sys/dev/pci/drm/radeon/radeon_acpi.c

83

u32 function_bits; /* supported functions bit vector */

sys/dev/pci/drm/radeon/radeon_agp.c

38

u32 hostbridge_vendor;

sys/dev/pci/drm/radeon/radeon_agp.c

39

u32 hostbridge_device;

sys/dev/pci/drm/radeon/radeon_agp.c

40

u32 chip_vendor;

sys/dev/pci/drm/radeon/radeon_agp.c

41

u32 chip_device;

sys/dev/pci/drm/radeon/radeon_agp.c

42

u32 subsys_vendor;

sys/dev/pci/drm/radeon/radeon_agp.c

43

u32 subsys_device;

sys/dev/pci/drm/radeon/radeon_agp.c

44

u32 default_mode;

sys/dev/pci/drm/radeon/radeon_asic.c

140

u32 reg, u32 *val)

sys/dev/pci/drm/radeon/radeon_asic.h

146

u32 r100_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

148

u32 r100_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

200

extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/pci/drm/radeon/radeon_asic.h

201

extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon_asic.h

236

u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);

sys/dev/pci/drm/radeon/radeon_asic.h

278

u32 vga_render_control;

sys/dev/pci/drm/radeon/radeon_asic.h

279

u32 vga_hdp_control;

sys/dev/pci/drm/radeon/radeon_asic.h

381

u32 r600_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

383

u32 r600_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

388

u32 reg, u32 *val);

sys/dev/pci/drm/radeon/radeon_asic.h

400

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);

sys/dev/pci/drm/radeon/radeon_asic.h

406

u32 r600_get_xclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

409

int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon_asic.h

428

u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

429

u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

436

u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

437

u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

446

u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

447

u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

454

u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

455

u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

475

u32 rv770_get_xclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

476

int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon_asic.h

487

u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

488

u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

496

u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

497

u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

503

u32 vga_render_control;

sys/dev/pci/drm/radeon/radeon_asic.h

504

u32 vga_hdp_control;

sys/dev/pci/drm/radeon/radeon_asic.h

523

u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);

sys/dev/pci/drm/radeon/radeon_asic.h

533

int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon_asic.h

534

int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon_asic.h

54

u32 GENMO_WT;

sys/dev/pci/drm/radeon/radeon_asic.h

55

u32 CRTC_EXT_CNTL;

sys/dev/pci/drm/radeon/radeon_asic.h

551

u32 reg, u32 *val);

sys/dev/pci/drm/radeon/radeon_asic.h

56

u32 CRTC_GEN_CNTL;

sys/dev/pci/drm/radeon/radeon_asic.h

57

u32 CRTC2_GEN_CNTL;

sys/dev/pci/drm/radeon/radeon_asic.h

570

u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

571

u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

575

u32 btc_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

576

u32 btc_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

58

u32 CUR_OFFSET;

sys/dev/pci/drm/radeon/radeon_asic.h

587

u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

588

u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

59

u32 CUR2_OFFSET;

sys/dev/pci/drm/radeon/radeon_asic.h

595

u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

596

u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

642

u32 cayman_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

644

u32 cayman_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

655

u32 reg, u32 *val);

sys/dev/pci/drm/radeon/radeon_asic.h

665

u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

666

u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

674

u32 ni_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

675

u32 ni_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

68

u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);

sys/dev/pci/drm/radeon/radeon_asic.h

686

u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

687

u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

695

u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

696

u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

697

int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/pci/drm/radeon/radeon_asic.h

746

u32 si_get_xclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

748

int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon_asic.h

749

int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/pci/drm/radeon/radeon_asic.h

752

u32 reg, u32 *val);

sys/dev/pci/drm/radeon/radeon_asic.h

768

u32 *speed);

sys/dev/pci/drm/radeon/radeon_asic.h

770

u32 speed);

sys/dev/pci/drm/radeon/radeon_asic.h

771

u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

772

void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);

sys/dev/pci/drm/radeon/radeon_asic.h

773

u32 si_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

774

u32 si_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

783

u32 cik_get_xclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

786

int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/radeon_asic.h

787

int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/pci/drm/radeon/radeon_asic.h

850

u32 cik_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

852

u32 cik_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

856

u32 cik_compute_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

858

u32 cik_compute_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

862

u32 cik_sdma_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

864

u32 cik_sdma_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

871

u32 reg, u32 *val);

sys/dev/pci/drm/radeon/radeon_asic.h

883

u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

884

u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

893

u32 ci_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

894

u32 ci_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

897

u32 *speed);

sys/dev/pci/drm/radeon/radeon_asic.h

899

u32 speed);

sys/dev/pci/drm/radeon/radeon_asic.h

900

u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

901

void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);

sys/dev/pci/drm/radeon/radeon_asic.h

913

u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

914

u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/pci/drm/radeon/radeon_asic.h

923

u32 kv_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

924

u32 kv_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_atombios.c

1511

int id, u32 clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

2047

u32 misc, u32 misc2)

sys/dev/pci/drm/radeon/radeon_atombios.c

2088

u32 misc, misc2 = 0;

sys/dev/pci/drm/radeon/radeon_atombios.c

240

u32 reg;

sys/dev/pci/drm/radeon/radeon_atombios.c

2413

u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);

sys/dev/pci/drm/radeon/radeon_atombios.c

2414

u32 misc2 = le16_to_cpu(non_clock_info->usClassification);

sys/dev/pci/drm/radeon/radeon_atombios.c

2487

u32 sclk, mclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2845

u32 clock,

sys/dev/pci/drm/radeon/radeon_atombios.c

2961

u32 clock,

sys/dev/pci/drm/radeon/radeon_atombios.c

3065

u32 eng_clock, u32 mem_clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

3069

u32 tmp;

sys/dev/pci/drm/radeon/radeon_atombios.c

3084

u32 mem_clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

3086

u32 args;

sys/dev/pci/drm/radeon/radeon_atombios.c

3095

u32 mem_clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

3099

u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);

sys/dev/pci/drm/radeon/radeon_atombios.c

3321

u32 entry_id;

sys/dev/pci/drm/radeon/radeon_atombios.c

3322

u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;

sys/dev/pci/drm/radeon/radeon_atombios.c

3349

u32 *gpio_value, u32 *gpio_mask)

sys/dev/pci/drm/radeon/radeon_atombios.c

3368

*gpio_mask = le32_to_cpu(*(u32 *)&args.v2);

sys/dev/pci/drm/radeon/radeon_atombios.c

3376

*gpio_value = le32_to_cpu(*(u32 *)&args.v2);

sys/dev/pci/drm/radeon/radeon_atombios.c

3401

u32 size = le16_to_cpu(v1->sHeader.usStructureSize);

sys/dev/pci/drm/radeon/radeon_atombios.c

3402

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

3418

u32 size = le16_to_cpu(v2->sHeader.usStructureSize);

sys/dev/pci/drm/radeon/radeon_atombios.c

3419

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

3435

u32 size = le16_to_cpu(v3->sHeader.usStructureSize);

sys/dev/pci/drm/radeon/radeon_atombios.c

3436

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

3926

u32 mem_timing_size = gddr5 ?

sys/dev/pci/drm/radeon/radeon_atombios.c

3997

u32 i = 0, j;

sys/dev/pci/drm/radeon/radeon_atombios.c

4039

while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&

sys/dev/pci/drm/radeon/radeon_atombios.c

4041

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/pci/drm/radeon/radeon_atombios.c

4045

(u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)

sys/dev/pci/drm/radeon/radeon_atombios.c

4050

(u32)le32_to_cpu(*((u32 *)reg_data + j));

sys/dev/pci/drm/radeon/radeon_atombios.c

4062

if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)

sys/dev/pci/drm/radeon/radeon_audio.c

288

u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)

sys/dev/pci/drm/radeon/radeon_audio.c

296

void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/radeon_audio.c

297

u32 reg, u32 v)

sys/dev/pci/drm/radeon/radeon_audio.c

47

static const u32 pin_offsets[7] = {

sys/dev/pci/drm/radeon/radeon_audio.c

57

static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)

sys/dev/pci/drm/radeon/radeon_audio.c

62

static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/radeon_audio.c

63

u32 reg, u32 v)

sys/dev/pci/drm/radeon/radeon_audio.h

38

u32 (*endpoint_rreg)(struct radeon_device *rdev, u32 offset, u32 reg);

sys/dev/pci/drm/radeon/radeon_audio.h

40

u32 offset, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon_audio.h

58

void (*set_vbi_packet)(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/radeon_audio.h

59

void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc);

sys/dev/pci/drm/radeon/radeon_audio.h

60

void (*set_avi_packet)(struct radeon_device *rdev, u32 offset,

sys/dev/pci/drm/radeon/radeon_audio.h

62

void (*set_audio_packet)(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/radeon_audio.h

63

void (*set_mute)(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/pci/drm/radeon/radeon_audio.h

73

u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_audio.h

74

u32 offset, u32 reg);

sys/dev/pci/drm/radeon/radeon_audio.h

76

u32 offset, u32 reg, u32 v);

sys/dev/pci/drm/radeon/radeon_audio.h

94

void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/pci/drm/radeon/radeon_audio.h

95

void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/pci/drm/radeon/radeon_bios.c

392

u32 bus_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

393

u32 d1vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

394

u32 d2vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

395

u32 vga_render_control;

sys/dev/pci/drm/radeon/radeon_bios.c

396

u32 rom_cntl;

sys/dev/pci/drm/radeon/radeon_clocks.c

114

const u32 *val;

sys/dev/pci/drm/radeon/radeon_clocks.c

284

u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);

sys/dev/pci/drm/radeon/radeon_combios.c

1251

u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;

sys/dev/pci/drm/radeon/radeon_combios.c

404

u32 clk_mask,

sys/dev/pci/drm/radeon/radeon_combios.c

405

u32 data_mask)

sys/dev/pci/drm/radeon/radeon_combios.c

409

u32 clk_mask,

sys/dev/pci/drm/radeon/radeon_combios.c

410

u32 data_mask)

sys/dev/pci/drm/radeon/radeon_cs.c

209

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)

sys/dev/pci/drm/radeon/radeon_cs.c

275

u32 ring = RADEON_CS_RING_GFX;

sys/dev/pci/drm/radeon/radeon_cursor.c

75

u32 reg;

sys/dev/pci/drm/radeon/radeon_device.c

127

u32 chip_vendor;

sys/dev/pci/drm/radeon/radeon_device.c

128

u32 chip_device;

sys/dev/pci/drm/radeon/radeon_device.c

129

u32 subsys_vendor;

sys/dev/pci/drm/radeon/radeon_device.c

130

u32 subsys_device;

sys/dev/pci/drm/radeon/radeon_device.c

131

u32 px_quirk_flags;

sys/dev/pci/drm/radeon/radeon_device.c

203

const u32 *registers,

sys/dev/pci/drm/radeon/radeon_device.c

204

const u32 array_size)

sys/dev/pci/drm/radeon/radeon_device.c

206

u32 tmp, reg, and_mask, or_mask;

sys/dev/pci/drm/radeon/radeon_device.c

346

rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);

sys/dev/pci/drm/radeon/radeon_device.c

351

rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));

sys/dev/pci/drm/radeon/radeon_device.c

393

int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)

sys/dev/pci/drm/radeon/radeon_device.c

413

void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)

sys/dev/pci/drm/radeon/radeon_device.c

740

u32 sclk = rdev->pm.current_sclk;

sys/dev/pci/drm/radeon/radeon_device.c

741

u32 mclk = rdev->pm.current_mclk;

sys/dev/pci/drm/radeon/radeon_display.c

1130

u32 pll_out_min, pll_out_max;

sys/dev/pci/drm/radeon/radeon_display.c

1692

u32 src_v = 1, dst_v = 1;

sys/dev/pci/drm/radeon/radeon_display.c

1693

u32 src_h = 1, dst_h = 1;

sys/dev/pci/drm/radeon/radeon_display.c

1814

u32 stat_crtc = 0, vbl = 0, position = 0;

sys/dev/pci/drm/radeon/radeon_display.c

286

u32 update_pending;

sys/dev/pci/drm/radeon/radeon_display.c

957

u32 freq,

sys/dev/pci/drm/radeon/radeon_display.c

958

u32 *dot_clock_p,

sys/dev/pci/drm/radeon/radeon_display.c

959

u32 *fb_div_p,

sys/dev/pci/drm/radeon/radeon_display.c

960

u32 *frac_fb_div_p,

sys/dev/pci/drm/radeon/radeon_display.c

961

u32 *ref_div_p,

sys/dev/pci/drm/radeon/radeon_display.c

962

u32 *post_div_p)

sys/dev/pci/drm/radeon/radeon_dp_auxch.c

44

static const u32 aux_offset[] =

sys/dev/pci/drm/radeon/radeon_encoders.c

368

u32 pixel_clock)

sys/dev/pci/drm/radeon/radeon_fbdev.c

64

u32 tiling_flags = 0;

sys/dev/pci/drm/radeon/radeon_fbdev.c

68

u32 cpp;

sys/dev/pci/drm/radeon/radeon_fence.c

67

static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)

sys/dev/pci/drm/radeon/radeon_fence.c

88

static u32 radeon_fence_read(struct radeon_device *rdev, int ring)

sys/dev/pci/drm/radeon/radeon_fence.c

91

u32 seq = 0;

sys/dev/pci/drm/radeon/radeon_gem.c

167

u32 flags, bool kernel,

sys/dev/pci/drm/radeon/radeon_gem.c

766

u32 invalid_flags;

sys/dev/pci/drm/radeon/radeon_i2c.c

103

u32 reg;

sys/dev/pci/drm/radeon/radeon_i2c.c

330

static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/radeon_i2c.c

332

u32 sclk = rdev->pm.current_sclk;

sys/dev/pci/drm/radeon/radeon_i2c.c

333

u32 prescale = 0;

sys/dev/pci/drm/radeon/radeon_i2c.c

334

u32 nm;

sys/dev/pci/drm/radeon/radeon_i2c.c

428

u32 prescale;

sys/dev/pci/drm/radeon/radeon_i2c.c

429

u32 i2c_cntl_0, i2c_cntl_1, i2c_data;

sys/dev/pci/drm/radeon/radeon_i2c.c

430

u32 tmp, reg;

sys/dev/pci/drm/radeon/radeon_i2c.c

681

u32 prescale;

sys/dev/pci/drm/radeon/radeon_i2c.c

682

u32 tmp, reg;

sys/dev/pci/drm/radeon/radeon_i2c.c

683

u32 saved1, saved2;

sys/dev/pci/drm/radeon/radeon_i2c.c

987

static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)

sys/dev/pci/drm/radeon/radeon_irq_kms.c

608

u32 reg, u32 mask,

sys/dev/pci/drm/radeon/radeon_irq_kms.c

611

u32 tmp = RREG32(reg);

sys/dev/pci/drm/radeon/radeon_kms.c

760

u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)

sys/dev/pci/drm/radeon/radeon_kms.c

765

u32 count;

sys/dev/pci/drm/radeon/radeon_kms.h

31

u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

544

crtc_offset = (u32)base;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

62

u32 scale, inc, crtc_more_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

63

u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

64

u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

65

u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

516

((u32)h_inc << RADEON_H_INC_SHIFT);

sys/dev/pci/drm/radeon/radeon_mode.h

354

u32 adjusted_clock;

sys/dev/pci/drm/radeon/radeon_mode.h

356

u32 pll_reference_div;

sys/dev/pci/drm/radeon/radeon_mode.h

357

u32 pll_post_div;

sys/dev/pci/drm/radeon/radeon_mode.h

358

u32 pll_flags;

sys/dev/pci/drm/radeon/radeon_mode.h

362

u32 line_time;

sys/dev/pci/drm/radeon/radeon_mode.h

363

u32 wm_low;

sys/dev/pci/drm/radeon/radeon_mode.h

364

u32 wm_high;

sys/dev/pci/drm/radeon/radeon_mode.h

365

u32 lb_vblank_lead_lines;

sys/dev/pci/drm/radeon/radeon_mode.h

480

u32 reg;

sys/dev/pci/drm/radeon/radeon_mode.h

481

u32 mask;

sys/dev/pci/drm/radeon/radeon_mode.h

482

u32 shift;

sys/dev/pci/drm/radeon/radeon_mode.h

492

u32 router_id;

sys/dev/pci/drm/radeon/radeon_mode.h

546

u32 post_div;

sys/dev/pci/drm/radeon/radeon_mode.h

550

u32 reserved : 6;

sys/dev/pci/drm/radeon/radeon_mode.h

551

u32 whole_fb_div : 12;

sys/dev/pci/drm/radeon/radeon_mode.h

552

u32 frac_fb_div : 14;

sys/dev/pci/drm/radeon/radeon_mode.h

554

u32 frac_fb_div : 14;

sys/dev/pci/drm/radeon/radeon_mode.h

555

u32 whole_fb_div : 12;

sys/dev/pci/drm/radeon/radeon_mode.h

556

u32 reserved : 6;

sys/dev/pci/drm/radeon/radeon_mode.h

559

u32 fb_div;

sys/dev/pci/drm/radeon/radeon_mode.h

561

u32 ref_div;

sys/dev/pci/drm/radeon/radeon_mode.h

564

u32 vco_mode;

sys/dev/pci/drm/radeon/radeon_mode.h

565

u32 real_clock;

sys/dev/pci/drm/radeon/radeon_mode.h

567

u32 post_divider;

sys/dev/pci/drm/radeon/radeon_mode.h

568

u32 flags;

sys/dev/pci/drm/radeon/radeon_mode.h

575

u32 reserved : 8;

sys/dev/pci/drm/radeon/radeon_mode.h

576

u32 clkfrac : 12;

sys/dev/pci/drm/radeon/radeon_mode.h

577

u32 clkf : 12;

sys/dev/pci/drm/radeon/radeon_mode.h

579

u32 clkf : 12;

sys/dev/pci/drm/radeon/radeon_mode.h

580

u32 clkfrac : 12;

sys/dev/pci/drm/radeon/radeon_mode.h

581

u32 reserved : 8;

sys/dev/pci/drm/radeon/radeon_mode.h

584

u32 fb_div;

sys/dev/pci/drm/radeon/radeon_mode.h

586

u32 post_div;

sys/dev/pci/drm/radeon/radeon_mode.h

587

u32 bwcntl;

sys/dev/pci/drm/radeon/radeon_mode.h

588

u32 dll_speed;

sys/dev/pci/drm/radeon/radeon_mode.h

589

u32 vco_mode;

sys/dev/pci/drm/radeon/radeon_mode.h

590

u32 yclk_sel;

sys/dev/pci/drm/radeon/radeon_mode.h

591

u32 qdr;

sys/dev/pci/drm/radeon/radeon_mode.h

592

u32 half_rate;

sys/dev/pci/drm/radeon/radeon_mode.h

613

u32 mclk[MAX_AC_TIMING_ENTRIES];

sys/dev/pci/drm/radeon/radeon_mode.h

620

u32 mclk_max;

sys/dev/pci/drm/radeon/radeon_mode.h

621

u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/radeon_mode.h

640

u32 smio_low;

sys/dev/pci/drm/radeon/radeon_mode.h

644

u32 count;

sys/dev/pci/drm/radeon/radeon_mode.h

645

u32 mask_low;

sys/dev/pci/drm/radeon/radeon_mode.h

646

u32 phase_delay;

sys/dev/pci/drm/radeon/radeon_mode.h

701

u32 pixel_clock);

sys/dev/pci/drm/radeon/radeon_mode.h

770

int id, u32 clock);

sys/dev/pci/drm/radeon/radeon_mode.h

783

u32 freq,

sys/dev/pci/drm/radeon/radeon_mode.h

784

u32 *dot_clock_p,

sys/dev/pci/drm/radeon/radeon_mode.h

785

u32 *fb_div_p,

sys/dev/pci/drm/radeon/radeon_mode.h

786

u32 *frac_fb_div_p,

sys/dev/pci/drm/radeon/radeon_mode.h

787

u32 *ref_div_p,

sys/dev/pci/drm/radeon/radeon_mode.h

788

u32 *post_div_p);

sys/dev/pci/drm/radeon/radeon_object.c

130

u32 domain, u32 flags, struct sg_table *sg,

sys/dev/pci/drm/radeon/radeon_object.c

272

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,

sys/dev/pci/drm/radeon/radeon_object.c

331

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)

sys/dev/pci/drm/radeon/radeon_object.c

508

u32 domain = lobj->preferred_domains;

sys/dev/pci/drm/radeon/radeon_object.c

509

u32 allowed = lobj->allowed_domains;

sys/dev/pci/drm/radeon/radeon_object.c

510

u32 current_domain =

sys/dev/pci/drm/radeon/radeon_object.c

76

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)

sys/dev/pci/drm/radeon/radeon_object.c

78

u32 c = 0, i;

sys/dev/pci/drm/radeon/radeon_object.h

138

bool kernel, u32 domain, u32 flags,

sys/dev/pci/drm/radeon/radeon_object.h

146

extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);

sys/dev/pci/drm/radeon/radeon_object.h

147

extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,

sys/dev/pci/drm/radeon/radeon_object.h

158

u32 tiling_flags, u32 pitch);

sys/dev/pci/drm/radeon/radeon_object.h

160

u32 *tiling_flags, u32 *pitch);

sys/dev/pci/drm/radeon/radeon_object.h

192

unsigned size, u32 align, u32 domain,

sys/dev/pci/drm/radeon/radeon_object.h

193

u32 flags);

sys/dev/pci/drm/radeon/radeon_object.h

40

static inline unsigned radeon_mem_type_to_domain(u32 mem_type)

sys/dev/pci/drm/radeon/radeon_pm.c

1498

u32 chip_vendor;

sys/dev/pci/drm/radeon/radeon_pm.c

1499

u32 chip_device;

sys/dev/pci/drm/radeon/radeon_pm.c

1500

u32 subsys_vendor;

sys/dev/pci/drm/radeon/radeon_pm.c

1501

u32 subsys_device;

sys/dev/pci/drm/radeon/radeon_pm.c

175

u32 sclk, mclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1866

u32 stat_crtc = 0;

sys/dev/pci/drm/radeon/radeon_pm.c

586

u32 pwm_mode = 0;

sys/dev/pci/drm/radeon/radeon_pm.c

643

u32 value;

sys/dev/pci/drm/radeon/radeon_pm.c

664

u32 speed;

sys/dev/pci/drm/radeon/radeon_pm.c

732

u32 sclk = 0;

sys/dev/pci/drm/radeon/radeon_pm.c

950

u32 ui_class;

sys/dev/pci/drm/radeon/radeon_ring.c

386

unsigned rptr_offs, u32 nop)

sys/dev/pci/drm/radeon/radeon_ring.c

425

u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);

sys/dev/pci/drm/radeon/radeon_sa.c

49

unsigned int size, u32 sa_align, u32 domain,

sys/dev/pci/drm/radeon/radeon_sa.c

50

u32 flags)

sys/dev/pci/drm/radeon/radeon_trace.h

112

__field(u32, ring)

sys/dev/pci/drm/radeon/radeon_trace.h

113

__field(u32, id)

sys/dev/pci/drm/radeon/radeon_trace.h

127

TP_PROTO(struct drm_device *dev, int ring, u32 seqno),

sys/dev/pci/drm/radeon/radeon_trace.h

132

__field(u32, dev)

sys/dev/pci/drm/radeon/radeon_trace.h

134

__field(u32, seqno)

sys/dev/pci/drm/radeon/radeon_trace.h

149

TP_PROTO(struct drm_device *dev, int ring, u32 seqno),

sys/dev/pci/drm/radeon/radeon_trace.h

156

TP_PROTO(struct drm_device *dev, int ring, u32 seqno),

sys/dev/pci/drm/radeon/radeon_trace.h

163

TP_PROTO(struct drm_device *dev, int ring, u32 seqno),

sys/dev/pci/drm/radeon/radeon_trace.h

20

__field(u32, pages)

sys/dev/pci/drm/radeon/radeon_trace.h

34

__field(u32, ring)

sys/dev/pci/drm/radeon/radeon_trace.h

35

__field(u32, dw)

sys/dev/pci/drm/radeon/radeon_trace.h

36

__field(u32, fences)

sys/dev/pci/drm/radeon/radeon_trace.h

54

__field(u32, vmid)

sys/dev/pci/drm/radeon/radeon_trace.h

55

__field(u32, ring)

sys/dev/pci/drm/radeon/radeon_trace.h

71

__field(u32, flags)

sys/dev/pci/drm/radeon/radeon_trace.h

90

__field(u32, count)

sys/dev/pci/drm/radeon/radeon_trace.h

91

__field(u32, incr)

sys/dev/pci/drm/radeon/radeon_trace.h

92

__field(u32, flags)

sys/dev/pci/drm/radeon/radeon_uvd.c

155

family_id = (__force u32)(hdr->ucode_version) & 0xff;

sys/dev/pci/drm/radeon/radeon_uvd.c

783

writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);

sys/dev/pci/drm/radeon/radeon_uvd.c

785

writel((__force u32)cpu_to_le32(handle), &msg[2]);

sys/dev/pci/drm/radeon/radeon_uvd.c

790

writel((__force u32)cpu_to_le32(0x00000780), &msg[7]);

sys/dev/pci/drm/radeon/radeon_uvd.c

791

writel((__force u32)cpu_to_le32(0x00000440), &msg[8]);

sys/dev/pci/drm/radeon/radeon_uvd.c

793

writel((__force u32)cpu_to_le32(0x01b37000), &msg[10]);

sys/dev/pci/drm/radeon/radeon_uvd.c

819

writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);

sys/dev/pci/drm/radeon/radeon_uvd.c

820

writel((__force u32)cpu_to_le32(0x00000002), &msg[1]);

sys/dev/pci/drm/radeon/radeon_uvd.c

821

writel((__force u32)cpu_to_le32(handle), &msg[2]);

sys/dev/pci/drm/radeon/rs400.c

165

tmp = (u32)rdev->gart.table_addr & 0xfffff000;

sys/dev/pci/drm/radeon/rs400.c

237

u32 *gtt = rdev->gart.ptr;

sys/dev/pci/drm/radeon/rs600.c

123

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rs600.c

138

(u32)crtc_base);

sys/dev/pci/drm/radeon/rs600.c

140

(u32)crtc_base);

sys/dev/pci/drm/radeon/rs600.c

171

u32 tmp = 0;

sys/dev/pci/drm/radeon/rs600.c

233

u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;

sys/dev/pci/drm/radeon/rs600.c

234

u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;

sys/dev/pci/drm/radeon/rs600.c

327

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

345

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

361

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

384

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

465

u32 status, tmp;

sys/dev/pci/drm/radeon/rs600.c

564

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

57

static const u32 crtc_offsets[2] = {

sys/dev/pci/drm/radeon/rs600.c

628

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

670

u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &

sys/dev/pci/drm/radeon/rs600.c

672

u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &

sys/dev/pci/drm/radeon/rs600.c

674

u32 hdmi0;

sys/dev/pci/drm/radeon/rs600.c

719

static inline u32 rs600_irq_ack(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rs600.c

72

u32 pos1, pos2;

sys/dev/pci/drm/radeon/rs600.c

723

u32 tmp;

sys/dev/pci/drm/radeon/rs600.c

768

u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &

sys/dev/pci/drm/radeon/rs600.c

780

u32 status, msi_rearm;

sys/dev/pci/drm/radeon/rs600.c

851

u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)

sys/dev/pci/drm/radeon/rs600.c

903

u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;

sys/dev/pci/drm/radeon/rs600.c

933

u32 r;

sys/dev/pci/drm/radeon/rs690.c

209

u32 tmp;

sys/dev/pci/drm/radeon/rs690.c

212

u32 lb_size = 8192;

sys/dev/pci/drm/radeon/rs690.c

260

u32 lb_request_fifo_depth;

sys/dev/pci/drm/radeon/rs690.c

282

u32 selected_sclk;

sys/dev/pci/drm/radeon/rs690.c

465

u32 *d1mode_priority_a_cnt,

sys/dev/pci/drm/radeon/rs690.c

466

u32 *d2mode_priority_a_cnt)

sys/dev/pci/drm/radeon/rs690.c

590

u32 tmp;

sys/dev/pci/drm/radeon/rs690.c

591

u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;

sys/dev/pci/drm/radeon/rs690.c

592

u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;

sys/dev/pci/drm/radeon/rs780_dpm.c

1006

u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rs780_dpm.c

1008

u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;

sys/dev/pci/drm/radeon/rs780_dpm.c

1009

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/pci/drm/radeon/rs780_dpm.c

1010

u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;

sys/dev/pci/drm/radeon/rs780_dpm.c

1011

u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +

sys/dev/pci/drm/radeon/rs780_dpm.c

1013

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/pci/drm/radeon/rs780_dpm.c

1020

u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rs780_dpm.c

212

u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;

sys/dev/pci/drm/radeon/rs780_dpm.c

226

u32 fv_throt_pwm_fb_div_range[3];

sys/dev/pci/drm/radeon/rs780_dpm.c

227

u32 fv_throt_pwm_range[4];

sys/dev/pci/drm/radeon/rs780_dpm.c

405

static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)

sys/dev/pci/drm/radeon/rs780_dpm.c

509

static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rs780_dpm.c

752

u32 sclk;

sys/dev/pci/drm/radeon/rs780_dpm.c

964

u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/rs780_dpm.c

974

u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/rs780_dpm.c

986

u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;

sys/dev/pci/drm/radeon/rs780_dpm.c

987

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/pci/drm/radeon/rs780_dpm.c

988

u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;

sys/dev/pci/drm/radeon/rs780_dpm.c

989

u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +

sys/dev/pci/drm/radeon/rs780_dpm.c

991

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/pci/drm/radeon/rs780_dpm.h

39

u32 system_config;

sys/dev/pci/drm/radeon/rs780_dpm.h

40

u32 bootup_uma_clk;

sys/dev/pci/drm/radeon/rs780_dpm.h

55

u32 sclk_low;

sys/dev/pci/drm/radeon/rs780_dpm.h

56

u32 sclk_high;

sys/dev/pci/drm/radeon/rs780_dpm.h

57

u32 flags;

sys/dev/pci/drm/radeon/rv515.c

1084

u32 *d1mode_priority_a_cnt,

sys/dev/pci/drm/radeon/rv515.c

1085

u32 *d2mode_priority_a_cnt)

sys/dev/pci/drm/radeon/rv515.c

1209

u32 tmp;

sys/dev/pci/drm/radeon/rv515.c

1210

u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;

sys/dev/pci/drm/radeon/rv515.c

1211

u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;

sys/dev/pci/drm/radeon/rv515.c

270

u32 crtc_enabled, tmp, frame_count, blackout;

sys/dev/pci/drm/radeon/rv515.c

352

u32 tmp, frame_count;

sys/dev/pci/drm/radeon/rv515.c

371

(u32)rdev->mc.vram_start);

sys/dev/pci/drm/radeon/rv515.c

373

(u32)rdev->mc.vram_start);

sys/dev/pci/drm/radeon/rv515.c

375

WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

sys/dev/pci/drm/radeon/rv515.c

46

static const u32 crtc_offsets[2] = {

sys/dev/pci/drm/radeon/rv515.c

911

u32 lb_request_fifo_depth;

sys/dev/pci/drm/radeon/rv515.c

933

u32 selected_sclk;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1001

static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

102

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

111

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1182

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

123

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1351

static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

139

u32 clock, struct rv6xx_sclk_stepping *step)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

160

u32 step_index, struct rv6xx_sclk_stepping *step)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

163

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

164

u32 fb_divider;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

165

u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

176

u32 lo_len = (step->post_divider - 2) / 2;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

177

u32 hi_len = step->post_divider - 2 - lo_len;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1821

u32 sclk, mclk;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

195

bool increasing_vco, u32 step_size)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2034

u32 current_index =

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2054

u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2059

u32 current_index =

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2077

u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2082

u32 current_index =

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2110

u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2120

u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

240

u32 low, u32 high,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

241

u32 start_index, u8 *end_index)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

246

u32 step_index = start_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

297

u32 clock, u32 index)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

306

u32 start_index, u32 end_index)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

308

u32 step_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

315

u32 index, u32 clk_s)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

322

u32 index, u32 clk_v)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

329

u32 index, bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

33

static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

34

u32 unscaled_count, u32 unit);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

340

u32 clk_s)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

346

u32 clk_v)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

370

u32 index, bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

380

u32 index, u32 divider)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

387

u32 index, u32 divider)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

394

u32 index, u32 divider)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

400

static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

410

static u32 rv6xx_clocks_per_unit(u32 unit)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

412

u32 tmp = 1 << (2 * unit);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

417

static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

418

u32 unscaled_count, u32 unit)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

420

u32 count_per_unit = rv6xx_clocks_per_unit(unit);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

425

static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

426

u32 delay_us, u32 unit)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

428

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

52

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

525

static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

527

u32 fb_divider_scale)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

533

static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

534

u32 ss_rate, u32 ss_percent,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

535

u32 fb_divider_scale)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

537

u32 fb_divider = vco_freq / ref_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

543

static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

549

u32 clock, enum r600_power_level level)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

551

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

555

u32 vco_freq, clk_v, clk_s;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

598

u32 entry, u32 clock)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

631

u32 requested_memory_clock,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

632

u32 ref_clk,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

634

u32 *vco_freq)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

638

u32 vco_freq_temp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

655

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

658

u32 vco_freq = 0, clk_v, clk_s;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

702

u32 entry, u16 voltage)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

704

u32 mask, set_pins;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

76

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

781

static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv6xx_dpm.c

782

u32 engine_clock)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

784

u32 dram_rows, dram_refresh_rate;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

785

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

797

u32 sqm_ratio;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

798

u32 arb_refresh_rate;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

799

u32 high_clock;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

840

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

90

u32 tmp;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

915

u32 rt;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

944

u32 tmp_mask, tmp_set_pins;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

983

u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |

sys/dev/pci/drm/radeon/rv6xx_dpm.h

32

u32 vco_frequency;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

33

u32 post_divider;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

37

u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];

sys/dev/pci/drm/radeon/rv6xx_dpm.h

38

u32 mclks[R600_PM_NUMBER_OF_MCLKS];

sys/dev/pci/drm/radeon/rv6xx_dpm.h

66

u32 fb_div_scale;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

67

u32 spll_ref_div;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

68

u32 mpll_ref_div;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

69

u32 bsu;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

70

u32 bsp;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

72

u32 active_auto_throttle_sources;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

74

u32 restricted_levels;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

79

u32 sclk;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

80

u32 mclk;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

82

u32 flags;

sys/dev/pci/drm/radeon/rv730_dpm.c

117

u32 engine_clock, u32 memory_clock,

sys/dev/pci/drm/radeon/rv730_dpm.c

121

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

122

u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

123

u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

124

u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;

sys/dev/pci/drm/radeon/rv730_dpm.c

125

u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;

sys/dev/pci/drm/radeon/rv730_dpm.c

126

u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;

sys/dev/pci/drm/radeon/rv730_dpm.c

127

u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;

sys/dev/pci/drm/radeon/rv730_dpm.c

129

u32 post_divider, reference_divider;

sys/dev/pci/drm/radeon/rv730_dpm.c

165

u32 vco_freq = memory_clock * post_divider;

sys/dev/pci/drm/radeon/rv730_dpm.c

169

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv730_dpm.c

170

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/rv730_dpm.c

171

u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);

sys/dev/pci/drm/radeon/rv730_dpm.c

230

u32 mpll_func_cntl = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

231

u32 mpll_func_cntl_2 = 0 ;

sys/dev/pci/drm/radeon/rv730_dpm.c

232

u32 mpll_func_cntl_3 = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

233

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

234

u32 dll_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

235

u32 spll_func_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

236

u32 spll_func_cntl_2;

sys/dev/pci/drm/radeon/rv730_dpm.c

237

u32 spll_func_cntl_3;

sys/dev/pci/drm/radeon/rv730_dpm.c

322

u32 a_t;

sys/dev/pci/drm/radeon/rv730_dpm.c

38

u32 engine_clock,

sys/dev/pci/drm/radeon/rv730_dpm.c

394

u32 arb_refresh_rate = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

395

u32 dram_timing = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

396

u32 dram_timing2 = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

397

u32 old_dram_timing = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

398

u32 old_dram_timing2 = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

43

u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

44

u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/rv730_dpm.c

45

u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/rv730_dpm.c

46

u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/rv730_dpm.c

47

u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/rv730_dpm.c

476

u32 i = use_dcodt ? 0 : 1;

sys/dev/pci/drm/radeon/rv730_dpm.c

477

u32 mc4_io_pad_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

49

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv730_dpm.c

495

u32 mc4_io_pad_cntl;

sys/dev/pci/drm/radeon/rv730_dpm.c

50

u32 reference_divider, post_divider;

sys/dev/pci/drm/radeon/rv730_dpm.c

51

u32 fbdiv;

sys/dev/pci/drm/radeon/rv730_dpm.c

69

fbdiv = (u32) tmp;

sys/dev/pci/drm/radeon/rv730_dpm.c

90

u32 vco_freq = engine_clock * post_divider;

sys/dev/pci/drm/radeon/rv730_dpm.c

94

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/rv730_dpm.c

95

u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/radeon/rv740_dpm.c

119

int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,

sys/dev/pci/drm/radeon/rv740_dpm.c

124

u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

125

u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

126

u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/rv740_dpm.c

127

u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/rv740_dpm.c

128

u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

130

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv740_dpm.c

131

u32 reference_divider;

sys/dev/pci/drm/radeon/rv740_dpm.c

132

u32 fbdiv;

sys/dev/pci/drm/radeon/rv740_dpm.c

144

fbdiv = (u32) tmp;

sys/dev/pci/drm/radeon/rv740_dpm.c

159

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/pci/drm/radeon/rv740_dpm.c

163

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/rv740_dpm.c

164

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/radeon/rv740_dpm.c

186

u32 engine_clock, u32 memory_clock,

sys/dev/pci/drm/radeon/rv740_dpm.c

190

u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

191

u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

192

u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

193

u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

194

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

195

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

196

u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;

sys/dev/pci/drm/radeon/rv740_dpm.c

197

u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;

sys/dev/pci/drm/radeon/rv740_dpm.c

199

u32 ibias;

sys/dev/pci/drm/radeon/rv740_dpm.c

200

u32 dll_speed;

sys/dev/pci/drm/radeon/rv740_dpm.c

246

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/pci/drm/radeon/rv740_dpm.c

250

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv740_dpm.c

251

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/pci/drm/radeon/rv740_dpm.c

252

u32 clk_s, clk_v;

sys/dev/pci/drm/radeon/rv740_dpm.c

32

u32 rv740_get_decoded_reference_divider(u32 encoded_ref)

sys/dev/pci/drm/radeon/rv740_dpm.c

321

u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

322

u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

323

u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

324

u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

325

u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

326

u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/rv740_dpm.c

327

u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/rv740_dpm.c

328

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

329

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/pci/drm/radeon/rv740_dpm.c

34

u32 ref = 0;

sys/dev/pci/drm/radeon/rv740_dpm.c

408

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock)

sys/dev/pci/drm/radeon/rv740_dpm.c

70

u32 dll_speed;

sys/dev/pci/drm/radeon/rv740_dpm.c

93

u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock)

sys/dev/pci/drm/radeon/rv740_dpm.c

96

u32 factor;

sys/dev/pci/drm/radeon/rv770.c

1008

u32 tmp;

sys/dev/pci/drm/radeon/rv770.c

1137

u32 tmp, i;

sys/dev/pci/drm/radeon/rv770.c

1170

u32 ta_aux_cntl;

sys/dev/pci/drm/radeon/rv770.c

1171

u32 sx_debug_1;

sys/dev/pci/drm/radeon/rv770.c

1172

u32 smx_dc_ctl0;

sys/dev/pci/drm/radeon/rv770.c

1173

u32 db_debug3;

sys/dev/pci/drm/radeon/rv770.c

1174

u32 num_gs_verts_per_thread;

sys/dev/pci/drm/radeon/rv770.c

1175

u32 vgt_gs_per_es;

sys/dev/pci/drm/radeon/rv770.c

1176

u32 gs_prim_buffer_depth = 0;

sys/dev/pci/drm/radeon/rv770.c

1177

u32 sq_ms_fifo_sizes;

sys/dev/pci/drm/radeon/rv770.c

1178

u32 sq_config;

sys/dev/pci/drm/radeon/rv770.c

1179

u32 sq_thread_resource_mgmt;

sys/dev/pci/drm/radeon/rv770.c

1180

u32 hdp_host_path_cntl;

sys/dev/pci/drm/radeon/rv770.c

1181

u32 sq_dyn_gpr_size_simd_ab_0;

sys/dev/pci/drm/radeon/rv770.c

1182

u32 gb_tiling_config = 0;

sys/dev/pci/drm/radeon/rv770.c

1183

u32 cc_gc_shader_pipe_config = 0;

sys/dev/pci/drm/radeon/rv770.c

1184

u32 mc_arb_ramcfg;

sys/dev/pci/drm/radeon/rv770.c

1185

u32 db_debug4, tmp;

sys/dev/pci/drm/radeon/rv770.c

1186

u32 inactive_pipes, shader_pipe_config;

sys/dev/pci/drm/radeon/rv770.c

1187

u32 disabled_rb_mask;

sys/dev/pci/drm/radeon/rv770.c

139

static const u32 r7xx_golden_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

154

static const u32 r7xx_golden_dyn_gpr_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

1644

u32 tmp;

sys/dev/pci/drm/radeon/rv770.c

166

static const u32 rv770_golden_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

175

static const u32 rv770ce_golden_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

186

static const u32 rv770_mgcg_init[] = {

sys/dev/pci/drm/radeon/rv770.c

2022

u32 link_width_cntl, lanes, speed_cntl, tmp;

sys/dev/pci/drm/radeon/rv770.c

343

static const u32 rv710_golden_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

352

static const u32 rv710_mgcg_init[] = {

sys/dev/pci/drm/radeon/rv770.c

410

static const u32 rv730_golden_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

420

static const u32 rv730_mgcg_init[] = {

sys/dev/pci/drm/radeon/rv770.c

52

int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/pci/drm/radeon/rv770.c

54

int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/pci/drm/radeon/rv770.c

541

static const u32 rv740_golden_registers[] = {

sys/dev/pci/drm/radeon/rv770.c

577

static const u32 rv740_mgcg_init[] = {

sys/dev/pci/drm/radeon/rv770.c

718

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

721

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/pci/drm/radeon/rv770.c

725

(const u32)ARRAY_SIZE(rv770ce_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

729

(const u32)ARRAY_SIZE(rv770_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

732

(const u32)ARRAY_SIZE(rv770_mgcg_init));

sys/dev/pci/drm/radeon/rv770.c

737

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

740

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/pci/drm/radeon/rv770.c

743

(const u32)ARRAY_SIZE(rv730_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

746

(const u32)ARRAY_SIZE(rv730_mgcg_init));

sys/dev/pci/drm/radeon/rv770.c

751

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

754

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/pci/drm/radeon/rv770.c

757

(const u32)ARRAY_SIZE(rv710_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

760

(const u32)ARRAY_SIZE(rv710_mgcg_init));

sys/dev/pci/drm/radeon/rv770.c

765

(const u32)ARRAY_SIZE(rv740_golden_registers));

sys/dev/pci/drm/radeon/rv770.c

768

(const u32)ARRAY_SIZE(rv740_mgcg_init));

sys/dev/pci/drm/radeon/rv770.c

786

u32 rv770_get_xclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv770.c

788

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv770.c

789

u32 tmp = RREG32(CG_CLKPIN_CNTL);

sys/dev/pci/drm/radeon/rv770.c

804

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rv770.c

826

(u32)crtc_base);

sys/dev/pci/drm/radeon/rv770.c

828

(u32)crtc_base);

sys/dev/pci/drm/radeon/rv770.c

855

u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>

sys/dev/pci/drm/radeon/rv770.c

896

u32 tmp;

sys/dev/pci/drm/radeon/rv770.c

932

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/rv770.c

946

u32 tmp;

sys/dev/pci/drm/radeon/rv770.c

980

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dma.c

51

u32 size_in_dw, cur_size_in_dw;

sys/dev/pci/drm/radeon/rv770_dpm.c

1030

u32 a_t;

sys/dev/pci/drm/radeon/rv770_dpm.c

104

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

116

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

1237

u32 steps = 0;

sys/dev/pci/drm/radeon/rv770_dpm.c

1239

u32 i;

sys/dev/pci/drm/radeon/rv770_dpm.c

1251

u32 gpio_pins, gpio_mask;

sys/dev/pci/drm/radeon/rv770_dpm.c

1276

static u32 rv770_get_mclk_split_point(struct atom_memory_info *memory_info)

sys/dev/pci/drm/radeon/rv770_dpm.c

1287

u32 gpio_pins, gpio_mask;

sys/dev/pci/drm/radeon/rv770_dpm.c

1345

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/rv770_dpm.c

150

u32 mgcg_cgtt_local0;

sys/dev/pci/drm/radeon/rv770_dpm.c

1566

u32 sw_smio_index, vid_smio_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.c

1594

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

1609

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

1704

u32 voltage_response_time, backbias_response_time;

sys/dev/pci/drm/radeon/rv770_dpm.c

1705

u32 acpi_delay_time, vbi_time_out;

sys/dev/pci/drm/radeon/rv770_dpm.c

1706

u32 vddc_dly, bb_dly, acpi_dly, vbi_dly;

sys/dev/pci/drm/radeon/rv770_dpm.c

1707

u32 reference_clock;

sys/dev/pci/drm/radeon/rv770_dpm.c

1709

voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;

sys/dev/pci/drm/radeon/rv770_dpm.c

1710

backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;

sys/dev/pci/drm/radeon/rv770_dpm.c

1814

static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/pci/drm/radeon/rv770_dpm.c

2182

u32 sclk, mclk;

sys/dev/pci/drm/radeon/rv770_dpm.c

237

u16 reg_offset, u32 *value)

sys/dev/pci/drm/radeon/rv770_dpm.c

2473

u32 current_index =

sys/dev/pci/drm/radeon/rv770_dpm.c

248

u16 reg_offset, u32 value)

sys/dev/pci/drm/radeon/rv770_dpm.c

2497

u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv770_dpm.c

2502

u32 current_index =

sys/dev/pci/drm/radeon/rv770_dpm.c

2519

u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv770_dpm.c

2524

u32 current_index =

sys/dev/pci/drm/radeon/rv770_dpm.c

2552

u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/rv770_dpm.c

2562

u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/rv770_dpm.c

2574

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/pci/drm/radeon/rv770_dpm.c

2575

u32 switch_limit = 200; /* 300 */

sys/dev/pci/drm/radeon/rv770_dpm.c

268

u32 a_t;

sys/dev/pci/drm/radeon/rv770_dpm.c

319

static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock,

sys/dev/pci/drm/radeon/rv770_dpm.c

320

u32 reference_clock,

sys/dev/pci/drm/radeon/rv770_dpm.c

323

u32 *clkf,

sys/dev/pci/drm/radeon/rv770_dpm.c

324

u32 *clkfrac)

sys/dev/pci/drm/radeon/rv770_dpm.c

326

u32 post_divider, reference_divider, feedback_divider8;

sys/dev/pci/drm/radeon/rv770_dpm.c

327

u32 fyclk;

sys/dev/pci/drm/radeon/rv770_dpm.c

344

static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv)

sys/dev/pci/drm/radeon/rv770_dpm.c

372

u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)

sys/dev/pci/drm/radeon/rv770_dpm.c

388

u32 engine_clock, u32 memory_clock,

sys/dev/pci/drm/radeon/rv770_dpm.c

393

u32 mpll_ad_func_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

395

u32 mpll_ad_func_cntl_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

397

u32 mpll_dq_func_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

399

u32 mpll_dq_func_cntl_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

401

u32 mclk_pwrmgt_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

403

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.c

405

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv770_dpm.c

406

u32 clkf, clkfrac;

sys/dev/pci/drm/radeon/rv770_dpm.c

407

u32 postdiv_yclk;

sys/dev/pci/drm/radeon/rv770_dpm.c

408

u32 ibias;

sys/dev/pci/drm/radeon/rv770_dpm.c

486

u32 engine_clock,

sys/dev/pci/drm/radeon/rv770_dpm.c

491

u32 spll_func_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

493

u32 spll_func_cntl_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

495

u32 spll_func_cntl_3 =

sys/dev/pci/drm/radeon/rv770_dpm.c

497

u32 cg_spll_spread_spectrum =

sys/dev/pci/drm/radeon/rv770_dpm.c

499

u32 cg_spll_spread_spectrum_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

502

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv770_dpm.c

503

u32 reference_divider, post_divider;

sys/dev/pci/drm/radeon/rv770_dpm.c

504

u32 fbdiv;

sys/dev/pci/drm/radeon/rv770_dpm.c

521

fbdiv = (u32) tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

541

u32 vco_freq = engine_clock * post_divider;

sys/dev/pci/drm/radeon/rv770_dpm.c

545

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/rv770_dpm.c

546

u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/radeon/rv770_dpm.c

593

int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/pci/drm/radeon/rv770_dpm.c

723

u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv770_dpm.c

724

u32 engine_clock)

sys/dev/pci/drm/radeon/rv770_dpm.c

726

u32 dram_rows;

sys/dev/pci/drm/radeon/rv770_dpm.c

727

u32 dram_refresh_rate;

sys/dev/pci/drm/radeon/rv770_dpm.c

728

u32 mc_arb_rfsh_rate;

sys/dev/pci/drm/radeon/rv770_dpm.c

729

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

74

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

745

u32 sqm_ratio;

sys/dev/pci/drm/radeon/rv770_dpm.c

746

u32 arb_refresh_rate;

sys/dev/pci/drm/radeon/rv770_dpm.c

747

u32 high_clock;

sys/dev/pci/drm/radeon/rv770_dpm.c

820

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/rv770_dpm.c

881

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/rv770_dpm.c

921

u32 mpll_ad_func_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

923

u32 mpll_ad_func_cntl_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

925

u32 mpll_dq_func_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

927

u32 mpll_dq_func_cntl_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

929

u32 spll_func_cntl =

sys/dev/pci/drm/radeon/rv770_dpm.c

931

u32 spll_func_cntl_2 =

sys/dev/pci/drm/radeon/rv770_dpm.c

933

u32 spll_func_cntl_3 =

sys/dev/pci/drm/radeon/rv770_dpm.c

935

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.c

936

u32 dll_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.c

95

u32 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.h

100

u32 mvdd_mask_low;

sys/dev/pci/drm/radeon/rv770_dpm.h

101

u32 mvdd_split_frequency;

sys/dev/pci/drm/radeon/rv770_dpm.h

102

u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];

sys/dev/pci/drm/radeon/rv770_dpm.h

109

u32 mclk_odt_threshold;

sys/dev/pci/drm/radeon/rv770_dpm.h

113

u32 boot_sclk;

sys/dev/pci/drm/radeon/rv770_dpm.h

115

u32 ref_div;

sys/dev/pci/drm/radeon/rv770_dpm.h

116

u32 active_auto_throttle_sources;

sys/dev/pci/drm/radeon/rv770_dpm.h

117

u32 mclk_stutter_mode_threshold;

sys/dev/pci/drm/radeon/rv770_dpm.h

118

u32 mclk_strobe_mode_threshold;

sys/dev/pci/drm/radeon/rv770_dpm.h

119

u32 mclk_edc_enable_threshold;

sys/dev/pci/drm/radeon/rv770_dpm.h

120

u32 bsp;

sys/dev/pci/drm/radeon/rv770_dpm.h

121

u32 bsu;

sys/dev/pci/drm/radeon/rv770_dpm.h

122

u32 pbsp;

sys/dev/pci/drm/radeon/rv770_dpm.h

123

u32 pbsu;

sys/dev/pci/drm/radeon/rv770_dpm.h

124

u32 dsp;

sys/dev/pci/drm/radeon/rv770_dpm.h

125

u32 psp;

sys/dev/pci/drm/radeon/rv770_dpm.h

126

u32 asi;

sys/dev/pci/drm/radeon/rv770_dpm.h

127

u32 pasi;

sys/dev/pci/drm/radeon/rv770_dpm.h

128

u32 vrc;

sys/dev/pci/drm/radeon/rv770_dpm.h

129

u32 restricted_levels;

sys/dev/pci/drm/radeon/rv770_dpm.h

130

u32 rlp;

sys/dev/pci/drm/radeon/rv770_dpm.h

131

u32 rmp;

sys/dev/pci/drm/radeon/rv770_dpm.h

132

u32 lhp;

sys/dev/pci/drm/radeon/rv770_dpm.h

133

u32 lmp;

sys/dev/pci/drm/radeon/rv770_dpm.h

143

u32 sclk;

sys/dev/pci/drm/radeon/rv770_dpm.h

144

u32 mclk;

sys/dev/pci/drm/radeon/rv770_dpm.h

147

u32 flags;

sys/dev/pci/drm/radeon/rv770_dpm.h

181

u32 engine_clock,

sys/dev/pci/drm/radeon/rv770_dpm.h

184

u32 engine_clock, u32 memory_clock,

sys/dev/pci/drm/radeon/rv770_dpm.h

202

int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,

sys/dev/pci/drm/radeon/rv770_dpm.h

205

u32 engine_clock, u32 memory_clock,

sys/dev/pci/drm/radeon/rv770_dpm.h

212

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);

sys/dev/pci/drm/radeon/rv770_dpm.h

213

u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);

sys/dev/pci/drm/radeon/rv770_dpm.h

214

u32 rv740_get_decoded_reference_divider(u32 encoded_ref);

sys/dev/pci/drm/radeon/rv770_dpm.h

217

u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);

sys/dev/pci/drm/radeon/rv770_dpm.h

220

int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/pci/drm/radeon/rv770_dpm.h

226

u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv770_dpm.h

227

u32 engine_clock);

sys/dev/pci/drm/radeon/rv770_dpm.h

283

u16 reg_offset, u32 value);

sys/dev/pci/drm/radeon/rv770_dpm.h

30

u32 cg_spll_func_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

31

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/rv770_dpm.h

32

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/rv770_dpm.h

33

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/rv770_dpm.h

34

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/rv770_dpm.h

35

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

36

u32 mpll_ad_func_cntl_2;

sys/dev/pci/drm/radeon/rv770_dpm.h

37

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

38

u32 mpll_dq_func_cntl_2;

sys/dev/pci/drm/radeon/rv770_dpm.h

39

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

40

u32 dll_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

41

u32 mpll_ss1;

sys/dev/pci/drm/radeon/rv770_dpm.h

42

u32 mpll_ss2;

sys/dev/pci/drm/radeon/rv770_dpm.h

46

u32 cg_spll_func_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

47

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/rv770_dpm.h

48

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/rv770_dpm.h

49

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/rv770_dpm.h

50

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/rv770_dpm.h

51

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

52

u32 dll_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

53

u32 mpll_func_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

54

u32 mpll_func_cntl2;

sys/dev/pci/drm/radeon/rv770_dpm.h

55

u32 mpll_func_cntl3;

sys/dev/pci/drm/radeon/rv770_dpm.h

56

u32 mpll_ss;

sys/dev/pci/drm/radeon/rv770_dpm.h

57

u32 mpll_ss2;

sys/dev/pci/drm/radeon/rv770_dpm.h

69

u32 low_smio;

sys/dev/pci/drm/radeon/rv770_dpm.h

97

u32 s0_vid_lower_smio_cntl;

sys/dev/pci/drm/radeon/rv770_dpm.h

99

u32 vddc_mask_low;

sys/dev/pci/drm/radeon/rv770_smc.c

268

u32 addr;

sys/dev/pci/drm/radeon/rv770_smc.c

288

u32 data, original_data, extra_shift;

sys/dev/pci/drm/radeon/rv770_smc.c

351

u32 smc_first_vector, const u8 *src,

sys/dev/pci/drm/radeon/rv770_smc.c

352

u32 byte_count)

sys/dev/pci/drm/radeon/rv770_smc.c

354

u32 tmp, i;

sys/dev/pci/drm/radeon/rv770_smc.c

402

u32 tmp;

sys/dev/pci/drm/radeon/rv770_smc.c

414

u32 tmp;

sys/dev/pci/drm/radeon/rv770_smc.c

592

u16 smc_address, u32 *value, u16 limit)

sys/dev/pci/drm/radeon/rv770_smc.c

607

u16 smc_address, u32 value, u16 limit)

sys/dev/pci/drm/radeon/rv770_smc.h

192

u16 smc_address, u32 *value, u16 limit);

sys/dev/pci/drm/radeon/rv770_smc.h

194

u16 smc_address, u32 value, u16 limit);

sys/dev/pci/drm/radeon/si.c

1006

static const u32 hainan_mgcg_cgcg_init[] = {

sys/dev/pci/drm/radeon/si.c

1082

static u32 verde_pg_init[] = {

sys/dev/pci/drm/radeon/si.c

1214

(const u32)ARRAY_SIZE(tahiti_golden_registers));

sys/dev/pci/drm/radeon/si.c

1217

(const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));

sys/dev/pci/drm/radeon/si.c

1220

(const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/si.c

1223

(const u32)ARRAY_SIZE(tahiti_golden_registers2));

sys/dev/pci/drm/radeon/si.c

1228

(const u32)ARRAY_SIZE(pitcairn_golden_registers));

sys/dev/pci/drm/radeon/si.c

1231

(const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));

sys/dev/pci/drm/radeon/si.c

1234

(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/si.c

1239

(const u32)ARRAY_SIZE(verde_golden_registers));

sys/dev/pci/drm/radeon/si.c

1242

(const u32)ARRAY_SIZE(verde_golden_rlc_registers));

sys/dev/pci/drm/radeon/si.c

1245

(const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/si.c

1248

(const u32)ARRAY_SIZE(verde_pg_init));

sys/dev/pci/drm/radeon/si.c

1253

(const u32)ARRAY_SIZE(oland_golden_registers));

sys/dev/pci/drm/radeon/si.c

1256

(const u32)ARRAY_SIZE(oland_golden_rlc_registers));

sys/dev/pci/drm/radeon/si.c

1259

(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/si.c

1264

(const u32)ARRAY_SIZE(hainan_golden_registers));

sys/dev/pci/drm/radeon/si.c

1267

(const u32)ARRAY_SIZE(hainan_golden_registers2));

sys/dev/pci/drm/radeon/si.c

1270

(const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));

sys/dev/pci/drm/radeon/si.c

128

static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);

sys/dev/pci/drm/radeon/si.c

1288

u32 reg, u32 *val)

sys/dev/pci/drm/radeon/si.c

1318

u32 si_get_xclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si.c

1320

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/si.c

1321

u32 tmp;

sys/dev/pci/drm/radeon/si.c

1337

u32 temp;

sys/dev/pci/drm/radeon/si.c

1355

static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/si.c

1394

static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/si.c

141

static const u32 crtc_offsets[] = {

sys/dev/pci/drm/radeon/si.c

1433

static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/si.c

1472

static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/si.c

150

static const u32 si_disp_int_status[] = {

sys/dev/pci/drm/radeon/si.c

1511

static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/pci/drm/radeon/si.c

1555

u32 running;

sys/dev/pci/drm/radeon/si.c

1556

u32 *io_mc_regs = NULL;

sys/dev/pci/drm/radeon/si.c

1579

io_mc_regs = (u32 *)&tahiti_io_mc_regs;

sys/dev/pci/drm/radeon/si.c

1583

io_mc_regs = (u32 *)&pitcairn_io_mc_regs;

sys/dev/pci/drm/radeon/si.c

1588

io_mc_regs = (u32 *)&verde_io_mc_regs;

sys/dev/pci/drm/radeon/si.c

1592

io_mc_regs = (u32 *)&oland_io_mc_regs;

sys/dev/pci/drm/radeon/si.c

1596

io_mc_regs = (u32 *)&hainan_io_mc_regs;

sys/dev/pci/drm/radeon/si.c

163

static const u32 verde_rlc_save_restore_register_list[] = {

sys/dev/pci/drm/radeon/si.c

1947

static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/si.c

1952

u32 tmp, buffer_alloc, i;

sys/dev/pci/drm/radeon/si.c

1953

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/pci/drm/radeon/si.c

2006

static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si.c

2008

u32 tmp = RREG32(MC_SHARED_CHMAP);

sys/dev/pci/drm/radeon/si.c

2034

u32 dram_channels; /* number of dram channels */

sys/dev/pci/drm/radeon/si.c

2035

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/pci/drm/radeon/si.c

2036

u32 sclk; /* engine clock in kHz */

sys/dev/pci/drm/radeon/si.c

2037

u32 disp_clk; /* display clock in kHz */

sys/dev/pci/drm/radeon/si.c

2038

u32 src_width; /* viewport width */

sys/dev/pci/drm/radeon/si.c

2039

u32 active_time; /* active display time in ns */

sys/dev/pci/drm/radeon/si.c

2040

u32 blank_time; /* blank time in ns */

sys/dev/pci/drm/radeon/si.c

2043

u32 num_heads; /* number of active crtcs */

sys/dev/pci/drm/radeon/si.c

2044

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/pci/drm/radeon/si.c

2045

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/pci/drm/radeon/si.c

2046

u32 vtaps; /* vertical scaler taps */

sys/dev/pci/drm/radeon/si.c

2049

static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2069

static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2089

static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2109

static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2114

static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2120

u32 min_bandwidth;

sys/dev/pci/drm/radeon/si.c

2146

static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2149

u32 dram_bandwidth = dce6_dram_bandwidth(wm);

sys/dev/pci/drm/radeon/si.c

2150

u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);

sys/dev/pci/drm/radeon/si.c

2151

u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);

sys/dev/pci/drm/radeon/si.c

2156

static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2180

static u32 dce6_latency_watermark(struct dce6_wm_params *wm)

sys/dev/pci/drm/radeon/si.c

2183

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/pci/drm/radeon/si.c

2184

u32 available_bandwidth = dce6_available_bandwidth(wm);

sys/dev/pci/drm/radeon/si.c

2185

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/pci/drm/radeon/si.c

2186

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/pci/drm/radeon/si.c

2187

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/pci/drm/radeon/si.c

2188

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/pci/drm/radeon/si.c

2190

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/pci/drm/radeon/si.c

2191

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/pci/drm/radeon/si.c

2192

u32 tmp, dmif_size = 12288;

sys/dev/pci/drm/radeon/si.c

2250

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/pci/drm/radeon/si.c

2251

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/pci/drm/radeon/si.c

2252

u32 latency_tolerant_lines;

sys/dev/pci/drm/radeon/si.c

2253

u32 latency_hiding;

sys/dev/pci/drm/radeon/si.c

2276

u32 lb_size, u32 num_heads)

sys/dev/pci/drm/radeon/si.c

2280

u32 dram_channels;

sys/dev/pci/drm/radeon/si.c

2281

u32 active_time;

sys/dev/pci/drm/radeon/si.c

2282

u32 line_time = 0;

sys/dev/pci/drm/radeon/si.c

2283

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/pci/drm/radeon/si.c

2284

u32 priority_a_mark = 0, priority_b_mark = 0;

sys/dev/pci/drm/radeon/si.c

2285

u32 priority_a_cnt = PRIORITY_OFF;

sys/dev/pci/drm/radeon/si.c

2286

u32 priority_b_cnt = PRIORITY_OFF;

sys/dev/pci/drm/radeon/si.c

2287

u32 tmp, arb_control3;

sys/dev/pci/drm/radeon/si.c

2291

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/radeon/si.c

2292

(u32)mode->clock);

sys/dev/pci/drm/radeon/si.c

2293

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/radeon/si.c

2294

(u32)mode->clock);

sys/dev/pci/drm/radeon/si.c

2295

line_time = min(line_time, (u32)65535);

sys/dev/pci/drm/radeon/si.c

2359

latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);

sys/dev/pci/drm/radeon/si.c

2361

latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);

sys/dev/pci/drm/radeon/si.c

2444

u32 num_heads = 0, lb_size;

sys/dev/pci/drm/radeon/si.c

2471

u32 *tile = rdev->config.si.tile_mode_array;

sys/dev/pci/drm/radeon/si.c

2472

const u32 num_tile_mode_states =

sys/dev/pci/drm/radeon/si.c

2474

u32 reg_offset, split_equal_to_row_size;

sys/dev/pci/drm/radeon/si.c

2928

u32 se_num, u32 sh_num)

sys/dev/pci/drm/radeon/si.c

2930

u32 data = INSTANCE_BROADCAST_WRITES;

sys/dev/pci/drm/radeon/si.c

2943

static u32 si_create_bitmask(u32 bit_width)

sys/dev/pci/drm/radeon/si.c

2945

u32 i, mask = 0;

sys/dev/pci/drm/radeon/si.c

2954

static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)

sys/dev/pci/drm/radeon/si.c

2956

u32 data, mask;

sys/dev/pci/drm/radeon/si.c

2973

u32 se_num, u32 sh_per_se,

sys/dev/pci/drm/radeon/si.c

2974

u32 cu_per_sh)

sys/dev/pci/drm/radeon/si.c

2977

u32 data, mask, active_cu;

sys/dev/pci/drm/radeon/si.c

2999

static u32 si_get_rb_disabled(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/si.c

3000

u32 max_rb_num_per_se,

sys/dev/pci/drm/radeon/si.c

3001

u32 sh_per_se)

sys/dev/pci/drm/radeon/si.c

3003

u32 data, mask;

sys/dev/pci/drm/radeon/si.c

3020

u32 se_num, u32 sh_per_se,

sys/dev/pci/drm/radeon/si.c

3021

u32 max_rb_num_per_se)

sys/dev/pci/drm/radeon/si.c

3024

u32 data, mask;

sys/dev/pci/drm/radeon/si.c

3025

u32 disabled_rbs = 0;

sys/dev/pci/drm/radeon/si.c

3026

u32 enabled_rbs = 0;

sys/dev/pci/drm/radeon/si.c

3071

u32 gb_addr_config = 0;

sys/dev/pci/drm/radeon/si.c

3072

u32 mc_arb_ramcfg;

sys/dev/pci/drm/radeon/si.c

3073

u32 sx_debug_1;

sys/dev/pci/drm/radeon/si.c

3074

u32 hdp_host_path_cntl;

sys/dev/pci/drm/radeon/si.c

3075

u32 tmp;

sys/dev/pci/drm/radeon/si.c

3384

u32 header;

sys/dev/pci/drm/radeon/si.c

3393

u32 next_rptr;

sys/dev/pci/drm/radeon/si.c

3473

u32 fw_size;

sys/dev/pci/drm/radeon/si.c

3631

u32 tmp;

sys/dev/pci/drm/radeon/si.c

3632

u32 rb_bufsz;

sys/dev/pci/drm/radeon/si.c

3754

u32 si_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si.c

3756

u32 reset_mask = 0;

sys/dev/pci/drm/radeon/si.c

3757

u32 tmp;

sys/dev/pci/drm/radeon/si.c

3835

static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/pci/drm/radeon/si.c

3838

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/pci/drm/radeon/si.c

3839

u32 tmp;

sys/dev/pci/drm/radeon/si.c

384

static const u32 tahiti_golden_rlc_registers[] = {

sys/dev/pci/drm/radeon/si.c

393

static const u32 tahiti_golden_registers[] = {

sys/dev/pci/drm/radeon/si.c

3969

u32 tmp, i;

sys/dev/pci/drm/radeon/si.c

3996

u32 tmp;

sys/dev/pci/drm/radeon/si.c

4018

u32 tmp, i;

sys/dev/pci/drm/radeon/si.c

4069

u32 reset_mask;

sys/dev/pci/drm/radeon/si.c

4109

u32 reset_mask = si_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/si.c

4124

u32 tmp;

sys/dev/pci/drm/radeon/si.c

4188

u32 tmp;

sys/dev/pci/drm/radeon/si.c

427

static const u32 tahiti_golden_registers2[] = {

sys/dev/pci/drm/radeon/si.c

4300

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/si.c

431

static const u32 pitcairn_golden_rlc_registers[] = {

sys/dev/pci/drm/radeon/si.c

4328

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/pci/drm/radeon/si.c

439

static const u32 pitcairn_golden_registers[] = {

sys/dev/pci/drm/radeon/si.c

4391

static bool si_vm_reg_valid(u32 reg)

sys/dev/pci/drm/radeon/si.c

4438

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/pci/drm/radeon/si.c

4459

static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)

sys/dev/pci/drm/radeon/si.c

4461

u32 start_reg, reg, i;

sys/dev/pci/drm/radeon/si.c

4462

u32 command = ib[idx + 4];

sys/dev/pci/drm/radeon/si.c

4463

u32 info = ib[idx + 1];

sys/dev/pci/drm/radeon/si.c

4464

u32 idx_value = ib[idx];

sys/dev/pci/drm/radeon/si.c

4511

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/pci/drm/radeon/si.c

4514

u32 idx = pkt->idx + 1;

sys/dev/pci/drm/radeon/si.c

4515

u32 idx_value = ib[idx];

sys/dev/pci/drm/radeon/si.c

4516

u32 start_reg, end_reg, reg, i;

sys/dev/pci/drm/radeon/si.c

4629

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/pci/drm/radeon/si.c

4632

u32 idx = pkt->idx + 1;

sys/dev/pci/drm/radeon/si.c

4633

u32 idx_value = ib[idx];

sys/dev/pci/drm/radeon/si.c

4634

u32 start_reg, reg, i;

sys/dev/pci/drm/radeon/si.c

469

static const u32 verde_golden_rlc_registers[] = {

sys/dev/pci/drm/radeon/si.c

4719

u32 idx = 0, i;

sys/dev/pci/drm/radeon/si.c

477

static const u32 verde_golden_registers[] = {

sys/dev/pci/drm/radeon/si.c

4802

u32 status, u32 addr)

sys/dev/pci/drm/radeon/si.c

4804

u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;

sys/dev/pci/drm/radeon/si.c

4805

u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

sys/dev/pci/drm/radeon/si.c

4806

u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

sys/dev/pci/drm/radeon/si.c

5128

u32 tmp = RREG32(CP_INT_CNTL_RING0);

sys/dev/pci/drm/radeon/si.c

5129

u32 mask;

sys/dev/pci/drm/radeon/si.c

5154

u32 tmp, tmp2;

sys/dev/pci/drm/radeon/si.c

5179

u32 tmp = RREG32(UVD_CGC_CTRL);

sys/dev/pci/drm/radeon/si.c

5185

static u32 si_halt_rlc(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si.c

5187

u32 data, orig;

sys/dev/pci/drm/radeon/si.c

5201

static void si_update_rlc(struct radeon_device *rdev, u32 rlc)

sys/dev/pci/drm/radeon/si.c

5203

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5212

u32 data, orig;

sys/dev/pci/drm/radeon/si.c

5225

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5237

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5261

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5279

static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)

sys/dev/pci/drm/radeon/si.c

5281

u32 mask = 0, tmp, tmp1;

sys/dev/pci/drm/radeon/si.c

5304

u32 i, j, k, active_cu_number = 0;

sys/dev/pci/drm/radeon/si.c

5305

u32 mask, counter, cu_bitmap;

sys/dev/pci/drm/radeon/si.c

5306

u32 tmp = 0;

sys/dev/pci/drm/radeon/si.c

532

static const u32 oland_golden_rlc_registers[] = {

sys/dev/pci/drm/radeon/si.c

5338

u32 data, orig, tmp;

sys/dev/pci/drm/radeon/si.c

5378

u32 data, orig, tmp = 0;

sys/dev/pci/drm/radeon/si.c

540

static const u32 oland_golden_registers[] = {

sys/dev/pci/drm/radeon/si.c

5434

u32 orig, data, tmp;

sys/dev/pci/drm/radeon/si.c

5463

static const u32 mc_cg_registers[] =

sys/dev/pci/drm/radeon/si.c

5480

u32 orig, data;

sys/dev/pci/drm/radeon/si.c

5497

u32 orig, data;

sys/dev/pci/drm/radeon/si.c

5513

u32 orig, data, offset;

sys/dev/pci/drm/radeon/si.c

5550

u32 orig, data;

sys/dev/pci/drm/radeon/si.c

5568

u32 orig, data;

sys/dev/pci/drm/radeon/si.c

5584

u32 orig, data;

sys/dev/pci/drm/radeon/si.c

5598

u32 block, bool enable)

sys/dev/pci/drm/radeon/si.c

5663

u32 si_get_csb_size(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si.c

5665

u32 count = 0;

sys/dev/pci/drm/radeon/si.c

5695

void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)

sys/dev/pci/drm/radeon/si.c

5697

u32 count = 0, i;

sys/dev/pci/drm/radeon/si.c

570

static const u32 hainan_golden_registers[] = {

sys/dev/pci/drm/radeon/si.c

5789

u32 tmp = RREG32(GRBM_SOFT_RESET);

sys/dev/pci/drm/radeon/si.c

5819

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5830

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5847

u32 i;

sys/dev/pci/drm/radeon/si.c

5873

u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;

sys/dev/pci/drm/radeon/si.c

5902

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/radeon/si.c

5903

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/radeon/si.c

5914

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/pci/drm/radeon/si.c

5915

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/pci/drm/radeon/si.c

5931

u32 tmp;

sys/dev/pci/drm/radeon/si.c

5962

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/pci/drm/radeon/si.c

598

static const u32 hainan_golden_registers2[] = {

sys/dev/pci/drm/radeon/si.c

602

static const u32 tahiti_mgcg_cgcg_init[] = {

sys/dev/pci/drm/radeon/si.c

6033

u32 cp_int_cntl;

sys/dev/pci/drm/radeon/si.c

6034

u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;

sys/dev/pci/drm/radeon/si.c

6035

u32 grbm_int_cntl = 0;

sys/dev/pci/drm/radeon/si.c

6036

u32 dma_cntl, dma_cntl1;

sys/dev/pci/drm/radeon/si.c

6037

u32 thermal_int = 0;

sys/dev/pci/drm/radeon/si.c

6128

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/pci/drm/radeon/si.c

6129

u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;

sys/dev/pci/drm/radeon/si.c

6190

static inline u32 si_get_ih_wptr(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si.c

6192

u32 wptr, tmp;

sys/dev/pci/drm/radeon/si.c

6227

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/pci/drm/radeon/si.c

6228

u32 crtc_idx, hpd_idx;

sys/dev/pci/drm/radeon/si.c

6229

u32 mask;

sys/dev/pci/drm/radeon/si.c

6230

u32 wptr;

sys/dev/pci/drm/radeon/si.c

6231

u32 rptr;

sys/dev/pci/drm/radeon/si.c

6232

u32 src_id, src_data, ring_id;

sys/dev/pci/drm/radeon/si.c

6233

u32 ring_index;

sys/dev/pci/drm/radeon/si.c

6237

u32 status, addr;

sys/dev/pci/drm/radeon/si.c

6628

(u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);

sys/dev/pci/drm/radeon/si.c

6977

int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/pci/drm/radeon/si.c

7070

u32 speed_cntl, current_data_rate;

sys/dev/pci/drm/radeon/si.c

7119

u32 max_lw, current_lw, tmp;

sys/dev/pci/drm/radeon/si.c

7228

u32 data, orig;

sys/dev/pci/drm/radeon/si.c

731

static const u32 pitcairn_mgcg_cgcg_init[] = {

sys/dev/pci/drm/radeon/si.c

7357

u32 lnkcap;

sys/dev/pci/drm/radeon/si.c

7462

int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

sys/dev/pci/drm/radeon/si.c

828

static const u32 verde_mgcg_cgcg_init[] = {

sys/dev/pci/drm/radeon/si.c

927

static const u32 oland_mgcg_cgcg_init[] = {

sys/dev/pci/drm/radeon/si.h

31

u32 si_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/si.h

35

u32 si_get_csb_size(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/si.h

36

void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);

sys/dev/pci/drm/radeon/si_blit_shaders.h

249

static const u32 si_default_size = ARRAY_SIZE(si_default_state);

sys/dev/pci/drm/radeon/si_blit_shaders.h

28

static const u32 si_default_state[] = {

sys/dev/pci/drm/radeon/si_dma.c

239

u32 size_in_bytes, cur_size_in_bytes;

sys/dev/pci/drm/radeon/si_dma.c

42

u32 reset_mask = si_gpu_check_soft_reset(rdev);

sys/dev/pci/drm/radeon/si_dma.c

43

u32 mask;

sys/dev/pci/drm/radeon/si_dpm.c

1688

u16 reg_offset, u32 value);

sys/dev/pci/drm/radeon/si_dpm.c

1693

u32 engine_clock,

sys/dev/pci/drm/radeon/si_dpm.c

1707

u16 v, s32 t, u32 ileakage, u32 *leakage)

sys/dev/pci/drm/radeon/si_dpm.c

1737

u32 i_leakage,

sys/dev/pci/drm/radeon/si_dpm.c

1738

u32 *leakage)

sys/dev/pci/drm/radeon/si_dpm.c

1744

const u32 fixed_kt, u16 v,

sys/dev/pci/drm/radeon/si_dpm.c

1745

u32 ileakage, u32 *leakage)

sys/dev/pci/drm/radeon/si_dpm.c

1763

const u32 fixed_kt,

sys/dev/pci/drm/radeon/si_dpm.c

1765

u32 i_leakage,

sys/dev/pci/drm/radeon/si_dpm.c

1766

u32 *leakage)

sys/dev/pci/drm/radeon/si_dpm.c

1775

u32 p_limit1 = rdev->pm.dpm.tdp_limit;

sys/dev/pci/drm/radeon/si_dpm.c

1776

u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;

sys/dev/pci/drm/radeon/si_dpm.c

1777

u32 k = dte_data->k;

sys/dev/pci/drm/radeon/si_dpm.c

1778

u32 t_max = dte_data->max_t;

sys/dev/pci/drm/radeon/si_dpm.c

1779

u32 t_split[5] = { 10, 15, 20, 25, 30 };

sys/dev/pci/drm/radeon/si_dpm.c

1780

u32 t_0 = dte_data->t0;

sys/dev/pci/drm/radeon/si_dpm.c

1781

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

1788

(t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /

sys/dev/pci/drm/radeon/si_dpm.c

1789

(p_limit2 * (u32)100);

sys/dev/pci/drm/radeon/si_dpm.c

2028

static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si_dpm.c

2033

static u32 si_calculate_cac_wintime(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si_dpm.c

2035

u32 xclk;

sys/dev/pci/drm/radeon/si_dpm.c

2036

u32 wintime;

sys/dev/pci/drm/radeon/si_dpm.c

2037

u32 cac_window;

sys/dev/pci/drm/radeon/si_dpm.c

2038

u32 cac_window_size;

sys/dev/pci/drm/radeon/si_dpm.c

2053

static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)

sys/dev/pci/drm/radeon/si_dpm.c

2060

u32 tdp_adjustment,

sys/dev/pci/drm/radeon/si_dpm.c

2061

u32 *tdp_limit,

sys/dev/pci/drm/radeon/si_dpm.c

2062

u32 *near_tdp_limit)

sys/dev/pci/drm/radeon/si_dpm.c

2064

u32 adjustment_delta, max_tdp_limit;

sys/dev/pci/drm/radeon/si_dpm.c

2066

if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)

sys/dev/pci/drm/radeon/si_dpm.c

2101

u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);

sys/dev/pci/drm/radeon/si_dpm.c

2102

u32 tdp_limit;

sys/dev/pci/drm/radeon/si_dpm.c

2103

u32 near_tdp_limit;

sys/dev/pci/drm/radeon/si_dpm.c

2130

sizeof(u32) * 3,

sys/dev/pci/drm/radeon/si_dpm.c

2164

u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);

sys/dev/pci/drm/radeon/si_dpm.c

2179

sizeof(u32) * 2,

sys/dev/pci/drm/radeon/si_dpm.c

2230

u32 prev_sclk;

sys/dev/pci/drm/radeon/si_dpm.c

2231

u32 max_sclk;

sys/dev/pci/drm/radeon/si_dpm.c

2232

u32 min_sclk;

sys/dev/pci/drm/radeon/si_dpm.c

2276

min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;

sys/dev/pci/drm/radeon/si_dpm.c

2322

u32 sq_power_throttle, sq_power_throttle2;

sys/dev/pci/drm/radeon/si_dpm.c

2409

u32 table_size;

sys/dev/pci/drm/radeon/si_dpm.c

2411

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

2455

for (i = 0; i < (u32)tdep_count; i++) {

sys/dev/pci/drm/radeon/si_dpm.c

2474

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

2475

u32 v0_loadline;

sys/dev/pci/drm/radeon/si_dpm.c

2519

u32 leakage;

sys/dev/pci/drm/radeon/si_dpm.c

2522

u32 smc_leakage;

sys/dev/pci/drm/radeon/si_dpm.c

2523

u32 scaling_factor;

sys/dev/pci/drm/radeon/si_dpm.c

2558

u32 leakage;

sys/dev/pci/drm/radeon/si_dpm.c

2560

u32 smc_leakage;

sys/dev/pci/drm/radeon/si_dpm.c

2561

u32 scaling_factor;

sys/dev/pci/drm/radeon/si_dpm.c

2595

u32 load_line_slope, reg;

sys/dev/pci/drm/radeon/si_dpm.c

2597

u32 ticks_per_us = radeon_get_xclk(rdev) / 100;

sys/dev/pci/drm/radeon/si_dpm.c

2637

load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;

sys/dev/pci/drm/radeon/si_dpm.c

2642

cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);

sys/dev/pci/drm/radeon/si_dpm.c

2643

cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);

sys/dev/pci/drm/radeon/si_dpm.c

2650

cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);

sys/dev/pci/drm/radeon/si_dpm.c

2651

cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);

sys/dev/pci/drm/radeon/si_dpm.c

2676

u32 data = 0, offset;

sys/dev/pci/drm/radeon/si_dpm.c

2787

u32 fb_div, p_div;

sys/dev/pci/drm/radeon/si_dpm.c

2788

u32 clk_s, clk_v;

sys/dev/pci/drm/radeon/si_dpm.c

2789

u32 sclk = 0;

sys/dev/pci/drm/radeon/si_dpm.c

2791

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

2871

u32 evclk, u32 ecclk, u16 *voltage)

sys/dev/pci/drm/radeon/si_dpm.c

2873

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

2909

u32 mclk, sclk;

sys/dev/pci/drm/radeon/si_dpm.c

2911

u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

sys/dev/pci/drm/radeon/si_dpm.c

2912

u32 max_sclk = 0, max_mclk = 0;

sys/dev/pci/drm/radeon/si_dpm.c

3128

u16 reg_offset, u32 *value)

sys/dev/pci/drm/radeon/si_dpm.c

3139

u16 reg_offset, u32 value)

sys/dev/pci/drm/radeon/si_dpm.c

3151

u32 tmp, width, row, column, bank, density;

sys/dev/pci/drm/radeon/si_dpm.c

3196

u32 index, u16 *leakage_voltage)

sys/dev/pci/drm/radeon/si_dpm.c

3222

static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/pci/drm/radeon/si_dpm.c

3297

u32 thermal_level)

sys/dev/pci/drm/radeon/si_dpm.c

3329

PPSMC_Msg msg, u32 parameter)

sys/dev/pci/drm/radeon/si_dpm.c

3349

u32 levels = ps->performance_level_count;

sys/dev/pci/drm/radeon/si_dpm.c

3424

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

3586

u32 voltage_response_time, acpi_delay_time, vbi_time_out;

sys/dev/pci/drm/radeon/si_dpm.c

3587

u32 vddc_dly, acpi_dly, vbi_dly;

sys/dev/pci/drm/radeon/si_dpm.c

3588

u32 reference_clock;

sys/dev/pci/drm/radeon/si_dpm.c

3592

voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;

sys/dev/pci/drm/radeon/si_dpm.c

3615

u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */

sys/dev/pci/drm/radeon/si_dpm.c

3626

u32 tmp, pipe;

sys/dev/pci/drm/radeon/si_dpm.c

3685

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/si_dpm.c

3743

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/si_dpm.c

3767

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/pci/drm/radeon/si_dpm.c

3780

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/pci/drm/radeon/si_dpm.c

3802

static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/pci/drm/radeon/si_dpm.c

3839

u32 data, num_bits, num_levels;

sys/dev/pci/drm/radeon/si_dpm.c

3863

u32 max_voltage_steps,

sys/dev/pci/drm/radeon/si_dpm.c

3883

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

4043

(u32)si_pi->vddc_phase_shed_table.phase_delay);

sys/dev/pci/drm/radeon/si_dpm.c

4073

static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/pci/drm/radeon/si_dpm.c

4103

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/pci/drm/radeon/si_dpm.c

4107

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/radeon/si_dpm.c

4118

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/pci/drm/radeon/si_dpm.c

4122

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/radeon/si_dpm.c

4133

if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/pci/drm/radeon/si_dpm.c

4153

u16 voltage, u32 sclk, u32 mclk,

sys/dev/pci/drm/radeon/si_dpm.c

4173

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

4200

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

4216

static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/si_dpm.c

4217

u32 engine_clock)

sys/dev/pci/drm/radeon/si_dpm.c

4219

u32 dram_rows;

sys/dev/pci/drm/radeon/si_dpm.c

4220

u32 dram_refresh_rate;

sys/dev/pci/drm/radeon/si_dpm.c

4221

u32 mc_arb_rfsh_rate;

sys/dev/pci/drm/radeon/si_dpm.c

4222

u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

sys/dev/pci/drm/radeon/si_dpm.c

4239

u32 dram_timing;

sys/dev/pci/drm/radeon/si_dpm.c

4240

u32 dram_timing2;

sys/dev/pci/drm/radeon/si_dpm.c

4241

u32 burst_time;

sys/dev/pci/drm/radeon/si_dpm.c

4316

u32 reg;

sys/dev/pci/drm/radeon/si_dpm.c

4437

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4438

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/si_dpm.c

4439

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/si_dpm.c

4440

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/si_dpm.c

4441

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4442

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4443

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4444

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4445

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4446

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/pci/drm/radeon/si_dpm.c

4447

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/pci/drm/radeon/si_dpm.c

4448

u32 reg;

sys/dev/pci/drm/radeon/si_dpm.c

4578

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/pci/drm/radeon/si_dpm.c

4644

u32 lane_width;

sys/dev/pci/drm/radeon/si_dpm.c

4645

u32 vr_hot_gpio;

sys/dev/pci/drm/radeon/si_dpm.c

4727

u32 engine_clock,

sys/dev/pci/drm/radeon/si_dpm.c

4733

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4734

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/si_dpm.c

4735

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/si_dpm.c

4736

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/si_dpm.c

4737

u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/si_dpm.c

4738

u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/si_dpm.c

4740

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/si_dpm.c

4741

u32 reference_divider;

sys/dev/pci/drm/radeon/si_dpm.c

4742

u32 fbdiv;

sys/dev/pci/drm/radeon/si_dpm.c

4754

fbdiv = (u32) tmp;

sys/dev/pci/drm/radeon/si_dpm.c

4769

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/pci/drm/radeon/si_dpm.c

4773

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/pci/drm/radeon/si_dpm.c

4774

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/pci/drm/radeon/si_dpm.c

4797

u32 engine_clock,

sys/dev/pci/drm/radeon/si_dpm.c

4818

u32 engine_clock,

sys/dev/pci/drm/radeon/si_dpm.c

4819

u32 memory_clock,

sys/dev/pci/drm/radeon/si_dpm.c

4826

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4827

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4828

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4829

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4830

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

4831

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/pci/drm/radeon/si_dpm.c

4832

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/pci/drm/radeon/si_dpm.c

4833

u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;

sys/dev/pci/drm/radeon/si_dpm.c

4834

u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;

sys/dev/pci/drm/radeon/si_dpm.c

4860

u32 freq_nom;

sys/dev/pci/drm/radeon/si_dpm.c

4861

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

4862

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/si_dpm.c

4873

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/pci/drm/radeon/si_dpm.c

4874

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/pci/drm/radeon/si_dpm.c

5036

u32 a_t;

sys/dev/pci/drm/radeon/si_dpm.c

5037

u32 t_l, t_h;

sys/dev/pci/drm/radeon/si_dpm.c

5038

u32 high_bsp;

sys/dev/pci/drm/radeon/si_dpm.c

5142

u32 threshold;

sys/dev/pci/drm/radeon/si_dpm.c

5143

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/pci/drm/radeon/si_dpm.c

5219

u32 address = si_pi->state_table_start +

sys/dev/pci/drm/radeon/si_dpm.c

5244

u32 address = si_pi->state_table_start +

sys/dev/pci/drm/radeon/si_dpm.c

5247

u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);

sys/dev/pci/drm/radeon/si_dpm.c

5304

u32 temp_reg;

sys/dev/pci/drm/radeon/si_dpm.c

5440

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

5530

u32 i, j;

sys/dev/pci/drm/radeon/si_dpm.c

5548

u32 num_entries, u32 valid_flag)

sys/dev/pci/drm/radeon/si_dpm.c

5550

u32 i, j;

sys/dev/pci/drm/radeon/si_dpm.c

5565

u32 i = 0;

sys/dev/pci/drm/radeon/si_dpm.c

5637

u32 address = si_pi->mc_reg_table_start +

sys/dev/pci/drm/radeon/si_dpm.c

5679

u32 speed_cntl;

sys/dev/pci/drm/radeon/si_dpm.c

5755

bool ds_status_on, u32 count_write)

sys/dev/pci/drm/radeon/si_dpm.c

5816

u32 i;

sys/dev/pci/drm/radeon/si_dpm.c

5861

u32 lane_width;

sys/dev/pci/drm/radeon/si_dpm.c

5862

u32 new_lane_width =

sys/dev/pci/drm/radeon/si_dpm.c

5864

u32 current_lane_width =

sys/dev/pci/drm/radeon/si_dpm.c

5904

u32 thermal_int = RREG32(CG_THERMAL_INT);

sys/dev/pci/drm/radeon/si_dpm.c

5951

static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)

sys/dev/pci/drm/radeon/si_dpm.c

5954

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

5977

u32 duty100;

sys/dev/pci/drm/radeon/si_dpm.c

5978

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/radeon/si_dpm.c

5980

u32 reference_clock, tmp;

sys/dev/pci/drm/radeon/si_dpm.c

6080

u32 *speed)

sys/dev/pci/drm/radeon/si_dpm.c

6082

u32 duty, duty100;

sys/dev/pci/drm/radeon/si_dpm.c

6096

*speed = (u32)tmp64;

sys/dev/pci/drm/radeon/si_dpm.c

6105

u32 speed)

sys/dev/pci/drm/radeon/si_dpm.c

6108

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

6109

u32 duty, duty100;

sys/dev/pci/drm/radeon/si_dpm.c

6128

duty = (u32)tmp64;

sys/dev/pci/drm/radeon/si_dpm.c

6137

void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)

sys/dev/pci/drm/radeon/si_dpm.c

6153

u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si_dpm.c

6156

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

6167

u32 *speed)

sys/dev/pci/drm/radeon/si_dpm.c

6169

u32 tach_period;

sys/dev/pci/drm/radeon/si_dpm.c

6170

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/si_dpm.c

6188

u32 speed)

sys/dev/pci/drm/radeon/si_dpm.c

6190

u32 tach_period, tmp;

sys/dev/pci/drm/radeon/si_dpm.c

6191

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/si_dpm.c

6220

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

6244

u32 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

6828

u32 sclk, mclk;

sys/dev/pci/drm/radeon/si_dpm.c

7042

u32 current_index =

sys/dev/pci/drm/radeon/si_dpm.c

7056

u32 si_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si_dpm.c

7062

u32 current_index =

sys/dev/pci/drm/radeon/si_dpm.c

7074

u32 si_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/si_dpm.c

7080

u32 current_index =

sys/dev/pci/drm/radeon/si_dpm.h

103

u32 mclk_max;

sys/dev/pci/drm/radeon/si_dpm.h

104

u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/si_dpm.h

137

u32 cg_ulv_control;

sys/dev/pci/drm/radeon/si_dpm.h

138

u32 cg_ulv_parameter;

sys/dev/pci/drm/radeon/si_dpm.h

139

u32 volt_change_delay;

sys/dev/pci/drm/radeon/si_dpm.h

154

u32 max_cu;

sys/dev/pci/drm/radeon/si_dpm.h

159

u32 sys_pcie_mask;

sys/dev/pci/drm/radeon/si_dpm.h

169

u32 sram_end;

sys/dev/pci/drm/radeon/si_dpm.h

170

u32 state_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

171

u32 soft_regs_start;

sys/dev/pci/drm/radeon/si_dpm.h

172

u32 mc_reg_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

173

u32 arb_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

174

u32 cac_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

175

u32 dte_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

176

u32 spll_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

177

u32 papm_cfg_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

178

u32 fan_table_start;

sys/dev/pci/drm/radeon/si_dpm.h

196

u32 t_min;

sys/dev/pci/drm/radeon/si_dpm.h

197

u32 fan_ctrl_default_mode;

sys/dev/pci/drm/radeon/si_dpm.h

230

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);

sys/dev/pci/drm/radeon/si_dpm.h

231

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);

sys/dev/pci/drm/radeon/si_dpm.h

233

u32 max_voltage_steps,

sys/dev/pci/drm/radeon/si_dpm.h

36

u32 offset;

sys/dev/pci/drm/radeon/si_dpm.h

37

u32 mask;

sys/dev/pci/drm/radeon/si_dpm.h

38

u32 shift;

sys/dev/pci/drm/radeon/si_dpm.h

39

u32 value;

sys/dev/pci/drm/radeon/si_dpm.h

44

u32 cac_window;

sys/dev/pci/drm/radeon/si_dpm.h

45

u32 l2_lta_window_size_default;

sys/dev/pci/drm/radeon/si_dpm.h

50

u32 fixed_kt;

sys/dev/pci/drm/radeon/si_dpm.h

51

u32 lkge_lut_v0_percent;

sys/dev/pci/drm/radeon/si_dpm.h

57

u32 cac_leakage;

sys/dev/pci/drm/radeon/si_dpm.h

59

u32 wintime;

sys/dev/pci/drm/radeon/si_dpm.h

60

u32 l2_lta_window_size;

sys/dev/pci/drm/radeon/si_dpm.h

68

u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/radeon/si_dpm.h

69

u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/radeon/si_dpm.h

70

u32 k;

sys/dev/pci/drm/radeon/si_dpm.h

71

u32 t0;

sys/dev/pci/drm/radeon/si_dpm.h

72

u32 max_t;

sys/dev/pci/drm/radeon/si_dpm.h

78

u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/radeon/si_dpm.h

79

u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/radeon/si_dpm.h

80

u32 t_threshold;

sys/dev/pci/drm/radeon/si_dpm.h

85

u32 cg_spll_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.h

86

u32 cg_spll_func_cntl_2;

sys/dev/pci/drm/radeon/si_dpm.h

87

u32 cg_spll_func_cntl_3;

sys/dev/pci/drm/radeon/si_dpm.h

88

u32 cg_spll_func_cntl_4;

sys/dev/pci/drm/radeon/si_dpm.h

89

u32 cg_spll_spread_spectrum;

sys/dev/pci/drm/radeon/si_dpm.h

90

u32 cg_spll_spread_spectrum_2;

sys/dev/pci/drm/radeon/si_dpm.h

91

u32 dll_cntl;

sys/dev/pci/drm/radeon/si_dpm.h

92

u32 mclk_pwrmgt_cntl;

sys/dev/pci/drm/radeon/si_dpm.h

93

u32 mpll_ad_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.h

94

u32 mpll_dq_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.h

95

u32 mpll_func_cntl;

sys/dev/pci/drm/radeon/si_dpm.h

96

u32 mpll_func_cntl_1;

sys/dev/pci/drm/radeon/si_dpm.h

97

u32 mpll_func_cntl_2;

sys/dev/pci/drm/radeon/si_dpm.h

98

u32 mpll_ss1;

sys/dev/pci/drm/radeon/si_dpm.h

99

u32 mpll_ss2;

sys/dev/pci/drm/radeon/si_smc.c

115

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/pci/drm/radeon/si_smc.c

124

u32 tmp;

sys/dev/pci/drm/radeon/si_smc.c

145

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/si_smc.c

154

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/si_smc.c

163

u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/pci/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/si_smc.c

174

u32 tmp;

sys/dev/pci/drm/radeon/si_smc.c

195

u32 tmp;

sys/dev/pci/drm/radeon/si_smc.c

211

int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)

sys/dev/pci/drm/radeon/si_smc.c

214

u32 ucode_start_address;

sys/dev/pci/drm/radeon/si_smc.c

215

u32 ucode_size;

sys/dev/pci/drm/radeon/si_smc.c

217

u32 data;

sys/dev/pci/drm/radeon/si_smc.c

282

int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/pci/drm/radeon/si_smc.c

283

u32 *value, u32 limit)

sys/dev/pci/drm/radeon/si_smc.c

297

int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/pci/drm/radeon/si_smc.c

298

u32 value, u32 limit)

sys/dev/pci/drm/radeon/si_smc.c

34

u32 smc_address, u32 limit)

sys/dev/pci/drm/radeon/si_smc.c

48

u32 smc_start_address,

sys/dev/pci/drm/radeon/si_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/radeon/si_smc.c

53

u32 data, original_data, addr, extra_shift;

sys/dev/pci/drm/radeon/sislands_smc.h

398

u32 smc_start_address,

sys/dev/pci/drm/radeon/sislands_smc.h

399

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/radeon/sislands_smc.h

408

int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);

sys/dev/pci/drm/radeon/sislands_smc.h

409

int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/pci/drm/radeon/sislands_smc.h

410

u32 *value, u32 limit);

sys/dev/pci/drm/radeon/sislands_smc.h

411

int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/pci/drm/radeon/sislands_smc.h

412

u32 value, u32 limit);

sys/dev/pci/drm/radeon/sumo_dpm.c

1001

u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/sumo_dpm.c

1002

u32 sclk,

sys/dev/pci/drm/radeon/sumo_dpm.c

1003

u32 min_sclk_in_sr)

sys/dev/pci/drm/radeon/sumo_dpm.c

1006

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

1007

u32 temp;

sys/dev/pci/drm/radeon/sumo_dpm.c

1008

u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?

sys/dev/pci/drm/radeon/sumo_dpm.c

1026

static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/sumo_dpm.c

1027

u32 lower_limit)

sys/dev/pci/drm/radeon/sumo_dpm.c

103

u32 local0;

sys/dev/pci/drm/radeon/sumo_dpm.c

1030

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

104

u32 local1;

sys/dev/pci/drm/radeon/sumo_dpm.c

1045

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/pci/drm/radeon/sumo_dpm.c

1046

u32 current_vddc;

sys/dev/pci/drm/radeon/sumo_dpm.c

1047

u32 current_sclk;

sys/dev/pci/drm/radeon/sumo_dpm.c

1048

u32 current_index = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

1091

u32 min_voltage = 0; /* ??? */

sys/dev/pci/drm/radeon/sumo_dpm.c

1092

u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */

sys/dev/pci/drm/radeon/sumo_dpm.c

1093

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/pci/drm/radeon/sumo_dpm.c

1094

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

120

u32 p, u;

sys/dev/pci/drm/radeon/sumo_dpm.c

121

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

131

u32 p, u;

sys/dev/pci/drm/radeon/sumo_dpm.c

132

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

133

u32 grs = 256 * 25 / 100;

sys/dev/pci/drm/radeon/sumo_dpm.c

1434

u32 sclk;

sys/dev/pci/drm/radeon/sumo_dpm.c

148

u32 rcu_pwr_gating_cntl;

sys/dev/pci/drm/radeon/sumo_dpm.c

149

u32 p, u;

sys/dev/pci/drm/radeon/sumo_dpm.c

150

u32 p_c, p_p, d_p;

sys/dev/pci/drm/radeon/sumo_dpm.c

151

u32 r_t, i_t;

sys/dev/pci/drm/radeon/sumo_dpm.c

152

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

1528

u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/sumo_dpm.c

1530

u32 vid_2bit)

sys/dev/pci/drm/radeon/sumo_dpm.c

1532

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

1543

u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/sumo_dpm.c

1545

u32 vid_7bit)

sys/dev/pci/drm/radeon/sumo_dpm.c

1547

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

1559

u32 vid_2bit)

sys/dev/pci/drm/radeon/sumo_dpm.c

1562

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);

sys/dev/pci/drm/radeon/sumo_dpm.c

1574

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

1596

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

1597

u32 n = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

1598

u32 prev_sclk = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

1618

u32 i, j;

sys/dev/pci/drm/radeon/sumo_dpm.c

1745

u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;

sys/dev/pci/drm/radeon/sumo_dpm.c

1821

u32 current_index =

sys/dev/pci/drm/radeon/sumo_dpm.c

1842

u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/sumo_dpm.c

1848

u32 current_index =

sys/dev/pci/drm/radeon/sumo_dpm.c

1863

u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/sumo_dpm.c

1876

u32 current_index =

sys/dev/pci/drm/radeon/sumo_dpm.c

1903

u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/sumo_dpm.c

1914

u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/sumo_dpm.c

313

u32 high_clk)

sys/dev/pci/drm/radeon/sumo_dpm.c

316

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

344

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

345

u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;

sys/dev/pci/drm/radeon/sumo_dpm.c

36

static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = {

sys/dev/pci/drm/radeon/sumo_dpm.c

362

u32 index, u32 value)

sys/dev/pci/drm/radeon/sumo_dpm.c

387

u32 asi;

sys/dev/pci/drm/radeon/sumo_dpm.c

388

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

389

u32 m_a;

sys/dev/pci/drm/radeon/sumo_dpm.c

390

u32 a_t;

sys/dev/pci/drm/radeon/sumo_dpm.c

391

u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/pci/drm/radeon/sumo_dpm.c

392

u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/pci/drm/radeon/sumo_dpm.c

450

void sumo_program_vc(struct radeon_device *rdev, u32 vrc)

sys/dev/pci/drm/radeon/sumo_dpm.c

462

u32 p, u;

sys/dev/pci/drm/radeon/sumo_dpm.c

463

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

472

u32 index, u32 divider)

sys/dev/pci/drm/radeon/sumo_dpm.c

474

u32 reg_index = index / 4;

sys/dev/pci/drm/radeon/sumo_dpm.c

475

u32 field_index = index % 4;

sys/dev/pci/drm/radeon/sumo_dpm.c

492

u32 index, u32 divider)

sys/dev/pci/drm/radeon/sumo_dpm.c

497

u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);

sys/dev/pci/drm/radeon/sumo_dpm.c

506

u32 index, u32 divider)

sys/dev/pci/drm/radeon/sumo_dpm.c

511

u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);

sys/dev/pci/drm/radeon/sumo_dpm.c

519

static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)

sys/dev/pci/drm/radeon/sumo_dpm.c

521

u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);

sys/dev/pci/drm/radeon/sumo_dpm.c

528

static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)

sys/dev/pci/drm/radeon/sumo_dpm.c

531

u32 temp = gnb_slow;

sys/dev/pci/drm/radeon/sumo_dpm.c

532

u32 cg_sclk_dpm_ctrl_3;

sys/dev/pci/drm/radeon/sumo_dpm.c

54

static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = {

sys/dev/pci/drm/radeon/sumo_dpm.c

545

struct sumo_pl *pl, u32 index)

sys/dev/pci/drm/radeon/sumo_dpm.c

550

u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;

sys/dev/pci/drm/radeon/sumo_dpm.c

578

static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

580

u32 reg_index = index / 4;

sys/dev/pci/drm/radeon/sumo_dpm.c

581

u32 field_index = index % 4;

sys/dev/pci/drm/radeon/sumo_dpm.c

681

u32 nbps1_old = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

682

u32 nbps1_new = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

699

u32 nbps1_old = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

700

u32 nbps1_new = 0;

sys/dev/pci/drm/radeon/sumo_dpm.c

724

static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)

sys/dev/pci/drm/radeon/sumo_dpm.c

738

u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);

sys/dev/pci/drm/radeon/sumo_dpm.c

756

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

757

u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;

sys/dev/pci/drm/radeon/sumo_dpm.c

800

u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);

sys/dev/pci/drm/radeon/sumo_dpm.c

801

u32 i;

sys/dev/pci/drm/radeon/sumo_dpm.c

875

u32 v = RREG32(DOUT_SCRATCH3);

sys/dev/pci/drm/radeon/sumo_dpm.c

889

u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);

sys/dev/pci/drm/radeon/sumo_dpm.c

890

u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);

sys/dev/pci/drm/radeon/sumo_dpm.c

891

u32 t = 1;

sys/dev/pci/drm/radeon/sumo_dpm.c

925

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

926

u32 p, u;

sys/dev/pci/drm/radeon/sumo_dpm.c

927

u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);

sys/dev/pci/drm/radeon/sumo_dpm.c

940

u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);

sys/dev/pci/drm/radeon/sumo_dpm.c

969

u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);

sys/dev/pci/drm/radeon/sumo_dpm.c

970

u32 p, u;

sys/dev/pci/drm/radeon/sumo_dpm.c

971

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_dpm.c

996

u32 sumo_get_sleep_divider_from_id(u32 id)

sys/dev/pci/drm/radeon/sumo_dpm.h

100

u32 boost_vid_2bit;

sys/dev/pci/drm/radeon/sumo_dpm.h

105

u32 asi;

sys/dev/pci/drm/radeon/sumo_dpm.h

106

u32 pasi;

sys/dev/pci/drm/radeon/sumo_dpm.h

107

u32 bsp;

sys/dev/pci/drm/radeon/sumo_dpm.h

108

u32 bsu;

sys/dev/pci/drm/radeon/sumo_dpm.h

109

u32 pbsp;

sys/dev/pci/drm/radeon/sumo_dpm.h

110

u32 pbsu;

sys/dev/pci/drm/radeon/sumo_dpm.h

111

u32 dsp;

sys/dev/pci/drm/radeon/sumo_dpm.h

112

u32 psp;

sys/dev/pci/drm/radeon/sumo_dpm.h

113

u32 thermal_auto_throttling;

sys/dev/pci/drm/radeon/sumo_dpm.h

114

u32 uvd_m3_arbiter;

sys/dev/pci/drm/radeon/sumo_dpm.h

115

u32 fw_version;

sys/dev/pci/drm/radeon/sumo_dpm.h

193

void sumo_program_vc(struct radeon_device *rdev, u32 vrc);

sys/dev/pci/drm/radeon/sumo_dpm.h

203

u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/sumo_dpm.h

205

u32 vid_2bit);

sys/dev/pci/drm/radeon/sumo_dpm.h

206

u32 sumo_get_sleep_divider_from_id(u32 id);

sys/dev/pci/drm/radeon/sumo_dpm.h

207

u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/sumo_dpm.h

208

u32 sclk,

sys/dev/pci/drm/radeon/sumo_dpm.h

209

u32 min_sclk_in_sr);

sys/dev/pci/drm/radeon/sumo_dpm.h

215

void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);

sys/dev/pci/drm/radeon/sumo_dpm.h

220

u32 sumo_get_running_fw_version(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/sumo_dpm.h

33

u32 sclk;

sys/dev/pci/drm/radeon/sumo_dpm.h

34

u32 vddc_index;

sys/dev/pci/drm/radeon/sumo_dpm.h

35

u32 ds_divider_index;

sys/dev/pci/drm/radeon/sumo_dpm.h

36

u32 ss_divider_index;

sys/dev/pci/drm/radeon/sumo_dpm.h

37

u32 allow_gnb_slow;

sys/dev/pci/drm/radeon/sumo_dpm.h

38

u32 sclk_dpm_tdp_limit;

sys/dev/pci/drm/radeon/sumo_dpm.h

47

u32 num_levels;

sys/dev/pci/drm/radeon/sumo_dpm.h

49

u32 flags;

sys/dev/pci/drm/radeon/sumo_dpm.h

56

u32 num_max_voltage_levels;

sys/dev/pci/drm/radeon/sumo_dpm.h

57

u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];

sys/dev/pci/drm/radeon/sumo_dpm.h

66

u32 num_entries;

sys/dev/pci/drm/radeon/sumo_dpm.h

71

u32 sclk_frequency;

sys/dev/pci/drm/radeon/sumo_dpm.h

77

u32 num_max_dpm_entries;

sys/dev/pci/drm/radeon/sumo_dpm.h

82

u32 bootup_sclk;

sys/dev/pci/drm/radeon/sumo_dpm.h

83

u32 min_sclk;

sys/dev/pci/drm/radeon/sumo_dpm.h

84

u32 bootup_uma_clk;

sys/dev/pci/drm/radeon/sumo_dpm.h

91

u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];

sys/dev/pci/drm/radeon/sumo_dpm.h

92

u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];

sys/dev/pci/drm/radeon/sumo_dpm.h

93

u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];

sys/dev/pci/drm/radeon/sumo_dpm.h

94

u32 sclk_dpm_boost_margin;

sys/dev/pci/drm/radeon/sumo_dpm.h

95

u32 sclk_dpm_throttle_margin;

sys/dev/pci/drm/radeon/sumo_dpm.h

96

u32 sclk_dpm_tdp_limit_pg;

sys/dev/pci/drm/radeon/sumo_dpm.h

97

u32 gnb_tdp_limit;

sys/dev/pci/drm/radeon/sumo_dpm.h

98

u32 sclk_dpm_tdp_limit_boost;

sys/dev/pci/drm/radeon/sumo_dpm.h

99

u32 boost_sclk;

sys/dev/pci/drm/radeon/sumo_smc.c

109

u32 param = 0;

sys/dev/pci/drm/radeon/sumo_smc.c

130

static u32 sumo_power_of_4(u32 unit)

sys/dev/pci/drm/radeon/sumo_smc.c

132

u32 ret = 1;

sys/dev/pci/drm/radeon/sumo_smc.c

133

u32 i;

sys/dev/pci/drm/radeon/sumo_smc.c

144

u32 period, unit, timer_value;

sys/dev/pci/drm/radeon/sumo_smc.c

145

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/sumo_smc.c

163

void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit)

sys/dev/pci/drm/radeon/sumo_smc.c

165

u32 regoffset = 0;

sys/dev/pci/drm/radeon/sumo_smc.c

166

u32 shift = 0;

sys/dev/pci/drm/radeon/sumo_smc.c

167

u32 mask = 0xFFF;

sys/dev/pci/drm/radeon/sumo_smc.c

168

u32 sclk_dpm_tdp_limit;

sys/dev/pci/drm/radeon/sumo_smc.c

207

u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE);

sys/dev/pci/drm/radeon/sumo_smc.c

214

u32 sumo_get_running_fw_version(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/sumo_smc.c

33

static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)

sys/dev/pci/drm/radeon/sumo_smc.c

35

u32 gfx_int_req;

sys/dev/pci/drm/radeon/sumo_smc.c

72

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

1140

u32 nbpsconfig;

sys/dev/pci/drm/radeon/trinity_dpm.c

124

static const u32 trinity_sysls_disable[] = {

sys/dev/pci/drm/radeon/trinity_dpm.c

1261

u32 vid_2bit)

sys/dev/pci/drm/radeon/trinity_dpm.c

1264

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);

sys/dev/pci/drm/radeon/trinity_dpm.c

1265

u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;

sys/dev/pci/drm/radeon/trinity_dpm.c

1266

u32 step = (svi_mode == 0) ? 1250 : 625;

sys/dev/pci/drm/radeon/trinity_dpm.c

1267

u32 delta = vid_7bit * step + 50;

sys/dev/pci/drm/radeon/trinity_dpm.c

1286

static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)

sys/dev/pci/drm/radeon/trinity_dpm.c

1310

u32 sclk, u32 min_sclk_in_sr)

sys/dev/pci/drm/radeon/trinity_dpm.c

1313

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

1314

u32 temp;

sys/dev/pci/drm/radeon/trinity_dpm.c

1315

u32 min = (min_sclk_in_sr > TRINITY_MINIMUM_ENGINE_CLOCK) ?

sys/dev/pci/drm/radeon/trinity_dpm.c

1333

static u32 trinity_get_valid_engine_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/trinity_dpm.c

1334

u32 lower_limit)

sys/dev/pci/drm/radeon/trinity_dpm.c

1337

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

1355

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/pci/drm/radeon/trinity_dpm.c

1356

u32 current_vddc;

sys/dev/pci/drm/radeon/trinity_dpm.c

1357

u32 current_sclk;

sys/dev/pci/drm/radeon/trinity_dpm.c

1358

u32 current_index = 0;

sys/dev/pci/drm/radeon/trinity_dpm.c

1384

struct trinity_ps *ps, u32 index)

sys/dev/pci/drm/radeon/trinity_dpm.c

1403

static u32 trinity_get_uvd_clock_index(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/trinity_dpm.c

1407

u32 i = 0;

sys/dev/pci/drm/radeon/trinity_dpm.c

1427

u32 high_index = 0;

sys/dev/pci/drm/radeon/trinity_dpm.c

1428

u32 low_index = 0;

sys/dev/pci/drm/radeon/trinity_dpm.c

1457

u32 evclk, u32 ecclk, u16 *voltage)

sys/dev/pci/drm/radeon/trinity_dpm.c

1459

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

147

static const u32 trinity_sysls_enable[] = {

sys/dev/pci/drm/radeon/trinity_dpm.c

1493

u32 min_voltage = 0; /* ??? */

sys/dev/pci/drm/radeon/trinity_dpm.c

1494

u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */

sys/dev/pci/drm/radeon/trinity_dpm.c

1495

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/pci/drm/radeon/trinity_dpm.c

1496

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

1499

u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;

sys/dev/pci/drm/radeon/trinity_dpm.c

1588

u32 gpu_cac_avrg_cntl_window_size;

sys/dev/pci/drm/radeon/trinity_dpm.c

1589

u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;

sys/dev/pci/drm/radeon/trinity_dpm.c

1591

u32 dc_cac_value;

sys/dev/pci/drm/radeon/trinity_dpm.c

1596

dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>

sys/dev/pci/drm/radeon/trinity_dpm.c

1666

u32 sclk;

sys/dev/pci/drm/radeon/trinity_dpm.c

169

static const u32 trinity_override_mgpg_sequences[] = {

sys/dev/pci/drm/radeon/trinity_dpm.c

1760

u32 sclk;

sys/dev/pci/drm/radeon/trinity_dpm.c

1781

static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)

sys/dev/pci/drm/radeon/trinity_dpm.c

1784

u32 divider;

sys/dev/pci/drm/radeon/trinity_dpm.c

1990

u32 current_index =

sys/dev/pci/drm/radeon/trinity_dpm.c

2005

u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/trinity_dpm.c

2011

u32 current_index =

sys/dev/pci/drm/radeon/trinity_dpm.c

2023

u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/trinity_dpm.c

2044

u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/trinity_dpm.c

2055

u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/pci/drm/radeon/trinity_dpm.c

294

const u32 *seq, u32 count);

sys/dev/pci/drm/radeon/trinity_dpm.c

317

u32 p, u;

sys/dev/pci/drm/radeon/trinity_dpm.c

318

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

320

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/trinity_dpm.c

321

u32 sssd = 1;

sys/dev/pci/drm/radeon/trinity_dpm.c

323

u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;

sys/dev/pci/drm/radeon/trinity_dpm.c

357

u32 local0;

sys/dev/pci/drm/radeon/trinity_dpm.c

358

u32 local1;

sys/dev/pci/drm/radeon/trinity_dpm.c

385

u32 count;

sys/dev/pci/drm/radeon/trinity_dpm.c

386

const u32 *seq = NULL;

sys/dev/pci/drm/radeon/trinity_dpm.c

389

count = sizeof(trinity_mgcg_shls_default) / (3 * sizeof(u32));

sys/dev/pci/drm/radeon/trinity_dpm.c

408

const u32 *seq, u32 count)

sys/dev/pci/drm/radeon/trinity_dpm.c

410

u32 i, length = count * 3;

sys/dev/pci/drm/radeon/trinity_dpm.c

417

const u32 *seq, u32 count)

sys/dev/pci/drm/radeon/trinity_dpm.c

419

u32 i, length = count * 2;

sys/dev/pci/drm/radeon/trinity_dpm.c

42

static const u32 trinity_mgcg_shls_default[] = {

sys/dev/pci/drm/radeon/trinity_dpm.c

428

u32 count;

sys/dev/pci/drm/radeon/trinity_dpm.c

429

const u32 *seq = NULL;

sys/dev/pci/drm/radeon/trinity_dpm.c

432

count = sizeof(trinity_override_mgpg_sequences) / (2 * sizeof(u32));

sys/dev/pci/drm/radeon/trinity_dpm.c

440

u32 count;

sys/dev/pci/drm/radeon/trinity_dpm.c

441

const u32 *seq = NULL;

sys/dev/pci/drm/radeon/trinity_dpm.c

445

count = sizeof(trinity_sysls_enable) / (3 * sizeof(u32));

sys/dev/pci/drm/radeon/trinity_dpm.c

448

count = sizeof(trinity_sysls_disable) / (3 * sizeof(u32));

sys/dev/pci/drm/radeon/trinity_dpm.c

471

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

536

u32 index, u32 sclk)

sys/dev/pci/drm/radeon/trinity_dpm.c

540

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

541

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

565

u32 index, u32 divider)

sys/dev/pci/drm/radeon/trinity_dpm.c

567

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

568

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

577

u32 index, u32 divider)

sys/dev/pci/drm/radeon/trinity_dpm.c

579

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

580

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

588

static void trinity_set_vid(struct radeon_device *rdev, u32 index, u32 vid)

sys/dev/pci/drm/radeon/trinity_dpm.c

591

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid);

sys/dev/pci/drm/radeon/trinity_dpm.c

592

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

593

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

607

u32 index, u32 gnb_slow)

sys/dev/pci/drm/radeon/trinity_dpm.c

609

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

610

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

619

u32 index, u32 force_nbp_state)

sys/dev/pci/drm/radeon/trinity_dpm.c

621

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

622

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

631

u32 index, u32 wm)

sys/dev/pci/drm/radeon/trinity_dpm.c

633

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

634

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

643

u32 index, u32 wm)

sys/dev/pci/drm/radeon/trinity_dpm.c

645

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

646

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

655

u32 index, u32 at)

sys/dev/pci/drm/radeon/trinity_dpm.c

657

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

658

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

667

struct trinity_pl *pl, u32 index)

sys/dev/pci/drm/radeon/trinity_dpm.c

686

u32 index, bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

688

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.c

689

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/pci/drm/radeon/trinity_dpm.c

708

u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);

sys/dev/pci/drm/radeon/trinity_dpm.c

743

u32 sclk_dpm_cntl;

sys/dev/pci/drm/radeon/trinity_dpm.c

797

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

798

u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;

sys/dev/pci/drm/radeon/trinity_dpm.c

812

u32 i;

sys/dev/pci/drm/radeon/trinity_dpm.c

825

u32 uvdstates = (ps->vclk_low_divider |

sys/dev/pci/drm/radeon/trinity_dpm.c

834

u32 interval)

sys/dev/pci/drm/radeon/trinity_dpm.c

836

u32 p, u;

sys/dev/pci/drm/radeon/trinity_dpm.c

837

u32 tp = RREG32_SMC(PM_TP);

sys/dev/pci/drm/radeon/trinity_dpm.c

838

u32 val;

sys/dev/pci/drm/radeon/trinity_dpm.c

839

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/trinity_dpm.c

891

u32 tmp = RREG32(CG_MISC_REG);

sys/dev/pci/drm/radeon/trinity_dpm.c

960

u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);

sys/dev/pci/drm/radeon/trinity_dpm.c

970

u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);

sys/dev/pci/drm/radeon/trinity_dpm.c

979

u32 p, u;

sys/dev/pci/drm/radeon/trinity_dpm.c

980

u32 tp = RREG32_SMC(PM_TP);

sys/dev/pci/drm/radeon/trinity_dpm.c

981

u32 ni;

sys/dev/pci/drm/radeon/trinity_dpm.c

982

u32 xclk = radeon_get_xclk(rdev);

sys/dev/pci/drm/radeon/trinity_dpm.c

983

u32 value;

sys/dev/pci/drm/radeon/trinity_dpm.h

124

int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);

sys/dev/pci/drm/radeon/trinity_dpm.h

125

int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n);

sys/dev/pci/drm/radeon/trinity_dpm.h

31

u32 sclk;

sys/dev/pci/drm/radeon/trinity_dpm.h

48

u32 num_levels;

sys/dev/pci/drm/radeon/trinity_dpm.h

51

u32 nbps_flags;

sys/dev/pci/drm/radeon/trinity_dpm.h

52

u32 bapm_flags;

sys/dev/pci/drm/radeon/trinity_dpm.h

59

u32 vclk_low_divider;

sys/dev/pci/drm/radeon/trinity_dpm.h

60

u32 vclk_high_divider;

sys/dev/pci/drm/radeon/trinity_dpm.h

61

u32 dclk_low_divider;

sys/dev/pci/drm/radeon/trinity_dpm.h

62

u32 dclk_high_divider;

sys/dev/pci/drm/radeon/trinity_dpm.h

68

u32 vclk;

sys/dev/pci/drm/radeon/trinity_dpm.h

69

u32 dclk;

sys/dev/pci/drm/radeon/trinity_dpm.h

76

u32 bootup_uma_clk;

sys/dev/pci/drm/radeon/trinity_dpm.h

77

u32 bootup_sclk;

sys/dev/pci/drm/radeon/trinity_dpm.h

78

u32 min_sclk;

sys/dev/pci/drm/radeon/trinity_dpm.h

79

u32 dentist_vco_freq;

sys/dev/pci/drm/radeon/trinity_dpm.h

80

u32 nb_dpm_enable;

sys/dev/pci/drm/radeon/trinity_dpm.h

81

u32 nbp_mclk[TRINITY_NUM_NBPSTATES];

sys/dev/pci/drm/radeon/trinity_dpm.h

82

u32 nbp_nclk[TRINITY_NUM_NBPSTATES];

sys/dev/pci/drm/radeon/trinity_dpm.h

89

u32 uma_channel_number;

sys/dev/pci/drm/radeon/trinity_dpm.h

94

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/pci/drm/radeon/trinity_dpm.h

95

u32 dpm_interval;

sys/dev/pci/drm/radeon/trinity_dpm.h

96

u32 thermal_auto_throttling;

sys/dev/pci/drm/radeon/trinity_dpm.h

99

u32 min_sclk_did;

sys/dev/pci/drm/radeon/trinity_smc.c

29

static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id)

sys/dev/pci/drm/radeon/trinity_smc.c

32

u32 v = 0;

sys/dev/pci/drm/radeon/trinity_smc.c

73

int trinity_dpm_force_state(struct radeon_device *rdev, u32 n)

sys/dev/pci/drm/radeon/trinity_smc.c

80

int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n)

sys/dev/pci/drm/radeon/uvd_v1_0.c

270

u32 lmi_swap_cntl = 0;

sys/dev/pci/drm/radeon/uvd_v1_0.c

271

u32 mp_swap_cntl = 0;

sys/dev/pci/drm/radeon/vce_v1_0.c

105

u32 tmp;

sys/dev/pci/drm/radeon/vce_v1_0.c

138

u32 tmp;

sys/dev/pci/drm/radeon/vce_v2_0.c

133

u32 tmp;

sys/dev/pci/drm/radeon/vce_v2_0.c

41

u32 tmp;

sys/dev/pci/drm/radeon/vce_v2_0.c

76

u32 orig, tmp;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

62

__field(u32, job_count)

sys/dev/pci/drm/scheduler/sched_main.c

100

u32 credits;

sys/dev/pci/drm/scheduler/sched_main.c

806

u32 credits, void *owner,

sys/dev/pci/drm/scheduler/sched_main.c

893

u32 id = 0;

sys/dev/pci/drm/scheduler/sched_main.c

938

u32 handle,

sys/dev/pci/drm/scheduler/sched_main.c

939

u32 point)

sys/dev/pci/drm/scheduler/sched_main.c

98

static u32 drm_sched_available_credits(struct drm_gpu_scheduler *sched)

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

246

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

287

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

331

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

389

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

504

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

555

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

1041

u32 mem_type = TTM_PL_MOCK1;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

1081

u32 mem_type = TTM_PL_TT, mem_type_evict = TTM_PL_MOCK2;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

109

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

155

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

158

u32 mem_type = TTM_PL_VRAM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

197

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

23

u32 mem_type;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

230

u32 fst_mem = TTM_PL_SYSTEM, snd_mem = TTM_PL_VRAM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

235

u32 size = ALIGN(SZ_8K, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

275

u32 unknown_mem_type = TTM_PL_PRIV + 1;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

276

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

302

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

305

u32 mem_type = TTM_PL_VRAM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

331

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

333

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

378

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

414

u32 fst_mem = TTM_PL_VRAM, snd_mem = TTM_PL_VRAM + 1;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

419

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

465

u32 fst_mem = TTM_PL_VRAM, tmp_mem = TTM_PL_TT, final_mem = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

468

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

522

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

524

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

530

u32 flags;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

593

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

595

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

645

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

647

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

703

u32 fst_mem = TTM_PL_VRAM, snd_mem = TTM_PL_VRAM + 1;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

707

u32 size = ALIGN(BO_SIZE, PAGE_SIZE);

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

763

u32 mem_type = TTM_PL_VRAM, mem_multihop = TTM_PL_TT,

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

767

u32 small = SZ_8K, medium = SZ_512K,

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

769

u32 bo_sizes[] = { small, medium, big };

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

774

u32 bo_no = 3;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

824

u32 mem_type = TTM_PL_VRAM, mem_multihop = TTM_PL_TT;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

868

u32 mem_type = TTM_PL_VRAM, mem_multihop = TTM_PL_TT,

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

876

u32 size = SZ_512K;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

934

u32 small = SZ_8K, big = MANAGER_SIZE - BO_SIZE;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

939

u32 mem_type = TTM_PL_VRAM;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

983

u32 mem_type = TTM_PL_VRAM, mem_type_evict = TTM_PL_MOCK1;

sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c

202

struct ttm_place *ttm_place_kunit_init(struct kunit *test, u32 mem_type, u32 flags)

sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c

48

static struct ttm_tt *ttm_tt_simple_create(struct ttm_buffer_object *bo, u32 page_flags)

sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.h

41

struct ttm_place *ttm_place_kunit_init(struct kunit *test, u32 mem_type,

sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.h

42

u32 flags);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

128

void ttm_mock_manager_fini(struct ttm_device *bdev, u32 mem_type)

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

192

int ttm_bad_manager_init(struct ttm_device *bdev, u32 mem_type, u32 size)

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

210

int ttm_busy_manager_init(struct ttm_device *bdev, u32 mem_type, u32 size)

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

96

int ttm_mock_manager_init(struct ttm_device *bdev, u32 mem_type, u32 size)

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.h

24

int ttm_mock_manager_init(struct ttm_device *bdev, u32 mem_type, u32 size);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.h

25

int ttm_bad_manager_init(struct ttm_device *bdev, u32 mem_type, u32 size);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.h

26

int ttm_busy_manager_init(struct ttm_device *bdev, u32 mem_type, u32 size);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.h

27

void ttm_mock_manager_fini(struct ttm_device *bdev, u32 mem_type);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.h

28

void ttm_bad_manager_fini(struct ttm_device *bdev, u32 mem_type);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

51

u32 page_flags,

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

14

u32 mem_type;

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

15

u32 flags;

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

271

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

296

u32 mem_type = TTM_PL_SYSTEM;

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

50

u32 mem_type, u32 flags)

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

63

u32 mem_type)

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

14

u32 size;

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

15

u32 extra_pages_num;

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

214

u32 page_flags)

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

44

u32 page_flags = TTM_TT_FLAG_ZERO_ALLOC;

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

46

u32 extra_pages = params->extra_pages_num;

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

72

u32 size = SZ_8K;

sys/dev/pci/drm/ttm/ttm_bo_util.c

89

u32 num_pages,

sys/dev/pci/drm/ttm/ttm_range_manager.c

124

u32 num_pages = PFN_UP(size);

sys/dev/pci/drm/ttm/ttm_range_manager.c

140

u32 num_pages = PFN_UP(size);

sys/dev/pci/if_ice.c

16547

u32 arr[ICE_META_INIT_DW_CNT];

sys/dev/pci/if_mcx.c

3171

mcx_mix_u32(uint32_t xor, uint32_t u32)

sys/dev/pci/if_mcx.c

3173

xor ^= u32;

sys/dev/pci/if_mwx.c

5264

u32 v0, v1;

sys/dev/usb/dwc2/dwc2_core.c

1017

u32 usbcfg, ggpio, i2cctl;

sys/dev/usb/dwc2/dwc2_core.c

1087

u32 usbcfg, usbcfg_old;

sys/dev/usb/dwc2/dwc2_core.c

1144

u32 usbcfg;

sys/dev/usb/dwc2/dwc2_core.c

1162

u32 usbcfg;

sys/dev/usb/dwc2/dwc2_core.c

1163

u32 otgctl;

sys/dev/usb/dwc2/dwc2_core.c

186

u32 pcgcctl;

sys/dev/usb/dwc2/dwc2_core.c

254

u32 gpwrdn;

sys/dev/usb/dwc2/dwc2_core.c

365

u32 gsnpsid;

sys/dev/usb/dwc2/dwc2_core.c

366

u32 ghwcfg4;

sys/dev/usb/dwc2/dwc2_core.c

382

u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);

sys/dev/usb/dwc2/dwc2_core.c

432

u32 greset;

sys/dev/usb/dwc2/dwc2_core.c

448

u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);

sys/dev/usb/dwc2/dwc2_core.c

449

u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);

sys/dev/usb/dwc2/dwc2_core.c

541

u32 gusbcfg;

sys/dev/usb/dwc2/dwc2_core.c

542

u32 set;

sys/dev/usb/dwc2/dwc2_core.c

543

u32 clear;

sys/dev/usb/dwc2/dwc2_core.c

589

u32 gusbcfg;

sys/dev/usb/dwc2/dwc2_core.c

639

u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);

sys/dev/usb/dwc2/dwc2_core.c

821

u32 greset;

sys/dev/usb/dwc2/dwc2_core.c

849

u32 greset;

sys/dev/usb/dwc2/dwc2_core.c

886

u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);

sys/dev/usb/dwc2/dwc2_core.c

900

u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);

sys/dev/usb/dwc2/dwc2_core.c

909

u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);

sys/dev/usb/dwc2/dwc2_core.c

952

int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,

sys/dev/usb/dwc2/dwc2_core.c

953

u32 timeout)

sys/dev/usb/dwc2/dwc2_core.c

955

u32 i;

sys/dev/usb/dwc2/dwc2_core.c

975

int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,

sys/dev/usb/dwc2/dwc2_core.c

976

u32 timeout)

sys/dev/usb/dwc2/dwc2_core.c

978

u32 i;

sys/dev/usb/dwc2/dwc2_core.c

995

u32 hcfg, val;

sys/dev/usb/dwc2/dwc2_core.h

1172

u32 d32;

sys/dev/usb/dwc2/dwc2_core.h

1225

u32 *frame_list;

sys/dev/usb/dwc2/dwc2_core.h

1227

u32 frame_list_sz;

sys/dev/usb/dwc2/dwc2_core.h

1242

u32 fifo_map;

sys/dev/usb/dwc2/dwc2_core.h

1280

static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,

sys/dev/usb/dwc2/dwc2_core.h

1284

u32 *buf = buffer;

sys/dev/usb/dwc2/dwc2_core.h

1287

u32 x = dwc2_readl(hsotg, offset);

sys/dev/usb/dwc2/dwc2_core.h

1293

static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,

sys/dev/usb/dwc2/dwc2_core.h

1297

const u32 *buf = buffer;

sys/dev/usb/dwc2/dwc2_core.h

1391

int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,

sys/dev/usb/dwc2/dwc2_core.h

1392

u32 timeout);

sys/dev/usb/dwc2/dwc2_core.h

1393

int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,

sys/dev/usb/dwc2/dwc2_core.h

1394

u32 timeout);

sys/dev/usb/dwc2/dwc2_core.h

536

u32 max_transfer_size;

sys/dev/usb/dwc2/dwc2_core.h

537

u32 ahbcfg;

sys/dev/usb/dwc2/dwc2_core.h

540

u32 ref_clk_per;

sys/dev/usb/dwc2/dwc2_core.h

559

u32 g_rx_fifo_size;

sys/dev/usb/dwc2/dwc2_core.h

560

u32 g_np_tx_fifo_size;

sys/dev/usb/dwc2/dwc2_core.h

561

u32 g_tx_fifo_size[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

715

u32 snpsid;

sys/dev/usb/dwc2/dwc2_core.h

716

u32 dev_ep_dirs;

sys/dev/usb/dwc2/dwc2_core.h

717

u32 g_tx_fifo_size[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

742

u32 gotgctl;

sys/dev/usb/dwc2/dwc2_core.h

743

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_core.h

744

u32 gahbcfg;

sys/dev/usb/dwc2/dwc2_core.h

745

u32 gusbcfg;

sys/dev/usb/dwc2/dwc2_core.h

746

u32 grxfsiz;

sys/dev/usb/dwc2/dwc2_core.h

747

u32 gnptxfsiz;

sys/dev/usb/dwc2/dwc2_core.h

748

u32 gi2cctl;

sys/dev/usb/dwc2/dwc2_core.h

749

u32 glpmcfg;

sys/dev/usb/dwc2/dwc2_core.h

750

u32 pcgcctl;

sys/dev/usb/dwc2/dwc2_core.h

751

u32 pcgcctl1;

sys/dev/usb/dwc2/dwc2_core.h

752

u32 gdfifocfg;

sys/dev/usb/dwc2/dwc2_core.h

753

u32 gpwrdn;

sys/dev/usb/dwc2/dwc2_core.h

775

u32 dcfg;

sys/dev/usb/dwc2/dwc2_core.h

776

u32 dctl;

sys/dev/usb/dwc2/dwc2_core.h

777

u32 daintmsk;

sys/dev/usb/dwc2/dwc2_core.h

778

u32 diepmsk;

sys/dev/usb/dwc2/dwc2_core.h

779

u32 doepmsk;

sys/dev/usb/dwc2/dwc2_core.h

780

u32 diepctl[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

781

u32 dieptsiz[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

782

u32 diepdma[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

783

u32 doepctl[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

784

u32 doeptsiz[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

785

u32 doepdma[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

786

u32 dtxfsiz[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

802

u32 hcfg;

sys/dev/usb/dwc2/dwc2_core.h

803

u32 haintmsk;

sys/dev/usb/dwc2/dwc2_core.h

804

u32 hcintmsk[MAX_EPS_CHANNELS];

sys/dev/usb/dwc2/dwc2_core.h

805

u32 hprt0;

sys/dev/usb/dwc2/dwc2_core.h

806

u32 hfir;

sys/dev/usb/dwc2/dwc2_core.h

807

u32 hptxfsiz;

sys/dev/usb/dwc2/dwc2_coreintr.c

122

u32 gotgint;

sys/dev/usb/dwc2/dwc2_coreintr.c

123

u32 gotgctl;

sys/dev/usb/dwc2/dwc2_coreintr.c

124

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_coreintr.c

284

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_coreintr.c

318

u32 hprt0;

sys/dev/usb/dwc2/dwc2_coreintr.c

365

u32 glpmcfg;

sys/dev/usb/dwc2/dwc2_coreintr.c

366

u32 i = 0;

sys/dev/usb/dwc2/dwc2_coreintr.c

435

u32 dctl = dwc2_readl(hsotg, DCTL);

sys/dev/usb/dwc2/dwc2_coreintr.c

514

u32 dsts;

sys/dev/usb/dwc2/dwc2_coreintr.c

604

u32 glpmcfg;

sys/dev/usb/dwc2/dwc2_coreintr.c

605

u32 pcgcctl;

sys/dev/usb/dwc2/dwc2_coreintr.c

606

u32 hird;

sys/dev/usb/dwc2/dwc2_coreintr.c

607

u32 hird_thres;

sys/dev/usb/dwc2/dwc2_coreintr.c

608

u32 hird_thres_en;

sys/dev/usb/dwc2/dwc2_coreintr.c

609

u32 enslpm;

sys/dev/usb/dwc2/dwc2_coreintr.c

669

STATIC u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)

sys/dev/usb/dwc2/dwc2_coreintr.c

671

u32 gintsts;

sys/dev/usb/dwc2/dwc2_coreintr.c

672

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_coreintr.c

673

u32 gahbcfg;

sys/dev/usb/dwc2/dwc2_coreintr.c

674

u32 gintmsk_common = GINTMSK_COMMON;

sys/dev/usb/dwc2/dwc2_coreintr.c

699

u32 gpwrdn)

sys/dev/usb/dwc2/dwc2_coreintr.c

701

u32 gpwrdn_tmp;

sys/dev/usb/dwc2/dwc2_coreintr.c

764

u32 gpwrdn;

sys/dev/usb/dwc2/dwc2_coreintr.c

842

u32 gintsts;

sys/dev/usb/dwc2/dwc2_coreintr.c

92

u32 hprt0 = dwc2_readl(hsotg, HPRT0);

sys/dev/usb/dwc2/dwc2_hcd.c

1015

struct dwc2_host_chan *chan, u32 *hcchar)

sys/dev/usb/dwc2/dwc2_hcd.c

1057

bytes_in_fifo = sizeof(u32) *

sys/dev/usb/dwc2/dwc2_hcd.c

107

u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);

sys/dev/usb/dwc2/dwc2_hcd.c

1152

u32 i;

sys/dev/usb/dwc2/dwc2_hcd.c

1153

u32 remaining_count;

sys/dev/usb/dwc2/dwc2_hcd.c

1154

u32 byte_count;

sys/dev/usb/dwc2/dwc2_hcd.c

1155

u32 dword_count;

sys/dev/usb/dwc2/dwc2_hcd.c

1156

u32 *data_buf = (u32 *)chan->xfer_buf;

sys/dev/usb/dwc2/dwc2_hcd.c

1176

u32 data = data_buf[0] | data_buf[1] << 8 |

sys/dev/usb/dwc2/dwc2_hcd.c

1198

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

1199

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcd.c

1251

u32 max_hc_xfer_size = hsotg->params.max_transfer_size;

sys/dev/usb/dwc2/dwc2_hcd.c

1253

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

1254

u32 hctsiz = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

1256

u32 ec_mc = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

1317

u32 max_periodic_len =

sys/dev/usb/dwc2/dwc2_hcd.c

1403

dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));

sys/dev/usb/dwc2/dwc2_hcd.c

1417

u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));

sys/dev/usb/dwc2/dwc2_hcd.c

1473

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

1474

u32 hctsiz = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

151

u32 usbcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

1594

u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));

sys/dev/usb/dwc2/dwc2_hcd.c

1612

u32 hcchar = dwc2_readl(hsotg,

sys/dev/usb/dwc2/dwc2_hcd.c

1716

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

1738

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

1812

u32 intr;

sys/dev/usb/dwc2/dwc2_hcd.c

1813

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

1922

u32 intr_mask;

sys/dev/usb/dwc2/dwc2_hcd.c

1938

u32 hprt0 = dwc2_readl(hsotg, HPRT0);

sys/dev/usb/dwc2/dwc2_hcd.c

1939

u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;

sys/dev/usb/dwc2/dwc2_hcd.c

207

u32 intmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

2119

u32 usbcfg, otgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

2207

u32 hcfg, hfir, otgctl, usbcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

2247

u32 op_mode = hsotg->hw_params.op_mode;

sys/dev/usb/dwc2/dwc2_hcd.c

2286

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

231

u32 intmsk = dwc2_readl(hsotg, GINTMSK);

sys/dev/usb/dwc2/dwc2_hcd.c

2327

u32 hprt0 = dwc2_read_hprt0(hsotg);

sys/dev/usb/dwc2/dwc2_hcd.c

250

u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;

sys/dev/usb/dwc2/dwc2_hcd.c

2928

u32 tx_status;

sys/dev/usb/dwc2/dwc2_hcd.c

2929

u32 fspcavail;

sys/dev/usb/dwc2/dwc2_hcd.c

2930

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

2934

u32 qspcavail;

sys/dev/usb/dwc2/dwc2_hcd.c

3062

u32 tx_status;

sys/dev/usb/dwc2/dwc2_hcd.c

3063

u32 qspcavail;

sys/dev/usb/dwc2/dwc2_hcd.c

3064

u32 fspcavail;

sys/dev/usb/dwc2/dwc2_hcd.c

3065

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

308

u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;

sys/dev/usb/dwc2/dwc2_hcd.c

3203

u32 gintmsk = dwc2_readl(hsotg, GINTMSK);

sys/dev/usb/dwc2/dwc2_hcd.c

3215

u32 count = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

3216

u32 gotgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

3305

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

3351

u32 pcgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

3352

u32 gotgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

3465

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

3466

u32 port_status;

sys/dev/usb/dwc2/dwc2_hcd.c

3467

u32 speed;

sys/dev/usb/dwc2/dwc2_hcd.c

3468

u32 pcgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

3469

u32 pwr;

sys/dev/usb/dwc2/dwc2_hcd.c

3680

u32 hcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

376

u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)

sys/dev/usb/dwc2/dwc2_hcd.c

378

u32 usbcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

379

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

3865

u32 hfnum = dwc2_readl(hsotg, HFNUM);

sys/dev/usb/dwc2/dwc2_hcd.c

3876

u32 hprt = dwc2_readl(hsotg, HPRT0);

sys/dev/usb/dwc2/dwc2_hcd.c

3877

u32 hfir = dwc2_readl(hsotg, HFIR);

sys/dev/usb/dwc2/dwc2_hcd.c

3878

u32 hfnum = dwc2_readl(hsotg, HFNUM);

sys/dev/usb/dwc2/dwc2_hcd.c

3914

u32 size = sizeof(*urb) + iso_desc_count *

sys/dev/usb/dwc2/dwc2_hcd.c

3926

u32 size = sizeof(*urb) + iso_desc_count *

sys/dev/usb/dwc2/dwc2_hcd.c

3962

u32 np_tx_status;

sys/dev/usb/dwc2/dwc2_hcd.c

3963

u32 p_tx_status;

sys/dev/usb/dwc2/dwc2_hcd.c

4007

u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

425

u32 *data_buf = (u32 *)dest;

sys/dev/usb/dwc2/dwc2_hcd.c

4346

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

4413

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

4461

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

4572

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

458

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

459

u32 hcsplt;

sys/dev/usb/dwc2/dwc2_hcd.c

460

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcd.c

461

u32 hc_dma;

sys/dev/usb/dwc2/dwc2_hcd.c

4783

u32 tflags = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

5186

u32 ahbcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

5187

u32 dctl;

sys/dev/usb/dwc2/dwc2_hcd.c

5264

u32 hcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

5518

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

5519

u32 pcgcctl;

sys/dev/usb/dwc2/dwc2_hcd.c

5520

u32 gusbcfg;

sys/dev/usb/dwc2/dwc2_hcd.c

5521

u32 gpwrdn;

sys/dev/usb/dwc2/dwc2_hcd.c

554

u32 hcintmsk = HCINTMSK_CHHLTD;

sys/dev/usb/dwc2/dwc2_hcd.c

5627

u32 gpwrdn;

sys/dev/usb/dwc2/dwc2_hcd.c

5628

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

5775

u32 pcgcctl;

sys/dev/usb/dwc2/dwc2_hcd.c

5776

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

5851

u32 pcgcctl;

sys/dev/usb/dwc2/dwc2_hcd.c

5853

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

5931

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

5932

u32 pcgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

5967

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcd.c

5968

u32 pcgctl;

sys/dev/usb/dwc2/dwc2_hcd.c

632

u32 hcintmsk = HCINTMSK_CHHLTD;

sys/dev/usb/dwc2/dwc2_hcd.c

669

u32 intmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

710

u32 hcintmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

711

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

712

u32 hcsplt = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

79

u32 intmsk;

sys/dev/usb/dwc2/dwc2_hcd.c

825

u32 nptxsts, hptxsts, hcchar;

sys/dev/usb/dwc2/dwc2_hcd.c

858

u32 hcintmsk = HCINTMSK_CHHLTD;

sys/dev/usb/dwc2/dwc2_hcd.c

988

u32 hcintmsk;

sys/dev/usb/dwc2/dwc2_hcd.h

142

u32 xfer_len;

sys/dev/usb/dwc2/dwc2_hcd.h

143

u32 xfer_count;

sys/dev/usb/dwc2/dwc2_hcd.h

164

u32 hcint;

sys/dev/usb/dwc2/dwc2_hcd.h

169

u32 desc_list_sz;

sys/dev/usb/dwc2/dwc2_hcd.h

183

u32 offset;

sys/dev/usb/dwc2/dwc2_hcd.h

184

u32 length;

sys/dev/usb/dwc2/dwc2_hcd.h

185

u32 actual_length;

sys/dev/usb/dwc2/dwc2_hcd.h

186

u32 status;

sys/dev/usb/dwc2/dwc2_hcd.h

200

u32 length;

sys/dev/usb/dwc2/dwc2_hcd.h

201

u32 actual_length;

sys/dev/usb/dwc2/dwc2_hcd.h

202

u32 status;

sys/dev/usb/dwc2/dwc2_hcd.h

203

u32 error_count;

sys/dev/usb/dwc2/dwc2_hcd.h

204

u32 packet_count;

sys/dev/usb/dwc2/dwc2_hcd.h

205

u32 flags;

sys/dev/usb/dwc2/dwc2_hcd.h

259

u32 start_schedule_us;

sys/dev/usb/dwc2/dwc2_hcd.h

366

u32 ls_start_schedule_slice;

sys/dev/usb/dwc2/dwc2_hcd.h

378

u32 desc_list_sz;

sys/dev/usb/dwc2/dwc2_hcd.h

379

u32 *n_bytes;

sys/dev/usb/dwc2/dwc2_hcd.h

450

u32 ssplit_out_xfer_count;

sys/dev/usb/dwc2/dwc2_hcd.h

467

u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);

sys/dev/usb/dwc2/dwc2_hcd.h

484

static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)

sys/dev/usb/dwc2/dwc2_hcd.h

486

u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum));

sys/dev/usb/dwc2/dwc2_hcd.h

502

static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)

sys/dev/usb/dwc2/dwc2_hcd.h

504

u32 hprt0 = dwc2_readl(hsotg, HPRT0);

sys/dev/usb/dwc2/dwc2_hcd.h

708

static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)

sys/dev/usb/dwc2/dwc2_hcd.h

714

static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)

sys/dev/usb/dwc2/dwc2_hcd.h

719

static inline u32 dwc2_hcd_urb_get_actual_length(

sys/dev/usb/dwc2/dwc2_hcd.h

725

static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)

sys/dev/usb/dwc2/dwc2_hcd.h

731

struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,

sys/dev/usb/dwc2/dwc2_hcd.h

732

u32 length)

sys/dev/usb/dwc2/dwc2_hcd.h

738

static inline u32 dwc2_hcd_urb_get_iso_desc_status(

sys/dev/usb/dwc2/dwc2_hcd.h

744

static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(

sys/dev/usb/dwc2/dwc2_hcdddma.c

1075

u32 n_bytes, int *xfer_done)

sys/dev/usb/dwc2/dwc2_hcdddma.c

1162

u32 n_bytes;

sys/dev/usb/dwc2/dwc2_hcdddma.c

118

qh->n_bytes = malloc(sizeof(u32) * dwc2_max_desc_num(qh), M_USBHC,

sys/dev/usb/dwc2/dwc2_hcdddma.c

146

free(qh->n_bytes, M_USBHC, sizeof(u32) * dwc2_max_desc_num(qh));

sys/dev/usb/dwc2/dwc2_hcdddma.c

193

STATIC void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)

sys/dev/usb/dwc2/dwc2_hcdddma.c

195

u32 hcfg;

sys/dev/usb/dwc2/dwc2_hcdddma.c

219

u32 hcfg;

sys/dev/usb/dwc2/dwc2_hcdddma.c

553

struct dwc2_qh *qh, u32 max_xfer_size,

sys/dev/usb/dwc2/dwc2_hcdddma.c

567

dma_desc->buf = (u32)(DMAADDR(qtd->urb->usbdma, frame_desc->offset));

sys/dev/usb/dwc2/dwc2_hcdddma.c

593

u32 max_xfer_size;

sys/dev/usb/dwc2/dwc2_hcdddma.c

728

dma_desc->buf = (u32)chan->xfer_dma;

sys/dev/usb/dwc2/dwc2_hcdddma.c

916

dma_desc->buf = (u32)(DMAADDR(qtd->urb->usbdma, frame_desc->offset));

sys/dev/usb/dwc2/dwc2_hcdintr.c

1201

u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,

sys/dev/usb/dwc2/dwc2_hcdintr.c

1203

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1580

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1581

u32 hcsplt;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1582

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1583

u32 hc_dma;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1799

u32 hcchar;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1800

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1801

u32 hcintmsk;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1802

u32 hcsplt;

sys/dev/usb/dwc2/dwc2_hcdintr.c

1858

u32 hcintmsk;

sys/dev/usb/dwc2/dwc2_hcdintr.c

197

u32 grxsts, chnum, bcnt, dpid, pktsts;

sys/dev/usb/dwc2/dwc2_hcdintr.c

2072

u32 hcint, hcintmsk;

sys/dev/usb/dwc2/dwc2_hcdintr.c

2223

u32 haint;

sys/dev/usb/dwc2/dwc2_hcdintr.c

2259

u32 gintsts, dbg_gintsts;

sys/dev/usb/dwc2/dwc2_hcdintr.c

272

STATIC void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,

sys/dev/usb/dwc2/dwc2_hcdintr.c

273

u32 *hprt0_modify)

sys/dev/usb/dwc2/dwc2_hcdintr.c

277

u32 usbcfg;

sys/dev/usb/dwc2/dwc2_hcdintr.c

278

u32 prtspd;

sys/dev/usb/dwc2/dwc2_hcdintr.c

279

u32 hcfg;

sys/dev/usb/dwc2/dwc2_hcdintr.c

280

u32 fslspclksel;

sys/dev/usb/dwc2/dwc2_hcdintr.c

281

u32 hfir;

sys/dev/usb/dwc2/dwc2_hcdintr.c

369

u32 hprt0;

sys/dev/usb/dwc2/dwc2_hcdintr.c

370

u32 hprt0_modify;

sys/dev/usb/dwc2/dwc2_hcdintr.c

417

u32 hcfg;

sys/dev/usb/dwc2/dwc2_hcdintr.c

454

STATIC u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,

sys/dev/usb/dwc2/dwc2_hcdintr.c

460

u32 hctsiz, count, length;

sys/dev/usb/dwc2/dwc2_hcdintr.c

513

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcdintr.c

562

u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));

sys/dev/usb/dwc2/dwc2_hcdintr.c

563

u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;

sys/dev/usb/dwc2/dwc2_hcdintr.c

732

u32 haintmsk;

sys/dev/usb/dwc2/dwc2_hcdintr.c

843

u32 gintmsk;

sys/dev/usb/dwc2/dwc2_hcdintr.c

940

u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));

sys/dev/usb/dwc2/dwc2_hcdintr.c

957

u32 len;

sys/dev/usb/dwc2/dwc2_hcdintr.c

958

u32 hctsiz;

sys/dev/usb/dwc2/dwc2_hcdintr.c

959

u32 pid;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1340

u32 max_xfer_size;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1341

u32 max_channel_xfer_size;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1520

u32 hprt = dwc2_readl(hsotg, HPRT0);

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1521

u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1733

u32 intr_mask;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1783

u32 intr_mask;

sys/dev/usb/dwc2/dwc2_hw.h

847

u32 status;

sys/dev/usb/dwc2/dwc2_hw.h

848

u32 buf;

sys/dev/usb/dwc2/dwc2_params.c

383

u32 hs_phy_type = hsotg->hw_params.hs_phy_type;

sys/dev/usb/dwc2/dwc2_params.c

630

u32 hs_phy_type;

sys/dev/usb/dwc2/dwc2_params.c

631

u32 fs_phy_type;

sys/dev/usb/dwc2/dwc2_params.c

742

u32 total = 0;

sys/dev/usb/dwc2/dwc2_params.c

743

u32 dptxfszn;

sys/dev/usb/dwc2/dwc2_params.c

862

u32 gnptxfsiz;

sys/dev/usb/dwc2/dwc2_params.c

863

u32 hptxfsiz;

sys/dev/usb/dwc2/dwc2_params.c

887

u32 gnptxfsiz;

sys/dev/usb/dwc2/dwc2_params.c

920

u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;

sys/dev/usb/dwc2/dwc2_params.c

921

u32 grxfsiz;

sys/lib/libsa/rijndael.c

1038

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

sys/lib/libsa/rijndael.c

1041

u32 s0, s1, s2, s3, t0, t1, t2, t3;

sys/lib/libsa/rijndael.c

115

static const u32 Te1[256] = {

sys/lib/libsa/rijndael.c

181

static const u32 Te2[256] = {

sys/lib/libsa/rijndael.c

247

static const u32 Te3[256] = {

sys/lib/libsa/rijndael.c

313

static const u32 Te4[256] = {

sys/lib/libsa/rijndael.c

379

static const u32 Td0[256] = {

sys/lib/libsa/rijndael.c

445

static const u32 Td1[256] = {

sys/lib/libsa/rijndael.c

49

static const u32 Te0[256] = {

sys/lib/libsa/rijndael.c

511

static const u32 Td2[256] = {

sys/lib/libsa/rijndael.c

577

static const u32 Td3[256] = {

sys/lib/libsa/rijndael.c

643

static const u32 Td4[256] = {

sys/lib/libsa/rijndael.c

709

static const u32 rcon[] = {

sys/lib/libsa/rijndael.c

715

#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))

sys/lib/libsa/rijndael.c

724

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/lib/libsa/rijndael.c

727

u32 temp;

sys/lib/libsa/rijndael.c

811

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/lib/libsa/rijndael.c

814

u32 temp;

sys/lib/libsa/rijndael.c

854

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

sys/lib/libsa/rijndael.c

857

u32 s0, s1, s2, s3, t0, t1, t2, t3;

sys/lib/libsa/rijndael.h

44

u32 ek[4*(AES_MAXROUNDS + 1)]; /* encrypt key schedule */

sys/lib/libsa/rijndael.h

45

u32 dk[4*(AES_MAXROUNDS + 1)]; /* decrypt key schedule */

sys/netinet/inet_nat64.c

100

d->u32[0] = inet_nat64_mask(s->u32[3], p->u32[3],

sys/netinet/inet_nat64.c

144

d->u32[3] = inet_nat64_mask(s->u32[0], p->u32[3],

sys/netinet/inet_nat64.c

195

d->u32[0] = inet_nat64_mask(s->u32[3], p->u32[0], pfxlen);

sys/netinet/inet_nat64.c

208

d->u32[0] = d->u32[1] = d->u32[2] = 0;

sys/netinet/inet_nat64.c

211

d->u32[3] = inet_nat64_mask(s->u32[0], p->u32[0], pfxlen);

sys/netinet/inet_nat64.c

27

u_int32_t u32[4];

sys/netinet/inet_nat64.c

44

u_int32_t u32;

sys/netinet/inet_nat64.c

49

u32 =

sys/netinet/inet_nat64.c

52

return (u32);

usr.bin/ssh/chacha.c

19

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

usr.bin/ssh/chacha.c

25

(((u32)((p)[0]) ) | \

usr.bin/ssh/chacha.c

26

((u32)((p)[1]) << 8) | \

usr.bin/ssh/chacha.c

27

((u32)((p)[2]) << 16) | \

usr.bin/ssh/chacha.c

28

((u32)((p)[3]) << 24))

usr.bin/ssh/chacha.c

53

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

usr.bin/ssh/chacha.c

87

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

usr.bin/ssh/chacha.c

89

u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15;

usr.bin/ssh/chacha.c

90

u32 j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15;

usr.bin/ssh/cipher-aesctr.c

29

aesctr_inc(u8 *ctr, u32 len)

usr.bin/ssh/cipher-aesctr.c

53

aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits)

usr.bin/ssh/cipher-aesctr.c

65

aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes)

usr.bin/ssh/cipher-aesctr.c

67

u32 n = 0;

usr.bin/ssh/cipher-aesctr.h

27

u32 ek[4*(AES_MAXROUNDS + 1)]; /* encrypt key schedule */

usr.bin/ssh/cipher-aesctr.h

31

void aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits);

usr.bin/ssh/cipher-aesctr.h

33

void aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes);

usr.bin/ssh/rijndael.c

117

static const u32 Te1[256] = {

usr.bin/ssh/rijndael.c

183

static const u32 Te2[256] = {

usr.bin/ssh/rijndael.c

249

static const u32 Te3[256] = {

usr.bin/ssh/rijndael.c

316

static const u32 Td0[256] = {

usr.bin/ssh/rijndael.c

382

static const u32 Td1[256] = {

usr.bin/ssh/rijndael.c

448

static const u32 Td2[256] = {

usr.bin/ssh/rijndael.c

51

static const u32 Te0[256] = {

usr.bin/ssh/rijndael.c

514

static const u32 Td3[256] = {

usr.bin/ssh/rijndael.c

615

static const u32 rcon[] = {

usr.bin/ssh/rijndael.c

621

#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))

usr.bin/ssh/rijndael.c

630

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

usr.bin/ssh/rijndael.c

633

u32 temp;

usr.bin/ssh/rijndael.c

718

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

usr.bin/ssh/rijndael.c

721

u32 temp;

usr.bin/ssh/rijndael.c

762

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

usr.bin/ssh/rijndael.c

765

u32 s0, s1, s2, s3, t0, t1, t2, t3;

usr.bin/ssh/rijndael.c

947

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

usr.bin/ssh/rijndael.c

950

u32 s0, s1, s2, s3, t0, t1, t2, t3;

usr.bin/ssh/umac.c

167

rijndaelEncrypt((u32 *)(int_key), AES_ROUNDS, (u8 *)(in), (u8 *)(out))

usr.bin/ssh/umac.c

169

rijndaelKeySetupEnc((u32 *)(int_key), (const unsigned char *)(key), \

usr.sbin/bgpctl/bgpctl.c

1059

uint32_t as4, u32;

usr.sbin/bgpctl/bgpctl.c

1070

u32 = ext;

usr.sbin/bgpctl/bgpctl.c

1072

log_ext_subtype(type, subtype), log_as(as2), u32);

usr.sbin/bgpctl/parser.c

1509

uint32_t u32;

usr.sbin/bgpctl/parser.c

1531

u32 = htonl(val);

usr.sbin/bgpctl/parser.c

1532

data = &u32;

usr.sbin/bgpd/parse.y

5889

uint32_t u32;

usr.sbin/bgpd/parse.y

5907

u32 = htonl(val);

usr.sbin/bgpd/parse.y

5908

data = &u32;

usr.sbin/bgpd/util.c

181

uint32_t u32;

usr.sbin/bgpd/util.c

187

u32 = rd & 0xffffffff;

usr.sbin/bgpd/util.c

189

snprintf(buf, sizeof(buf), "rd %hu:%u", u16, u32);

usr.sbin/bgpd/util.c

192

u32 = (rd >> 16) & 0xffffffff;

usr.sbin/bgpd/util.c

194

snprintf(buf, sizeof(buf), "rd %s:%hu", log_as(u32), u16);

usr.sbin/bgpd/util.c

197

u32 = (rd >> 16) & 0xffffffff;

usr.sbin/bgpd/util.c

199

addr.s_addr = htonl(u32);

usr.sbin/lldpd/pdu.c

38

uint32_t u32;

usr.sbin/lldpd/pdu.c

40

u32 = (uint32_t)buf[0] << 24;

usr.sbin/lldpd/pdu.c

41

u32 |= (uint32_t)buf[1] << 16;

usr.sbin/lldpd/pdu.c

42

u32 |= (uint32_t)buf[2] << 8;

usr.sbin/lldpd/pdu.c

43

u32 |= (uint32_t)buf[3];

usr.sbin/lldpd/pdu.c

45

return (u32);

usr.sbin/radiusd/radiusd_ipcp.c

1746

uint32_t u32;

usr.sbin/radiusd/radiusd_ipcp.c

1784

if (radius_get_uint32_attr(radres, RADIUS_TYPE_ERROR_CAUSE, &u32) == 0){

usr.sbin/radiusd/radiusd_ipcp.c

1785

cause = radius_error_cause_string(u32);

usr.sbin/radiusd/radiusd_ipcp.c

1788

u32, cause);

usr.sbin/radiusd/radiusd_ipcp.c

1790

snprintf(causestr, sizeof(causestr), " cause=%u", u32);

usr.sbin/smtpd/mproc.c

394

m_add_u32(struct mproc *m, uint32_t u32)

usr.sbin/smtpd/mproc.c

396

m_add(m, &u32, sizeof(u32));

usr.sbin/smtpd/mproc.c

503

m_get_u32(struct msg *m, uint32_t *u32)

usr.sbin/smtpd/mproc.c

505

m_get(m, u32, sizeof(*u32));

usr.sbin/smtpd/unpack_dns.c

255

unpack_u32(struct unpack *p, uint32_t *u32)

usr.sbin/smtpd/unpack_dns.c

257

if (unpack_data(p, u32, 4) == -1)

usr.sbin/smtpd/unpack_dns.c

260

*u32 = ntohl(*u32);