bin/ksh/c_ksh.c
711
(fset&UCASEV_AL) ? true : false);
bin/ksh/c_sh.c
44
evaluate(arg, &val, KSH_UNWIND_ERROR, false);
bin/ksh/c_sh.c
465
rv = shell(s, false);
bin/ksh/c_sh.c
499
s = (gettrap(*wp, false) == NULL) ? *wp++ : NULL; /* get command */
bin/ksh/c_test.c
282
return gmatch(opnd1, opnd2, false);
bin/ksh/c_test.c
286
return !gmatch(opnd1, opnd2, false);
bin/ksh/c_test.c
301
if (!evaluate(opnd1, &v1, KSH_RETURN_ERROR, false) ||
bin/ksh/c_test.c
302
!evaluate(opnd2, &v2, KSH_RETURN_ERROR, false)) {
bin/ksh/c_ulimit.c
145
if (!evaluate(v, &rval, KSH_RETURN_ERROR, false))
bin/ksh/edit.c
110
x_mode(false);
bin/ksh/edit.c
125
x_mode(false);
bin/ksh/edit.c
760
bool saw_slash = false;
bin/ksh/edit.c
868
if (gmatch(te->name, pat, false))
bin/ksh/emacs.c
1065
xlp_valid = false;
bin/ksh/emacs.c
1221
x_delete(len, false);
bin/ksh/emacs.c
1720
x_delete(end - start, false);
bin/ksh/emacs.c
1764
x_delete(olen, false);
bin/ksh/emacs.c
1809
xlp_valid = false;
bin/ksh/emacs.c
386
x_mode(false);
bin/ksh/emacs.c
455
xlp_valid = false;
bin/ksh/emacs.c
483
x_delete(x_arg, false);
bin/ksh/emacs.c
500
x_delete(x_arg, false);
bin/ksh/emacs.c
535
xlp_valid = false;
bin/ksh/emacs.c
553
xlp_valid = false;
bin/ksh/emacs.c
840
xlp_valid = false;
bin/ksh/eval.c
921
ksh_dup2(pv[1], 1, false);
bin/ksh/eval.c
948
if (gmatch(str, pat, false)) {
bin/ksh/eval.c
958
if (gmatch(str, pat, false)) {
bin/ksh/eval.c
967
if (gmatch(p, pat, false))
bin/ksh/eval.c
973
if (gmatch(p, pat, false))
bin/ksh/exec.c
146
(void) ksh_dup2(pv[1], 1, false); /* stdout of curr */
bin/ksh/exec.c
153
(void) ksh_dup2(pv[0], 0, false); /* stdin of next */
bin/ksh/exec.c
203
ksh_dup2(pv[0], 0, false);
bin/ksh/exec.c
210
ksh_dup2(coproc.readw, 1, false);
bin/ksh/exec.c
214
ksh_dup2(pv[1], 1, false);
bin/ksh/exec.c
310
is_first = false;
bin/ksh/exec.c
353
gmatch(cp, s, false))
bin/ksh/exec.c
576
if (!(ftp = findfunc(cp, hash(cp), false)) ||
bin/ksh/exec.c
609
Flag(FXTRACE) = tp->flag & TRACE ? true : false;
bin/ksh/exec.c
859
tp = findfunc(name, h, false);
bin/ksh/expr.c
230
es->arith = false;
bin/ksh/expr.c
319
vl = do_ppmm(es, es->tok, vl, false);
bin/ksh/history.c
145
hp = first ? hist_get(first, false, false) :
bin/ksh/history.c
146
hist_get_newest(false);
bin/ksh/history.c
170
hist_get_newest(false);
bin/ksh/history.c
174
hlast = hist_get_newest(false);
bin/ksh/history.c
180
hfirst = hist_get(first, (lflag || last) ? true : false,
bin/ksh/history.c
181
lflag ? true : false);
bin/ksh/history.c
184
hlast = last ? hist_get(last, true, lflag ? true : false) :
bin/ksh/history.c
185
(lflag ? hist_get_newest(false) : hfirst);
bin/ksh/history.c
231
setstr(local("_", false), tf->name, KSH_RETURN_ERROR);
bin/ksh/history.c
575
warningf(false, "resizing history storage: %s",
bin/ksh/jobs.c
203
warningf(false, "%s: tcsetpgrp() failed: %s",
bin/ksh/jobs.c
207
warningf(false,
bin/ksh/jobs.c
227
warningf(false, "%s: setpgid() failed: %s",
bin/ksh/jobs.c
232
warningf(false,
bin/ksh/jobs.c
303
tty_init(false);
bin/ksh/jobs.c
311
warningf(false, "%s: getpgrp() failed: %s",
bin/ksh/jobs.c
323
warningf(false,
bin/ksh/jobs.c
339
warningf(false, "%s: setpgid() failed: %s",
bin/ksh/jobs.c
344
warningf(false,
bin/ksh/jobs.c
355
warningf(false,
bin/ksh/jobs.c
490
coproc_cleanup(false);
bin/ksh/lex.c
263
if (is_wdvarname(Xstring(ws, wp), false)) {
bin/ksh/mail.c
202
setstr((vp = local("_", false)), mbp->mb_path, KSH_RETURN_ERROR);
bin/ksh/main.c
405
warningf(false, "Cannot determine current working directory");
bin/ksh/main.c
526
i = shell(s, false);
bin/ksh/main.c
547
return shell(s, false);
bin/ksh/misc.c
437
if (arrayset && (!*array || *skip_varname(array, false))) {
bin/ksh/misc.c
908
warningf(false, "%s%s-%c: unknown option",
bin/ksh/misc.c
934
warningf(false, "%s%s-`%c' requires argument",
bin/ksh/syn.c
155
reject = false;
bin/ksh/syn.c
231
reject = false;
bin/ksh/syn.c
252
reject = false;
bin/ksh/syn.c
259
reject = false;
bin/ksh/syn.c
262
t = function_body(XPptrv(args)[0], false);
bin/ksh/syn.c
290
reject = false;
bin/ksh/syn.c
300
reject = false;
bin/ksh/syn.c
53
((reject) ? (reject = false, symbol) : (symbol = yylex(cf)))
bin/ksh/syn.c
62
reject = false;
bin/ksh/syn.c
654
{ "&&", LOGAND, false },
bin/ksh/syn.c
655
{ "||", LOGOR, false },
bin/ksh/syn.c
656
{ ";;", BREAK, false },
bin/ksh/syn.c
657
{ "((", MDPAREN, false },
bin/ksh/syn.c
658
{ "|&", COPROC, false },
bin/ksh/syn.c
660
{ "newline", '\n', false },
bin/ksh/syn.c
859
reject = false;
bin/ksh/syn.c
877
reject = false;
bin/ksh/trap.c
188
warningf(false, "timed out waiting for input");
bin/ksh/tty.c
39
warningf(false, "No controlling tty (open /dev/tty: %s)",
bin/ksh/tty.c
48
warningf(false, "Can't find tty file descriptor");
bin/ksh/tty.c
53
warningf(false, "%s: dup of tty fd failed: %s",
bin/ksh/var.c
1023
if (getint(vp, &l, false) == -1) {
bin/ksh/var.c
143
*arrayp = false;
bin/ksh/var.c
144
p = skip_varname(n, false);
bin/ksh/var.c
353
base = getint(vp, &num, false);
bin/ksh/var.c
606
val = skip_varname(var, false);
bin/ksh/var.c
644
vp = (set&LOCAL) ? local(tvar, (set & LOCAL_COPY) ? true : false) :
bin/ksh/vi.c
229
x_mode(false);
games/fortune/fortune/fortune.c
1120
Found_one = false;
games/fortune/fortune/fortune.c
285
Short_only = false;
games/fortune/fortune/fortune.c
292
Long_only = false;
games/fortune/fortune/fortune.c
400
was_malloc = false;
games/fortune/fortune/fortune.c
85
bool Found_one = false; /* did we find a match? */
games/fortune/fortune/fortune.c
86
bool Find_files = false; /* display a list of fortune files */
games/fortune/fortune/fortune.c
87
bool Wait = false; /* wait desired after fortune */
games/fortune/fortune/fortune.c
88
bool Short_only = false; /* short fortune desired */
games/fortune/fortune/fortune.c
89
bool Long_only = false; /* long fortune desired */
games/fortune/fortune/fortune.c
90
bool Offend = false; /* offensive fortunes only */
games/fortune/fortune/fortune.c
907
static bool did_noprobs = false;
games/fortune/fortune/fortune.c
91
bool All_forts = false; /* any fortune allowed */
games/fortune/fortune/fortune.c
92
bool Equal_probs = false; /* scatter un-allocted prob equally */
games/fortune/fortune/fortune.c
93
bool Match = false; /* dump fortunes matching a pattern */
games/fortune/strfile/strfile.c
191
first = false;
games/fortune/strfile/strfile.c
394
n1 = false;
games/fortune/strfile/strfile.c
395
n2 = false;
games/fortune/strfile/strfile.c
93
bool Sflag = false; /* silent run flag */
games/fortune/strfile/strfile.c
94
bool Oflag = false; /* ordering flag */
games/fortune/strfile/strfile.c
95
bool Iflag = false; /* ignore case flag */
games/fortune/strfile/strfile.c
96
bool Rflag = false; /* randomize order flag */
games/fortune/strfile/strfile.c
97
bool Xflag = false; /* set rotated bit */
include/stdbool.h
27
#define false false
include/stdbool.h
38
#define false false
lib/libc/gen/getpwent.c
270
remap = false;
lib/libc/gen/getpwent.c
280
remap = false;
lib/libc/gen/getpwent.c
789
return getpwnam_internal(name, pw, buf, buflen, pwretp, false, true);
lib/libc/gen/getpwent.c
799
my_errno = getpwnam_internal(name, NULL, NULL, 0, &pw, false, false);
lib/libc/gen/getpwent.c
813
my_errno = getpwnam_internal(name, NULL, NULL, 0, &pw, true, false);
lib/libc/gen/getpwent.c
873
return getpwuid_internal(uid, pw, buf, buflen, pwretp, false, true);
lib/libc/gen/getpwent.c
883
my_errno = getpwuid_internal(uid, NULL, NULL, 0, &pw, false, false);
lib/libc/gen/getpwent.c
897
my_errno = getpwuid_internal(uid, NULL, NULL, 0, &pw, true, false);
lib/libcbor/src/cbor.c
157
return _cbor_copy_int(item, false);
lib/libcbor/src/cbor.c
56
.stack = &stack, .creation_failed = false, .syntax_error = false};
lib/libcbor/src/cbor/arrays.c
32
return false;
lib/libcbor/src/cbor/arrays.c
37
if (index >= item->metadata.array_metadata.end_ptr) return false;
lib/libcbor/src/cbor/arrays.c
52
return false;
lib/libcbor/src/cbor/arrays.c
60
return false;
lib/libcbor/src/cbor/arrays.c
70
return false;
lib/libcbor/src/cbor/bytestrings.c
101
return false;
lib/libcbor/src/cbor/bytestrings.c
112
return false;
lib/libcbor/src/cbor/common.h
65
_cbor_enable_assert = false; \
lib/libcbor/src/cbor/internal/builder_callbacks.c
358
return false;
lib/libcbor/src/cbor/maps.c
108
if (!_cbor_map_add_key(item, pair.key)) return false;
lib/libcbor/src/cbor/maps.c
60
return false;
lib/libcbor/src/cbor/maps.c
70
return false;
lib/libcbor/src/cbor/maps.c
81
return false;
lib/libcbor/src/cbor/streaming.c
17
return false;
lib/libcbor/src/cbor/streaming.c
544
callbacks->boolean(context, false);
lib/libcbor/src/cbor/strings.c
100
return false;
lib/libcbor/src/cbor/strings.c
90
return false;
lib/libcurses/tinfo/lib_win32con.c
1178
_nc_console_MapColor(false, COLOR_BLACK);
lib/libexpat/examples/element_declarations.c
148
return false;
lib/libexpat/examples/element_declarations.c
168
return false;
lib/libexpat/lib/xmlparse.c
825
tolerable = false;
lib/libexpat/lib/xmlparse.c
836
tolerable = false;
lib/libexpat/lib/xmltok.c
369
bool input_incomplete = false;
lib/libexpat/lib/xmltok.c
370
bool output_exhausted = false;
lib/libexpat/tests/alloc_tests.c
2105
bool values[] = {true, false};
lib/libexpat/tests/basic_tests.c
1234
false},
lib/libexpat/tests/basic_tests.c
1241
false},
lib/libexpat/tests/basic_tests.c
1269
const bool rejection_expected = false;
lib/libexpat/tests/basic_tests.c
358
success = false;
lib/libexpat/tests/basic_tests.c
4906
{false, false, "\xBA"}, // [<1>011 1010]
lib/libexpat/tests/basic_tests.c
4907
{true, false, "\x39"}, // [0011 1001] = ASCII nine '9'
lib/libexpat/tests/basic_tests.c
4908
{false, false, "\xB9"}, // [<1>011 1001]
lib/libexpat/tests/basic_tests.c
4913
{false, false, "\x9B\xA5"}, // [1<0>01 1011] [1010 0101]
lib/libexpat/tests/basic_tests.c
4914
{false, false, "\xDB\x25"}, // [1101 1011] [<0>010 0101]
lib/libexpat/tests/basic_tests.c
4915
{false, false, "\xDB\xE5"}, // [1101 1011] [1<1>10 0101]
lib/libexpat/tests/basic_tests.c
4916
{true, false, "\xCC\x81"}, // [1100 1100] [1000 0001] =
lib/libexpat/tests/basic_tests.c
4918
{false, false, "\x8C\x81"}, // [1<0>00 1100] [1000 0001]
lib/libexpat/tests/basic_tests.c
4919
{false, false, "\xCC\x01"}, // [1100 1100] [<0>000 0001]
lib/libexpat/tests/basic_tests.c
4920
{false, false, "\xCC\xC1"}, // [1100 1100] [1<1>00 0001]
lib/libexpat/tests/basic_tests.c
4925
{false, false, "\xA0\xA4\x85"}, // [1<0>10 0000] [1010 0100] [1000 0101]
lib/libexpat/tests/basic_tests.c
4926
{false, false, "\xE0\x24\x85"}, // [1110 0000] [<0>010 0100] [1000 0101]
lib/libexpat/tests/basic_tests.c
4927
{false, false, "\xE0\xE4\x85"}, // [1110 0000] [1<1>10 0100] [1000 0101]
lib/libexpat/tests/basic_tests.c
4928
{false, false, "\xE0\xA4\x05"}, // [1110 0000] [1010 0100] [<0>000 0101]
lib/libexpat/tests/basic_tests.c
4929
{false, false, "\xE0\xA4\xC5"}, // [1110 0000] [1010 0100] [1<1>00 0101]
lib/libexpat/tests/basic_tests.c
4930
{true, false, "\xE0\xA4\x81"}, // [1110 0000] [1010 0100] [1000 0001] =
lib/libexpat/tests/basic_tests.c
4932
{false, false, "\xA0\xA4\x81"}, // [1<0>10 0000] [1010 0100] [1000 0001]
lib/libexpat/tests/basic_tests.c
4933
{false, false, "\xE0\x24\x81"}, // [1110 0000] [<0>010 0100] [1000 0001]
lib/libexpat/tests/basic_tests.c
4934
{false, false, "\xE0\xE4\x81"}, // [1110 0000] [1<1>10 0100] [1000 0001]
lib/libexpat/tests/basic_tests.c
4935
{false, false, "\xE0\xA4\x01"}, // [1110 0000] [1010 0100] [<0>000 0001]
lib/libexpat/tests/basic_tests.c
4936
{false, false, "\xE0\xA4\xC1"}, // [1110 0000] [1010 0100] [1<1>00 0001]
lib/libexpat/tests/basic_tests.c
4938
const bool atNameStart[] = {true, false};
lib/libexpat/tests/basic_tests.c
4964
success = false;
lib/libexpat/tests/basic_tests.c
4968
success = false;
lib/libfido2/src/assert.c
21
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/assert.c
303
if (fido_dev_is_fido2(dev) == false) {
lib/libfido2/src/assert.c
381
&cbor)) == NULL || cbor_isa_bytestring(item) == false ||
lib/libfido2/src/assert.c
382
cbor_bytestring_is_definite(item) == false) {
lib/libfido2/src/assert.c
55
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/authkey.c
14
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/bio.c
153
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/bio.c
174
if (cbor_isa_map(item) == false ||
lib/libfido2/src/bio.c
175
cbor_map_is_definite(item) == false) {
lib/libfido2/src/bio.c
201
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/bio.c
208
if (cbor_isa_array(val) == false ||
lib/libfido2/src/bio.c
209
cbor_array_is_definite(val) == false) {
lib/libfido2/src/bio.c
340
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/bio.c
374
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/bio.c
626
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/cbor.c
1138
if (cbor_isa_float_ctrl(val) == false ||
lib/libfido2/src/cbor.c
1140
cbor_is_bool(val) == false) {
lib/libfido2/src/cbor.c
1147
if (cbor_isa_uint(val) == false ||
lib/libfido2/src/cbor.c
1155
if (cbor_isa_float_ctrl(val) == false ||
lib/libfido2/src/cbor.c
1157
cbor_is_bool(val) == false) {
lib/libfido2/src/cbor.c
1164
if (cbor_isa_uint(val) == false ||
lib/libfido2/src/cbor.c
1197
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1198
cbor_map_is_definite(item) == false ||
lib/libfido2/src/cbor.c
1265
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1266
cbor_map_is_definite(item) == false ||
lib/libfido2/src/cbor.c
1292
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/cbor.c
1293
cbor_bytestring_is_definite(item) == false) {
lib/libfido2/src/cbor.c
1341
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/cbor.c
1342
cbor_bytestring_is_definite(item) == false) {
lib/libfido2/src/cbor.c
1404
if (cbor_isa_negint(val) == false ||
lib/libfido2/src/cbor.c
1422
if (cbor_isa_array(val) == false ||
lib/libfido2/src/cbor.c
1423
cbor_array_is_definite(val) == false ||
lib/libfido2/src/cbor.c
145
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1452
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1453
cbor_map_is_definite(item) == false ||
lib/libfido2/src/cbor.c
146
cbor_map_is_definite(item) == false) {
lib/libfido2/src/cbor.c
1472
if (cbor_isa_uint(item) == false) {
lib/libfido2/src/cbor.c
1511
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1512
cbor_map_is_definite(item) == false ||
lib/libfido2/src/cbor.c
1566
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1567
cbor_map_is_definite(item) == false ||
lib/libfido2/src/cbor.c
1612
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
1613
cbor_map_is_definite(item) == false ||
lib/libfido2/src/cbor.c
182
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/cbor.c
183
cbor_bytestring_is_definite(item) == false) {
lib/libfido2/src/cbor.c
209
if (cbor_isa_string(item) == false ||
lib/libfido2/src/cbor.c
210
cbor_string_is_definite(item) == false) {
lib/libfido2/src/cbor.c
497
if (cbor_map_add(body, alg) == false ||
lib/libfido2/src/cbor.c
499
cbor_array_push(item, body) == false)
lib/libfido2/src/cbor.c
548
cbor_array_push(array, key) == false)
lib/libfido2/src/cbor.c
574
cbor_array_push(array, entry) == false)
lib/libfido2/src/cbor.c
944
if (cbor_isa_uint(val) == false ||
lib/libfido2/src/cbor.c
954
if (cbor_isa_negint(val) == false ||
lib/libfido2/src/cbor.c
987
if (cbor_isa_map(item) == false ||
lib/libfido2/src/cbor.c
988
cbor_map_is_definite(item) == false ||
lib/libfido2/src/config.c
199
return config_pin_minlen(dev, len, false, NULL, pin, &ms);
lib/libfido2/src/config.c
224
r = config_pin_minlen(dev, 0, false, &sa, pin, &ms);
lib/libfido2/src/cred.c
203
if (fido_dev_is_fido2(dev) == false) {
lib/libfido2/src/cred.c
22
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/credman.c
129
if (fido_dev_is_fido2(dev) == false) {
lib/libfido2/src/credman.c
183
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/credman.c
253
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/credman.c
304
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/credman.c
472
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/credman.c
513
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/dev.c
353
if (fido_dev_is_fido2(dev) == false)
lib/libfido2/src/eddsa.c
62
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/eddsa.c
63
cbor_bytestring_is_definite(item) == false ||
lib/libfido2/src/eddsa.c
79
if (cbor_isa_negint(key) == false ||
lib/libfido2/src/eddsa.c
94
if (cbor_isa_map(item) == false ||
lib/libfido2/src/eddsa.c
95
cbor_map_is_definite(item) == false ||
lib/libfido2/src/es256.c
25
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/es256.c
26
cbor_bytestring_is_definite(item) == false ||
lib/libfido2/src/es256.c
42
if (cbor_isa_negint(key) == false ||
lib/libfido2/src/es256.c
59
if (cbor_isa_map(item) == false ||
lib/libfido2/src/es256.c
60
cbor_map_is_definite(item) == false ||
lib/libfido2/src/info.c
117
if (cbor_isa_uint(item) == false ||
lib/libfido2/src/info.c
136
if (cbor_isa_array(item) == false ||
lib/libfido2/src/info.c
137
cbor_array_is_definite(item) == false) {
lib/libfido2/src/info.c
169
if (cbor_isa_negint(val) == false ||
lib/libfido2/src/info.c
195
if (cbor_isa_map(item) == false ||
lib/libfido2/src/info.c
196
cbor_map_is_definite(item) == false) {
lib/libfido2/src/info.c
221
if (cbor_isa_array(item) == false ||
lib/libfido2/src/info.c
222
cbor_array_is_definite(item) == false) {
lib/libfido2/src/info.c
244
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/info.c
32
if (cbor_isa_array(item) == false ||
lib/libfido2/src/info.c
33
cbor_array_is_definite(item) == false) {
lib/libfido2/src/info.c
53
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/info.c
54
cbor_bytestring_is_definite(item) == false ||
lib/libfido2/src/info.c
71
if (cbor_isa_float_ctrl(val) == false ||
lib/libfido2/src/info.c
73
cbor_is_bool(val) == false) {
lib/libfido2/src/info.c
97
if (cbor_isa_map(item) == false ||
lib/libfido2/src/info.c
98
cbor_map_is_definite(item) == false) {
lib/libfido2/src/largeblob.c
190
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/largeblob.c
270
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/pin.c
231
if (fido_dev_has_uv(dev) == false) {
lib/libfido2/src/pin.c
272
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/pin.c
519
if (cbor_isa_uint(key) == false ||
lib/libfido2/src/rs256.c
34
if (cbor_isa_bytestring(item) == false ||
lib/libfido2/src/rs256.c
35
cbor_bytestring_is_definite(item) == false ||
lib/libfido2/src/rs256.c
51
if (cbor_isa_negint(key) == false ||
lib/libfido2/src/rs256.c
68
if (cbor_isa_map(item) == false ||
lib/libfido2/src/rs256.c
69
cbor_map_is_definite(item) == false ||
lib/libfido2/src/touch.c
29
if (fido_dev_is_fido2(dev) == false)
lib/libfido2/src/touch.c
89
if (fido_dev_is_fido2(dev) == false)
lib/libradius/radius_attr.c
358
return (false);
lib/libradius/radius_attr.c
368
return (false);
libexec/tradcpp/directive.c
142
is->seenelse = false;
libexec/tradcpp/directive.c
161
newstate->curtrue = false;
libexec/tradcpp/directive.c
264
ifstate->curtrue = false;
libexec/tradcpp/directive.c
435
return false;
libexec/tradcpp/directive.c
449
text = macroexpand(p2, line, strlen(line), false);
libexec/tradcpp/directive.c
540
msg = macroexpand(p2, line, strlen(line), false);
libexec/tradcpp/directive.c
554
msg = macroexpand(p2, line, strlen(line), false);
libexec/tradcpp/directive.c
582
{ "elif", false, d_elif },
libexec/tradcpp/directive.c
583
{ "else", false, d_else },
libexec/tradcpp/directive.c
584
{ "endif", false, d_endif },
libexec/tradcpp/directive.c
586
{ "if", false, d_if },
libexec/tradcpp/directive.c
587
{ "ifdef", false, d_ifdef },
libexec/tradcpp/directive.c
588
{ "ifndef", false, d_ifndef },
libexec/tradcpp/directive.c
64
bool incomment = false;
libexec/tradcpp/directive.c
65
bool inesc = false;
libexec/tradcpp/directive.c
66
bool inquote = false;
libexec/tradcpp/directive.c
664
incomment = false;
libexec/tradcpp/directive.c
73
incomment = false;
libexec/tradcpp/directive.c
80
inesc = false;
libexec/tradcpp/directive.c
88
inquote = false;
libexec/tradcpp/eval.c
220
return false;
libexec/tradcpp/eval.c
236
return false;
libexec/tradcpp/eval.c
252
return false;
libexec/tradcpp/eval.c
658
return false;
libexec/tradcpp/eval.c
683
return false;
libexec/tradcpp/eval.c
698
return false;
libexec/tradcpp/eval.c
753
result = false;
libexec/tradcpp/files.c
128
bool inquote = false;
libexec/tradcpp/files.c
148
inquote = false;
libexec/tradcpp/files.c
183
bool ateof = false;
libexec/tradcpp/files.c
323
bool needslash = false;
libexec/tradcpp/files.c
376
file_read(pf, fd, name, false);
libexec/tradcpp/files.c
388
file_read(pf, fd, file, false);
libexec/tradcpp/files.c
422
pf = place_addfile(place, "<standard-input>", false);
libexec/tradcpp/files.c
429
pf = place_addfile(place, name, false);
libexec/tradcpp/macro.c
1045
expand_missingargs(es, p, false);
libexec/tradcpp/macro.c
1081
expand_missingargs(es, p, false);
libexec/tradcpp/macro.c
1110
expand_missingargs(es, p, false);
libexec/tradcpp/macro.c
1133
expand_missingargs(es, p, false);
libexec/tradcpp/macro.c
1159
bool inquote = false;
libexec/tradcpp/macro.c
1234
inquote = false;
libexec/tradcpp/macro.c
1305
expstate_init(&mainstate, false, false);
libexec/tradcpp/macro.c
160
return false;
libexec/tradcpp/macro.c
165
return false;
libexec/tradcpp/macro.c
170
return false;
libexec/tradcpp/macro.c
192
m->hasparams = false;
libexec/tradcpp/macro.c
195
m->inuse = false;
libexec/tradcpp/macro.c
220
return false;
libexec/tradcpp/macro.c
224
return false;
libexec/tradcpp/macro.c
230
return false;
libexec/tradcpp/macro.c
237
return false;
libexec/tradcpp/macro.c
244
return false;
libexec/tradcpp/macro.c
251
return false;
libexec/tradcpp/macro.c
486
oldm = macrotable_find(m->name, false);
libexec/tradcpp/macro.c
563
return false;
libexec/tradcpp/macro.c
665
m = macrotable_find(macro, false);
libexec/tradcpp/macro.c
891
m = macrotable_find(name, false);
libexec/tradcpp/macro.c
900
assert(m->inuse == false);
libexec/tradcpp/macro.c
907
newbuf2 = macroexpand(p, newbuf, strlen(newbuf), false);
libexec/tradcpp/macro.c
915
m->inuse = false;
libexec/tradcpp/macro.c
977
m = macrotable_findlen(buf, len, false);
libexec/tradcpp/main.c
309
commandline_addfile(p, name, false);
libexec/tradcpp/main.c
325
bool save = false;
libexec/tradcpp/main.c
333
mode.do_output = false;
libexec/tradcpp/main.c
440
files_addquotepath(dir, false);
libexec/tradcpp/main.c
442
files_addquotepath(NULL, false);
libexec/tradcpp/main.c
447
files_addquotepath(dir, false);
libexec/tradcpp/main.c
448
files_addbracketpath(dir, false);
libexec/tradcpp/main.c
483
files_addquotepath(dir, false);
libexec/tradcpp/main.c
484
files_addbracketpath(dir, false);
libexec/tradcpp/main.c
49
.werror = false,
libexec/tradcpp/main.c
51
.input_allow_dollars = false,
libexec/tradcpp/main.c
59
.output_cheaplinenumbers = false,
libexec/tradcpp/main.c
60
.output_retain_comments = false,
libexec/tradcpp/main.c
609
mode.macrolist_include_stddef = false;
libexec/tradcpp/main.c
620
mode.do_output = false;
libexec/tradcpp/main.c
628
mode.macrolist_include_stddef = false;
libexec/tradcpp/main.c
629
mode.macrolist_include_expansions = false;
libexec/tradcpp/main.c
63
.do_depend = false,
libexec/tradcpp/main.c
64
.depend_report_system = false,
libexec/tradcpp/main.c
641
mode.trace_namesonly = false;
libexec/tradcpp/main.c
642
mode.trace_indented = false;
libexec/tradcpp/main.c
65
.depend_assume_generated = false,
libexec/tradcpp/main.c
66
.depend_issue_fakerules = false,
libexec/tradcpp/main.c
664
mode.depend_quote_target = false;
libexec/tradcpp/main.c
690
mode.do_output = false;
libexec/tradcpp/main.c
698
mode.depend_report_system = false;
libexec/tradcpp/main.c
699
mode.do_output = false;
libexec/tradcpp/main.c
71
.do_macrolist = false,
libexec/tradcpp/main.c
715
mode.depend_report_system = false;
libexec/tradcpp/main.c
72
.macrolist_include_stddef = false,
libexec/tradcpp/main.c
73
.macrolist_include_expansions = false,
libexec/tradcpp/main.c
731
warns.nestcomment = false;
libexec/tradcpp/main.c
732
warns.undef = false;
libexec/tradcpp/main.c
733
warns.unused = false;
libexec/tradcpp/main.c
740
warns.nestcomment = false;
libexec/tradcpp/main.c
741
warns.endiflabels = false;
libexec/tradcpp/main.c
742
warns.undef = false;
libexec/tradcpp/main.c
743
warns.unused = false;
libexec/tradcpp/main.c
75
.do_trace = false,
libexec/tradcpp/main.c
76
.trace_namesonly = false,
libexec/tradcpp/main.c
77
.trace_indented = false,
libexec/tradcpp/main.c
785
{ "P", &mode.output_linenumbers, false },
libexec/tradcpp/main.c
789
{ "Wno-comment", &warns.nestcomment, false },
libexec/tradcpp/main.c
790
{ "Wno-endif-labels", &warns.endiflabels, false },
libexec/tradcpp/main.c
791
{ "Wno-error", &mode.werror, false },
libexec/tradcpp/main.c
792
{ "Wno-undef", &warns.undef, false },
libexec/tradcpp/main.c
793
{ "Wno-unused-macros", &warns.unused, false },
libexec/tradcpp/main.c
797
{ "fno-dollars-in-identifiers", &mode.input_allow_dollars, false },
libexec/tradcpp/main.c
798
{ "nostdinc", &mode.do_stdinc, false },
libexec/tradcpp/main.c
800
{ "undef", &mode.do_stddef, false },
libexec/tradcpp/main.c
82
.nestcomment = false,
libexec/tradcpp/main.c
83
.undef = false,
libexec/tradcpp/main.c
84
.unused = false,
libexec/tradcpp/main.c
864
return false;
libexec/tradcpp/main.c
884
return false;
libexec/tradcpp/main.c
904
return false;
libexec/tradcpp/main.c
925
return false;
libexec/tradcpp/main.c
951
return false;
libexec/tradcpp/output.c
106
bool inesc = false;
libexec/tradcpp/output.c
107
bool inquote = false;
libexec/tradcpp/output.c
131
incomment = false;
libexec/tradcpp/output.c
141
inesc = false;
libexec/tradcpp/output.c
148
inquote = false;
libexec/tradcpp/output.c
42
static bool incomment = false;
libexec/tradcpp/place.c
241
return false;
libexec/tradcpp/place.c
244
return false;
libexec/tradcpp/place.c
253
return false;
libexec/tradcpp/place.c
256
return false;
libexec/tradcpp/utils.c
238
return false;
libexec/tradcpp/utils.c
241
return false;
regress/lib/libc/sys/t_dup.c
188
check_mode(false, true, false);
regress/lib/libc/sys/t_dup.c
263
check_mode(false, false, true);
regress/lib/libc/sys/t_dup.c
384
check_mode(true, false, false);
regress/lib/libc/sys/t_dup.c
76
if (_dup != false)
regress/lib/libc/sys/t_dup.c
78
else if (_dup2 != false)
regress/lib/libc/sys/t_dup.c
80
else if (_dup3 != false)
regress/lib/libc/sys/t_fork.c
317
ASSERT_EQ(!!WIFCONTINUED(status), false);
regress/lib/libc/sys/t_fork.c
318
ASSERT_EQ(!!WIFSIGNALED(status), false);
regress/lib/libc/sys/t_fork.c
319
ASSERT_EQ(!!WIFSTOPPED(status), false);
regress/lib/libc/sys/t_fork.c
328
ATF_REQUIRE_EQ(!!WIFCONTINUED(status), false);
regress/lib/libc/sys/t_fork.c
329
ATF_REQUIRE_EQ(!!WIFSIGNALED(status), false);
regress/lib/libc/sys/t_fork.c
330
ATF_REQUIRE_EQ(!!WIFSTOPPED(status), false);
regress/lib/libc/sys/t_getitimer.c
143
if (fail != false)
regress/lib/libc/sys/t_getitimer.c
52
fail = false;
regress/lib/libc/sys/t_msgget.c
203
bool fail = false;
regress/lib/libc/sys/t_msgget.c
242
if (fail != false)
regress/lib/libc/sys/t_sigaction.c
44
static bool handler_called = false;
regress/lib/libc/sys/t_sigaltstack.c
54
handler_use_altstack = false;
regress/lib/libc/sys/t_sigaltstack.c
84
handler_called = false;
regress/lib/libc/sys/t_write.c
127
if (fail != false)
regress/lib/libc/sys/t_write.c
48
static bool fail = false;
regress/lib/libc/sys/t_write.c
54
fail = false;
regress/lib/libm/msun/logarithm_test.c
251
if (atf_tc_get_config_var_as_bool_wd(tc, "ci", false))
regress/sys/kern/ptrace2/ptrace_test.c
235
if (atf_tc_get_config_var_as_bool_wd(tc, "ci", false))
sbin/mountd/mountd.c
1039
if (!xdr_bool(xdrsp, &false))
sbin/mountd/mountd.c
940
int true = 1, false = 0;
sbin/mountd/mountd.c
956
if (!xdr_bool(xdrsp, &false))
sbin/mountd/mountd.c
968
int false = 0, putdef;
sbin/mountd/mountd.c
980
if (!xdr_bool(xdrsp, &false))
sbin/mountd/mountd.c
995
int true = 1, false = 0, gotalldir = 0;
sys/arch/amd64/include/ghcb.h
180
_ghcb_mem_rw(addr, GHCB_SZ8, &v, false);
sys/arch/amd64/include/ghcb.h
186
_ghcb_mem_rw(addr, GHCB_SZ16, &v, false);
sys/arch/amd64/include/ghcb.h
192
_ghcb_mem_rw(addr, GHCB_SZ32, &v, false);
sys/arch/amd64/include/ghcb.h
198
_ghcb_mem_rw(addr, GHCB_SZ64, &v, false);
sys/arch/amd64/include/ghcb.h
233
_ghcb_io_rw(port, GHCB_SZ8, &val, false);
sys/arch/amd64/include/ghcb.h
241
_ghcb_io_rw(port, GHCB_SZ16, &val, false);
sys/arch/amd64/include/ghcb.h
247
_ghcb_io_rw(port, GHCB_SZ32, &v, false);
sys/arch/arm64/arm64/db_disasm.c
43
return db_get_value(address, sizeof(uint32_t), false);
sys/arch/arm64/arm64/disasm.c
628
return false;
sys/arch/arm64/arm64/disasm.c
632
return false;
sys/arch/arm64/arm64/disasm.c
637
return false;
sys/arch/arm64/arm64/disasm.c
686
return false;
sys/arch/arm64/arm64/disasm.c
691
return false;
sys/arch/arm64/arm64/disasm.c
693
return false;
sys/arch/arm64/arm64/disasm.c
698
return false;
sys/arch/arm64/arm64/disasm.c
708
return false;
sys/arch/arm64/arm64/disasm.c
710
return false;
sys/arch/arm64/arm64/disasm.c
713
return false;
sys/arch/arm64/arm64/disasm.c
716
return false;
sys/arch/armv7/omap/if_cpsw.c
1051
sc->sc_rxeoq = false;
sys/arch/armv7/omap/if_cpsw.c
1069
sc->sc_rxrun = false;
sys/arch/armv7/omap/if_cpsw.c
1107
sc->sc_rxrun = false;
sys/arch/armv7/omap/if_cpsw.c
1117
sc->sc_rxeoq = false;
sys/arch/armv7/omap/if_cpsw.c
1149
bool handled = false;
sys/arch/armv7/omap/if_cpsw.c
1160
sc->sc_txrun = false;
sys/arch/armv7/omap/if_cpsw.c
1186
sc->sc_txrun = false;
sys/arch/armv7/omap/if_cpsw.c
1222
sc->sc_txeoq = false;
sys/arch/armv7/omap/if_cpsw.c
622
sc->sc_txeoq = false;
sys/arch/armv7/omap/if_cpsw.c
934
sc->sc_rxeoq = false;
sys/arch/armv7/omap/if_cpsw.c
977
sc->sc_txrun = false;
sys/arch/armv7/omap/if_cpsw.c
979
sc->sc_rxrun = false;
sys/arch/luna88k/dev/siotty.c
227
sc->sc_tx_busy = false;
sys/arch/luna88k/dev/siotty.c
245
sc->sc_rx_ready = false;
sys/arch/luna88k/dev/siotty.c
249
sc->sc_tx_done = false;
sys/arch/luna88k/dev/xp.c
183
sc->sc_isopen = false;
sys/ddb/db_dwarf.c
119
return (false);
sys/ddb/db_dwarf.c
131
return (read_leb128(d, v, false));
sys/ddb/db_dwarf.c
140
return (false);
sys/ddb/db_dwarf.c
152
return (false);
sys/ddb/db_dwarf.c
164
return (false);
sys/ddb/db_dwarf.c
175
return (false);
sys/ddb/db_dwarf.c
182
return (false);
sys/ddb/db_dwarf.c
190
return (false);
sys/ddb/db_dwarf.c
204
return (false);
sys/ddb/db_dwarf.c
210
return (false);
sys/ddb/db_dwarf.c
234
return (false);
sys/ddb/db_dwarf.c
259
return (false);
sys/ddb/db_dwarf.c
264
bool basic_block = false, end_sequence = false;
sys/ddb/db_dwarf.c
265
bool prologue_end = false, epilogue_begin = false;
sys/ddb/db_dwarf.c
268
bool have_last = false;
sys/ddb/db_dwarf.c
274
bool emit = false, reset_basic_block = false;
sys/ddb/db_dwarf.c
389
basic_block = false;
sys/ddb/db_dwarf.c
438
showdir = false;
sys/ddb/db_dwarf.c
65
return (false);
sys/dev/fdt/bcm2835_sdhost.c
279
bcmsdhost_bus_clock(sc, 400, false);
sys/dev/fdt/qcdpc.c
250
edp_dpcd, ¤t_level, ¤t_mode, false);
sys/dev/fdt/rktcphy.c
242
rktcphy_set_usb2_only(sc, false);
sys/dev/fdt/rkvop.c
275
false, true);
sys/dev/i2c/ietp.c
359
require_wakeup = false;
sys/dev/ic/dwhdmi.c
411
return false;
sys/dev/ic/dwhdmi.c
606
dwhdmi_connector->hdmi_monitor = false;
sys/dev/ic/dwhdmi.c
607
dwhdmi_connector->monitor_audio = false;
sys/dev/ic/qwx.c
12715
reg_info->is_ext_reg_event = false;
sys/dev/ic/qwx.c
12878
bool intersect = false;
sys/dev/ic/qwx.c
20795
.lmac_ring = false,
sys/dev/ic/qwx.c
20808
.lmac_ring = false,
sys/dev/ic/qwx.c
20816
.lmac_ring = false,
sys/dev/ic/qwx.c
20825
.lmac_ring = false,
sys/dev/ic/qwx.c
20834
.lmac_ring = false,
sys/dev/ic/qwx.c
20843
.lmac_ring = false,
sys/dev/ic/qwx.c
20852
.lmac_ring = false,
sys/dev/ic/qwx.c
20861
.lmac_ring = false,
sys/dev/ic/qwx.c
20869
.lmac_ring = false,
sys/dev/ic/qwx.c
20877
.lmac_ring = false,
sys/dev/ic/qwx.c
20885
.lmac_ring = false,
sys/dev/ic/qwx.c
20893
.lmac_ring = false,
sys/dev/ic/qwx.c
20901
.lmac_ring = false,
sys/dev/ic/qwx.c
20909
.lmac_ring = false,
sys/dev/ic/qwx.c
26472
peer->rx_tid, 1, 0, false);
sys/dev/ic/qwx.c
3648
.internal_sleep_clock = false,
sys/dev/ic/qwx.c
3657
.single_pdev_only = false,
sys/dev/ic/qwx.c
3660
.rx_mac_buf_ring = false,
sys/dev/ic/qwx.c
3661
.vdev_start_delay = false,
sys/dev/ic/qwx.c
3680
.full_monitor_mode = false,
sys/dev/ic/qwx.c
3682
.supports_shadow_regs = false,
sys/dev/ic/qwx.c
3683
.idle_ps = false,
sys/dev/ic/qwx.c
3684
.supports_sta_ps = false,
sys/dev/ic/qwx.c
3690
.supports_suspend = false,
sys/dev/ic/qwx.c
3692
.supports_regdb = false,
sys/dev/ic/qwx.c
3694
.credit_flow = false,
sys/dev/ic/qwx.c
3698
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
3700
.supports_rssi_stats = false,
sys/dev/ic/qwx.c
3702
.fw_wmi_diag_event = false,
sys/dev/ic/qwx.c
3703
.current_cc_support = false,
sys/dev/ic/qwx.c
3705
.global_reset = false,
sys/dev/ic/qwx.c
3709
.m3_fw_support = false,
sys/dev/ic/qwx.c
3712
.static_window_map = false,
sys/dev/ic/qwx.c
3714
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
3715
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
3716
.support_off_channel_tx = false,
sys/dev/ic/qwx.c
3717
.supports_multi_bssid = false,
sys/dev/ic/qwx.c
3725
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
3740
.internal_sleep_clock = false,
sys/dev/ic/qwx.c
3749
.single_pdev_only = false,
sys/dev/ic/qwx.c
3752
.rx_mac_buf_ring = false,
sys/dev/ic/qwx.c
3753
.vdev_start_delay = false,
sys/dev/ic/qwx.c
3769
.full_monitor_mode = false,
sys/dev/ic/qwx.c
3771
.supports_shadow_regs = false,
sys/dev/ic/qwx.c
3772
.idle_ps = false,
sys/dev/ic/qwx.c
3773
.supports_sta_ps = false,
sys/dev/ic/qwx.c
3779
.supports_suspend = false,
sys/dev/ic/qwx.c
3781
.supports_regdb = false,
sys/dev/ic/qwx.c
3783
.credit_flow = false,
sys/dev/ic/qwx.c
3787
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
3789
.supports_rssi_stats = false,
sys/dev/ic/qwx.c
3791
.fw_wmi_diag_event = false,
sys/dev/ic/qwx.c
3792
.current_cc_support = false,
sys/dev/ic/qwx.c
3794
.global_reset = false,
sys/dev/ic/qwx.c
3798
.m3_fw_support = false,
sys/dev/ic/qwx.c
3801
.static_window_map = false,
sys/dev/ic/qwx.c
3802
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
3803
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
3805
.support_off_channel_tx = false,
sys/dev/ic/qwx.c
3806
.supports_multi_bssid = false,
sys/dev/ic/qwx.c
3814
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
3839
.rxdma1_enable = false,
sys/dev/ic/qwx.c
3843
.htt_peer_map_v2 = false,
sys/dev/ic/qwx.c
3851
.fragment_160mhz = false,
sys/dev/ic/qwx.c
3856
.supports_monitor = false,
sys/dev/ic/qwx.c
3857
.full_monitor_mode = false,
sys/dev/ic/qwx.c
3862
.cold_boot_calib = false,
sys/dev/ic/qwx.c
3863
.cbcal_restart_fw = false,
sys/dev/ic/qwx.c
3869
.supports_regdb = false,
sys/dev/ic/qwx.c
3875
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
3876
.alloc_cacheable_memory = false,
sys/dev/ic/qwx.c
3881
.dbr_debug_support = false,
sys/dev/ic/qwx.c
3887
.fixed_bdf_addr = false,
sys/dev/ic/qwx.c
3888
.fixed_mem_region = false,
sys/dev/ic/qwx.c
3889
.static_window_map = false,
sys/dev/ic/qwx.c
3890
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
3891
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
3905
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
3918
.single_pdev_only = false,
sys/dev/ic/qwx.c
3923
.internal_sleep_clock = false,
sys/dev/ic/qwx.c
3933
.rx_mac_buf_ring = false,
sys/dev/ic/qwx.c
3934
.vdev_start_delay = false,
sys/dev/ic/qwx.c
3943
.fragment_160mhz = false,
sys/dev/ic/qwx.c
3952
.supports_shadow_regs = false,
sys/dev/ic/qwx.c
3953
.idle_ps = false,
sys/dev/ic/qwx.c
3954
.supports_sta_ps = false,
sys/dev/ic/qwx.c
3955
.cold_boot_calib = false,
sys/dev/ic/qwx.c
3956
.cbcal_restart_fw = false,
sys/dev/ic/qwx.c
3960
.supports_suspend = false,
sys/dev/ic/qwx.c
3962
.supports_regdb = false,
sys/dev/ic/qwx.c
3964
.credit_flow = false,
sys/dev/ic/qwx.c
3970
.supports_rssi_stats = false,
sys/dev/ic/qwx.c
3972
.fw_wmi_diag_event = false,
sys/dev/ic/qwx.c
3973
.current_cc_support = false,
sys/dev/ic/qwx.c
3975
.global_reset = false,
sys/dev/ic/qwx.c
3980
.fixed_bdf_addr = false,
sys/dev/ic/qwx.c
3981
.fixed_mem_region = false,
sys/dev/ic/qwx.c
3983
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
3984
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
3986
.support_off_channel_tx = false,
sys/dev/ic/qwx.c
3987
.supports_multi_bssid = false,
sys/dev/ic/qwx.c
3995
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
4020
.rxdma1_enable = false,
sys/dev/ic/qwx.c
4024
.htt_peer_map_v2 = false,
sys/dev/ic/qwx.c
4032
.fragment_160mhz = false,
sys/dev/ic/qwx.c
4037
.supports_monitor = false,
sys/dev/ic/qwx.c
4038
.full_monitor_mode = false,
sys/dev/ic/qwx.c
4043
.cold_boot_calib = false,
sys/dev/ic/qwx.c
4044
.cbcal_restart_fw = false,
sys/dev/ic/qwx.c
4051
.fix_l1ss = false,
sys/dev/ic/qwx.c
4056
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
4057
.alloc_cacheable_memory = false,
sys/dev/ic/qwx.c
4062
.dbr_debug_support = false,
sys/dev/ic/qwx.c
4068
.fixed_bdf_addr = false,
sys/dev/ic/qwx.c
4069
.fixed_mem_region = false,
sys/dev/ic/qwx.c
4070
.static_window_map = false,
sys/dev/ic/qwx.c
4071
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
4072
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
4086
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
4111
.rxdma1_enable = false,
sys/dev/ic/qwx.c
4115
.htt_peer_map_v2 = false,
sys/dev/ic/qwx.c
4123
.fragment_160mhz = false,
sys/dev/ic/qwx.c
4128
.supports_monitor = false,
sys/dev/ic/qwx.c
4133
.cold_boot_calib = false,
sys/dev/ic/qwx.c
4134
.cbcal_restart_fw = false,
sys/dev/ic/qwx.c
4141
.fix_l1ss = false,
sys/dev/ic/qwx.c
4146
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
4147
.alloc_cacheable_memory = false,
sys/dev/ic/qwx.c
4152
.dbr_debug_support = false,
sys/dev/ic/qwx.c
4158
.fixed_bdf_addr = false,
sys/dev/ic/qwx.c
4159
.fixed_mem_region = false,
sys/dev/ic/qwx.c
4160
.static_window_map = false,
sys/dev/ic/qwx.c
4161
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
4162
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
4176
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
4191
.internal_sleep_clock = false,
sys/dev/ic/qwx.c
4201
.rxdma1_enable = false,
sys/dev/ic/qwx.c
4205
.htt_peer_map_v2 = false,
sys/dev/ic/qwx.c
4213
.fragment_160mhz = false,
sys/dev/ic/qwx.c
4218
.supports_monitor = false,
sys/dev/ic/qwx.c
4224
.cbcal_restart_fw = false,
sys/dev/ic/qwx.c
4228
.supports_suspend = false,
sys/dev/ic/qwx.c
4231
.fix_l1ss = false,
sys/dev/ic/qwx.c
4236
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
4237
.alloc_cacheable_memory = false,
sys/dev/ic/qwx.c
4240
.fw_wmi_diag_event = false,
sys/dev/ic/qwx.c
4242
.dbr_debug_support = false,
sys/dev/ic/qwx.c
4243
.global_reset = false,
sys/dev/ic/qwx.c
4247
.m3_fw_support = false,
sys/dev/ic/qwx.c
4248
.fixed_bdf_addr = false,
sys/dev/ic/qwx.c
4249
.fixed_mem_region = false,
sys/dev/ic/qwx.c
4259
.tcl_ring_retry = false,
sys/dev/ic/qwx.c
4288
.rxdma1_enable = false,
sys/dev/ic/qwx.c
4292
.htt_peer_map_v2 = false,
sys/dev/ic/qwx.c
4300
.fragment_160mhz = false,
sys/dev/ic/qwx.c
4305
.supports_monitor = false,
sys/dev/ic/qwx.c
4306
.full_monitor_mode = false,
sys/dev/ic/qwx.c
4311
.cold_boot_calib = false,
sys/dev/ic/qwx.c
4312
.cbcal_restart_fw = false,
sys/dev/ic/qwx.c
4319
.fix_l1ss = false,
sys/dev/ic/qwx.c
4324
.supports_dynamic_smps_6ghz = false,
sys/dev/ic/qwx.c
4325
.alloc_cacheable_memory = false,
sys/dev/ic/qwx.c
4330
.dbr_debug_support = false,
sys/dev/ic/qwx.c
4336
.fixed_bdf_addr = false,
sys/dev/ic/qwx.c
4337
.fixed_mem_region = false,
sys/dev/ic/qwx.c
4338
.static_window_map = false,
sys/dev/ic/qwx.c
4339
.hybrid_bus_type = false,
sys/dev/ic/qwx.c
4340
.fixed_fw_mem = false,
sys/dev/ic/qwx.c
4354
.smp2p_wow_exit = false,
sys/dev/ic/qwx.c
9671
cached = false;
sys/dev/ic/qwz.c
10410
reg_info->is_ext_reg_event = false;
sys/dev/ic/qwz.c
10571
bool intersect = false;
sys/dev/ic/qwz.c
1291
return false;
sys/dev/ic/qwz.c
15196
return false;
sys/dev/ic/qwz.c
1722
.rxdma1_enable = false,
sys/dev/ic/qwz.c
1728
.htt_peer_map_v2 = false,
sys/dev/ic/qwz.c
1729
.reoq_lut_support = false,
sys/dev/ic/qwz.c
1731
.fix_l1ss = false,
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
42
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1530
#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1658
static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1659
static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1660
static inline bool amdgpu_has_atpx(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1755
static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1758
static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1773
static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1774
static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
142
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
146
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
221
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
252
bool found = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
594
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
890
ret = amdgpu_ras_set_aca_debug_mode(adev, val ? true : false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
160
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
258
pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
511
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
568
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1332
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1336
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1344
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1367
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1371
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1379
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1398
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1402
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1405
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1410
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1469
atif->notification_cfg.enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1478
atif->backlight_caps.caps_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1481
atif->backlight_caps.caps_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1540
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1543
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1546
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1559
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1566
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
321
n->enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
655
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
513
mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
529
return amdgpu_dpm_get_sclk(adev, false) / 100;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
695
ret = dma_fence_wait(f, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
71
kfd_initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
732
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
899
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
210
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
281
bool valid = false; \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
458
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
540
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
546
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
239
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
334
suspend_resume_compute_scheduler(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
360
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
382
set_barrier_auto_waitcnt(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
386
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
124
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
136
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
176
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
180
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
180
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
478
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
510
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
774
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
783
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
800
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
876
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
464
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
497
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
453
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
485
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
167
bool valid_wptr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
325
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
356
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
162
bool valid_wptr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
357
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
388
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
489
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
521
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
711
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
734
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
810
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1059
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1294
ret = amdgpu_vm_bo_update(adev, bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1439
AMDGPU_FENCE_OWNER_KFD, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1495
ret = amdgpu_bo_reserve(bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1505
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1520
amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1538
ret = amdgpu_bo_reserve(bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1637
WRITE_ONCE(pinfo->block_mmu_notifications, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1894
bool is_imported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1946
ret = unreserve_bo_and_vms(&ctx, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2009
bool is_invalid_userptr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2092
ret = unreserve_bo_and_vms(&ctx, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2097
unreserve_bo_and_vms(&ctx, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2175
entry->is_mapped = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2183
unreserve_bo_and_vms(&ctx, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2397
add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2527
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2641
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2727
amdgpu_sync_wait(&sync, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2952
ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2957
AMDGPU_GEM_DOMAIN_GTT, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3012
ret = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3046
amdgpu_sync_wait(&sync_obj, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3123
add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3129
ret = amdgpu_bo_reserve(gws_bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3181
ret = amdgpu_bo_reserve(gws_bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3226
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
338
ret = amdgpu_bo_reserve(mem->bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
420
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
437
amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
447
int ret = amdgpu_bo_reserve(bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
471
return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
506
ret = amdgpu_vm_update_pdes(adev, vm, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
727
struct ttm_operation_ctx ctx = {.interruptible = false};
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
86
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
880
bool same_hive = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
962
ret = amdgpu_bo_reserve(bo[i], false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1002
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1046
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1048
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1068
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1070
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1368
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1373
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1377
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1555
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1627
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
192
gpio.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
295
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
298
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
308
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
332
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
335
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
385
router.ddc_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
386
router.cd_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
491
ddc_bus.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
65
i2c.hw_capable = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
70
i2c.mm_i2c = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
77
i2c.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
913
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
917
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
94
i2c.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
555
bool mem_ecc_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
558
adev->ras_default_ecc_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
571
(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
576
(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
583
(umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
585
(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
589
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
597
(umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
599
(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
603
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
607
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
627
return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
643
return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
698
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
85
return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
903
return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_benchmark.c
42
false, false, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_benchmark.c
45
r = dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
116
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
120
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
126
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
131
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
139
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
154
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
159
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
164
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
170
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
178
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
195
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
200
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
208
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
232
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
236
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
246
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
259
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
262
if (amdgpu_asic_read_bios_from_rom(adev, &header[0], sizeof(header)) == false)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
263
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
270
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
278
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
287
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
303
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
307
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
325
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
340
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
346
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
353
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
413
bool found = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
417
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
450
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
456
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
470
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
478
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
485
false : amdgpu_asic_read_disabled_bios(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
497
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
501
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
514
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
520
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
535
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
543
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
548
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
575
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
588
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
63
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
644
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
676
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
678
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
681
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
685
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
69
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
75
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
81
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
90
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1020
bool dret = false, broken_edid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1032
amdgpu_connector->detected_hpd_without_ddc = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1041
dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1058
amdgpu_connector->detected_by_load = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1124
amdgpu_connector->use_digital = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1137
amdgpu_connector->use_digital = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1190
amdgpu_connector->use_digital = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1377
bool found = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1398
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1481
false))
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1617
bool shared_ddc = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1618
bool is_dp_bridge = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1619
bool has_aux = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1640
amdgpu_connector->shared_ddc = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1641
shared_ddc = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1756
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1776
connector->interlace_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1777
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1886
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1935
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1983
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
2008
connector->interlace_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
2009
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
2032
connector->interlace_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
2033
connector->doublescan_allowed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
229
connected = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
383
mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
436
mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
469
new_coherent_mode = val ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
553
amdgpu_connector->dac_load_detect = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
751
amdgpu_connector->ddc_bus->has_aux = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
858
bool dret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
875
dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
877
amdgpu_connector->detected_by_load = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
962
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
164
amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
197
amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, poison,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
234
amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
451
return strcmp(chdr->signature, "CPER") ? false : true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
557
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
570
ring->use_doorbell = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
605
adev->cper.enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
1125
r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
1137
r = amdgpu_vm_bo_update(adev, bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
1157
r = amdgpu_vm_bo_update(adev, bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
1171
r = amdgpu_vm_update_pdes(adev, vm, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
1197
amdgpu_vm_bo_invalidate(bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
1783
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
291
p->jobs[i]->enforce_isolation = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
292
p->jobs[i]->run_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
300
p->jobs[i]->run_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
304
p->jobs[i]->run_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
806
.no_wait_gpu = false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
859
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
891
bool userpage_invalidated = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c
63
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c
711
r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
112
use_bank = use_ring = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1308
amdgpu_set_gfx_off_residency(adev, value ? true : false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1407
amdgpu_gfx_off_ctrl(adev, value ? true : false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1887
preempted = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
204
return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
81
pm_pg_lock = use_bank = use_ring = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1791
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1795
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1797
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1823
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1826
adev->has_hw_reset = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1838
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1858
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1862
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1866
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1869
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1896
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1917
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1930
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1944
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1948
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1951
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1971
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1975
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1978
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1980
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2455
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2590
adev->enable_virtual_display = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2891
adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2893
adev->has_pr3 = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2905
adev->virt.is_xgmi_node_migrate_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2918
adev->ip_blocks[i].status.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2922
adev->ip_blocks[i].status.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2928
total = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2984
if (ip_block->status.valid != false)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
329
ip_block->status.hw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3390
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3403
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3650
ip_block->status.hw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3709
if (amdgpu_virt_release_full_gpu(adev, false))
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3767
adev->ip_blocks[i].status.sw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3768
adev->ip_blocks[i].status.valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3778
adev->ip_blocks[i].status.late_initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3885
adev->ip_blocks[i].status.hw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3934
adev->ip_blocks[i].status.hw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3970
amdgpu_virt_request_full_gpu(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3973
amdgpu_ttm_set_buffer_funcs_status(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3981
amdgpu_virt_release_full_gpu(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4002
block->status.hw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4242
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4258
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4280
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4296
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
437
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4446
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4455
adev->gfx.mcbp = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4479
bool px = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4483
adev->shutdown = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4495
adev->accel_working = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
451
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
456
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4752
adev->have_atomics_support = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4955
adev->ucode_sysfs_en = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5100
amdgpu_virt_request_full_gpu(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5130
amdgpu_ttm_set_buffer_funcs_status(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5162
adev->accel_working = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5286
adev->in_s4 = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5381
r = amdgpu_virt_request_full_gpu(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5390
drm_client_dev_suspend(adev_to_drm(adev), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5405
amdgpu_ttm_set_buffer_funcs_status(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5412
amdgpu_virt_release_full_gpu(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5522
drm_client_dev_resume(adev_to_drm(adev), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5549
adev->in_suspend = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5570
bool asic_hang = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5652
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5712
adev->in_s0ix = adev->in_s3 = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5824
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5875
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5908
adev->no_hw_access = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5933
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5998
amdgpu_fence_driver_isr_toggle(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6052
bool full_reset, vram_lost = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6077
amdgpu_reset_set_dpc_status(tmp_adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6092
amdgpu_coredump(tmp_adev, false, vram_lost, reset_context->job);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6138
drm_client_dev_resume(adev_to_drm(tmp_adev), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6471
amdgpu_ras_set_error_query_ready(tmp_adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6483
drm_client_dev_suspend(adev_to_drm(tmp_adev), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6663
bool job_signaled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6666
bool need_emergency_restart = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7075
!(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7095
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7108
adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
715
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7191
hive, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7364
tmp_adev->pcie_reset_ctx.in_link_reset = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7371
amdgpu_device_gpu_resume(adev, &device_list, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7448
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7455
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7465
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7469
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7481
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7488
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7496
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7762
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7790
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
801
GC_HWIP, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1821
amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1827
sizeof(*nps_data), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
301
sz_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
308
adev->mman.discovery_tmr_size, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
107
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1136
block_size_log2 = get_dcc_block_size(modifier, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
116
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1172
*tmz_surface = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1173
*gfx12_dcc = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1178
r = amdgpu_bo_reserve(rbo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1436
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1614
in_vbl = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1692
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1695
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
230
r = amdgpu_bo_reserve(new_abo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
290
if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
317
bool active = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
349
adev->have_disp_power_ref = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
520
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
531
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
692
r = amdgpu_bo_reserve(rbo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
101
pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
102
attach->peer2peer = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
193
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
283
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
293
ret = amdgpu_bo_reserve(bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
376
.allow_res_evict = false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
461
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
469
amdgpu_vm_bo_invalidate(bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
593
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
601
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
606
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
614
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
98
attach->peer2peer = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2338
bool supports_atomic = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2675
adev->in_s0ix = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2677
adev->in_s3 = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
270
.timeout_fatal_disable = false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2869
ret = amdgpu_device_suspend(drm_dev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2871
adev->in_runpm = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2936
ret = amdgpu_device_resume(drm_dev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2945
adev->in_runpm = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
3368
bool supports_atomic = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
3530
adev->irq.msi_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
3773
dev->registered = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
3920
amdgpu_asic_set_vga_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
4027
adev->in_s4 = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c
239
false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
229
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
234
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
237
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
244
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
251
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
256
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
260
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_eviction_fence.c
196
dma_fence_wait(&ev_fence->base, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
156
r = dma_fence_wait(old, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
251
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
329
r = dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
491
ring->fence_drv.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
542
bool is_gfx_power_domain = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
642
ring->fence_drv.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
113
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
49
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
75
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
79
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
86
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
94
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c
103
false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c
89
false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gart.c
241
ret = amdgpu_bo_reserve(adev->gart.bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
336
r = amdgpu_bo_reserve(abo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
554
r = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
607
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
76
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
794
r = amdgpu_bo_reserve(robj, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
866
r = amdgpu_vm_bo_update(adev, bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
872
r = amdgpu_vm_update_pdes(adev, vm, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1501
r = dma_fence_wait(f, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
165
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
189
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
202
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2073
adev->gfx.userq_sch_inactive[idx] = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2094
bool wait = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2147
bool sched_work = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2171
amdgpu_gfx_kfd_sch_ctrl(adev, idx, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2187
bool sched_work = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2231
r = amdgpu_dpm_switch_power_profile(adev, profile, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2236
adev->gfx.workload_profile_active = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2384
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2454
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
816
!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false, 0)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
817
adev->gfx.gfx_off_state = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
849
bool no_delay = adev->in_s0ix ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
553
#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false))
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1027
adev->mman.keep_stolen_vga_memory = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1476
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1533
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1551
valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1566
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
474
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
712
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
78
r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
882
adev->gmc.tmz_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
912
adev->gmc.tmz_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
922
adev->gmc.tmz_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c
310
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
110
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
75
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
82
false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
140
bool need_pipe_sync = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
169
init_shadow = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
252
secure = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
263
amdgpu_ring_emit_frame_cntl(ring, false, secure);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
274
amdgpu_ring_emit_frame_cntl(ring, false, secure);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
289
amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
313
ring->funcs->emit_wave_limit(ring, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
379
adev->ib_pool_ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
451
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
457
adev->accel_working = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
135
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
152
false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
539
id_mgr->reserved_vmid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
244
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
287
adev->irq.msi_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
334
adev->irq.msi_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
342
adev->irq.installed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
452
bool handled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
676
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
679
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
682
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c
48
amdgpu_coredump(adev, true, false, job);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
241
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
378
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
551
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
1281
r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
883
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
923
dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
924
dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
37
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
521
ret = amdgpu_ras_set_mca_debug_mode(adev, val ? true : false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
613
bool need_retry = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
737
r |= amdgpu_mes_set_enforce_isolation(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
752
mem, adev->mes.event_log_size, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c
62
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1371
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1425
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
252
bool free = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
281
r = amdgpu_bo_reserve(*bo_ptr, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
398
r = amdgpu_bo_reserve(*bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
450
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
577
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
585
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
595
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
610
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
616
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
835
false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
936
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
99
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
193
r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_preempt_mgr.c
134
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
100
psp->pmfw_centralized_cstate_management = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
119
psp->pmfw_centralized_cstate_management = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1286
psp->asd_context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1430
psp->xgmi_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
176
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
177
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
182
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
183
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
188
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1887
psp->ras_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
189
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2000
psp->ras_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
203
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
208
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
209
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
212
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2142
psp->hdcp_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
217
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
221
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2216
psp->dtm_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2280
psp->rap_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
233
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
239
psp->autoload_supported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
240
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2416
psp->securedisplay_context.context.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2456
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2465
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
247
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2470
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
251
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
260
psp->boot_time_tmr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3025
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3149
ret = psp_xgmi_initialize(psp, false, true);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3356
ret = psp_xgmi_initialize(psp, false, true);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
372
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
378
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
385
sizeof(struct psp_runtime_data_header), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
390
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
395
sizeof(struct psp_runtime_data_directory), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
400
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
411
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
415
(uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
4204
adev->psp.vbflash_done = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
422
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
426
(uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
430
ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
466
adev->scpm_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
687
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
700
bool ras_intr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
701
bool skip_unsupport = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
906
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
487
((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
489
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c
62
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_rap.c
72
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1228
blk_name, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1251
blk_name, true, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1274
blk_name, false, true);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
170
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
202
err_data.err_addr_cnt, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2118
ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
222
bool hit = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2284
bool poison_stat = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2721
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2873
&addr_in, NULL, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2910
&addr_in, NULL, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3410
return ret ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3653
control->is_eeprom_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3663
con->update_channel_flag = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3817
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3831
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4136
con->update_channel_flag = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4285
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4461
amdgpu_ras_set_aca_debug_mode(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4463
amdgpu_ras_set_mca_debug_mode(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4567
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4620
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4723
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4835
if (notifier_registered == false) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4962
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4980
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5040
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5049
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5064
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5406
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5466
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5533
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
1387
ras->is_rma = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
1569
control->is_eeprom_valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
166
return (adev->gmc.is_app_apu) ? false : true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
168
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
179
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
232
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
490
con->update_channel_flag = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
561
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
565
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
568
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
578
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
586
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_res_cursor.h
185
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_res_cursor.h
188
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.c
44
adev->ip_blocks[i].status.hw = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
408
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
466
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
587
amdgpu_virt_req_ras_cper_dump(ring->adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
783
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
786
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
854
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
128
mux->s_resubmit = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
160
mux->s_resubmit = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
573
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
576
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
588
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
598
mux->pending_trailing_fence_signaled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c
76
adev->gfx.rlc.in_safe_mode[xcc_id] = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sa.c
84
GFP_KERNEL, false, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
384
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
390
page->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
527
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
534
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c
106
r = amdgpu_vm_bo_update(adev, *bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
149
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
202
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
208
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
218
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
224
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
228
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
77
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1016
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1109
gtt->bound = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1346
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1353
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1368
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1381
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1465
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1476
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1488
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1492
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1513
amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1583
if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1647
amdgpu_bo_move_notify(bo, false, NULL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1797
bool mem_train_support = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1876
false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2005
amdgpu_ttm_set_buffer_funcs_status(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2244
adev->mman.initialized = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2369
resv, vm_needs_flush, &job, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2418
r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2484
1, ring, false, &size, &addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2535
1, ring, false, &cur_size, &to);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2620
amdgpu_device_vram_access(adev, *pos, value, bytes, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
356
&next, false, true, copy_flags);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
411
false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
423
r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
431
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
449
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
457
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
462
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
478
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
483
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
782
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
79
false, size_in_page);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
214
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c
1412
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c
530
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c
169
err_data->err_addr_cnt, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c
177
con->update_channel_flag = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c
509
&addr_out, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c
81
err_data.err_addr_cnt, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c
97
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1123
adev->userq_halt_for_enforce_isolation = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
590
skip_map_queue = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
705
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
762
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
77
r = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
773
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
796
ret = amdgpu_vm_bo_update(adev, bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
848
ret = amdgpu_vm_update_pdes(adev, vm, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
858
dma_fence_wait(bo_va->last_pt_update, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
859
dma_fence_wait(vm->last_update, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
346
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
398
r = amdgpu_bo_reserve(queue->vm->root.bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1183
amdgpu_bo_fence(bo, f, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1278
amdgpu_dpm_enable_uvd(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1337
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1348
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
144
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
531
r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
538
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
581
struct ttm_operation_ctx tctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
1163
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
296
r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
343
amdgpu_dpm_enable_vce(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
420
r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
605
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1077
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1416
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
158
adev->vcn.inst[i].indirect_sram = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
299
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
437
pg = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
444
adev, PP_SMC_POWER_PROFILE_VIDEO, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
451
adev->vcn.workload_profile_active = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
748
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
820
ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
879
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1024
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1180
amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1195
xnack_mode = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1205
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1363
amdgpu_virt_req_ras_err_count_internal(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1492
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1531
*hit = tmp->hit ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
246
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
337
virt->ras_init_done = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
415
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
507
adev->virt.is_mm_bw_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
785
bool is_sriov = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
819
is_sriov = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
848
bool is_sriov = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
859
return amdgpu_sriov_is_debug(adev) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
864
return amdgpu_sriov_is_normal(adev) ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
916
adev->gfx.is_poweron = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
919
adev->mes.ring[0].sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
929
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
942
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
963
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
984
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
402
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1028
bool flush_tlb_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1395
uncached = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1428
r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1454
bo_va->base.moved = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
152
rb_insert_color_cached(&node->rb, root, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1539
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1631
r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1684
r = amdgpu_vm_bo_update(adev, bo_va, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1698
clear = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1702
clear = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1703
unlock = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1707
unlock = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1752
bool all_hub = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2028
valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2300
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2304
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2309
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
253
vm_bo->moved = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2676
vm->is_compute_context = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2698
vm->evicting = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2702
false, &root, xcp_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2718
r = amdgpu_vm_pt_clear(adev, vm, root, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2825
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2856
dma_fence_wait(vm->last_unlocked, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2858
dma_fence_wait(vm->last_tlb_flush, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2867
prt_fini_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3031
bool is_compute_context = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3049
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3098
r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3113
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
708
vm->evicting = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
761
has_compute_vm_bug = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
780
ring->has_compute_vm_bug = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
801
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
812
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
839
bool cleaner_shader_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
840
bool pasid_mapping_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
683
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
184
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
215
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
223
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
243
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
364
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c
57
dma_fence_wait(f->dependency, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c
90
dma_fence_wait(*fence, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
331
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
380
vpe->context_started = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
642
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
693
amdgpu_dpm_enable_vpe(adev, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
694
vpe->context_started = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
853
ret = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
68
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
76
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
815
drm_buddy_reset_clear(mm, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
849
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
879
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
974
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
155
xcp_mgr->xcp[i].valid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
254
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1020
ret = psp_xgmi_initialize(&adev->psp, false, true);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1083
&adev->psp.xgmi_context.top_info, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1101
&tmp_adev->psp.xgmi_context.top_info, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1135
ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1442
mask_data, &ue_cnt, &ce_cnt, true, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1449
mask_data, &ue_cnt, &ce_cnt, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1458
mask_data, &ue_cnt, &ce_cnt, true, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1465
mask_data, &ue_cnt, &ce_cnt, false, false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1485
mask_data, &ue_cnt, &ce_cnt, false, true);
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1725
reset_scheduled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
956
return false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
972
ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false);
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
350
return false;
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
367
return false;
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
370
return false;
sys/dev/pci/drm/amd/amdgpu/atom.c
1244
ectx.abort = false;
sys/dev/pci/drm/amd/amdgpu/atom.c
1627
return false;
sys/dev/pci/drm/amd/amdgpu/atom.c
1647
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
569
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
757
amdgpu_crtc->ss_enabled = false;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
115
amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
463
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
465
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
612
clock_recovery = false;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
679
channel_eq = false;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
748
dp_info.tp3_supported = false;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
750
dp_info.tp3_supported = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1178
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1367
amdgpu_dig_connector->edp_on = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1685
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1713
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
2035
lvds->linkb = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
2041
bool bad_record = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
2122
dig->linkb = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
274
return false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
760
bool is_dp = false;
sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c
99
amdgpu_atombios_copy_swap(buf, base, num, false);
sys/dev/pci/drm/amd/amdgpu/cik.c
1020
return false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1022
return false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1025
return false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1116
{mmGB_BACKEND_MAP, false},
sys/dev/pci/drm/amd/amdgpu/cik.c
1373
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
sys/dev/pci/drm/amd/amdgpu/cik.c
1408
baco_reset = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1460
clock, false, ÷rs);
sys/dev/pci/drm/amd/amdgpu/cik.c
1501
ecclk, false, ÷rs);
sys/dev/pci/drm/amd/amdgpu/cik.c
1692
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1693
bool disable_clkreq = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1776
clk_req_support = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1781
clk_req_support = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1936
return false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1945
return false;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
305
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
354
return false;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
91
adev->irq.ih.enabled = false;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1004
cik_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1005
cik_sdma_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1029
return false;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1187
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1225
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
536
cik_sdma_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
576
cik_sdma_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
686
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
296
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
350
return false;
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
91
adev->irq.ih.enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1012
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1047
amdgpu_dpm_get_mclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1049
amdgpu_dpm_get_sclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1059
wm_high.interlaced = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1098
wm_low.interlaced = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1189
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1451
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1456
dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1470
adev->mode_info.audio.enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1590
dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1759
dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1855
bool bypass_lut = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1873
r = amdgpu_bo_reserve(abo, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2008
dce_v10_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2355
dce_v10_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2393
ret = amdgpu_bo_reserve(aobj, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2429
dce_v10_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2458
dce_v10_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2505
dce_v10_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2521
dce_v10_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2524
amdgpu_crtc->enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2568
dce_v10_0_grph_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2590
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2643
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2646
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2648
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2654
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
283
bool connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2881
adev->mode_info.mode_config_initialized = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2894
dce_v10_0_set_vga_render_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2903
dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2919
dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3421
amdgpu_atombios_scratch_regs_lock(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3433
dce_v10_0_afmt_enable(encoder, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3560
amdgpu_encoder->is_ext_encoder = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
436
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
487
dce_v10_0_set_vga_render_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
957
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
977
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1161
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1440
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1445
dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1459
adev->mode_info.audio.enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1757
dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1773
dce_v6_0_audio_set_mute(encoder, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1802
dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1892
bool bypass_lut = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1910
r = amdgpu_bo_reserve(abo, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2029
dce_v6_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2328
dce_v6_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2366
ret = amdgpu_bo_reserve(aobj, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2402
dce_v6_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2430
dce_v6_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
247
bool connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2491
amdgpu_crtc->enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2536
dce_v6_0_grph_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2557
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2610
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2613
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2615
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2621
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2829
adev->mode_info.mode_config_initialized = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2840
dce_v6_0_set_vga_render_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2849
dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2865
dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3312
amdgpu_atombios_scratch_regs_lock(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3325
dce_v6_0_afmt_enable(encoder, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3456
amdgpu_encoder->is_ext_encoder = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
403
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
439
dce_v6_0_set_vga_render_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
810
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
830
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
865
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
909
amdgpu_dpm_get_mclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
911
amdgpu_dpm_get_sclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
921
wm_high.interlaced = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
948
wm_low.interlaced = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1000
amdgpu_dpm_get_mclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1002
amdgpu_dpm_get_sclk(adev, false) * 10;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1012
wm_high.interlaced = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1051
wm_low.interlaced = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1144
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1432
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1437
dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1451
adev->mode_info.audio.enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1557
dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1706
dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1802
bool bypass_lut = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1820
r = amdgpu_bo_reserve(abo, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1941
dce_v8_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2274
dce_v8_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
231
bool connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2312
ret = amdgpu_bo_reserve(aobj, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2348
dce_v8_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2377
dce_v8_0_lock_cursor(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2424
dce_v8_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2440
dce_v8_0_vga_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2443
amdgpu_crtc->enabled = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2487
dce_v8_0_grph_enable(crtc, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2508
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2516
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2569
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2572
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2574
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2580
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2800
adev->mode_info.mode_config_initialized = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2811
dce_v8_0_set_vga_render_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2820
dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2836
dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3329
amdgpu_atombios_scratch_regs_lock(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3341
dce_v8_0_afmt_enable(encoder, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3468
amdgpu_encoder->is_ext_encoder = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
387
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
445
dce_v8_0_set_vga_render_state(adev, false);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
910
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
930
return false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
965
return false;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
100
adev->df.funcs->enable_broadcast_mode(adev, false);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
34
adev->df.hash_status.hash_64k = false;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
35
adev->df.hash_status.hash_2m = false;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
36
adev->df.hash_status.hash_1g = false;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
218
adev->df.hash_status.hash_64k = false;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
219
adev->df.hash_status.hash_2m = false;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
220
adev->df.hash_status.hash_1g = false;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
332
adev->df.funcs->enable_broadcast_mode(adev, false);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
574
false);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
622
false);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
664
return false;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
668
return false;
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
51
return false;
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
55
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4108
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4142
adev->gfx.cp_fw_write_wait = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4178
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4186
ret = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4810
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4829
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4843
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4857
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4863
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5513
gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6340
gfx_v10_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6640
adev->gfx.kiq[0].ring.sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6656
gfx_v10_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6894
r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7213
false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7227
gfx_v10_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7322
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7558
gfx_v10_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7564
gfx_v10_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7565
gfx_v10_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7586
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7666
gfx_v10_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7669
gfx_v10_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7770
gfx_v10_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7775
gfx_v10_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7780
gfx_v10_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7785
gfx_v10_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7860
return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8323
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8338
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8349
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8455
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8664
(!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8821
(!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8884
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9039
bool fw_version_ok = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9727
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9737
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9768
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1651
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1666
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1680
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1694
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1708
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1714
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2290
gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3578
gfx_v11_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3869
gfx_v11_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3921
gfx_v11_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4216
r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4558
r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4572
gfx_v11_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4892
gfx_v11_0_set_userq_eop_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4915
gfx_v11_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4916
gfx_v11_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4920
adev->gfx.is_poweron = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4941
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5053
r = gfx_v11_0_request_gfx_index_mutex(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5148
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5166
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5198
gfx_v11_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5203
gfx_v11_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5208
gfx_v11_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5213
gfx_v11_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5226
adev->gfx.disable_kq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5230
adev->gfx.disable_kq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5231
adev->gfx.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5235
adev->gfx.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5296
return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5575
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5675
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6179
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
641
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6762
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6826
bool use_mmio = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
706
adev->gfx.cp_gfx_shadow = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7096
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
710
adev->gfx.cp_gfx_shadow = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7106
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7139
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1446
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1955
gfx_v12_0_rlc_smu_handshake_cntl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2643
gfx_v12_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2816
gfx_v12_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3094
r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3437
r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3451
gfx_v12_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3750
gfx_v12_0_set_userq_eop_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3765
gfx_v12_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3773
gfx_v12_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3774
gfx_v12_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3778
adev->gfx.is_poweron = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3799
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3843
adev->gfx.disable_kq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3847
adev->gfx.disable_kq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3848
adev->gfx.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3852
adev->gfx.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3909
return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4608
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5175
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5185
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5211
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5236
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5300
bool use_mmio = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
534
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1917
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1961
gfx_v6_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2268
gfx_v6_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2466
gfx_v6_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2495
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2571
gfx_v6_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2913
gfx_v6_0_update_gfx_pg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2915
gfx_v6_0_enable_cp_pg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2916
gfx_v6_0_enable_gds_pg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3091
ring->use_doorbell = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3152
gfx_v6_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3174
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3382
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3388
gfx_v6_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3393
gfx_v6_0_enable_cgcg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3394
gfx_v6_0_enable_mgcg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3404
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3457
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2322
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2416
gfx_v7_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2671
gfx_v7_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3080
gfx_v7_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3374
gfx_v7_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3464
gfx_v7_0_enable_lbpw(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3478
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3518
gfx_v7_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3621
gfx_v7_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3627
gfx_v7_0_enable_cgcg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3628
gfx_v7_0_enable_mgcg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3933
gfx_v7_0_update_gfx_pg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3935
gfx_v7_0_enable_cp_pg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3936
gfx_v7_0_enable_gds_pg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4463
gfx_v7_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4485
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4542
gfx_v7_0_update_cg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4820
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4826
gfx_v7_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4832
gfx_v7_0_enable_cgcg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4833
gfx_v7_0_enable_mgcg(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4843
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4912
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4946
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1053
adev->virt.chained_ib_support = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1612
r = dma_fence_wait(f, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3884
new_entry = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4045
gfx_v8_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4286
adev->gfx.kiq[0].ring.sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4715
gfx_v8_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4804
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4814
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4868
gfx_v8_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4948
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4969
gfx_v8_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4987
gfx_v8_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5323
cz_enable_gfx_cg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5324
cz_enable_gfx_pipeline_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5350
cz_enable_sck_slow_down_on_power_up(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5351
cz_enable_sck_slow_down_on_power_down(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5356
cz_enable_cp_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5363
gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5368
gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5376
gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5381
gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5386
polaris11_enable_gfx_quick_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5495
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5548
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5731
gfx_v8_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6726
gfx_v8_0_parse_sq_irq(adev, ih_data, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6848
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6894
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6929
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
902
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1258
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1295
adev->gfx.me_fw_write_wait = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1296
adev->gfx.mec_fw_write_wait = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1397
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1405
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1415
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1543
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2251
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2263
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2269
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3122
gfx_v9_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3219
gfx_v9_0_enable_lbpw(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3228
gfx_v9_0_enable_lbpw(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3283
gfx_v9_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3472
adev->gfx.kiq[0].ring.sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3487
gfx_v9_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3929
r = gfx_v9_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3943
gfx_v9_0_enable_gui_idle_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3959
gfx_v9_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3960
gfx_v9_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4064
gfx_v9_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4087
gfx_v9_0_cp_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4116
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4172
gfx_v9_0_cp_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4175
gfx_v9_0_cp_compute_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4290
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4317
gfx_v9_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4322
gfx_v9_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4327
gfx_v9_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4332
gfx_v9_0_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4779
r = dma_fence_wait(f, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4890
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4930
gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4932
gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4947
gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4952
gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5176
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5191
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5202
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5239
amdgpu_gfx_off_ctrl_immediate(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5245
gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5246
gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5252
gfx_v9_0_enable_cp_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5432
true : false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5722
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5815
flags & AMDGPU_IB_PREEMPTED) ? true : false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7303
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7313
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
567
r = dma_fence_wait(fences[0], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
573
r = dma_fence_wait(fences[1], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
607
r = dma_fence_wait(fences[2], false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
673
r = dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
683
false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1052
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1058
adev->gfx.enable_cleaner_shader = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1404
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1525
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1704
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1720
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1746
adev->gfx.kiq[xcc_id].ring.sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1764
gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2233
r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2246
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2255
gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2348
gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2411
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2466
gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2495
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2500
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2505
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2510
gfx_v9_4_3_write_data_to_reg(ring, 0, false,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3503
return false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
485
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4957
is_symmetric_cus = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
906
return false;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
649
value = false;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
628
gfxhub_v2_1_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
70
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
78
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
69
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
78
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
60
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
68
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1083
gmc_v6_0_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1102
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
553
gmc_v6_0_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
968
return false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1154
return false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1277
gmc_v7_0_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1305
info->prot_valid = protections & 0x7 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1306
info->prot_read = protections & 0x8 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1307
info->prot_write = protections & 0x10 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1308
info->prot_exec = protections & 0x20 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1318
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
697
gmc_v7_0_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1277
return false;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1328
return false;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1455
gmc_v8_0_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1493
info->prot_valid = protections & 0x7 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1494
info->prot_read = protections & 0x8 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1495
info->prot_write = protections & 0x10 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1496
info->prot_exec = protections & 0x20 ? true : false;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
937
gmc_v8_0_set_fault_enable_default(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1124
bool snoop = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1393
return false;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1661
adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
2220
value = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
2280
adev->mmhub.funcs->update_power_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
802
return false;
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
295
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
344
return false;
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
91
adev->irq.ih.enabled = false;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
183
ih->enabled = false;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
330
ret = ih_v6_0_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
352
ih[i]->overflow = false;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
417
force_update_wptr_for_self_int(adev, 0, 8, false);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
418
ih_v6_0_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
155
ih->enabled = false;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
302
ret = ih_v6_1_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
388
force_update_wptr_for_self_int(adev, 0, 8, false);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
389
ih_v6_1_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
155
ih->enabled = false;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
302
ret = ih_v7_0_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
388
force_update_wptr_for_self_int(adev, 0, 8, false);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
389
ih_v7_0_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
357
val_l = imu_v12_0_grbm_gfx_index_remap(adev, data, false);
sys/dev/pci/drm/amd/amdgpu/isp_v4_1_1.c
80
return amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ISP, false, 0);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
558
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
402
amdgpu_dpm_enable_jpeg(adev, false);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
421
amdgpu_dpm_enable_jpeg(adev, false);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
581
amdgpu_dpm_enable_jpeg(adev, false);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1427
return false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1432
return false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
973
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
597
amdgpu_dpm_enable_jpeg(adev, false);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
507
amdgpu_dpm_enable_jpeg(adev, false);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
1042
return false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
1047
return false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
660
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c
132
queue_input.paging = false;
sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c
224
r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false,
sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c
306
userq_props->hqd_active = false;
sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c
72
ret = amdgpu_bo_reserve(wptr_vm->root.bo, false);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1014
mes_v11_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1571
r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1604
adev->mes.enable_legacy_queue_map = false;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1623
adev->mes.ring[0].sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1631
mes_v11_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1689
adev->gfx.kiq[0].ring.sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
412
gfx_v11_0_request_gfx_index_mutex(adev, false);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1157
mes_v12_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1183
mes_v12_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1457
kiq_ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1721
adev->mes.ring[0].sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1748
r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1808
adev->mes.ring[0].sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1811
mes_v12_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1876
adev->gfx.kiq[0].ring.sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
437
gfx_v12_0_request_gfx_index_mutex(adev, false);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
824
return false;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
829
return false;
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
132
xgpu_ai_mailbox_set_valid(adev, false);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
160
xgpu_ai_mailbox_set_valid(adev, false);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
150
xgpu_nv_mailbox_set_valid(adev, false);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
170
xgpu_nv_mailbox_set_valid(adev, false);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
443
xgpu_vi_mailbox_set_valid(adev, false);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
181
ih->enabled = false;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
325
ret = navi10_ih_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
388
force_update_wptr_for_self_int(adev, 0, 8, false);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
389
navi10_ih_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
570
use_bus_addr = false;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
82
if (use_doorbell == false)
sys/dev/pci/drm/amd/amdgpu/nv.c
1022
adev->nbio.funcs->enable_doorbell_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/nv.c
1023
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/nv.c
332
return false;
sys/dev/pci/drm/amd/amdgpu/nv.c
437
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
sys/dev/pci/drm/amd/amdgpu/nv.c
547
return false;
sys/dev/pci/drm/amd/amdgpu/nv.c
556
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
485
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
564
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
574
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
653
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
868
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
871
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
879
con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
882
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
892
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
905
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
918
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
921
return false;
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
439
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
518
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
304
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1118
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
509
sdma_v2_4_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
622
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
858
ring->use_doorbell = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
899
sdma_v2_4_enable(ip_block->adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
921
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1187
sdma_v3_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1188
sdma_v3_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1210
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1249
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1265
sdma_v3_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1266
sdma_v3_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1560
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
782
sdma_v3_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
783
sdma_v3_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
896
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1347
sdma_v4_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1388
sdma_v4_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1389
sdma_v4_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1554
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1746
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1750
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1766
adev->sdma.has_page_queue = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1947
amdgpu_sdma_destroy_inst_ctx(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1959
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1982
sdma_v4_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1983
sdma_v4_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1997
sdma_v4_0_gfx_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2027
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
637
ret = amdgpu_sdma_init_microcode(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1150
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1338
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1340
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1460
adev->sdma.instance[i].gfx_guilty = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1461
adev->sdma.instance[i].page_guilty = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1546
amdgpu_sdma_destroy_inst_ctx(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1563
r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1585
sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1586
sdma_v4_4_2_inst_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1618
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1668
r = amdgpu_sdma_reset_engine(adev, id, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1685
sdma_v4_4_2_is_queue_selected(adev, instance_id, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
204
ret = amdgpu_sdma_init_microcode(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2397
r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2415
sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2416
sdma_v4_4_2_inst_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2570
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2575
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
929
sdma_v4_4_2_inst_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
974
sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
975
sdma_v4_4_2_inst_enable(adev, false, inst_mask);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1118
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1454
amdgpu_sdma_destroy_inst_ctx(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1480
sdma_v5_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1481
sdma_v5_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1505
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1640
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1903
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
295
ret = amdgpu_sdma_init_microcode(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
854
r = sdma_v5_0_gfx_resume_instance(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
891
sdma_v5_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
932
sdma_v5_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
933
sdma_v5_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1017
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1393
sdma_v5_2_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1394
sdma_v5_2_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1418
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1549
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1705
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1709
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1713
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1860
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1905
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
701
r = sdma_v5_2_gfx_resume_instance(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
738
sdma_v5_2_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
823
sdma_v5_2_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
824
sdma_v5_2_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1023
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1280
adev->sdma.no_user_submission = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1284
adev->sdma.no_user_submission = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1285
adev->sdma.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1289
adev->sdma.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1472
sdma_v6_0_ctxempty_int_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1473
sdma_v6_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1474
sdma_v6_0_set_userq_trap_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1498
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1533
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1716
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
636
r = sdma_v6_0_gfx_resume_instance(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
674
sdma_v6_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
809
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
825
sdma_v6_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1040
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1265
adev->sdma.no_user_submission = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1269
adev->sdma.no_user_submission = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1270
adev->sdma.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1274
adev->sdma.disable_uq = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1428
sdma_v7_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1429
sdma_v7_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1430
sdma_v7_0_set_userq_trap_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1454
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1489
amdgpu_ring_set_preempt_cond_exec(ring, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1649
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
620
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
638
r = sdma_v7_0_gfx_resume_instance(adev, i, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
688
sdma_v7_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
802
return false;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
843
sdma_v7_0_ctx_switch_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
844
sdma_v7_0_enable(adev, false);
sys/dev/pci/drm/amd/amdgpu/si.c
1327
return false;
sys/dev/pci/drm/amd/amdgpu/si.c
1329
return false;
sys/dev/pci/drm/amd/amdgpu/si.c
1332
return false;
sys/dev/pci/drm/amd/amdgpu/si.c
1422
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
sys/dev/pci/drm/amd/amdgpu/si.c
1527
return false;
sys/dev/pci/drm/amd/amdgpu/si.c
2430
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/amd/amdgpu/si.c
2431
bool disable_clkreq = false;
sys/dev/pci/drm/amd/amdgpu/si.c
2557
clk_req_support = false;
sys/dev/pci/drm/amd/amdgpu/si.c
2562
clk_req_support = false;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
291
r = dma_fence_wait_timeout(f, false, timeout);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
511
ring->use_doorbell = false;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
567
return false;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
727
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/si_ih.c
174
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
220
return false;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
59
adev->irq.ih.enabled = false;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
284
16, 1, data, numbytes, false);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
435
16, 1, data, bytes_received, false);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
494
return false;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
502
smu_v11_0_i2c_set_clock_gating(control, false);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
508
res = smu_v11_0_i2c_enable(control, false);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
527
res = smu_v11_0_i2c_enable(control, false);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
565
return false;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
574
if (!amdgpu_dpm_smu_i2c_bus_access(adev, false))
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
577
return false;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
624
return false;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
635
adev->pm.bus_locked = false;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
778
return false;
sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c
38
return false;
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
128
return data ? true : false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
1327
adev->nbio.funcs->enable_doorbell_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1328
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc15.c
378
return false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
513
adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc15.c
530
bool connected_to_cpu = false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
614
return false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
868
return false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
871
return false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
880
return false;
sys/dev/pci/drm/amd/amdgpu/soc21.c
253
return false;
sys/dev/pci/drm/amd/amdgpu/soc21.c
365
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc21.c
474
return false;
sys/dev/pci/drm/amd/amdgpu/soc21.c
483
return false;
sys/dev/pci/drm/amd/amdgpu/soc21.c
903
adev->nbio.funcs->enable_doorbell_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc21.c
904
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc21.c
940
return false;
sys/dev/pci/drm/amd/amdgpu/soc24.c
275
return false;
sys/dev/pci/drm/amd/amdgpu/soc24.c
284
return false;
sys/dev/pci/drm/amd/amdgpu/soc24.c
510
adev->nbio.funcs->enable_doorbell_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/soc24.c
511
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
362
return false;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
398
return false;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
87
adev->irq.ih.enabled = false;
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
106
return false;
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
431
return false;
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
434
return false;
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
95
return false;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
182
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
501
uvd_v3_1_set_dcm(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
754
amdgpu_dpm_enable_uvd(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
247
amdgpu_dpm_enable_uvd(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
464
uvd_v4_2_set_dcm(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
776
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
245
amdgpu_dpm_enable_uvd(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
808
uvd_v5_0_enable_clock_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
883
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1184
return false;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1266
int_handled = false;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1272
int_handled = false;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1470
uvd_v6_0_enable_clock_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1553
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1579
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1608
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
348
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
571
amdgpu_dpm_enable_uvd(adev, false);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1540
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1572
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
355
r = dma_fence_wait_timeout(fence, false, timeout);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
639
amdgpu_dpm_enable_uvd(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
401
vce_v2_0_set_sw_cg(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
403
vce_v2_0_set_dyn_cg(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
471
vce_v2_0_enable_mgcg(adev, true, false);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
511
amdgpu_dpm_enable_vce(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
584
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
585
bool sw_cg = false;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
637
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
232
vce_v3_0_override_vce_clock_gating(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
522
amdgpu_dpm_enable_vce(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
666
return false;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
920
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
944
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
588
amdgpu_dpm_enable_vce(adev, false);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
826
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1906
amdgpu_dpm_enable_vcn(adev, false, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1934
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2060
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2123
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2158
.support_64bit_ptrs = false,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
315
amdgpu_dpm_enable_vcn(adev, false, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1285
amdgpu_dpm_enable_vcn(adev, false, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
300
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1652
amdgpu_dpm_enable_vcn(adev, false, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
479
adev->vcn.inst[j].ring_enc[1].sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
480
adev->vcn.inst[j].ring_enc[2].sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1708
amdgpu_dpm_enable_vcn(adev, false, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1896
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1909
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
336
fw_shared->sw_ring.is_enabled = false;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
383
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
396
ring->sched.ready = false;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1685
amdgpu_dpm_enable_vcn(adev, false, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1813
dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1826
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2045
return false;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2050
return false;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
270
fw_shared->sq.is_enabled = cpu_to_le32(false);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1348
amdgpu_dpm_enable_vcn(adev, false, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1076
amdgpu_dpm_enable_vcn(adev, false, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1670
return false;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1675
return false;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
126
ih->enabled = false;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
269
ret = vega10_ih_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
318
vega10_ih_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
162
ih->enabled = false;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
315
ret = vega20_ih_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
353
ih[i]->overflow = false;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
399
vega20_ih_toggle_interrupts(adev, false);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
582
use_bus_addr = false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1075
ecclk, false, ÷rs);
sys/dev/pci/drm/amd/amdgpu/vi.c
1123
bool bL1SS = false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1183
bClkReqSupport = false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1337
return false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1415
return false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1424
return false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1720
vi_enable_doorbell_aperture(adev, false);
sys/dev/pci/drm/amd/amdgpu/vi.c
642
return false;
sys/dev/pci/drm/amd/amdgpu/vi.c
644
return false;
sys/dev/pci/drm/amd/amdgpu/vi.c
647
return false;
sys/dev/pci/drm/amd/amdgpu/vi.c
739
{mmGB_BACKEND_MAP, false},
sys/dev/pci/drm/amd/amdgpu/vi.c
894
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
sys/dev/pci/drm/amd/amdgpu/vi.c
989
clock, false, ÷rs);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
201
vpe_v6_1_halt(vpe, false);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
304
vpe->ring.sched.ready = false;
sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c
69
return false;
sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c
74
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
1028
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
1144
flags, false);
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
245
q_properties->is_interop = false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
246
q_properties->is_gws = false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2631
p->queues_paused = false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2718
p->queues_paused = false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2795
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2803
false,
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2814
p, NULL, 0, false, NULL, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2837
kfd_dbg_trap_deactivate(p, false, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2841
p, NULL, 0, false, NULL, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2861
p->runtime_info.ttmp_setup = false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2871
false,
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
3252
bool ptrace_attached = false;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
402
kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
1582
bool cache_line_size_missing = false;
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2024
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2159
amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
127
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
190
is_subscribed = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
208
bool signaled_to_debugger_or_runtime = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
213
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
318
q->properties.is_dbg_wa = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
339
kfd_dbg_set_queue_workaround(pqn->q, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
365
false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
419
bool owns_watch_id = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
445
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
484
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
617
kfd_process_set_trap_debug_flag(&pdd->qpd, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
621
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
639
kfd_dbg_set_workaround(target, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
677
kfd_dbg_trap_deactivate(target, false, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
690
target->debug_trap_enabled = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
727
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
735
false,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
818
kfd_dbg_trap_deactivate(target, false, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
873
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
909
amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
935
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
125
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1040
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1124
bool is_patched = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1438
amdgpu_amdkfd_set_compute_idle(node->adev, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1454
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1629
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1634
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1706
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
491
kfd->init_complete = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
755
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
811
false)) {
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
972
kfd_smi_event_update_gpu_reset(node, false, reset_context);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1024
pdd->qpd.mapped_gws_queue = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1026
q->properties.is_gws = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1092
q->properties.is_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1121
q->properties.is_suspended = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1165
q->properties.is_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1223
q->properties.is_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1301
q->properties.is_evicted = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1366
q->properties.is_evicted = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1569
dqm->sched_running = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1641
bool free_bit_found = false, is_xgmi = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1753
dqm->active_runlist = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1783
USE_DEFAULT_GRACE_PERIOD, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1806
dqm->sched_halt = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1897
unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1901
dqm->sched_running = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1953
qpd->is_debug = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2138
q->properties.is_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2272
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2294
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2318
if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) ||
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
238
queue_input.paging = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2422
reset_queues_on_hws_hang(dqm, false))
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2437
dqm->active_runlist = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2473
retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2561
q->properties.is_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2591
-1, false, NULL, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2648
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2781
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2791
qpd->is_debug = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2835
qpd->reset_wavefronts = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2903
(void *)&(mem_obj->cpu_ptr), false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3083
q->properties.is_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3141
USE_DEFAULT_GRACE_PERIOD, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3190
USE_DEFAULT_GRACE_PERIOD, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3576
r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3618
bool r = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
423
qpd->mapped_gws_queue = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
746
set = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
899
qpd->reset_wavefronts = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
94
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
950
bool prev_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
968
KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
120
retval = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
121
retval = false;
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
1135
send_signal = false;
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
415
ev->signaled = false;
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
680
ev->signaled = false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
148
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
169
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
274
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
281
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
291
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
275
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
297
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
326
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
339
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
594
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
100
node->interrupts_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
113
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
128
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c
128
prop.is_interop = false;
sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c
129
prop.is_gws = false;
sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c
193
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c
70
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c
74
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
157
NULL, &next, false, true, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
199
r = dma_fence_wait(mfence, false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c
311
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
370
data, sizeof(struct cik_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
377
data, sizeof(struct cik_sdma_rlc_registers), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
432
data, sizeof(struct v10_compute_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
439
data, sizeof(struct v10_sdma_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
460
data, sizeof(struct v11_compute_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
467
data, sizeof(struct v11_sdma_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
362
data, sizeof(struct v12_compute_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
369
data, sizeof(struct v12_sdma_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
651
bool ret = false;
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
916
data, sizeof(struct v9_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
923
data, sizeof(struct v9_sdma_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
427
data, sizeof(struct vi_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
434
data, sizeof(struct vi_sdma_mqd), false);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c
316
pm->allocated = false;
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c
382
rl_ib_size / sizeof(uint32_t), false);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c
527
pm->allocated = false;
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c
546
pm->ib_buffer_obj->cpu_ptr, pm->ib_size_bytes, false);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
177
use_static = false; /* no static queues under SDMA */
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1059
kfd_smi_event_process(pdd, false);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1088
pdd->runtime_inuse = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1481
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1492
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1495
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1530
process->queues_paused = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1538
process->debug_trap_enabled = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1554
process->xnack_enabled = kfd_process_xnack_mode(process, false);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1634
pdd->qpd.mapped_gws_queue = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1637
pdd->already_dequeued = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1638
pdd->runtime_inuse = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1648
false,
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1909
pdd->dev->dqm->is_hws_hang = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
2186
pdd->process->irq_drain_is_open = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
2193
pdd->process->irq_drain_is_open = false;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
2207
WRITE_ONCE(p->irq_drain_is_open, false);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
748
flags, false);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
925
process = find_process(thread, false);
sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
272
false);
sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
375
false);
sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
601
err = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
972
qp->is_interop = false;
sys/dev/pci/drm/amd/amdkfd/kfd_queue.c
255
err = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdkfd/kfd_queue.c
381
err = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
169
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1127
*new = svm_range_new(svms, last + 1, old_last, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1129
*new = svm_range_new(svms, old_start, start - 1, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1137
svm_range_free(*new, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1339
return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, start,
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1363
prange->mapped_to_gpu = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1388
r = dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1446
r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, true,
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1463
r = amdgpu_vm_update_pdes(adev, vm, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1519
r = dma_fence_wait(fence, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1896
MAX_GPU_INSTANCE, false, true, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2043
new = svm_range_new(old->svms, old->start, old->last, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2047
svm_range_free(new, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2248
svm_range_free(prange, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2832
r = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2936
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2951
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3008
bool write_locked = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3010
bool migration = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3192
r = svm_range_validate_and_map(mm, start, last, prange, gpuidx, false,
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3193
false, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3379
r = amdgpu_bo_reserve(vm->root.bo, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3550
*migrated = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3670
bool update_mapping = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3721
svm_range_free(prange, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
375
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3798
bool get_preferred_loc = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3799
bool get_prefetch_loc = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3800
bool get_granularity = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3801
bool get_accessible = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3802
bool get_flags = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3895
get_preferred_loc = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3906
get_prefetch_loc = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
473
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
494
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
509
dma_fence_wait(f, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
535
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
623
r = amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
707
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
826
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
832
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
841
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
844
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
847
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
852
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
856
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
860
return false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
272
#define KFD_IS_SVM_API_SUPPORTED(dev) false
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1132
is_unique = false;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1696
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1982
firmware_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10199
bool mode_set_reset_required = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10202
bool set_backlight_level = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10228
acrtc->wb_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10448
wb_info->dwb_params.cnv_params.crop_en = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10449
wb_info->dwb_params.stereo_params.stereo_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10575
bool enable_encryption = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10686
bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10857
wait_for_vblank = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11105
bool fs_vid_mode = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11144
new_crtc_state->vrr_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11157
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11177
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1124
*enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11297
new_crtc_state->mode_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11335
new_crtc_state->mode_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11348
high_mode = get_highest_refresh_rate_mode(aconnector, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11510
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11628
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1206
adev->mode_info.audio.pin[i].connected = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12090
bool consider_mode_change = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12091
bool entire_crtc_covered = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12092
bool cursor_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12221
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12229
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12271
bool lock_and_validation_needed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1231
adev->dm.audio_registered = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12329
dm_old_crtc_state->dsc_force_changed == false)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1236
adev->mode_info.audio.enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12363
bool modified = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12444
false,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12458
false,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12783
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12801
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12813
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12822
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12841
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12857
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12863
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12866
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12879
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12967
vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12976
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12985
bool valid_vsdb_found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13033
bool freesync_capable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13052
freesync_capable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13127
amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13128
amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13192
ASSERT(false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13286
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13295
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13313
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1600
offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1642
offload_work->offload_wq->is_handling_link_loss = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1720
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1928
init_data.flags.disable_dmcu = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1947
init_data.flags.gpu_vm_support = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1950
init_data.flags.gpu_vm_support = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1980
init_data.flags.seamless_boot_edp_requested = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2036
adev->dm.dc->debug.force_single_disp_pipe_split = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2041
adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2059
adev->dm.dc->debug.fams2_config.bits.enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2154
dmub_aux_setconfig_callback, false)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2163
dmub_aux_fused_io_callback, false)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2240
adev->dm.idle_workqueue->enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2728
params.backlight_ramping_override = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
302
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3057
&acrtc->base, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3200
dc_allow_idle_optimizations(adev->dm.dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3205
dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
334
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3425
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3528
s3_handle_hdmi_cec(ddev, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3531
s3_handle_mst(ddev, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3570
aconnector->fake_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3584
bool init = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3599
aconnector->dc_link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3689
caps->aux_support = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3700
caps->aux_support = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
374
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3884
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3886
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3889
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3893
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3922
bool fake_reconnect = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3923
bool reallow_idle = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3924
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3930
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3980
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3981
bool debounce_required = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3997
aconnector->fake_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3999
aconnector->timing_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4103
bool result = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4107
bool link_loss = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4108
bool has_left_work = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4139
bool skip = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4160
bool skip = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4187
aconnector->fake_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4198
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4207
aconnector->fake_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4931
caps->caps_valid = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5080
bool rc, reallow_idle = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5114
dc_allow_idle_optimizations(dm->dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5370
bool psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5371
bool replay_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5498
psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5549
link->psr_settings.psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5584
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5598
psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6275
*dirty_regions_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6304
false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6337
new_plane_state->crtc_h, &i, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6344
old_plane_state->crtc_h, &i, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6352
clips->y2 - clips->y1, &i, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6358
new_plane_state->crtc_h, &i, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6599
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6606
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
672
acrtc->wb_pending = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6986
high_mode = get_highest_refresh_rate_mode(aconnector, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6988
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7002
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7013
dsc_caps->is_dsc_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7184
bool native_mode_found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7185
bool recalculate_timing = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7262
freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7549
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7552
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7562
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7635
state->underscan_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7859
dc_plane_state->is_tiling_rotated = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7977
aconnector->force_yuv422_output = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7978
aconnector->force_yuv420_output = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
807
ASSERT(false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8098
sizeof(out->sb), false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
815
ASSERT(false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8237
bool is_y420 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8359
dm_conn_state->pbn, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8501
bool mode_existed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8604
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8750
aconnector->base.interlace_allowed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8751
aconnector->base.doublescan_allowed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8752
aconnector->base.stereo_allowed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8756
aconnector->pack_sdp_v1_3 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8783
link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8791
link->link_enc->features.dp_ycbcr420_supported ? true : false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8985
i2c = create_i2c(link->ddc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9213
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9265
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9287
dm_con_state->update_hdcp = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9304
dm_con_state->update_hdcp = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9319
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9323
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9333
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9343
acrtc->enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
936
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9377
bool pack_sdp_v1_3 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9542
WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9691
acrtc_attach->dm_irq_params.allow_sr_entry = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9715
bool cursor_update = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9716
bool pflip_present = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9717
bool dirty_rects_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9718
bool updated_planes_and_streams = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1021
ret = amdgpu_dm_check_crtc_color_mgmt(crtc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1041
stream->csc_color_matrix.enable_adjustment = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1044
stream->gamut_remap_matrix.enable_remap = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1045
stream->csc_color_matrix.enable_adjustment = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1124
NULL, false))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1174
&dc_plane_state->in_transfer_func, NULL, false))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1200
ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1216
ret = amdgpu_dm_atomic_blend_lut(blend_lut, false,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1319
dc_plane_state->input_csc_color_matrix.enable_adjustment = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1322
dc_plane_state->gamut_remap_matrix.enable_remap = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1323
dc_plane_state->input_csc_color_matrix.enable_adjustment = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
366
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
373
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
539
__drm_lut_to_dc_gamma(lut, gamma, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
630
__drm_lut_to_dc_gamma(lut, gamma, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
741
lut->lut_3d.use_tetrahedral_9 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
939
crtc->cm_has_degamma = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
940
crtc->cm_is_degamma_srgb = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
152
bool swap = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
199
dm->secure_display_ctx.phy_id_mapping[idx].is_mst = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
220
bool found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
228
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
234
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
246
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
276
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
289
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
313
acrtc->dm_irq_params.window_param[i].enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
314
acrtc->dm_irq_params.window_param[i].update_win = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
317
acrtc->dm_irq_params.crc_window_activated = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
460
phy_id, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
463
phy_id, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
471
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
556
bool enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
557
bool enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
778
bool reset_crc_frame_count[MAX_CRC_WINDOW_NUM] = {false};
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
783
bool forward_roi_change = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
784
bool notify_ta = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
835
crtc_ctx->crc_info.crc[i].crc_ready = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
841
crtc_ctx->crc_info.crc[i].crc_ready = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
859
&crc_window, true, true, i, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
863
acrtc->dm_irq_params.window_param[i].update_win = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
871
crtc_ctx->crc_info.crc[i].crc_ready = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
883
&crc_window, true, true, i, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
910
all_crc_ready = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
98
dm->secure_display_ctx.phy_mapping_updated = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
134
bool is_crc_window_active = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
147
amdgpu_dm_psr_disable(vblank_work->stream, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
187
is_headless = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
209
dc_allow_idle_optimizations(idle_work->dm->dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
227
idle_work->dm->idle_workqueue->running = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
239
idle_work->enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
240
idle_work->running = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
260
dc_allow_idle_optimizations(dm->dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
337
rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
422
amdgpu_dm_crtc_set_vblank(crtc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
762
acrtc->base.enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1007
bool sink_support_replay = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1008
bool driver_support_replay = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1369
bool try_again = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1370
bool is_fec_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1371
bool is_dsc_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1376
try_again = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1447
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
299
valid_input = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3133
link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
314
valid_input = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
322
dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3240
aconnector->disallow_edp_enter_psr = val ? true : false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
331
prefer_link_settings.use_link_rate_set = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
336
dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
345
bool is_end_device = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3471
valid_input = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3476
valid_input = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3481
prefer_link_settings.use_link_rate_set = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3483
dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3499
NULL, link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3582
acrtc->dm_irq_params.window_param[0].update_win = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3619
acrtc->dm_irq_params.window_param[0].update_win = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3655
acrtc->dm_irq_params.window_param[0].update_win = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3691
acrtc->dm_irq_params.window_param[0].update_win = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3919
dc_link_dp_receiver_power_ctrl(link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3920
drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4020
unsigned int mall_in_use = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4021
unsigned int subvp_in_use = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4129
adev->dm.dc->debug.skip_detection_link_training = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
433
valid_input = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
448
valid_input = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
456
dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
465
prefer_link_settings.use_link_rate_set = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
761
bool disable_hpd = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
762
bool valid_test_pattern = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
821
valid_test_pattern = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
503
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
520
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
536
bool link_is_hdcp14 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
58
{false, address, size, data} };
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
663
link_lock(work, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
701
link_lock(work, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1029
connector->edid_corrupt = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1138
panel_config->dsc.disable_dsc_edp = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1242
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1329
dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1336
false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1346
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1374
bool ret_val = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1411
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1417
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
285
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
386
set_flag, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
391
clr_flag, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
420
amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
521
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
536
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
553
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
560
drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
564
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
578
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
594
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
613
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
619
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
655
bool success = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
718
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
738
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
745
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
752
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
760
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
767
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
772
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
845
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
912
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
140
bool handler_removed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
175
if (handler_removed == false) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
246
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
252
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
258
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
269
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
274
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
313
if (false == validate_irq_registration_params(int_params, ih))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
378
if (false == validate_irq_unregistration_params(irq_source, ih))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
498
dc_interrupt_set(adev->dm.dc, src, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
571
bool work_queued = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
730
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
899
if (!dc_interrupt_set(adev->dm.dc, i, false))
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
989
false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
996
false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1012
bpp_increased[i] = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1115
tried[i] = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1155
vars[next_index].dsc_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1199
bool debugfs_overwrite = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1282
vars[i + k].dsc_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1312
vars[i + k].dsc_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1356
bool is_dsc_need_re_compute = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1438
is_dsc_need_re_compute = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1496
computed_streams[i] = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1565
computed_streams[i] = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1628
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1632
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1641
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1647
ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1812
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1841
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1848
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
249
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
265
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
296
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
299
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
308
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
319
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
323
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
342
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
349
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
378
MST_REMOTE_EDID, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
575
false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
720
bool new_irq_handled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
806
new_irq_handled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
844
drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1034
r = amdgpu_bo_reserve(rbo, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
104
*per_pixel_alpha = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
106
*global_alpha = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
133
*pre_multiplied_alpha = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1444
dc_plane_force_dcc_and_tiling_disable(dc_plane_state, fb->modifier ? true : false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1534
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1552
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1565
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1570
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1575
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1580
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1677
bool replaced = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1914
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
374
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
394
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
417
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
425
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
440
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
444
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
457
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
104
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
107
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
124
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
187
dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
201
bool psr_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
205
return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
217
return dc_set_psr_allow_active(dm->dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
230
bool allow_active = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
264
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
274
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
38
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
41
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
44
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
48
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
52
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
55
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
58
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
69
link->psr_settings.psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
74
link->psr_settings.psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
80
link->psr_settings.psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c
162
dm->aux_hpd_discon_quirk = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c
163
dm->edp0_on_dp1_quirk = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c
38
.aux_hpd_discon = false,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c
39
.support_edp0_on_dp1 = false
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
100
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
126
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
131
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
134
pr_config->replay_smu_opt_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
137
pr_config->replay_timing_sync_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
159
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
167
link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
171
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
182
bool replay_active = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
186
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
192
link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
196
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
208
return dc_set_replay_allow_active(dm->dc, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
49
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
52
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
56
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
59
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
63
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
68
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
90
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
93
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
96
return false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
157
r = amdgpu_bo_reserve(rbo, false);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
49
bool found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/dc_fpu.c
118
TRACE_DCN_FPU(false, function_name, line, depth);
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
44
*negative = false;
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
54
*negative = false;
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
45
return false;
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
49
return false;
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
59
return false;
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
68
return false;
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
79
return false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
171
d0_underlay_enable = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
175
d1_underlay_enable = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2105
dceip->large_cursor = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2107
dceip->dmif_pipe_en_fbc_chunk_tracker = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2114
dceip->display_write_back_supported = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2115
dceip->argb_compression_support = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2141
dceip->graphics_lb_nodownscaling_multi_line_prefetching = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2221
dceip->large_cursor = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2223
dceip->dmif_pipe_en_fbc_chunk_tracker = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2230
dceip->display_write_back_supported = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2337
dceip->large_cursor = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2339
dceip->dmif_pipe_en_fbc_chunk_tracker = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2346
dceip->display_write_back_supported = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2442
vbios->scatter_gather_enable = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2453
dceip->large_cursor = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2455
dceip->dmif_pipe_en_fbc_chunk_tracker = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2566
dceip->large_cursor = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2568
dceip->dmif_pipe_en_fbc_chunk_tracker = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2575
dceip->display_write_back_supported = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2602
dceip->graphics_lb_nodownscaling_multi_line_prefetching = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2668
vbios->scatter_gather_enable = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2679
dceip->large_cursor = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2712
dceip->underlay_downscale_prefetch_enabled = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2775
return false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2780
return false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2820
data->fbc_en[num_displays + 4] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2821
data->lpt_en[num_displays + 4] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2872
data->interlace_mode[num_displays + 4] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2877
data->fbc_en[num_displays * 2 + j] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2878
data->lpt_en[num_displays * 2 + j] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2919
data->fbc_en[num_displays + 4] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2920
data->lpt_en[num_displays + 4] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3001
data->interlace_mode[num_displays + 4] = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
302
fbc_enabled = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3023
return false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3028
return false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
303
lpt_enabled = false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3051
return false;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3058
calcs_output->all_displays_in_sync = false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
167
return false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
213
return false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
313
return false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
40
return false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
45
return false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
66
return false;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
72
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1062
info->type.STEP_AND_DELAY_INFO = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1929
rc = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1935
rc = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1939
rc = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1950
if (false == dal_graphics_object_id_is_valid(id1)) {
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1953
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1956
if (false == dal_graphics_object_id_is_valid(id2)) {
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1959
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1966
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2872
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2875
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2888
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2893
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2897
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2904
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2909
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2915
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2927
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2934
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
713
ss_info->type.STEP_AND_DELAY_INFO = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1830
info->oem_i2c_present = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1917
info->oem_i2c_present = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
2059
info->oem_i2c_present = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
2089
info->oem_i2c_present = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3705
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3708
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3722
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3727
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3731
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3738
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3743
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3750
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3762
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3772
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3777
return false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
466
bool find_valid = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
511
if (find_valid == false)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
515
info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
828
ss_info->type.STEP_AND_DELAY_INFO = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
923
ss_info->type.STEP_AND_DELAY_INFO = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
994
ss_info->type.STEP_AND_DELAY_INFO = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1011
bp_params->signal_type, false));
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1076
bp_params->signal_type, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1165
bp_params->signal_type, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1243
clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1534
bp_params->signal_type, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1578
bp_params->signal_type, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2218
bool is_input_signal_dp = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2272
cntl->signal, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2294
cntl->signal, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
405
frev, crev) == false)
sys/dev/pci/drm/amd/display/dc/bios/command_table2.c
382
bool is_phy_transition_interlock_allowed = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table2.c
521
bp_params->signal_type, false);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
112
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
218
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
240
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
358
bool result = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
69
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
81
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
104
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
136
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
203
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
226
return false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
92
return false;
sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
141
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
144
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
192
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
145
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
148
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
196
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
220
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
246
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
143
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
146
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
194
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
218
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
244
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
100
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
97
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c
100
result = false;
sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c
97
result = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
109
bool allow_active = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
115
dc->link_srv->edp_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
116
dc->link_srv->edp_set_replay_allow_active(edp_link, &allow_active, false, false, NULL);
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
136
&clk_mgr->psr_allow_active_cache, false, false, NULL);
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
138
&clk_mgr->psr_allow_active_cache, false, false, NULL);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
458
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
208
context->bw_ctx.bw.dce.nbp_state_change_enable == false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
210
context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
212
context->bw_ctx.bw.dce.cpup_state_change_enable == false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
110
dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
183
dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
62
clk_mgr_dce->xgmi_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
154
request_dpp_div = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
196
bool send_request_to_increase = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
197
bool send_request_to_lower = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
200
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
330
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
177
false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
203
dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
225
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
226
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
227
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
228
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
230
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
321
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
399
clk_mgr->clks.dtbclk_en = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
473
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
475
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
477
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
479
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
481
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
483
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
485
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
487
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
551
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
586
clk_mgr->dfs_bypass_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
157
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
198
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
91
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
92
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
93
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
94
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
139
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
140
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
141
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
532
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
534
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
536
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
538
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
58
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
682
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
724
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
117
clk_mgr->smu_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
201
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
202
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
203
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
204
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
205
bool update_pstate_unsupported_clk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
207
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
208
bool update_uclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
301
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
440
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
442
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
444
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
446
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
448
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
450
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
539
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
558
clk_mgr->dfs_bypass_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
560
clk_mgr->smu_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
108
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
123
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
138
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
157
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
176
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
105
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
103
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
104
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
105
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
469
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
471
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
473
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
475
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
623
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
67
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
696
clk_mgr->base.ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
143
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
144
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
145
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
163
dcn31_smu_set_dtbclk(clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
184
dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
229
dcn31_disable_otg_wa(clk_mgr_base, context, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
314
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
316
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
318
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
320
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
322
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
324
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
624
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
692
clk_mgr->base.ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
81
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
1031
if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
178
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
282
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
283
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
284
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
304
dcn314_smu_set_dtbclk(clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
324
dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
378
dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
450
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
452
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
454
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
456
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
458
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
460
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
877
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
934
clk_mgr->base.ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
134
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
135
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
136
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
149
dcn315_smu_set_dtbclk(clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
216
dcn315_disable_otg_wa(clk_mgr_base, context, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
576
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
62
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
622
clk_mgr->base.ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
96
ret = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
144
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
145
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
146
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
158
dcn316_smu_set_dtbclk(clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
224
dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
556
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
597
clk_mgr->base.ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
74
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1057
clk_mgr->dpm_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1073
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1075
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1077
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1079
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1081
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1083
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1085
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1169
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1205
clk_mgr->dfs_bypass_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1207
clk_mgr->smu_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
178
clk_mgr->smu_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
179
clk_mgr->dpm_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
336
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
396
false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
445
dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
492
bool is_native_scaling = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
629
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
630
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
631
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
632
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
634
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
635
bool update_uclk = false, update_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
732
dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
811
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
158
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
206
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
252
hard_min_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
284
bool hard_min_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
96
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1183
bw_params->wm_table.entries[i].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1219
return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1387
clk_mgr->base.ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1512
if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1529
bool ips_support = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1534
ctx->dc->debug.ignore_pg = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1535
ctx->dc->debug.disable_dpp_power_gate = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1536
ctx->dc->debug.disable_hubp_power_gate = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1537
ctx->dc->debug.disable_dsc_power_gate = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
162
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
208
bool stream_changed_otg_dig_on = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
209
bool has_active_hpo = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
304
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
386
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
387
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
388
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
414
dcn35_smu_set_dtbclk(clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
428
dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
494
dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
577
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
579
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
581
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
583
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
585
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
587
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
101
ppclk_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1020
block_sequence[num_steps].params.update_pstate_support_params.support = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1088
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1089
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1090
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1091
bool dppclk_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
112
ppclk_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1157
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
122
bool ppclk_idle_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
136
ppclk_idle_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1412
clk_mgr->dpm_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1432
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1434
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1436
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1438
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1440
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1442
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1444
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
146
bool is_df_throttle_opt_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1570
clk_mgr->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1598
clk_mgr->dfs_bypass_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1600
clk_mgr->smu_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
197
clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
209
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
213
clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
231
clk_mgr->smu_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
232
clk_mgr->dpm_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
397
bool is_native_scaling = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
578
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
77
bool ppclk_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
774
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
775
bool update_active_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
776
bool update_active_uclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
777
bool update_idle_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
778
bool update_idle_uclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
779
bool update_subvp_prefetch_dramclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
780
bool update_subvp_prefetch_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
142
TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
143
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
158
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
177
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
196
return false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
277
bool hardmin_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
304
bool hard_min_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
80
TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
81
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1016
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1027
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
1028
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1035
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1119
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
1135
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
1187
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1198
stream->writeback_info[i].wb_enabled = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1327
bool pipe_split_change = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1339
should_disable = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1391
apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
1400
dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
1473
pipe->stream->dpms_off = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1552
edp_link->edp_sink_present = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1699
status->timing_sync_info.master = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1765
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1782
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1787
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1793
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1800
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1817
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1822
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1827
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1834
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1839
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1844
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1849
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1854
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1859
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1864
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1869
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1874
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1879
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1884
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1889
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1894
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1899
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1905
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1930
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1940
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1945
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1953
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1958
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1963
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1970
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1975
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1980
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2118
bool subvp_prev_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
212
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2121
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2146
dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2165
dc->hwss.update_dsc_pg(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2180
apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2224
dc->hwss.interdependent_update_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2231
dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2233
dc->hwss.fams2_global_control_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2247
apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
2307
context->streams[i]->mode_changed = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2346
bool handle_exit_odm2to1 = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2472
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2473
bool found_pipe_idx = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2514
pipe->plane_state->status.is_flip_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2519
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2579
dc->optimized_required = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2592
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2597
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2607
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2627
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2645
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2909
bool has_flip_immediate_plane = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
325
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3292
update->crtc_timing_adjust->timing_adjust_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3421
stream->apply_seamless_boot_optimization = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3468
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
3470
return false; /* Cannot commit surface to stream that is not committed */
sys/dev/pci/drm/amd/display/dc/core/dc.c
3502
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3523
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3583
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
360
res = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3722
should_program_abm = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3750
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3952
bool should_offload_fams2_flip = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3968
should_offload_fams2_flip = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3974
should_offload_fams2_flip = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4012
pipe_ctx->plane_state->triplebuffer_flips = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4071
bool subvp_prev_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4072
bool subvp_curr_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4080
subvp_prev_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4103
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4109
dc->hwss.update_dsc_pg(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
417
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
420
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4214
dc->hwss.interdependent_update_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4216
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4228
dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4232
dc->hwss.fams2_global_control_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4264
pipe_ctx->plane_state->triplebuffer_flips = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4274
plane_state->flip_immediate = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4275
plane_state->triplebuffer_flips = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
435
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4404
dc->hwss.interdependent_update_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4406
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4430
false,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4469
dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4471
dc->hwss.fams2_global_control_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4474
dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4476
dc->hwss.fams2_global_control_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4531
bool force_minimal_pipe_splitting = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4532
bool subvp_active = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4535
*is_plane_addition = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4614
dc->debug.enable_single_display_2to1_odm_policy = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4658
stream_status->plane_states[j]->flip_immediate = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
467
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4724
pipe_ctx->plane_state->force_full_update = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4750
bool success = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4780
bool success = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
481
stream->adjust.timing_adjust_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
485
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4894
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4895
bool odm_in_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
495
stream->adjust.timing_adjust_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4959
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
499
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5015
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5035
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5113
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5157
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5167
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5173
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
519
bool status = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5302
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5336
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5373
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5420
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5495
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5527
if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
sys/dev/pci/drm/amd/display/dc/core/dc.c
5528
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5530
allow_active = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5531
if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
sys/dev/pci/drm/amd/display/dc/core/dc.c
5532
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5558
false, false, NULL))
sys/dev/pci/drm/amd/display/dc/core/dc.c
5559
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5561
allow_active = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5563
true, false, NULL))
sys/dev/pci/drm/amd/display/dc/core/dc.c
5564
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5637
dc_allow_idle_optimizations_internal(dc, false, caller_name);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5643
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5646
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5649
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5658
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5708
dc->hwss.disable_pixel_data(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5711
hubp->funcs->set_blank_regs(hubp, false);
sys/dev/pci/drm/amd/display/dc/core/dc.c
5780
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5813
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
599
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5998
is_cmd_complete = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
614
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6189
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6201
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6212
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6220
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6262
if (edp_link->skip_implict_edp_power_control == false)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6326
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6331
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6337
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6349
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6361
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
665
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
676
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
711
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
753
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
787
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
794
return false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
864
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
883
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
996
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1008
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
119
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1201
pipe->plane_state->status.is_flip_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1250
dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
135
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
146
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
157
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
167
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
178
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
188
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
305
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
387
bool is_sdr = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
659
enable_subvp = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
700
stream->adjust.timing_adjust_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
884
block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
891
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
899
block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
105
state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
189
bool is_avail = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
214
bool are_equal = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
254
state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
304
ASSERT(state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid == false);
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
34
bool is_dig_stream = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
452
bool is_mappable = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
611
is_avail = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
621
bool is_valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
645
valid_entries = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
653
valid_stream_ptrs = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
678
valid_uniqueness = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
682
valid_uniqueness = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
697
valid_avail = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
709
valid_streams = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
717
if (is_valid == false) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
170
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
200
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
75
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1449
bool res = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1460
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1694
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1948
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2141
bool two_pixel_alignment_required = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2178
int odm_segment_offset = resource_get_odm_slice_dst_width(otg_master, false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2259
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2282
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2744
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2799
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2865
false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2871
false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2884
false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2930
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2984
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2991
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3125
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3131
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3146
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3202
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3206
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3264
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3269
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3324
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3329
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3353
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3432
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3435
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3438
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3441
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3458
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3461
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3464
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3468
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3483
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3488
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3493
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3544
if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3553
if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3558
if (res_ctx->is_audio_acquired[i] == false) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
357
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
379
aud_support->hdmi_audio_native = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
380
aud_support->hdmi_audio_on_dongle = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3870
bool acquired = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3884
stream->apply_seamless_boot_optimization = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3989
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4011
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4028
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4046
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4051
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4088
bool found = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4107
found = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4124
found = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4152
found = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4249
dc_state_set_stream_subvp_cursor_limit(context->streams[i], context, false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
430
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4739
sdp_line_num->adaptive_sync_line_num_valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4792
info->avi.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4793
info->gamut.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4794
info->vendor.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4795
info->spd.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4796
info->hdrsmd.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4797
info->vsc.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4798
info->hfvsif.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4799
info->vtem.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4800
info->adaptive_sync.valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
481
dc->caps.dynamic_audio = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4884
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4908
if (false == pipe_ctx_old->stream->link->link_state_valid &&
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4909
false == pipe_ctx_old->stream->dpms_off)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
491
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4925
bool need_reprogram = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4936
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5141
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5243
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5249
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5403
bool divisible = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5450
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5478
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5516
false);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5619
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
571
false == stream1->has_non_synchronizable_pclk &&
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
572
false == stream2->has_non_synchronizable_pclk &&
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
578
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
581
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
598
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
606
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
609
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
613
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
617
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
621
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
625
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
628
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
633
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
636
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
639
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
648
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
652
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
663
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
666
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
672
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
676
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
680
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
684
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
761
*orthogonal_rotation = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
762
*flip_vert_scan_dir = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
763
*flip_horz_scan_dir = false;
sys/dev/pci/drm/amd/display/dc/core/dc_sink.c
40
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_sink.c
84
if (false == dc_sink_construct(sink, init_params))
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
100
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1004
bool limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1033
bool limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1049
bool can_clear_limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1076
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
109
bool res = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
142
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
472
bool added = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
51
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
552
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
567
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
60
bool res = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
609
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
619
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
636
result = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
811
phantom_stream_status->mall_stream_config.subvp_limit_cursor_size = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
812
phantom_stream_status->mall_stream_config.cursor_size_limit_subvp = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
888
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
898
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
921
bool removed_phantom = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
93
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
930
dc_state_rem_all_phantom_planes_for_stream(dc, phantom_stream, state, false);
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
977
bool is_fams2_in_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1166
false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1179
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1213
return dc_stream_get_max_flickerless_instant_vtotal_delta(stream, is_gaming, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1218
bool is_limit_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1228
bool can_clear_limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
176
if (dc_stream_construct(stream, sink) == false)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
261
dc->hwss.cursor_lock(dc, pipe_to_program, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
263
dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
281
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
285
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
290
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
303
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
317
bool result = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
320
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
335
bool reset_idle_optimizations = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
338
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
346
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
359
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
396
dc->hwss.cursor_lock(dc, pipe_to_program, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
405
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
410
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
424
bool reset_idle_optimizations = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
428
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
440
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
472
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
479
bool isDrc = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
485
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
490
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
495
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
503
dwb->dwb_is_drc = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
530
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
557
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
562
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
567
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
593
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
598
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
603
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
611
stream->writeback_info[i].wb_enabled = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
626
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
673
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
707
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
712
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
744
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
770
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
774
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
783
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
787
return false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
916
dc_stream_get_3dlut_for_stream(dc, stream, false);
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
919
rmcm_3dlut->isInUse = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
931
dc->res_pool->rmcm_3dlut[i].isInUse = false;
sys/dev/pci/drm/amd/display/dc/core/dc_surface.c
141
pipe_ctx->plane_state->status.is_flip_pending = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1012
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1023
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1199
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1388
dc_dmub_srv->needs_idle_wake = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1451
dc_dmub_srv_notify_idle(dc, false);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
148
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1525
bool reallow_idle = false, should_detect = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1528
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1538
dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1586
dc_dmub_srv->idle_allowed = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1612
bool result = false, reallow_idle = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1615
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1621
dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1652
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1659
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1672
bool result = false, reallow_idle = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1675
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1678
dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
174
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
190
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1955
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1980
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
208
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
223
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
233
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
243
bool res = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
267
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
286
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
306
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
319
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
327
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
337
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
351
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
359
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
449
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
603
pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
81
return false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
947
return false;
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c
47
return false;
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c
60
return false;
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c
79
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
103
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
105
const bool over_aux = false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
114
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
132
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
141
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
22
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
25
loc->is_aux = false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
47
return false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
88
return false;
sys/dev/pci/drm/amd/display/dc/dc_helper.c
156
return false;
sys/dev/pci/drm/amd/display/dc/dc_helper.c
184
offload->should_burst_write = false;
sys/dev/pci/drm/amd/display/dc/dc_helper.c
496
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dc_helper.c
654
offload->gather_in_progress = false;
sys/dev/pci/drm/amd/display/dc/dc_helper.c
655
offload->should_burst_write = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
117
spl_in->basic_in.num_h_slices_recout_width_align.use_recout_width_aligned = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
145
spl_in->disable_easf = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
147
spl_in->prefer_easf = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
154
spl_in->adaptive_sharpness.enable = false;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
176
spl_in->adaptive_sharpness.enable = false;
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
60
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
91
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
67
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
675
dccg31_set_symclk32_le_root_clock_gating(dccg, 0, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
676
dccg31_set_symclk32_le_root_clock_gating(dccg, 1, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
686
dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
687
dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
688
dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
689
dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
690
dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
311
PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1015
dccg35_set_physymclk_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1037
dccg35_set_dppclk_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1074
dccg35_set_dsc_clk_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1082
dccg35_set_dtbclk_p_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1104
dccg35_set_dpstreamclk_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1165
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1168
dccg35_set_dppclk_rcg(dccg, dpp_inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1176
dcn35_set_dppclk_enable(dccg, dpp_inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1671
dccg35_set_dppclk_rcg(dccg, dpp_inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1769
dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1783
dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2164
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
921
dccg35_set_symclk_fe_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
938
dccg35_set_symclk_be_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
968
dccg35_set_symclk32_se_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
985
dccg35_set_symclk32_le_rcg(dccg, inst, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
596
bool enable = false;
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
723
dccg401_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
724
dccg401_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
725
dccg401_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
726
dccg401_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
90
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
99
dcn401_set_dppclk_enable(dccg, dpp_inst, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
203
if (abm->dmcu_is_running == false)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
222
if (abm->dmcu_is_running == false)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
273
base->dmcu_is_running = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
63
if (abm->dmcu_is_running == false)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
131
bool limit_freq_to_48_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
132
bool limit_freq_to_88_2_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
133
bool limit_freq_to_96_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
134
bool limit_freq_to_174_4_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
635
set_high_bit_rate_capable(audio, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
678
bool is_ac3_supported = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
93
bool found = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
118
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
344
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
393
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
405
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
411
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
416
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
43
#define IS_DC_I2CAUX_LOGGING_ENABLED() (false)
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
702
bool retry_on_defer = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
721
payload_reply = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
738
(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
767
(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
806
payload->write = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
969
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
327
dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
475
clk_mgr_dce->xgmi_enabled = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
621
context->bw_ctx.bw.dce.nbp_state_change_enable == false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
623
context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
625
context->bw_ctx.bw.dce.cpup_state_change_enable == false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
832
clk_mgr_dce->ss_on_dprefclk = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1055
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1110
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1157
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1227
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1510
if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1600
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1603
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1641
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1646
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1690
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1745
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
175
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1758
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1765
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1787
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1788
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
248
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
290
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
461
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
644
false);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
662
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
664
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
666
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
668
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
753
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
755
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
894
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
907
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
954
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
290
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
383
bool status = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
409
status = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
443
(config->disable_fractional_pwm == false) ? 1 : 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
446
status = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
454
status = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
468
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
484
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
614
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
762
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
774
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
797
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
825
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
828
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
865
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
887
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
894
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
903
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
913
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
919
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
925
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
40
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
46
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
49
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
64
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
69
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
82
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
135
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
139
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
150
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
153
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
165
bool last_transaction = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
170
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
225
DC_I2C_DATA_RW, false,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
232
DC_I2C_DATA_RW, false,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
304
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
313
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
322
REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
339
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
572
bool result = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
581
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
608
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
648
result = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
655
pool->i2c_hw_buffer_in_use = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
116
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
118
write_bit_to_ddc(ddc_handle, SCL, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
137
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
145
write_bit_to_ddc(ddc_handle, SCL, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
171
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
176
write_bit_to_ddc(ddc_handle, SCL, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
200
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
202
write_bit_to_ddc(ddc_handle, SCL, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
223
write_bit_to_ddc(ddc_handle, SCL, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
227
write_bit_to_ddc(ddc_handle, SDA, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
234
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
247
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
260
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
264
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
282
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
287
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
29
#define SCL false
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
326
write_bit_to_ddc(ddc_handle, SDA, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
330
write_bit_to_ddc(ddc_handle, SCL, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
337
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
364
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
421
result = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
432
result = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
462
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
486
result = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
93
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c
134
REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c
64
REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1038
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1421
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1477
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1670
LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1790
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
197
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
284
set_link_training_complete(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
288
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
327
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
335
disable_prbs_symbols(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
350
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
355
disable_prbs_symbols(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
371
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
426
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
460
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
479
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
512
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
537
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
565
enable_phy_bypass_mode(enc110, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
592
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
731
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
738
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
740
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
743
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
753
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
756
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
771
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
774
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
776
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
780
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
785
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
790
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
793
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
802
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
888
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
950
is_valid = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
969
cntl.coherent = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
129
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
853
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1465
dce110_se_enable_audio_clock(enc, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1482
dce110_se_enable_audio_clock(enc, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
661
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
685
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1188
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1199
scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1200
scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1213
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1223
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
128
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1314
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1342
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1377
if (default_adjust->force_hw_default == false) {
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
164
return false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
417
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
811
spatial_dither_enable = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
871
spatial_dither_enable = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
117
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
142
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
160
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
177
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
211
base->dmcu_is_running = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
69
dc_allow_idle_optimizations(abm->ctx->dc, false);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
76
dc_allow_idle_optimizations(abm->ctx->dc, false);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
83
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
59
uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;
sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
68
return false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
87
return false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
146
return false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
165
return false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
316
return false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
320
return false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
141
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
253
compressor->is_enabled = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
255
wait_for_fbc_state_changed(cp110, false);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
290
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
431
compressor->base.options.bits.DUMMY_BACKEND = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
439
compressor->base.options.bits.CLK_GATING_DISABLED = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
454
compressor->base.is_enabled = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
483
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
570
const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
389
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
409
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
424
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
444
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
679
if (default_adjust->force_hw_default == false) {
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
505
power_on_lut(xfm, true, false, true);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
514
power_on_lut(xfm, false, false, true);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1126
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1133
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1137
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1146
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1153
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1156
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1164
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1404
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1982
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2082
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2126
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2248
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2268
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2292
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
238
result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
185
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
617
return false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
161
bool is_scaling_needed = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
526
bool is_scaling_required = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
527
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
280
return false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
428
compressor->is_enabled = false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
435
wait_for_fbc_state_changed(cp110, false);
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
464
return false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
798
compressor->base.options.bits.DUMMY_BACKEND = false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
803
compressor->base.options.bits.LPT_SUPPORT = false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
805
compressor->base.options.bits.CLK_GATING_DISABLED = false;
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
820
compressor->base.is_enabled = false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1070
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1101
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1168
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
117
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1186
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1210
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
123
return false;
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
728
return false;
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
198
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
162
fmt.sign = false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
170
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
175
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
180
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
186
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
191
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
196
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
202
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
207
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
212
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
216
fmt.sign = false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
221
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
226
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
231
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
245
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
250
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
255
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
262
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
267
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
272
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
285
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
291
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
297
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
303
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
309
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
315
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
349
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
403
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
554
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
590
return false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
680
hw_points, false);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
55
caps->caps.support_ogam = false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
57
caps->caps.support_ocsc = false;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
60
return false;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
108
return false;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
167
return false;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
61
caps->caps.support_ogam = false;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
62
caps->caps.support_wbscl = false;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
63
caps->caps.support_ocsc = false;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
68
return false;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
181
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
67
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
75
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
76
mpcc->shared_bottom = false;
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
176
cfg->load_sram_fw = false;
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
199
return false;
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
216
return false;
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
229
return false;
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
416
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
126
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
184
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
318
fmt.sign = false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
326
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
331
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
336
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
342
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
347
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
352
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
358
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
363
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
368
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
382
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
387
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
392
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
397
fmt.sign = false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
402
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
407
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
412
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
418
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
423
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
428
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
440
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
446
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
452
return false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
471
ret = false;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
100
REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c
61
if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c
71
if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
129
return false;
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
139
return false;
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
189
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
47
return false;
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
56
if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
70
if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false &&
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1201
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1455
LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
168
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
217
set_link_training_complete(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
221
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
257
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
265
disable_prbs_symbols(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
280
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
285
disable_prbs_symbols(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
301
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
357
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
392
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
416
enable_phy_bypass_mode(enc10, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
442
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
583
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
590
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
592
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
595
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
605
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
608
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
626
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
629
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
632
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
634
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
638
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
643
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
648
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
651
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
661
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
752
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
821
is_valid = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
840
cntl.coherent = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
910
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1456
enc1_se_enable_audio_clock(enc, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1476
enc1_se_enable_audio_clock(enc, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1521
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
612
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
218
cfg->load_sram_fw = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
239
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
289
bool is_usb_c_alt_mode = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
475
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
515
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
175
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
542
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
164
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
129
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
364
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
600
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
608
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
119
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
350
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
74
enc314_reset_fifo(enc, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
166
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
176
return false;
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
307
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
298
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
416
enc32_reset_fifo(enc, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
77
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
161
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
112
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
240
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
262
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
330
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
420
enc35_reset_fifo(enc, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
438
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
65
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
149
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
292
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
323
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
426
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
77
cntl.enable_dp_audio = false;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1312
return false;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
305
input->src.is_hsplit = false;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
640
bool updated = false;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
902
v->underscan_output[input_idx] = false; /* taken care of in recout already*/
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
903
v->interlace_output[input_idx] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1054
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1192
context->res_ctx.pipe_ctx[i].unbounded_req = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1232
cstate_en = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1242
false, false, true);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1344
synchronized_vblank = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1384
pipes[pipe_cnt].pipe.src.dcc = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1599
pipes[pipe_cnt].pipe.src.is_hsplit = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1960
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1962
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1964
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1966
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1968
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1970
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1972
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1974
duplicate = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2031
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2069
out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2081
bool voltage_supported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2082
bool full_pstate_supported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2083
bool dummy_pstate_supported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2118
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2123
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2322
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2365
out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
617
.xfc_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1072
*PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1297
mode_lib->vba.DCCEnabledAnyPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1329
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2050
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2051
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2185
prefetch_vm_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2199
prefetch_row_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2227
mode_lib->vba.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2311
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2314
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2315
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2319
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2324
mode_lib->vba.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2378
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2384
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2385
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2696
FirstMainPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2731
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3182
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3296
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3306
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3324
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3359
== false))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3367
mode_lib->vba.SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3431
mode_lib->vba.DCCEnabledInAnyPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3503
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3513
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3528
locals->ROBSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3545
mode_lib->vba.WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3551
mode_lib->vba.WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3559
if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3562
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3595
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3621
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3639
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3926
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3982
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3993
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4005
locals->ViewportSizeSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4009
locals->ViewportSizeSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4021
locals->TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4036
mode_lib->vba.NumberOfOTGSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4040
mode_lib->vba.NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4058
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4074
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4090
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4094
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4095
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4103
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4119
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4123
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4124
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4134
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4150
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4154
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4155
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4174
locals->DIOSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4180
locals->DSCCLKRequiredMoreThanSupported[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4211
locals->NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4235
|| locals->RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4389
locals->UrgentLatencySupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4786
locals->prefetch_vm_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4795
locals->prefetch_row_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4812
locals->BandwidthWithoutPrefetchSupported[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4817
locals->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4824
locals->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4832
locals->VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4913
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4916
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4917
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4921
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4937
mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4946
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4947
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4948
locals->PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4970
&& mode_lib->vba.Cursor64BppSupport == false)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4971
mode_lib->vba.CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4984
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4996
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5012
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5029
} else if (locals->NotEnoughDSCUnits[i] != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5031
} else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
504
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5061
} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5068
locals->ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5079
if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1132
*PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1357
mode_lib->vba.DCCEnabledAnyPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1389
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2086
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2087
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2219
prefetch_vm_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2233
prefetch_row_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2261
mode_lib->vba.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2345
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2348
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2349
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2353
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2358
mode_lib->vba.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2412
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2418
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2419
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2769
FirstMainPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2804
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3255
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3403
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3413
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3431
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3466
== false))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3474
mode_lib->vba.SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3538
mode_lib->vba.DCCEnabledInAnyPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3610
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3620
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3635
locals->ROBSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3652
mode_lib->vba.WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3658
mode_lib->vba.WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3666
if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3669
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3702
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3728
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3746
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4040
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4096
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4107
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4119
locals->ViewportSizeSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4123
locals->ViewportSizeSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4135
locals->TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4150
mode_lib->vba.NumberOfOTGSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4154
mode_lib->vba.NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4173
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4190
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4207
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4211
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4212
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4221
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4238
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4242
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4243
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4254
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4271
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4275
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4276
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4295
locals->DIOSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4301
locals->DSCCLKRequiredMoreThanSupported[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4332
locals->NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4356
|| locals->RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4506
locals->UrgentLatencySupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4905
locals->prefetch_vm_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4914
locals->prefetch_row_bw_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4931
locals->BandwidthWithoutPrefetchSupported[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4936
locals->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4943
locals->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4951
locals->VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5032
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5035
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5036
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5040
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5053
mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5062
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5063
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5064
locals->PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5086
&& mode_lib->vba.Cursor64BppSupport == false)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5087
mode_lib->vba.CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5100
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5112
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5128
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5145
} else if (locals->NotEnoughDSCUnits[i] != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5147
} else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5177
} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5184
locals->ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5195
if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
595
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
110
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
243
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
244
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
267
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
268
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
273
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
283
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
350
false);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
110
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
243
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
244
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
267
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
268
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
273
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
283
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
350
false);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1186
*Independent64ByteBlock = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1191
*Independent64ByteBlock = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1435
*PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1682
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2098
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2099
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2275
if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2310
mode_lib->vba.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2386
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2389
if (locals->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2390
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2394
mode_lib->vba.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2399
mode_lib->vba.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2571
locals->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2577
locals->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2578
locals->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2591
false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2829
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3261
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3530
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3540
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3558
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3593
== false))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3601
mode_lib->vba.SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3665
mode_lib->vba.DCCEnabledInAnyPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3678
if (mode_lib->vba.HostVMEnable == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3696
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3706
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3724
locals->ROBSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3741
mode_lib->vba.WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3747
mode_lib->vba.WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3755
if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3758
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3791
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3817
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3835
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4134
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4190
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4201
locals->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4213
locals->ViewportSizeSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4217
locals->ViewportSizeSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4229
locals->TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4244
mode_lib->vba.NumberOfOTGSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4248
mode_lib->vba.NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4258
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4262
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4267
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4284
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4301
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4305
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4306
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4315
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4332
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4336
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4337
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4348
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4365
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4369
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4370
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4389
locals->DIOSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4395
locals->DSCCLKRequiredMoreThanSupported[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4426
locals->NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4450
|| locals->RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4840
if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4865
locals->BandwidthWithoutPrefetchSupported[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4872
locals->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4879
locals->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4887
locals->VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4890
mode_lib->vba.AnyLinesForVMOrRowTooLarge = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4897
if (mode_lib->vba.MaxVStartup <= 13 || mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4970
locals->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4973
if (locals->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4974
locals->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4978
locals->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5063
locals->TotalVerticalActiveBandwidthSupport[i][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5074
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5075
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5076
locals->PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5087
if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5088
mode_lib->vba.CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5101
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5113
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5129
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5186
locals->ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5197
if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6014
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6048
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
698
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
225
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
226
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
251
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
252
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
257
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
267
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
339
false);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
85
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
118
.xfc_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
318
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
324
stream_status->fpo_in_use = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1061
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1064
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1072
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1075
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1083
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1086
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1757
*PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1797
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1798
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1982
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2356
DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2357
VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2440
v->NotEnoughUrgentLatencyHiding[0][0] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2441
v->NotEnoughUrgentLatencyHidingPre = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2538
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2619
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2623
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2624
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2628
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2633
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2641
v->ImmediateFlipSupported)) ? true : false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2850
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2856
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2857
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2868
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2910
v->FirstMainPlane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2994
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3207
if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3349
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3438
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3455
bool ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3475
if (v->ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3487
v->ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3511
v->ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3521
v->SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3581
v->WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3587
v->WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3604
EnoughWritebackUnits = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3610
WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3613
WritebackModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3639
v->WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3642
v->WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3829
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3833
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3839
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3850
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3868
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3886
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3891
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3904
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3914
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3926
v->TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3932
v->NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3962
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3963
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3966
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3967
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3975
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3990
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3993
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3994
v->LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3995
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4094
v->DIOSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4103
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4104
v->ODMCombine4To1SupportCheckOK[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4112
v->NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4191
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4436
v->NotUrgentLatencyHiding[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4589
v->ROBSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4610
v->TotalVerticalActiveBandwidthSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4626
v->BandwidthWithoutPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4770
v->NotEnoughUrgentLatencyHidingPre = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4778
if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4780
v->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4785
v->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4792
v->DynamicMetadataSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4799
v->VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4802
v->AnyLinesForVMOrRowTooLarge = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4876
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4879
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4880
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4884
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4886
if (v->MaxVStartup <= 13 || v->AnyLinesForVMOrRowTooLarge == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4893
&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4965
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4966
v->PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4976
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4977
v->CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5005
v->PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5038
v->ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5741
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5773
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6160
*ViewportSizeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6161
ViewportSizeSupportPerPlane[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
824
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
894
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
902
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
933
MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1183
bool visited[DC__NUM_PIPES__MAX] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1187
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
169
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
170
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
195
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
196
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
201
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
205
req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
218
req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
933
bool dual_plane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
947
bool scl_enable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
105
.xfc_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
213
.do_urgent_latency_adjustment = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
106
.xfc_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
103
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
105
.xfc_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
115
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
116
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
195
.do_urgent_latency_adjustment = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
220
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
223
.dsc422_native_support = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
260
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
261
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
291
.do_urgent_latency_adjustment = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
319
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
322
.dsc422_native_support = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
359
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
360
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
439
.do_urgent_latency_adjustment = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
75
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
78
.dsc422_native_support = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1022
MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1201
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1204
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1212
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1215
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1223
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1226
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1956
*PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2165
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2449
NoChromaPlanes = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2585
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2586
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2688
v->NoEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2689
v->NoEnoughUrgentLatencyHidingPre = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2806
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2818
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2885
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2889
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2894
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2898
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2904
v->ImmediateFlipSupported)) ? true : false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3090
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3094
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3095
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3105
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3165
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3304
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3436
if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3565
v->ImmediateFlipSupportedForPipe[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3664
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0))
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3795
bool P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3796
bool DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3797
bool DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3799
bool ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3800
bool FMTBufferExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3812
if (v->ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3818
v->ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3832
v->ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3842
v->SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3892
v->WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3906
EnoughWritebackUnits = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3921
v->WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3924
v->WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4140
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4144
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4150
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4162
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4177
NoChroma = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4190
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4209
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4215
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4231
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4241
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4253
v->TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4259
v->NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4288
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4289
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4292
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4293
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4301
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4316
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4319
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4320
v->LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4324
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4531
v->LinkCapacitySupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4556
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4558
v->ODMCombine4To1SupportCheckOK[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4566
v->NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4647
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4895
v->DCCMetaBufferSizeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4929
v->NotEnoughUrgentLatencyHidingA[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5062
v->ROBSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5087
v->TotalVerticalActiveBandwidthSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5106
bool UnboundedRequestEnabledThisState = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5115
v->BandwidthWithoutPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5220
v->NotEnoughUrgentLatencyHidingPre = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5228
if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5230
v->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5235
v->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5242
v->DynamicMetadataSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5249
v->VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5252
v->AnyLinesForVMOrRowTooLarge = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5309
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5312
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5313
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5317
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5320
if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5328
&& ((v->HostVMEnable == false &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5378
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5379
v->PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5389
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5390
v->CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5421
v->PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5444
&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5445
&& v->DTBCLKRequiredMoreThanSupported[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5449
&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5452
&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5453
&& ((v->HostVMEnable == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5456
&& FMTBufferExceeded == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5459
v->ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5461
if (v->ScaleRatioAndTapsSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5463
if (v->SourceFormatPixelAndScanSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5465
if (v->ViewportSizeSupport[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5467
if (v->LinkCapacitySupport[i] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5469
if (v->ODMCombine4To1SupportCheckOK[i] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5475
if (v->ROBSupport[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5477
if (v->DISPCLK_DPPCLK_Support[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5479
if (v->TotalAvailablePipesSupport[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5481
if (EnoughWritebackUnits == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5483
if (v->WritebackLatencySupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5485
if (v->WritebackScaleRatioAndTapsSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5487
if (v->CursorSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5489
if (v->PitchSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5493
if (v->PrefetchSupported[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5495
if (v->DynamicMetadataSupported[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5497
if (v->TotalVerticalActiveBandwidthSupport[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5499
if (v->VRatioInPrefetchSupported[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5501
if (v->PTEBufferSizeNotExceeded[i][j] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5505
if (!((v->HostVMEnable == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6222
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6250
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6786
*ViewportSizeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6787
ViewportSizeSupportPerPlane[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7220
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7224
ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
876
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
960
if (DynamicMetadataEnable == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
974
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
977
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1060
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
176
.do_urgent_latency_adjustment = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
194
if (dc->config.use_default_clock_table == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
314
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
366
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
394
dc->config.enable_4to1MPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
56
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
59
.dsc422_native_support = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
96
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
97
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1040
MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1219
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1222
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1230
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1233
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1241
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1244
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1973
*PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2183
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2468
NoChromaPlanes = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2603
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2604
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2707
v->NoEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2708
v->NoEnoughUrgentLatencyHidingPre = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2825
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2837
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2904
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2908
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2912
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2916
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2922
v->ImmediateFlipSupported)) ? true : false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3109
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3113
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3114
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3124
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3183
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3323
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3542
if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3671
v->ImmediateFlipSupportedForPipe[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3770
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0))
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3888
bool P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3889
bool DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3890
bool DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3892
bool ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3893
bool FMTBufferExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3905
if (v->ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3911
v->ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3925
v->ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3933
v->SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3983
v->WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3997
EnoughWritebackUnits = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4012
v->WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4015
v->WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4230
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4234
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4240
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4252
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4263
NoChroma = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4277
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4296
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4302
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4318
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4328
v->DISPCLK_DPPCLK_Support[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4340
v->TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4346
v->NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4375
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4376
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4379
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4380
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4388
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4403
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4406
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4407
v->LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4411
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4618
v->LinkCapacitySupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4644
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4646
v->ODMCombine4To1SupportCheckOK[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4654
v->NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4734
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4983
v->DCCMetaBufferSizeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5017
v->NotEnoughUrgentLatencyHidingA[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5148
v->ROBSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5173
v->TotalVerticalActiveBandwidthSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5192
bool UnboundedRequestEnabledThisState = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5201
v->BandwidthWithoutPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5306
v->NotEnoughUrgentLatencyHidingPre = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5314
if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5316
v->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5321
v->PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5328
v->DynamicMetadataSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5335
v->VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5338
v->AnyLinesForVMOrRowTooLarge = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5395
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5398
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5399
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5403
v->ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5406
if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5414
&& ((v->HostVMEnable == false &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5464
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5465
v->PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5475
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5476
v->CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5507
v->PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5530
&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5531
&& v->DTBCLKRequiredMoreThanSupported[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5535
&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5538
&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5539
&& ((v->HostVMEnable == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5542
&& FMTBufferExceeded == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5545
v->ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6317
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6345
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6877
*ViewportSizeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6878
ViewportSizeSupportPerPlane[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7308
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7312
ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
894
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
978
if (DynamicMetadataEnable == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
992
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
995
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1147
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1041
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1088
schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
119
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
120
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1228
bool updated = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1313
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1325
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1331
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1338
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1345
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1365
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1369
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1380
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1384
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1388
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1434
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1449
bool found_supported_config = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1476
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1556
found_supported_config = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1610
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1650
bool usr_retraining_support = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1651
bool unbounded_req_enabled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1678
context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1692
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1693
unbounded_req_enabled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1717
context->res_ctx.pipe_ctx[i].unbounded_req = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1737
context->res_ctx.pipe_ctx[i].has_vactive_margin = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1920
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1945
bool newly_split[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2065
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2070
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2088
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2092
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2107
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2111
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2123
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2145
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2146
bool repopulate_pipes = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2148
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2157
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2203
context->bw_ctx.dml.validate_max_state = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2272
bool flags_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2295
out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2319
bool need_fclk_lat_as_dummy = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2320
bool is_subvp_p_drr = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2355
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2361
stream_status->fpo_in_use = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2407
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2413
stream_status->fpo_in_use = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3393
bool allow = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3435
bool allow = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3586
vactive_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
605
bool valid_assignment_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
684
bool subvp_possible = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
78
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
780
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
799
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
814
bool subvp_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
815
bool drr_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
902
bool found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
903
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
988
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1125
if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1126
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1133
v->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1139
v->ImmediateFlipSupported)) ? true : false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1460
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1676
&& mode_lib->vba.NotEnoughDSCUnits[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
168
false, // ForceSingleDPP
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1680
&& mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1682
&& mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1694
&& mode_lib->vba.ViewportExceedsSurface == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1702
&& mode_lib->vba.NonsupportedDSCInputBPC == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1704
&& (mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1706
&& ((mode_lib->vba.HostVMEnable == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1718
mode_lib->vba.ModeSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1749
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1759
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1788
mode_lib->vba.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1798
mode_lib->vba.SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1863
mode_lib->vba.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1876
mode_lib->vba.EnoughWritebackUnits = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1892
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1896
mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2021
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2022
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2049
false,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2117
if (mode_lib->vba.RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2122
mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2130
mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2138
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2141
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2144
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2152
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2160
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2162
mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2177
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NoChroma = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2209
mode_lib->vba.MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2271
mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
228
false, /* ForceSingleDPP */
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2287
== k || mode_lib->vba.OutputMultistreamEn[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2300
mode_lib->vba.NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2311
mode_lib->vba.ExceededMultistreamSlots[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2336
mode_lib->vba.LinkCapacitySupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2341
mode_lib->vba.P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2342
mode_lib->vba.DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2343
mode_lib->vba.DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2344
mode_lib->vba.LinkRateDoesNotMatchDPVersion = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2345
mode_lib->vba.LinkRateForMultistreamNotIndicated = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2346
mode_lib->vba.BPPForMultistreamNotIndicated = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2347
mode_lib->vba.MultistreamWithHDMIOreDP = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2348
mode_lib->vba.MSOOrODMSplitWithNonDPLink = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2349
mode_lib->vba.NotEnoughLanesForMSO = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2414
mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2437
mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2443
mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2449
mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2486
mode_lib->vba.NotEnoughDSCUnits[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2487
mode_lib->vba.NotEnoughDSCSlices[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2495
mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2502
mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2508
mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2562
false, /* ForceSingleDPP */
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2843
if (mode_lib->vba.PTEBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2844
mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2849
if (mode_lib->vba.DCCMetaBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2850
mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2997
mode_lib->vba.ImmediateFlipRequiredFinal = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3003
mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3016
mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3026
mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3038
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.FullFrameMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3039
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SubViewportMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3040
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.PhantomPipeMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3131
mode_lib->vba.ROBSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3161
mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3322
mode_lib->vba.PrefetchModePerState[i][j] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3408
mode_lib->vba.PrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3415
mode_lib->vba.DynamicMetadataSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3423
mode_lib->vba.VRatioInPrefetchSupported[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3426
mode_lib->vba.AnyLinesForVMOrRowTooLarge = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3540
== false))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3541
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3544
mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3548
|| mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3560
((mode_lib->vba.HostVMEnable == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3623
if (mode_lib->vba.CursorBPP[k][0] == 64 && mode_lib->vba.Cursor64BppSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3624
mode_lib->vba.CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3665
mode_lib->vba.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3669
mode_lib->vba.ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
44
false, //mode_lib->vba.override_setting.nomDETInKByteOverrideEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
68
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
69
bool VRatioPrefetchMoreThanMax = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
719
ImmediateFlipRequirementFinal = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
743
DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
744
VRatioPrefetchMoreThanMax = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
816
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
991
if (VRatioPrefetchMoreThanMax != false || DestinationLineTimesForPrefetchLessThan2 != false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
992
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
997
v->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1046
DETPieceAssignedToThisSurfaceAlready[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1057
NextPotentialSurfaceToAssignDETPieceFound = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1239
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1251
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1257
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1264
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1280
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1368
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1369
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1376
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1377
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1379
PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1392
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1394
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1395
LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1399
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1678
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
189
bool is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
194
is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2163
PTEBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2214
DCCMetaBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2637
CanAddAnotherSurfaceToMALL = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3232
if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3451
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3531
if (v->DynamicMetadataEnable[k] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3549
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3552
*NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3604
MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3813
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3816
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3826
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3829
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3839
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3842
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4239
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4295
bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4503
SynchronizedSurfaces[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4529
SameTimingForFCLKChange = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4546
*USRRetrainingSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5193
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5239
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
542
NoChromaSurfaces = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5651
bool FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6005
SameTiming = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6123
bool NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6124
bool CalculateVActiveBandwithSupport_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6178
bool NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6306
bool NotEnoughDETSwathFillLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6309
return false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
636
*ViewportSizeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
637
ViewportSizeSupportPerSurface[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
885
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
890
ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
893
ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
896
ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
307
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
57
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
98
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
99
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
110
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
111
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
445
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
501
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
531
dc->config.enable_4to1MPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
60
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
39
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
478
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
534
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
564
dc->config.enable_4to1MPC = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
89
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
90
.odm_combine_4to1_supported = false,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1027
return false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1031
return false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1036
return false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1041
return false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
389
mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
527
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
531
mode_lib->vba.ImmediateFlipSupport = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
840
PlaneVisited[j] = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
860
mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
876
mode_lib->vba.GPUVMEnable = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
877
mode_lib->vba.HostVMEnable = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1002
s->MyError = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1088
if (DynamicMetadataEnable == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1102
*p->NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1105
*p->NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1152
s->MyError = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1348
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1351
Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1358
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1361
Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1368
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1371
Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1885
if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2056
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2813
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2963
*p->USRRetrainingSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2967
s->FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2986
s->SynchronizedSurfaces[i][j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3684
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3712
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3793
dml_bool_t FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4024
SameTiming = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4176
NoChromaOrLinearSurfaces = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4246
*p->ViewportSizeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4247
p->ViewportSizeSupportPerSurface[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4716
dml_bool_t ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4721
ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4936
DETPieceAssignedToThisSurfaceAlready[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4945
NextPotentialSurfaceToAssignDETPieceFound = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5224
p->PTEBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5290
p->DCCMetaBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5373
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5374
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5382
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5383
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5384
*OutBpp = TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5396
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5399
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5400
LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5404
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5542
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5548
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5550
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5576
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5586
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5592
*TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5744
CanAddAnotherSurfaceToMALL = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5932
dml_bool_t NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5933
dml_bool_t CalculateVActiveBandwithSupport_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5985
dml_bool_t NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6482
mode_lib->ms.support.PrefetchSupported[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6489
mode_lib->ms.support.DynamicMetadataSupported[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6500
mode_lib->ms.support.VRatioInPrefetchSupported[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6504
s->AnyLinesForVMOrRowTooLarge = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6606
if (!(mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required) && (mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6607
mode_lib->ms.support.ImmediateFlipSupportedForState[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6611
mode_lib->ms.support.ImmediateFlipSupportedForState[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6614
if (s->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || s->AnyLinesForVMOrRowTooLarge == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6620
s->AllPrefetchModeTested = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6748
if (mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6760
mode_lib->ms.support.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6780
mode_lib->ms.support.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6788
mode_lib->ms.support.SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6850
mode_lib->ms.support.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6864
mode_lib->ms.support.EnoughWritebackUnits = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6880
mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6883
mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7033
s->MPCCombineMethodAsNeededForPStateChangeAndVoltage = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7034
s->MPCCombineMethodAsPossible = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7056
false, // DSCEnable
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7124
if (mode_lib->ms.RequiresDSC[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7128
mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7134
mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7141
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7144
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7147
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7152
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7159
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7161
mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7175
s->NoChromaOrLinear = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7189
mode_lib->ms.MPCCombine[j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7245
mode_lib->ms.support.TotalAvailablePipesSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7262
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k || mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7274
mode_lib->ms.support.NonsupportedDSCInputBPC = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7276
if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7286
mode_lib->ms.support.ExceededMultistreamSlots = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7302
if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7305
mode_lib->ms.support.LinkCapacitySupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7309
mode_lib->ms.support.P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7310
mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7311
mode_lib->ms.support.DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7312
mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7313
mode_lib->ms.support.LinkRateForMultistreamNotIndicated = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7314
mode_lib->ms.support.BPPForMultistreamNotIndicated = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7315
mode_lib->ms.support.MultistreamWithHDMIOreDP = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7316
mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7317
mode_lib->ms.support.NotEnoughLanesForMSO = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7365
mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7387
mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7391
mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7395
mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7442
mode_lib->ms.support.NotEnoughDSCUnits = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7443
mode_lib->ms.support.NotEnoughDSCSlices = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7450
mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7456
mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7462
mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7514
CalculateSwathAndDETConfiguration_params->ForceSingleDPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7768
if (mode_lib->ms.PTEBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7769
mode_lib->ms.support.PTEBufferSizeNotExceeded[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7780
if (mode_lib->ms.DCCMetaBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7781
mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7909
s->ImmediateFlipRequiredFinal = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7914
mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7922
mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7929
mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7936
s->FullFrameMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7937
s->SubViewportMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7938
s->PhantomPipeMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7939
s->SubViewportMALLRefreshGreaterThan120Hz = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8030
mode_lib->ms.support.ROBSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8051
mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8065
if (mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] == 64 && mode_lib->ms.ip.cursor_64bpp_support == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8066
mode_lib->ms.support.CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8100
mode_lib->ms.support.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8104
mode_lib->ms.support.ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8149
&& mode_lib->ms.support.NotEnoughDSCUnits == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8153
&& mode_lib->ms.support.DSCCLKRequiredMoreThanSupported == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8155
&& mode_lib->ms.support.DTBCLKRequiredMoreThanSupported == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8169
&& mode_lib->ms.support.ViewportExceedsSurface == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8177
&& mode_lib->ms.support.NonsupportedDSCInputBPC == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8179
&& ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !s->ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8187
mode_lib->ms.support.ModeSupport[j] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8198
if ((mode_lib->ms.support.ModeSupport[0] == false && mode_lib->ms.support.ModeSupport[1] == true) || s->MPCCombineMethodAsPossible ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8448
false, // ForceSingleDPP
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8499
CalculateSwathAndDETConfiguration_params->ForceSingleDPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8922
s->ImmediateFlipRequirementFinal = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8935
s->AllPrefetchModeTested = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8943
s->DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8944
s->VRatioPrefetchMoreThanMax = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9197
if (s->VRatioPrefetchMoreThanMax != false || s->DestinationLineTimesForPrefetchLessThan2 != false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9200
locals->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9207
locals->PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9340
if (mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required && locals->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9341
locals->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9348
locals->ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9358
locals->ImmediateFlipSupported)) ? true : false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9380
s->AllPrefetchModeTested = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9384
s->AllPrefetchModeTested = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9716
locals->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
362
dml_print("DML: MODE SUPPORT: Link Rate Does Not Match DP Version : %s\n", mode_lib->ms.support.LinkRateDoesNotMatchDPVersion == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
363
dml_print("DML: MODE SUPPORT: Link Rate For Multistream Not Indicated : %s\n", mode_lib->ms.support.LinkRateForMultistreamNotIndicated == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
364
dml_print("DML: MODE SUPPORT: BPP For Multi stream Not Indicated : %s\n", mode_lib->ms.support.BPPForMultistreamNotIndicated == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
365
dml_print("DML: MODE SUPPORT: Multistream With HDMI Or eDP : %s\n", mode_lib->ms.support.MultistreamWithHDMIOreDP == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
366
dml_print("DML: MODE SUPPORT: Exceeded Multistream Slots : %s\n", mode_lib->ms.support.ExceededMultistreamSlots == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
367
dml_print("DML: MODE SUPPORT: MSO Or ODM Split With Non DP Link : %s\n", mode_lib->ms.support.MSOOrODMSplitWithNonDPLink == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
368
dml_print("DML: MODE SUPPORT: Not Enough Lanes For MSO : %s\n", mode_lib->ms.support.NotEnoughLanesForMSO == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
370
dml_print("DML: MODE SUPPORT: P2IWith420 : %s\n", mode_lib->ms.support.P2IWith420 == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
371
dml_print("DML: MODE SUPPORT: DSCOnlyIfNecessaryWithBPP : %s\n", mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
372
dml_print("DML: MODE SUPPORT: DSC422NativeNotSupported : %s\n", mode_lib->ms.support.DSC422NativeNotSupported == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
373
dml_print("DML: MODE SUPPORT: MPCCombineMethodIncompatible : %s\n", mode_lib->ms.support.MPCCombineMethodIncompatible == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
376
dml_print("DML: MODE SUPPORT: NotEnoughDSCUnits : %s\n", mode_lib->ms.support.NotEnoughDSCUnits == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
377
dml_print("DML: MODE SUPPORT: NotEnoughDSCSlices : %s\n", mode_lib->ms.support.NotEnoughDSCSlices == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
378
dml_print("DML: MODE SUPPORT: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe : %s\n", mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
379
dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPStateAndStaticScreen : %s\n", mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
380
dml_print("DML: MODE SUPPORT: DSCCLKRequiredMoreThanSupported : %s\n", mode_lib->ms.support.DSCCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
382
dml_print("DML: MODE SUPPORT: DTBCLKRequiredMoreThanSupported : %s\n", mode_lib->ms.support.DTBCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
383
dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPState : %s\n", mode_lib->ms.support.InvalidCombinationOfMALLUseForPState == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
384
dml_print("DML: MODE SUPPORT: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified : %s\n", mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
394
dml_print("DML: MODE SUPPORT: Viewport Exceeds Surface : %s\n", mode_lib->ms.support.ViewportExceedsSurface == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
402
dml_print("DML: MODE SUPPORT: Non supported DSC Input BPC : %s\n", mode_lib->ms.support.NonsupportedDSCInputBPC == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
403
dml_print("DML: MODE SUPPORT: Exceeded MALL Size : %s\n", mode_lib->ms.support.ExceededMALLSize == false ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
404
dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported");
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
46
dml_bool_t val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
704
dml_bool_t is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
708
is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
141
timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
307
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
376
surface->dcc.enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
408
plane->composition.viewport.stationary = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
414
plane->composition.scaler_info.enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
427
plane->dynamic_meta_data.enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
545
plane->composition.viewport.stationary = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
555
plane->composition.scaler_info.enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
557
(plane->composition.scaler_info.enabled == false)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
572
if (plane->composition.scaler_info.enabled == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
599
plane->composition.viewport.stationary = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
626
plane->dynamic_meta_data.enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
649
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
662
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
688
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
738
dml_dispcfg->hostvm_enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
744
dml_dispcfg->overrides.hw.force_unbounded_requesting.value = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
208
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
222
pipe_ctx->unbounded_req = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
271
phantom_stream->use_dynamic_meta = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
327
bool phantoms_added = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
41
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
493
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
52
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
19
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
206
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
23
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
231
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
237
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
268
bool is_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
292
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
300
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
33
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
459
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
50
dml_ctx->config.pmo.force_pstate_method_enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
74
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
129
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
146
core->clean_me_up.mode_lib.ip.imall_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
165
phantom->timing.drr_config.enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
182
phantom->immediate_flip = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
183
phantom->dynamic_meta_data.enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
186
phantom->tdlut.setup_for_tdlut = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
208
svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.value = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
298
programming->stream_programming[stream_index].phantom_stream.enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
545
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
63
.ptoi_supported = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
657
in_out->mcache_allocation->requires_dedicated_mall_mcache = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
66
.dynamic_metadata_vm_enabled = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10064
bool FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10265
SameTiming = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1030
bool MinimizeReallocationSuccess = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10538
false, // ForceSingleDPP
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10580
CalculateSwathAndDETConfiguration_params->ForceSingleDPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11048
bool cursor_not_enough_urgent_latency_hiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11129
s->immediate_flip_required = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11167
s->DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11168
s->VRatioPrefetchMoreThanMax = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1122
MinimizeReallocationSuccess = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11320
mode_lib->mp.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11335
mode_lib->mp.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11342
mode_lib->mp.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11459
mode_lib->mp.PrefetchModeSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11585
if (display_cfg->plane_descriptors[k].immediate_flip && mode_lib->mp.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11586
mode_lib->mp.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11593
mode_lib->mp.ImmediateFlipSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11672
CalculateWatermarks_params->USRRetrainingRequired = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1179
DETPieceAssignedToThisSurfaceAlready[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1186
NextPotentialSurfaceToAssignDETPieceFound = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11884
mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12049
bool surf_linear_128_l = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12050
bool surf_linear_128_c = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12150
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12371
l->dual_plane = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12376
l->interlaced = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12799
base_programming->config.bits.min_ttu_vblank_usable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12983
out->informative.mode_support_info.DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12998
out->informative.mode_support_info.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13310
out->informative.misc.ROBUrgencyAvoidance = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1358
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1970
CanAddAnotherSurfaceToMALL = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
235
bool is_phantom = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3050
p->PTEBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3120
p->DCCMetaBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3767
NoChromaOrLinear = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3864
*p->ViewportSizeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3872
p->ViewportSizeSupportPerSurface[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3925
*p->hw_debug5 = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4065
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4067
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4070
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4078
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4082
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4084
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4086
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4088
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4091
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4097
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4233
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4234
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4255
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4256
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4257
*OutBpp = TruncToValidBPP(&s->TruncToValidBPP_locals, math_min2(600, PHYCLK) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4268
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4271
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4272
LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4276
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4380
*RequiresDSC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4381
LinkDSCEnable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4382
*RequiresFEC = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
444
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4834
if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4913
bool exclude_this_plane = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5097
s->NoTimeToPrefetch = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5215
*p->NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5218
*p->NotEnoughTimeForDynamicMetadata = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
539
bool is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
543
is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5610
bool Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5611
bool Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5612
bool Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6640
*ImmediateFlipSupportedForPipe = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6683
bool FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6865
*p->global_fclk_change_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6888
*p->global_dram_clock_change_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6932
*p->g6_temp_read_support = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7114
bool clk_entry_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7566
mode_lib->ms.support.PrefetchSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7578
mode_lib->ms.support.DynamicMetadataSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7586
mode_lib->ms.support.VRatioInPrefetchSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7693
mode_lib->ms.support.PrefetchSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7851
if (display_cfg->plane_descriptors[k].immediate_flip == true && mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7852
mode_lib->ms.support.ImmediateFlipSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7856
mode_lib->ms.support.ImmediateFlipSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7877
CalculateWatermarks_params->USRRetrainingRequired = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8008
if (display_cfg->plane_descriptors[k].composition.scaler_info.enabled == false
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8014
mode_lib->ms.support.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8030
mode_lib->ms.support.ScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8038
mode_lib->ms.support.SourceFormatPixelAndScanSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8116
mode_lib->ms.support.WritebackLatencySupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8134
mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8137
mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8221
if (display_cfg->plane_descriptors[k].cursor.cursor_bpp == 64 && mode_lib->ip.cursor_64bpp_support == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8222
mode_lib->ms.support.CursorSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8249
mode_lib->ms.support.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8265
mode_lib->ms.support.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8272
mode_lib->ms.support.PitchSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8280
mode_lib->ms.support.ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8394
false, // DSCEnable
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8459
if (mode_lib->ms.RequiresDSC[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8463
mode_lib->ms.support.TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8469
mode_lib->ms.support.TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8517
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8521
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8524
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8527
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8534
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8552
mode_lib->ms.support.TotalAvailablePipesSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8625
mode_lib->ms.support.EnoughWritebackUnits = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8632
mode_lib->ms.support.ExceededMultistreamSlots = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8635
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_disabled == false &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8638
mode_lib->ms.support.LinkCapacitySupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8642
mode_lib->ms.support.P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8643
mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8644
mode_lib->ms.support.DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8645
mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8646
mode_lib->ms.support.LinkRateForMultistreamNotIndicated = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8647
mode_lib->ms.support.BPPForMultistreamNotIndicated = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8648
mode_lib->ms.support.MultistreamWithHDMIOreDP = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8649
mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8650
mode_lib->ms.support.NotEnoughLanesForMSO = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8702
mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8730
mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8774
mode_lib->ms.support.NotEnoughDSCSlices = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8791
mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8800
mode_lib->ms.support.NotEnoughDSCUnits = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8821
CalculateSwathAndDETConfiguration_params->ForceSingleDPP = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8995
if (mode_lib->ms.PTEBufferSizeNotExceeded[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8996
mode_lib->ms.support.PTEBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8998
if (mode_lib->ms.DCCMetaBufferSizeNotExceeded[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8999
mode_lib->ms.support.DCCMetaBufferSizeNotExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9081
bool cursor_not_enough_urgent_latency_hiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9188
s->ImmediateFlipRequired = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9193
mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9201
mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9208
s->FullFrameMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9209
s->SubViewportMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9210
s->PhantomPipeMALLPStateMethod = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9211
s->SubViewportMALLRefreshGreaterThan120Hz = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9273
mode_lib->ms.support.OutstandingRequestsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9277
mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9293
mode_lib->ms.support.OutstandingRequestsSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9297
mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9446
mode_lib->ms.support.EnoughUrgentLatencyHidingSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9454
mode_lib->ms.support.AvgBandwidthSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9472
mode_lib->ms.support.ROBSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9478
mode_lib->ms.support.ROBSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9553
mode_lib->ms.support.ModeSupport = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
989
bool unb_req_ok = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
990
bool unb_req_en = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
11
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
14
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
20
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
156
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
30
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
417
bool is_phantom = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
473
bool is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
477
is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
536
bool clk_entry_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
558
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
584
phantom->timing.drr_config.enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
601
phantom->immediate_flip = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
602
phantom->dynamic_meta_data.enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
605
phantom->tdlut.setup_for_tdlut = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
627
svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.value = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
683
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
697
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
713
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
728
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
751
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
767
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
784
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
93
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
211
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
260
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
326
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
340
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
364
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
365
bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_identical = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
369
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
419
bool contains_drr = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
437
identical = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
532
if (in_out->programming->uclk_pstate_supported == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
544
if (in_out->programming->fclk_pstate_supported == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
658
in_out->programming->fclk_pstate_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
659
in_out->programming->uclk_pstate_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
679
if (in_out->programming->uclk_pstate_supported == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
682
if (in_out->programming->fclk_pstate_supported == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
713
if (in_out->programming->uclk_pstate_supported == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
716
if (in_out->programming->fclk_pstate_supported == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
724
in_out->programming->stutter.supported_in_blank = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
731
in_out->programming->z8_stutter.meets_eco = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
737
in_out->programming->z8_stutter.supported_in_blank = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
21
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
24
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
150
bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_equal = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
153
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
156
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
159
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
41
bool dcfclk_fine_grained = false, fclk_fine_grained = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
16
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
19
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
106
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
111
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
123
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
164
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
177
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
201
bool contains_drr = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
220
identical = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
276
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
290
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
338
is_vmin = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
375
bool optimizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
386
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
390
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
503
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
508
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
661
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
672
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
73
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
98
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1020
synchronizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1052
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1056
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1062
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1068
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1108
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1121
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1130
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1137
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1146
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
119
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1227
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
125
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1310
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1334
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1374
schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1391
bool swapped = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1436
schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1450
bool swapped = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1475
schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1529
strategy_matches_drr_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1535
strategy_matches_drr_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1541
strategy_matches_drr_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1547
strategy_matches_drr_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
155
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1556
strategy_matches_drr_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1560
strategy_matches_drr_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1591
strategy_matches_forced_requirements = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
161
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1617
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1620
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1623
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1626
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1629
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1901
false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1915
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1930
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1941
display_config->stage3.stream_svp_meta[stream_index].valid = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1943
display_config->display_config.stream_descriptors[stream_index].overrides.minimize_active_latency_hiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
201
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2111
bool fams2_required = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2120
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
214
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2188
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2197
p_state_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2205
p_state_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2210
if (in_out->base_display_config->stage3.stream_svp_meta[stream_index].valid == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2211
p_state_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2217
p_state_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2221
p_state_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2231
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2267
bool z8_stutter_optimization_too_expensive = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2268
bool stutter_optimization_too_expensive = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2276
return false; // Unexpected SoCBB setup
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
228
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2281
stutter_period_meets_z8_eco = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2311
pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2320
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2336
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2341
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2351
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
266
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
274
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
279
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
29
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
336
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
341
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
464
skip_to_next_stream = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
465
expanded_strategy_added = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
466
skip_iteration = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
528
valid = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
574
variant_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
59
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
65
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
71
.allow_state_increase = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
737
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
753
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
803
is_vmin = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
840
bool optimizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
851
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
855
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
930
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
12
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
22
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
27
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
30
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
23
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
30
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
38
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
46
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1043
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1074
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1116
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
135
if (params->last_candidate_supported == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
136
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
208
bool test_passed = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
220
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
229
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
285
bool supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
292
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
339
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
401
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
419
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
47
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
477
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
501
success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
527
bool p0pass = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
528
bool p1pass = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
61
bool mcache_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
62
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
735
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
754
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
767
result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
781
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
782
bool mcache_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
801
.all_or_nothing = false,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
829
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
830
bool mcache_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
831
bool uclk_pstate_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
832
bool vmin_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
833
bool stutter_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
863
l->informative_params.mode_is_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
866
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
879
l->min_clock_for_latency_phase.all_or_nothing = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
902
l->informative_params.mode_is_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
907
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
94
bool optimize_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
941
l->vmin_phase.all_or_nothing = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
96
if (params->last_candidate_supported == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
97
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
104
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1091
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1106
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1148
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1155
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1162
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
232
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
240
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
337
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
485
sorted = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
488
swapped = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
503
sorted = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
507
swapped = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
521
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
65
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
655
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
692
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
763
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
79
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
816
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
822
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
838
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
891
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
91
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
157
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
170
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
232
bool valid_assignment_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
234
bool current_assignment_freesync = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
272
current_assignment_freesync = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
313
bool subvp_possible = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
411
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
433
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
511
bool found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
512
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
637
schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
645
schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
801
pipe->stream->use_dynamic_meta = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
802
pipe->plane_state->flip_immediate = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
823
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
833
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
843
bool removed_pipe = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
860
pipe->plane_state->is_phantom = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
880
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
883
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
886
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
909
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c
291
policy->UseMinimumRequiredDCFCLK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c
296
policy->NomDETInKByteOverrideEnable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c
306
policy->DCCProgrammingAssumesScanDirectionUnknownFinal = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
100
out->cursor_64bpp_support = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
101
out->dynamic_metadata_vm_enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1026
out->ViewportStationary[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1034
out->ScalerEnabled[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1048
out->DynamicMetadataEnable[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1056
out->ScalerEnabled[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1078
out->ViewportStationary[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1092
if (out->ScalerEnabled[location] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1123
out->DynamicMetadataEnable[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1153
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1167
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1178
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1200
dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1213
if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1298
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1299
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1300
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1301
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
161
out->dynamic_metadata_vm_enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
231
out->ptoi_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
233
out->gpuvm_enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
234
out->hostvm_enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
236
out->dynamic_metadata_vm_enabled = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
776
out->DRRDisplay[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
866
out->OutputMultistreamEn[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
900
out->DCCEnable[location] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
96
out->ptoi_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
98
out->gpuvm_enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
99
out->hostvm_enable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
159
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
179
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
223
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
237
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
289
context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
327
context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
515
bool need_recalculation = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
547
bool is_stereo = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
121
bool optimization_done = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
149
optimization_done = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
183
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
184
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
249
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
259
pass = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
291
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
292
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
364
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
405
bool need_recalculation = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
419
context->bw_ctx.bw.dcn.clk.dtbclk_en = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
457
ASSERT(need_recalculation == false);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
551
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
554
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
636
return false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
686
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
134
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
139
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
292
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
301
is_float = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
343
force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
706
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
717
*ram_a_inuse = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
798
bool in_use = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
811
*ram_a_inuse = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
832
bool rama_occupied = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
111
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
120
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
283
bool h_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
284
bool v_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
285
bool h_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
286
bool v_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
314
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
660
dpp1_power_on_dscl(dpp_base, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
110
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
147
force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1004
*is_17x17x17 = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1130
dpp20_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1131
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
531
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
68
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
79
*ram_a_inuse = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
942
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
995
*is_12bits_color_channel = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
200
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
205
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
57
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
94
force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1203
dpp3_power_on_shaper(dpp_base, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1204
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1262
*is_12bits_color_channel = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1271
*is_17x17x17 = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1396
dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1397
dpp3_power_on_hdr3dlut(dpp_base, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1398
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1536
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
217
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
256
force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
469
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
496
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
498
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
527
dpp_base->deferred_reg_writes.bits.disable_dscl = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
536
dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
545
dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
554
dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
563
dpp_base->deferred_reg_writes.bits.disable_shaper = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
790
dpp3_power_on_blnd_lut(dpp_base, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
791
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
228
dpp3_power_on_gamcor_lut(dpp_base, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
229
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
103
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1068
bool program_isharp_1dlut = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1069
bool bs_coeffs_updated = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
112
return false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1134
dpp401_power_on_dscl(dpp_base, false);
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
276
bool h_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
277
bool v_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
278
bool h_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
279
bool v_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
327
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
956
*bs_coeffs_updated = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1063
bool is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1090
dsc_cfg->ycbcr422_simple = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1118
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1123
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1140
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1194
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1204
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1229
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1261
is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1302
bool is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1458
options->force_dsc_when_not_needed = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
215
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
231
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
291
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
322
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
337
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
342
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
353
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
362
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
384
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
389
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
397
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
468
bool is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
704
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
720
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
724
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
731
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
735
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
755
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
165
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
391
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
418
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
439
return false;
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
118
return false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
58
caps->caps.support_ocsc = false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
62
return false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
243
return false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
247
return false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
277
bool result = false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
288
dwb_ogam_lut, false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c
128
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
100
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
114
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
115
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
135
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
136
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
173
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
176
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
177
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
217
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
218
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
249
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
250
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
278
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
279
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
304
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
305
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
321
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
322
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
345
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
346
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
351
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
352
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
72
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
73
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
99
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
145
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
121
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
122
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
136
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
137
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
157
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
158
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
195
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
198
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
199
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
239
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
240
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
271
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
272
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
300
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
301
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
326
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
327
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
343
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
344
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
367
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
368
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
373
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
374
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
94
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
95
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
132
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
124
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
139
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
160
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
202
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
206
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
247
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
279
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
308
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
334
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
351
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
375
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
386
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
97
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
132
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
124
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
139
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
160
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
202
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
206
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
247
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
279
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
308
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
334
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
351
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
375
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
386
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
97
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
177
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
121
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
122
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
136
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
137
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
157
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
158
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
195
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
198
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
199
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
239
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
240
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
271
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
272
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
300
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
301
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
326
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
327
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
343
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
344
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
367
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
368
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
373
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
374
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
94
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
95
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
197
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
125
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
126
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
146
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
147
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
187
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
188
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
226
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
227
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
256
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
257
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
285
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
286
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
311
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
312
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
319
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
320
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
324
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
325
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
329
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
330
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
334
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
335
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
339
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
340
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
346
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
347
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
98
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
99
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
185
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
124
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
125
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
145
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
146
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
183
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
184
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
219
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
220
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
246
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
247
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
275
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
276
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
301
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
302
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
309
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
310
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
314
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
315
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
319
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
320
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
324
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
325
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
329
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
330
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
336
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
337
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
97
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
98
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
216
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
105
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
106
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
132
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
133
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
153
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
154
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
194
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
195
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
233
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
234
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
263
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
264
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
292
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
293
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
318
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
319
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
326
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
327
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
331
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
332
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
336
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
337
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
341
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
342
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
346
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
347
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
353
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
354
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c
206
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
125
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
126
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
146
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
147
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
184
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
185
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
220
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
221
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
247
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
248
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
276
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
277
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
302
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
303
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
310
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
311
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
315
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
316
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
320
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
321
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
325
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
326
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
330
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
331
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
337
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
338
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
98
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
99
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
218
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
117
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
118
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
138
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
139
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
165
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
166
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
201
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
202
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
228
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
229
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
254
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
255
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
277
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
278
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
285
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
286
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
290
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
291
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
295
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
296
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
300
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
301
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
305
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
306
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
312
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
313
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
93
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
94
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
210
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
113
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
114
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
148
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
149
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
185
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
186
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
212
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
213
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
238
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
239
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
261
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
262
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
269
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
270
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
274
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
275
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
279
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
280
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
284
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
285
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
289
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
290
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
296
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
297
result = false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
68
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
69
return false;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
92
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
93
return false;
sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c
276
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c
307
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c
318
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
135
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
152
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
166
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
243
return false;
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
267
service->busyness[id][en] = false;
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
276
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
290
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
310
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
315
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
342
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
347
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
352
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
368
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
460
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
470
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
478
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
661
config_data.config.ddc.data_en_bit_present = false;
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
662
config_data.config.ddc.clock_en_bit_present = false;
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
232
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
238
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
80
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c
122
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c
123
return false;
sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c
110
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c
116
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
138
ptr->opened = false;
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
189
pin->base.opened = false;
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
196
pin->mux_supported = false;
sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c
131
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c
137
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c
124
return false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
119
.supported = false
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
140
return false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
159
i2c_payloads[1].write = false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
168
return false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
282
return false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
306
return false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
321
return false;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
44
[HDCP_MESSAGE_ID_WRITE_AKSV] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
45
[HDCP_MESSAGE_ID_WRITE_AINFO] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
46
[HDCP_MESSAGE_ID_WRITE_AN] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
59
[HDCP_MESSAGE_ID_WRITE_AKE_INIT] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
61
[HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
62
[HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
65
[HDCP_MESSAGE_ID_WRITE_LC_INIT] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
67
[HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
69
[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
70
[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = false,
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
73
[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
112
return enable ? true : false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
144
forced_pstate_allow = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
215
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
251
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
365
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
510
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
590
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
626
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
679
dh_data->dchub_info_valid = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
698
bool standard_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
699
bool display_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
748
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
774
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
817
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
821
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
841
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
844
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
848
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
885
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
891
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
896
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
904
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
909
output->const_color_support = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
135
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
167
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
209
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
213
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
231
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
235
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
239
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
281
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
287
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
292
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
300
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
327
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
370
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
503
dh_data->dchub_info_valid = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
580
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
587
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
599
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
616
hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
62
bool standard_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
63
bool display_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
64
bool render_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
60
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
149
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
343
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
497
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
533
wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
581
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
103
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
144
bool standard_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
145
bool display_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
146
bool render_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
227
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
268
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
272
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
290
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
294
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
298
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
340
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
347
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
355
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
369
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1004
forced_pstate_allow = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1035
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
181
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
371
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
645
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
679
wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
724
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
796
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
800
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
817
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
821
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
825
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
867
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
874
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
881
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
896
output->grph.rgb.independent_64b_blks = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
967
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
974
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
185
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
375
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
522
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
675
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
767
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
774
hubbub32_set_sdp_control(hubbub, false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
775
hubbub1_allow_self_refresh_control(hubbub, false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
120
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
283
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
292
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
304
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1003
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1199
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
192
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
291
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
418
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
456
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
608
bool swizzle_supported = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
620
swizzle_supported = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
647
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
702
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
74
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
750
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
754
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
782
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
787
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
799
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
805
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
815
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
821
false : /* full 256B request */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
845
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
850
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
854
is_dual_plane = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
926
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
934
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
973
return false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
998
return false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1319
return in_blank ? true : false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
758
return false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
776
return false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
336
bool use_pitch_c = false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
930
return false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
948
return false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
165
REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
197
bool is_vready_at_or_after_vsync = false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
603
bool use_pitch_c = false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
726
return in_blank ? true : false;
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
217
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
105
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
117
false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1129
if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1135
pipe_ctx->stream_res.audio->enabled = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1232
hws->funcs.edp_backlight_control(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1541
if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1571
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1720
pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1721
pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1737
dc->link_srv->blank_dp_stream(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1745
link_enc->funcs->fec_set_enable(link_enc, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1746
link_enc->funcs->fec_set_ready(link_enc, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1750
link->link_status.link_active = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1770
dc->res_pool->dp_clock_source) == false)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1775
dc->res_pool->clock_sources[i]) == false)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1887
se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1896
pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1921
bool can_apply_edp_fast_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1922
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1923
bool keep_edp_vdd_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1955
can_apply_edp_fast_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2007
hws->funcs.edp_backlight_control(edp_link_with_sink, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2023
dc->hwss.edp_power_control(edp_link_with_sink, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2213
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2217
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2233
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2236
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2240
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2244
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2248
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2252
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2256
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2331
pipe_ctx_old->stream_res.audio, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
252
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2543
dcb->funcs->set_scratch_critical_state(dcb, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2555
default_adjust.force_hw_default = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2596
bool blank_target = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2687
bool rc = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2714
if (false == rc)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
278
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2835
dce_clock_gating_power_up(dc->hwseq, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2898
false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
293
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2968
false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3153
pos_cpy.enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3156
pos_cpy.enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
317
result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3201
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
324
result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3348
link->dc->hwss.edp_backlight_control(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
347
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
353
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
359
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
363
fmt.sign = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
368
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
374
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
380
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
390
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
396
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
402
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
408
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
414
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
420
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
452
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
626
xfm->funcs->opp_power_on_regamma_lut(xfm, false);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
716
bool edp_hpd_high = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
869
cntl.coherent = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
149
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
189
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
191
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
242
dh_data->dchub_info_valid = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
102
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
106
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
147
default_adjust.force_hw_default = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
184
bool blank_target = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
323
false);
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
64
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
68
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
87
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
90
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
94
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
98
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1046
hws->funcs.hubp_pg_control(hws, 0, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1050
hws->wa_state.DEGVIDCN10_253_applied = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1079
hubp->funcs->set_hubp_blank_en(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1116
if (allow_self_fresh_force_enable == false &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1201
if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1265
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1315
pipe_ctx->stream_res.audio, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1331
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1355
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1400
hubbub1_soft_reset(dc->res_pool->hubbub, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1499
hws->funcs.dpp_pg_control(hws, dpp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1502
hws->funcs.hubp_pg_control(hws, hubp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1514
hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1529
hubp->funcs->hubp_clk_cntl(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1531
dpp->funcs->dpp_dppclk_control(dpp, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1536
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1539
dc->optimized_required = false; /* We're powering off, no need to optimize */
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1574
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1575
bool tg_enabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1677
hubp->power_gated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
168
pipe_ctx->wait_is_required = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1754
hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1769
bool is_optimized_init_done = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1812
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1920
dc->hwseq->funcs.edp_backlight_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1922
dc->hwss.edp_power_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2003
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2008
bool addr_patched = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2039
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2066
result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2115
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2118
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2131
&dpp->regamma_params, false)) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2268
bool rc = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2297
if (false == rc)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2308
bool ret = checkUint32Bounary == false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2440
&modulo[i], true) == false) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2461
pclk*get_clock_divider(grouped_pipes[i], false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
247
dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2503
grouped_pipes[i]->stream->vblank_synchronized = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2504
grouped_pipes[i]->stream->has_non_synchronizable_pclk = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2521
get_clock_divider(grouped_pipes[master], false),
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2522
get_clock_divider(grouped_pipes[i], false));
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2578
grouped_pipes[i]->stream->vblank_synchronized = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2809
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2897
blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2914
blnd_cfg.pre_multiplied_alpha = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2988
bool should_divided_by_2 = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3023
should_divided_by_2 = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3131
hubp->power_gated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3136
hubp->funcs->set_blank(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3325
hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3348
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3480
bool non_stereo_timing = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3487
if (non_stereo_timing == false &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3525
dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3527
dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3551
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3577
pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3630
hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3658
bool pipe_split_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3746
pos_cpy.enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3749
pos_cpy.enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
454
bool is_gamut_remap_available = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
827
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
837
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1052
&mpc->blender_params, false))
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1081
&dpp_base->regamma_params, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1123
bool use_degamma_ram = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1126
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1172
result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1196
int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1397
bool flip_immediate = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1458
dcn20_setup_gsl_group_as_lock(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1689
bool viewport_changed = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1693
dpp->funcs->dpp_dppclk_control(dpp, false, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1852
hubp->power_gated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1871
hubp->funcs->set_blank(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2082
dc->res_pool->hubbub, true, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2224
bool is_dsc_ungated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2308
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2366
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2386
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2405
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2421
hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2463
dc->clk_mgr->clks.fw_based_mclk_switching = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2493
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2517
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2585
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2596
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2607
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2633
hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2635
hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2726
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2731
bool addr_patched = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2846
pipe_ctx->stream_res.audio, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2861
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2943
blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2955
blnd_cfg.pre_multiplied_alpha = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2972
blnd_cfg.pre_multiplied_alpha = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3109
bool enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3117
pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
315
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3191
res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3208
hubp->power_gated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
430
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
443
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
722
dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
725
hubp->funcs->hubp_update_mall_sel(hubp, 0, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
727
dc->hwss.set_flip_control_gsl(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
729
hubp->funcs->hubp_clk_cntl(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
731
dpp->funcs->dpp_dppclk_control(dpp, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
79
bool is_gamut_remap_available = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
873
odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
886
if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
961
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
101
is_in_uma = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
135
bool addr_patched = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
258
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
301
res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
318
hubp->power_gated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
386
bool mpcc_removed = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
408
if (mpcc_removed == false)
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
450
blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
82
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
99
is_in_uma = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
105
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
134
pipe_ctx->stream->dpms_off = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
256
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
300
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1016
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1024
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1025
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1088
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1143
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1146
dc_dmub_srv_p_state_delegate(dc, false, NULL);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1147
dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1192
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1203
dc_dmub_srv_p_state_delegate(dc, false, context);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1209
bool pending_updates = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1215
pending_updates = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
242
&plane_state->blend_tf, &dpp_base->regamma_params, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
260
bool result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
324
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
338
&dpp_base->degamma_params, false))
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
398
bool ret = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
404
if (ret == false && mpc->funcs->set_output_gamma) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
411
&mpc->blender_params, false))
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
481
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
486
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
510
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
700
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
757
dc->hwss.edp_backlight_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
759
dc->hwss.edp_power_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
77
bool is_gamut_remap_available = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
820
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
887
bool enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
895
pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
914
bool cursor_cache_enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
919
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
948
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
154
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
247
hws->funcs.setup_hpo_hw_control(hws, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
269
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
353
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
367
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
530
dc->hwseq->wa_state.skip_blank_stream = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
545
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
589
dc->link_srv->set_dsc_enable(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
602
pipe_ctx->stream_res.audio, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
607
dc->hwseq->wa_state.skip_blank_stream = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
717
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
107
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
177
int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
197
false,
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
301
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
315
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
331
bool two_pix_per_container = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
358
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
402
bool otg_disabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
437
int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
514
link->dc->hwss.edp_backlight_control(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1002
dc->debug.fams2_config.bits.enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1062
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1136
int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1187
bool two_pix_per_container = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1216
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1247
bool otg_disabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1282
int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1348
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1353
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1405
link->dc->hwss.edp_backlight_control(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
141
force_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1530
hws->funcs.dsc_pg_control(hws, dsc->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1657
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1672
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1781
is_seamless = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1797
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1808
dc_dmub_srv_p_state_delegate(dc, false, context);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1837
dc->hwss.pipe_control_lock(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
212
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
237
mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
258
bool mall_ss_unsupported = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
262
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
270
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
325
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
348
bool enable_subvp = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
379
bool subvp_immediate_flip = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
380
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
446
bool result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
491
&dpp_base->regamma_params, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
535
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
549
&dpp_base->degamma_params, false))
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
569
bool ret = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
575
if (ret == false && mpc->funcs->set_output_gamma) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
582
&mpc->blender_params, false))
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
619
hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
621
hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
671
bool cache_cursor = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
701
hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
832
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
891
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
913
dc->hwss.edp_backlight_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
915
dc->hwss.edp_power_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
977
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1008
update_state->pg_pipe_res_update[PG_OPTC][0] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1016
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1017
update_state->pg_pipe_res_update[PG_DPP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1029
bool hpo_frl_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1030
bool hpo_dp_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1193
pg_cntl->funcs->hpo_pg_control(pg_cntl, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1201
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1208
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1215
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1221
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1228
pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1396
dc->hwss.root_clock_control(dc, &pg_update_state, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1506
if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1507
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1511
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1517
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1535
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1550
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1553
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1559
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
187
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
282
hws->funcs.setup_hpo_hw_control(hws, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
305
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
363
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
433
int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
453
false,
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
534
dc->hwseq->funcs.edp_backlight_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
536
dc->hwss.edp_power_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
586
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
590
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
594
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
601
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
615
dc_dmub_srv_apply_idle_power_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
626
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
627
bool tg_enabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
729
hubp->power_gated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
809
pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
829
dpp->funcs->dpp_dppclk_control(dpp, false, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
871
dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
876
dc->hwss.set_flip_control_gsl(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
878
hubp->funcs->hubp_clk_cntl(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
880
dpp->funcs->dpp_dppclk_control(dpp, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
881
dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
925
bool hpo_frl_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
926
bool hpo_dp_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
956
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
959
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
962
update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
965
update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
967
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
968
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
974
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
975
update_state->pg_pipe_res_update[PG_DPP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
982
update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
985
update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
991
update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
998
update_state->pg_pipe_res_update[PG_OPTC][i] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
111
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
117
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
125
pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
49
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
50
update_state->pg_pipe_res_update[PG_DPP][j] = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1051
link->dc->hwss.edp_backlight_control(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1066
link->dc->hwss.edp_power_control(link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1094
bool mpc_combine_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1201
pos_cpy.enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1210
pos_cpy.enable = false; /* not visible beyond right edge*/
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1213
pos_cpy.enable = false; /* not visible beyond bottom edge*/
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1216
pos_cpy.enable = false; /* not visible beyond left edge*/
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1219
pos_cpy.enable = false; /* not visible beyond top edge*/
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1234
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1257
mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1276
bool mall_ss_unsupported = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1280
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1287
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1348
bool is_wait_needed = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1380
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1392
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1401
false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1404
dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1412
hubbub->funcs->program_compbuf_segments(hubbub, compbuf_size, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1417
dcn401_fams2_update_config(dc, context, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1418
dcn401_fams2_global_control_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1439
dcn401_fams2_global_control_lock(dc, context, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1568
int odm_slice_width = resource_get_odm_slice_dst_width(otg_master, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1638
dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1655
dc->clk_mgr->clks.p_state_change_support = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1660
dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1729
dc->hwss.pipe_control_lock(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1748
dc->hwss.pipe_control_lock(dc, pipe, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1787
pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1795
pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1846
pipe_ctx->stream_res.audio, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1861
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
198
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2138
dc->res_pool->hubbub, true, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2330
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2390
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2408
return false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2432
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
260
dc_allow_idle_optimizations(dc, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2666
hws->funcs.dpp_pg_control(hws, dpp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2669
hws->funcs.hubp_pg_control(hws, hubp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2682
hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
282
dc->hwss.edp_backlight_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
284
dc->hwss.edp_power_control(edp_link, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
346
dc->res_pool->hubbub, false, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
378
bool lut1d_enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
438
&dpp_base->regamma_params, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
455
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
474
hubp->funcs->hubp_enable_3dlut_fl(hubp, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
635
&dpp_base->regamma_params, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
671
bool ret = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
677
if (ret == false && mpc->funcs->set_output_gamma) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
684
&mpc->blender_params, false))
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
713
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
770
bool manual_mode = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
792
odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
812
if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
859
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
451
return false;
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
189
return false;
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
198
return false;
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
217
return false;
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
224
return false;
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
120
return false;
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
163
return false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
1017
if (skip_immediate_retrain == false)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
185
dp_retrain_link_dp_test(link, &link_settings, false);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
677
return false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
699
link->test_pattern_enabled = false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
72
bool dpms_off = false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
73
bool needs_divider_update = false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
808
return false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
813
return false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
877
return false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
936
false,
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
991
dp_retrain_link_dp_test(link, &store_settings, false);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
100
pipe_ctx->stream->signal, false);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
104
false);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
272
pipe_ctx->stream_res.stream_enc, false);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
111
return false;
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
84
return false;
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
87
return false;
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
97
return false;
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
102
false);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
146
false);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
130
return false;
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
133
return false;
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
145
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1017
if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1018
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1028
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1051
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1085
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1283
link->dc->hwss.edp_power_control(link, false);
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1290
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1296
bool is_delegated_to_mst_top_mgr = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1328
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1352
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1383
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
298
.write = false,
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
328
bool is_type2_dongle = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
374
is_valid_hdmi_signature = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
385
is_valid_hdmi_signature = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
431
sink_cap->is_dongle_type_one = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
572
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
576
link->cur_link_settings.use_link_rate_set = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
599
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
608
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
626
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
629
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
687
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
717
link->wa_flags.dpia_mst_dsc_always_on = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
756
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
821
bool destrictive = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
823
bool is_link_enc_unavailable = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
841
destrictive = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
846
destrictive = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
876
bool converter_disable_audio = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
878
bool same_edid = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
891
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
910
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
922
link->link_state_valid = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
983
return false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
990
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1003
pipe_ctx->stream_res.stream_enc, false, NULL, true);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1013
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1026
dp_set_dsc_on_rx(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1027
link_set_dsc_on_stream(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1039
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1041
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1044
link_set_dsc_pps_packet(pipe_ctx, true, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1365
false))
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
145
dpcd_write_rx_power_ctrl(link, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1556
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1571
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1928
link->dc->hwss.edp_power_control(link, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1933
enable_mst_on_sink(link, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1937
dp_set_fec_enable(link, link_res, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1938
dp_set_fec_ready(link, link_res, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1957
link->link_status.link_active = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1959
link->link_status.link_active = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1970
bool is_over_340mhz = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1981
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2047
bool apply_seamless_boot_optimization = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2051
bool do_fallback = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2085
enable_mst_on_sink(link, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2102
state, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2118
skip_video_pattern = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
219
pipe->stream->dpms_off == false) {
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2286
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
229
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
235
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2389
update_sst_payload(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2401
false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2406
false, false, &settings);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2409
false, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2412
write_i2c_redriver_setting(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2432
edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2436
link_set_dsc_enable(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2514
pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2528
pipe_ctx->stream->dpms_off = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2536
update_psp_stream_config(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2545
pipe_ctx->stream->dpms_off = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2546
update_psp_stream_config(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2596
if (false == stream->link->link_status.link_active)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2664
update_psp_stream_config(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2669
set_avmute(pipe_ctx, false);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
301
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
303
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
305
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
309
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
314
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
345
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
360
bool i2c_success = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
517
bool i2c_success = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
639
bool i2c_success = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
776
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
789
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
840
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
893
false,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
902
pipe_ctx->stream_res.stream_enc, false, NULL, true);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
952
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
955
return false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
971
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
998
false,
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
736
link->psr_settings.psr_vtotal_control_support = false;
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
757
return false;
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
786
link->is_internal_display = false;
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
826
return false;
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
847
if (false == link_construct(link, init_params))
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
105
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
109
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
113
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
119
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
130
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
141
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
144
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
153
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
156
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
159
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
163
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
166
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
169
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
172
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
175
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
178
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
181
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
184
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
187
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
190
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
193
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
196
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
199
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
202
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
205
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
208
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
211
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
214
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
217
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
220
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
223
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
287
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
310
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
329
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
414
if ((link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) && (link->hpd_status == false))
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
419
if ((dp_tunnel_settings == NULL) || (dp_tunnel_settings->should_use_dp_bw_allocation == false))
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
426
bool is_new_slot = false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
443
if (link_count && link_dpia_validate_dp_tunnel_bandwidth(dpia_link_sets, link_count) == false)
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
69
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
83
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
87
return false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
91
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
95
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
134
hw_info.hw_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
143
ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
144
ddc_service->flags.FORCE_READ_REPEATED_START = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
145
ddc_service->flags.EDID_STRESS_READ = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
202
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
279
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
282
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
285
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
301
current_payload.write_status_update = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
335
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
344
payload.write_status_update = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
359
payload.write = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
363
payload.mot = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
374
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
385
&payloads, address, read_size, read_buf, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
462
.i2c_over_aux = false,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
469
.write_status_update = false,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
480
.i2c_over_aux = false,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
481
.write = false,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
487
.write_status_update = false,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
505
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
63
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1147
link->dpcd_caps.is_branch_dev = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1347
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1488
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1518
bool mst = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1524
*link->preferred_training_settings.mst_enable == false) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1525
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1555
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1558
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1563
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1567
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1698
bool is_fec_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1699
bool is_dsc_basic_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1700
bool is_dsc_passthrough_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1722
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1756
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1838
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1881
link->test_pattern_enabled = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2010
link->wa_flags.dpia_forced_tbt3_mode = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2129
(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true : false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2135
(general_edp_cap & DP_EDP_SET_POWER_CAP) ? true : false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2215
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2230
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2273
is_uhbr13_5_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2299
is_uhbr13_5_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2317
is_uhbr13_5_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2344
bool success = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2410
bool success = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2420
dp_trace_set_lt_start_timestamp(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2534
*auxless_support = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2535
*auxwake_support = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
331
link->wa_flags.dp_keep_receiver_powered = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
335
link->wa_flags.dp_keep_receiver_powered = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
358
bool force_disable = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
361
force_disable = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
368
dsc_support.DSC_SUPPORT == false
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
580
current_link_setting->use_link_rate_set = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
595
bool found = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
598
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
668
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
676
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
695
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
711
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
716
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
723
LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
729
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
759
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
809
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
836
initial_link_setting.use_link_rate_set = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
840
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
883
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
938
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c
143
link->hpd_status = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c
68
if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling == false)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
225
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
228
if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
230
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
395
if (router_sets[j].is_valid == false) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
425
if (router_sets[i].is_valid == false)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
435
is_success = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
58
link->dpia_bw_alloc_config.bw_alloc_enabled = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
115
return_code = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
127
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
168
allow_active = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
169
edp_set_psr_allow_active(link, &allow_active, true, false, NULL);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
171
edp_set_psr_allow_active(link, &allow_active, true, false, NULL);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
185
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
193
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
257
allow_active = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
258
edp_set_replay_allow_active(link, &allow_active, true, false, NULL);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
260
edp_set_replay_allow_active(link, &allow_active, true, false, NULL);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
407
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
417
bool status = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
420
*out_link_loss = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
423
*has_left_work = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
444
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
464
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
470
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
493
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
517
status = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
57
sink_status_changed = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
58
return_code = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
172
link_enc->funcs->fec_set_ready(link_enc, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
205
link_enc->funcs->fec_set_enable(link_enc, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
80
dpcd_write_rx_power_ctrl(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1235
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1436
req_drv_setting_changed = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1440
req_drv_setting_changed = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1459
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1464
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1538
perform_post_lt_adj_req_sequence(link, link_res, lt_settings) == false)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1636
bool is_link_bw_low = false; /* link bandwidth < stream bandwidth */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1650
dp_trace_set_lt_start_timestamp(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1706
dp_trace_lt_total_count_increment(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1707
dp_trace_lt_result_update(link, status, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1708
dp_trace_set_lt_end_timestamp(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1723
dp_trace_lt_fail_count_update(link, fail_count, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1738
do_fallback = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1779
is_link_bw_low = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1814
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
473
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
485
done = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
498
done = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
509
locked = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
748
lt_settings->always_match_dpcd_with_hw_lane_settings = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
195
ASSERT(false); /* Message type not supported by helper function. */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
224
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
109
bool apply_toggle_rate_wa = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1004
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1012
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1021
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1024
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1078
link->replay_settings.config.replay_video_conferencing_optimization_enabled = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1097
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1105
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1120
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1123
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1141
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1144
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1162
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1174
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1176
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1231
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1233
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1242
bool use_hpo_dp_link_enc = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
162
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
196
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
201
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
227
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
231
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
247
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
250
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
254
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
264
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
275
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
281
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
292
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
298
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
306
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
326
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
332
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
361
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
395
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
426
dpcd_write_rx_power_ctrl(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
430
link->dc->hwss.edp_backlight_control(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
434
link->dc->hwss.edp_power_control(link, false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
446
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
517
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
523
alpm_config.bits.ENABLE = (enable ? true : false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
56
bool panel_mode_edp = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
572
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
593
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
596
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
600
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
628
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
641
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
704
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
730
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
737
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
740
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
929
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
944
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
947
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
978
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
126
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
178
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
184
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
210
return false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
233
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
68
link->is_hpd_filter_disabled = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
89
ASSERT_CRITICAL(false);
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
100
REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
277
bool found = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
341
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
344
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
417
if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
514
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
522
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1054
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1062
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1063
mpcc->shared_bottom = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1234
mpc3_set_3dlut_mode(mpc, LUT_BYPASS, false, false, rmu_idx);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1235
return false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1298
mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
386
mpc3_power_on_ogam_lut(mpc, mpcc_id, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
875
return false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
89
return false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
899
mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
957
*is_12bits_color_channel = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
966
*is_17x17x17 = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
273
mpc32_power_on_blnd_lut(mpc, mpcc_id, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
274
return false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
724
return false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
747
mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
784
*is_12bits_color_channel = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
793
*is_17x17x17 = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
923
mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
924
return false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
987
mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
106
*is_17x17x17 = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
159
mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
218
mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
97
*is_12bits_color_channel = false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1293
bool ret = false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1302
ret = false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1313
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1414
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1473
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1538
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1570
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1594
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
457
optc1_set_blank_data_double_buffer(optc, false);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
614
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
618
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
627
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
631
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
635
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
640
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
694
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
719
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
101
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
104
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
108
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
113
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
92
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
190
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
267
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
159
ASSERT(false);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
321
bool program_manual_trigger = false;
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
395
false);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
462
return false;
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
84
if (second_preferred_memory_for_opp[i] == false) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
407
all_stream_disabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
411
all_mpcc_disabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
414
all_opp_disabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
417
all_optc_disabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
498
bool block_enabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
82
bool block_enabled = false;
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1021
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1023
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1025
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1033
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1035
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1094
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1176
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
388
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
846
bool at_least_one_pipe = false;
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
891
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
895
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1057
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1068
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1075
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1082
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1168
false);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1261
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1377
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1392
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1395
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1532
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
408
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
436
.argb8888 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
438
.fp16 = false
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
934
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
936
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
968
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1003
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1007
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1248
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1259
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1264
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1269
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1274
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1279
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1284
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1413
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
413
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
617
.dp_ycbcr420_supported = false,
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
891
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1090
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1100
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1104
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1108
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1112
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1116
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1120
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1286
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
511
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
701
.dp_ycbcr420_supported = false,
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1064
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1122
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1124
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1126
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1134
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1136
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1262
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1321
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1323
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1331
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1333
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1459
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
402
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
403
.fp16 = false
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
702
transform->prescaler_on = false;
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
912
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
926
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
928
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
936
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
938
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1074
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1134
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1136
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1138
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1146
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1148
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1274
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1335
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1337
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1345
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1471
return false;
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
404
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
708
transform->prescaler_on = false;
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
920
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
934
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
936
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
938
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
946
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
948
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1156
bool video_down_scaled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1157
bool video_large = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1158
bool desktop_large = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1159
bool dcc_disabled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1160
bool mpo_enabled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1302
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1307
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1358
dc->caps.post_blend_color_processing = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1359
dc->caps.extended_aux_timeout_support = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1409
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1413
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1417
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1423
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1499
dc->debug.az_endpoint_mute_only = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1671
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
517
.p010 = false
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
535
.disable_dmcu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
536
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
545
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
546
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
554
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
556
.recovery_enabled = false, /*enable this by default after testing.*/
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
560
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
869
hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1368
res_ctx->is_dsc_acquired[i] = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1515
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1527
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1611
if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1668
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1673
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1824
bool force_split = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1994
dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2012
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2014
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2019
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2121
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2180
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2248
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2273
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2352
bool clock_limits_available = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2353
bool uclk_states_available = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2493
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2497
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2501
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2505
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2509
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2513
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2760
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
707
.disable_dmcu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
708
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
712
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
715
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
717
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
719
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
722
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1167
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1171
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1298
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
580
.nv12 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
582
.p010 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
602
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
606
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
609
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
614
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
618
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1476
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1480
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1484
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1488
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1492
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1528
dc->debug.dmub_command_table = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1697
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
611
.disable_dmcu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
612
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
617
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
620
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
622
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
625
.disable_48mhz_pwrdwn = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
630
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
635
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
636
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
637
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
774
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
776
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
781
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
915
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1226
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1251
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1394
if (writeback_info->wb_enabled == false)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1436
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1471
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1475
res_ctx->is_mpc_3dlut_acquired[i] = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1493
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1506
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1565
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1633
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1634
bool repopulate_pipes = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1636
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1637
bool newly_split[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1643
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1691
context->bw_ctx.dml.validate_max_state = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1877
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1948
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1954
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1966
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1969
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1972
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1975
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1978
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1982
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1986
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1989
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1992
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1995
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2000
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2042
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2088
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2393
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2397
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2401
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2405
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2409
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2413
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2613
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
692
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
713
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
717
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
720
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
722
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
724
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
730
.enable_legacy_fast_update = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
731
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
736
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
737
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
738
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1186
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1211
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1286
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1299
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1517
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1521
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1525
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1529
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1719
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
663
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
684
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
686
.disable_dpp_power_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
687
.disable_hubp_power_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
692
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
695
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
698
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
702
.use_max_lb = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
705
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
101
.enable_legacy_fast_update = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
102
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
107
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
108
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
109
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1309
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1313
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1317
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1321
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1325
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
143
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1506
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
718
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
753
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
84
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
88
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
91
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
93
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
95
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
951
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
963
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
101
.enable_legacy_fast_update = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
102
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
107
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
108
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
109
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1253
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1257
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
140
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1438
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
679
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
714
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
84
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
88
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
896
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
908
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
91
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
93
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
95
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1524
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1549
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1634
pipes[i].pipe.src.hostvm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1649
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1673
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1703
dc->config.enable_4to1MPC = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1765
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1809
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1916
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1997
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2001
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2007
&clk_src_regs_b0[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2011
&clk_src_regs_b0[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2016
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2020
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2026
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2218
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
839
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
860
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
862
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
864
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
867
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
869
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
871
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
881
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
894
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
899
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
900
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
901
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1582
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1607
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1703
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1720
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1748
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1845
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1936
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1940
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1944
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1948
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1952
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
2136
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
851
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
872
.disable_z10 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
878
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
880
.disable_dpp_power_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
881
.disable_hubp_power_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
882
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
884
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
887
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
889
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
891
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
901
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
918
.symclk32_se = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
928
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
935
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
936
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
937
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1524
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1549
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1641
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1643
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1656
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1659
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1695
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1788
dc->config.enable_4to1MPC = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1885
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1958
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1962
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1966
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1970
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1974
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
2157
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
838
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
860
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
862
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
864
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
867
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
869
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
871
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
881
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
892
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
897
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
898
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
899
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1517
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1542
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1639
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1673
dc->config.enable_4to1MPC = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1761
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1834
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1838
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1842
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1846
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1850
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
2025
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
833
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
855
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
857
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
859
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
862
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
864
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
866
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
876
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
886
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
891
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
892
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
893
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1515
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1544
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1603
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1625
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1629
res_ctx->is_mpc_3dlut_acquired[i] = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1737
pipe->stream->use_dynamic_meta = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1738
pipe->plane_state->flip_immediate = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1748
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1760
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1804
out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1827
dc_state_set_stream_cursor_subvp_limit(stream, context, false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1874
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1878
bool single_display_subvp = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1961
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1977
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2020
context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2234
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2316
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2320
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2324
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2328
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2332
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2564
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
671
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
692
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
694
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
696
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
699
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
701
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
703
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
709
.vga = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
710
.i2c = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
711
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
712
.dscl = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
713
.cm = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
714
.mpc = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
719
.force_disable_subvp = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
721
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
722
.using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
728
.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
731
.disable_unbounded_requesting = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
733
.disable_fpo_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
735
.disable_fpo_vactive = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
736
.disable_boot_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
737
.disable_subvp_high_refresh = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
741
.enable_legacy_fast_update = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
165
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
181
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
192
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
209
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
214
bool is_center_timing = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
235
bool psr_capable = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
469
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
475
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
478
!dc_stream_is_refresh_rate_range_flickerless(fpo_candidate_stream, (refresh_rate_max_stretch_100hz / 100), current_refresh_rate, false))
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
479
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
520
bool is_fpo_vactive = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
593
bool is_native_scaling = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
620
bool disallow = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
646
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
650
bool drr_pipe_found = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
651
bool drr_psr_capable = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
653
bool subvp_disallow = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
706
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
710
bool drr_pipe_found = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
712
bool vblank_psr_capable = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
714
bool subvp_disallow = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1495
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1524
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1816
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1820
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1824
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1828
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1832
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2055
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
667
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
688
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
690
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
692
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
695
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
697
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
699
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
705
.vga = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
706
.i2c = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
707
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
708
.dscl = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
709
.cm = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
710
.mpc = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
715
.force_disable_subvp = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
722
.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
725
.disable_unbounded_requesting = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
727
.disable_fpo_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
729
.disable_fpo_vactive = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
730
.disable_boot_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
731
.disable_subvp_high_refresh = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
734
.enable_legacy_fast_update = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
736
.using_dml2 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1609
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1648
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1739
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1864
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1966
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1970
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1974
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1978
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1982
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2179
dc->dml2_options.minimize_dispclk_using_odm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2200
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
693
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
714
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
716
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
718
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
724
.disable_clock_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
727
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
729
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
731
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
739
.vga = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
741
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
760
.physymclk = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
769
.enable_hpo_pg_support = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
772
.disable_idle_power_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
773
.dmcub_emulation = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
774
.disable_boot_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
775
.disable_unbounded_requesting = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
776
.disable_mem_low_power = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
780
.disable_z10 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
785
.disable_dmub_reallow_idle = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
793
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
794
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
795
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1589
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1628
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1719
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1837
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1938
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1942
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1946
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1950
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1954
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2152
dc->dml2_options.minimize_dispclk_using_odm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2173
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
673
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
694
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
696
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
698
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
704
.disable_clock_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
707
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
709
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
711
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
719
.vga = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
721
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
738
.symclk32_le = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
740
.physymclk = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
749
.enable_hpo_pg_support = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
752
.disable_idle_power_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
753
.dmcub_emulation = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
754
.disable_boot_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
755
.disable_unbounded_requesting = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
756
.disable_mem_low_power = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
760
.disable_z10 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
765
.disable_dmub_reallow_idle = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
773
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
774
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
775
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1590
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1629
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1720
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1837
dc->caps.force_dp_tps4_for_cp2520 = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1939
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1943
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1947
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1951
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1955
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2152
dc->dml2_options.minimize_dispclk_using_odm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2173
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
674
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
695
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
697
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
699
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
705
.disable_clock_gate = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
708
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
710
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
712
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
720
.vga = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
722
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
741
.physymclk = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
750
.enable_hpo_pg_support = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
753
.disable_idle_power_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
754
.dmcub_emulation = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
755
.disable_boot_optimizations = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
756
.disable_unbounded_requesting = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
757
.disable_mem_low_power = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
761
.disable_z10 = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
766
.disable_dmub_reallow_idle = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
774
.disable_psr = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
775
.disallow_psrsu = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
776
.disallow_replay = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1518
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1549
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1650
dc_state_set_stream_cursor_subvp_limit(stream, context, false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2014
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2018
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2022
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2026
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2259
return false;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
662
.ayuv = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
683
.force_abm_enable = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
685
.disable_pplib_clock_request = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
687
.force_single_disp_pipe_split = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
690
.performance_trace = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
692
.disable_pplib_wm_range = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
694
.sanity_checks = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
700
.vga = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
701
.i2c = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
702
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
703
.dscl = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
704
.cm = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
705
.mpc = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
710
.force_disable_subvp = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
711
.disable_force_pstate_allow_on_hw_release = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
720
.allow_sw_cursor_fallback = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
723
.disable_unbounded_requesting = false,
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
724
.enable_legacy_fast_update = false,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1053
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1055
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1092
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1093
*enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1095
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1105
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1106
*enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1108
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1117
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1118
*enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1140
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1141
*enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1468
dscl_prog_data->easf_v_en = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1605
dscl_prog_data->easf_h_en = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1805
bool res = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1832
bool res = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1833
bool enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1834
bool enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1840
bool enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1897
bool res = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1898
bool enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1899
bool enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
19
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1900
bool enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
27
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
36
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
45
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
517
*orthogonal_rotation = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
518
*flip_vert_scan_dir = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
519
*flip_horz_scan_dir = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
805
bool skip_easf = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
840
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
846
bool enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
853
if (spl_in->adaptive_sharpness.enable == false)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
896
bool check_max_downscale = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
976
bool skip_easf = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
983
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
984
*enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
985
*enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
986
return false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
992
*enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
993
*enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
994
*enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
23
*negative = false;
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
33
*negative = false;
sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c
91
LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
147
return false;
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
149
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6549
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6552
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6581
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6584
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6610
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6653
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6676
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6695
return false;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6698
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
565
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1130
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1154
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1162
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
425
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
618
*is_supported = false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
631
*is_hw_init = false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
827
dmub->hw_init = false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
886
return false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv_stat.c
123
notify->pending_notification = false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv_stat.c
58
notify->pending_notification = false;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv_stat.c
67
notify->pending_notification = false;
sys/dev/pci/drm/amd/display/include/grph_object_id.h
311
return false;
sys/dev/pci/drm/amd/display/include/logger_interface.h
63
print_not_impl = false; \
sys/dev/pci/drm/amd/display/include/signal_types.h
117
return false;
sys/dev/pci/drm/amd/display/include/signal_types.h
130
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1063
bool use_eetf = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1064
bool is_clipped = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1072
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1187
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1578
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1682
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1685
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1836
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1924
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1927
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
416
ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
687
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
725
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
730
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
735
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
769
return false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
930
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_table.c
35
bool ret = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1033
in_out_vrr->supported = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1066
in_out_vrr->btr.btr_enabled = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1074
in_out_vrr->btr.btr_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1078
in_out_vrr->fixed.fixed_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1126
in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1180
if (in_out_vrr->supported == false)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1200
in_out_vrr->flip_interval.program_flip_interval_workaround = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1207
in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1253
in_out_vrr->fixed.ramping_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
257
in_out_vrr->fixed.ramping_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
270
in_out_vrr->fixed.ramping_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
311
in_out_vrr->btr.btr_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
450
bool update = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
466
in_out_vrr->fixed.fixed_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
519
in_vrr->flip_interval.flip_interval_workaround_active = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
560
return false;
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c
264
adj->disable == false) {
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c
265
display->adjust.disable = false;
sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c
142
bool stereo3dSupport = false;
sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c
455
bool hdmi_vic_mode = false;
sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c
460
info_packet->valid = false;
sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c
529
info_packet->valid = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
1026
return false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
699
bool result = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
703
return false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
708
fill_iram_v_2_3(&ram_table, params, false);
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
770
bool result = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
773
return false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
820
bool isPSRSUSupported = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
837
isPSRSUSupported = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
841
isPSRSUSupported = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
843
isPSRSUSupported = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
845
isPSRSUSupported = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
920
link->psr_settings.psr_frame_capture_indication_req = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
962
return false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
971
return false;
sys/dev/pci/drm/amd/include/amd_pcie_helpers.h
33
return false;
sys/dev/pci/drm/amd/include/amd_pcie_helpers.h
41
return false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1114
amdgpu_gfx_off_ctrl(adev, false);
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1620
bool cclk_dpm_supported = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1623
return false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1681
return false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1703
return false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
185
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
2079
bool support_temp_metrics = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
291
bool support_mode1_reset = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
319
bool support_link_reset = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
504
adev->pm.ac_power = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
601
adev->pm.dpm.uvd_active = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
636
adev->pm.dpm.vce_active = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
767
return false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
812
return false;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
112
bool runpm_check = runpm ? adev->in_runpm : false;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
155
ret = amdgpu_pm_dev_state_check(adev, false);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4497
return false;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4508
return false;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4526
return false;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
500
adev->pm.pp_force_state_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1050
table->entries[i].clk, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1109
table->entries[i].clk, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1258
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1351
ret = amdgpu_kv_smc_bapm_enable(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1383
err = amdgpu_kv_smc_bapm_enable(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1388
kv_enable_nb_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1391
kv_dpm_powergate_acp(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1392
kv_dpm_powergate_samu(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1398
kv_enable_smc_cac(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1399
kv_enable_didt(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1402
kv_enable_ulv(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1468
pi->uvd_power_gated = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1469
pi->vce_power_gated = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1470
pi->samu_power_gated = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1471
pi->acp_power_gated = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1579
kv_enable_vce_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1706
kv_enable_vce_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1736
kv_update_samu_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1759
kv_update_acp_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1864
pi->nb_dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1971
kv_freeze_sclk_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2020
kv_freeze_sclk_dpm(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2287
pi->battery_state = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2452
kv_dpm_power_level_enable(adev, i, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2588
pi->sys_info.nb_dpm_enable = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2808
pi->enable_didt = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2819
pi->caps_sclk_ds = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2822
pi->disable_nb_ps3_in_battery = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2824
pi->bapm_enable = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2828
pi->caps_sclk_throttle_low_notification = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2829
pi->caps_fps = false; /* true? */
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2830
pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2832
pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2833
pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2834
pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2835
pi->caps_stable_p_state = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3051
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3078
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3102
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3169
bool queue_thermal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3177
adev->pm.dpm.thermal.high_to_low = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3235
*equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3240
*equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3247
*equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
560
pi->cac_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
565
pi->cac_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
659
sclk, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
727
amdgpu_kv_smc_dpm_enable(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
919
table->entries[i].vclk, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
925
table->entries[i].dclk, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
987
table->entries[i].evclk, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
1007
adev->pm.dpm.thermal_active = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
337
adev->pm.dpm.power_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
781
single_display = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
900
bool equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
938
equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1150
false
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1708
false
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1995
bool update_dte_from_pl2 = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2160
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2161
ni_pi->enable_cac = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2162
ni_pi->enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2163
si_pi->enable_dte = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2187
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2192
si_pi->dyn_powertune_data.disable_uvd_powertune = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2277
false, /* ??? */
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2382
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2411
if (ni_pi->enable_power_containment == false)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2505
enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2508
enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2511
enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2514
enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2517
enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2559
ni_pi->pc_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2568
ni_pi->pc_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2586
si_pi->enable_dte = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2588
if (si_pi->enable_dte == false)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2596
si_pi->enable_dte = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2772
if (ni_pi->enable_cac == false)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2838
ni_pi->enable_cac = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2839
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2892
if ((ni_pi->enable_cac == false) ||
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2893
(ni_pi->cac_configuration_required == false))
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2924
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2930
ni_pi->cac_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2947
ni_pi->cac_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3020
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3093
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3407
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3439
pi->dynamic_ss = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3450
bool disable_mclk_switching = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3451
bool disable_sclk_switching = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3553
if (adev->pm.ac_power == false) {
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3697
ps->dc_compatible = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3725
bool ret = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
376
false
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3806
want_thermal_protection = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3994
amdgpu_si_smc_clock(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4378
bool strobe_mode = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4400
amdgpu_si_smc_clock(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4412
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4419
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4424
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4427
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4521
pi->mvdd_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4526
pi->mvdd_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4540
si_pi->vddc_phase_shed_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4544
si_pi->vddc_phase_shed_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4615
si_pi->vddc_phase_shed_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4665
bool voltage_found = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5346
engine_clock, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5564
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5566
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5568
dll_state_on = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5574
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5692
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5701
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5706
return false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5747
eg_pi->uvd_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5796
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5800
ni_pi->enable_sq_ramping = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5997
result = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6279
si_pi->pspp_notify_required = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6284
if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6291
if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6326
amdgpu_acpi_pcie_performance_request(adev, request, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6522
si_pi->fan_ctrl_is_in_default_mode = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6546
adev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6553
adev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
658
false
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6597
adev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6625
si_pi->fan_is_controlled_by_smc = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6884
eg_pi->dynamic_ac_timing = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6962
ret = si_notify_smc_display_change(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6982
ret = si_thermal_enable_alert(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7006
si_enable_thermal_protection(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7007
si_enable_power_containment(adev, boot_ps, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7008
si_enable_smc_cac(adev, boot_ps, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7009
si_enable_spread_spectrum(adev, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7010
si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7094
ret = si_enable_power_containment(adev, new_ps, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7099
ret = si_enable_smc_cac(adev, new_ps, false);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7271
si_pi->ulv.supported = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7273
si_pi->ulv.one_pcie_lane_in_ulv = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7468
0, false, ÷rs);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7474
eg_pi->smu_uvd_hs = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7523
si_pi->sclk_deep_sleep_above_low = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7528
pi->thermal_protection = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7537
eg_pi->pcie_performance_request = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7650
bool queue_thermal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7658
adev->pm.dpm.thermal.high_to_low = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7845
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7871
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7896
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
8037
*equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
8042
*equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
8049
*equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
167
return false;
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1371
return false;
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1375
return false;
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
249
return false;
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
365
hwmgr->en_umd_pstate = false;
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
685
ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
116
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
39
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
76
ret = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
95
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
269
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
272
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
275
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
106
hwmgr->od_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
111
hwmgr->od_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
126
hwmgr->od_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
181
hwmgr->od_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
222
? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
229
hwmgr->pm_en = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
338
ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
378
ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
93
hwmgr->gfxoff_state_changed_by_workload = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_psm.c
263
equal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
564
"Could not find Voltage Table in BIOS.", return false;);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
640
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
674
bool bRet = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
679
"Could not find GPIO lookup Table in BIOS.", return false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
832
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
154
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
87
return false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
90
voltage_type, voltage_mode)) ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
771
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
689
ps->classification.temporary_state = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
690
ps->classification.to_be_deleted = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
705
ps->display.disableFrameModulation = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
720
ps->display.limitRefreshrate = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
722
ps->display.limitRefreshrate = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1174
bool latency_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1313
has_gfx_busy = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1379
smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1420
smu10_data->vcn_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1491
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1512
smu10_gfx_off_control(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1522
hwmgr->gfxoff_state_changed_by_workload = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
323
smu10_data->cc6_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
324
smu10_data->pstate_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
325
smu10_data->cc6_setting_changed = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
345
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
105
data->uvd_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
106
data->vce_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
137
smu7_update_uvd_dpm(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
165
smu7_update_vce_dpm(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1132
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1139
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1155
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1387
protection = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1725
smu7_avfs_control(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1727
smu7_avfs_control(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1766
tmp_result = smu7_avfs_control(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1810
data->dll_default_on = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1824
data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1825
data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1834
data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1964
data->disable_edc_leakage_controller = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1977
data->enable_tdc_limit_feature = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1978
data->enable_pkg_pwr_tracking_feature = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3000
data->is_tlu_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3309
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3332
bool latency_allowed = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3340
data->mclk_ignore_signal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3399
disable_mclk_switching = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3454
data->mclk_ignore_signal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3620
power_state->classification.temporary_state = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3621
power_state->classification.to_be_deleted = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3629
power_state->display.disableFrameModulation = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3630
power_state->display.limitRefreshrate = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4182
data->pspp_notify_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4188
if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4195
if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4309
dpm_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4431
if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4553
data->apply_optimized_settings = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4684
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4731
*equal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4738
*equal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4768
data->need_long_memory_training = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4871
data->uvd_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4872
data->vce_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5350
valid_entry = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5465
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5474
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5482
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5485
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
1070
result = smu7_enable_didt(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
1120
data->cac_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
117
hwmgr->fan_ctrl_is_in_default_mode = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
194
hwmgr->fan_ctrl_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1107
smu8_nbdpm_pstate_enable_disable(hwmgr, false, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1109
smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1471
hw_data->cc6_settings.cc6_setting_changed = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1930
smu8_enable_disable_uvd_dpm(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
2002
smu8_dpm_update_uvd_dpm(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
2024
smu8_enable_disable_vce_dpm(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
2029
data->vce_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
225
data->cc6_settings.cpu_cc6_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
226
data->cc6_settings.cpu_pstate_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
227
data->cc6_settings.nb_pstate_switch_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
673
data->uvd_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
674
data->vce_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
675
data->samu_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
677
data->acp_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
838
data->is_nb_dpm_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
875
disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
876
enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
879
smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
934
hw_data->disp_clk_bypass_pending = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
935
hw_data->disp_clk_bypass = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
942
hw_data->is_nb_dpm_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
949
hw_data->cc6_settings.cc6_setting_changed = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
951
hw_data->cc6_settings.cpu_cc6_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
952
hw_data->cc6_settings.cpu_pstate_disable = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
208
bool found = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
225
found = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
356
dpm_table->dpm_level[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
1027
bool found = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
1043
found = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
120
hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
122
hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
124
hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
126
hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
129
hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
138
hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
141
hwmgr->feature_mask & PP_ULV_MASK ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
144
hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
153
hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2353
data->smu_features[GNLD_AVFS].supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2389
data->smu_features[GNLD_ACG].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2402
if (!vega10_enable_smc_features(hwmgr, false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2404
data->smu_features[GNLD_ACG].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2462
false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2466
data->smu_features[GNLD_AVFS].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2478
vega10_avfs_enable(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2480
vega10_avfs_enable(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2519
AVFSFUSETABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2692
data->vbios_boot_state.bsoc_vddc_lock = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2721
result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2764
false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2768
data->smu_features[GNLD_THERMAL].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2823
false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2826
data->smu_features[GNLD_ULV].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2877
false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2880
data->smu_features[GNLD_DS_GFXCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2885
false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2888
data->smu_features[GNLD_DS_SOCCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2893
false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2896
data->smu_features[GNLD_DS_LCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2901
false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2904
data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2920
false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2922
data->smu_features[GNLD_LED_DISPLAY].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2931
data->smu_features[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2937
return vega10_enable_smc_features(hwmgr, false, feature_mask);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2969
data->smu_features[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2984
data->vbios_boot_state.bsoc_vddc_lock = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2999
false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3001
data->smu_features[GNLD_DPM_LINK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3002
data->smu_features[GNLD_DPM_LINK].supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3170
power_state->classification.temporary_state = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3171
power_state->classification.to_be_deleted = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3177
power_state->display.disableFrameModulation = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3178
power_state->display.limitRefreshrate = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3370
disable_mclk_switching = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3535
dpm_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3552
dpm_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3554
dpm_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
370
data->smu_features[i].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
371
data->smu_features[i].supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3862
result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4113
vega10_notify_smc_display_change(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4384
if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4650
ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4976
result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5050
*equal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5060
*equal = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5079
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5110
tmp_result = vega10_avfs_enable(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5130
vega10_enable_disable_PCC_limit_feature(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5429
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5439
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5448
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5451
return false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5740
data->smu_features[GNLD_ULV].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5741
data->smu_features[GNLD_DS_GFXCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5742
data->smu_features[GNLD_DS_SOCCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5743
data->smu_features[GNLD_DS_LCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5744
data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
865
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
913
data->is_tlu_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1035
vega10_didt_set_mask(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1094
vega10_didt_set_mask(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1125
vega10_didt_set_mask(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1228
result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1230
data->smu_features[GNLD_DIDT].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1307
data->smu_features[GNLD_PPT].supported = false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1313
data->smu_features[GNLD_TDC].supported = false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1331
false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1333
data->smu_features[GNLD_PPT].supported = false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1337
false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1339
data->smu_features[GNLD_TDC].supported = false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
927
vega10_didt_set_mask(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
980
vega10_didt_set_mask(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
314
bool is_acg_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
682
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
137
hwmgr->fan_ctrl_is_in_default_mode = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
203
hwmgr, false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
208
data->smu_features[GNLD_FAN_CONTROL].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
474
false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
478
data->smu_features[GNLD_FW_CTF].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
556
PPTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
581
PPTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1350
vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1373
vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1418
ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1469
ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1517
ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1526
ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1626
vega12_notify_smc_display_change(hwmgr, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1819
if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2220
ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2362
bool vblank_too_short = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2568
(uint8_t *)wm_table, TABLE_WATERMARKS, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2626
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
363
false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
415
data->avfs_exist = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
428
data->is_tlu_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
455
data->gfxoff_controlled_by_driver = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
567
false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
572
data->smu_features[GNLD_DPM_LINK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
573
data->smu_features[GNLD_DPM_LINK].supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
852
(uint8_t *)pp_table, TABLE_PPTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
911
data->uvd_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
914
data->vce_power_gated = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
932
enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
958
enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
47
fan_speed_info->supports_percent_read = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
48
fan_speed_info->supports_percent_write = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
93
hwmgr, false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
98
data->smu_features[GNLD_FAN_CONTROL].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
1135
hwmgr->od_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
1392
ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
1468
ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
171
data->gfxoff_allowed = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2075
ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2101
ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2149
ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2194
ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2224
ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2249
ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2258
ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2774
if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3135
data->gfxclk_overdrive = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3136
data->memclk_overdrive = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3149
TABLE_OVERDRIVE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3156
data->gfxclk_overdrive = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3165
data->memclk_overdrive = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3300
ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3318
true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3661
(uint8_t *)wm_table, TABLE_WATERMARKS, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3743
bool vblank_too_short = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3826
disable_fclk_switching = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3920
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
403
false : true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
459
data->avfs_exist = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
471
data->is_tlu_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
484
data->is_custom_profile_set = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
826
(uint8_t *)pp_table, TABLE_PPTABLE, false);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
913
false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
918
data->smu_features[GNLD_DPM_LINK].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
919
data->smu_features[GNLD_DPM_LINK].supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
990
true : false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
119
bool od_supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
39
hwmgr, false,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
45
data->smu_features[GNLD_FAN_CONTROL].enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2375
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2534
result = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
552
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
769
bool vol_found = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
961
data->ulv_supported = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1191
mem_level->StutterEnable = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1411
table->MemoryACPILevel.StutterEnable = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
149
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1732
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1831
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2452
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
301
hwmgr->avfs_supported = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
323
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
330
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
613
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
700
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
706
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
711
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
715
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
722
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
728
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
734
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
740
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
747
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2285
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2461
result = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
345
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
409
PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
446
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
452
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
458
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
464
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
469
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
473
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
480
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
486
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
492
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
499
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
535
bool vol_found = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
728
data->ulv_supported = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1185
mem_level->StutterEnable = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1348
table->MemoryACPILevel.StutterEnable = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1699
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1729
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
239
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2498
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
332
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
531
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
615
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
620
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
625
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
629
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
635
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
640
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
645
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
650
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
657
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
425
TASK_TYPE_UCODE_SAVE, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
443
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
445
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
447
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
449
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
453
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
456
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
459
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
464
TASK_TYPE_UCODE_LOAD, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
468
TASK_TYPE_UCODE_LOAD, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
496
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
499
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
501
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
503
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
505
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
507
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
510
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
885
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
892
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
50
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c
230
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1661
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1920
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2006
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2012
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2017
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2022
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2028
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2034
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2041
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2048
false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2056
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2764
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2923
result = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
158
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
191
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
61
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
615
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1010
mem_level->StutterEnable = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1178
table->MemoryACPILevel.StutterEnable = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
139
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1535
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1558
return false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1683
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1709
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1771
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1855
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1860
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1865
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1869
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1875
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1880
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1885
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1890
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1898
PP_ASSERT_WITH_CODE(false,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
231
bool error = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
1333
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
157
false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
1595
smu->wbrf_supported = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
1925
smu->pm_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2082
ret = smu_system_features_control(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2092
ret = smu_notify_rlc_state(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2157
smu_dpm_set_vcn_enable(smu, false, i);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2160
smu_dpm_set_jpeg_enable(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2162
smu_dpm_set_umsch_mm_enable(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2167
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2226
adev->pm.dpm_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2234
smu_set_gfx_cgpg(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2351
smu_gpo_control(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2352
smu_gfx_ulv_control(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2353
smu_deep_sleep_control(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2361
amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
243
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2476
ret = smu_adjust_power_state_dynamic(smu, level, false);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3269
bool custom = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3516
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3519
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3551
bool ret = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3554
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3565
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3917
bool ret = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3920
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
593
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
599
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
607
return false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
671
smu->uploading_custom_pp_table = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
754
smu->od_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
804
smu->is_apu = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
806
smu->smu_baco.platform_support = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
807
smu->smu_baco.maco_support = false;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1694
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1031
false,
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1407
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1465
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1598
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1887
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
465
false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
647
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
137
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
367
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
371
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1694
ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1881
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1954
(void *)(&activity_monitor), false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2021
(void *)(&activity_monitor), false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2587
ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
272
is_secure = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2735
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2817
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2823
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2906
uint8_t umc_fw_greater_than_v136 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2907
uint8_t umc_fw_disable_cdr = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
379
false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
566
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
652
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
741
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
827
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1470
ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1583
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1652
(void *)(&activity_monitor_external), false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1722
(void *)(&activity_monitor_external), false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2226
0, (void *)boot_od_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2242
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2426
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2521
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2524
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2689
bool use_metrics_v2 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2690
bool use_metrics_v3 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2859
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
375
false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
391
smu_baco->platform_support = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
741
bool use_metrics_v2 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
742
bool use_metrics_v3 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
773
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1456
adev->pm.ac_power = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1875
bool auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1928
auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1293
ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1329
ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1348
ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1356
ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1364
ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1372
ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1403
ret = vangogh_force_dpm_limit_value(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2159
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
282
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
351
false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
517
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
522
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
578
bool cur_value_match_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
582
ret = smu_cmn_get_metrics_table(smu, &metrics, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
679
bool cur_value_match_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
684
ret = smu_cmn_get_metrics_table(smu, &metrics, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
887
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
1197
false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
1364
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
500
bool cur_value_match_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
504
ret = smu_cmn_get_metrics_table(smu, &metrics, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
707
ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
740
ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
894
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
902
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
944
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk, sclk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
947
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk, socclk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
950
ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_FCLK, fclk, fclk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
971
ret = renoir_force_dpm_limit_value(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
205
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1061
false,
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1392
min, max, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1412
ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1487
smu, SMU_GFXCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1509
return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1526
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1775
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1876
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
2018
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
2021
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
675
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1317
adev->pm.ac_power = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1611
bool auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1685
auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2251
adev->gfx.is_poweron = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2359
smu_table->clocks_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1164
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1972
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2054
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2244
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2376
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2532
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2587
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2707
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2712
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2715
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
3046
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
3079
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
370
smu->od_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
716
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
751
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
363
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
584
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
219
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
309
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
1055
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
1068
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
1078
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
237
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
267
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
510
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
956
ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1274
ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1663
smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2079
smu, SMU_UCLK, 0, uclk_table->max, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2146
smu, SMU_UCLK, 0, max, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2286
smu, SMU_GFXCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2294
smu, SMU_UCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2318
smu, SMU_GFXCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2329
smu, SMU_UCLK, min_clk, max_clk, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2365
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2659
ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2760
ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3144
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3194
ret = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3477
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3542
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3545
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3557
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3665
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1153
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1961
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2043
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2225
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2488
(void *)(&activity_monitor_external[i]), false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2540
(void *)(&activity_monitor_external), false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2656
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
363
smu->od_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
714
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
743
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1140
ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1263
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1276
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1286
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1296
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1306
false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
264
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
344
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
641
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1273
bool auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1866
smu_table->clocks_table, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1290
ret = smu_v14_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1439
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1452
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1462
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1472
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1482
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1492
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1502
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
266
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
477
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1449
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1649
ret = smu_cmn_get_metrics_table(smu, NULL, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1787
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1842
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1899
smu_v14_0_deep_sleep_control(smu, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2330
false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2367
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2797
smu->user_dpm_profile.user_od = false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
342
smu->od_enabled = false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
646
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
675
false);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1043
false);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1065
false);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1099
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1113
snd_driver_loaded = pci_is_enabled(p) ? true : false;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
290
*poll = false;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
454
poll = false;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
682
return false;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
877
false);
sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h
100
#define smu_is_asic_wbrf_supported(smu) smu_ppt_funcs(is_asic_wbrf_supported, false, smu)
sys/dev/pci/drm/apple/afk.c
306
service->enabled = false;
sys/dev/pci/drm/apple/afk.c
547
return false;
sys/dev/pci/drm/apple/afk.c
555
return false;
sys/dev/pci/drm/apple/afk.c
561
return false;
sys/dev/pci/drm/apple/afk.c
574
return false;
sys/dev/pci/drm/apple/afk.c
593
return false;
sys/dev/pci/drm/apple/afk.c
603
return false;
sys/dev/pci/drm/apple/afk.c
889
service->cmds[idx].free_on_ack = false;
sys/dev/pci/drm/apple/afk.c
890
service->cmds[idx].done = false;
sys/dev/pci/drm/apple/apple_drv.c
361
connector->connected = false;
sys/dev/pci/drm/apple/dcp.c
313
dcp->dptxport[port].connected = false;
sys/dev/pci/drm/apple/dcp.c
376
dptxport_set_hpd(dcp->dptxport[0].service, false);
sys/dev/pci/drm/apple/dptxep.c
352
bool phy_set_rate = false;
sys/dev/pci/drm/apple/dptxep.c
389
phy_set_rate = false;
sys/dev/pci/drm/apple/iomfb.c
558
dcp->active = false;
sys/dev/pci/drm/apple/iomfb.c
559
dcp->valid_mode = false;
sys/dev/pci/drm/apple/iomfb_template.c
1015
dcp->valid_mode = false;
sys/dev/pci/drm/apple/iomfb_template.c
1023
dcp->valid_mode = false;
sys/dev/pci/drm/apple/iomfb_template.c
112
return false;
sys/dev/pci/drm/apple/iomfb_template.c
1147
dcp_swap_submit(dcp, false, &DCP_FW_UNION(dcp->swap), dcp_swapped, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
1156
dcp_swap_start(dcp, false, &start_req, dcp_swap_started, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
1223
dcp_set_digital_out_mode(dcp, false, &dcp->mode,
sys/dev/pci/drm/apple/iomfb_template.c
1235
dcp->during_modeset = false;
sys/dev/pci/drm/apple/iomfb_template.c
1294
bool is_premultiplied = false;
sys/dev/pci/drm/apple/iomfb_template.c
1329
req->surf_null[l] = false;
sys/dev/pci/drm/apple/iomfb_template.c
139
iomfb_a358_vi_set_temperature_hint(dcp, false,
sys/dev/pci/drm/apple/iomfb_template.c
1400
dcp->brightness.update = false;
sys/dev/pci/drm/apple/iomfb_template.c
1418
iomfb_set_matrix(dcp, false, &mat, do_swap, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
144
return false;
sys/dev/pci/drm/apple/iomfb_template.c
1443
dcp_is_main_display(dcp, false, res_is_main_display, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
1448
dcp_first_client_open(dcp, false, init_3, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
1454
dcp_enable_disable_video_power_savings(dcp, false, &val, init_2, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
1466
iomfb_get_color_remap_mode(dcp, false, &color_remap, init_1, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
1475
dcp_set_power_state(dcp, false, &req, NULL, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
162
iomfb_a131_pmu_service_matched(dcp, false, complete_pmu_service_matched,
sys/dev/pci/drm/apple/iomfb_template.c
166
return false;
sys/dev/pci/drm/apple/iomfb_template.c
190
iomfb_a132_backlight_service_matched(dcp, false, complete_backlight_service_matched, out);
sys/dev/pci/drm/apple/iomfb_template.c
193
return false;
sys/dev/pci/drm/apple/iomfb_template.c
414
return false;
sys/dev/pci/drm/apple/iomfb_template.c
508
return false;
sys/dev/pci/drm/apple/iomfb_template.c
516
return false;
sys/dev/pci/drm/apple/iomfb_template.c
527
return false;
sys/dev/pci/drm/apple/iomfb_template.c
532
return false;
sys/dev/pci/drm/apple/iomfb_template.c
547
return false;
sys/dev/pci/drm/apple/iomfb_template.c
557
return false;
sys/dev/pci/drm/apple/iomfb_template.c
569
return false;
sys/dev/pci/drm/apple/iomfb_template.c
579
return false;
sys/dev/pci/drm/apple/iomfb_template.c
613
dcp_set_display_refresh_properties(dcp, false, boot_done, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
620
dcp_late_init_signal(dcp, false, &v_true, boot_5, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
622
dcp_late_init_signal(dcp, false, boot_5, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
630
dcp_flush_supports_power(dcp, false, &v_true, boot_4, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
635
dcp_setup_video_limits(dcp, false, boot_3, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
640
dcp_create_default_fb(dcp, false, boot_2, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
647
dcp_set_create_dfb(dcp, false, boot_1_5, NULL);
sys/dev/pci/drm/apple/iomfb_template.c
648
return false;
sys/dev/pci/drm/apple/iomfb_template.c
757
dcp_swap_submit(dcp, false, &DCP_FW_UNION(dcp->swap), dcp_swap_cleared, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
776
dcp_set_power_state(dcp, false, &req, dcp_on_final, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
791
dcp_set_parameter_dcp(dcp, false, ¶m, dcp_on_set_power_state, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
812
dcp_set_display_device(dcp, false, &handle, dcp_on_set_power_state,
sys/dev/pci/drm/apple/iomfb_template.c
816
dcp_set_display_device(dcp, false, &handle,
sys/dev/pci/drm/apple/iomfb_template.c
846
dcp_set_power_state(dcp, false, &power_req, complete_set_powerstate,
sys/dev/pci/drm/apple/iomfb_template.c
853
iomfb_last_client_close(dcp, false, &last_client_req,
sys/dev/pci/drm/apple/iomfb_template.c
907
dcp_swap_start(dcp, false, &swap_req, dcp_swap_clear_started, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
927
iomfb_abort_swaps_dcp(dcp, false, &abort_req,
sys/dev/pci/drm/apple/iomfb_template.c
949
dcp_set_power_state(dcp, false, &power_req, complete_set_powerstate, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
955
iomfb_last_client_close(dcp, false, &req, last_client_closed_sleep, cookie);
sys/dev/pci/drm/apple/iomfb_template.c
977
iomfb_abort_swaps_dcp(dcp, false, &req, aborted_swaps_dcp_sleep,
sys/dev/pci/drm/apple/iomfb_v12_3.c
104
dcp_start_signal(dcp, false, dcp_started, NULL);
sys/dev/pci/drm/apple/iomfb_v13_3.c
109
dcp_start_signal(dcp, false, dcp_started, NULL);
sys/dev/pci/drm/apple/parser.c
1008
bool type_match = false;
sys/dev/pci/drm/apple/parser.c
140
return false;
sys/dev/pci/drm/apple/parser.c
144
return false;
sys/dev/pci/drm/apple/parser.c
149
return false;
sys/dev/pci/drm/apple/parser.c
249
for (iterator_begin(handle, &it, false); it.idx < it.len; ++it.idx)
sys/dev/pci/drm/apple/parser.c
436
bool is_virtual = false;
sys/dev/pci/drm/apple/parser.c
567
ret = iterator_begin(handle, &it, false);
sys/dev/pci/drm/apple/parser.c
640
bool parsed_unit = false;
sys/dev/pci/drm/apple/parser.c
641
bool parsed_name = false;
sys/dev/pci/drm/apple/parser.c
642
bool parsed_class = false;
sys/dev/pci/drm/clients/drm_fbdev_client.c
82
drm_fb_helper_set_suspend(fb_helper, false);
sys/dev/pci/drm/clients/drm_fbdev_client.c
84
drm_fb_helper_set_suspend_unlocked(fb_helper, false);
sys/dev/pci/drm/clients/drm_log.c
317
dlog->probed = false;
sys/dev/pci/drm/display/drm_dp_helper.c
101
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
105
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1091
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1098
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1104
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1126
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1133
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1140
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1147
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1155
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1162
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
120
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1504
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1507
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1514
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1518
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1535
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1538
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1543
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1547
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1567
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1570
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1575
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
1579
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
175
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
180
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
196
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
2314
drm_crtc_add_crc_entry(crtc, false, 0, crcs);
sys/dev/pci/drm/display/drm_dp_helper.c
2539
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
sys/dev/pci/drm/display/drm_dp_helper.c
2541
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
sys/dev/pci/drm/display/drm_dp_helper.c
2543
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
sys/dev/pci/drm/display/drm_dp_helper.c
2549
{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
sys/dev/pci/drm/display/drm_dp_helper.c
2551
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
sys/dev/pci/drm/display/drm_dp_helper.c
3002
if (drm_dp_lttpr_set_transparent_mode(aux, false)) {
sys/dev/pci/drm/display/drm_dp_helper.c
3342
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
3348
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
3367
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
3371
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
352
return __read_delay(aux, dpcd, dp_phy, uhbr, false);
sys/dev/pci/drm/display/drm_dp_helper.c
3523
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
3528
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
3668
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
3762
return false;
sys/dev/pci/drm/display/drm_dp_helper.c
4123
ret = drm_edp_backlight_set_enable(aux, bl, false);
sys/dev/pci/drm/display/drm_dp_helper.c
4384
bl->enabled = false;
sys/dev/pci/drm/display/drm_dp_helper.c
4449
¤t_level, ¤t_mode, false);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1047
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1077
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1108
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1132
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1150
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1242
req.u.enc_status.valid_stream_event = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1244
req.u.enc_status.valid_stream_behavior = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2063
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2367
bool created = false, send_link_addr = false, changed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2492
bool dowork = false, create_connector = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2506
mstb->link_address_sent = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2516
mstb->link_address_sent = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2539
dowork = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2640
bool changed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2725
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2876
ret = process_single_tx_qlock(mgr, txmsg, false);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2934
bool changed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3001
mstb->link_address_sent = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
312
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
316
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
321
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
333
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3386
bool send_remove = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3708
mgr->payload_id_table_cleared = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3728
mstb->link_address_sent = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3895
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3899
if (ret == false) {
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3901
1, replyblock, len, false);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3903
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3911
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3917
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3924
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3936
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3942
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3976
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3985
if (!drm_dp_get_one_sb_msg(mgr, false, &mstb))
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4047
bool probing_done = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4068
bool hotplug = false, dowork = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4086
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4112
bool send_hotplug = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4176
false);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4214
mgr->reset_rx_state = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4247
*handled = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4294
kick = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4560
update_payload = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4894
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5048
bool wake_tx = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5080
bool send_hotplug = false, go_again;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5088
go_again = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5209
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5218
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5223
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5231
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5234
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5277
bool found = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
543
bool failed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5780
drm_dp_mst_topology_mgr_set_mst(mgr, false);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5808
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5813
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5827
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
6032
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
6059
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
764
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
773
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
801
msg->chunk, msg->curchunk_len, false);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
860
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
881
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
896
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
915
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
939
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
962
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
981
return false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
994
return false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1017
err = set_bw_alloc_mode(tunnel, false);
sys/dev/pci/drm/display/drm_dp_tunnel.c
1245
bool changed = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1588
return false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
280
return false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
361
group->active = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
463
return false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
562
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
568
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
577
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
585
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
592
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
599
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
610
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
634
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
645
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
657
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
673
ret = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
704
bool changed = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
975
set_bw_alloc_mode(tunnel, false);
sys/dev/pci/drm/display/drm_hdmi_cec_helper.c
64
cec_s_phys_addr(data->adapter, addr, false);
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
1110
infoframe->set = false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
1130
drm_connector_hdmi_audio_plugged_notify(connector, false);
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
367
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
373
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
399
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
405
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
411
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
416
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
436
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
441
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
453
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
458
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
463
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
468
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
473
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
485
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
490
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
508
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
513
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
518
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
527
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
592
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
600
return false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
688
infoframe->set = false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
719
infoframe->set = false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
743
infoframe->set = false;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
772
infoframe->set = false;
sys/dev/pci/drm/display/drm_scdc_helper.c
164
return false;
sys/dev/pci/drm/display/drm_scdc_helper.c
194
return false;
sys/dev/pci/drm/display/drm_scdc_helper.c
207
return false;
sys/dev/pci/drm/display/drm_scdc_helper.c
254
return false;
sys/dev/pci/drm/display/drm_scdc_helper.c
267
return false;
sys/dev/pci/drm/dma-resv.c
448
cursor->is_restarted = false;
sys/dev/pci/drm/dma-resv.c
499
cursor->is_restarted = false;
sys/dev/pci/drm/dma-resv.c
664
1, false);
sys/dev/pci/drm/dma-resv.c
758
return false;
sys/dev/pci/drm/drm_atomic.c
1596
return config->funcs->atomic_commit(state->dev, state, false);
sys/dev/pci/drm/drm_atomic.c
1714
new_crtc_state->active = false;
sys/dev/pci/drm/drm_atomic.c
1747
crtc_state->active = false;
sys/dev/pci/drm/drm_atomic.c
1915
__drm_state_dump(dev, p, false);
sys/dev/pci/drm/drm_atomic.c
576
return false;
sys/dev/pci/drm/drm_atomic.c
579
return false;
sys/dev/pci/drm/drm_atomic_helper.c
2061
drm_atomic_helper_wait_for_fences(dev, state, false);
sys/dev/pci/drm/drm_atomic_helper.c
210
crtc_state->active = false;
sys/dev/pci/drm/drm_atomic_helper.c
2173
ret = funcs->atomic_async_check(plane, state, false);
sys/dev/pci/drm/drm_atomic_helper.c
3571
crtc_state->active = false;
sys/dev/pci/drm/drm_atomic_helper.c
3938
state->allow_modeset = false;
sys/dev/pci/drm/drm_atomic_helper.c
704
new_crtc_state->no_vblank = false;
sys/dev/pci/drm/drm_atomic_helper.c
709
ret = handle_conflicting_encoders(state, false);
sys/dev/pci/drm/drm_atomic_helper.c
918
plane_state->visible = false;
sys/dev/pci/drm/drm_atomic_helper.c
924
plane_state->visible = false;
sys/dev/pci/drm/drm_atomic_helper.c
943
drm_rect_debug_print("dst: ", &plane_state->dst, false);
sys/dev/pci/drm/drm_atomic_helper.c
967
drm_rect_debug_print("dst: ", dst, false);
sys/dev/pci/drm/drm_atomic_helper.c
968
drm_rect_debug_print("clip: ", &clip, false);
sys/dev/pci/drm/drm_atomic_state_helper.c
147
state->mode_changed = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
148
state->active_changed = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
149
state->planes_changed = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
150
state->connectors_changed = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
151
state->color_mgmt_changed = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
152
state->zpos_changed = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
155
state->async_flip = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
159
state->self_refresh_active = false;
sys/dev/pci/drm/drm_atomic_state_helper.c
356
state->color_mgmt_changed = false;
sys/dev/pci/drm/drm_atomic_uapi.c
100
state->enable = false;
sys/dev/pci/drm/drm_atomic_uapi.c
1419
bool async_flip = false;
sys/dev/pci/drm/drm_atomic_uapi.c
165
state->enable = false;
sys/dev/pci/drm/drm_atomic_uapi.c
374
bool replaced = false;
sys/dev/pci/drm/drm_atomic_uapi.c
479
bool replaced = false;
sys/dev/pci/drm/drm_atomic_uapi.c
677
bool replaced = false;
sys/dev/pci/drm/drm_atomic_uapi.c
953
bool active = false;
sys/dev/pci/drm/drm_auth.c
281
drm_set_master(dev, file_priv, false);
sys/dev/pci/drm/drm_auth.c
444
return false;
sys/dev/pci/drm/drm_buddy.c
551
__drm_buddy_free(mm, block, false);
sys/dev/pci/drm/drm_buddy.c
583
__drm_buddy_free_list(mm, objects, false, false);
sys/dev/pci/drm/drm_buddy.c
698
__drm_buddy_free(mm, block, false);
sys/dev/pci/drm/drm_buddy.c
709
bool fallback = false;
sys/dev/pci/drm/drm_buddy.c
808
__drm_buddy_free(mm, block, false);
sys/dev/pci/drm/drm_buddy.c
894
__drm_buddy_free(mm, block, false);
sys/dev/pci/drm/drm_cache.c
182
return false;
sys/dev/pci/drm/drm_client_event.c
167
client->suspended = false;
sys/dev/pci/drm/drm_client_event.c
69
client->hotplug_pending = false;
sys/dev/pci/drm/drm_client_modeset.c
1032
return false;
sys/dev/pci/drm/drm_client_modeset.c
1038
return false;
sys/dev/pci/drm/drm_client_modeset.c
1107
crtc_state->active = false;
sys/dev/pci/drm/drm_client_modeset.c
1217
ret = drm_client_modeset_commit_atomic(client, true, false);
sys/dev/pci/drm/drm_client_modeset.c
1296
ret = drm_client_modeset_commit_atomic(client, mode == DRM_MODE_DPMS_ON, false);
sys/dev/pci/drm/drm_client_modeset.c
191
if (cmdline_mode->specified == false)
sys/dev/pci/drm/drm_client_modeset.c
223
prefer_non_interlace = false;
sys/dev/pci/drm/drm_client_modeset.c
235
return false;
sys/dev/pci/drm/drm_client_modeset.c
249
bool any_enabled = false;
sys/dev/pci/drm/drm_client_modeset.c
268
enabled[i] = drm_connector_enabled(connectors[i], false);
sys/dev/pci/drm/drm_client_modeset.c
298
bool can_clone = false;
sys/dev/pci/drm/drm_client_modeset.c
303
return false;
sys/dev/pci/drm/drm_client_modeset.c
313
return false;
sys/dev/pci/drm/drm_client_modeset.c
326
can_clone = false;
sys/dev/pci/drm/drm_client_modeset.c
337
can_clone = false;
sys/dev/pci/drm/drm_client_modeset.c
348
dmt_mode = drm_mode_find_dmt(dev, 1024, 768, 60, false);
sys/dev/pci/drm/drm_client_modeset.c
368
can_clone = false;
sys/dev/pci/drm/drm_client_modeset.c
378
return false;
sys/dev/pci/drm/drm_client_modeset.c
444
if (enabled[i] == false) {
sys/dev/pci/drm/drm_client_modeset.c
541
return false;
sys/dev/pci/drm/drm_client_modeset.c
639
return false;
sys/dev/pci/drm/drm_client_modeset.c
642
return false;
sys/dev/pci/drm/drm_client_modeset.c
646
return false;
sys/dev/pci/drm/drm_client_modeset.c
689
enabled[i] = false;
sys/dev/pci/drm/drm_client_modeset.c
700
enabled[i] = false;
sys/dev/pci/drm/drm_client_modeset.c
762
fallback = false;
sys/dev/pci/drm/drm_client_modeset.c
795
ret = false;
sys/dev/pci/drm/drm_client_modeset.c
979
return false;
sys/dev/pci/drm/drm_color_mgmt.c
250
return false;
sys/dev/pci/drm/drm_color_mgmt.c
299
use_gamma_lut = false;
sys/dev/pci/drm/drm_connector.c
241
false, drm_connector_free);
sys/dev/pci/drm/drm_connector.c
2956
return false;
sys/dev/pci/drm/drm_connector.c
3241
drm_connector_update_privacy_screen_properties(connector, false);
sys/dev/pci/drm/drm_connector.c
3305
return false;
sys/dev/pci/drm/drm_connector.c
3322
return false;
sys/dev/pci/drm/drm_connector.c
3415
mode->expose_to_userspace = false;
sys/dev/pci/drm/drm_connector.c
3433
mode->expose_to_userspace = false;
sys/dev/pci/drm/drm_connector.c
3444
mode->expose_to_userspace = false;
sys/dev/pci/drm/drm_crtc.c
957
return false;
sys/dev/pci/drm/drm_crtc_helper.c
1002
if (ret == false)
sys/dev/pci/drm/drm_crtc_helper.c
133
return false;
sys/dev/pci/drm/drm_crtc_helper.c
165
return false;
sys/dev/pci/drm/drm_crtc_helper.c
309
return false;
sys/dev/pci/drm/drm_crtc_helper.c
558
bool mode_changed = false; /* if true do a full mode set */
sys/dev/pci/drm/drm_crtc_helper.c
559
bool fb_changed = false; /* if true and !mode_changed just do a flip */
sys/dev/pci/drm/drm_crtc_internal.h
326
static inline bool drm_panic_is_enabled(struct drm_device *dev) { return false; }
sys/dev/pci/drm/drm_damage_helper.c
275
bool ret = false;
sys/dev/pci/drm/drm_damage_helper.c
279
iter->full_update = false;
sys/dev/pci/drm/drm_damage_helper.c
318
bool valid = false;
sys/dev/pci/drm/drm_debugfs_crc.c
188
crc->overflow = false;
sys/dev/pci/drm/drm_debugfs_crc.c
193
crc->opened = false;
sys/dev/pci/drm/drm_debugfs_crc.c
266
crc->opened = false;
sys/dev/pci/drm/drm_drv.c
1250
dev->registered = false;
sys/dev/pci/drm/drm_drv.c
529
return false;
sys/dev/pci/drm/drm_edid.c
1841
return false;
sys/dev/pci/drm/drm_edid.c
1845
return false;
sys/dev/pci/drm/drm_edid.c
1848
return false;
sys/dev/pci/drm/drm_edid.c
1977
block, EDID_LENGTH, false);
sys/dev/pci/drm/drm_edid.c
1993
return false;
sys/dev/pci/drm/drm_edid.c
2013
*edid_corrupt = false;
sys/dev/pci/drm/drm_edid.c
2044
return false;
sys/dev/pci/drm/drm_edid.c
2050
return false;
sys/dev/pci/drm/drm_edid.c
2071
return false;
sys/dev/pci/drm/drm_edid.c
2074
return false;
sys/dev/pci/drm/drm_edid.c
2080
return false;
sys/dev/pci/drm/drm_edid.c
2406
connector->edid_corrupt = false;
sys/dev/pci/drm/drm_edid.c
3202
bool ret = false;
sys/dev/pci/drm/drm_edid.c
3444
false);
sys/dev/pci/drm/drm_edid.c
3460
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
sys/dev/pci/drm/drm_edid.c
3476
false);
sys/dev/pci/drm/drm_edid.c
3567
mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
sys/dev/pci/drm/drm_edid.c
3696
return false;
sys/dev/pci/drm/drm_edid.c
3699
return false;
sys/dev/pci/drm/drm_edid.c
3704
return false;
sys/dev/pci/drm/drm_edid.c
3709
return false;
sys/dev/pci/drm/drm_edid.c
3712
return false;
sys/dev/pci/drm/drm_edid.c
3721
bool ok = false;
sys/dev/pci/drm/drm_edid.c
3727
return false; /* duplicated */
sys/dev/pci/drm/drm_edid.c
4089
false, false);
sys/dev/pci/drm/drm_edid.c
4157
closure->preferred = false;
sys/dev/pci/drm/drm_edid.c
4242
bool found = false;
sys/dev/pci/drm/drm_edid.c
4353
return false;
sys/dev/pci/drm/drm_edid.c
5587
return false;
sys/dev/pci/drm/drm_edid.c
5593
.matched = false,
sys/dev/pci/drm/drm_edid.c
5670
connector->latency_present[0] = false;
sys/dev/pci/drm/drm_edid.c
5671
connector->latency_present[1] = false;
sys/dev/pci/drm/drm_edid.c
5927
bool hdmi = false;
sys/dev/pci/drm/drm_edid.c
5970
bool has_audio = false;
sys/dev/pci/drm/drm_edid.c
6110
return false;
sys/dev/pci/drm/drm_edid.c
6117
return false;
sys/dev/pci/drm/drm_edid.c
6276
bool dsc_support = false;
sys/dev/pci/drm/drm_edid.c
6659
info->dvi_dual = false;
sys/dev/pci/drm/drm_edid.c
6660
info->is_hdmi = false;
sys/dev/pci/drm/drm_edid.c
6661
info->has_audio = false;
sys/dev/pci/drm/drm_edid.c
6662
info->has_hdmi_infoframe = false;
sys/dev/pci/drm/drm_edid.c
6663
info->rgb_quant_range_selectable = false;
sys/dev/pci/drm/drm_edid.c
6920
mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false);
sys/dev/pci/drm/drm_edid.c
7280
connector->display_info.has_hdmi_infoframe : false;
sys/dev/pci/drm/drm_edid.c
7509
connector->display_info.has_hdmi_infoframe : false;
sys/dev/pci/drm/drm_edid.c
7608
connector->has_tile = false;
sys/dev/pci/drm/drm_encoder.c
308
bool uses_atomic = false;
sys/dev/pci/drm/drm_exec.c
127
return false;
sys/dev/pci/drm/drm_fb_helper.c
1893
fb_helper->deferred_setup = false;
sys/dev/pci/drm/drm_fb_helper.c
247
fb_helper->delayed_hotplug = false;
sys/dev/pci/drm/drm_fb_helper.c
272
return __drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper, false);
sys/dev/pci/drm/drm_file.c
68
return false;
sys/dev/pci/drm/drm_format_helper.c
1005
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
1046
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
1087
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
1131
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
1171
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
1212
drm_fb_swab(dst, dst_pitch, src, fb, clip, false, state);
sys/dev/pci/drm/drm_format_helper.c
1215
drm_fb_swab(dst, dst_pitch, src, fb, clip, false, state);
sys/dev/pci/drm/drm_format_helper.c
1252
drm_fb_swab(dst, dst_pitch, src, fb, clip, false, state);
sys/dev/pci/drm/drm_format_helper.c
37
state->tmp.preallocated = false;
sys/dev/pci/drm/drm_format_helper.c
560
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
58
state->tmp.preallocated = false;
sys/dev/pci/drm/drm_format_helper.c
599
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
639
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
679
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
719
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
759
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
799
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
839
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
879
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
921
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_format_helper.c
963
drm_fb_xfrm(dst, dst_pitch, dst_pixsize, src, fb, clip, false, state,
sys/dev/pci/drm/drm_fourcc.c
244
.hsub = 1, .vsub = 1, .has_alpha = false },
sys/dev/pci/drm/drm_fourcc.c
248
.hsub = 1, .vsub = 1, .has_alpha = false },
sys/dev/pci/drm/drm_framebuffer.c
1013
bool disable_crtcs = false;
sys/dev/pci/drm/drm_framebuffer.c
1061
crtc_state->active = false;
sys/dev/pci/drm/drm_framebuffer.c
403
bool found = false;
sys/dev/pci/drm/drm_framebuffer.c
893
false, drm_framebuffer_free);
sys/dev/pci/drm/drm_gem.c
434
return false;
sys/dev/pci/drm/drm_gem.c
481
bool final = false;
sys/dev/pci/drm/drm_gpusvm.c
1037
flags.has_devmem_pages = false;
sys/dev/pci/drm/drm_gpusvm.c
1038
flags.has_dma_mapping = false;
sys/dev/pci/drm/drm_gpusvm.c
1234
return false;
sys/dev/pci/drm/drm_gpusvm.c
1608
return false;
sys/dev/pci/drm/drm_gpusvm.c
341
return false;
sys/dev/pci/drm/drm_gpusvm.c
713
return false;
sys/dev/pci/drm/drm_gpusvm.c
743
return err ? false : true;
sys/dev/pci/drm/drm_gpusvm.c
903
bool notifier_alloc = false;
sys/dev/pci/drm/drm_gpuvm.c
1225
drm_gpuvm_bo_list_add(vm_bo, evict, false);
sys/dev/pci/drm/drm_gpuvm.c
1469
drm_gpuvm_bo_list_del_init(vm_bo, evict, false);
sys/dev/pci/drm/drm_gpuvm.c
1620
return false;
sys/dev/pci/drm/drm_gpuvm.c
2368
bool prev_split = false, next_split = false;
sys/dev/pci/drm/drm_gpuvm.c
2403
ret = op_unmap_cb(ops, priv, va, false, false);
sys/dev/pci/drm/drm_gpuvm.c
2452
return __drm_gpuvm_sm_map(gpuvm, ops, priv, req, false);
sys/dev/pci/drm/drm_gpuvm.c
2590
return __drm_gpuvm_sm_map(gpuvm, &lock_ops, exec, req, false);
sys/dev/pci/drm/drm_gpuvm.c
2774
return __drm_gpuvm_sm_map_ops_create(gpuvm, req, false);
sys/dev/pci/drm/drm_gpuvm.c
936
false)
sys/dev/pci/drm/drm_ioctl.c
1004
return false;
sys/dev/pci/drm/drm_ioctl.c
1007
return false;
sys/dev/pci/drm/drm_linux.c
1866
return false;
sys/dev/pci/drm/drm_linux.c
1880
return false;
sys/dev/pci/drm/drm_linux.c
1886
if (dma_fence_is_signaled_locked(fence) == false)
sys/dev/pci/drm/drm_linux.c
2123
return false;
sys/dev/pci/drm/drm_linux.c
2186
if (dma_fence_is_signaled(f) == false)
sys/dev/pci/drm/drm_linux.c
2277
return false;
sys/dev/pci/drm/drm_linux.c
232
return false;
sys/dev/pci/drm/drm_linux.c
236
return false;
sys/dev/pci/drm/drm_linux.c
242
bool ret = false;
sys/dev/pci/drm/drm_linux.c
2446
if (dma_fence_chain_enable_signaling(&chain->base) == false)
sys/dev/pci/drm/drm_linux.c
245
return false;
sys/dev/pci/drm/drm_linux.c
2484
return false;
sys/dev/pci/drm/drm_linux.c
2500
if (dma_fence_is_signaled(f) == false) {
sys/dev/pci/drm/drm_linux.c
2502
return false;
sys/dev/pci/drm/drm_linux.c
2841
return false;
sys/dev/pci/drm/drm_linux.c
2847
return false;
sys/dev/pci/drm/drm_linux.c
3167
rb_insert_color_cached(&node->rb, root, false);
sys/dev/pci/drm/drm_linux.c
494
return false;
sys/dev/pci/drm/drm_linux.c
497
return false;
sys/dev/pci/drm/drm_linux.c
510
return false;
sys/dev/pci/drm/drm_linux.c
736
return false;
sys/dev/pci/drm/drm_mipi_dsi.c
415
dsi->attached = false;
sys/dev/pci/drm/drm_mipi_dsi.c
508
return false;
sys/dev/pci/drm/drm_mipi_dsi.c
541
return false;
sys/dev/pci/drm/drm_mm.c
214
leftmost = false;
sys/dev/pci/drm/drm_mm.c
230
leftmost = false;
sys/dev/pci/drm/drm_mm.c
278
first = false;
sys/dev/pci/drm/drm_mm.c
793
return false;
sys/dev/pci/drm/drm_mm.c
811
return false;
sys/dev/pci/drm/drm_mm.c
815
return false;
sys/dev/pci/drm/drm_mode_object.c
134
return false;
sys/dev/pci/drm/drm_mode_object.c
572
ret = drm_atomic_set_property(state, file_priv, obj, prop, prop_value, false);
sys/dev/pci/drm/drm_modes.c
1539
return false;
sys/dev/pci/drm/drm_modes.c
1543
return false;
sys/dev/pci/drm/drm_modes.c
1547
return false;
sys/dev/pci/drm/drm_modes.c
1551
return false;
sys/dev/pci/drm/drm_modes.c
1555
return false;
sys/dev/pci/drm/drm_modes.c
1559
return false;
sys/dev/pci/drm/drm_modes.c
1895
bool found_it = false;
sys/dev/pci/drm/drm_modes.c
2035
bool rb = false, cvt = false;
sys/dev/pci/drm/drm_modes.c
2074
false,
sys/dev/pci/drm/drm_modes.c
2375
bool freestanding = false, parse_extras = false;
sys/dev/pci/drm/drm_modes.c
2387
return false;
sys/dev/pci/drm/drm_modes.c
2423
return false;
sys/dev/pci/drm/drm_modes.c
2427
return false;
sys/dev/pci/drm/drm_modes.c
2434
return false;
sys/dev/pci/drm/drm_modes.c
2443
return false;
sys/dev/pci/drm/drm_modes.c
2453
return false; /* syntax error */
sys/dev/pci/drm/drm_modes.c
2466
return false;
sys/dev/pci/drm/drm_modes.c
2475
return false;
sys/dev/pci/drm/drm_modes.c
2500
return false;
sys/dev/pci/drm/drm_modes.c
2508
return false;
sys/dev/pci/drm/drm_modes.c
2513
return false;
sys/dev/pci/drm/drm_modes.c
344
bool bt601 = false;
sys/dev/pci/drm/drm_modeset_helper.c
206
drm_client_dev_suspend(dev, false);
sys/dev/pci/drm/drm_modeset_helper.c
209
drm_client_dev_resume(dev, false);
sys/dev/pci/drm/drm_modeset_helper.c
255
drm_client_dev_resume(dev, false);
sys/dev/pci/drm/drm_modeset_lock.c
402
return modeset_lock(lock, ctx, ctx->interruptible, false);
sys/dev/pci/drm/drm_panel.c
199
panel->prepared = false;
sys/dev/pci/drm/drm_panel.c
310
panel->enabled = false;
sys/dev/pci/drm/drm_panel.c
575
return false;
sys/dev/pci/drm/drm_panic.c
481
draw_txt_rectangle(sb, font, logo_ascii, logo_ascii_lines, false, rect,
sys/dev/pci/drm/drm_panic.c
531
draw_txt_rectangle(sb, font, &line_wrap, 1, false, &r_txt, fg_color);
sys/dev/pci/drm/drm_panic.c
538
draw_txt_rectangle(sb, font, &line_wrap, 1, false, &r_txt, fg_color);
sys/dev/pci/drm/drm_panic.c
544
draw_txt_rectangle(sb, font, line, 1, false, &r_txt, fg_color);
sys/dev/pci/drm/drm_panic.c
577
while (kmsg_dump_get_buffer(&iter, false, kmsg_buf, sizeof(kmsg_buf), &kmsg_len)) {
sys/dev/pci/drm/drm_panic.c
673
kmsg_dump_get_buffer(&iter, false, qrbuf1, max_kmsg_size, &kmsg_len);
sys/dev/pci/drm/drm_panic.c
722
kmsg_dump_get_buffer(&iter, false, qrbuf1, max_kmsg_size, &kmsg_len);
sys/dev/pci/drm/drm_panic.c
835
return false;
sys/dev/pci/drm/drm_panic.c
968
return false;
sys/dev/pci/drm/drm_panic.c
973
return false;
sys/dev/pci/drm/drm_plane.c
1006
return false;
sys/dev/pci/drm/drm_plane.c
926
return false;
sys/dev/pci/drm/drm_plane.c
930
return false;
sys/dev/pci/drm/drm_plane.c
940
return false;
sys/dev/pci/drm/drm_plane_helper.c
205
false, false, &visible);
sys/dev/pci/drm/drm_print.c
332
first = false;
sys/dev/pci/drm/drm_privacy_screen_x86.c
37
return false;
sys/dev/pci/drm/drm_privacy_screen_x86.c
42
return false;
sys/dev/pci/drm/drm_privacy_screen_x86.c
47
return false;
sys/dev/pci/drm/drm_privacy_screen_x86.c
49
return (output & 0x10000) ? true : false;
sys/dev/pci/drm/drm_probe_helper.c
1092
return false;
sys/dev/pci/drm/drm_probe_helper.c
245
bool poll = false;
sys/dev/pci/drm/drm_probe_helper.c
645
drm_mode_prune_invalid(dev, &connector->modes, false);
sys/dev/pci/drm/drm_probe_helper.c
763
bool repoll = false, changed;
sys/dev/pci/drm/drm_probe_helper.c
771
dev->mode_config.delayed_event = false;
sys/dev/pci/drm/drm_probe_helper.c
776
dev->mode_config.poll_running = false;
sys/dev/pci/drm/drm_probe_helper.c
807
connector->status = drm_helper_probe_detect(connector, NULL, false);
sys/dev/pci/drm/drm_probe_helper.c
868
return false;
sys/dev/pci/drm/drm_probe_helper.c
904
dev->mode_config.poll_running = false;
sys/dev/pci/drm/drm_probe_helper.c
947
dev->mode_config.poll_enabled = false;
sys/dev/pci/drm/drm_probe_helper.c
991
connector->status = drm_helper_probe_detect(connector, NULL, false);
sys/dev/pci/drm/drm_probe_helper.c
999
return false;
sys/dev/pci/drm/drm_property.c
69
return false;
sys/dev/pci/drm/drm_property.c
73
return false;
sys/dev/pci/drm/drm_property.c
745
return false;
sys/dev/pci/drm/drm_property.c
77
return false;
sys/dev/pci/drm/drm_property.c
883
bool found = false;
sys/dev/pci/drm/drm_property.c
939
return false;
sys/dev/pci/drm/drm_property.c
945
return false;
sys/dev/pci/drm/drm_property.c
952
return false;
sys/dev/pci/drm/drm_property.c
971
return false;
sys/dev/pci/drm/drm_property.c
986
return false;
sys/dev/pci/drm/drm_self_refresh_helper.c
111
crtc_state->active = false;
sys/dev/pci/drm/drm_self_refresh_helper.c
197
state->async_update = false;
sys/dev/pci/drm/drm_suballoc.c
185
return false;
sys/dev/pci/drm/drm_suballoc.c
292
return false;
sys/dev/pci/drm/drm_syncobj.c
1447
args, NULL, syncobjs, false, tp);
sys/dev/pci/drm/drm_syncobj.c
993
1, false);
sys/dev/pci/drm/drm_vblank.c
1016
if (!drm_crtc_get_last_vbltimestamp(crtc, vblanktime, false))
sys/dev/pci/drm/drm_vblank.c
1579
drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);
sys/dev/pci/drm/drm_vblank.c
1704
return false;
sys/dev/pci/drm/drm_vblank.c
1895
bool high_prec = false;
sys/dev/pci/drm/drm_vblank.c
1941
return false;
sys/dev/pci/drm/drm_vblank.c
1944
return false;
sys/dev/pci/drm/drm_vblank.c
1958
return false;
sys/dev/pci/drm/drm_vblank.c
254
rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);
sys/dev/pci/drm/drm_vblank.c
424
drm_update_vblank_count(dev, pipe, false);
sys/dev/pci/drm/drm_vblank.c
480
drm_update_vblank_count(dev, pipe, false);
sys/dev/pci/drm/drm_vblank.c
482
vblank->enabled = false;
sys/dev/pci/drm/drm_vblank.c
714
return false;
sys/dev/pci/drm/drm_vblank.c
720
return false;
sys/dev/pci/drm/drm_vblank.c
735
return false;
sys/dev/pci/drm/drm_vblank.c
760
return false;
sys/dev/pci/drm/drm_vblank.c
875
bool ret = false;
sys/dev/pci/drm/drm_vblank_work.c
120
bool passed, inmodeset, rescheduling = false, wake = false;
sys/dev/pci/drm/drm_vblank_work.c
193
bool ret = false;
sys/dev/pci/drm/drm_vblank_work.c
54
bool wake = false;
sys/dev/pci/drm/drm_vma_manager.c
341
return vma_node_allow(node, tag, false);
sys/dev/pci/drm/hdmi.c
1599
frame->itc = ptr[2] & 0x80 ? true : false;
sys/dev/pci/drm/hdmi.c
1699
frame->downmix_inhibit = ptr[4] & 0x80 ? true : false;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
212
return false;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
243
return false;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
315
ch7017_dpms(dvo, false);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
372
return false;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
183
return false;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
210
return false;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
223
return false;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
250
ch7xxx->quiet = false;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
256
return false;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
352
return false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
233
return false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
261
return false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
274
return false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
282
priv->quiet = false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
310
return false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
391
return false;
sys/dev/pci/drm/i915/display/dvo_ivch.c
396
return false;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
429
return false;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
463
return false;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
481
return false;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
504
ns->quiet = false;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
512
return false;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
650
return false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
109
return false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
135
return false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
148
return false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
171
sil->quiet = false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
178
return false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
230
if (ret == false)
sys/dev/pci/drm/i915/display/dvo_sil164.c
247
if (ret == false)
sys/dev/pci/drm/i915/display/dvo_sil164.c
248
return false;
sys/dev/pci/drm/i915/display/dvo_sil164.c
253
return false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
130
return false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
156
return false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
180
return false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
199
tfp->quiet = false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
203
return false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
260
return false;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
265
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
1213
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
1294
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
1305
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
1429
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
182
#define assert_dp_port_disabled(d) assert_dp_port((d), false)
sys/dev/pci/drm/i915/display/g4x_dp.c
193
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
sys/dev/pci/drm/i915/display/g4x_dp.c
273
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
311
return false;
sys/dev/pci/drm/i915/display/g4x_dp.c
441
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_dp.c
442
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_dp.c
507
intel_dp->link.active = false;
sys/dev/pci/drm/i915/display/g4x_dp.c
916
bool uniq_trans_scale = false;
sys/dev/pci/drm/i915/display/g4x_dp.h
36
return false;
sys/dev/pci/drm/i915/display/g4x_dp.h
41
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
127
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
403
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
404
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
427
false,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
430
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
551
chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
678
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
681
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
692
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
77
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
778
return false;
sys/dev/pci/drm/i915/display/g4x_hdmi.h
27
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
105
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
131
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
146
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
199
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
202
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
205
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
216
return false;
sys/dev/pci/drm/i915/display/hsw_ips.c
242
crtc_state->ips_enabled = false;
sys/dev/pci/drm/i915/display/hsw_ips.c
68
bool need_vblank_wait = false;
sys/dev/pci/drm/i915/display/hsw_ips.h
30
return false;
sys/dev/pci/drm/i915/display/hsw_ips.h
35
return false;
sys/dev/pci/drm/i915/display/hsw_ips.h
43
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
112
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
120
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1262
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1269
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
150
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
739
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
77
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
87
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.c
95
return false;
sys/dev/pci/drm/i915/display/i9xx_plane.h
59
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1027
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1043
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1068
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1149
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1168
wm_state->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1175
wm_state->hpll_en = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1186
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1190
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1194
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1304
intermediate->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1305
intermediate->hpll_en = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
133
500, 3000, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1402
wm->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1404
wm->hpll_en = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1406
wm->fbc_en = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1412
wm->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1413
wm->hpll_en = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1414
wm->fbc_en = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1440
_intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1669
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1688
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1976
intermediate->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
200
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2044
wm->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2051
wm->cxsr = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2082
chv_set_memory_dvfs(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2085
chv_set_memory_pm5(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2088
_intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2183
cxsr_enabled = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2185
intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2313
intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2648
max->pri = ilk_plane_wm_max(display, level, config, ddb_partitioning, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2658
max->pri = ilk_plane_wm_reg_max(display, level, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2673
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2811
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2915
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3098
ret_wm->enable = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3133
wm->enable = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3144
merged->fbc_wm_enabled = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3155
wm->enable = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3327
bool changed = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3943
500, 3000, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
4170
intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
663
intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
714
intel_set_memory_cxsr(display, false);
sys/dev/pci/drm/i915/display/i9xx_wm.c
726
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
736
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.h
23
return false;
sys/dev/pci/drm/i915/display/i9xx_wm.h
30
return false;
sys/dev/pci/drm/i915/display/icl_dsi.c
100
return false;
sys/dev/pci/drm/i915/display/icl_dsi.c
1461
icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
sys/dev/pci/drm/i915/display/icl_dsi.c
1475
gen11_dsi_config_util_pin(encoder, false);
sys/dev/pci/drm/i915/display/icl_dsi.c
1730
bool ret = false;
sys/dev/pci/drm/i915/display/icl_dsi.c
1736
return false;
sys/dev/pci/drm/i915/display/icl_dsi.c
1775
return false;
sys/dev/pci/drm/i915/display/icl_dsi.c
1826
bool enable_lpdt = false;
sys/dev/pci/drm/i915/display/icl_dsi.c
437
intel_dsi->lane_count, false);
sys/dev/pci/drm/i915/display/icl_dsi.c
658
bool clock_enabled = false;
sys/dev/pci/drm/i915/display/icl_dsi.c
81
10, 100, false);
sys/dev/pci/drm/i915/display/icl_dsi.c
84
return false;
sys/dev/pci/drm/i915/display/icl_dsi.c
97
10, 100, false);
sys/dev/pci/drm/i915/display/intel_alpm.c
150
return false;
sys/dev/pci/drm/i915/display/intel_alpm.c
155
return false;
sys/dev/pci/drm/i915/display/intel_alpm.c
181
return false;
sys/dev/pci/drm/i915/display/intel_alpm.c
184
return false;
sys/dev/pci/drm/i915/display/intel_alpm.c
249
return false;
sys/dev/pci/drm/i915/display/intel_alpm.c
252
return false;
sys/dev/pci/drm/i915/display/intel_alpm.c
607
return false;
sys/dev/pci/drm/i915/display/intel_atomic.c
210
return false;
sys/dev/pci/drm/i915/display/intel_atomic.c
265
crtc_state->update_pipe = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
266
crtc_state->update_m_n = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
267
crtc_state->update_lrr = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
268
crtc_state->disable_cxsr = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
269
crtc_state->update_wm_pre = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
270
crtc_state->update_wm_post = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
271
crtc_state->fifo_changed = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
272
crtc_state->preload_luts = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
273
crtc_state->wm.need_postvbl_update = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
274
crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
279
crtc_state->use_dsb = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
354
state->dpll_set = state->modeset = false;
sys/dev/pci/drm/i915/display/intel_audio.c
1082
glk_force_audio_cdclk(display, false);
sys/dev/pci/drm/i915/display/intel_audio.c
1399
display->audio.component_registered = false;
sys/dev/pci/drm/i915/display/intel_audio.c
446
intel_audio_sdp_split_update(old_crtc_state, false);
sys/dev/pci/drm/i915/display/intel_audio.c
716
return false;
sys/dev/pci/drm/i915/display/intel_audio.c
841
intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false);
sys/dev/pci/drm/i915/display/intel_backlight.c
1501
return false;
sys/dev/pci/drm/i915/display/intel_backlight.c
1741
panel->backlight.present = false;
sys/dev/pci/drm/i915/display/intel_backlight.c
449
panel->backlight.pwm_state.enabled = false;
sys/dev/pci/drm/i915/display/intel_backlight.c
479
panel->backlight.enabled = false;
sys/dev/pci/drm/i915/display/intel_bios.c
234
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
238
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
242
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
2524
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
2527
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
253
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
258
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
262
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
269
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
274
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
2823
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
287
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
292
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
299
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3020
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3024
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3029
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
303
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3035
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3045
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3051
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
311
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3275
intel_bios_init_panel(display, panel, devdata, NULL, false);
sys/dev/pci/drm/i915/display/intel_bios.c
330
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3336
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3362
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
339
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3410
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3428
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3437
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3445
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3449
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3459
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3493
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3579
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3587
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
3683
return false;
sys/dev/pci/drm/i915/display/intel_bios.c
907
drm_edid_print_product_id(&p, pnp_id, false);
sys/dev/pci/drm/i915/display/intel_bw.c
1277
return false;
sys/dev/pci/drm/i915/display/intel_bw.c
1300
return false;
sys/dev/pci/drm/i915/display/intel_bw.c
1605
bool changed = false;
sys/dev/pci/drm/i915/display/intel_bw.c
1770
return false;
sys/dev/pci/drm/i915/display/intel_bw.c
1778
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2030
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2034
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2043
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2055
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2382
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2385
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2401
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2427
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2469
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2478
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
3157
cdclk_state->disable_pipes = false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
3917
return false;
sys/dev/pci/drm/i915/display/intel_cdclk.c
711
500, 50 * 1000, false);
sys/dev/pci/drm/i915/display/intel_cdclk.c
729
500, 50 * 1000, false);
sys/dev/pci/drm/i915/display/intel_cdclk.c
796
500, 50 * 1000, false);
sys/dev/pci/drm/i915/display/intel_cmtg.c
123
return false;
sys/dev/pci/drm/i915/display/intel_cmtg.c
92
return false;
sys/dev/pci/drm/i915/display/intel_color.c
2049
return false;
sys/dev/pci/drm/i915/display/intel_color.c
2079
return false;
sys/dev/pci/drm/i915/display/intel_color.c
2181
new_crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/intel_color.c
2488
crtc_state->wgc_enable = false;
sys/dev/pci/drm/i915/display/intel_color.c
2668
false);
sys/dev/pci/drm/i915/display/intel_color.c
2771
false);
sys/dev/pci/drm/i915/display/intel_color.c
3136
return false;
sys/dev/pci/drm/i915/display/intel_color.c
3151
return false;
sys/dev/pci/drm/i915/display/intel_color.c
3154
return false;
sys/dev/pci/drm/i915/display/intel_color.c
3163
return false;
sys/dev/pci/drm/i915/display/intel_color.c
3166
return false;
sys/dev/pci/drm/i915/display/intel_color.c
413
return false;
sys/dev/pci/drm/i915/display/intel_color.c
417
return false;
sys/dev/pci/drm/i915/display/intel_color.c
427
return false;
sys/dev/pci/drm/i915/display/intel_color.c
430
return false;
sys/dev/pci/drm/i915/display/intel_color.c
442
return false;
sys/dev/pci/drm/i915/display/intel_color.c
565
ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, false);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
106
return false;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
187
return false;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
215
return false;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
225
return false;
sys/dev/pci/drm/i915/display/intel_crt.c
118
return false;
sys/dev/pci/drm/i915/display/intel_crt.c
255
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_crt.c
296
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_crt.c
310
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_crt.c
489
crt->force_hotplug_required = false;
sys/dev/pci/drm/i915/display/intel_crt.c
519
ret = false;
sys/dev/pci/drm/i915/display/intel_crt.c
568
ret = false;
sys/dev/pci/drm/i915/display/intel_crt.c
582
bool ret = false;
sys/dev/pci/drm/i915/display/intel_crt.c
638
intel_gmbus_force_bit(ddc, false);
sys/dev/pci/drm/i915/display/intel_crt.c
666
bool ret = false;
sys/dev/pci/drm/i915/display/intel_crt.c
747
bool restore_vblank = false;
sys/dev/pci/drm/i915/display/intel_crt.h
24
return false;
sys/dev/pci/drm/i915/display/intel_crtc.c
157
crtc->vblank_psr_notify = false;
sys/dev/pci/drm/i915/display/intel_crtc.c
330
intel_init_fifo_underrun_reporting(display, crtc, false);
sys/dev/pci/drm/i915/display/intel_crtc.c
689
false);
sys/dev/pci/drm/i915/display/intel_crtc.c
704
false);
sys/dev/pci/drm/i915/display/intel_cursor.c
292
pos = intel_cursor_position(crtc_state, plane_state, false);
sys/dev/pci/drm/i915/display/intel_cursor.c
333
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
440
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
449
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
461
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
464
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
669
pos = intel_cursor_position(crtc_state, plane_state, false);
sys/dev/pci/drm/i915/display/intel_cursor.c
742
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
783
return false;
sys/dev/pci/drm/i915/display/intel_cursor.c
948
false);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2367
crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2595
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2608
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
27
#define MB_WRITE_UNCOMMITTED false
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3458
pll_state->use_c10 = false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3476
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3479
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3482
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3491
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3494
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3498
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3501
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3514
return false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
52
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
1831
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
1884
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
2141
ddi_clk_needed = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
2354
10 * 1000, 200 * 1000, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
2431
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
2468
intel_combo_phy_power_up_lanes(display, phy, false,
sys/dev/pci/drm/i915/display/intel_ddi.c
2506
pipe_config->splitter.enable = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
3118
intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
3134
intel_dp_set_infoframes(encoder, false,
sys/dev/pci/drm/i915/display/intel_ddi.c
3159
intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
3161
intel_ddi_config_transcoder_dp2(old_crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
3199
dig_port->set_infoframes(encoder, false,
sys/dev/pci/drm/i915/display/intel_ddi.c
3218
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
3575
intel_dp->link.active = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
3586
false);
sys/dev/pci/drm/i915/display/intel_ddi.c
3598
false, false))
sys/dev/pci/drm/i915/display/intel_ddi.c
3876
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
3879
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
4406
fastset = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
4411
fastset = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
4866
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
4869
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
4877
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
4984
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
5043
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
5069
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
5169
init_hdmi = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
713
intel_ddi_config_transcoder_dp2(crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
757
return false;
sys/dev/pci/drm/i915/display/intel_ddi.c
761
ret = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
789
ret = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
791
ret = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
811
*is_dp_mst = false;
sys/dev/pci/drm/i915/display/intel_ddi.c
943
return false;
sys/dev/pci/drm/i915/display/intel_de.h
205
trace_i915_reg_rw(false, reg, val, sizeof(val), true);
sys/dev/pci/drm/i915/display/intel_display.c
1013
return false;
sys/dev/pci/drm/i915/display/intel_display.c
1025
return false;
sys/dev/pci/drm/i915/display/intel_display.c
1036
return false;
sys/dev/pci/drm/i915/display/intel_display.c
1065
intel_async_flip_vtd_wa(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1069
skl_wa_827(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1073
icl_wa_scalerclkgating(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1077
icl_wa_cursorclkgating(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1156
bool need_vbl_wait = false;
sys/dev/pci/drm/i915/display/intel_display.c
1168
old_crtc_state, old_plane_state, false);
sys/dev/pci/drm/i915/display/intel_display.c
1192
intel_crtc_update_active_timings(old_crtc_state, false);
sys/dev/pci/drm/i915/display/intel_display.c
1235
new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))
sys/dev/pci/drm/i915/display/intel_display.c
1282
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1425
intel_opregion_notify_encoder(encoder, false);
sys/dev/pci/drm/i915/display/intel_display.c
1539
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1540
intel_set_pch_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1736
glk_pipe_scaler_clock_gating_wa(pipe_crtc, false);
sys/dev/pci/drm/i915/display/intel_display.c
1767
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1768
intel_set_pch_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
1822
return false;
sys/dev/pci/drm/i915/display/intel_display.c
1837
return false;
sys/dev/pci/drm/i915/display/intel_display.c
1848
return false;
sys/dev/pci/drm/i915/display/intel_display.c
1857
return false;
sys/dev/pci/drm/i915/display/intel_display.c
2161
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
2827
return false;
sys/dev/pci/drm/i915/display/intel_display.c
292
return false;
sys/dev/pci/drm/i915/display/intel_display.c
302
return false;
sys/dev/pci/drm/i915/display/intel_display.c
3025
bool ret = false;
sys/dev/pci/drm/i915/display/intel_display.c
3031
return false;
sys/dev/pci/drm/i915/display/intel_display.c
3367
bool ret = false;
sys/dev/pci/drm/i915/display/intel_display.c
3373
return false;
sys/dev/pci/drm/i915/display/intel_display.c
3839
return false;
sys/dev/pci/drm/i915/display/intel_display.c
3852
return false;
sys/dev/pci/drm/i915/display/intel_display.c
3937
return false;
sys/dev/pci/drm/i915/display/intel_display.c
4025
return false;
sys/dev/pci/drm/i915/display/intel_display.c
4144
return false;
sys/dev/pci/drm/i915/display/intel_display.c
4427
ret = false;
sys/dev/pci/drm/i915/display/intel_display.c
4443
return false;
sys/dev/pci/drm/i915/display/intel_display.c
448
cur_state = false;
sys/dev/pci/drm/i915/display/intel_display.c
472
#define assert_plane_disabled(p) assert_plane(p, false)
sys/dev/pci/drm/i915/display/intel_display.c
4796
return false;
sys/dev/pci/drm/i915/display/intel_display.c
4803
return false;
sys/dev/pci/drm/i915/display/intel_display.c
5032
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5044
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5056
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5066
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5078
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5088
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5108
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5118
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5128
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5164
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5174
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5184
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5194
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5206
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5217
ret = false; \
sys/dev/pci/drm/i915/display/intel_display.c
5340
PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
sys/dev/pci/drm/i915/display/intel_display.c
5553
crtc_state->update_pipe = false;
sys/dev/pci/drm/i915/display/intel_display.c
5554
crtc_state->update_m_n = false;
sys/dev/pci/drm/i915/display/intel_display.c
5555
crtc_state->update_lrr = false;
sys/dev/pci/drm/i915/display/intel_display.c
5595
crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/intel_display.c
5741
new_crtc_state->update_lrr = false;
sys/dev/pci/drm/i915/display/intel_display.c
5749
new_crtc_state->uapi.mode_changed = false;
sys/dev/pci/drm/i915/display/intel_display.c
5754
new_crtc_state->update_m_n = false;
sys/dev/pci/drm/i915/display/intel_display.c
5758
new_crtc_state->update_lrr = false;
sys/dev/pci/drm/i915/display/intel_display.c
5802
return false;
sys/dev/pci/drm/i915/display/intel_display.c
5819
return false;
sys/dev/pci/drm/i915/display/intel_display.c
6357
bool any_ms = false;
sys/dev/pci/drm/i915/display/intel_display.c
6369
new_crtc_state->inherited = false;
sys/dev/pci/drm/i915/display/intel_display.c
6708
intel_crtc_update_active_timings(pipe_crtc_state, false);
sys/dev/pci/drm/i915/display/intel_display.c
682
intel_set_plane_visible(crtc_state, plane_state, false);
sys/dev/pci/drm/i915/display/intel_display.c
6839
intel_psr_notify_pipe_change(state, crtc, false);
sys/dev/pci/drm/i915/display/intel_display.c
6848
pipe_crtc->active = false;
sys/dev/pci/drm/i915/display/intel_display.c
689
crtc_state->ips_enabled = false;
sys/dev/pci/drm/i915/display/intel_display.c
703
intel_set_memory_cxsr(display, false))
sys/dev/pci/drm/i915/display/intel_display.c
711
intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);
sys/dev/pci/drm/i915/display/intel_display.c
7118
ret = dma_fence_wait_timeout(new_plane_state->fence, false,
sys/dev/pci/drm/i915/display/intel_display.c
7261
new_crtc_state->use_flipq = false;
sys/dev/pci/drm/i915/display/intel_display.c
7262
new_crtc_state->use_dsb = false;
sys/dev/pci/drm/i915/display/intel_display.c
7653
state->base.legacy_cursor_update = false;
sys/dev/pci/drm/i915/display/intel_display.c
7719
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7722
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7725
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7733
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7736
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7740
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7744
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7747
return false;
sys/dev/pci/drm/i915/display/intel_display.c
7761
bool dpd_is_edp = false;
sys/dev/pci/drm/i915/display/intel_display.c
7864
bool found = false;
sys/dev/pci/drm/i915/display/intel_display.c
789
return false;
sys/dev/pci/drm/i915/display/intel_display.c
8185
crtc_state->inherited = false;
sys/dev/pci/drm/i915/display/intel_display.c
839
return false;
sys/dev/pci/drm/i915/display/intel_display.c
845
return false;
sys/dev/pci/drm/i915/display/intel_display.c
856
return false;
sys/dev/pci/drm/i915/display/intel_display.c
869
return false;
sys/dev/pci/drm/i915/display/intel_display.c
954
return false;
sys/dev/pci/drm/i915/display/intel_display.c
963
return false;
sys/dev/pci/drm/i915/display/intel_display.c
996
return false;
sys/dev/pci/drm/i915/display/intel_display.h
541
#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1174
bool dsc_fractional_bpp_enable = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
700
bool lpsp_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
850
bool lpsp_capable = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
893
bool try_again = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
898
try_again = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
91
bool sr_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
963
bool dsc_enable = false;
sys/dev/pci/drm/i915/display/intel_display_device.c
1908
display_runtime->has_dbuf_overlap_detection = false;
sys/dev/pci/drm/i915/display/intel_display_driver.c
238
intel_power_domains_init_hw(display, false);
sys/dev/pci/drm/i915/display/intel_display_driver.c
383
set_display_access(display, false, current);
sys/dev/pci/drm/i915/display/intel_display_driver.c
385
set_display_access(display, false, curproc);
sys/dev/pci/drm/i915/display/intel_display_driver.c
403
set_display_access(display, false, NULL);
sys/dev/pci/drm/i915/display/intel_display_driver.c
423
set_display_access(display, false, current);
sys/dev/pci/drm/i915/display/intel_display_driver.c
425
set_display_access(display, false, curproc);
sys/dev/pci/drm/i915/display/intel_display_driver.c
473
return false;
sys/dev/pci/drm/i915/display/intel_display_driver.c
86
return false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1188
bool found = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1373
bool found = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1690
return false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1747
if (gen11_dsi_configure_te(crtc, false))
sys/dev/pci/drm/i915/display/intel_display_irq.c
2176
display->irq.vlv_display_irqs_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
583
bool blc_event = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
607
bool blc_event = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
88
return false;
sys/dev/pci/drm/i915/display/intel_display_params.h
34
param(bool, enable_flipq, false, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
41
param(bool, load_detect_test, false, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
42
param(bool, force_reset_modeset_test, false, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
43
param(bool, disable_display, false, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
45
param(bool, nuclear_pageflip, false, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
50
param(bool, psr_safest_params, false, 0400) \
sys/dev/pci/drm/i915/display/intel_display_power.c
1318
100, 1000, false);
sys/dev/pci/drm/i915/display/intel_display_power.c
1535
intel_pch_reset_handshake(display, false);
sys/dev/pci/drm/i915/display/intel_display_power.c
1834
display->power.chv_phy_assert[DPIO_PHY0] = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
1856
display->power.chv_phy_assert[DPIO_PHY1] = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
1994
power_domains->initializing = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
214
return false;
sys/dev/pci/drm/i915/display/intel_display_power.c
2166
power_domains->display_core_suspended = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
2214
dump_domain_info = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
223
is_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
392
bool err = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
495
bool ret = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
509
cancel_async_put_work(power_domains, false);
sys/dev/pci/drm/i915/display/intel_display_power.c
591
is_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
701
cancel_async_put_work(power_domains, false);
sys/dev/pci/drm/i915/display/intel_display_power.c
811
cancel_async_put_work(power_domains, false);
sys/dev/pci/drm/i915/display/intel_display_power.c
909
return false;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1149
500, 100 * 1000, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1169
vlv_set_power_well(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1176
bool enabled = false;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
127
power_well->hw_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1313
vlv_set_power_well(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1349
vlv_set_power_well(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1545
vlv_set_power_well(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1739
500, 100 * 1000, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1772
chv_set_pipe_power_well(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1827
tgl_tc_cold_request(display, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
392
hsw_wait_for_power_well_enable(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
445
hsw_wait_for_power_well_enable(display, power_well, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
561
100, 1000, false);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
809
intel_dmc_update_dc6_allowed_count(display, false);
sys/dev/pci/drm/i915/display/intel_display_reset.c
32
return false;
sys/dev/pci/drm/i915/display/intel_display_types.h
1960
return false;
sys/dev/pci/drm/i915/display/intel_display_types.h
2031
return false;
sys/dev/pci/drm/i915/display/intel_display_types.h
2044
return false;
sys/dev/pci/drm/i915/display/intel_display_wa.c
75
return false;
sys/dev/pci/drm/i915/display/intel_display_wa.h
18
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
1011
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
1016
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
1571
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
1576
intel_dmc_update_dc6_allowed_count(display, false);
sys/dev/pci/drm/i915/display/intel_dmc.c
1730
dmc_configure_event(display, dmc_id, event, false);
sys/dev/pci/drm/i915/display/intel_dmc.c
559
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
562
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
567
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
580
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
588
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
604
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
713
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
720
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
729
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
739
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
752
return false;
sys/dev/pci/drm/i915/display/intel_dmc.c
911
pipedmc_clock_gating_wa(display, false);
sys/dev/pci/drm/i915/display/intel_dmc.c
933
pipedmc_clock_gating_wa(display, false);
sys/dev/pci/drm/i915/display/intel_dmc.c
950
return false;
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
191
wl->taken = false;
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
240
return false;
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
278
return false;
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
407
wl->enabled = false;
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
419
wl->taken = false;
sys/dev/pci/drm/i915/display/intel_dp.c
1061
drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
sys/dev/pci/drm/i915/display/intel_dp.c
1107
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1116
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1125
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1133
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1138
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1153
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1156
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1361
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1396
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1399
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1403
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1406
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1426
bool dsc = false;
sys/dev/pci/drm/i915/display/intel_dp.c
1648
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1664
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1668
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1948
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
1952
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2139
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2145
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2152
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2488
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2546
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2603
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2687
false,
sys/dev/pci/drm/i915/display/intel_dp.c
2703
0, false);
sys/dev/pci/drm/i915/display/intel_dp.c
2761
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2781
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2783
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2958
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
2996
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
3005
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
3009
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
3012
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
3071
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
3294
ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3378
intel_dp->link.active = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3379
intel_dp->needs_modeset_retry = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3390
intel_dp->link.retrain_disabled = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3543
connector->dp.dsc_decompression_enabled = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3545
return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
sys/dev/pci/drm/i915/display/intel_dp.c
3609
intel_dp_sink_set_dsc_decompression(connector, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3610
intel_dp_sink_set_dsc_passthrough(connector, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3640
WRITE_ONCE(intel_dp->oui_valid, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3648
WRITE_ONCE(intel_dp->oui_valid, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3726
bool dpcd_updated = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3763
fastset = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3778
fastset = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3786
fastset = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3876
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
3906
ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3912
1000, TIMEOUT_FRL_READY_MS * 1000, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3933
1000, TIMEOUT_HDMI_LINK_ACTIVE_MS * 1000, false);
sys/dev/pci/drm/i915/display/intel_dp.c
3954
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4112
bool ycbcr444_to_420 = false;
sys/dev/pci/drm/i915/display/intel_dp.c
4113
bool rgb_to_ycbcr = false;
sys/dev/pci/drm/i915/display/intel_dp.c
4180
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4424
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4477
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4497
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4518
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4535
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4622
intel_dp->is_mst = false;
sys/dev/pci/drm/i915/display/intel_dp.c
4639
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4659
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4685
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
4898
as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
sys/dev/pci/drm/i915/display/intel_dp.c
491
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5138
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5144
bool handled = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5166
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5193
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5202
link_ok = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5212
link_ok = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5258
intel_dp->frl.is_trained = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5271
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5282
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5289
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5301
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5304
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5322
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5336
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5451
intel_dp->link.force_retrain = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5512
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5516
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5520
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5554
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5569
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5690
bool is_connected = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5696
30, 4000, false);
sys/dev/pci/drm/i915/display/intel_dp.c
5786
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5861
intel_dp->dfp.ycbcr_444_to_420 = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5862
connector->base.ycbcr_420_allowed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5865
false);
sys/dev/pci/drm/i915/display/intel_dp.c
5882
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5888
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
5950
intel_dp->psr.sink_panel_replay_support = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5951
intel_dp->psr.sink_panel_replay_su_support = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5981
intel_dp->reset_link_params = false;
sys/dev/pci/drm/i915/display/intel_dp.c
6027
intel_dp_dpcd_set_probe(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_dp.c
6060
intel_dp_dpcd_set_probe(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_dp.c
6154
connector->dp.dsc_decompression_enabled = false;
sys/dev/pci/drm/i915/display/intel_dp.c
6360
bool need_work = false;
sys/dev/pci/drm/i915/display/intel_dp.c
6465
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6488
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6494
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6500
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6589
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6728
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6746
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6768
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6827
intel_dp->frl.is_trained = false;
sys/dev/pci/drm/i915/display/intel_dp.c
6838
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
6885
intel_dp->is_mst = false;
sys/dev/pci/drm/i915/display/intel_dp.c
6886
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false);
sys/dev/pci/drm/i915/display/intel_dp.c
807
return false;
sys/dev/pci/drm/i915/display/intel_dp.c
811
return false;
sys/dev/pci/drm/i915/display/intel_dp_aux.c
319
trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
sys/dev/pci/drm/i915/display/intel_dp_aux.c
443
intel_pps_vdd_off_unlocked(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
126
return false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
134
return false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
137
return false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
155
return false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
579
panel->backlight.enabled = false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
590
panel->backlight.enabled = false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
623
return false;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
648
bool try_intel_interface = false, try_vesa_interface = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
269
return false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
307
{ HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
309
false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
311
false, 0, 0, 0 },
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
313
false, 0, 0, 0 },
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
320
{ HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
322
false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
323
{ HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
328
{ HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
331
DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
334
false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
338
DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
370
*msg_ready = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
407
bool msg_ready = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
654
*capable = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
686
*capable = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
706
*hdcp_capable = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
707
*hdcp2_capable = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1015
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1031
bool channel_eq = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1047
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1149
500, 500 * 1000, false);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1169
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
117
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1200
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1227
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1285
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1355
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1403
bool timeout = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1414
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1422
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1429
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1436
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1447
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1454
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1465
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1482
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1489
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1498
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1504
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1515
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1538
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1545
bool timeout = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1554
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1567
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1573
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1588
bool passed = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1593
500, 500 * 1000, false);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
187
intel_dp_set_lttpr_transparent_mode(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
488
bool changed = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
684
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
687
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
702
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
705
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
912
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
937
bool max_vswing_reached = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
949
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
972
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
983
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
989
return false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
997
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1026
intel_dp->link.active = false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1105
false);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1111
intel_dp_set_infoframes(primary_encoder, false, old_crtc_state, NULL);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1361
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1462
bool dsc = false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1624
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1679
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1692
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1695
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1699
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1709
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2027
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2033
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2069
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2095
intel_dp_link_training_set_mode(intel_dp, link_rate, false);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2136
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
341
false, dsc_slice_count, link_bpp_x16);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
456
fxp_q4_from_int(2 * 3), false);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
538
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
541
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
544
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
547
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
572
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
581
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
605
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
623
crtc_state, false, dsc,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
625
return false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
666
pipe_config->has_pch_encoder = false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
672
pipe_config, false, &limits);
sys/dev/pci/drm/i915/display/intel_dp_test.c
500
return false;
sys/dev/pci/drm/i915/display/intel_dp_test.c
526
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp_test.c
598
intel_dp->compliance.test_active = false;
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
309
intel_dp->tunnel_suspended = false;
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
76
return false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1021
__chv_data_lane_soft_reset(encoder, crtc_state, false);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1032
chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1033
dig_port->release_cl2_override = false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1069
chv_phy_powergate_lanes(encoder, false, 0x0);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
181
.dual_channel = false,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
193
.dual_channel = false,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
203
.dual_channel = false,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
213
.dual_channel = false,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
363
return false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
370
return false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
377
return false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
537
return false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
554
return false;
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
95
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
1817
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
2325
assert_pll(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_dpll.c
586
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
588
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
590
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
592
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
598
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
603
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
605
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
609
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
614
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
777
bool found = false;
sys/dev/pci/drm/i915/display/intel_dpll.c
838
return false;
sys/dev/pci/drm/i915/display/intel_dpll.c
873
bool found = false;
sys/dev/pci/drm/i915/display/intel_dpll.c
929
int found = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1441
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1443
ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1479
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1481
ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2187
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2189
ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
246
pll->on = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3018
bool use_ssc = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3556
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3564
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3623
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3629
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3695
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3701
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
540
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
761
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
782
return false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
405
#define assert_dpll_disabled(d, p) assert_dpll(d, p, false)
sys/dev/pci/drm/i915/display/intel_dpt.c
317
dpt->obj->is_dpt = false;
sys/dev/pci/drm/i915/display/intel_drrs.c
293
intel_drrs_frontbuffer_update(display, frontbuffer_bits, false);
sys/dev/pci/drm/i915/display/intel_dsb.c
112
return false;
sys/dev/pci/drm/i915/display/intel_dsb.c
299
return false;
sys/dev/pci/drm/i915/display/intel_dsb.c
880
100, 1000, false);
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
46
return false;
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
50
return false;
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
58
return false;
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
64
return false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
416
native = false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
827
return false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
844
return false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
918
bool want_backlight_gpio = false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
919
bool want_panel_gpio = false;
sys/dev/pci/drm/i915/display/intel_dvo.c
142
return false;
sys/dev/pci/drm/i915/display/intel_dvo.c
194
intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
sys/dev/pci/drm/i915/display/intel_dvo.c
471
intel_gmbus_force_bit(i2c, false);
sys/dev/pci/drm/i915/display/intel_dvo.c
488
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1251
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1260
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1267
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1275
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1322
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1325
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
1655
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
2170
if (dma_resv_test_signaled(obj->resv, dma_resv_usage_rw(false)))
sys/dev/pci/drm/i915/display/intel_fb.c
2173
ret = dma_resv_get_singleton(obj->resv, dma_resv_usage_rw(false),
sys/dev/pci/drm/i915/display/intel_fb.c
520
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
553
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
556
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
564
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
568
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
572
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
628
return false;
sys/dev/pci/drm/i915/display/intel_fb.c
635
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1005
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1044
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1047
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1063
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1066
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1082
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1115
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1597
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1601
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1604
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1607
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1611
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1615
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1619
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1623
return false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1634
bool need_vblank_wait = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1660
fbc->activated = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1669
bool need_vblank_wait = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1707
fbc_compressor_clkgate_disable_wa(fbc, false);
sys/dev/pci/drm/i915/display/intel_fbc.c
1710
fbc->flip_pending = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1718
fbc->flip_pending = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1988
fbc->underrun_detected = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
737
fbc->active = false;
sys/dev/pci/drm/i915/display/intel_fbdev.c
257
bool prealloc = false;
sys/dev/pci/drm/i915/display/intel_fbdev.c
303
false, &flags);
sys/dev/pci/drm/i915/display/intel_fbdev.c
535
return false;
sys/dev/pci/drm/i915/display/intel_fbdev_fb.c
96
for_i915_gem_ww(&ww, ret, false) {
sys/dev/pci/drm/i915/display/intel_fdi.c
118
assert_fdi_rx_pll(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_fdi.c
321
intel_dp_bw_fec_overhead(false),
sys/dev/pci/drm/i915/display/intel_fdi.c
424
cpt_set_fdi_bc_bifurcation(display, false);
sys/dev/pci/drm/i915/display/intel_fdi.c
59
assert_fdi_tx(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_fdi.c
80
assert_fdi_rx(display, pipe, false);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
378
if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
400
false)) {
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
71
return false;
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
88
return false;
sys/dev/pci/drm/i915/display/intel_flipq.c
116
return false;
sys/dev/pci/drm/i915/display/intel_flipq.c
119
return false;
sys/dev/pci/drm/i915/display/intel_flipq.c
445
intel_flipq_preempt(crtc, false);
sys/dev/pci/drm/i915/display/intel_frontbuffer.h
104
return false;
sys/dev/pci/drm/i915/display/intel_frontbuffer.h
108
return false;
sys/dev/pci/drm/i915/display/intel_global_state.c
157
return false;
sys/dev/pci/drm/i915/display/intel_global_state.c
214
obj_state->changed = false;
sys/dev/pci/drm/i915/display/intel_global_state.c
215
obj_state->serialized = false;
sys/dev/pci/drm/i915/display/intel_global_state.c
348
return false;
sys/dev/pci/drm/i915/display/intel_gmbus.c
347
pnv_gmbus_clock_gating(display, false);
sys/dev/pci/drm/i915/display/intel_gmbus.c
371
ptl_handle_mask_bits(bus, false);
sys/dev/pci/drm/i915/display/intel_gmbus.c
529
0, 2, false);
sys/dev/pci/drm/i915/display/intel_gmbus.c
533
500, 50 * 1000, false);
sys/dev/pci/drm/i915/display/intel_gmbus.c
580
bool extra_byte_added = false;
sys/dev/pci/drm/i915/display/intel_gmbus.c
778
bxt_gmbus_clock_gating(display, false);
sys/dev/pci/drm/i915/display/intel_gmbus.c
780
pch_gmbus_clock_gating(display, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
1014
hdcp->hdcp_encrypted = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
1028
ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
120
bool enforce_type0 = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
1908
dig_port->hdcp.auth_status = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
192
return false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
1979
false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2092
intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2122
ret = hdcp->shim->stream_2_2_encryption(connector, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2140
connector->hdcp.hdcp2_encrypted = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2141
dig_port->hdcp.auth_status = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
225
bool capable = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2355
return false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2386
display->hdcp.comp_added = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2427
hdcp->hdcp2_supported = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2552
DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2554
ret = _intel_hdcp2_disable(connector, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
257
return false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2573
bool content_protection_type_changed, desired_and_not_enabled = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
262
return false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2646
display->hdcp.comp_added = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
269
return false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2758
bool hdcp_cap = false, hdcp2_cap = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2791
__intel_hdcp_info(m, connector, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
280
bool capable = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2812
__intel_hdcp_info(m, connector, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2828
bool force_hdcp14 = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
283
return false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
304
*hdcp2_capable = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
332
100 * 1000, 5 * 1000 * 1000, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
344
bool enabled = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
909
100, 1000, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
944
100, 1000, false);
sys/dev/pci/drm/i915/display/intel_hdcp.c
997
ret = hdcp->shim->stream_encryption(connector, false);
sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c
31
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1516
false, TRANS_DDI_HDCP_SIGNALLING);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1582
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1593
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1608
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1686
bool msg_ready = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1697
4000, timeout * 1000, false);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1784
*capable = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1937
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1952
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1960
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1970
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2092
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2105
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2112
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2202
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2223
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2362
ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2509
bool connected = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2520
intel_gmbus_force_bit(ddc, false);
sys/dev/pci/drm/i915/display/intel_hdmi.c
3061
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
3067
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
3071
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
3275
bool bpp_found = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
732
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
764
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
790
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
796
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
822
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
826
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
856
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
861
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
966
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
989
return false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
998
return false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
1078
bool do_flush = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
1158
display->hotplug.detection_work_enabled = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
160
bool storm = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
164
return false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
200
return false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
211
return false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
222
return false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
232
bool hpd_disabled = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
316
bool ret = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
322
status = drm_helper_probe_detect(&connector->base, NULL, false);
sys/dev/pci/drm/i915/display/intel_hotplug.c
367
return false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
591
bool storm_detected = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
592
bool queue_dig = false, queue_hp = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
913
WRITE_ONCE(display->hotplug.poll_enabled, false);
sys/dev/pci/drm/i915/display/intel_hotplug.c
956
bool was_pending = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
995
bool queue_hp_work = false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
227
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
241
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
254
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
269
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
279
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
295
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
305
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
319
return false;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
333
return false;
sys/dev/pci/drm/i915/display/intel_hti.c
27
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
160
ret = __intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason, false);
sys/dev/pci/drm/i915/display/intel_link_bw.c
188
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
222
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
226
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
230
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
265
bool bpps_changed = false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
272
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
279
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
291
return false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
433
return false;
sys/dev/pci/drm/i915/display/intel_lpe_audio.c
196
return false;
sys/dev/pci/drm/i915/display/intel_lpe_audio.c
198
int lpe_present = false;
sys/dev/pci/drm/i915/display/intel_lpe_audio.c
383
ppdata->dp_output = false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
118
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
145
lspcon->hdr_supported = false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
200
5000, timeout_us, false);
sys/dev/pci/drm/i915/display/intel_lspcon.c
252
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
286
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
301
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
345
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
353
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
369
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
378
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
393
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
422
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
429
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
456
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
467
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
477
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
484
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
621
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
636
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
686
lspcon->active = false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
691
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
696
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
701
return false;
sys/dev/pci/drm/i915/display/intel_lspcon.c
98
return false;
sys/dev/pci/drm/i915/display/intel_lvds.c
113
return false;
sys/dev/pci/drm/i915/display/intel_lvds.h
26
return false;
sys/dev/pci/drm/i915/display/intel_lvds.h
37
return false;
sys/dev/pci/drm/i915/display/intel_modeset_lock.c
30
return false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
136
pmdemand_state, false);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
406
return false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
421
return false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
493
return false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
502
return false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
596
has_active_crtc = false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
608
pmdemand_state, false);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
757
false);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
94
crtc->active = false;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
95
crtc->base.enabled = false;
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
121
bool enabled = false, found = false;
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
223
hw_crtc_state, false)) {
sys/dev/pci/drm/i915/display/intel_opregion.c
1177
return false;
sys/dev/pci/drm/i915/display/intel_opregion.c
1201
return false;
sys/dev/pci/drm/i915/display/intel_opregion.c
1207
return false;
sys/dev/pci/drm/i915/display/intel_opregion.c
363
1000, dslp * 1000, false);
sys/dev/pci/drm/i915/display/intel_opregion.c
806
bool requested_callbacks = false;
sys/dev/pci/drm/i915/display/intel_opregion.h
125
return false;
sys/dev/pci/drm/i915/display/intel_opregion.h
136
return false;
sys/dev/pci/drm/i915/display/intel_opregion.h
93
return false;
sys/dev/pci/drm/i915/display/intel_overlay.c
1186
overlay->pfit_active = false;
sys/dev/pci/drm/i915/display/intel_overlay.c
1245
return false;
sys/dev/pci/drm/i915/display/intel_overlay.c
1249
return false;
sys/dev/pci/drm/i915/display/intel_overlay.c
1261
return false;
sys/dev/pci/drm/i915/display/intel_overlay.c
278
i830_overlay_clock_gating(display, false);
sys/dev/pci/drm/i915/display/intel_overlay.c
388
overlay->active = false;
sys/dev/pci/drm/i915/display/intel_overlay.c
509
overlay->active = false;
sys/dev/pci/drm/i915/display/intel_overlay.c
632
bool scale_changed = false;
sys/dev/pci/drm/i915/display/intel_overlay.c
805
bool scale_changed = false;
sys/dev/pci/drm/i915/display/intel_overlay.h
35
return false;
sys/dev/pci/drm/i915/display/intel_panel.c
192
return false;
sys/dev/pci/drm/i915/display/intel_panel.c
78
return false;
sys/dev/pci/drm/i915/display/intel_pch_display.h
49
return false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
290
with_fdi = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
411
return false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
421
return false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
430
return false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
440
return false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
446
bool has_fdi = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
507
bool has_lvds = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
508
bool has_cpu_edp = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
509
bool has_panel = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
510
bool has_ck505 = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
511
bool can_ssc = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
512
bool using_ssc_source = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
535
has_ck505 = false;
sys/dev/pci/drm/i915/display/intel_pfit.c
699
return false;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
133
bool need_stable_symbols = false;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
629
intel_crtc_crc_setup_workarounds(crtc, false);
sys/dev/pci/drm/i915/display/intel_plane.c
1011
plane_state->uapi.visible = false;
sys/dev/pci/drm/i915/display/intel_plane.c
1136
ret = dma_resv_get_singleton(resv, dma_resv_usage_rw(false), &new);
sys/dev/pci/drm/i915/display/intel_plane.c
1275
intel_display_rps_mark_interactive(display, state, false);
sys/dev/pci/drm/i915/display/intel_plane.c
1516
plane_state->is_y_plane = false;
sys/dev/pci/drm/i915/display/intel_plane.c
186
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
196
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
445
plane_state->uapi.visible = false;
sys/dev/pci/drm/i915/display/intel_plane.c
465
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
468
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
498
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
509
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
537
return false;
sys/dev/pci/drm/i915/display/intel_plane.c
606
was_visible = false;
sys/dev/pci/drm/i915/display/intel_plane.c
620
visible = false;
sys/dev/pci/drm/i915/display/intel_plane.c
786
new_plane_state->uapi.visible = false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
104
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
111
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
277
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
282
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
303
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
53
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
87
return false;
sys/dev/pci/drm/i915/display/intel_plane_initial.c
97
return false;
sys/dev/pci/drm/i915/display/intel_pmdemand.c
244
old_conn_state, false,
sys/dev/pci/drm/i915/display/intel_pmdemand.c
292
return false;
sys/dev/pci/drm/i915/display/intel_pmdemand.c
577
bool changed = false;
sys/dev/pci/drm/i915/display/intel_pps.c
100
bool pll_enabled, release_cl_override = false;
sys/dev/pci/drm/i915/display/intel_pps.c
1066
intel_dp->pps.want_panel_vdd = false;
sys/dev/pci/drm/i915/display/intel_pps.c
1154
is_enabled = false;
sys/dev/pci/drm/i915/display/intel_pps.c
1365
bool have_power = false;
sys/dev/pci/drm/i915/display/intel_pps.c
167
chv_phy_powergate_ch(display, phy, ch, false);
sys/dev/pci/drm/i915/display/intel_pps.c
1708
pps_init_registers(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_pps.c
1730
pps_init_registers(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_pps.c
1770
pps_init_registers(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_pps.c
1772
intel_dp->pps.initializing = false;
sys/dev/pci/drm/i915/display/intel_pps.c
1893
locked = false;
sys/dev/pci/drm/i915/display/intel_pps.c
268
intel_dp->pps.bxt_pps_reset = false;
sys/dev/pci/drm/i915/display/intel_pps.c
274
pps_init_registers(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_pps.c
555
return false;
sys/dev/pci/drm/i915/display/intel_pps.c
568
return false;
sys/dev/pci/drm/i915/display/intel_pps.c
754
return false;
sys/dev/pci/drm/i915/display/intel_pps.c
819
vdd = false;
sys/dev/pci/drm/i915/display/intel_pps.c
944
intel_dp->pps.want_panel_vdd = false;
sys/dev/pci/drm/i915/display/intel_pps.c
960
intel_pps_vdd_off_unlocked(intel_dp, false);
sys/dev/pci/drm/i915/display/intel_psr.c
1128
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1262
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1279
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1282
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1301
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1305
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1329
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1389
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1403
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1409
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1424
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1429
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1437
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1443
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1450
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1462
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1487
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1495
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1498
if (!alpm_config_valid(intel_dp, crtc_state, false))
sys/dev/pci/drm/i915/display/intel_psr.c
1499
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1507
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1565
crtc_state->enable_psr2_sel_fetch = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1566
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1577
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1583
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1592
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1609
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1613
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1619
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1629
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1635
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1646
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1650
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
1716
crtc_state->has_psr = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1832
bool activate = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1998
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
2025
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2112
false);
sys/dev/pci/drm/i915/display/intel_psr.c
2120
intel_dp->psr.active = false;
sys/dev/pci/drm/i915/display/intel_psr.c
214
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
2185
intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);
sys/dev/pci/drm/i915/display/intel_psr.c
2203
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);
sys/dev/pci/drm/i915/display/intel_psr.c
2205
intel_dp->psr.enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2206
intel_dp->psr.panel_replay_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2207
intel_dp->psr.sel_update_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2208
intel_dp->psr.psr2_sel_fetch_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2209
intel_dp->psr.su_region_et_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2210
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2238
intel_dp->psr.link_ok = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2344
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
245
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
256
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
2575
bool su_area_changed = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2652
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
2667
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
2728
bool full_update = false, su_area_changed;
sys/dev/pci/drm/i915/display/intel_psr.c
3011
bool keep_disabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3157
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
3451
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3672
psr->link_ok = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3724
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
3751
return false;
sys/dev/pci/drm/i915/display/intel_psr.c
738
return false;
sys/dev/pci/drm/i915/display/intel_sbi.c
79
intel_sbi_rw(display, reg, destination, &value, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1019
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1022
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1029
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1039
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1079
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1118
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1129
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1148
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1152
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1242
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1246
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1265
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1270
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1274
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1332
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1348
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1864
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1865
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1987
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2674
intel_gmbus_force_bit(sdvo->i2c, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
276
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2809
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2839
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2861
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2872
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2885
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2901
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2914
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2933
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2944
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2962
intel_panel_add_edid_fixed_modes(intel_connector, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
2976
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3007
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3035
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3045
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3076
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3082
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3087
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3099
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3116
return false; \
sys/dev/pci/drm/i915/display/intel_sdvo.c
3119
if (!intel_sdvo_connector->name) return false; \
sys/dev/pci/drm/i915/display/intel_sdvo.c
3147
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3152
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3160
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3168
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3180
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3185
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3194
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3203
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3226
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3232
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3391
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3394
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3398
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3521
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
475
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
480
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
518
ret = false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
524
ret = false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
617
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
636
&ddc_bus, 1, false);
sys/dev/pci/drm/i915/display/intel_sdvo.c
642
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
651
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
677
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
734
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.c
968
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.h
26
return false;
sys/dev/pci/drm/i915/display/intel_sdvo.h
31
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1244
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1258
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1266
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1492
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1505
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1513
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1531
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1539
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
1561
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
471
return false;
sys/dev/pci/drm/i915/display/intel_sprite.c
902
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1060
200, 5000, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1066
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1136
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1139
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1141
__xelpdp_tc_phy_enable_tcss_power(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1142
xelpdp_tc_phy_wait_for_tcss_power(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1144
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1226
xelpdp_tc_phy_take_ownership(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1227
xelpdp_tc_phy_wait_for_tcss_power(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1232
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1240
xelpdp_tc_phy_take_ownership(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1241
xelpdp_tc_phy_enable_tcss_power(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1347
1000, 500 * 1000, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1352
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1590
bool update_mode = false;
sys/dev/pci/drm/i915/display/intel_tc.c
1627
intel_tc_port_update_mode(tc, 1, false);
sys/dev/pci/drm/i915/display/intel_tc.c
1749
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1839
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
1869
false);
sys/dev/pci/drm/i915/display/intel_tc.c
578
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
598
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
622
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
678
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
686
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
722
icl_tc_phy_take_ownership(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
726
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
738
icl_tc_phy_take_ownership(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
750
tc_phy_load_fia_params(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
863
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
959
adlp_tc_phy_take_ownership(tc, false);
sys/dev/pci/drm/i915/display/intel_tc.c
963
return false;
sys/dev/pci/drm/i915/display/intel_tc.c
980
adlp_tc_phy_take_ownership(tc, false);
sys/dev/pci/drm/i915/display/intel_tv.c
1268
tv_conn_state->bypass_vfilter = false;
sys/dev/pci/drm/i915/display/intel_tv.c
1471
burst_ena = false;
sys/dev/pci/drm/i915/display/intel_tv.c
393
.component_only = false,
sys/dev/pci/drm/i915/display/intel_tv.c
399
.progressive = false, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
422
.pal_burst = false,
sys/dev/pci/drm/i915/display/intel_tv.c
436
.component_only = false,
sys/dev/pci/drm/i915/display/intel_tv.c
441
.progressive = false, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
464
.pal_burst = false,
sys/dev/pci/drm/i915/display/intel_tv.c
478
.component_only = false,
sys/dev/pci/drm/i915/display/intel_tv.c
484
.progressive = false, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
507
.pal_burst = false,
sys/dev/pci/drm/i915/display/intel_tv.c
521
.component_only = false,
sys/dev/pci/drm/i915/display/intel_tv.c
527
.progressive = false, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
565
.component_only = false,
sys/dev/pci/drm/i915/display/intel_tv.c
570
.progressive = false, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
610
.component_only = false,
sys/dev/pci/drm/i915/display/intel_tv.c
615
.progressive = false, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
657
.progressive = true, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
662
.veq_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
667
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
681
.progressive = true, .trilevel_sync = false,
sys/dev/pci/drm/i915/display/intel_tv.c
686
.veq_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
691
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
710
.veq_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
715
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
734
.veq_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
739
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
753
.progressive = false, .trilevel_sync = true,
sys/dev/pci/drm/i915/display/intel_tv.c
765
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
779
.progressive = false, .trilevel_sync = true,
sys/dev/pci/drm/i915/display/intel_tv.c
791
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
811
.veq_ena = false, .veq_start_f1 = 0,
sys/dev/pci/drm/i915/display/intel_tv.c
817
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
837
.veq_ena = false, .veq_start_f1 = 0,
sys/dev/pci/drm/i915/display/intel_tv.c
843
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_tv.c
863
.veq_ena = false, .veq_start_f1 = 0,
sys/dev/pci/drm/i915/display/intel_tv.c
869
.burst_ena = false,
sys/dev/pci/drm/i915/display/intel_vblank.c
348
return false;
sys/dev/pci/drm/i915/display/intel_vblank.c
504
500, 100 * 1000, false);
sys/dev/pci/drm/i915/display/intel_vblank.c
513
wait_for_pipe_scanline_moving(crtc, false);
sys/dev/pci/drm/i915/display/intel_vdsc.c
30
return false;
sys/dev/pci/drm/i915/display/intel_vdsc.c
302
vdsc_cfg->native_422 = false;
sys/dev/pci/drm/i915/display/intel_vdsc.c
303
vdsc_cfg->simple_422 = false;
sys/dev/pci/drm/i915/display/intel_vdsc.c
305
vdsc_cfg->vbr_enable = false;
sys/dev/pci/drm/i915/display/intel_vdsc.c
33
return false;
sys/dev/pci/drm/i915/display/intel_vdsc.c
48
return false;
sys/dev/pci/drm/i915/display/intel_vdsc.c
880
*all_equal = false;
sys/dev/pci/drm/i915/display/intel_vga.c
35
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
191
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
201
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
240
crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
sys/dev/pci/drm/i915/display/intel_vrr.c
34
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
375
crtc_state->vrr.in_range = false;
sys/dev/pci/drm/i915/display/intel_vrr.c
38
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
42
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
46
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
578
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
586
return false;
sys/dev/pci/drm/i915/display/intel_vrr.c
591
return false;
sys/dev/pci/drm/i915/display/intel_wm.c
126
return false;
sys/dev/pci/drm/i915/display/intel_wm.c
76
return false;
sys/dev/pci/drm/i915/display/intel_wm_types.h
73
return false;
sys/dev/pci/drm/i915/display/skl_scaler.c
206
scaler_state->scalers[*scaler_id].in_use = false;
sys/dev/pci/drm/i915/display/skl_scaler.c
304
bool need_scaler = false;
sys/dev/pci/drm/i915/display/skl_scaler.c
429
scaler_state->scalers[*scaler_id].in_use = false;
sys/dev/pci/drm/i915/display/skl_scaler.c
461
drm_rect_debug_print("dst: ", dst, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
498
drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
776
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
777
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
832
y_hphase = skl_scaler_calc_phase(1, hscale, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
833
y_vphase = skl_scaler_calc_phase(1, vscale, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
837
uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
843
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
844
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1703
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1945
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2233
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2239
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2259
plane_state->decrypt = intel_pxp_key_check(obj, false) == 0;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2354
plane_state->uapi.visible = false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2416
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2440
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2443
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2446
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2499
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2543
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2553
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2597
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2607
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2649
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2759
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3189
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3196
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
534
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
536
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
549
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
557
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
565
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
582
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
584
return false;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
933
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
1057
.join_mbus = false,
sys/dev/pci/drm/i915/display/skl_watermark.c
1064
.join_mbus = false,
sys/dev/pci/drm/i915/display/skl_watermark.c
1174
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2337
wm->wm[level].enable = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2338
wm->uv_wm[level].enable = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2352
wm->sagv.wm0.enable = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2353
wm->sagv.trans_wm.enable = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2415
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2453
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2489
new_crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2781
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2790
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
2859
new_crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
310
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
3153
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
316
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
3355
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
349
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
368
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
3685
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
3703
dbuf_state->joined_mbus = false;
sys/dev/pci/drm/i915/display/skl_watermark.c
3740
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
379
return false;
sys/dev/pci/drm/i915/display/skl_watermark.c
387
return false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
333
bool cold_boot = false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
733
bool glk_cold_boot = false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
807
dpi_send_cmd(intel_dsi, TURN_ON, false, port);
sys/dev/pci/drm/i915/display/vlv_dsi.c
853
dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
sys/dev/pci/drm/i915/display/vlv_dsi.c
941
bool active = false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
948
return false;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
238
500, 20 * 1000, false);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
282
return false;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
297
enabled = false;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
303
enabled = false;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
622
assert_dsi_pll(display, false);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.h
41
return false;
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
105
return false;
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
128
obj->cache_dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
131
obj->cache_dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
80
return false;
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
91
obj->cache_dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
92
return false;
sys/dev/pci/drm/i915/gem/i915_gem_context.c
267
pc->uses_protected_content = false;
sys/dev/pci/drm/i915/gem/i915_gem_dmabuf.c
156
err = i915_gem_object_set_to_gtt_domain(obj, false);
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
24
return false;
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
42
return false;
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
45
return false;
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
685
ret = i915_gem_object_set_to_cpu_domain(obj, false);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1400
wide = false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1768
bool have_copy = false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1779
eb_release_vmas(eb, false);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1814
err = eb_pin_engine(eb, false);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1859
eb_release_vmas(eb, false);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1904
throttle = false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1933
eb_release_vmas(eb, false);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
3232
false);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
407
return false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
635
return false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
641
return false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
700
bool unpinned = false;
sys/dev/pci/drm/i915/gem/i915_gem_internal.c
126
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_mman.c
33
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
223
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
613
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
637
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
710
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
713
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
719
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
722
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
728
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
735
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
846
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
855
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
869
bool lmem_placement = false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
873
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
881
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.h
32
return false;
sys/dev/pci/drm/i915/gem/i915_gem_object.h
876
static inline bool i915_gem_object_is_userptr(struct drm_i915_gem_object *obj) { return false; }
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
40
obj->cache_dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
519
pinned = false;
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
625
obj->cache_dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
76
shrinkable = false;
sys/dev/pci/drm/i915/gem/i915_gem_phys.c
148
__i915_gem_object_release_shmem(obj, pages, false);
sys/dev/pci/drm/i915/gem/i915_gem_phys.c
188
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_pm.c
147
bool flush = false;
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
228
shmem_sg_free_table(st, mapping, false, false, obj);
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
292
shmem_sg_free_table(st, mapping, false, false);
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
294
shmem_sg_free_table(st, NULL, false, false, obj);
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
321
shmem_sg_free_table(st, mapping, false, false);
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
323
shmem_sg_free_table(st, NULL, false, false, obj);
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
428
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
465
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
29
return false;
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
55
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
129
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
136
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
139
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
142
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
145
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
155
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
171
return false;
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
175
return false;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
1506
.no_wait_gpu = false,
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
238
shmem_sg_free_table(st, filp->f_mapping, false, false);
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
370
return false;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
378
return false;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
382
return false;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
433
.no_wait_gpu = false,
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
808
.no_wait_gpu = false,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
448
dma_fence_wait(dep, false);
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
461
return false;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
465
return false;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
467
return I915_SELFTEST_ONLY(ban_memcpy) ? false : true;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
517
dma_fence_wait(dep, false);
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
669
dma_fence_wait(migration_fence, false);
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
746
copy_fence = __i915_ttm_move(src_bo, &ctx, false, dst_bo->resource,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.c
195
false);
sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.c
97
err = i915_gem_obj_copy_ttm(backup, obj, pm_apply->allow_gpu, false);
sys/dev/pci/drm/i915/gem/i915_gem_userptr.c
175
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/i915_gem_userptr.c
203
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/selftests/huge_gem_object.c
91
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
161
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
310
obj->mm.dirty = false;
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
722
bool single = false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
123
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
132
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
136
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
306
t->batch = __create_vma(t, PAGE_SIZE, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
310
t->scratch.vma = create_vma(t, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
700
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
124
err = i915_gem_object_set_to_gtt_domain(ctx->obj, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
179
err = i915_gem_object_set_to_wc_domain(ctx->obj, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
262
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
270
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1715
err = i915_gem_object_set_to_cpu_domain(obj, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
971
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
977
err = i915_gem_object_set_to_gtt_domain(obj, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c
144
force_different_devices = false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c
199
mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c
319
force_different_devices = false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
21
intel_gt_coherent_map_type(gt, obj, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
279
err = igt_fill_check_buffer(obj, gt, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
354
i915_ttm_migrate_set_failure_modes(false, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
355
i915_ttm_migrate_set_ban_memcpy(false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
426
spin_fence, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
509
i915_ttm_migrate_set_failure_modes(false, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
510
i915_ttm_migrate_set_ban_memcpy(false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
89
err = igt_fill_check_buffer(obj, gt, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1249
i915_ttm_migrate_set_failure_modes(true, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1264
i915_ttm_migrate_set_failure_modes(false, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1592
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1835
bool unuse_mm = false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
555
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
879
return false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
883
return false;
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
272
*is_local = false;
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
179
bool flush = false;
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
316
ppgtt->scan_for_unused_pt = false;
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
15
bool vf_flush_wa = false, dc_flush_wa = false;
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
355
*cs++ = preparser_disable(false);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
409
*cs++ = preparser_disable(false);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
230
gen8_ppgtt_notify_vgt(ppgtt, false);
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
103
return false;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
116
return false;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
121
return false;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
126
return false;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
465
bool release = false;
sys/dev/pci/drm/i915/gt/intel_context.c
230
bool handoff = false;
sys/dev/pci/drm/i915/gt/intel_context.h
391
return false;
sys/dev/pci/drm/i915/gt/intel_engine.h
304
return false;
sys/dev/pci/drm/i915/gt/intel_engine.h
341
return false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1858
idle = false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1863
idle = false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1913
return false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1937
return false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1946
return false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1985
return false; /* uses physical not virtual addresses */
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2047
bool skip = false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2064
false) >= sizeof(line));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2068
skip = false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
745
return false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
752
return false;
sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c
57
return false;
sys/dev/pci/drm/i915/gt/intel_engine_pm.c
239
result = false;
sys/dev/pci/drm/i915/gt/intel_engine_types.h
692
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1001
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1004
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1017
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1156
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1160
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1164
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1184
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1193
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1196
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1266
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1280
bool submit = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1547
merge = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1725
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2101
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2129
bool result = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2416
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2419
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2489
bool tasklet = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2566
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
307
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
329
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3878
first = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
795
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
801
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
816
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
825
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
844
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
859
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
875
ok = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
884
ok = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
893
ok = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
900
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
952
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
955
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
985
return false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
988
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1568
*is_local = false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1760
bool write_domain_objs = false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1766
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1808
flush = i915_ggtt_resume_vm(&ggtt->vm, false);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
194
__i915_vma_evict(vma, false);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
214
i915_ggtt_suspend_vm(&ggtt->vm, false);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
243
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
387
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
468
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
588
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
230
WRITE_ONCE(fence->dirty, false);
sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c
76
return false;
sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c
81
return false;
sys/dev/pci/drm/i915/gt/intel_gt.c
1155
__intel_gt_bind_context_set_ready(gt, false);
sys/dev/pci/drm/i915/gt/intel_gt.c
1172
return false;
sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c
113
node->pinned = false;
sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c
154
node->pinned = false;
sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c
41
bool active = false;
sys/dev/pci/drm/i915/gt/intel_gt_irq.c
210
return false;
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
570
return false;
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
580
return false;
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
180
return false;
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
221
__intel_engine_reset(engine, false);
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
224
intel_uc_reset(>->uc, false);
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
316
user_forcewake(gt, false);
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
395
gt_sanitize(gt, false);
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
75
gt->stats.active = false;
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
543
return false;
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
101
return false;
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
23
return false;
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
38
bool active = false;
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
41
return false;
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
44
return false;
sys/dev/pci/drm/i915/gt/intel_gtt.c
490
can_use_gtt_cache = false;
sys/dev/pci/drm/i915/gt/intel_llc.c
62
return false;
sys/dev/pci/drm/i915/gt/intel_lrc.c
1029
inhibit = false;
sys/dev/pci/drm/i915/gt/intel_lrc.c
1206
false) |
sys/dev/pci/drm/i915/gt/intel_lrc.c
1473
u32 * const start = context_wabb(ce, false);
sys/dev/pci/drm/i915/gt/intel_lrc.c
1581
set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false);
sys/dev/pci/drm/i915/gt/intel_lrc.c
1599
valid = false;
sys/dev/pci/drm/i915/gt/intel_lrc.c
1609
valid = false;
sys/dev/pci/drm/i915/gt/intel_lrc.c
1618
valid = false;
sys/dev/pci/drm/i915/gt/intel_lrc.c
819
bool ctx_is_protected = false;
sys/dev/pci/drm/i915/gt/intel_migrate.c
26
return false;
sys/dev/pci/drm/i915/gt/intel_migrate.c
483
return false;
sys/dev/pci/drm/i915/gt/intel_migrate.c
716
ccs_is_src = false;
sys/dev/pci/drm/i915/gt/intel_migrate.c
819
err = emit_pte(rq, &it_ccs, ccs_pat_index, false,
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
130
bool free = false;
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
133
return false;
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
30
pt->is_compact = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
445
enable_rc6 = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
457
enable_rc6 = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
466
enable_rc6 = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
473
enable_rc6 = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
478
enable_rc6 = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
483
enable_rc6 = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
495
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
498
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
501
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
506
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
513
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
519
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
536
rc6->wakeref = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
544
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
547
return false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
624
rc6->enabled = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
715
rc6->enabled = false;
sys/dev/pci/drm/i915/gt/intel_region_lmem.c
211
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
1076
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
1107
dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/i915/gt/intel_reset.c
1126
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
127
bool banned = false;
sys/dev/pci/drm/i915/gt/intel_reset.c
1611
return _intel_gt_reset_lock(gt, srcu, false);
sys/dev/pci/drm/i915/gt/intel_reset.c
1725
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
1731
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
415
bool lock_obtained, lock_to_other = false;
sys/dev/pci/drm/i915/gt/intel_reset.c
707
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
710
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
806
return false;
sys/dev/pci/drm/i915/gt/intel_reset.c
85
banned = false;
sys/dev/pci/drm/i915/gt/intel_ring.c
60
int type = intel_gt_coherent_map_type(vma->vm->gt, vma->obj, false);
sys/dev/pci/drm/i915/gt/intel_ring.h
72
return false;
sys/dev/pci/drm/i915/gt/intel_ring.h
75
return false;
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
1405
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
740
bool force_restore = false;
sys/dev/pci/drm/i915/gt/intel_rps.c
1232
return false;
sys/dev/pci/drm/i915/gt/intel_rps.c
1541
return false;
sys/dev/pci/drm/i915/gt/intel_rps.c
1551
bool enabled = false;
sys/dev/pci/drm/i915/gt/intel_rps.c
1828
bool client_boost = false;
sys/dev/pci/drm/i915/gt/intel_rps.c
2169
return intel_gpu_freq(rps, __read_cagf(rps, false));
sys/dev/pci/drm/i915/gt/intel_rps.c
2683
intel_rps_set_manual(rps, false);
sys/dev/pci/drm/i915/gt/intel_rps.c
2708
intel_rps_set_manual(rps, false);
sys/dev/pci/drm/i915/gt/intel_rps.c
2837
return false;
sys/dev/pci/drm/i915/gt/intel_rps.c
2864
return false;
sys/dev/pci/drm/i915/gt/intel_rps.c
2890
return false;
sys/dev/pci/drm/i915/gt/intel_rps.c
2913
return false;
sys/dev/pci/drm/i915/gt/intel_rps.c
929
rps_set(rps, rps->idle_freq, false);
sys/dev/pci/drm/i915/gt/intel_rps.c
972
bool boost = false;
sys/dev/pci/drm/i915/gt/intel_sseu.c
708
subslice_pg = false;
sys/dev/pci/drm/i915/gt/intel_sseu.h
127
return false;
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
265
i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), sseu);
sys/dev/pci/drm/i915/gt/intel_wopcm.c
121
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
140
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
152
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
156
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
175
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
183
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
192
return false;
sys/dev/pci/drm/i915/gt/intel_wopcm.c
208
return false;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1287
intel_gt_mcr_report_steering(&p, gt, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1527
0, 0, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1570
0, 0, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1751
return false;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1850
return false;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1855
return false;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
248
wa_add(wal, reg, clear, set, clear | set, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
254
wa_mcr_add(wal, reg, clear, set, clear | set, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
2973
return false;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
2985
return false;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
3048
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
761
0, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
828
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
39
return false;
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
122
vaddr = i915_gem_object_pin_map_unlocked(obj, intel_gt_coherent_map_type(gt, obj, false));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
76
intel_gt_coherent_map_type(gt, h->obj, false));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
845
return __igt_reset_engine(arg, false);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1306
false));
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1512
return false;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1610
return emit_wabb_ctx_canary(ce, cs, false);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1645
return false;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1742
return lrc_wabb_ctx(arg, false);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
423
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
50
return false;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
717
err = __live_lrc_gpr(engine, scratch, false);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
905
err = __lrc_timestamp(&data, false);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
268
bool ccs_cap = false;
sys/dev/pci/drm/i915/gt/selftest_migrate.c
355
false, &rq);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
651
len = emit_pte(rq, &it, obj->pat_index, false, 0, CHUNK_SZ);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
988
dst = create_init_lmem_internal(gt, sz, false);
sys/dev/pci/drm/i915/gt/selftest_rps.c
645
engine->kernel_context->vm, false,
sys/dev/pci/drm/i915/gt/selftest_slpc.c
89
err = intel_guc_slpc_set_ignore_eff_freq(slpc, false);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
229
{ "unset", 0, false, false },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
230
{ "new", 0, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
232
{ "1a", 1, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
234
{ "0b", 0, true, false },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
235
{ "2a", 2, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
236
{ "4", 4, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
237
{ "INT_MAX", INT_MAX, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
238
{ "INT_MAX-1", INT_MAX-1, true, false },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
239
{ "INT_MAX+1", (u32)INT_MAX+1, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
240
{ "INT_MAX", INT_MAX, true, false },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
241
{ "UINT_MAX", UINT_MAX, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
242
{ "wrap", 0, false, true },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
243
{ "unwrap", UINT_MAX, true, false },
sys/dev/pci/drm/i915/gt/selftest_timeline.c
47
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1012
return false;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1180
return false;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
217
err = i915_gem_object_set_to_cpu_domain(results, false);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
433
return false;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
446
return false;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
456
return false;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
537
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
970
return false;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
990
return false;
sys/dev/pci/drm/i915/gt/shmem_utils.c
165
return __shmem_rw(file, off, dst, len, false);
sys/dev/pci/drm/i915/gt/shmem_utils.c
288
return __uao_rw(uao, off, dst, len, false);
sys/dev/pci/drm/i915/gt/sysfs_engines.c
137
return __caps_show(kobj_to_engine(kobj), -1, buf, false);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
237
bool too_old = false;
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
64
return gsc_uc_get_fw_status(gsc_uc_to_gt(gsc)->uncore, false) &
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c
127
intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC, false);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c
84
if (intel_gsc_uc_fw_proxy_init_done(gsc, false)) {
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
148
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc.c
114
guc->interrupts.enabled = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc.c
158
guc->interrupts.enabled = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
404
ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
405
ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
423
false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
428
ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
430
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
433
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
434
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
435
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
436
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
437
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
438
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
439
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1107
bool is_partial = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1540
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1544
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1559
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
517
return guc_capture_getlistsize(guc, owner, type, classid, size, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
813
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1008
bool found = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1036
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1049
bool found = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
165
ctb->broken = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
360
err = ct_register_buffer(ct, false, desc, cmds, size);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
378
ct->dead_ct_reported = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
400
ct->enabled = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
403
ct_control_enable(ct, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
641
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
734
send_again = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h
117
ct->enabled = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
129
*success = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
144
*success = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
148
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c
105
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
335
bool overflow = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
522
log->relay.buf_in_use = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
533
log->relay.started = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
831
log->relay.started = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
51
ret = intel_guc_log_dump(m->private, &p, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c
23
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c
80
return __guc_rc_control(guc, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
291
slpc->ignore_eff_freq = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
292
slpc->min_is_rpmax = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
694
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
700
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
74
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1040
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1044
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1478
engine->stats.guc.running = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1887
guilty = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2198
guc->submission_initialized = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3192
enable = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4282
bool result = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4807
guc_route_semaphores(guc, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4817
guc_route_semaphores(guc, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4832
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4960
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5074
ce->drop_deregister = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5135
ce->drop_schedule_enable = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5148
ce->drop_schedule_disable = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5422
found = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
6011
return false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
721
err = guc_context_policy_init_v70(ce, false);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
931
bool submit = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
994
ret = try_context_registration(ce, false);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
612
return false;
sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c
114
return false;
sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c
117
return false;
sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c
120
return false;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
460
bool pl1en = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
641
uc->reset_in_progress = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
662
guc->interrupts.enabled = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
672
false, OUTSTANDING_CTB_TIMEOUT_PERIOD);
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
690
guc->interrupts.enabled = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
753
return __uc_resume(uc, false);
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1420
got_wanted = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1423
got_wanted = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1427
got_wanted = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
219
.legacy = false, .has_gsc_headers = gsc_ }
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
226
UC_FW_BLOB_NEW(major_, minor_, patch_, false, \
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
234
UC_FW_BLOB_NEW(0, 0, 0, false, MAKE_HUC_FW_PATH_BLANK(prefix_))
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
306
found = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
352
return false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
443
return false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
902
bool old_ver = false;
sys/dev/pci/drm/i915/gt/uc/selftest_guc.c
318
bool spinning = false;
sys/dev/pci/drm/i915/gt/uc/selftest_guc.c
382
spinning = false;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
87
ret = alloc_gm(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
157
trap_gttmmio(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
158
map_aperture(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
209
trap_gttmmio(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
216
map_aperture(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
220
intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
230
trap_gttmmio(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
236
map_aperture(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
390
trap_gttmmio(vgpu, false);
sys/dev/pci/drm/i915/gvt/cfg_space.c
391
map_aperture(vgpu, false);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1115
ret |= cmd_address_audit(s, gma, sizeof(u32), false);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1139
ret |= cmd_address_audit(s, gma, sizeof(u32), false);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1186
bool index_mode = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1636
ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1689
ret = cmd_address_audit(s, gma, op_size, false);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1718
bool index_mode = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1821
bool bb_end = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
2864
s.is_ctx_wa = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
3028
ret = i915_gem_object_set_to_cpu_domain(obj, false);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
3143
s.is_ctx_wa = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
3195
s.is_ctx_wa = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
3196
s.is_init_ctx = false;
sys/dev/pci/drm/i915/gvt/display.c
787
vgpu_update_vblank_emulation(vgpu, false);
sys/dev/pci/drm/i915/gvt/dmabuf.c
251
return false;
sys/dev/pci/drm/i915/gvt/dmabuf.c
545
dmabuf_obj->initref = false;
sys/dev/pci/drm/i915/gvt/dmabuf.c
587
dmabuf_obj->initref = false;
sys/dev/pci/drm/i915/gvt/edid.c
577
edid->target_selected = false;
sys/dev/pci/drm/i915/gvt/edid.c
578
edid->edid_available = false;
sys/dev/pci/drm/i915/gvt/edid.c
583
edid->aux_ch.i2c_over_aux_ch = false;
sys/dev/pci/drm/i915/gvt/edid.c
584
edid->aux_ch.aux_ch_mot = false;
sys/dev/pci/drm/i915/gvt/execlist.c
214
emulate_csb_update(execlist, &status, false);
sys/dev/pci/drm/i915/gvt/execlist.c
235
emulate_csb_update(execlist, &status, false);
sys/dev/pci/drm/i915/gvt/execlist.c
244
emulate_csb_update(execlist, &status, false);
sys/dev/pci/drm/i915/gvt/execlist.c
321
emulate_csb_update(execlist, &status, false);
sys/dev/pci/drm/i915/gvt/execlist.c
354
emulate_csb_update(execlist, &status, false);
sys/dev/pci/drm/i915/gvt/execlist.c
400
bool lite_restore = false;
sys/dev/pci/drm/i915/gvt/gtt.c
1001
return false;
sys/dev/pci/drm/i915/gvt/gtt.c
1011
bool ips = false;
sys/dev/pci/drm/i915/gvt/gtt.c
1356
ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
1372
ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
1677
false, 0, vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
1716
mm->ppgtt_mm.shadowed = false;
sys/dev/pci/drm/i915/gvt/gtt.c
2156
bool partial_update = false;
sys/dev/pci/drm/i915/gvt/gtt.c
2176
bool found = false;
sys/dev/pci/drm/i915/gvt/gtt.c
2284
s->last_ctx[i].valid = false;
sys/dev/pci/drm/i915/gvt/gtt.c
2347
ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
2416
intel_vgpu_reset_ggtt(vgpu, false);
sys/dev/pci/drm/i915/gvt/gtt.c
359
return false;
sys/dev/pci/drm/i915/gvt/gtt.c
497
entry, index, false, 0, mm->vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
498
update_entry_type_for_real(pte_ops, entry, false);
sys/dev/pci/drm/i915/gvt/gtt.c
50
static bool enable_out_of_sync = false;
sys/dev/pci/drm/i915/gvt/gtt.c
510
_ppgtt_get_root_entry(mm, entry, index, false);
sys/dev/pci/drm/i915/gvt/gtt.c
521
entry, index, false, 0, mm->vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
527
_ppgtt_set_root_entry(mm, entry, index, false);
sys/dev/pci/drm/i915/gvt/gtt.c
539
false, 0, mm->vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
550
false, 0, mm->vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
560
pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
579
pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
sys/dev/pci/drm/i915/gvt/gtt.c
607
spt->guest_page.pde_ips : false);
sys/dev/pci/drm/i915/gvt/gtt.c
644
spt->shadow_page.type, e, index, false)
sys/dev/pci/drm/i915/gvt/gtt.c
648
spt->shadow_page.type, e, index, false)
sys/dev/pci/drm/i915/gvt/gtt.c
71
return false;
sys/dev/pci/drm/i915/gvt/gvt.h
725
return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);
sys/dev/pci/drm/i915/gvt/handlers.c
1461
bool invalid_read = false;
sys/dev/pci/drm/i915/gvt/handlers.c
1538
bool invalid_write = false;
sys/dev/pci/drm/i915/gvt/handlers.c
2018
vgpu->d3_entered = false;
sys/dev/pci/drm/i915/gvt/handlers.c
366
intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
sys/dev/pci/drm/i915/gvt/handlers.c
726
vgpu_update_vblank_emulation(vgpu, false);
sys/dev/pci/drm/i915/gvt/handlers.c
782
return false;
sys/dev/pci/drm/i915/gvt/kvmgt.c
464
intel_vgpu_emulate_hotplug(vgpu, false);
sys/dev/pci/drm/i915/gvt/kvmgt.c
645
bool ret = false;
sys/dev/pci/drm/i915/gvt/kvmgt.c
855
return false;
sys/dev/pci/drm/i915/gvt/kvmgt.c
862
true : false;
sys/dev/pci/drm/i915/gvt/kvmgt.c
881
ppos, false);
sys/dev/pci/drm/i915/gvt/kvmgt.c
893
ppos, false);
sys/dev/pci/drm/i915/gvt/kvmgt.c
905
ppos, false);
sys/dev/pci/drm/i915/gvt/kvmgt.c
917
false);
sys/dev/pci/drm/i915/gvt/mmio.c
193
failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
sys/dev/pci/drm/i915/gvt/mmio.c
226
ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
sys/dev/pci/drm/i915/gvt/mmio_context.c
100
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
101
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
102
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
103
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
104
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
105
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
106
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
107
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
sys/dev/pci/drm/i915/gvt/mmio_context.c
115
{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
116
{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
119
{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
120
{RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
121
{RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
122
{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
137
{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
138
{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
139
{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
140
{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
141
{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
143
{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
145
{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
148
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
149
{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
150
{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
152
{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
153
{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
156
{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
157
{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
158
{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
159
{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
sys/dev/pci/drm/i915/gvt/mmio_context.c
60
{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
61
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
62
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
64
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
65
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
66
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
67
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
sys/dev/pci/drm/i915/gvt/mmio_context.c
68
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
69
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
70
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
71
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
72
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
73
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
74
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
75
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
sys/dev/pci/drm/i915/gvt/mmio_context.c
83
{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
84
{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
85
{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
86
{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
87
{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
88
{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
sys/dev/pci/drm/i915/gvt/mmio_context.c
92
{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
93
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
94
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
96
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
97
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
98
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
99
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
sys/dev/pci/drm/i915/gvt/opregion.c
403
return false;
sys/dev/pci/drm/i915/gvt/page_track.c
145
track->tracked = false;
sys/dev/pci/drm/i915/gvt/sched_policy.c
169
scheduler->need_reschedule = false;
sys/dev/pci/drm/i915/gvt/sched_policy.c
195
vgpu_data->pri_sched = false;
sys/dev/pci/drm/i915/gvt/sched_policy.c
367
vgpu_data->active = false;
sys/dev/pci/drm/i915/gvt/sched_policy.c
47
return false;
sys/dev/pci/drm/i915/gvt/scheduler.c
140
bool skip = false;
sys/dev/pci/drm/i915/gvt/scheduler.c
1492
s->active = false;
sys/dev/pci/drm/i915/gvt/scheduler.c
188
sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
sys/dev/pci/drm/i915/gvt/scheduler.c
214
s->last_ctx[ring_id].valid = false;
sys/dev/pci/drm/i915/gvt/scheduler.c
553
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gvt/scheduler.c
619
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/gvt/scheduler.c
927
return false;
sys/dev/pci/drm/i915/gvt/scheduler.c
933
return false;
sys/dev/pci/drm/i915/gvt/vgpu.c
212
vgpu->d3_entered = false;
sys/dev/pci/drm/i915/gvt/vgpu.c
337
vgpu->d3_entered = false;
sys/dev/pci/drm/i915/gvt/vgpu.c
482
vgpu->failsafe = false;
sys/dev/pci/drm/i915/gvt/vgpu.c
488
vgpu->d3_entered = false;
sys/dev/pci/drm/i915/gvt/vgpu.c
490
vgpu->pv_notified = false;
sys/dev/pci/drm/i915/i915_active.c
428
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1256
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1277
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1288
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1294
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1302
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1330
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1342
return false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1455
bool needs_clflush_after = false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1597
bool active = false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
828
ret = false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
855
ret = false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
872
return false;
sys/dev/pci/drm/i915/i915_driver.c
1003
drm_client_dev_suspend(&i915->drm, false);
sys/dev/pci/drm/i915/i915_driver.c
1049
return false;
sys/dev/pci/drm/i915/i915_driver.c
1086
drm_client_dev_suspend(dev, false);
sys/dev/pci/drm/i915/i915_driver.c
1194
return i915_drm_suspend_late(&i915->drm, false);
sys/dev/pci/drm/i915/i915_driver.c
1272
drm_client_dev_resume(dev, false);
sys/dev/pci/drm/i915/i915_driver.c
1338
ret = vlv_resume_prepare(dev_priv, false);
sys/dev/pci/drm/i915/i915_driver.c
1413
return i915_drm_suspend_late(&i915->drm, false);
sys/dev/pci/drm/i915/i915_driver.c
178
bool pre = false;
sys/dev/pci/drm/i915/i915_driver.c
2599
dev->registered = false;
sys/dev/pci/drm/i915/i915_driver.c
2647
dev->registered = false;
sys/dev/pci/drm/i915/i915_drv.h
683
#define HAS_RC6pp(i915) (false) /* HW was never validated */
sys/dev/pci/drm/i915/i915_gem.c
397
vma = i915_gem_gtt_prepare(obj, &node, false);
sys/dev/pci/drm/i915/i915_gem_evict.c
103
return false;
sys/dev/pci/drm/i915/i915_gem_evict.c
106
return false;
sys/dev/pci/drm/i915/i915_gem_evict.c
120
return false;
sys/dev/pci/drm/i915/i915_gem_evict.c
76
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
102
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
126
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
1289
ret = compress_page(compress, s, dst, false);
sys/dev/pci/drm/i915/i915_gpu_error.c
283
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
290
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
81
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
84
return false;
sys/dev/pci/drm/i915/i915_gpu_error.c
980
bool print_guc_capture = false;
sys/dev/pci/drm/i915/i915_hwmon.c
573
hwmon->ddat.reset_in_progress = false;
sys/dev/pci/drm/i915/i915_irq.c
1237
dev_priv->irqs_enabled = false;
sys/dev/pci/drm/i915/i915_irq.c
1272
dev_priv->irqs_enabled = false;
sys/dev/pci/drm/i915/i915_irq.c
1284
i915->irqs_enabled = false;
sys/dev/pci/drm/i915/i915_memcpy.c
124
return false;
sys/dev/pci/drm/i915/i915_memcpy.c
136
return false;
sys/dev/pci/drm/i915/i915_memcpy.c
43
static bool has_movntdqa = false;
sys/dev/pci/drm/i915/i915_mitigations.c
111
enable = false;
sys/dev/pci/drm/i915/i915_mitigations.c
53
first = false;
sys/dev/pci/drm/i915/i915_module.c
39
use_kms = false;
sys/dev/pci/drm/i915/i915_module.c
42
use_kms = false;
sys/dev/pci/drm/i915/i915_params.h
55
param(bool, memtest, false, 0400) \
sys/dev/pci/drm/i915/i915_params.h
66
param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \
sys/dev/pci/drm/i915/i915_params.h
67
param(bool, enable_debug_only_api, false, IS_ENABLED(CONFIG_DRM_I915_REPLAY_GPU_HANGS_API) ? 0400 : 0)
sys/dev/pci/drm/i915/i915_pci.c
104
.has_coherent_ggtt = false, \
sys/dev/pci/drm/i915/i915_pci.c
147
.has_coherent_ggtt = false,
sys/dev/pci/drm/i915/i915_pci.c
211
.has_snoop = false,
sys/dev/pci/drm/i915/i915_pci.c
219
.has_snoop = false,
sys/dev/pci/drm/i915/i915_pci.c
226
.gpu_reset_clobbers_display = false,
sys/dev/pci/drm/i915/i915_pci.c
234
.gpu_reset_clobbers_display = false,
sys/dev/pci/drm/i915/i915_pci.c
379
.has_coherent_ggtt = false,
sys/dev/pci/drm/i915/i915_pci.c
465
.has_coherent_ggtt = false,
sys/dev/pci/drm/i915/i915_pci.c
526
.has_coherent_ggtt = false, \
sys/dev/pci/drm/i915/i915_pci.c
607
.has_coherent_ggtt = false, \
sys/dev/pci/drm/i915/i915_pci.c
89
.has_coherent_ggtt = false, \
sys/dev/pci/drm/i915/i915_pci.c
896
return false;
sys/dev/pci/drm/i915/i915_pci.c
906
return false;
sys/dev/pci/drm/i915/i915_pci.c
908
for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
sys/dev/pci/drm/i915/i915_pci.c
930
return device_id_in_list(device_id, i915_modparams.force_probe, false);
sys/dev/pci/drm/i915/i915_pci.c
941
return false;
sys/dev/pci/drm/i915/i915_pci.c
944
return false;
sys/dev/pci/drm/i915/i915_pci.c
947
return false;
sys/dev/pci/drm/i915/i915_perf.c
1460
bool found = false;
sys/dev/pci/drm/i915/i915_perf.c
2148
stream, cs, false /* restore */, CS_GPR(i),
sys/dev/pci/drm/i915/i915_perf.c
2151
stream, cs, false /* restore */, mi_predicate_result,
sys/dev/pci/drm/i915/i915_perf.c
3082
stream->pollin = false;
sys/dev/pci/drm/i915/i915_perf.c
3514
stream->pollin = false;
sys/dev/pci/drm/i915/i915_perf.c
3638
stream->enabled = false;
sys/dev/pci/drm/i915/i915_perf.c
3878
privileged_op = false;
sys/dev/pci/drm/i915/i915_perf.c
3881
privileged_op = false;
sys/dev/pci/drm/i915/i915_perf.c
4014
bool config_instance = false;
sys/dev/pci/drm/i915/i915_perf.c
4015
bool config_class = false;
sys/dev/pci/drm/i915/i915_perf.c
4016
bool config_sseu = false;
sys/dev/pci/drm/i915/i915_perf.c
4363
return false;
sys/dev/pci/drm/i915/i915_perf.c
4375
return false;
sys/dev/pci/drm/i915/i915_perf.c
4506
return false;
sys/dev/pci/drm/i915/i915_pmu.c
1222
pmu->registered = false;
sys/dev/pci/drm/i915/i915_pmu.c
315
pmu->timer_enabled = false;
sys/dev/pci/drm/i915/i915_pmu.c
936
.global = false, \
sys/dev/pci/drm/i915/i915_query.c
465
return query_perf_config_data(i915, query_item, false);
sys/dev/pci/drm/i915/i915_request.c
1483
return false;
sys/dev/pci/drm/i915/i915_request.c
2002
return false;
sys/dev/pci/drm/i915/i915_request.c
2030
return false;
sys/dev/pci/drm/i915/i915_request.c
2161
__intel_engine_flush_submission(rq->engine, false);
sys/dev/pci/drm/i915/i915_request.c
231
return false;
sys/dev/pci/drm/i915/i915_request.c
2345
found = false;
sys/dev/pci/drm/i915/i915_request.c
267
bool ret = false;
sys/dev/pci/drm/i915/i915_request.c
406
return false;
sys/dev/pci/drm/i915/i915_request.c
488
bool inflight = false;
sys/dev/pci/drm/i915/i915_request.c
491
return false;
sys/dev/pci/drm/i915/i915_request.c
530
return false;
sys/dev/pci/drm/i915/i915_request.c
598
return false;
sys/dev/pci/drm/i915/i915_request.c
629
return false;
sys/dev/pci/drm/i915/i915_request.c
634
return false;
sys/dev/pci/drm/i915/i915_request.c
659
bool result = false;
sys/dev/pci/drm/i915/i915_request.h
581
return false;
sys/dev/pci/drm/i915/i915_scatterlist.c
22
return false;
sys/dev/pci/drm/i915/i915_scatterlist.c
25
return false;
sys/dev/pci/drm/i915/i915_scatterlist.h
112
for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
sys/dev/pci/drm/i915/i915_scatterlist.h
116
(__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
sys/dev/pci/drm/i915/i915_scheduler.c
349
bool ret = false;
sys/dev/pci/drm/i915/i915_scheduler.c
464
return false;
sys/dev/pci/drm/i915/i915_scheduler.c
83
first = false;
sys/dev/pci/drm/i915/i915_scheduler.h
78
sched_engine->no_priolist = false;
sys/dev/pci/drm/i915/i915_sw_fence.c
233
return false;
sys/dev/pci/drm/i915/i915_sw_fence.c
288
return false;
sys/dev/pci/drm/i915/i915_sw_fence.c
301
return false;
sys/dev/pci/drm/i915/i915_sw_fence.c
336
return false;
sys/dev/pci/drm/i915/i915_sw_fence.c
505
ret = dma_fence_wait(dma, false);
sys/dev/pci/drm/i915/i915_switcheroo.c
74
return vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
sys/dev/pci/drm/i915/i915_syncmap.c
158
return false;
sys/dev/pci/drm/i915/i915_syncmap.c
167
return false;
sys/dev/pci/drm/i915/i915_syncmap.c
180
return false;
sys/dev/pci/drm/i915/i915_syncmap.c
183
return false;
sys/dev/pci/drm/i915/i915_syncmap.c
190
return false;
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c
187
return false;
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c
217
return false;
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c
339
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/i915/i915_utils.c
54
return false;
sys/dev/pci/drm/i915/i915_utils.h
158
return false;
sys/dev/pci/drm/i915/i915_utils.h
55
#define i915_error_injected() false
sys/dev/pci/drm/i915/i915_vma.c
1858
release_references(vma, vma->vm->gt, false);
sys/dev/pci/drm/i915/i915_vma.c
1870
vma->vm_ddestroy = false;
sys/dev/pci/drm/i915/i915_vma.c
2126
dma_fence_wait(unbind_fence, false);
sys/dev/pci/drm/i915/i915_vma.c
2168
__i915_vma_evict(vma, false);
sys/dev/pci/drm/i915/i915_vma.c
701
return false;
sys/dev/pci/drm/i915/i915_vma.c
728
return false;
sys/dev/pci/drm/i915/i915_vma.c
772
return false;
sys/dev/pci/drm/i915/i915_vma.c
777
return false;
sys/dev/pci/drm/i915/i915_vma.c
966
return false;
sys/dev/pci/drm/i915/i915_vma.c
969
return false;
sys/dev/pci/drm/i915/i915_vma_resource.c
419
dma_fence_wait(fence, false);
sys/dev/pci/drm/i915/i915_vma_resource.c
99
rb_insert_color_cached(&node->rb, root, false);
sys/dev/pci/drm/i915/intel_cpu_info.c
42
bool intel_match_g8_cpu(void) { return false; }
sys/dev/pci/drm/i915/intel_device_info.c
226
return false;
sys/dev/pci/drm/i915/intel_gvt.c
67
return false;
sys/dev/pci/drm/i915/intel_memory_region.c
185
return false;
sys/dev/pci/drm/i915/intel_pcode.c
119
err = __snb_pcode_rw(uncore, mbox, &val, NULL, 250, timeout_ms, false);
sys/dev/pci/drm/i915/intel_region_ttm.c
38
drm->vma_offset_manager, false, false);
sys/dev/pci/drm/i915/intel_region_ttm.c
42
drm->vma_offset_manager, false, false);
sys/dev/pci/drm/i915/intel_region_ttm.c
94
ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
sys/dev/pci/drm/i915/intel_runtime_pm.c
199
return __intel_runtime_pm_get(rpm, false);
sys/dev/pci/drm/i915/intel_runtime_pm.c
265
return __intel_runtime_pm_get_if_active(rpm, false);
sys/dev/pci/drm/i915/intel_runtime_pm.c
324
__intel_runtime_pm_put(rpm, wref, false);
sys/dev/pci/drm/i915/intel_uncore.c
1205
return false;
sys/dev/pci/drm/i915/intel_uncore.c
1826
return false;
sys/dev/pci/drm/i915/intel_uncore.c
1852
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1865
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1913
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
2013
unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, false)
sys/dev/pci/drm/i915/intel_uncore.c
2017
unclaimed_reg_debug_footer(uncore, reg, false); \
sys/dev/pci/drm/i915/intel_uncore.c
2848
trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
sys/dev/pci/drm/i915/intel_uncore.c
2861
return false;
sys/dev/pci/drm/i915/intel_uncore.c
2873
bool ret = false;
sys/dev/pci/drm/i915/intel_uncore.c
2876
return false;
sys/dev/pci/drm/i915/intel_uncore.c
447
if (xchg(&domain->active, false))
sys/dev/pci/drm/i915/intel_uncore.c
474
if (xchg(&domain->active, false))
sys/dev/pci/drm/i915/intel_uncore.c
511
smp_store_mb(domain->active, false);
sys/dev/pci/drm/i915/intel_uncore.c
558
return false;
sys/dev/pci/drm/i915/intel_uncore.c
588
return false;
sys/dev/pci/drm/i915/intel_uncore.c
613
bool ret = false;
sys/dev/pci/drm/i915/intel_uncore.c
618
return false;
sys/dev/pci/drm/i915/intel_uncore.c
837
__intel_uncore_forcewake_put(uncore, fw_domains, false);
sys/dev/pci/drm/i915/intel_uncore.c
870
WRITE_ONCE(domain->active, false);
sys/dev/pci/drm/i915/intel_uncore.c
892
__intel_uncore_forcewake_put(uncore, fw_domains, false);
sys/dev/pci/drm/i915/intel_uncore.h
375
__uncore_read(read16_notrace, 16, w, false)
sys/dev/pci/drm/i915/intel_uncore.h
376
__uncore_read(read_notrace, 32, l, false)
sys/dev/pci/drm/i915/intel_uncore.h
381
__uncore_write(write_notrace, 32, l, false)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
200
bool is_full_feature = false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
249
i915->pxp->arb_is_valid = false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
264
pxp->arb_is_valid = false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
285
bool bound = false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
316
intel_pxp_terminate(pxp, false);
sys/dev/pci/drm/i915/pxp/intel_pxp.c
380
return false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
80
kcr_pxp_set_status(pxp, false);
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
205
return false;
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
32
return false;
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
40
return false;
sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c
100
pxp->irq_enabled = false;
sys/dev/pci/drm/i915/pxp/intel_pxp_pm.c
33
pxp->hw_state_invalidated = false;
sys/dev/pci/drm/i915/pxp/intel_pxp_pm.c
67
_pxp_resume(pxp, false);
sys/dev/pci/drm/i915/pxp/intel_pxp_pm.c
75
pxp->arb_is_valid = false;
sys/dev/pci/drm/i915/pxp/intel_pxp_pm.c
79
pxp->hw_state_invalidated = false;
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
105
ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false);
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
59
pxp->arb_is_valid = false;
sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
332
pxp->pxp_component_added = false;
sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
38
return false;
sys/dev/pci/drm/i915/selftests/i915_gem_evict.c
358
for_i915_gem_ww(&ww, err, false) {
sys/dev/pci/drm/i915/selftests/i915_gem_evict.c
466
igt_evict_ctl.fail_if_busy = false;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
105
obj->mm.dirty = false;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
183
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
329
i915_gem_ww_ctx_init(&ww, false);
sys/dev/pci/drm/i915/selftests/i915_request.c
1537
return false;
sys/dev/pci/drm/i915/selftests/i915_request.c
165
if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
sys/dev/pci/drm/i915/selftests/i915_request.c
177
if (dma_fence_wait_timeout(&request->fence, false, T / 2) != -ETIME) {
sys/dev/pci/drm/i915/selftests/i915_request.c
182
if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
sys/dev/pci/drm/i915/selftests/i915_request.c
192
if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
sys/dev/pci/drm/i915/selftests/i915_request.c
2589
struct signal_cb cb = { .seen = false };
sys/dev/pci/drm/i915/selftests/i915_request.c
2992
busy = false;
sys/dev/pci/drm/i915/selftests/i915_request.c
3067
busy = false;
sys/dev/pci/drm/i915/selftests/i915_request.c
3143
busy = false;
sys/dev/pci/drm/i915/selftests/i915_request.c
503
threads[n].stop = false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
332
allow = false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
344
result = false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
352
result = false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
465
return false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
481
bool skip = false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
498
false) >= sizeof(line));
sys/dev/pci/drm/i915/selftests/i915_selftest.c
502
skip = false;
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
92
return false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
233
return false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
236
return false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
45
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
51
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
57
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
730
return false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
737
return false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
757
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
763
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
770
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
776
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
782
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
787
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
79
ok = false;
sys/dev/pci/drm/i915/selftests/i915_vma.c
85
ok = false;
sys/dev/pci/drm/i915/selftests/igt_spinner.c
101
mode = intel_gt_coherent_map_type(spin->gt, spin->obj, false);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
148
return false;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
116
{ __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
sys/dev/pci/drm/i915/selftests/intel_uncore.c
117
{ __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
sys/dev/pci/drm/i915/selftests/intel_uncore.c
203
smp_store_mb(domain->active, false);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
240
smp_store_mb(domain->active, false);
sys/dev/pci/drm/i915/selftests/librapl.c
15
return false;
sys/dev/pci/drm/i915/soc/intel_gmch.c
122
i915->gmch.mchbar_need_disable = false;
sys/dev/pci/drm/i915/vlv_iosf_sb.c
186
opcode = unit_to_opcode(unit, false);
sys/dev/pci/drm/i915/vlv_suspend.c
300
trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
sys/dev/pci/drm/i915/vlv_suspend.c
395
vlv_wait_for_gt_wells(dev_priv, false);
sys/dev/pci/drm/i915/vlv_suspend.c
407
err = vlv_allow_gt_wake(dev_priv, false);
sys/dev/pci/drm/i915/vlv_suspend.c
413
err = vlv_force_gfx_clock(dev_priv, false);
sys/dev/pci/drm/i915/vlv_suspend.c
423
vlv_force_gfx_clock(dev_priv, false);
sys/dev/pci/drm/i915/vlv_suspend.c
449
err = vlv_force_gfx_clock(dev_priv, false);
sys/dev/pci/drm/include/asm/cpufeature.h
34
return false;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
1011
return false;
sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h
140
return false;
sys/dev/pci/drm/include/drm/drm_bridge.h
1393
return false;
sys/dev/pci/drm/include/drm/drm_cache.h
49
return false;
sys/dev/pci/drm/include/drm/drm_cache.h
51
return false;
sys/dev/pci/drm/include/drm/drm_cache.h
69
return false;
sys/dev/pci/drm/include/drm/drm_cache.h
77
return false;
sys/dev/pci/drm/include/drm/drm_drv.h
525
return false;
sys/dev/pci/drm/include/drm/drm_format_helper.h
50
__DRM_FORMAT_CONV_STATE_INIT(NULL, 0, false)
sys/dev/pci/drm/include/drm/drm_panel.h
368
return false;
sys/dev/pci/drm/include/drm/drm_util.h
65
return false;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
533
#define class_ttm_bo_lru_cursor_is_conditional false
sys/dev/pci/drm/include/linux/apple-gmux.h
9
return false;
sys/dev/pci/drm/include/linux/bitmap.h
114
return false;
sys/dev/pci/drm/include/linux/capability.h
29
return false;
sys/dev/pci/drm/include/linux/cc_platform.h
13
return false;
sys/dev/pci/drm/include/linux/completion.h
157
return false;
sys/dev/pci/drm/include/linux/console.h
27
return false;
sys/dev/pci/drm/include/linux/device.h
171
#define dev_is_removable(x) false
sys/dev/pci/drm/include/linux/dma-buf.h
85
return false;
sys/dev/pci/drm/include/linux/dma-fence.h
120
return false;
sys/dev/pci/drm/include/linux/dma-mapping.h
45
return false;
sys/dev/pci/drm/include/linux/hashtable.h
42
return false;
sys/dev/pci/drm/include/linux/interrupt.h
80
ts->use_callback = false;
sys/dev/pci/drm/include/linux/iopoll.h
42
poll_timeout_us((val) = (op)(addr), cond, sleep_us, timeout_us, false)
sys/dev/pci/drm/include/linux/iosys-map.h
70
ism->is_iomem = false;
sys/dev/pci/drm/include/linux/iosys-map.h
87
ism->is_iomem = false;
sys/dev/pci/drm/include/linux/mm.h
101
return false;
sys/dev/pci/drm/include/linux/pci.h
277
return false;
sys/dev/pci/drm/include/linux/pci.h
473
return false;
sys/dev/pci/drm/include/linux/pci.h
564
return false;
sys/dev/pci/drm/include/linux/pm_qos.h
29
return false;
sys/dev/pci/drm/include/linux/preempt.h
50
return false;
sys/dev/pci/drm/include/linux/rbtree.h
193
rb_insert_color_cached(node, root, false);
sys/dev/pci/drm/include/linux/refcount.h
34
return false;
sys/dev/pci/drm/include/linux/refcount.h
40
return false;
sys/dev/pci/drm/include/linux/scatterlist.h
49
#define sg_is_chain(sg) false
sys/dev/pci/drm/include/linux/seq_buf.h
16
struct seq_buf name = { (char[bsize]) {0}, bsize, 0, false }
sys/dev/pci/drm/include/linux/tracepoint.h
12
static inline bool trace_##name##_enabled(void) { return false; }
sys/dev/pci/drm/include/linux/tracepoint.h
19
static inline bool trace_##name##_enabled(void) { return false; }
sys/dev/pci/drm/include/linux/vga_switcheroo.h
69
return false;
sys/dev/pci/drm/include/linux/workqueue.h
113
return false;
sys/dev/pci/drm/include/linux/workqueue.h
195
return false;
sys/dev/pci/drm/include/linux/workqueue.h
205
return false;
sys/dev/pci/drm/include/linux/ww_mutex.h
210
return __ww_mutex_lock(lock, ctx, false, false);
sys/dev/pci/drm/include/linux/ww_mutex.h
215
(void)__ww_mutex_lock(lock, ctx, true, false);
sys/dev/pci/drm/include/linux/ww_mutex.h
220
return __ww_mutex_lock(lock, ctx, false, true);
sys/dev/pci/drm/include/linux/ww_mutex.h
97
bool res = false;
sys/dev/pci/drm/include/video/nomodeset.h
9
return false;
sys/dev/pci/drm/include/xen/xen.h
9
return false;
sys/dev/pci/drm/linux_radix.c
86
return (false);
sys/dev/pci/drm/linux_radix.c
89
return (false);
sys/dev/pci/drm/radeon/atom.c
1197
ectx.abort = false;
sys/dev/pci/drm/radeon/atom.c
1389
return false;
sys/dev/pci/drm/radeon/atom.c
1409
return false;
sys/dev/pci/drm/radeon/atombios_crtc.c
1010
radeon_crtc->ss_enabled = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
1150
bool bypass_lut = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
1168
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/atombios_crtc.c
1442
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/atombios_crtc.c
1470
bool bypass_lut = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
1485
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/atombios_crtc.c
1650
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/atombios_crtc.c
1917
(dig->linkb == false))
sys/dev/pci/drm/radeon/atombios_crtc.c
2050
bool is_tvcv = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2103
return false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2112
return false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2114
return false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2120
return false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2158
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/atombios_crtc.c
2192
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
sys/dev/pci/drm/radeon/atombios_crtc.c
2201
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
sys/dev/pci/drm/radeon/atombios_crtc.c
294
radeon_crtc->enabled = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
94
bool is_tv = false, is_cv = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
965
radeon_crtc->ss_enabled = false;
sys/dev/pci/drm/radeon/atombios_dp.c
145
radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
sys/dev/pci/drm/radeon/atombios_dp.c
402
return false;
sys/dev/pci/drm/radeon/atombios_dp.c
506
return false;
sys/dev/pci/drm/radeon/atombios_dp.c
508
return false;
sys/dev/pci/drm/radeon/atombios_dp.c
674
clock_recovery = false;
sys/dev/pci/drm/radeon/atombios_dp.c
739
channel_eq = false;
sys/dev/pci/drm/radeon/atombios_dp.c
813
dp_info.use_dpencoder = false;
sys/dev/pci/drm/radeon/atombios_dp.c
831
dp_info.tp3_supported = false;
sys/dev/pci/drm/radeon/atombios_dp.c
833
dp_info.tp3_supported = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
1011
bool is_dp = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
1411
return false;
sys/dev/pci/drm/radeon/atombios_encoders.c
1660
bool travis_quirk = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
1756
radeon_dig_connector->edp_on = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
2226
atombios_yuv_setup(encoder, false);
sys/dev/pci/drm/radeon/atombios_encoders.c
2289
return false;
sys/dev/pci/drm/radeon/atombios_encoders.c
2317
return false;
sys/dev/pci/drm/radeon/atombios_encoders.c
2477
radeon_atom_output_lock(encoder, false);
sys/dev/pci/drm/radeon/atombios_encoders.c
2538
radeon_hdmi_enable(rdev, encoder, false);
sys/dev/pci/drm/radeon/atombios_encoders.c
2652
dig->linkb = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
2706
radeon_encoder->is_ext_encoder = false;
sys/dev/pci/drm/radeon/atombios_i2c.c
91
radeon_atom_copy_swap(buf, base, num, false);
sys/dev/pci/drm/radeon/btc_dpm.c
1594
return false;
sys/dev/pci/drm/radeon/btc_dpm.c
1649
eg_pi->ulv.supported = false;
sys/dev/pci/drm/radeon/btc_dpm.c
1697
eg_pi->uvd_enabled = false;
sys/dev/pci/drm/radeon/btc_dpm.c
1769
return false;
sys/dev/pci/drm/radeon/btc_dpm.c
1772
return false;
sys/dev/pci/drm/radeon/btc_dpm.c
1864
result = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2061
return false;
sys/dev/pci/drm/radeon/btc_dpm.c
2078
disable_mclk_switching = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2085
if (rdev->pm.dpm.ac_power == false) {
sys/dev/pci/drm/radeon/btc_dpm.c
2218
ps->dc_compatible = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2385
eg_pi->dynamic_ac_timing = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2433
ret = cypress_notify_smc_display_change(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2474
rv770_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2477
btc_enable_dynamic_pcie_gen2(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2481
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2486
btc_cg_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2489
btc_mg_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2492
btc_ls_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2497
cypress_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/btc_dpm.c
2537
eg_pi->ulv.supported = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2578
0, false, ÷rs);
sys/dev/pci/drm/radeon/btc_dpm.c
2620
pi->power_gating = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2626
eg_pi->ls_clock_gating = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2627
eg_pi->sclk_deep_sleep = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2634
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2641
pi->dcodt = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2654
eg_pi->pcie_performance_request = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2660
eg_pi->dll_default_on = false;
sys/dev/pci/drm/radeon/btc_dpm.c
2662
eg_pi->sclk_deep_sleep = false;
sys/dev/pci/drm/radeon/ci_dpm.c
1039
pi->fan_is_controlled_by_smc = false;
sys/dev/pci/drm/radeon/ci_dpm.c
1359
want_thermal_protection = false;
sys/dev/pci/drm/radeon/ci_dpm.c
1566
ret = ci_enable_sclk_mclk_dpm(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
1725
return ci_enable_sclk_mclk_dpm(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
224
pi->caps_cac = false;
sys/dev/pci/drm/radeon/ci_dpm.c
225
pi->caps_sq_ramping = false;
sys/dev/pci/drm/radeon/ci_dpm.c
226
pi->caps_db_ramping = false;
sys/dev/pci/drm/radeon/ci_dpm.c
227
pi->caps_td_ramping = false;
sys/dev/pci/drm/radeon/ci_dpm.c
228
pi->caps_tcp_ramping = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2289
bool voltage_found = false;
sys/dev/pci/drm/radeon/ci_dpm.c
233
pi->enable_bapm_feature = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2625
table->UvdLevel[count].VclkFrequency, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
2633
table->UvdLevel[count].DclkFrequency, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
2666
table->VceLevel[count].Frequency, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
2699
table->AcpLevel[count].Frequency, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
2731
table->SamuLevel[count].Frequency, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
2877
memory_level->StutterEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2878
memory_level->StrobeEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2879
memory_level->EdcReadEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2880
memory_level->EdcWriteEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2881
memory_level->RttEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2887
(pi->uvd_enabled == false) &&
sys/dev/pci/drm/radeon/ci_dpm.c
2910
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ci_dpm.c
2912
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ci_dpm.c
2918
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ci_dpm.c
2970
table->ACPILevel.SclkFrequency, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
3051
table->MemoryACPILevel.StutterEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3052
table->MemoryACPILevel.StrobeEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3053
table->MemoryACPILevel.EdcReadEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3054
table->MemoryACPILevel.EdcWriteEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3055
table->MemoryACPILevel.RttEnable = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3088
pi->ulv.supported = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3132
engine_clock, false, ÷rs);
sys/dev/pci/drm/radeon/ci_dpm.c
3340
dpm_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3662
dpm_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3681
pcie_table->dpm_levels[i].enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3692
pcie_table->dpm_levels[j].enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
3917
pi->uvd_enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
4075
cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
sys/dev/pci/drm/radeon/ci_dpm.c
4088
ret = ci_enable_vce_dpm(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
4423
result = false;
sys/dev/pci/drm/radeon/ci_dpm.c
4814
pi->pspp_notify_required = false;
sys/dev/pci/drm/radeon/ci_dpm.c
4819
if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
sys/dev/pci/drm/radeon/ci_dpm.c
4826
if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
sys/dev/pci/drm/radeon/ci_dpm.c
4862
radeon_acpi_pcie_performance_request(rdev, request, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5048
pi->mem_gddr5 = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5128
pi->caps_dynamic_ac_timing = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5176
ret = ci_notify_smc_display_change(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5238
ret = ci_thermal_enable_alert(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5269
ci_dpm_powergate_uvd(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5277
ci_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5278
ci_enable_power_containment(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5279
ci_enable_smc_cac(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5280
ci_enable_didt(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5281
ci_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5282
ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5284
ci_enable_ds_master_switch(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5285
ci_enable_ulv(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5290
ci_enable_thermal_based_sclk_dpm(rdev, false);
sys/dev/pci/drm/radeon/ci_dpm.c
5698
pi->dll_default_on = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5732
pi->caps_fps = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5734
pi->caps_sclk_throttle_low_notification = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5780
pi->uvd_enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5863
pi->pcie_performance_request = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5872
pi->caps_sclk_ss_support = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5873
pi->caps_mclk_ss_support = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5880
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/ci_dpm.c
5884
pi->uvd_power_gated = false;
sys/dev/pci/drm/radeon/ci_dpm.c
680
pi->cac_enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
686
pi->cac_enabled = false;
sys/dev/pci/drm/radeon/ci_dpm.c
720
bool adjust_polarity = false; /* ??? */
sys/dev/pci/drm/radeon/ci_dpm.c
761
return false;
sys/dev/pci/drm/radeon/ci_dpm.c
787
disable_mclk_switching = false;
sys/dev/pci/drm/radeon/ci_dpm.c
792
pi->battery_state = false;
sys/dev/pci/drm/radeon/ci_dpm.c
799
if (rdev->pm.dpm.ac_power == false) {
sys/dev/pci/drm/radeon/ci_dpm.c
885
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/ci_dpm.c
915
pi->fan_ctrl_is_in_default_mode = false;
sys/dev/pci/drm/radeon/ci_dpm.c
939
rdev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/radeon/ci_dpm.c
946
rdev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/radeon/ci_dpm.c
998
rdev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/radeon/ci_smc.c
163
return false;
sys/dev/pci/drm/radeon/cik.c
1977
bool new_smc = false;
sys/dev/pci/drm/radeon/cik.c
2271
rdev->new_fw = false;
sys/dev/pci/drm/radeon/cik.c
3467
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/cik.c
3669
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/cik.c
3698
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/cik.c
3793
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/cik.c
3800
r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/cik.c
3871
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/cik.c
3891
cik_cp_gfx_enable(rdev, false);
sys/dev/pci/drm/radeon/cik.c
4018
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/cik.c
4033
cik_cp_gfx_enable(rdev, false);
sys/dev/pci/drm/radeon/cik.c
4103
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/cik.c
4232
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
sys/dev/pci/drm/radeon/cik.c
4233
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
sys/dev/pci/drm/radeon/cik.c
4253
cik_cp_compute_enable(rdev, false);
sys/dev/pci/drm/radeon/cik.c
4336
cik_cp_compute_enable(rdev, false);
sys/dev/pci/drm/radeon/cik.c
4345
r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
sys/dev/pci/drm/radeon/cik.c
4363
r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
sys/dev/pci/drm/radeon/cik.c
4404
r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
sys/dev/pci/drm/radeon/cik.c
4575
r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
sys/dev/pci/drm/radeon/cik.c
4739
rdev->ring[idx].ready = false;
sys/dev/pci/drm/radeon/cik.c
4775
cik_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/cik.c
5235
r600_set_bios_scratch_engine_hung(rdev, false);
sys/dev/pci/drm/radeon/cik.c
5257
return false;
sys/dev/pci/drm/radeon/cik.c
5879
cik_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/cik.c
5980
cik_enable_lbpw(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6011
cik_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6283
cik_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6289
cik_enable_cgcg(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6290
cik_enable_mgcg(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6347
RADEON_CG_BLOCK_HDP), false);
sys/dev/pci/drm/radeon/cik.c
6349
cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false);
sys/dev/pci/drm/radeon/cik.c
6782
cik_update_gfx_pg(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6784
cik_enable_cp_pg(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6785
cik_enable_gds_pg(rdev, false);
sys/dev/pci/drm/radeon/cik.c
6843
rdev->ih.enabled = false;
sys/dev/pci/drm/radeon/cik.c
7547
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/cik.c
7548
bool queue_dp = false;
sys/dev/pci/drm/radeon/cik.c
7549
bool queue_reset = false;
sys/dev/pci/drm/radeon/cik.c
7551
bool queue_thermal = false;
sys/dev/pci/drm/radeon/cik.c
8027
rdev->pm.dpm.thermal.high_to_low = false;
sys/dev/pci/drm/radeon/cik.c
8127
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/cik.c
8199
rdev->has_vce = false;
sys/dev/pci/drm/radeon/cik.c
8497
rdev->accel_working = false;
sys/dev/pci/drm/radeon/cik.c
8519
cik_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/cik.c
8520
cik_sdma_enable(rdev, false);
sys/dev/pci/drm/radeon/cik.c
8681
rdev->accel_working = false;
sys/dev/pci/drm/radeon/cik.c
9180
return false;
sys/dev/pci/drm/radeon/cik.c
9200
return false;
sys/dev/pci/drm/radeon/cik.c
9235
return false;
sys/dev/pci/drm/radeon/cik.c
9271
radeon_dpm_get_mclk(rdev, false) * 10;
sys/dev/pci/drm/radeon/cik.c
9273
radeon_dpm_get_sclk(rdev, false) * 10;
sys/dev/pci/drm/radeon/cik.c
9283
wm_high.interlaced = false;
sys/dev/pci/drm/radeon/cik.c
9323
wm_low.interlaced = false;
sys/dev/pci/drm/radeon/cik.c
9435
clock, false, ÷rs);
sys/dev/pci/drm/radeon/cik.c
9474
ecclk, false, ÷rs);
sys/dev/pci/drm/radeon/cik.c
9665
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/radeon/cik.c
9666
bool disable_clkreq = false;
sys/dev/pci/drm/radeon/cik.c
9744
clk_req_support = false;
sys/dev/pci/drm/radeon/cik.c
9749
clk_req_support = false;
sys/dev/pci/drm/radeon/cik_sdma.c
268
rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
sys/dev/pci/drm/radeon/cik_sdma.c
269
rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
sys/dev/pci/drm/radeon/cik_sdma.c
427
ring->ready = false;
sys/dev/pci/drm/radeon/cik_sdma.c
469
cik_sdma_enable(rdev, false);
sys/dev/pci/drm/radeon/cik_sdma.c
559
cik_sdma_enable(rdev, false);
sys/dev/pci/drm/radeon/cik_sdma.c
602
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/cik_sdma.c
628
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/cik_sdma.c
673
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/cik_sdma.c
733
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/cik_sdma.c
739
r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/cik_sdma.c
786
return false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1584
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1599
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1607
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1796
eg_pi->pcie_performance_request_registered = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1841
eg_pi->dynamic_ac_timing = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1894
ret = cypress_notify_smc_display_change(rdev, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
1929
rv770_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
1932
cypress_enable_dynamic_pcie_gen2(rdev, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
1936
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
1941
cypress_gfx_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
1944
cypress_mg_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
1949
cypress_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
2039
eg_pi->ulv.supported = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2059
0, false, ÷rs);
sys/dev/pci/drm/radeon/cypress_dpm.c
2089
pi->power_gating = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2093
pi->gfx_clock_gating = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2099
eg_pi->ls_clock_gating = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2100
eg_pi->sclk_deep_sleep = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2107
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2114
pi->dcodt = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2127
eg_pi->pcie_performance_request = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2135
eg_pi->dll_default_on = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2137
eg_pi->sclk_deep_sleep = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
2166
return false;
sys/dev/pci/drm/radeon/cypress_dpm.c
319
eg_pi->pcie_performance_request_registered = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
342
pi->pcie_gen2 = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
376
cypress_pcie_performance_request(rdev, request, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
398
cypress_pcie_performance_request(rdev, request, false);
sys/dev/pci/drm/radeon/cypress_dpm.c
426
bool strobe_mode = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
721
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/cypress_dpm.c
723
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/dce6_afmt.c
73
rdev->audio.pin[i].connected = false;
sys/dev/pci/drm/radeon/evergreen.c
1149
clock, false, ÷rs);
sys/dev/pci/drm/radeon/evergreen.c
1353
return false;
sys/dev/pci/drm/radeon/evergreen.c
1366
return false;
sys/dev/pci/drm/radeon/evergreen.c
1729
return false;
sys/dev/pci/drm/radeon/evergreen.c
2117
return false;
sys/dev/pci/drm/radeon/evergreen.c
2126
return false;
sys/dev/pci/drm/radeon/evergreen.c
2152
return false;
sys/dev/pci/drm/radeon/evergreen.c
2185
radeon_dpm_get_mclk(rdev, false) * 10;
sys/dev/pci/drm/radeon/evergreen.c
2187
radeon_dpm_get_sclk(rdev, false) * 10;
sys/dev/pci/drm/radeon/evergreen.c
2197
wm_high.interlaced = false;
sys/dev/pci/drm/radeon/evergreen.c
2224
wm_low.interlaced = false;
sys/dev/pci/drm/radeon/evergreen.c
2574
bool is_enabled = false;
sys/dev/pci/drm/radeon/evergreen.c
2575
bool found_crtc = false;
sys/dev/pci/drm/radeon/evergreen.c
2724
save->crtc_enabled[i] = false;
sys/dev/pci/drm/radeon/evergreen.c
2727
save->crtc_enabled[i] = false;
sys/dev/pci/drm/radeon/evergreen.c
3014
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/evergreen.c
3057
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/evergreen.c
3123
ring->ready = false;
sys/dev/pci/drm/radeon/evergreen.c
3818
return false;
sys/dev/pci/drm/radeon/evergreen.c
4076
r600_set_bios_scratch_engine_hung(rdev, false);
sys/dev/pci/drm/radeon/evergreen.c
4098
return false;
sys/dev/pci/drm/radeon/evergreen.c
4115
r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
sys/dev/pci/drm/radeon/evergreen.c
4127
r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
sys/dev/pci/drm/radeon/evergreen.c
4139
r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
sys/dev/pci/drm/radeon/evergreen.c
4181
r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
sys/dev/pci/drm/radeon/evergreen.c
4260
r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
sys/dev/pci/drm/radeon/evergreen.c
4338
r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
sys/dev/pci/drm/radeon/evergreen.c
4710
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/evergreen.c
4711
bool queue_hdmi = false;
sys/dev/pci/drm/radeon/evergreen.c
4712
bool queue_dp = false;
sys/dev/pci/drm/radeon/evergreen.c
4713
bool queue_thermal = false;
sys/dev/pci/drm/radeon/evergreen.c
4888
rdev->pm.dpm.thermal.high_to_low = false;
sys/dev/pci/drm/radeon/evergreen.c
4950
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/evergreen.c
5147
rdev->accel_working = false;
sys/dev/pci/drm/radeon/evergreen.c
5283
rdev->accel_working = false;
sys/dev/pci/drm/radeon/evergreen.c
5394
bool disable_l0s, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/radeon/evergreen.c
5400
bool fusion_platform = false;
sys/dev/pci/drm/radeon/evergreen.c
5421
disable_l0s = false;
sys/dev/pci/drm/radeon/evergreen_cs.c
1011
track->db_dirty = false;
sys/dev/pci/drm/radeon/evergreen_cs.c
168
track->sx_misc_kill_all_prims = false;
sys/dev/pci/drm/radeon/evergreen_cs.c
1764
return false;
sys/dev/pci/drm/radeon/evergreen_cs.c
1770
return false;
sys/dev/pci/drm/radeon/evergreen_cs.c
3435
return false;
sys/dev/pci/drm/radeon/evergreen_cs.c
965
track->streamout_dirty = false;
sys/dev/pci/drm/radeon/evergreen_cs.c
993
track->cb_dirty = false;
sys/dev/pci/drm/radeon/evergreen_dma.c
131
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/evergreen_dma.c
155
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/evergreen_dma.c
176
return false;
sys/dev/pci/drm/radeon/kv_dpm.c
1114
ret = kv_smc_bapm_enable(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1150
kv_smc_bapm_enable(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1153
kv_enable_nb_dpm(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1156
kv_dpm_powergate_acp(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1157
kv_dpm_powergate_samu(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1158
kv_dpm_powergate_vce(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1159
kv_dpm_powergate_uvd(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1161
kv_enable_smc_cac(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1162
kv_enable_didt(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1165
kv_enable_ulv(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1167
kv_enable_thermal_int(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1212
pi->uvd_power_gated = false;
sys/dev/pci/drm/radeon/kv_dpm.c
1213
pi->vce_power_gated = false;
sys/dev/pci/drm/radeon/kv_dpm.c
1214
pi->samu_power_gated = false;
sys/dev/pci/drm/radeon/kv_dpm.c
1215
pi->acp_power_gated = false;
sys/dev/pci/drm/radeon/kv_dpm.c
1303
kv_dpm_powergate_vce(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1305
cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1327
kv_enable_vce_dpm(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1443
cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1498
kv_update_samu_dpm(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1521
kv_update_acp_dpm(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
1626
pi->nb_dpm_enabled = false;
sys/dev/pci/drm/radeon/kv_dpm.c
1730
kv_freeze_sclk_dpm(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
2025
pi->battery_state = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2190
kv_dpm_power_level_enable(rdev, i, false);
sys/dev/pci/drm/radeon/kv_dpm.c
2323
pi->sys_info.nb_dpm_enable = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2543
pi->enable_nb_dpm = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2549
pi->enable_didt = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2559
pi->disable_nb_ps3_in_battery = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2565
pi->bapm_enable = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2567
pi->bapm_enable = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2572
pi->caps_sclk_throttle_low_notification = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2573
pi->caps_fps = false; /* true? */
sys/dev/pci/drm/radeon/kv_dpm.c
2576
pi->caps_vce_pg = false; /* XXX true */
sys/dev/pci/drm/radeon/kv_dpm.c
2577
pi->caps_samu_pg = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2578
pi->caps_acp_pg = false;
sys/dev/pci/drm/radeon/kv_dpm.c
2579
pi->caps_stable_p_state = false;
sys/dev/pci/drm/radeon/kv_dpm.c
284
pi->cac_enabled = false;
sys/dev/pci/drm/radeon/kv_dpm.c
289
pi->cac_enabled = false;
sys/dev/pci/drm/radeon/kv_dpm.c
383
sclk, false, ÷rs);
sys/dev/pci/drm/radeon/kv_dpm.c
497
kv_smc_dpm_enable(rdev, false);
sys/dev/pci/drm/radeon/kv_dpm.c
687
table->entries[i].vclk, false, ÷rs);
sys/dev/pci/drm/radeon/kv_dpm.c
693
table->entries[i].dclk, false, ÷rs);
sys/dev/pci/drm/radeon/kv_dpm.c
755
table->entries[i].evclk, false, ÷rs);
sys/dev/pci/drm/radeon/kv_dpm.c
818
table->entries[i].clk, false, ÷rs);
sys/dev/pci/drm/radeon/kv_dpm.c
877
table->entries[i].clk, false, ÷rs);
sys/dev/pci/drm/radeon/ni.c
1444
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni.c
1505
cayman_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/ni.c
1541
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/ni.c
1583
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/ni.c
1593
cayman_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/ni.c
1703
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni.c
1704
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni.c
1708
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni.c
1709
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni.c
1710
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni.c
1951
r600_set_bios_scratch_engine_hung(rdev, false);
sys/dev/pci/drm/radeon/ni.c
1973
return false;
sys/dev/pci/drm/radeon/ni.c
1994
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/ni.c
2062
rdev->has_vce = false;
sys/dev/pci/drm/radeon/ni.c
2299
rdev->accel_working = false;
sys/dev/pci/drm/radeon/ni.c
2310
cayman_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/ni.c
2431
rdev->accel_working = false;
sys/dev/pci/drm/radeon/ni.c
2698
ecclk, false, ÷rs);
sys/dev/pci/drm/radeon/ni_dma.c
174
rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni_dma.c
175
rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
sys/dev/pci/drm/radeon/ni_dma.c
251
ring->ready = false;
sys/dev/pci/drm/radeon/ni_dma.c
298
return false;
sys/dev/pci/drm/radeon/ni_dpm.c
1472
false, /* ??? */
sys/dev/pci/drm/radeon/ni_dpm.c
2018
engine_clock, false, ÷rs);
sys/dev/pci/drm/radeon/ni_dpm.c
2351
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ni_dpm.c
2353
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ni_dpm.c
2355
dll_state_on = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2471
if (ni_pi->enable_power_containment == false)
sys/dev/pci/drm/radeon/ni_dpm.c
2481
false, /* ??? */
sys/dev/pci/drm/radeon/ni_dpm.c
2561
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2564
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2567
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2570
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2573
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2612
ni_pi->pc_enabled = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2621
ni_pi->pc_enabled = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2678
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2682
ni_pi->enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
2816
result = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3147
if (ni_pi->enable_cac == false)
sys/dev/pci/drm/radeon/ni_dpm.c
3199
ni_pi->enable_cac = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3200
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3393
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3405
ni_pi->cac_enabled = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3410
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3426
if (eg_pi->pcie_performance_request_registered == false)
sys/dev/pci/drm/radeon/ni_dpm.c
3432
eg_pi->pcie_performance_request_registered = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3450
pi->pcie_gen2 = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3611
eg_pi->dynamic_ac_timing = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3680
ret = cypress_notify_smc_display_change(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3713
rv770_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3714
ni_enable_power_containment(rdev, boot_ps, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3715
ni_enable_smc_cac(rdev, boot_ps, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3716
cypress_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3717
rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3719
ni_enable_dynamic_pcie_gen2(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3723
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/ni_dpm.c
3728
ni_gfx_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3730
ni_mg_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3732
ni_ls_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3791
ret = ni_enable_power_containment(rdev, new_ps, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3796
ret = ni_enable_smc_cac(rdev, new_ps, false);
sys/dev/pci/drm/radeon/ni_dpm.c
3952
pi->acpi_pcie_gen2 = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4063
eg_pi->ulv.supported = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4106
0, false, ÷rs);
sys/dev/pci/drm/radeon/ni_dpm.c
4155
pi->power_gating = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4161
eg_pi->ls_clock_gating = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4162
eg_pi->sclk_deep_sleep = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4169
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4186
eg_pi->pcie_performance_request = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4189
eg_pi->dll_default_on = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4191
eg_pi->sclk_deep_sleep = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4240
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4241
ni_pi->enable_cac = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4242
ni_pi->enable_sq_ramping = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4245
ni_pi->driver_calculate_cac_leakage = false;
sys/dev/pci/drm/radeon/ni_dpm.c
4253
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/radeon/ni_dpm.c
781
return false;
sys/dev/pci/drm/radeon/ni_dpm.c
799
disable_mclk_switching = false;
sys/dev/pci/drm/radeon/ni_dpm.c
806
if (rdev->pm.dpm.ac_power == false) {
sys/dev/pci/drm/radeon/ni_dpm.c
897
ps->dc_compatible = false;
sys/dev/pci/drm/radeon/r100.c
1007
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r100.c
107
return false;
sys/dev/pci/drm/radeon/r100.c
1276
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/r100.c
1844
track->textures[i].roundup_w = false;
sys/dev/pci/drm/radeon/r100.c
1847
track->textures[i].roundup_h = false;
sys/dev/pci/drm/radeon/r100.c
1857
track->textures[i].use_pitch = false;
sys/dev/pci/drm/radeon/r100.c
2296
track->cb_dirty = false;
sys/dev/pci/drm/radeon/r100.c
2315
track->zb_dirty = false;
sys/dev/pci/drm/radeon/r100.c
233
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r100.c
2335
track->aa_dirty = false;
sys/dev/pci/drm/radeon/r100.c
238
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r100.c
2398
track->tex_dirty = false;
sys/dev/pci/drm/radeon/r100.c
2425
track->separate_cube = false;
sys/dev/pci/drm/radeon/r100.c
2426
track->aaresolve = false;
sys/dev/pci/drm/radeon/r100.c
2467
track->textures[i].enabled = false;
sys/dev/pci/drm/radeon/r100.c
2468
track->textures[i].lookup_disable = false;
sys/dev/pci/drm/radeon/r100.c
2555
return false;
sys/dev/pci/drm/radeon/r100.c
2644
bool force_dac2 = false;
sys/dev/pci/drm/radeon/r100.c
266
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r100.c
2732
rdev->mc.vram_is_ddr = false;
sys/dev/pci/drm/radeon/r100.c
287
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r100.c
3691
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r100.c
3753
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/r100.c
3758
r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/r100.c
3795
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/r100.c
3980
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r100.c
4075
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/r100.c
4117
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r100.c
526
return false;
sys/dev/pci/drm/radeon/r100.c
543
bool connected = false;
sys/dev/pci/drm/radeon/r100.c
784
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/r100.c
84
return false;
sys/dev/pci/drm/radeon/r100.c
89
return false;
sys/dev/pci/drm/radeon/r100.c
898
return false;
sys/dev/pci/drm/radeon/r100.c
974
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r200.c
127
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r200.c
423
track->textures[i].roundup_w = false;
sys/dev/pci/drm/radeon/r200.c
426
track->textures[i].roundup_h = false;
sys/dev/pci/drm/radeon/r300.c
1003
track->textures[i].roundup_w = false;
sys/dev/pci/drm/radeon/r300.c
1007
track->textures[i].roundup_h = false;
sys/dev/pci/drm/radeon/r300.c
1465
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r300.c
1537
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/r300.c
1587
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r300.c
333
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r300.c
841
track->z_enabled = false;
sys/dev/pci/drm/radeon/r420.c
224
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r420.c
239
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r420.c
335
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r420.c
413
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/r420.c
467
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r520.c
245
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r520.c
282
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/r520.c
326
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r600.c
1482
rdev->fastfb_working = false;
sys/dev/pci/drm/radeon/r600.c
1493
if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
sys/dev/pci/drm/radeon/r600.c
1520
r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
sys/dev/pci/drm/radeon/r600.c
1545
r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
sys/dev/pci/drm/radeon/r600.c
1608
return false;
sys/dev/pci/drm/radeon/r600.c
1907
r600_set_bios_scratch_engine_hung(rdev, false);
sys/dev/pci/drm/radeon/r600.c
1929
return false;
sys/dev/pci/drm/radeon/r600.c
2429
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/r600.c
2709
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r600.c
2770
ring->ready = false;
sys/dev/pci/drm/radeon/r600.c
2845
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r600.c
2988
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/r600.c
3022
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r600.c
3057
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/r600.c
3222
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r600.c
3332
rdev->accel_working = false;
sys/dev/pci/drm/radeon/r600.c
3419
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/r600.c
3424
r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/r600.c
3492
r = radeon_bo_reserve(rdev->ih.ring_obj, false);
sys/dev/pci/drm/radeon/r600.c
3518
r = radeon_bo_reserve(rdev->ih.ring_obj, false);
sys/dev/pci/drm/radeon/r600.c
3614
rdev->ih.enabled = false;
sys/dev/pci/drm/radeon/r600.c
380
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r600.c
385
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r600.c
4098
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/r600.c
4099
bool queue_hdmi = false;
sys/dev/pci/drm/radeon/r600.c
4100
bool queue_thermal = false;
sys/dev/pci/drm/radeon/r600.c
421
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r600.c
4305
rdev->pm.dpm.thermal.high_to_low = false;
sys/dev/pci/drm/radeon/r600.c
445
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r600.c
477
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r600.c
483
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r600.c
489
rdev->pm.dynpm_can_downclock = false;
sys/dev/pci/drm/radeon/r600.c
504
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r600.c
511
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r600.c
517
rdev->pm.dynpm_can_upclock = false;
sys/dev/pci/drm/radeon/r600.c
798
return false;
sys/dev/pci/drm/radeon/r600.c
806
bool connected = false;
sys/dev/pci/drm/radeon/r600_cs.c
1527
is_array = false;
sys/dev/pci/drm/radeon/r600_cs.c
1622
return false;
sys/dev/pci/drm/radeon/r600_cs.c
1628
return false;
sys/dev/pci/drm/radeon/r600_cs.c
180
return false;
sys/dev/pci/drm/radeon/r600_cs.c
185
return false;
sys/dev/pci/drm/radeon/r600_cs.c
191
return false;
sys/dev/pci/drm/radeon/r600_cs.c
194
return false;
sys/dev/pci/drm/radeon/r600_cs.c
199
return false;
sys/dev/pci/drm/radeon/r600_cs.c
320
track->is_resolve = false;
sys/dev/pci/drm/radeon/r600_cs.c
346
track->sx_misc_kill_all_prims = false;
sys/dev/pci/drm/radeon/r600_cs.c
704
track->db_dirty = false;
sys/dev/pci/drm/radeon/r600_cs.c
737
track->streamout_dirty = false;
sys/dev/pci/drm/radeon/r600_cs.c
771
track->cb_dirty = false;
sys/dev/pci/drm/radeon/r600_dma.c
108
rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
sys/dev/pci/drm/radeon/r600_dma.c
175
ring->ready = false;
sys/dev/pci/drm/radeon/r600_dma.c
213
return false;
sys/dev/pci/drm/radeon/r600_dma.c
257
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r600_dma.c
364
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/r600_dma.c
370
r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/r600_dma.c
467
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/r600_dma.c
491
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/r600_dpm.c
1025
rdev->pm.dpm.power_control = false;
sys/dev/pci/drm/radeon/r600_dpm.c
298
return false;
sys/dev/pci/drm/radeon/r600_dpm.c
685
r600_enable_sclk_control(rdev, false);
sys/dev/pci/drm/radeon/r600_dpm.c
686
r600_enable_mclk_control(rdev, false);
sys/dev/pci/drm/radeon/r600_dpm.c
695
r600_enable_spll_bypass(rdev, false);
sys/dev/pci/drm/radeon/r600_dpm.c
700
r600_enable_spll_bypass(rdev, false);
sys/dev/pci/drm/radeon/r600_dpm.c
709
r600_dynamicpm_enable(rdev, false);
sys/dev/pci/drm/radeon/r600_dpm.c
734
return false;
sys/dev/pci/drm/radeon/r600_dpm.c
776
return false; /* need special handling */
sys/dev/pci/drm/radeon/r600_dpm.c
781
return false;
sys/dev/pci/drm/radeon/r600_hdmi.c
122
bool changed = false;
sys/dev/pci/drm/radeon/radeon.h
2550
#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
sys/dev/pci/drm/radeon/radeon.h
2553
r100_mm_rreg(rdev, (reg), false))
sys/dev/pci/drm/radeon/radeon.h
2554
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
sys/dev/pci/drm/radeon/radeon.h
2603
#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
sys/dev/pci/drm/radeon/radeon.h
2743
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
sys/dev/pci/drm/radeon/radeon.h
437
return false;
sys/dev/pci/drm/radeon/radeon_acpi.c
285
n->enabled = false;
sys/dev/pci/drm/radeon/radeon_acpi.c
44
static inline bool radeon_atpx_dgpu_req_power_for_displays(void) { return false; }
sys/dev/pci/drm/radeon/radeon_acpi.c
553
return false;
sys/dev/pci/drm/radeon/radeon_acpi.c
779
atif->notification_cfg.enabled = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2328
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2329
rdev->has_vce = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2408
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2478
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2479
rdev->has_vce = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2482
rdev->has_vce = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2705
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/radeon_asic.c
2707
rdev->has_vce = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1041
bios_connectors[i].ddc_bus.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1046
bios_connectors[j].ddc_bus.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1061
bios_connectors[j].valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
111
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
116
i2c.mm_i2c = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
123
i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1296
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1309
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1329
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1378
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
140
i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1418
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1523
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1527
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1612
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1691
lvds->linkb = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1697
bool bad_record = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1806
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1812
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1851
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
210
gpio.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2168
false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2204
false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2240
false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2570
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2575
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2886
true : false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2889
dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2898
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2900
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
sys/dev/pci/drm/radeon/radeon_atombios.c
2918
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
sys/dev/pci/drm/radeon/radeon_atombios.c
2920
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
sys/dev/pci/drm/radeon/radeon_atombios.c
318
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
326
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
334
i2c_bus->valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
344
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
3484
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
3496
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
3501
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
3505
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
352
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
362
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
427
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
437
(i2c_bus->valid == false) &&
sys/dev/pci/drm/radeon/radeon_atombios.c
543
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
546
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
644
router.ddc_valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
645
router.cd_valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
753
ddc_bus.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
906
router.ddc_valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
907
router.cd_valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
911
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
916
return false;
sys/dev/pci/drm/radeon/radeon_atombios.c
937
bios_connectors[i].valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
964
bios_connectors[i].ddc_bus.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
967
bios_connectors[i].ddc_bus.valid = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
970
bios_connectors[i].ddc_bus.valid = false;
sys/dev/pci/drm/radeon/radeon_audio.c
274
rdev->audio.pin[i].connected = false;
sys/dev/pci/drm/radeon/radeon_audio.c
437
rdev->audio.enabled = false;
sys/dev/pci/drm/radeon/radeon_audio.c
666
radeon_audio_set_mute(encoder, false);
sys/dev/pci/drm/radeon/radeon_audio.c
761
*enabled = false;
sys/dev/pci/drm/radeon/radeon_audio.c
852
rdev->audio.component_registered = false;
sys/dev/pci/drm/radeon/radeon_benchmark.c
101
r = radeon_bo_reserve(sobj, false);
sys/dev/pci/drm/radeon/radeon_benchmark.c
113
r = radeon_bo_reserve(dobj, false);
sys/dev/pci/drm/radeon/radeon_benchmark.c
146
r = radeon_bo_reserve(sobj, false);
sys/dev/pci/drm/radeon/radeon_benchmark.c
154
r = radeon_bo_reserve(dobj, false);
sys/dev/pci/drm/radeon/radeon_benchmark.c
65
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_bios.c
103
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
112
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
129
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
137
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
142
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
167
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
171
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
181
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
198
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
202
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
217
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
230
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
236
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
251
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
256
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
262
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
322
bool found = false;
sys/dev/pci/drm/radeon/radeon_bios.c
326
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
359
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
365
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
379
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
386
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
526
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
67
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
73
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
756
bool r = false;
sys/dev/pci/drm/radeon/radeon_bios.c
759
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
78
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
810
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
83
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
833
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
855
rdev->is_atom_bios = false;
sys/dev/pci/drm/radeon/radeon_bios.c
863
return false;
sys/dev/pci/drm/radeon/radeon_bios.c
98
return false;
sys/dev/pci/drm/radeon/radeon_clocks.c
121
return false;
sys/dev/pci/drm/radeon/radeon_clocks.c
125
return false;
sys/dev/pci/drm/radeon/radeon_clocks.c
182
return false;
sys/dev/pci/drm/radeon/radeon_clocks.c
204
return false;
sys/dev/pci/drm/radeon/radeon_clocks.c
258
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
1143
lvds->use_bios_dividers = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1372
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
1439
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
1618
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1661
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1710
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1758
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1799
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1836
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1872
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1913
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
1954
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2078
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2139
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2187
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2203
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2226
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2234
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2248
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2254
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2260
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2536
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
2581
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2602
ddc_i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2753
false;
sys/dev/pci/drm/radeon/radeon_combios.c
2769
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
2893
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
3009
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
379
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
387
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
559
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
570
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
583
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
595
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
612
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
615
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
620
i2c.hw_capable = false;
sys/dev/pci/drm/radeon/radeon_combios.c
623
i2c.mm_i2c = false;
sys/dev/pci/drm/radeon/radeon_combios.c
631
i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
644
i2c.valid = false;
sys/dev/pci/drm/radeon/radeon_combios.c
803
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
813
return false;
sys/dev/pci/drm/radeon/radeon_combios.c
821
return false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1009
dret = radeon_ddc_probe(radeon_connector, false);
sys/dev/pci/drm/radeon/radeon_connectors.c
1011
radeon_connector->detected_by_load = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1109
tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false);
sys/dev/pci/drm/radeon/radeon_connectors.c
1154
ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
sys/dev/pci/drm/radeon/radeon_connectors.c
1198
return false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1222
bool dret = false, broken_edid = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1234
radeon_connector->detected_hpd_without_ddc = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1243
dret = radeon_ddc_probe(radeon_connector, false);
sys/dev/pci/drm/radeon/radeon_connectors.c
1259
radeon_connector->detected_by_load = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1352
radeon_connector->use_digital = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1364
radeon_connector->use_digital = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1371
if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
sys/dev/pci/drm/radeon/radeon_connectors.c
1444
radeon_connector->use_digital = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1597
bool found = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1619
return false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1703
if (radeon_ddc_probe(radeon_connector, false))
sys/dev/pci/drm/radeon/radeon_connectors.c
1851
bool shared_ddc = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1852
bool is_dp_bridge = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1853
bool has_aux = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1879
radeon_connector->shared_ddc = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1880
shared_ddc = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2003
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2023
connector->interlace_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2024
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2149
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2205
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2260
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2286
connector->interlace_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2287
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2306
connector->interlace_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2307
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2331
connector->interlace_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2332
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
237
connected = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2473
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2490
radeon_connector->dac_load_detect = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2499
connector->interlace_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2500
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2519
connector->interlace_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
2520
connector->doublescan_allowed = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
452
mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
sys/dev/pci/drm/radeon/radeon_connectors.c
507
mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
sys/dev/pci/drm/radeon/radeon_connectors.c
538
new_coherent_mode = val ? true : false;
sys/dev/pci/drm/radeon/radeon_connectors.c
646
radeon_connector->dac_load_detect = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
653
bool ret = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
892
radeon_connector->ddc_bus->has_aux = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
992
bool dret = false;
sys/dev/pci/drm/radeon/radeon_cs.c
816
return false;
sys/dev/pci/drm/radeon/radeon_cs.c
818
return false;
sys/dev/pci/drm/radeon/radeon_cs.c
820
return false;
sys/dev/pci/drm/radeon/radeon_cs.c
86
bool need_mmap_lock = false;
sys/dev/pci/drm/radeon/radeon_cursor.c
249
radeon_crtc->cursor_out_of_bounds = false;
sys/dev/pci/drm/radeon/radeon_cursor.c
271
radeon_lock_cursor(crtc, false);
sys/dev/pci/drm/radeon/radeon_cursor.c
310
ret = radeon_bo_reserve(robj, false);
sys/dev/pci/drm/radeon/radeon_cursor.c
347
radeon_lock_cursor(crtc, false);
sys/dev/pci/drm/radeon/radeon_cursor.c
352
ret = radeon_bo_reserve(robj, false);
sys/dev/pci/drm/radeon/radeon_cursor.c
384
radeon_lock_cursor(crtc, false);
sys/dev/pci/drm/radeon/radeon_device.c
120
static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
sys/dev/pci/drm/radeon/radeon_device.c
121
static inline bool radeon_is_atpx_hybrid(void) { return false; }
sys/dev/pci/drm/radeon/radeon_device.c
1248
radeon_suspend_kms(dev, true, true, false);
sys/dev/pci/drm/radeon/radeon_device.c
1300
bool runtime = false;
sys/dev/pci/drm/radeon/radeon_device.c
1302
rdev->shutdown = false;
sys/dev/pci/drm/radeon/radeon_device.c
1305
rdev->is_atom_bios = false;
sys/dev/pci/drm/radeon/radeon_device.c
1308
rdev->accel_working = false;
sys/dev/pci/drm/radeon/radeon_device.c
1621
r = radeon_bo_reserve(robj, false);
sys/dev/pci/drm/radeon/radeon_device.c
1634
r = radeon_bo_reserve(robj, false);
sys/dev/pci/drm/radeon/radeon_device.c
164
return false;
sys/dev/pci/drm/radeon/radeon_device.c
1679
drm_client_dev_suspend(dev, false);
sys/dev/pci/drm/radeon/radeon_device.c
1726
rdev->pm.dpm_enabled = false;
sys/dev/pci/drm/radeon/radeon_device.c
1742
r = radeon_bo_reserve(robj, false);
sys/dev/pci/drm/radeon/radeon_device.c
1789
drm_client_dev_resume(dev, false);
sys/dev/pci/drm/radeon/radeon_device.c
1807
bool saved = false;
sys/dev/pci/drm/radeon/radeon_device.c
1856
rdev->pm.dpm_enabled = false;
sys/dev/pci/drm/radeon/radeon_device.c
1880
rdev->needs_reset = false;
sys/dev/pci/drm/radeon/radeon_device.c
1900
rdev->in_reset = false;
sys/dev/pci/drm/radeon/radeon_device.c
299
rdev->scratch.free[i] = false;
sys/dev/pci/drm/radeon/radeon_device.c
435
rdev->wb.enabled = false;
sys/dev/pci/drm/radeon/radeon_device.c
450
if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
sys/dev/pci/drm/radeon/radeon_device.c
482
r = radeon_bo_reserve(rdev->wb.wb_obj, false);
sys/dev/pci/drm/radeon/radeon_device.c
507
rdev->wb.use_event = false;
sys/dev/pci/drm/radeon/radeon_device.c
510
rdev->wb.enabled = false;
sys/dev/pci/drm/radeon/radeon_device.c
514
rdev->wb.enabled = false;
sys/dev/pci/drm/radeon/radeon_device.c
517
rdev->wb.enabled = false;
sys/dev/pci/drm/radeon/radeon_device.c
654
return false;
sys/dev/pci/drm/radeon/radeon_device.c
674
return false;
sys/dev/pci/drm/radeon/radeon_device.c
681
return false;
sys/dev/pci/drm/radeon/radeon_device.c
725
return false;
sys/dev/pci/drm/radeon/radeon_device.c
780
return false;
sys/dev/pci/drm/radeon/radeon_display.c
1660
rdev->mode_info.mode_config_initialized = false;
sys/dev/pci/drm/radeon/radeon_display.c
1678
return false;
sys/dev/pci/drm/radeon/radeon_display.c
1743
first = false;
sys/dev/pci/drm/radeon/radeon_display.c
1753
return false;
sys/dev/pci/drm/radeon/radeon_display.c
1892
in_vbl = false;
sys/dev/pci/drm/radeon/radeon_display.c
1902
in_vbl = false;
sys/dev/pci/drm/radeon/radeon_display.c
1952
in_vbl = false;
sys/dev/pci/drm/radeon/radeon_display.c
271
r = radeon_bo_reserve(work->old_rbo, false);
sys/dev/pci/drm/radeon/radeon_display.c
425
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_display.c
434
r = dma_fence_wait(work->fence, false);
sys/dev/pci/drm/radeon/radeon_display.c
522
r = radeon_bo_reserve(new_rbo, false);
sys/dev/pci/drm/radeon/radeon_display.c
606
if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
sys/dev/pci/drm/radeon/radeon_display.c
627
bool active = false;
sys/dev/pci/drm/radeon/radeon_display.c
660
rdev->have_disp_power_ref = false;
sys/dev/pci/drm/radeon/radeon_display.c
847
bool ret = false;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
69
bool is_write = false;
sys/dev/pci/drm/radeon/radeon_drv.c
1324
radeon_vga_set_state(rdev, false);
sys/dev/pci/drm/radeon/radeon_drv.c
1348
radeon_suspend_kms(ddev, true, true, false);
sys/dev/pci/drm/radeon/radeon_drv.c
357
radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
sys/dev/pci/drm/radeon/radeon_drv.c
365
return radeon_suspend_kms(drm_dev, true, true, false);
sys/dev/pci/drm/radeon/radeon_drv.c
386
return radeon_suspend_kms(drm_dev, false, true, true);
sys/dev/pci/drm/radeon/radeon_drv.c
393
return radeon_resume_kms(drm_dev, false, true);
sys/dev/pci/drm/radeon/radeon_drv.c
409
radeon_suspend_kms(drm_dev, false, false, false);
sys/dev/pci/drm/radeon/radeon_drv.c
442
ret = radeon_resume_kms(drm_dev, false, false);
sys/dev/pci/drm/radeon/radeon_drv.c
650
static inline bool radeon_has_atpx(void) { return false; }
sys/dev/pci/drm/radeon/radeon_drv.h
134
static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
sys/dev/pci/drm/radeon/radeon_drv.h
135
static inline bool radeon_is_atpx_hybrid(void) { return false; }
sys/dev/pci/drm/radeon/radeon_encoders.c
168
bool use_bl = false;
sys/dev/pci/drm/radeon/radeon_encoders.c
174
use_bl = false;
sys/dev/pci/drm/radeon/radeon_encoders.c
183
use_bl = false;
sys/dev/pci/drm/radeon/radeon_encoders.c
188
use_bl = false;
sys/dev/pci/drm/radeon/radeon_encoders.c
393
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
398
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
401
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
408
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
415
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
420
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
424
return false;
sys/dev/pci/drm/radeon/radeon_encoders.c
447
return false;
sys/dev/pci/drm/radeon/radeon_fbdev.c
113
ret = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_fbdev.c
267
info->skip_vt_switch = false;
sys/dev/pci/drm/radeon/radeon_fbdev.c
331
return false;
sys/dev/pci/drm/radeon/radeon_fbdev.c
335
return false;
sys/dev/pci/drm/radeon/radeon_fbdev.c
337
return false;
sys/dev/pci/drm/radeon/radeon_fbdev.c
46
ret = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_fbdev.c
63
bool fb_tiled = false; /* useful for testing */
sys/dev/pci/drm/radeon/radeon_fence.c
147
(*fence)->is_vm_update = false;
sys/dev/pci/drm/radeon/radeon_fence.c
201
bool wake = false;
sys/dev/pci/drm/radeon/radeon_fence.c
287
fence_drv->delayed_irq = false;
sys/dev/pci/drm/radeon/radeon_fence.c
350
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
363
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
380
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
392
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
428
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
450
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
593
r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/radeon/radeon_fence.c
619
r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/radeon/radeon_fence.c
703
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
706
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
711
return false;
sys/dev/pci/drm/radeon/radeon_fence.c
819
rdev->fence_drv[ring].initialized = false;
sys/dev/pci/drm/radeon/radeon_fence.c
871
rdev->fence_drv[ring].initialized = false;
sys/dev/pci/drm/radeon/radeon_gart.c
203
r = radeon_bo_reserve(rdev->gart.robj, false);
sys/dev/pci/drm/radeon/radeon_gart.c
248
r = radeon_bo_reserve(rdev->gart.robj, false);
sys/dev/pci/drm/radeon/radeon_gart.c
426
rdev->gart.ready = false;
sys/dev/pci/drm/radeon/radeon_gem.c
285
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_gem.c
416
false, &gobj);
sys/dev/pci/drm/radeon/radeon_gem.c
440
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/radeon/radeon_gem.c
477
false, &gobj);
sys/dev/pci/drm/radeon/radeon_gem.c
679
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_gem.c
821
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_gem.c
880
r = radeon_bo_reserve(robj, false);
sys/dev/pci/drm/radeon/radeon_gem.c
943
false, &gobj);
sys/dev/pci/drm/radeon/radeon_i2c.c
72
return false;
sys/dev/pci/drm/radeon/radeon_i2c.c
81
return false;
sys/dev/pci/drm/radeon/radeon_ib.c
244
rdev->ib_pool_ready = false;
sys/dev/pci/drm/radeon/radeon_ib.c
272
ring->ready = false;
sys/dev/pci/drm/radeon/radeon_ib.c
273
rdev->needs_reset = false;
sys/dev/pci/drm/radeon/radeon_ib.c
278
rdev->accel_working = false;
sys/dev/pci/drm/radeon/radeon_ib.c
86
ib->is_const_ib = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
135
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
137
rdev->irq.hpd[i] = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
139
rdev->irq.crtc_vblank_int[i] = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
141
rdev->irq.afmt[i] = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
189
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
191
rdev->irq.hpd[i] = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
193
rdev->irq.crtc_vblank_int[i] = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
195
rdev->irq.afmt[i] = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
251
return false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
255
return false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
271
return false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
307
return false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
313
return false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
359
rdev->irq.installed = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
379
rdev->irq.installed = false;
sys/dev/pci/drm/radeon/radeon_irq_kms.c
539
rdev->irq.afmt[block] = false;
sys/dev/pci/drm/radeon/radeon_kms.c
264
*value = false;
sys/dev/pci/drm/radeon/radeon_kms.c
47
static inline bool radeon_has_atpx(void) { return false; }
sys/dev/pci/drm/radeon/radeon_kms.c
662
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
sys/dev/pci/drm/radeon/radeon_kms.c
733
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
sys/dev/pci/drm/radeon/radeon_kms.c
870
rdev->irq.crtc_vblank_int[pipe] = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
1031
return false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
1096
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
115
hscale = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
116
vscale = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
124
hscale = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
126
vscale = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
353
radeon_crtc->enabled = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
420
return false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
427
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
455
if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
526
return false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
560
r = radeon_bo_reserve(rbo, false);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
588
bool is_tv = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
619
return false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
745
bool use_bios_divs = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
750
bool is_tv = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1041
is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1156
bool is_tv = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1160
is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1306
bool found = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1377
bool found = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1444
bool found = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
181
radeon_atom_output_lock(encoder, false);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
183
radeon_combios_output_lock(encoder, false);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
426
pdata->negative = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
572
radeon_atom_output_lock(encoder, false);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
574
radeon_combios_output_lock(encoder, false);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
63
bool is_mac = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
934
radeon_atom_output_lock(encoder, false);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
936
radeon_combios_output_lock(encoder, false);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
436
return false;
sys/dev/pci/drm/radeon/radeon_mn.c
54
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/radeon/radeon_mn.c
61
return false;
sys/dev/pci/drm/radeon/radeon_mn.c
70
false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/radeon/radeon_mode.h
953
return false;
sys/dev/pci/drm/radeon/radeon_object.c
224
false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/radeon/radeon_object.c
275
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/radeon/radeon_object.c
355
if (rdev->mc.igp_sideport_enabled == false)
sys/dev/pci/drm/radeon/radeon_object.c
489
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/radeon/radeon_object.c
674
r = radeon_bo_reserve(bo, false);
sys/dev/pci/drm/radeon/radeon_object.c
73
return false;
sys/dev/pci/drm/radeon/radeon_object.c
738
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/drm/radeon/radeon_object.c
807
dma_fence_wait(&fence->base, false);
sys/dev/pci/drm/radeon/radeon_object.h
68
r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
sys/dev/pci/drm/radeon/radeon_pm.c
1236
rdev->pm.dpm.uvd_active = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1254
rdev->pm.dpm.vce_active = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1280
rdev->pm.dpm_enabled = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1478
rdev->pm.dpm_enabled = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1516
bool disable_dpm = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1633
rdev->pm.dpm_enabled = false;
sys/dev/pci/drm/radeon/radeon_pm.c
166
rdev->pm.vblank_sync = false;
sys/dev/pci/drm/radeon/radeon_pm.c
176
bool misc_after = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1824
rdev->pm.dpm.ac_power = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1857
in_vbl = false;
sys/dev/pci/drm/radeon/radeon_pm.c
225
radeon_pm_debug_check_in_vbl(rdev, false);
sys/dev/pci/drm/radeon/radeon_pm.c
234
radeon_pm_debug_check_in_vbl(rdev, false);
sys/dev/pci/drm/radeon/radeon_pm.c
82
rdev->pm.dpm.ac_power = false;
sys/dev/pci/drm/radeon/radeon_pm.c
919
rdev->pm.dpm.thermal_active = false;
sys/dev/pci/drm/radeon/radeon_pm.c
933
single_display = false;
sys/dev/pci/drm/radeon/radeon_pm.c
940
single_display = false;
sys/dev/pci/drm/radeon/radeon_prime.c
56
ret = radeon_bo_create(rdev, attach->dmabuf->size, PAGE_SIZE, false,
sys/dev/pci/drm/radeon/radeon_ring.c
263
return false;
sys/dev/pci/drm/radeon/radeon_ring.c
273
return false;
sys/dev/pci/drm/radeon/radeon_ring.c
366
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/radeon_ring.c
401
r = radeon_bo_reserve(ring->ring_obj, false);
sys/dev/pci/drm/radeon/radeon_ring.c
446
ring->ready = false;
sys/dev/pci/drm/radeon/radeon_ring.c
452
r = radeon_bo_reserve(ring_obj, false);
sys/dev/pci/drm/radeon/radeon_ring.c
71
return false;
sys/dev/pci/drm/radeon/radeon_sa.c
112
r = radeon_bo_reserve(sa_manager->bo, false);
sys/dev/pci/drm/radeon/radeon_sa.c
126
GFP_KERNEL, false, align);
sys/dev/pci/drm/radeon/radeon_sa.c
86
r = radeon_bo_reserve(sa_manager->bo, false);
sys/dev/pci/drm/radeon/radeon_semaphore.c
65
if (radeon_semaphore_ring_emit(rdev, ridx, ring, semaphore, false)) {
sys/dev/pci/drm/radeon/radeon_semaphore.c
72
return false;
sys/dev/pci/drm/radeon/radeon_semaphore.c
89
return false;
sys/dev/pci/drm/radeon/radeon_sync.c
144
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_sync.c
164
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_sync.c
174
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_sync.c
180
radeon_ring_commit(rdev, &rdev->ring[i], false);
sys/dev/pci/drm/radeon/radeon_test.c
134
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_test.c
185
r = radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_test.c
308
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/radeon_test.c
333
radeon_ring_unlock_commit(rdev, ringA, false);
sys/dev/pci/drm/radeon/radeon_test.c
345
radeon_ring_unlock_commit(rdev, ringA, false);
sys/dev/pci/drm/radeon/radeon_test.c
364
radeon_ring_unlock_commit(rdev, ringB, false);
sys/dev/pci/drm/radeon/radeon_test.c
366
r = radeon_fence_wait(fence1, false);
sys/dev/pci/drm/radeon/radeon_test.c
385
radeon_ring_unlock_commit(rdev, ringB, false);
sys/dev/pci/drm/radeon/radeon_test.c
387
r = radeon_fence_wait(fence2, false);
sys/dev/pci/drm/radeon/radeon_test.c
428
radeon_ring_unlock_commit(rdev, ringA, false);
sys/dev/pci/drm/radeon/radeon_test.c
440
radeon_ring_unlock_commit(rdev, ringB, false);
sys/dev/pci/drm/radeon/radeon_test.c
462
radeon_ring_unlock_commit(rdev, ringC, false);
sys/dev/pci/drm/radeon/radeon_test.c
488
radeon_ring_unlock_commit(rdev, ringC, false);
sys/dev/pci/drm/radeon/radeon_test.c
492
r = radeon_fence_wait(fenceA, false);
sys/dev/pci/drm/radeon/radeon_test.c
497
r = radeon_fence_wait(fenceB, false);
sys/dev/pci/drm/radeon/radeon_test.c
521
return false;
sys/dev/pci/drm/radeon/radeon_test.c
76
r = radeon_bo_reserve(vram_obj, false);
sys/dev/pci/drm/radeon/radeon_test.c
98
r = radeon_bo_reserve(gtt_obj[i], false);
sys/dev/pci/drm/radeon/radeon_ttm.c
110
if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
sys/dev/pci/drm/radeon/radeon_ttm.c
191
r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
sys/dev/pci/drm/radeon/radeon_ttm.c
484
gtt->bound = false;
sys/dev/pci/drm/radeon/radeon_ttm.c
670
return false;
sys/dev/pci/drm/radeon/radeon_ttm.c
681
return false;
sys/dev/pci/drm/radeon/radeon_ttm.c
751
r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
sys/dev/pci/drm/radeon/radeon_ttm.c
784
r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
sys/dev/pci/drm/radeon/radeon_ttm.c
795
rdev->mman.initialized = false;
sys/dev/pci/drm/radeon/radeon_ttm.c
81
false, rdev->mc.real_vram_size >> PAGE_SHIFT);
sys/dev/pci/drm/radeon/radeon_uvd.c
137
rdev->uvd.fw_header_present = false;
sys/dev/pci/drm/radeon/radeon_uvd.c
197
r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
sys/dev/pci/drm/radeon/radeon_uvd.c
237
r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
sys/dev/pci/drm/radeon/radeon_uvd.c
272
radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_uvd.c
346
radeon_fence_wait(fence, false);
sys/dev/pci/drm/radeon/radeon_uvd.c
679
bool has_msg_cmd = false;
sys/dev/pci/drm/radeon/radeon_uvd.c
752
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/radeon_uvd.c
868
radeon_dpm_enable_uvd(rdev, false);
sys/dev/pci/drm/radeon/radeon_uvd.c
880
bool streams_changed = false;
sys/dev/pci/drm/radeon/radeon_vce.c
179
r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
sys/dev/pci/drm/radeon/radeon_vce.c
258
r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
sys/dev/pci/drm/radeon/radeon_vce.c
299
radeon_dpm_enable_vce(rdev, false);
sys/dev/pci/drm/radeon/radeon_vce.c
318
bool streams_changed = false;
sys/dev/pci/drm/radeon/radeon_vce.c
325
streams_changed = false;
sys/dev/pci/drm/radeon/radeon_vce.c
419
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/radeon_vce.c
476
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/radeon_vce.c
553
*allocated = false;
sys/dev/pci/drm/radeon/radeon_vce.c
589
bool destroyed = false, created = false, allocated = false;
sys/dev/pci/drm/radeon/radeon_vce.c
798
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/radeon_vce.c
842
r = radeon_fence_wait_timeout(fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/radeon_vm.c
1020
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/radeon_vm.c
116
rdev->vm_manager.enabled = false;
sys/dev/pci/drm/radeon/radeon_vm.c
1242
r = radeon_bo_reserve(bo_va->bo, false);
sys/dev/pci/drm/radeon/radeon_vm.c
389
struct ttm_operation_ctx ctx = { true, false };
sys/dev/pci/drm/radeon/radeon_vm.c
395
r = radeon_bo_reserve(bo, false);
sys/dev/pci/drm/radeon/radeon_vm.c
416
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/radeon_vm.c
421
radeon_bo_fence(bo, ib.fence, false);
sys/dev/pci/drm/radeon/radeon_vm.c
704
r = radeon_ib_schedule(rdev, &ib, NULL, false);
sys/dev/pci/drm/radeon/radeon_vm.c
710
radeon_bo_fence(pd, ib.fence, false);
sys/dev/pci/drm/radeon/rs400.c
500
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rs400.c
565
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/rs400.c
596
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rs600.c
1066
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rs600.c
1132
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/rs600.c
1164
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rs600.c
362
bool connected = false;
sys/dev/pci/drm/radeon/rs600.c
67
return false;
sys/dev/pci/drm/radeon/rs600.c
781
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/rs600.c
782
bool queue_hdmi = false;
sys/dev/pci/drm/radeon/rs600.c
80
return false;
sys/dev/pci/drm/radeon/rs690.c
179
rdev->fastfb_working = false;
sys/dev/pci/drm/radeon/rs690.c
626
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
sys/dev/pci/drm/radeon/rs690.c
627
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
sys/dev/pci/drm/radeon/rs690.c
777
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rs690.c
844
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/rs690.c
876
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rs780_dpm.c
101
r600_engine_clock_entry_enable(rdev, i, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
103
r600_enable_mclk_control(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
1036
rs780_clk_scaling_enable(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
1037
rs780_voltage_scaling_enable(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
1044
ps->sclk_high, false, ÷rs);
sys/dev/pci/drm/radeon/rs780_dpm.c
1051
ps->sclk_low, false, ÷rs);
sys/dev/pci/drm/radeon/rs780_dpm.c
164
r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
165
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
166
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
178
r600_enable_sclk_control(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
179
r600_enable_mclk_control(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
188
r600_enable_spll_bypass(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
193
r600_enable_spll_bypass(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
439
new_state->sclk_low, false, &min_dividers);
sys/dev/pci/drm/radeon/rs780_dpm.c
444
new_state->sclk_high, false, &max_dividers);
sys/dev/pci/drm/radeon/rs780_dpm.c
449
old_state->sclk_high, false, ¤t_max_dividers);
sys/dev/pci/drm/radeon/rs780_dpm.c
634
r600_dynamicpm_enable(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
636
rs780_clk_scaling_enable(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
637
rs780_voltage_scaling_enable(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
640
r600_gfx_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
644
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/rs780_dpm.c
83
default_state->sclk_low, false, ÷rs);
sys/dev/pci/drm/radeon/rs780_dpm.c
869
pi->voltage_control = false;
sys/dev/pci/drm/radeon/rs780_dpm.c
884
(pi->num_of_cycles_in_period & 0x8000) ? true : false;
sys/dev/pci/drm/radeon/rs780_dpm.c
901
(pi->num_of_cycles_in_period & 0x8000) ? true : false;
sys/dev/pci/drm/radeon/rs780_dpm.c
911
(pi->system_config & 0x4) ? true : false;
sys/dev/pci/drm/radeon/rs780_dpm.c
920
pi->voltage_control = false;
sys/dev/pci/drm/radeon/rs780_dpm.c
925
pi->voltage_control = false;
sys/dev/pci/drm/radeon/rs780_dpm.c
929
pi->voltage_control = false;
sys/dev/pci/drm/radeon/rs780_dpm.c
94
r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
sys/dev/pci/drm/radeon/rs780_dpm.c
97
r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
sys/dev/pci/drm/radeon/rv515.c
116
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/rv515.c
1219
rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
sys/dev/pci/drm/radeon/rv515.c
1220
rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
sys/dev/pci/drm/radeon/rv515.c
1222
rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
sys/dev/pci/drm/radeon/rv515.c
1223
rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
sys/dev/pci/drm/radeon/rv515.c
305
save->crtc_enabled[i] = false;
sys/dev/pci/drm/radeon/rv515.c
308
save->crtc_enabled[i] = false;
sys/dev/pci/drm/radeon/rv515.c
565
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rv515.c
636
if (radeon_boot_test_post_card(rdev) == false)
sys/dev/pci/drm/radeon/rv515.c
675
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1146
rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1360
want_thermal_protection = false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
145
clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1477
rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1478
rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1479
rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1480
rv6xx_enable_dynamic_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1481
rv6xx_enable_memory_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1506
rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1507
r600_enable_dynamic_pcie_gen2(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1571
if (pi->display_gap == false)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1572
rv6xx_enable_display_gap(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1601
rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1622
rv6xx_enable_display_gap(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1627
r600_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1630
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1631
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1634
rv6xx_enable_backbias(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1636
rv6xx_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1642
rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1646
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1651
r600_gfx_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1672
r600_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1675
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1676
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1694
rv6xx_enable_dynamic_voltage_control(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1697
rv6xx_enable_dynamic_backbias_control(rdev, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1706
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
171
r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1717
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
174
r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1958
0, false, ÷rs);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1965
0, false, ÷rs);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1987
pi->sclk_ss = false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1992
pi->dynamic_ss = false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2000
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2147
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2148
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2152
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
311
r600_engine_clock_entry_enable(rdev, step_index, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
491
(state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
493
(state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
495
(state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
497
(state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
500
(state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
502
(state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
504
(state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
557
rv6xx_enable_engine_spread_spectrum(rdev, level, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
560
if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) {
sys/dev/pci/drm/radeon/rv6xx_dpm.c
602
if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs))
sys/dev/pci/drm/radeon/rv6xx_dpm.c
613
rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
641
requested_memory_clock, false, &req_dividers) == 0) {
sys/dev/pci/drm/radeon/rv6xx_dpm.c
660
rv6xx_enable_memory_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/rv730_dpm.c
133
memory_clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv730_dpm.c
55
engine_clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv740_dpm.c
136
engine_clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv740_dpm.c
204
memory_clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv770.c
1086
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/rv770.c
1703
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/rv770.c
1874
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rv770.c
1992
rdev->accel_working = false;
sys/dev/pci/drm/radeon/rv770_dma.c
66
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/rv770_dma.c
90
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/rv770_dpm.c
1319
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1327
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1602
pi->mem_gddr5 = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1617
pi->pcie_gen2 = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1623
pi->boot_in_gen2 = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1625
pi->boot_in_gen2 = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
170
bool dpm_en = false, cg_en = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1752
bool current_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1753
bool new_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1781
bool current_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1782
bool new_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1823
want_thermal_protection = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2010
rv770_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/rv770_dpm.c
2012
rv770_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/rv770_dpm.c
2015
rv770_enable_dynamic_pcie_gen2(rdev, false);
sys/dev/pci/drm/radeon/rv770_dpm.c
2019
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2024
rv770_gfx_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/rv770_dpm.c
2027
rv770_mg_clock_gating_enable(rdev, false);
sys/dev/pci/drm/radeon/rv770_dpm.c
211
return false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2233
pi->acpi_pcie_gen2 = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2342
pi->dynamic_ss = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2376
0, false, ÷rs);
sys/dev/pci/drm/radeon/rv770_dpm.c
2402
pi->power_gating = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2414
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2421
pi->dcodt = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
2586
return false;
sys/dev/pci/drm/radeon/rv770_dpm.c
412
memory_clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv770_dpm.c
508
engine_clock, false, ÷rs);
sys/dev/pci/drm/radeon/rv770_dpm.c
802
rv740_enable_mclk_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/rv770_smc.c
409
return false;
sys/dev/pci/drm/radeon/si.c
1658
bool new_smc = false;
sys/dev/pci/drm/radeon/si.c
1659
bool si58_fw = false;
sys/dev/pci/drm/radeon/si.c
1660
bool banks2_fw = false;
sys/dev/pci/drm/radeon/si.c
1918
rdev->new_fw = false;
sys/dev/pci/drm/radeon/si.c
2236
return false;
sys/dev/pci/drm/radeon/si.c
2245
return false;
sys/dev/pci/drm/radeon/si.c
2271
return false;
sys/dev/pci/drm/radeon/si.c
2307
radeon_dpm_get_mclk(rdev, false) * 10;
sys/dev/pci/drm/radeon/si.c
2309
radeon_dpm_get_sclk(rdev, false) * 10;
sys/dev/pci/drm/radeon/si.c
2319
wm_high.interlaced = false;
sys/dev/pci/drm/radeon/si.c
2346
wm_low.interlaced = false;
sys/dev/pci/drm/radeon/si.c
3449
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3450
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3451
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3463
si_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/si.c
3561
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/si.c
3590
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/si.c
3604
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/si.c
3613
si_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/si.c
3635
si_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/si.c
3732
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3733
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3734
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3739
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
3743
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
sys/dev/pci/drm/radeon/si.c
4093
r600_set_bios_scratch_engine_hung(rdev, false);
sys/dev/pci/drm/radeon/si.c
4115
return false;
sys/dev/pci/drm/radeon/si.c
4433
return false;
sys/dev/pci/drm/radeon/si.c
5177
si_set_uvd_dcm(rdev, false);
sys/dev/pci/drm/radeon/si.c
5361
si_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/si.c
5601
si_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/si.c
5607
si_enable_cgcg(rdev, false);
sys/dev/pci/drm/radeon/si.c
5608
si_enable_mgcg(rdev, false);
sys/dev/pci/drm/radeon/si.c
5654
si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
sys/dev/pci/drm/radeon/si.c
5660
RADEON_CG_BLOCK_HDP), false);
sys/dev/pci/drm/radeon/si.c
5779
si_enable_dma_pg(rdev, false);
sys/dev/pci/drm/radeon/si.c
5780
si_enable_gfx_cgpg(rdev, false);
sys/dev/pci/drm/radeon/si.c
5803
si_enable_gui_idle_interrupt(rdev, false);
sys/dev/pci/drm/radeon/si.c
5825
return false;
sys/dev/pci/drm/radeon/si.c
5924
rdev->ih.enabled = false;
sys/dev/pci/drm/radeon/si.c
6234
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/si.c
6235
bool queue_dp = false;
sys/dev/pci/drm/radeon/si.c
6236
bool queue_thermal = false;
sys/dev/pci/drm/radeon/si.c
6396
rdev->pm.dpm.thermal.high_to_low = false;
sys/dev/pci/drm/radeon/si.c
6457
rdev->has_uvd = false;
sys/dev/pci/drm/radeon/si.c
6524
rdev->has_vce = false;
sys/dev/pci/drm/radeon/si.c
6774
rdev->accel_working = false;
sys/dev/pci/drm/radeon/si.c
6787
si_cp_enable(rdev, false);
sys/dev/pci/drm/radeon/si.c
6913
rdev->accel_working = false;
sys/dev/pci/drm/radeon/si.c
7229
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/radeon/si.c
7230
bool disable_clkreq = false;
sys/dev/pci/drm/radeon/si.c
7359
clk_req_support = false;
sys/dev/pci/drm/radeon/si.c
7364
clk_req_support = false;
sys/dev/pci/drm/radeon/si_dma.c
254
radeon_sync_resv(rdev, &sync, resv, false);
sys/dev/pci/drm/radeon/si_dma.c
278
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/si_dma.c
52
return false;
sys/dev/pci/drm/radeon/si_dpm.c
1005
false
sys/dev/pci/drm/radeon/si_dpm.c
1549
false
sys/dev/pci/drm/radeon/si_dpm.c
1806
bool update_dte_from_pl2 = false;
sys/dev/pci/drm/radeon/si_dpm.c
1993
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/si_dpm.c
1994
ni_pi->enable_cac = false;
sys/dev/pci/drm/radeon/si_dpm.c
1995
ni_pi->enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
1996
si_pi->enable_dte = false;
sys/dev/pci/drm/radeon/si_dpm.c
2020
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/radeon/si_dpm.c
2025
si_pi->dyn_powertune_data.disable_uvd_powertune = false;
sys/dev/pci/drm/radeon/si_dpm.c
2112
false, /* ??? */
sys/dev/pci/drm/radeon/si_dpm.c
2219
return false;
sys/dev/pci/drm/radeon/si_dpm.c
2241
if (ni_pi->enable_power_containment == false)
sys/dev/pci/drm/radeon/si_dpm.c
2336
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
2339
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
2342
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
2345
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
2348
enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
2387
ni_pi->pc_enabled = false;
sys/dev/pci/drm/radeon/si_dpm.c
2396
ni_pi->pc_enabled = false;
sys/dev/pci/drm/radeon/si_dpm.c
2414
si_pi->enable_dte = false;
sys/dev/pci/drm/radeon/si_dpm.c
2416
if (si_pi->enable_dte == false)
sys/dev/pci/drm/radeon/si_dpm.c
2424
si_pi->enable_dte = false;
sys/dev/pci/drm/radeon/si_dpm.c
252
false
sys/dev/pci/drm/radeon/si_dpm.c
2599
if (ni_pi->enable_cac == false)
sys/dev/pci/drm/radeon/si_dpm.c
2663
ni_pi->enable_cac = false;
sys/dev/pci/drm/radeon/si_dpm.c
2664
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/si_dpm.c
2717
if ((ni_pi->enable_cac == false) ||
sys/dev/pci/drm/radeon/si_dpm.c
2718
(ni_pi->cac_configuration_required == false))
sys/dev/pci/drm/radeon/si_dpm.c
2749
ni_pi->support_cac_long_term_average = false;
sys/dev/pci/drm/radeon/si_dpm.c
2755
ni_pi->cac_enabled = false;
sys/dev/pci/drm/radeon/si_dpm.c
2772
ni_pi->cac_enabled = false;
sys/dev/pci/drm/radeon/si_dpm.c
2845
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/si_dpm.c
2907
bool disable_mclk_switching = false;
sys/dev/pci/drm/radeon/si_dpm.c
2908
bool disable_sclk_switching = false;
sys/dev/pci/drm/radeon/si_dpm.c
2978
if (rdev->pm.dpm.ac_power == false) {
sys/dev/pci/drm/radeon/si_dpm.c
3122
ps->dc_compatible = false;
sys/dev/pci/drm/radeon/si_dpm.c
3150
bool ret = false;
sys/dev/pci/drm/radeon/si_dpm.c
3231
want_thermal_protection = false;
sys/dev/pci/drm/radeon/si_dpm.c
3805
bool strobe_mode = false;
sys/dev/pci/drm/radeon/si_dpm.c
3842
return false;
sys/dev/pci/drm/radeon/si_dpm.c
3849
return false;
sys/dev/pci/drm/radeon/si_dpm.c
3854
return false;
sys/dev/pci/drm/radeon/si_dpm.c
3857
return false;
sys/dev/pci/drm/radeon/si_dpm.c
3951
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
3956
pi->mvdd_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
3970
si_pi->vddc_phase_shed_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
3974
si_pi->vddc_phase_shed_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
4045
si_pi->vddc_phase_shed_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
4095
bool voltage_found = false;
sys/dev/pci/drm/radeon/si_dpm.c
4746
engine_clock, false, ÷rs);
sys/dev/pci/drm/radeon/si_dpm.c
4931
bool gmc_pg = false;
sys/dev/pci/drm/radeon/si_dpm.c
4968
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/si_dpm.c
4970
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/si_dpm.c
4972
dll_state_on = false;
sys/dev/pci/drm/radeon/si_dpm.c
4978
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/si_dpm.c
5100
return false;
sys/dev/pci/drm/radeon/si_dpm.c
5109
return false;
sys/dev/pci/drm/radeon/si_dpm.c
5114
return false;
sys/dev/pci/drm/radeon/si_dpm.c
5155
eg_pi->uvd_enabled = false;
sys/dev/pci/drm/radeon/si_dpm.c
5204
ni_pi->enable_power_containment = false;
sys/dev/pci/drm/radeon/si_dpm.c
5208
ni_pi->enable_sq_ramping = false;
sys/dev/pci/drm/radeon/si_dpm.c
525
false
sys/dev/pci/drm/radeon/si_dpm.c
5417
result = false;
sys/dev/pci/drm/radeon/si_dpm.c
5701
si_pi->pspp_notify_required = false;
sys/dev/pci/drm/radeon/si_dpm.c
5706
if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
sys/dev/pci/drm/radeon/si_dpm.c
5713
if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
sys/dev/pci/drm/radeon/si_dpm.c
5748
radeon_acpi_pcie_performance_request(rdev, request, false);
sys/dev/pci/drm/radeon/si_dpm.c
5882
vce_v1_0_enable_mgcg(rdev, false);
sys/dev/pci/drm/radeon/si_dpm.c
5911
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/si_dpm.c
5961
si_pi->fan_ctrl_is_in_default_mode = false;
sys/dev/pci/drm/radeon/si_dpm.c
5985
rdev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
5992
rdev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
6044
rdev->pm.dpm.fan.ucode_fan_control = false;
sys/dev/pci/drm/radeon/si_dpm.c
6072
si_pi->fan_is_controlled_by_smc = false;
sys/dev/pci/drm/radeon/si_dpm.c
6316
eg_pi->dynamic_ac_timing = false;
sys/dev/pci/drm/radeon/si_dpm.c
6394
ret = si_notify_smc_display_change(rdev, false);
sys/dev/pci/drm/radeon/si_dpm.c
6415
ret = si_thermal_enable_alert(rdev, false);
sys/dev/pci/drm/radeon/si_dpm.c
6450
si_enable_thermal_protection(rdev, false);
sys/dev/pci/drm/radeon/si_dpm.c
6451
si_enable_power_containment(rdev, boot_ps, false);
sys/dev/pci/drm/radeon/si_dpm.c
6452
si_enable_smc_cac(rdev, boot_ps, false);
sys/dev/pci/drm/radeon/si_dpm.c
6453
si_enable_spread_spectrum(rdev, false);
sys/dev/pci/drm/radeon/si_dpm.c
6454
si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
sys/dev/pci/drm/radeon/si_dpm.c
6522
ret = si_enable_power_containment(rdev, new_ps, false);
sys/dev/pci/drm/radeon/si_dpm.c
6527
ret = si_enable_smc_cac(rdev, new_ps, false);
sys/dev/pci/drm/radeon/si_dpm.c
6717
si_pi->ulv.supported = false;
sys/dev/pci/drm/radeon/si_dpm.c
6719
si_pi->ulv.one_pcie_lane_in_ulv = false;
sys/dev/pci/drm/radeon/si_dpm.c
6927
0, false, ÷rs);
sys/dev/pci/drm/radeon/si_dpm.c
6933
eg_pi->smu_uvd_hs = false;
sys/dev/pci/drm/radeon/si_dpm.c
6982
si_pi->sclk_deep_sleep_above_low = false;
sys/dev/pci/drm/radeon/si_dpm.c
6987
pi->thermal_protection = false;
sys/dev/pci/drm/radeon/si_dpm.c
6996
eg_pi->pcie_performance_request = false;
sys/dev/pci/drm/radeon/si_smc.c
169
return false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1151
sumo_take_smu_control(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1263
sumo_enable_sclk_ds(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1267
sumo_enable_voltage_scaling(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1271
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1303
sumo_enable_boost(rdev, new_ps, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1714
pi->sys_info.enable_boost = false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1753
pi->driver_nbps_policy_disable = false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1757
pi->disable_gfx_power_gating_in_uvd = false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1760
pi->enable_dynamic_m3_arbiter = false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1766
pi->enable_gfx_power_gating = false;
sys/dev/pci/drm/radeon/sumo_dpm.c
1934
sumo_enable_boost(rdev, rps, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1939
sumo_power_level_enable(rdev, i, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1941
sumo_set_forced_mode(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1943
sumo_set_forced_mode(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1946
sumo_enable_boost(rdev, rps, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1951
sumo_power_level_enable(rdev, i, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1953
sumo_set_forced_mode(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
1955
sumo_set_forced_mode(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
305
sumo_gfx_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
307
sumo_gfx_powergating_enable(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
309
sumo_mg_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
553
pl->sclk, false, ÷rs);
sys/dev/pci/drm/radeon/sumo_dpm.c
602
return false;
sys/dev/pci/drm/radeon/sumo_dpm.c
653
sumo_set_forced_mode(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
721
sumo_boost_state_enable(rdev, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
765
sumo_power_level_enable(rdev, i, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
789
false, ÷rs);
sys/dev/pci/drm/radeon/sumo_dpm.c
809
sumo_power_level_enable(rdev, i, false);
sys/dev/pci/drm/radeon/sumo_dpm.c
819
sumo_gfx_powergating_enable(rdev, false);
sys/dev/pci/drm/radeon/sumo_smc.c
93
bool return_code = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1073
trinity_dpm_bapm_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
1110
trinity_dpm_bapm_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
1120
rdev->irq.dpm_thermal = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1573
sumo_take_smu_control(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
1582
trinity_dce_enable_voltage_adjustment(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
1924
pi->enable_bapm = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1926
pi->enable_bapm = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1934
pi->enable_mg_clock_gating = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1935
pi->enable_gfx_dynamic_mgpg = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1936
pi->override_dynamic_mgpg = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1938
pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */
sys/dev/pci/drm/radeon/trinity_dpm.c
326
25000, false, ÷rs);
sys/dev/pci/drm/radeon/trinity_dpm.c
524
trinity_gfx_powergating_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
526
trinity_gfx_dynamic_mgpg_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
528
trinity_gfx_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
530
trinity_mg_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
531
trinity_ls_clockgating_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
544
sclk, false, ÷rs);
sys/dev/pci/drm/radeon/trinity_dpm.c
554
sclk/2, false, ÷rs);
sys/dev/pci/drm/radeon/trinity_dpm.c
703
return false;
sys/dev/pci/drm/radeon/trinity_dpm.c
751
trinity_dpm_config(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
806
trinity_power_level_enable_disable(rdev, i, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
818
trinity_power_level_enable_disable(rdev, i, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
853
return false;
sys/dev/pci/drm/radeon/trinity_dpm.c
870
return false;
sys/dev/pci/drm/radeon/trinity_dpm.c
880
trinity_gfx_powergating_enable(rdev, false);
sys/dev/pci/drm/radeon/trinity_dpm.c
950
vce_v1_0_enable_mgcg(rdev, false);
sys/dev/pci/drm/radeon/uvd_v1_0.c
176
ring->ready = false;
sys/dev/pci/drm/radeon/uvd_v1_0.c
205
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/uvd_v1_0.c
253
ring->ready = false;
sys/dev/pci/drm/radeon/uvd_v1_0.c
436
radeon_ring_unlock_commit(rdev, ring, false);
sys/dev/pci/drm/radeon/uvd_v1_0.c
471
return false;
sys/dev/pci/drm/radeon/uvd_v1_0.c
526
r = radeon_fence_wait_timeout(fence, false, usecs_to_jiffies(
sys/dev/pci/drm/radeon/vce_v1_0.c
369
ring->ready = false;
sys/dev/pci/drm/radeon/vce_v1_0.c
377
ring->ready = false;
sys/dev/pci/drm/radeon/vce_v2_0.c
114
bool sw_cg = false;
sys/dev/pci/drm/radeon/vce_v2_0.c
125
vce_v2_0_set_sw_cg(rdev, false);
sys/dev/pci/drm/radeon/vce_v2_0.c
127
vce_v2_0_set_dyn_cg(rdev, false);
sys/dev/pci/drm/scheduler/sched_entity.c
156
return false;
sys/dev/pci/drm/scheduler/sched_entity.c
434
return false;
sys/dev/pci/drm/scheduler/sched_entity.c
459
return false;
sys/dev/pci/drm/scheduler/sched_internal.h
83
return false;
sys/dev/pci/drm/scheduler/sched_internal.h
86
return false;
sys/dev/pci/drm/scheduler/sched_main.c
1031
return false;
sys/dev/pci/drm/scheduler/sched_main.c
1148
*have_more = false;
sys/dev/pci/drm/scheduler/sched_main.c
124
return false;
sys/dev/pci/drm/scheduler/sched_main.c
1346
sched->own_submit_wq = false;
sys/dev/pci/drm/scheduler/sched_main.c
1376
sched->pause_submit = false;
sys/dev/pci/drm/scheduler/sched_main.c
1469
sched->ready = false;
sys/dev/pci/drm/scheduler/sched_main.c
1560
WRITE_ONCE(sched->pause_submit, false);
sys/dev/pci/drm/scheduler/sched_main.c
574
sched->free_guilty = false;
sys/dev/pci/drm/scheduler/sched_main.c
656
dma_fence_wait(&s_job->s_fence->finished, false);
sys/dev/pci/drm/scheduler/sched_main.c
745
bool found_guilty = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
113
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
114
bool no_wait = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
143
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
144
bool no_wait = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
190
bool no_wait = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
254
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
293
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
345
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
36
.interruptible = false,
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
37
.no_wait = false,
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
370
ttm_bo_reserve(bo1, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
397
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
409
err = ttm_tt_create(bo, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
41
.interruptible = false,
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
440
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
47
.no_wait = false,
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
480
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
515
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
566
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
76
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
95
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
1020
ttm_bo_reserve(bo_val, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
1064
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
1122
ttm_bo_reserve(bo_val, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
289
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
318
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
345
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
352
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
548
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
622
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
636
dma_resv_wait_timeout(bo->base.resv, usage, false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
663
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
678
.no_gpu_wait = false,
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
746
dma_fence_wait_timeout(man->move, false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
798
ttm_bo_reserve(bo_val, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
849
ttm_bo_reserve(bo_small, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
857
ttm_bo_reserve(bo_big, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
909
ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
922
ttm_bo_reserve(bo_pinned, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
966
ttm_bo_reserve(bo_small, false, false, NULL);
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
998
err = ttm_device_kunit_init_bad_evict(test->priv, priv->ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
112
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
122
.use_dma_alloc = false,
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
123
.use_dma32 = false,
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
124
.pools_init_expected = false,
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
134
.use_dma_alloc = false,
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
136
.pools_init_expected = false,
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
141
.use_dma32 = false,
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
28
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
58
err = ttm_device_kunit_init(priv, &ttm_devs[i], false, false);
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
84
err = ttm_device_kunit_init(priv, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
255
err = ttm_device_kunit_init(devs, ttm_dev, false, false);
sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c
141
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c
229
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
154
false);
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
221
ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
27
.no_wait_gpu = false,
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
351
ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
382
ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, false, false);
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
89
ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);
sys/dev/pci/drm/ttm/tests/ttm_resource_test.c
260
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/ttm/tests/ttm_resource_test.c
72
man->use_tt = false;
sys/dev/pci/drm/ttm/tests/ttm_tt_test.c
162
err = ttm_tt_create(bo, false);
sys/dev/pci/drm/ttm/tests/ttm_tt_test.c
181
err = ttm_tt_create(bo, false);
sys/dev/pci/drm/ttm/tests/ttm_tt_test.c
205
err = ttm_tt_create(bo, false);
sys/dev/pci/drm/ttm/tests/ttm_tt_test.c
235
err = ttm_tt_create(bo, false);
sys/dev/pci/drm/ttm/tests/ttm_tt_test.c
250
err = ttm_tt_create(bo, false);
sys/dev/pci/drm/ttm/ttm_agp_backend.c
113
return false;
sys/dev/pci/drm/ttm/ttm_agp_backend.c
118
return false;
sys/dev/pci/drm/ttm/ttm_bo.c
1027
struct ttm_operation_ctx ctx = { interruptible, false };
sys/dev/pci/drm/ttm/ttm_bo.c
1318
ret = ttm_bo_reserve(bo, false, false, NULL);
sys/dev/pci/drm/ttm/ttm_bo.c
240
dma_resv_wait_timeout(&bo->base._resv, DMA_RESV_USAGE_BOOKKEEP, false,
sys/dev/pci/drm/ttm/ttm_bo.c
265
DMA_RESV_USAGE_BOOKKEEP, false,
sys/dev/pci/drm/ttm/ttm_bo.c
350
ret = ttm_bo_handle_move_mem(bo, hop_mem, false, ctx, NULL);
sys/dev/pci/drm/ttm/ttm_bo.c
593
evict_walk.try_low = evict_walk.hit_low = false;
sys/dev/pci/drm/ttm/ttm_bo.c
595
evict_walk.walk.arg.trylock_only = false;
sys/dev/pci/drm/ttm/ttm_bo.c
790
bool force_space = false;
sys/dev/pci/drm/ttm/ttm_bo.c
835
force_space = false;
sys/dev/pci/drm/ttm/ttm_bo.c
865
ret = ttm_bo_handle_move_mem(bo, res, false, ctx, &hop);
sys/dev/pci/drm/ttm/ttm_bo_util.c
358
.interruptible = false,
sys/dev/pci/drm/ttm/ttm_bo_util.c
359
.no_wait_gpu = false
sys/dev/pci/drm/ttm/ttm_bo_util.c
55
mem->bus.is_iomem = false;
sys/dev/pci/drm/ttm/ttm_bo_util.c
556
.interruptible = false,
sys/dev/pci/drm/ttm/ttm_bo_util.c
557
.no_wait_gpu = false
sys/dev/pci/drm/ttm/ttm_bo_util.c
618
false, 15 * HZ);
sys/dev/pci/drm/ttm/ttm_bo_util.c
814
false, MAX_SCHEDULE_TIMEOUT);
sys/dev/pci/drm/ttm/ttm_bo_util.c
832
curs->needs_unlock = false;
sys/dev/pci/drm/ttm/ttm_bo_util.c
844
return false;
sys/dev/pci/drm/ttm/ttm_bo_util.c
995
bool bo_locked = false;
sys/dev/pci/drm/ttm/ttm_bo_util.c
999
first = false;
sys/dev/pci/drm/ttm/ttm_bo_vm.c
226
.no_wait_gpu = false,
sys/dev/pci/drm/ttm/ttm_bo_vm.c
528
.no_wait_gpu = false,
sys/dev/pci/drm/ttm/ttm_bo_vm.c
708
ret = ttm_bo_reserve(bo, true, false, NULL);
sys/dev/pci/drm/ttm/ttm_device.c
136
.interruptible = false,
sys/dev/pci/drm/ttm/ttm_device.c
137
.no_wait_gpu = false,
sys/dev/pci/drm/ttm/ttm_device.c
265
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/ttm/ttm_pool.c
56
#define should_fail(...) false
sys/dev/pci/drm/ttm/ttm_pool.c
906
allow_pools = false;
sys/dev/pci/drm/ttm/ttm_range_manager.c
129
return false;
sys/dev/pci/drm/ttm/ttm_range_manager.c
144
return false;
sys/dev/pci/drm/ttm/ttm_range_manager.c
227
ttm_resource_manager_set_used(man, false);
sys/dev/pci/drm/ttm/ttm_resource.c
267
return false;
sys/dev/pci/drm/ttm/ttm_resource.c
338
res->bus.is_iomem = false;
sys/dev/pci/drm/ttm/ttm_resource.c
449
return false;
sys/dev/pci/drm/ttm/ttm_resource.c
476
return false;
sys/dev/pci/drm/ttm/ttm_resource.c
500
return false;
sys/dev/pci/drm/ttm/ttm_resource.c
550
.interruptible = false,
sys/dev/pci/drm/ttm/ttm_resource.c
551
.no_wait_gpu = false,
sys/dev/pci/drm/ttm/ttm_resource.c
569
ret = dma_fence_wait(fence, false);
sys/dev/pci/drm/ttm/ttm_resource.c
755
.maps_tt = false,
sys/dev/pci/drm/ttm/ttm_resource.c
810
.maps_tt = false,
sys/dev/pci/drm/ttm/ttm_resource.c
842
iter_io->needs_unmap = false;
sys/dev/pci/drm/ttm/ttm_tt.c
245
if (bo->bdev->pool.use_dma32 == false)
sys/dev/pci/drm/ttm/ttm_tt.c
511
struct ttm_operation_ctx ctx = { false, false };
sys/dev/pci/if_ice.c
11327
is_tx_fltr = false;
sys/dev/pci/if_ice.c
11328
is_rx_lb_fltr = false;
sys/dev/pci/if_ice.c
11478
bool is_rx_lb_fltr = false;
sys/dev/pci/if_ice.c
11479
bool is_tx_fltr = false;
sys/dev/pci/if_ice.c
11636
bool remove_rule = false;
sys/dev/pci/if_ice.c
12265
bool apply_speed_filter = false;
sys/dev/pci/if_ice.c
1228
return false;
sys/dev/pci/if_ice.c
12289
status = ice_aq_get_phy_caps(pi, false, phy_data->report_mode, &pcaps, NULL);
sys/dev/pci/if_ice.c
12625
status = ice_aq_get_phy_caps(pi, false,
sys/dev/pci/if_ice.c
12896
status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
sys/dev/pci/if_ice.c
13021
status = ice_aq_set_link_restart_an(hw->port_info, false, NULL);
sys/dev/pci/if_ice.c
13033
sc->link_up = false;
sys/dev/pci/if_ice.c
13141
ice_control_all_rx_queues(&sc->pf_vsi, false);
sys/dev/pci/if_ice.c
13563
ice_control_all_rx_queues(&sc->pf_vsi, false);
sys/dev/pci/if_ice.c
13569
ice_set_link(sc, false);
sys/dev/pci/if_ice.c
14461
status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
sys/dev/pci/if_ice.c
14547
return false;
sys/dev/pci/if_ice.c
14957
&flags, false);
sys/dev/pci/if_ice.c
15191
return false;
sys/dev/pci/if_ice.c
15386
return seg_hdr ? true : false;
sys/dev/pci/if_ice.c
15472
bool retval = false;
sys/dev/pci/if_ice.c
15494
bool result = false;
sys/dev/pci/if_ice.c
15519
bool match = false;
sys/dev/pci/if_ice.c
15595
return false;
sys/dev/pci/if_ice.c
15603
return false;
sys/dev/pci/if_ice.c
16067
hw->tnl.tbl[hw->tnl.count].valid = false;
sys/dev/pci/if_ice.c
16068
hw->tnl.tbl[hw->tnl.count].in_use = false;
sys/dev/pci/if_ice.c
16069
hw->tnl.tbl[hw->tnl.count].marked = false;
sys/dev/pci/if_ice.c
16303
bool last = false;
sys/dev/pci/if_ice.c
16341
le32toh(seg->buf_tbl.buf_count), false);
sys/dev/pci/if_ice.c
16496
false, false, false, NULL);
sys/dev/pci/if_ice.c
16537
*dvm = false;
sys/dev/pci/if_ice.c
16589
return false;
sys/dev/pci/if_ice.c
16636
return false;
sys/dev/pci/if_ice.c
16657
return false;
sys/dev/pci/if_ice.c
16662
return false;
sys/dev/pci/if_ice.c
16839
return false;
sys/dev/pci/if_ice.c
16856
hw->dvm_ena = ice_aq_is_dvm_ena(hw) ? true : false;
sys/dev/pci/if_ice.c
1709
return false;
sys/dev/pci/if_ice.c
17576
bool flag = false;
sys/dev/pci/if_ice.c
17606
flag = false;
sys/dev/pci/if_ice.c
17642
bool already_loaded = false;
sys/dev/pci/if_ice.c
18030
resmgr->contig_only = false;
sys/dev/pci/if_ice.c
18279
ice_setup_vsi_common(sc, &sc->pf_vsi, ICE_VSI_PF, 0, false);
sys/dev/pci/if_ice.c
18496
return false;
sys/dev/pci/if_ice.c
18501
return false;
sys/dev/pci/if_ice.c
18665
return false;
sys/dev/pci/if_ice.c
18805
prof->tcam[i].in_use = false;
sys/dev/pci/if_ice.c
19067
status = ice_prof_tcam_ena_dis(hw, blk, false,
sys/dev/pci/if_ice.c
1916
bool cmd_completed = false;
sys/dev/pci/if_ice.c
19236
return false;
sys/dev/pci/if_ice.c
1998
ice_debug_cq(hw, cq, (void *)desc_on_ring, buf, buf_size, false);
sys/dev/pci/if_ice.c
20049
return false;
sys/dev/pci/if_ice.c
20059
return false;
sys/dev/pci/if_ice.c
2009
ice_usec_delay(5, false);
sys/dev/pci/if_ice.c
2015
ice_usec_delay(10, false);
sys/dev/pci/if_ice.c
20353
hw->blk[blk].es.written[prof_id] = false;
sys/dev/pci/if_ice.c
20376
return false;
sys/dev/pci/if_ice.c
20639
bool keep_alloc = false;
sys/dev/pci/if_ice.c
20975
status = ice_free_vsi(hw, vsi->idx, &ctx, false, NULL);
sys/dev/pci/if_ice.c
21221
ice_shutdown_all_ctrlq(hw, false);
sys/dev/pci/if_ice.c
21348
sc->stats.offsets_loaded = false;
sys/dev/pci/if_ice.c
2158
ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false);
sys/dev/pci/if_ice.c
21645
ice_aq_free_vsi(hw, vsi_ctx, false, cd);
sys/dev/pci/if_ice.c
22340
vsi_node->in_use = false;
sys/dev/pci/if_ice.c
22375
status = ice_sched_suspend_resume_elems(hw, 1, &teid, false);
sys/dev/pci/if_ice.c
22460
vsi->hw_stats.offsets_loaded = false;
sys/dev/pci/if_ice.c
23208
return false;
sys/dev/pci/if_ice.c
23425
status = ice_aq_get_phy_caps(pi, false,
sys/dev/pci/if_ice.c
24357
return false;
sys/dev/pci/if_ice.c
25133
status = ice_alloc_hw_res(hw, res_type, 1, false, &get_prof);
sys/dev/pci/if_ice.c
25477
return false;
sys/dev/pci/if_ice.c
25520
status = ice_add_prof_id_vsig(hw, blk, new_vsig, hdl, false, chg);
sys/dev/pci/if_ice.c
25627
status = ice_add_prof_id_vsig(hw, blk, vsig, hdl, false,
sys/dev/pci/if_ice.c
25825
ICE_FLOW_FLD_OFF_INVAL, false);
sys/dev/pci/if_ice.c
25904
false)))
sys/dev/pci/if_ice.c
26125
struct ice_rss_hash_cfg rss_cfg = { 0, 0, ICE_RSS_ANY_HEADERS, false };
sys/dev/pci/if_ice.c
26597
ice_do_dcb_reconfig(sc, false);
sys/dev/pci/if_ice.c
26611
ice_shutdown_all_ctrlq(hw, false);
sys/dev/pci/if_ice.c
26663
sc->hw.reset_ongoing = false;
sys/dev/pci/if_ice.c
26735
bool mdd_detected = false, request_reinit = false;
sys/dev/pci/if_ice.c
26964
status = ice_aq_set_link_restart_an(pi, false, NULL);
sys/dev/pci/if_ice.c
2715
return false;
sys/dev/pci/if_ice.c
27934
bool needs_reconfig = false;
sys/dev/pci/if_ice.c
27941
return (false);
sys/dev/pci/if_ice.c
28918
bool reschedule = false;
sys/dev/pci/if_ice.c
28984
ice_update_link_status(sc, false);
sys/dev/pci/if_ice.c
29993
*dcbx_agent_status = false;
sys/dev/pci/if_ice.c
30109
qos_cfg->is_sw_lldp = false;
sys/dev/pci/if_ice.c
30330
status = ice_aq_get_phy_caps(pi, false, report_mode, &pcaps, NULL);
sys/dev/pci/if_ice.c
30464
ice_set_link(sc, false);
sys/dev/pci/if_ice.c
30476
status = ice_aq_set_link_restart_an(pi, false, NULL);
sys/dev/pci/if_ice.c
3131
hw->fwlog_support_ena = false;
sys/dev/pci/if_ice.c
3229
return false;
sys/dev/pci/if_ice.c
3234
return false;
sys/dev/pci/if_ice.c
3244
return false;
sys/dev/pci/if_ice.c
3251
return false;
sys/dev/pci/if_ice.c
3268
return false;
sys/dev/pci/if_ice.c
3277
return false;
sys/dev/pci/if_ice.c
3282
return false;
sys/dev/pci/if_ice.c
3375
status = ice_aq_fwlog_register(hw, false);
sys/dev/pci/if_ice.c
3463
second_bank_active = false;
sys/dev/pci/if_ice.c
3628
status = ice_read_flat_nvm(hw, offset, &len, &data, false);
sys/dev/pci/if_ice.c
3896
status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
sys/dev/pci/if_ice.c
4403
flash->blank_nvm_mode = false;
sys/dev/pci/if_ice.c
4719
true : false;
sys/dev/pci/if_ice.c
4724
true : false;
sys/dev/pci/if_ice.c
4729
true : false;
sys/dev/pci/if_ice.c
4734
true : false;
sys/dev/pci/if_ice.c
4864
found = false;
sys/dev/pci/if_ice.c
5480
bool is_vf = false;
sys/dev/pci/if_ice.c
6433
return false;
sys/dev/pci/if_ice.c
6458
return false;
sys/dev/pci/if_ice.c
6621
return false;
sys/dev/pci/if_ice.c
6628
return false;
sys/dev/pci/if_ice.c
6879
pi->phy.get_link_info = false;
sys/dev/pci/if_ice.c
7178
return false;
sys/dev/pci/if_ice.c
7273
hw->blk[blk].xlt2.vsig_tbl[idx].in_use = false;
sys/dev/pci/if_ice.c
7402
hw->blk[i].is_list_init = false;
sys/dev/pci/if_ice.c
7471
false, false },
sys/dev/pci/if_ice.c
7473
false, false },
sys/dev/pci/if_ice.c
7475
false, true },
sys/dev/pci/if_ice.c
7479
false, false },
sys/dev/pci/if_ice.c
7757
status = ice_aq_get_phy_caps(hw->port_info, false,
sys/dev/pci/if_ice.c
7765
status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
sys/dev/pci/if_ice.c
7803
status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, false,
sys/dev/pci/if_ice.c
8104
fi->lb_en = false;
sys/dev/pci/if_ice.c
8105
fi->lan_en = false;
sys/dev/pci/if_ice.c
8155
fi->lb_en = false;
sys/dev/pci/if_ice.c
8585
*vsi_list_id, false,
sys/dev/pci/if_ice.c
8864
vsi_list_id, false, opcode,
sys/dev/pci/if_ice.c
9322
return false;
sys/dev/pci/if_ice.c
9330
return false;
sys/dev/pci/if_ice.c
9996
bool found = false;
sys/dev/pci/if_icevar.h
177
return false;
sys/dev/pci/if_icevar.h
186
return false;
sys/dev/pci/if_icevar.h
554
return false;
sys/dev/pci/if_icevar.h
559
return false;
sys/dev/pci/if_igc.c
225
hw->phy.autoneg_wait_to_complete = false;
sys/dev/pci/if_mwx.c
4218
&req_mu, sizeof(req_mu), false);
sys/dev/pci/if_mwx.c
4418
cck = false;
sys/dev/pci/if_qwx_pci.c
2147
qwx_pci_msi_config(sc, false);
sys/dev/pci/if_qwx_pci.c
2221
qwx_pci_sw_reset(sc, false);
sys/dev/pci/if_qwz_pci.c
2014
qwz_pci_msi_config(sc, false);
sys/dev/pci/if_qwz_pci.c
2088
qwz_pci_sw_reset(sc, false);
sys/dev/pci/igc_i225.c
1032
mac->get_link_status = false;
sys/dev/pci/igc_i225.c
396
hw->dev_spec._i225.clear_semaphore_once = false;
sys/dev/pci/igc_i225.c
680
bool ret_val = false;
sys/dev/pci/igc_i225.c
996
bool link = false;
sys/dev/pci/igc_phy.c
590
phy->speed_downgraded = false;
sys/dev/pci/igc_phy.c
926
return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
sys/dev/usb/dwc2/dwc2.c
1195
bool qh_allocated = false;
sys/dev/usb/dwc2/dwc2.c
1325
sc->sc_hcdenabled = false;
sys/dev/usb/dwc2/dwc2.c
1361
retval = dwc2_core_reset(hsotg, false);
sys/dev/usb/dwc2/dwc2_core.c
1033
retval = dwc2_core_reset(hsotg, false);
sys/dev/usb/dwc2/dwc2_core.c
1131
retval = dwc2_core_reset(hsotg, false);
sys/dev/usb/dwc2/dwc2_core.c
119
gr->valid = false;
sys/dev/usb/dwc2/dwc2_core.c
369
return false;
sys/dev/usb/dwc2/dwc2_core.c
374
return false;
sys/dev/usb/dwc2/dwc2_core.c
385
return false;
sys/dev/usb/dwc2/dwc2_core.c
433
bool wait_for_host_mode = false;
sys/dev/usb/dwc2/dwc2_core.c
621
dwc2_force_mode(hsotg, false);
sys/dev/usb/dwc2/dwc2_core.c
873
return false;
sys/dev/usb/dwc2/dwc2_core.h
1580
{ return false; }
sys/dev/usb/dwc2/dwc2_coreintr.c
247
dwc2_hcd_disconnect(hsotg, false);
sys/dev/usb/dwc2/dwc2_coreintr.c
501
dwc2_hcd_disconnect(hsotg, false);
sys/dev/usb/dwc2/dwc2_coreintr.c
742
dwc2_core_init(hsotg, false);
sys/dev/usb/dwc2/dwc2_coreintr.c
744
dwc2_hsotg_core_init_disconnected(hsotg, false);
sys/dev/usb/dwc2/dwc2_coreintr.c
750
dwc2_core_init(hsotg, false);
sys/dev/usb/dwc2/dwc2_hcd.c
1069
xfer_ns = dwc2_usb_calc_bus_time(host_speed, false, false,
sys/dev/usb/dwc2/dwc2_hcd.c
142
hsotg->params.dma_desc_enable = false;
sys/dev/usb/dwc2/dwc2_hcd.c
2146
retval = dwc2_core_reset(hsotg, false);
sys/dev/usb/dwc2/dwc2_hcd.c
2258
hsotg->params.dma_desc_enable = false;
sys/dev/usb/dwc2/dwc2_hcd.c
2932
bool no_queue_space = false;
sys/dev/usb/dwc2/dwc2_hcd.c
2933
bool no_fifo_space = false;
sys/dev/usb/dwc2/dwc2_hcd.c
3263
dwc2_exit_partial_power_down(hsotg, 0, false);
sys/dev/usb/dwc2/dwc2_hcd.c
3266
dwc2_core_init(hsotg, false);
sys/dev/usb/dwc2/dwc2_hcd.c
3269
dwc2_hsotg_core_init_disconnected(hsotg, false);
sys/dev/usb/dwc2/dwc2_hcd.c
3296
dwc2_core_init(hsotg, false);
sys/dev/usb/dwc2/dwc2_hcd.c
3321
hsotg->bus_suspended = false;
sys/dev/usb/dwc2/dwc2_hcd.c
3687
hsotg->new_connection = false;
sys/dev/usb/dwc2/dwc2_hcd.c
4630
dwc2_core_init(hsotg, false);
sys/dev/usb/dwc2/dwc2_hcd.c
4656
usb_phy_set_suspend(hsotg->uphy, false);
sys/dev/usb/dwc2/dwc2_hcd.c
4787
bool qh_allocated = false;
sys/dev/usb/dwc2/dwc2_hcd.c
5493
hr->valid = false;
sys/dev/usb/dwc2/dwc2_hcd.c
5756
return false;
sys/dev/usb/dwc2/dwc2_hcd.c
5901
hsotg->bus_suspended = false;
sys/dev/usb/dwc2/dwc2_hcd.c
6000
hsotg->bus_suspended = false;
sys/dev/usb/dwc2/dwc2_hcd.h
643
static inline bool dbg_perio(void) { return false; }
sys/dev/usb/dwc2/dwc2_hcdintr.c
1828
return false;
sys/dev/usb/dwc2/dwc2_hcdintr.c
1843
return false;
sys/dev/usb/dwc2/dwc2_hcdintr.c
2060
return false;
sys/dev/usb/dwc2/dwc2_hcdintr.c
419
hsotg->params.dma_desc_enable = false;
sys/dev/usb/dwc2/dwc2_hcdintr.c
420
hsotg->new_connection = false;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1010
return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1263
qh->unreserve_pending = false;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1490
qh->want_wait = false;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1751
qh->wait_timer_cancel = false;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
465
bool printed = false;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
617
qh->device_interval, search_slice, false);
sys/dev/usb/dwc2/dwc2_params.c
106
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
107
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
117
p->i2c_enable = false;
sys/dev/usb/dwc2/dwc2_params.c
118
p->reload_ctl = false;
sys/dev/usb/dwc2/dwc2_params.c
129
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
141
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
154
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
187
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
188
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
201
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
202
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
216
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
217
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
233
p->lpm = false;
sys/dev/usb/dwc2/dwc2_params.c
234
p->lpm_clock_gating = false;
sys/dev/usb/dwc2/dwc2_params.c
235
p->besl = false;
sys/dev/usb/dwc2/dwc2_params.c
236
p->hird_threshold_en = false;
sys/dev/usb/dwc2/dwc2_params.c
250
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
251
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
258
p->i2c_enable = false;
sys/dev/usb/dwc2/dwc2_params.c
275
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
276
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
284
p->i2c_enable = false;
sys/dev/usb/dwc2/dwc2_params.c
297
p->otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
298
p->otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
306
p->lpm = false;
sys/dev/usb/dwc2/dwc2_params.c
307
p->lpm_clock_gating = false;
sys/dev/usb/dwc2/dwc2_params.c
308
p->besl = false;
sys/dev/usb/dwc2/dwc2_params.c
309
p->hird_threshold_en = false;
sys/dev/usb/dwc2/dwc2_params.c
370
hsotg->params.otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
374
hsotg->params.otg_caps.hnp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
375
hsotg->params.otg_caps.srp_support = false;
sys/dev/usb/dwc2/dwc2_params.c
478
p->lpm_clock_gating = false;
sys/dev/usb/dwc2/dwc2_params.c
479
p->besl = false;
sys/dev/usb/dwc2/dwc2_params.c
480
p->hird_threshold_en = false;
sys/dev/usb/dwc2/dwc2_params.c
503
p->phy_ulpi_ddr = false;
sys/dev/usb/dwc2/dwc2_params.c
504
p->phy_ulpi_ext_vbus = false;
sys/dev/usb/dwc2/dwc2_params.c
510
p->ulpi_fs_ls = false;
sys/dev/usb/dwc2/dwc2_params.c
511
p->ts_dline = false;
sys/dev/usb/dwc2/dwc2_params.c
514
p->external_id_pin_ctl = false;
sys/dev/usb/dwc2/dwc2_params.c
515
p->ipg_isoc_en = false;
sys/dev/usb/dwc2/dwc2_params.c
516
p->service_interval = false;
sys/dev/usb/dwc2/dwc2_params.c
526
p->dma_desc_enable = false;
sys/dev/usb/dwc2/dwc2_params.c
527
p->dma_desc_fs_enable = false;
sys/dev/usb/dwc2/dwc2_params.c
528
p->host_support_fs_ls_low_power = false;
sys/dev/usb/dwc2/dwc2_params.c
529
p->host_ls_low_power_phy_clk = false;
sys/dev/usb/dwc2/dwc2_params.c
783
hsotg->params._param = false; \
sys/dev/usb/dwc2/dwc2_params.c
893
dwc2_force_mode(hsotg, false);
sys/dev/usb/ukspan.c
572
ukspan_cmsg_init(false, &sc->cmsg);
sys/kern/kern_rwlock.c
762
return false;
sys/sys/types.h
251
#define false false
sys/tmpfs/tmpfs_subr.c
728
KASSERT(false);
usr.bin/awk/awkgram.y
187
{ infunc = false; curfname=0; defn((Cell *)$2, $4, $8); $$ = 0; }
usr.bin/awk/awkgram.y
36
bool infunc = false; /* = true if in arglist or body of func */
usr.bin/awk/b.c
1417
commafound = false;
usr.bin/awk/b.c
1418
digitfound = false;
usr.bin/awk/b.c
1478
digitfound = false; /* reset */
usr.bin/awk/b.c
963
return false;
usr.bin/awk/lex.c
178
bool sc = false; /* true => return a } right now */
usr.bin/awk/lex.c
179
bool reg = false; /* true => return a REGEXPR now */
usr.bin/awk/lex.c
190
sc = false;
usr.bin/awk/lex.c
194
reg = false;
usr.bin/awk/lib.c
147
firsttime = false;
usr.bin/awk/lib.c
178
innew = false;
usr.bin/awk/lib.c
191
donefld = false;
usr.bin/awk/lib.c
232
isrec = (c == EOF && rr == buf) ? false : true;
usr.bin/awk/lib.c
248
isrec = (found == 0 && *buf == '\0') ? false : true;
usr.bin/awk/lib.c
278
isrec = (c == EOF && rr == buf) ? false : true;
usr.bin/awk/lib.c
299
bool in_quote = false;
usr.bin/awk/lib.c
879
bool retval = false;
usr.bin/awk/lib.c
880
bool is_nan = false;
usr.bin/awk/lib.c
881
bool is_inf = false;
usr.bin/awk/lib.c
884
*no_trailing = false;
usr.bin/awk/lib.c
891
return false;
usr.bin/awk/lib.c
901
return false;
usr.bin/awk/lib.c
904
return false;
usr.bin/awk/lib.c
910
return false;
usr.bin/awk/main.c
55
bool CSV = false; /* true for csv input */
usr.bin/awk/main.c
56
bool safe = false; /* true => "safe" mode */
usr.bin/awk/main.c
57
bool do_posix = false; /* true => POSIX mode */
usr.bin/awk/proto.h
150
#define is_number(s, val) is_valid_number(s, false, NULL, val)
usr.bin/awk/run.c
1089
static bool have_a_format = false;
usr.bin/awk/run.c
1096
first = false;
usr.bin/awk/run.c
2380
*pnewflag = false;
usr.bin/awk/run.c
2486
bool stat = false;
usr.bin/awk/run.c
452
n = getrec(&buf, &bufsize, false);
usr.bin/awk/tran.c
306
donerec = false; /* mark $0 invalid */
usr.bin/awk/tran.c
312
donerec = false; /* mark $0 invalid */
usr.bin/awk/tran.c
316
donefld = false; /* mark $1... invalid */
usr.bin/awk/tran.c
359
donerec = false; /* mark $0 invalid */
usr.bin/awk/tran.c
365
donefld = false; /* mark $1... invalid */
usr.bin/awk/tran.c
382
donerec = false; /* mark $0 invalid */
usr.bin/bc/bc.y
1120
do_fork = false;
usr.bin/bc/bc.y
182
st_has_continue = false;
usr.bin/bc/bc.y
188
st_has_continue = false;
usr.bin/chpass/getpwent.c
233
return getpwnam_internal(name, pw, buf, buflen, pwretp, false, true);
usr.bin/chpass/getpwent.c
242
my_errno = getpwnam_internal(name, NULL, NULL, 0, &pw, false, false);
usr.bin/chpass/getpwent.c
256
my_errno = getpwnam_internal(name, NULL, NULL, 0, &pw, true, false);
usr.bin/chpass/getpwent.c
308
return getpwuid_internal(uid, pw, buf, buflen, pwretp, false, true);
usr.bin/chpass/getpwent.c
317
my_errno = getpwuid_internal(uid, NULL, NULL, 0, &pw, false, false);
usr.bin/chpass/getpwent.c
331
my_errno = getpwuid_internal(uid, NULL, NULL, 0, &pw, true, false);
usr.bin/chpass/getpwent.c
89
remap = false;
usr.bin/chpass/getpwent.c
99
remap = false;
usr.bin/dc/bcode.c
1440
return false;
usr.bin/dc/bcode.c
1690
bmachine.interrupted = false;
usr.bin/dc/dc.c
44
bool extended_regs = false;
usr.bin/dc/inout.c
182
bool sign = false;
usr.bin/dc/inout.c
183
bool dot = false;
usr.bin/dc/inout.c
236
escape = false;
usr.bin/dc/inout.c
254
escape = false;
usr.bin/grep/util.c
636
return false;
usr.bin/indent/args.c
101
{"eei", PRO_BOOL, false, ON, &extra_expression_indent },
usr.bin/indent/args.c
115
{"nbacc", PRO_BOOL, false, OFF,
usr.bin/indent/args.c
117
{"nbadp", PRO_BOOL, false, OFF,
usr.bin/indent/args.c
119
{"nbad", PRO_BOOL, false, OFF, &blanklines_after_declarations },
usr.bin/indent/args.c
120
{"nbap", PRO_BOOL, false, OFF, &blanklines_after_procs },
usr.bin/indent/args.c
121
{"nbbb", PRO_BOOL, false, OFF, &blanklines_before_blockcomments },
usr.bin/indent/args.c
123
{"nbs", PRO_BOOL, false, OFF, &Bill_Shannon },
usr.bin/indent/args.c
126
{"ndj", PRO_BOOL, false, OFF, &ps.ljust_decl },
usr.bin/indent/args.c
127
{"neei", PRO_BOOL, false, OFF, &extra_expression_indent },
usr.bin/indent/args.c
132
{"npcs", PRO_BOOL, false, OFF, &proc_calls_space },
usr.bin/indent/args.c
135
{"nps", PRO_BOOL, false, OFF, &pointer_as_binop },
usr.bin/indent/args.c
137
{"nsob", PRO_BOOL, false, OFF, &swallow_optional_blanklines },
usr.bin/indent/args.c
139
{"nv", PRO_BOOL, false, OFF, &verbose },
usr.bin/indent/args.c
140
{"pcs", PRO_BOOL, false, ON, &proc_calls_space },
usr.bin/indent/args.c
142
{"ps", PRO_BOOL, false, ON, &pointer_as_binop },
usr.bin/indent/args.c
144
{"sob", PRO_BOOL, false, ON, &swallow_optional_blanklines },
usr.bin/indent/args.c
146
{"troff", PRO_BOOL, false, ON, &troff },
usr.bin/indent/args.c
148
{"v", PRO_BOOL, false, ON, &verbose },
usr.bin/indent/args.c
216
return (false);
usr.bin/indent/args.c
290
*p->p_obj = false;
usr.bin/indent/args.c
81
{"bacc", PRO_BOOL, false, ON,
usr.bin/indent/args.c
83
{"badp", PRO_BOOL, false, ON,
usr.bin/indent/args.c
85
{"bad", PRO_BOOL, false, ON, &blanklines_after_declarations },
usr.bin/indent/args.c
86
{"bap", PRO_BOOL, false, ON, &blanklines_after_procs },
usr.bin/indent/args.c
87
{"bbb", PRO_BOOL, false, ON, &blanklines_before_blockcomments },
usr.bin/indent/args.c
91
{"bs", PRO_BOOL, false, ON, &Bill_Shannon },
usr.bin/indent/args.c
99
{"dj", PRO_BOOL, false, ON, &ps.ljust_decl },
usr.bin/indent/indent.c
1028
ps.want_blank = false;
usr.bin/indent/indent.c
1072
ps.want_blank = false;
usr.bin/indent/indent.c
1080
ps.want_blank = false;
usr.bin/indent/indent.c
1084
sp_sw = false;
usr.bin/indent/indent.c
1087
ps.in_stmt = false;
usr.bin/indent/indent.c
1114
ps.want_blank = false; /* dont put a blank after a period */
usr.bin/indent/indent.c
1223
ps.pcase = false;
usr.bin/indent/indent.c
1273
flushed_nl = false;
usr.bin/indent/indent.c
1275
ps.want_blank = false; /* dont insert blank at line start */
usr.bin/indent/indent.c
1276
force_nl = false;
usr.bin/indent/indent.c
244
had_eof = ps.in_decl = ps.decl_on_line = break_comma = false;
usr.bin/indent/indent.c
245
sp_sw = force_nl = false;
usr.bin/indent/indent.c
246
ps.in_or_st = false;
usr.bin/indent/indent.c
250
ps.want_blank = ps.in_stmt = ps.ind_stmt = false;
usr.bin/indent/indent.c
253
scase = ps.pcase = false;
usr.bin/indent/indent.c
412
flushed_nl = false;
usr.bin/indent/indent.c
431
ps.search_brace = false;
usr.bin/indent/indent.c
485
force_nl = false;
usr.bin/indent/indent.c
489
ps.search_brace = false;
usr.bin/indent/indent.c
494
force_nl = false;
usr.bin/indent/indent.c
502
flushed_nl = false;
usr.bin/indent/indent.c
509
ps.search_brace = false; /* stop looking for start of
usr.bin/indent/indent.c
559
flushed_nl = false;
usr.bin/indent/indent.c
561
ps.want_blank = false; /* dont insert blank at line start */
usr.bin/indent/indent.c
562
force_nl = false;
usr.bin/indent/indent.c
576
ps.want_blank = false;
usr.bin/indent/indent.c
581
force_nl = false; /* cancel forced newline after newline, form
usr.bin/indent/indent.c
595
ps.want_blank = false;
usr.bin/indent/indent.c
602
ps.want_blank = false;
usr.bin/indent/indent.c
634
ps.want_blank = false;
usr.bin/indent/indent.c
642
ps.in_or_st = false; /* turn off flag for structure decl or
usr.bin/indent/indent.c
668
sp_sw = false;
usr.bin/indent/indent.c
672
ps.in_stmt = false; /* dont use stmt continuation
usr.bin/indent/indent.c
714
ps.want_blank = false;
usr.bin/indent/indent.c
783
ps.want_blank = false;
usr.bin/indent/indent.c
786
ps.in_stmt = false; /* seeing a label does not imply we are in a
usr.bin/indent/indent.c
800
scase = false;
usr.bin/indent/indent.c
801
ps.want_blank = false;
usr.bin/indent/indent.c
805
ps.in_or_st = false;/* we are not in an initialization or
usr.bin/indent/indent.c
807
scase = false; /* these will only need resetting in a error */
usr.bin/indent/indent.c
838
sp_sw = false;
usr.bin/indent/indent.c
854
ps.in_stmt = false; /* dont indent the {} */
usr.bin/indent/indent.c
866
ps.want_blank = false;
usr.bin/indent/indent.c
871
ps.want_blank = false;
usr.bin/indent/indent.c
882
sp_sw = false;
usr.bin/indent/indent.c
888
ps.ind_stmt = false; /* dont put extra indentation on line
usr.bin/indent/indent.c
896
ps.decl_on_line = false;
usr.bin/indent/indent.c
909
ps.want_blank = false;
usr.bin/indent/indent.c
922
sp_sw = false;
usr.bin/indent/indent.c
934
ps.in_stmt = ps.ind_stmt = false;
usr.bin/indent/indent.c
968
ps.in_stmt = false;
usr.bin/indent/indent.c
974
ps.want_blank = false;
usr.bin/indent/indent.c
985
ps.want_blank = false;
usr.bin/indent/io.c
127
ps.pcase = false;
usr.bin/indent/io.c
268
ps.use_ff = false;
usr.bin/indent/io.c
77
ps.bl_line = false;
usr.bin/indent/lexi.c
129
unary_delim = false;
usr.bin/indent/lexi.c
132
ps.last_nl = false;
usr.bin/indent/lexi.c
135
ps.col_1 = false; /* leading blanks imply token is not in column
usr.bin/indent/lexi.c
224
ps.its_a_keyword = false;
usr.bin/indent/lexi.c
225
ps.sizeof_keyword = false;
usr.bin/indent/lexi.c
228
l_struct = false;
usr.bin/indent/lexi.c
233
ps.last_u_d = false; /* Operator after identifier is binary */
usr.bin/indent/lexi.c
457
unary_delim = false;
usr.bin/indent/lexi.c
473
unary_delim = false;
usr.bin/indent/lexi.c
483
unary_delim = false;
usr.bin/indent/lexi.c
485
ps.want_blank = false;
usr.bin/indent/lexi.c
554
l_struct = false;
usr.bin/indent/parse.c
179
break_comma = false; /* turn off flag to break after commas in a
usr.bin/indent/parse.c
95
break_comma = false; /* don't break comma in an initial list */
usr.bin/indent/pr_comment.c
94
ps.box_com = false; /* at first, assume that we are not in
usr.bin/jot/jot.c
103
boring = word = false;
usr.bin/jot/jot.c
107
finalnl = false;
usr.bin/jot/jot.c
123
boring = chardata = false;
usr.bin/jot/jot.c
98
chardata = word = false;
usr.bin/lex/ccl.c
223
ccl_has_nl[lastccl] = false;
usr.bin/lex/ccl.c
295
return false;
usr.bin/lex/ccl.c
314
return (isupper(c) || islower(c)) ? true : false;
usr.bin/lex/dfa.c
238
static int did_stk_init = false, *stk;
usr.bin/lex/dfa.c
415
symlist[i] = false;
usr.bin/lex/filter.c
347
bool last_was_blank = false;
usr.bin/lex/filter.c
403
in_gen = false;
usr.bin/lex/filter.c
407
last_was_blank = false;
usr.bin/lex/filter.c
418
last_was_blank = false;
usr.bin/lex/flexdef.h
1099
#define b_isalnum(c) (isalnum(c)?true:false)
usr.bin/lex/flexdef.h
1100
#define b_isalpha(c) (isalpha(c)?true:false)
usr.bin/lex/flexdef.h
1101
#define b_isascii(c) (isascii(c)?true:false)
usr.bin/lex/flexdef.h
1102
#define b_isblank(c) (isblank(c)?true:false)
usr.bin/lex/flexdef.h
1103
#define b_iscntrl(c) (iscntrl(c)?true:false)
usr.bin/lex/flexdef.h
1104
#define b_isdigit(c) (isdigit(c)?true:false)
usr.bin/lex/flexdef.h
1105
#define b_isgraph(c) (isgraph(c)?true:false)
usr.bin/lex/flexdef.h
1106
#define b_islower(c) (islower(c)?true:false)
usr.bin/lex/flexdef.h
1107
#define b_isprint(c) (isprint(c)?true:false)
usr.bin/lex/flexdef.h
1108
#define b_ispunct(c) (ispunct(c)?true:false)
usr.bin/lex/flexdef.h
1109
#define b_isspace(c) (isspace(c)?true:false)
usr.bin/lex/flexdef.h
1110
#define b_isupper(c) (isupper(c)?true:false)
usr.bin/lex/flexdef.h
1111
#define b_isxdigit(c) (isxdigit(c)?true:false)
usr.bin/lex/gen.c
1503
int did_eof_rule = false;
usr.bin/lex/gen.c
842
gen_next_state(false);
usr.bin/lex/main.c
1037
ddebug = false;
usr.bin/lex/main.c
1041
useecs = usemecs = false;
usr.bin/lex/main.c
1046
useecs = usemecs = false;
usr.bin/lex/main.c
1076
do_yywrap = false;
usr.bin/lex/main.c
1084
gen_line_dirs = false;
usr.bin/lex/main.c
1113
reentrant = false;
usr.bin/lex/main.c
1121
spprdflt = false;
usr.bin/lex/main.c
1159
nowarn = false;
usr.bin/lex/main.c
1179
long_align = false;
usr.bin/lex/main.c
1195
yytext_is_array = false;
usr.bin/lex/main.c
1203
useecs = false;
usr.bin/lex/main.c
1215
usemecs = false;
usr.bin/lex/main.c
1256
do_stdinit = false;
usr.bin/lex/main.c
1268
do_yylineno = false;
usr.bin/lex/main.c
1276
do_yywrap = false;
usr.bin/lex/main.c
1284
yymore_really_used = false;
usr.bin/lex/main.c
1292
reject_really_used = false;
usr.bin/lex/main.c
1296
ansi_func_defs = false;
usr.bin/lex/main.c
1300
ansi_func_protos = false;
usr.bin/lex/main.c
1404
variable_trailing_context_rules = bol_needed = false;
usr.bin/lex/main.c
1474
else if (yymore_really_used == false)
usr.bin/lex/main.c
1475
yymore_used = false;
usr.bin/lex/main.c
1479
else if (reject_really_used == false)
usr.bin/lex/main.c
1480
reject = false;
usr.bin/lex/main.c
242
use_read = false;
usr.bin/lex/main.c
259
interactive = false;
usr.bin/lex/main.c
285
yytext_is_array = false;
usr.bin/lex/main.c
364
gentables = false;
usr.bin/lex/main.c
747
if (interactive == false)
usr.bin/lex/main.c
907
printstats = syntaxerror = trace = spprdflt = false;
usr.bin/lex/main.c
909
ddebug = fulltbl = false;
usr.bin/lex/main.c
911
false;
usr.bin/lex/main.c
913
false;
usr.bin/lex/main.c
917
reentrant = bison_bridge_lval = bison_bridge_lloc = false;
usr.bin/lex/main.c
922
use_read = use_stdout = false;
usr.bin/lex/main.c
923
tablesext = tablesverify = false;
usr.bin/lex/main.c
928
sawcmpflag = false;
usr.bin/lex/main.c
981
interactive = false;
usr.bin/lex/main.c
993
useecs = false;
usr.bin/lex/main.c
994
usemecs = false;
usr.bin/lex/main.c
995
fulltbl = false;
usr.bin/lex/nfa.c
710
rule_useful[num_rules] = false;
usr.bin/lex/nfa.c
711
rule_has_nl[num_rules] = false;
usr.bin/lex/parse.y
131
finish_rule( def_rule, false, 0, 0, 0);
usr.bin/lex/parse.y
150
scinstal( "INITIAL", false );
usr.bin/lex/parse.y
170
{ xcluflg = false; }
usr.bin/lex/parse.y
220
trlcontxt = variable_trail_rule = varlength = false;
usr.bin/lex/parse.y
440
varlength = false;
usr.bin/lex/parse.y
523
varlength = false;
usr.bin/lex/parse.y
77
static int madeany = false; /* whether we've made the '.' character class */
usr.bin/lex/parse.y
869
cclsorted = false;
usr.bin/lex/sym.c
243
sceof[lastsc] = false;
usr.bin/lex/yylex.c
46
static int beglin = false;
usr.bin/make/arch.c
224
subst_lib = false;
usr.bin/make/arch.c
229
return false;
usr.bin/make/arch.c
243
return false;
usr.bin/make/arch.c
251
bool subst_member = false;
usr.bin/make/arch.c
259
return false;
usr.bin/make/arch.c
271
return false;
usr.bin/make/arch.c
314
return false;
usr.bin/make/cmd_exec.c
161
run_command(cmd, false);
usr.bin/make/cond.c
1052
skipLine = false;
usr.bin/make/cond.c
1144
value = false;
usr.bin/make/cond.c
129
{ false,false, CondDoDefined }, /* if, ifdef */
usr.bin/make/cond.c
130
{ false,true, CondDoDefined }, /* ifndef */
usr.bin/make/cond.c
131
{ false,false, CondDoMake }, /* ifmake */
usr.bin/make/cond.c
132
{ false,true, CondDoMake }, /* ifnmake */
usr.bin/make/cond.c
133
{ true, false, CondDoDefined }, /* elif, elifdef */
usr.bin/make/cond.c
135
{ true, false, CondDoMake }, /* elifmake */
usr.bin/make/cond.c
137
{ true, false, NULL }
usr.bin/make/cond.c
167
static bool skipLine = false; /* Whether the parse module is skipping lines */
usr.bin/make/cond.c
203
arg->tofree = false;
usr.bin/make/cond.c
214
return false;
usr.bin/make/cond.c
218
return false;
usr.bin/make/cond.c
233
return false;
usr.bin/make/cond.c
278
return false;
usr.bin/make/cond.c
304
result = false;
usr.bin/make/cond.c
327
return false;
usr.bin/make/cond.c
348
return false;
usr.bin/make/cond.c
381
return false;
usr.bin/make/cond.c
658
bool invert = false;
usr.bin/make/cond.c
720
CondGetArg(&condExpr, &arg, "", false);
usr.bin/make/cond.c
868
(void)CondF(false);
usr.bin/make/cond.c
909
(void)CondE(false);
usr.bin/make/cond.c
935
bool value = false;
usr.bin/make/dir.c
307
return false;
usr.bin/make/dir.c
436
hasSlash = false;
usr.bin/make/dir.c
530
bool checkedDot = false;
usr.bin/make/dir.h
105
#define Dir_FindFileNoDoti(n, e, p) Dir_FindFileComplexi(n, e, p, false)
usr.bin/make/direxpand.c
191
dowild = false;
usr.bin/make/direxpand.c
309
bool wild = false;
usr.bin/make/direxpand.c
320
return false;
usr.bin/make/direxpand.c
329
return false;
usr.bin/make/dump.c
173
first = false;
usr.bin/make/dump.c
203
static bool dumped_once = false;
usr.bin/make/dump.c
210
targ_dump(false);
usr.bin/make/engine.c
115
return false;
usr.bin/make/engine.c
156
return false;
usr.bin/make/engine.c
174
first = false;
usr.bin/make/engine.c
371
do_oodate = false;
usr.bin/make/engine.c
456
oodate = false;
usr.bin/make/engine.c
491
oodate = false;
usr.bin/make/engine.c
531
silent = false;
usr.bin/make/engine.c
635
return false;
usr.bin/make/engine.c
640
silent = DEBUG(LOUD) ? false : true;
usr.bin/make/engine.c
642
errCheck = false;
usr.bin/make/engine.c
662
return false;
usr.bin/make/engine.c
668
return false;
usr.bin/make/engine.c
711
job->cmd = Var_Subst(command->string, &gn->localvars, false);
usr.bin/make/engine.c
717
return false;
usr.bin/make/error.c
153
first = false;
usr.bin/make/for.c
175
sub = Var_Subst(ptr, NULL, false);
usr.bin/make/for.c
229
return false;
usr.bin/make/for.c
258
arg->freeold = false;
usr.bin/make/job.c
215
first = false;
usr.bin/make/job.c
257
first = false;
usr.bin/make/job.c
289
first = false;
usr.bin/make/job.c
429
first = false;
usr.bin/make/job.c
592
return false;
usr.bin/make/job.c
602
bool include = false;
usr.bin/make/job.c
603
bool expensive = false;
usr.bin/make/job.c
607
return false;
usr.bin/make/job.c
614
include = false;
usr.bin/make/job.c
637
expensive = false;
usr.bin/make/job.c
645
return false;
usr.bin/make/job.c
708
no_new_jobs = false;
usr.bin/make/job.c
753
bool reaped = false;
usr.bin/make/job.c
850
return false;
usr.bin/make/job.c
888
ignoreErrors = false;
usr.bin/make/lst.lib/lstAddNew.c
42
return false;
usr.bin/make/main.c
143
keepgoing = false;
usr.bin/make/main.c
585
vpath = Var_Subst("${VPATH}", NULL, false);
usr.bin/make/main.c
648
bool outOfDate = false; /* false if all targets up to date */
usr.bin/make/main.c
649
bool errored = false; /* true if errors occurred */
usr.bin/make/main.c
670
beSilent = false; /* Print commands as executed */
usr.bin/make/main.c
671
ignoreErrors = false; /* Pay attention to non-zero returns */
usr.bin/make/main.c
672
noExecute = false; /* Execute all commands */
usr.bin/make/main.c
673
keepgoing = false; /* Stop on error */
usr.bin/make/main.c
674
allPrecious = false; /* Remove targets when interrupted */
usr.bin/make/main.c
675
queryFlag = false; /* This is not just a check-run */
usr.bin/make/main.c
676
noBuiltins = false; /* Read the built-in rules */
usr.bin/make/main.c
677
touchFlag = false; /* Actually update targets */
usr.bin/make/main.c
681
compatMake = false; /* No compat mode */
usr.bin/make/main.c
743
read_depend = false;
usr.bin/make/main.c
79
static bool forceJobs = false;
usr.bin/make/main.c
913
return false;
usr.bin/make/main.c
918
return false;
usr.bin/make/main.c
920
return false;
usr.bin/make/make.c
165
return false;
usr.bin/make/make.c
178
return false;
usr.bin/make/make.c
314
return false;
usr.bin/make/make.c
322
return false;
usr.bin/make/make.c
327
return false;
usr.bin/make/make.c
332
return false;
usr.bin/make/make.c
341
return false;
usr.bin/make/make.c
355
return false;
usr.bin/make/make.c
369
return false;
usr.bin/make/make.c
393
return false;
usr.bin/make/make.c
420
return false;
usr.bin/make/make.c
597
bool cycle = false;
usr.bin/make/make.c
608
first = false;
usr.bin/make/make.c
688
gn->in_cycle = false;
usr.bin/make/parse.c
103
static bool htargets_setup = false;
usr.bin/make/parse.c
1183
isSystem = false;
usr.bin/make/parse.c
1188
return false;
usr.bin/make/parse.c
1196
return false;
usr.bin/make/parse.c
1201
file2 = Var_Substi(file, efile, NULL, false);
usr.bin/make/parse.c
1215
bool okay = false;
usr.bin/make/parse.c
1219
file = Var_Subst(line, NULL, false);
usr.bin/make/parse.c
1256
lookup_sysv_style_include(file, directive, false);
usr.bin/make/parse.c
1273
bool not = false;
usr.bin/make/parse.c
1274
bool paren_to_match = false;
usr.bin/make/parse.c
1303
paren_to_match = false;
usr.bin/make/parse.c
1328
return false;
usr.bin/make/parse.c
1350
return false;
usr.bin/make/parse.c
1357
return false;
usr.bin/make/parse.c
1409
return false;
usr.bin/make/parse.c
1430
return false;
usr.bin/make/parse.c
1437
bool seen_target = false;
usr.bin/make/parse.c
1576
return false;
usr.bin/make/parse.c
1610
cp = Var_Subst(stripped, NULL, false);
usr.bin/make/parse.c
1630
bool expectingCommands = false;
usr.bin/make/parse.c
1631
bool commands_seen = false;
usr.bin/make/parse.c
1658
commands_seen = false;
usr.bin/make/parse.c
1660
expectingCommands = false;
usr.bin/make/parse.c
603
return false;
usr.bin/make/parse.c
611
return false;
usr.bin/make/parsevar.c
132
return false;
usr.bin/make/parsevar.c
183
errorIsOkay = false;
usr.bin/make/parsevar.c
189
res2 = Var_Subst(arg, NULL, false);
usr.bin/make/parsevar.c
220
errorIsOkay = false;
usr.bin/make/regress.c
54
CHECK(Str_Match("string", "string2") == false);
usr.bin/make/regress.c
57
CHECK(Str_Match("Long string", "Lo*ng ") == false);
usr.bin/make/regress.c
62
CHECK(Str_Match("Very long string just to see", "******a****") == false);
usr.bin/make/regress.c
64
CHECK(Str_Match("d[abc!", "d\\[abc\\?") == false);
usr.bin/make/regress.c
65
CHECK(Str_Match("dwabc?", "d\\[abc\\?") == false);
usr.bin/make/regress.c
69
CHECK(Str_Match("dy0", "d[a\\-z]0") == false);
usr.bin/make/stats.c
55
static bool mmapped = false;
usr.bin/make/str.c
251
return false;
usr.bin/make/str.c
263
return false;
usr.bin/make/str.c
273
return false;
usr.bin/make/str.c
282
return false;
usr.bin/make/str.c
288
return false;
usr.bin/make/str.c
300
return false;
usr.bin/make/str.c
325
return false;
usr.bin/make/str.c
332
return false;
usr.bin/make/str.c
342
return false;
usr.bin/make/str.c
347
return false;
usr.bin/make/str.c
355
return false;
usr.bin/make/suff.c
1532
first = false;
usr.bin/make/suff.c
1563
reprint = false;
usr.bin/make/suff.c
361
return false;
usr.bin/make/suff.c
366
return false;
usr.bin/make/suff.c
415
return false;
usr.bin/make/suff.c
751
return false;
usr.bin/make/suff.c
944
return false;
usr.bin/make/targ.c
155
gn->must_make = false;
usr.bin/make/targ.c
157
gn->in_cycle = false;
usr.bin/make/targ.c
158
gn->child_rebuilt = false;
usr.bin/make/targ.c
253
return false;
usr.bin/make/targ.c
262
return false;
usr.bin/make/targ.c
271
return false;
usr.bin/make/targequiv.c
295
free_a = false;
usr.bin/make/targequiv.c
302
free_b = false;
usr.bin/make/targequiv.c
327
free_a = false;
usr.bin/make/targequiv.c
334
free_b = false;
usr.bin/make/targequiv.c
432
static bool equiv_was_built = false;
usr.bin/make/targequiv.c
457
return false;
usr.bin/make/var.c
1046
errorReported = false;
usr.bin/make/var.c
1114
bool seen_target = false;
usr.bin/make/var.c
1140
bool doFree = false;
usr.bin/make/var.c
1141
char *val = VarModifiers_Apply(NULL, NULL, NULL, false,
usr.bin/make/var.c
1279
doFree = false;
usr.bin/make/var.c
1287
&name, NULL, false, &doFree, &p, paren);
usr.bin/make/var.c
1347
Var_setCheckEnvFirst(false);
usr.bin/make/var.c
1389
first = false; \
usr.bin/make/var.c
158
false, /* GLOBAL_INDEX */
usr.bin/make/var.c
160
false, /* $* */
usr.bin/make/var.c
161
false, /* $! */
usr.bin/make/var.c
164
false, /* $? */
usr.bin/make/var.c
165
false, /* $> */
usr.bin/make/var.c
634
var_set_append(name, ename, val, ctxt, false);
usr.bin/make/var.c
677
first = false;
usr.bin/make/var.c
679
varname_list_changed = false;
usr.bin/make/var.c
731
return false;
usr.bin/make/var.c
783
bool has_modifier = false;
usr.bin/make/var.c
789
tstr = VarName_Get(str+2, name, ctxt, false, find_pos(str[1]));
usr.bin/make/var.c
800
name->tofree = false;
usr.bin/make/var.c
819
return false;
usr.bin/make/var.c
825
bool freePtr = false;
usr.bin/make/var.c
829
result = false;
usr.bin/make/var.c
849
return false;
usr.bin/make/var.c
989
*freePtr = false;
usr.bin/make/var.c
995
*freePtr = false;
usr.bin/make/varmodifiers.c
1139
*freePtr = false;
usr.bin/make/varmodifiers.c
1151
*freePtr = false;
usr.bin/make/varmodifiers.c
530
done = false;
usr.bin/make/varmodifiers.c
537
addSpace = false;
usr.bin/make/varmodifiers.c
734
addSpace = false;
usr.bin/make/varmodifiers.c
965
return common_get_patternarg(p, ctxt, err, endc, false);
usr.bin/make/varname.c
44
name->tofree = false;
usr.bin/patch/inp.c
120
return false;
usr.bin/patch/inp.c
141
return false;
usr.bin/patch/inp.c
145
return false;
usr.bin/patch/inp.c
175
out_of_mem = false;
usr.bin/patch/inp.c
176
return false; /* force plan b because plan a bombed */
usr.bin/patch/inp.c
180
return false;
usr.bin/patch/inp.c
191
return false;
usr.bin/patch/inp.c
207
return false;
usr.bin/patch/inp.c
217
return false;
usr.bin/patch/inp.c
234
return false;
usr.bin/patch/inp.c
243
last_line_missing_eol = false;
usr.bin/patch/inp.c
284
using_plan_a = false;
usr.bin/patch/inp.c
379
warn_on_invalid_line = false;
usr.bin/patch/inp.c
429
return false;
usr.bin/patch/patch.c
107
static bool remove_empty_files = false;
usr.bin/patch/patch.c
1089
return false;
usr.bin/patch/patch.c
1094
return false;
usr.bin/patch/patch.c
1096
return false;
usr.bin/patch/patch.c
110
static bool reverse_flag_specified = false;
usr.bin/patch/patch.c
1106
return false;
usr.bin/patch/patch.c
1109
return false;
usr.bin/patch/patch.c
112
static bool Vflag = false;
usr.bin/patch/patch.c
1125
return false; /* no corresponding whitespace */
usr.bin/patch/patch.c
1133
return false;
usr.bin/patch/patch.c
133
static bool do_defines = false;
usr.bin/patch/patch.c
270
patch_seen = false;
usr.bin/patch/patch.c
311
out_of_mem = false;
usr.bin/patch/patch.c
508
skip_rest_of_patch = false;
usr.bin/patch/patch.c
55
bool out_of_mem = false; /* ran out of memory in plan a */
usr.bin/patch/patch.c
60
bool ok_to_create_file = false;
usr.bin/patch/patch.c
646
verbose = false;
usr.bin/patch/patch.c
67
bool toutkeep = false;
usr.bin/patch/patch.c
68
bool trejkeep = false;
usr.bin/patch/patch.c
76
bool force = false;
usr.bin/patch/patch.c
77
bool batch = false;
usr.bin/patch/patch.c
79
bool reverse = false;
usr.bin/patch/patch.c
80
bool noreverse = false;
usr.bin/patch/patch.c
81
bool skip_rest_of_patch = false;
usr.bin/patch/patch.c
83
bool canonicalize = false;
usr.bin/patch/patch.c
84
bool check_only = false;
usr.bin/patch/patch.c
909
copy_till(where + old - 1, false);
usr.bin/patch/patch.c
925
copy_till(where + old - 1, false);
usr.bin/patch/patch.c
947
copy_till(where + old - 1, false);
usr.bin/patch/patch.c
979
copy_till(where + old - 1, false);
usr.bin/patch/pch.c
1033
return false;
usr.bin/patch/pch.c
1072
return false;
usr.bin/patch/pch.c
1087
return false;
usr.bin/patch/pch.c
1111
return false;
usr.bin/patch/pch.c
1126
return false;
usr.bin/patch/pch.c
1199
bool blankline = false;
usr.bin/patch/pch.c
1223
return false; /* not enough memory to swap hunk! */
usr.bin/patch/pch.c
183
bool exists = false;
usr.bin/patch/pch.c
188
return false;
usr.bin/patch/pch.c
199
return false;
usr.bin/patch/pch.c
251
bool last_line_was_command = false, this_is_a_command = false;
usr.bin/patch/pch.c
252
bool stars_last_line = false, stars_this_line = false;
usr.bin/patch/pch.c
259
ok_to_create_file = false;
usr.bin/patch/pch.c
484
return false;
usr.bin/patch/pch.c
523
ptrn_spaces_eaten = false;
usr.bin/patch/pch.c
525
repl_missing = false;
usr.bin/patch/pch.c
534
return false;
usr.bin/patch/pch.c
583
return false;
usr.bin/patch/pch.c
655
return false;
usr.bin/patch/pch.c
690
repl_could_be_missing = false;
usr.bin/patch/pch.c
696
repl_could_be_missing = false;
usr.bin/patch/pch.c
714
return false;
usr.bin/patch/pch.c
736
return false;
usr.bin/patch/pch.c
758
return false;
usr.bin/patch/pch.c
869
return false;
usr.bin/patch/pch.c
909
return false;
usr.bin/patch/pch.c
917
return false;
usr.bin/patch/pch.c
946
return false;
usr.bin/patch/pch.c
985
return false;
usr.bin/pkgconf/cli/main.c
1051
bool opened_error_msgout = false;
usr.bin/pkgconf/cli/main.c
107
return false;
usr.bin/pkgconf/cli/main.c
111
return false;
usr.bin/pkgconf/cli/main.c
120
return false;
usr.bin/pkgconf/cli/main.c
124
return false;
usr.bin/pkgconf/cli/main.c
135
return false;
usr.bin/pkgconf/cli/main.c
138
return false;
usr.bin/pkgconf/cli/main.c
156
return false;
usr.bin/pkgconf/cli/main.c
159
return false;
usr.bin/pkgconf/cli/main.c
326
return false;
usr.bin/pkgconf/cli/main.c
468
return false;
usr.bin/pkgconf/cli/main.c
525
pkgconf_fragment_insert(client, fragment_list, 'D', havebuf, false);
usr.bin/pkgconf/cli/main.c
586
return false;
usr.bin/pkgconf/cli/main.c
590
return false;
usr.bin/pkgconf/cli/main.c
594
return false;
usr.bin/pkgconf/cli/main.c
613
return false;
usr.bin/pkgconf/cli/main.c
643
return false;
usr.bin/pkgconf/cli/main.c
716
return false;
usr.bin/pkgconf/cli/main.c
761
return false;
usr.bin/pkgconf/cli/main.c
798
return false;
usr.bin/pkgconf/cli/main.c
802
return false;
usr.bin/pkgconf/cli/main.c
831
return false;
usr.bin/pkgconf/libpkgconf/argvsplit.c
68
bool escaped = false;
usr.bin/pkgconf/libpkgconf/argvsplit.c
95
escaped = false;
usr.bin/pkgconf/libpkgconf/client.c
119
pkgconf_path_build_from_environ("PKG_CONFIG_SYSTEM_LIBRARY_PATH", NULL, &client->filter_libdirs, false);
usr.bin/pkgconf/libpkgconf/client.c
124
pkgconf_path_build_from_environ("PKG_CONFIG_SYSTEM_INCLUDE_PATH", NULL, &client->filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/client.c
128
pkgconf_path_build_from_environ("BELIBRARIES", NULL, &client->filter_libdirs, false);
usr.bin/pkgconf/libpkgconf/client.c
130
pkgconf_path_build_from_environ("LIBRARY_PATH", NULL, &client->filter_libdirs, false);
usr.bin/pkgconf/libpkgconf/client.c
132
pkgconf_path_build_from_environ("CPATH", NULL, &client->filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/client.c
133
pkgconf_path_build_from_environ("C_INCLUDE_PATH", NULL, &client->filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/client.c
134
pkgconf_path_build_from_environ("CPLUS_INCLUDE_PATH", NULL, &client->filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/client.c
135
pkgconf_path_build_from_environ("OBJC_INCLUDE_PATH", NULL, &client->filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/client.c
139
pkgconf_path_build_from_environ("INCLUDE", NULL, &client->filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/client.c
379
return false;
usr.bin/pkgconf/libpkgconf/fileio.c
22
bool quoted = false;
usr.bin/pkgconf/libpkgconf/fileio.c
45
quoted = false;
usr.bin/pkgconf/libpkgconf/fileio.c
59
quoted = false;
usr.bin/pkgconf/libpkgconf/fileio.c
77
quoted = false;
usr.bin/pkgconf/libpkgconf/fileio.c
88
quoted = false;
usr.bin/pkgconf/libpkgconf/fileio.c
98
quoted = false;
usr.bin/pkgconf/libpkgconf/fragment.c
113
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
279
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
285
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
287
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
289
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
300
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
303
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
372
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
67
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
69
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
76
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
765
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
777
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
81
return false;
usr.bin/pkgconf/libpkgconf/fragment.c
99
return false;
usr.bin/pkgconf/libpkgconf/parser.c
43
bool warned_key_whitespace = false, warned_value_whitespace = false;
usr.bin/pkgconf/libpkgconf/path.c
246
return false;
usr.bin/pkgconf/libpkgconf/path.c
357
return false;
usr.bin/pkgconf/libpkgconf/path.c
47
return false;
usr.bin/pkgconf/libpkgconf/personality.c
121
pkgconf_path_split(SYSTEM_LIBDIR, &default_personality.filter_libdirs, false);
usr.bin/pkgconf/libpkgconf/personality.c
122
pkgconf_path_split(SYSTEM_INCLUDEDIR, &default_personality.filter_includedirs, false);
usr.bin/pkgconf/libpkgconf/personality.c
157
return false;
usr.bin/pkgconf/libpkgconf/personality.c
196
pkgconf_path_split(value, dest, false);
usr.bin/pkgconf/libpkgconf/personality.c
296
out = load_personality_with_path(triplet, NULL, false);
usr.bin/pkgconf/libpkgconf/personality.c
335
out = load_personality_with_path(pn->path, triplet, false);
usr.bin/pkgconf/libpkgconf/pkg.c
1204
return false;
usr.bin/pkgconf/libpkgconf/pkg.c
1381
return false;
usr.bin/pkgconf/libpkgconf/pkg.c
1385
return false;
usr.bin/pkgconf/libpkgconf/pkg.c
1408
return false;
usr.bin/pkgconf/libpkgconf/pkg.c
1776
pkgconf_fragment_copy(client, list, frag, false);
usr.bin/pkgconf/libpkgconf/pkg.c
406
pkgconf_tuple_add(pkg->owner, &pkg->vars, keyword, newvalue, false, pkg->flags);
usr.bin/pkgconf/libpkgconf/pkg.c
419
pkg->prefix = pkgconf_tuple_add(pkg->owner, &pkg->vars, keyword, prefix_value, false, pkg->flags);
usr.bin/pkgconf/libpkgconf/pkg.c
472
valid = false;
usr.bin/pkgconf/libpkgconf/pkg.c
513
pkgconf_tuple_add(client, &pkg->vars, "pc_sysrootdir", "", false, pkg->flags);
usr.bin/pkgconf/libpkgconf/pkg.c
64
return false;
usr.bin/pkgconf/libpkgconf/pkg.c
985
isnum = false;
usr.bin/pkgconf/libpkgconf/queue.c
350
bool ret = false;
usr.bin/pkgconf/libpkgconf/queue.c
403
retval = false;
usr.bin/pkgconf/libpkgconf/tuple.c
131
tuple = pkgconf_tuple_add(client, &client->global_vars, workbuf, value, false, 0);
usr.bin/pkgconf/libpkgconf/tuple.c
199
return false;
usr.bin/pkgconf/libpkgconf/tuple.c
203
return false;
usr.bin/pkgconf/libpkgconf/tuple.c
206
return false;
usr.bin/pkgconf/libpkgconf/tuple.c
209
return false;
usr.bin/pkgconf/libpkgconf/tuple.c
212
return false;
usr.bin/pkgconf/libpkgconf/tuple.c
215
return false;
usr.bin/pkgconf/libpkgconf/tuple.c
48
pkgconf_tuple_add(client, &client->global_vars, key, value, false, 0);
usr.bin/sort/bwstring.c
824
*empty = false;
usr.bin/sort/coll.c
1083
key1_read = key2_read = false;
usr.bin/sort/coll.c
1237
key1_read = key2_read = false;
usr.bin/sort/coll.c
302
empty_field = false;
usr.bin/sort/coll.c
303
empty_key = false;
usr.bin/sort/coll.c
349
empty_field = false;
usr.bin/sort/coll.c
350
empty_key = false;
usr.bin/sort/coll.c
792
key1_read = key2_read = false;
usr.bin/sort/coll.c
812
kv1->hint->v.nh.neg = (sign1 < 0) ? true : false;
usr.bin/sort/coll.c
825
kv2->hint->v.nh.neg = (sign2 < 0) ? true : false;
usr.bin/sort/coll.c
932
return numcoll_impl(kv1, kv2, offset, false);
usr.bin/sort/file.c
1033
file_list_add(&new_fl, fnew, false);
usr.bin/sort/file.c
1036
fl->tmp = false; /* already taken care of */
usr.bin/sort/file.c
156
return false;
usr.bin/sort/file.c
238
fl->tmp = false;
usr.bin/sort/file.c
737
file_list_add(fl, fn, false);
usr.bin/sort/sort.c
1116
file_list_add(&fl, flast, false);
usr.bin/sort/sort.c
1133
file_list_init(&fl, false);
usr.bin/sort/sort.c
378
found_others = found_this = false;
usr.bin/sort/sort.c
466
return false;
usr.bin/sort/sort.c
591
{ false, false, false, false, false, false };
usr.bin/sort/sort.c
610
ret = parse_pos(pos1, ks, mef_flags, false);
usr.bin/sort/sort.c
620
ret = parse_pos(s, ks, mef_flags, false);
usr.bin/sort/sort.c
800
{ false, false, false, false, false, false };
usr.bin/sort/vsort.c
69
sfx = false;
usr.bin/sort/vsort.c
70
expect_alpha = false;
usr.bin/sort/vsort.c
76
expect_alpha = false;
usr.bin/sort/vsort.c
78
sfx = false;
usr.bin/sort/vsort.c
86
sfx = false;
usr.bin/ssh/libcrux_mlkem768_sha3.h
11693
libcrux_ml_kem_matrix_sample_matrix_A_2b(uu____2, ret, false);
usr.bin/ssh/libcrux_mlkem768_sha3.h
5004
lit.sponge = false;
usr.bin/ssh/libcrux_mlkem768_sha3.h
5305
lit.sponge = false;
usr.bin/ssh/libcrux_mlkem768_sha3.h
8363
done = false;
usr.bin/ssh/libcrux_mlkem768_sha3.h
8485
done = false;
usr.bin/ssh/libcrux_mlkem768_sha3.h
8663
libcrux_ml_kem_matrix_sample_matrix_A_2b(uu____1, ret, false);
usr.bin/timeout/timeout.c
174
bool timedout = false;
usr.bin/timeout/timeout.c
175
bool do_second_kill = false;
usr.bin/top/commands.c
195
first = false;
usr.bin/top/screen.c
103
smart_terminal = false;
usr.bin/top/screen.c
121
smart_terminal = false;
usr.bin/top/screen.c
134
smart_terminal = false;
usr.bin/top/screen.c
163
smart_terminal = false;
usr.bin/top/screen.c
59
static char is_a_terminal = false;
usr.bin/top/screen.c
73
smart_terminal = false;
usr.bin/top/screen.c
85
smart_terminal = false;
usr.bin/top/screen.c
97
smart_terminal = false;
usr.bin/top/top.c
205
old_system = false;
usr.bin/top/top.c
264
if (filterpid(optarg, false) == -1)
usr.bin/top/top.c
289
interactive = false;
usr.bin/top/top.c
296
interactive = false;
usr.bin/top/top.c
397
ps.system = false;
usr.bin/top/top.c
401
ps.rtable = false;
usr.bin/top/top.c
688
no_command = false;
usr.bin/top/top.c
826
display_header(false);
usr.bin/top/top.c
89
int old_system = false;
usr.bin/top/top.c
90
int old_threads = false;
usr.bin/top/top.c
91
int show_args = false;
usr.bin/top/top.c
96
int topn_specified = false;
usr.bin/unexpand/unexpand.c
50
bool all = false;
usr.bin/unifdef/unifdef.c
1006
defparen = false;
usr.bin/unifdef/unifdef.c
1022
constexpr = false;
usr.bin/unifdef/unifdef.c
1039
constexpr = false;
usr.bin/unifdef/unifdef.c
1099
constexpr = killconsts ? false : true;
usr.bin/unifdef/unifdef.c
120
NO_COMMENT = false, /* outside a comment */
usr.bin/unifdef/unifdef.c
1357
firstsym = zerosyms = false;
usr.bin/unifdef/unifdef.c
1485
return (false);
usr.bin/unifdef/unifdef.c
1508
addsym2(false, sym, val);
usr.bin/unifdef/unifdef.c
1515
addsym2(false, sym, NULL);
usr.bin/unifdef/unifdef.c
283
addsym1(true, false, optarg);
usr.bin/unifdef/unifdef.c
288
addsym1(false, true, optarg);
usr.bin/unifdef/unifdef.c
291
addsym1(false, false, optarg);
usr.bin/unifdef/unifdef.c
557
static void drop (void) { flushline(false); }
usr.sbin/btrace/btrace.c
729
if (stmt_test(r->br_filter->bf_condition, dtev) == false) {
usr.sbin/ldomctl/mdesc.c
255
return false;
usr.sbin/ldomctl/mdesc.c
269
return false;
usr.sbin/ldomctl/mdesc.c
283
return false;
usr.sbin/ldomctl/mdesc.c
297
return false;
usr.sbin/ldomctl/mdesc.c
312
return false;
usr.sbin/npppctl/npppctl.c
389
return (false);
usr.sbin/npppctl/npppctl.c
395
return (false);
usr.sbin/npppctl/npppctl.c
399
return (false);
usr.sbin/npppctl/npppctl.c
404
return (false);
usr.sbin/npppctl/npppctl.c
408
return (false);
usr.sbin/npppctl/npppctl.c
411
return (false);
usr.sbin/npppctl/npppctl.c
415
return (false);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1061
return ((off < winsz)? true : false);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1071
return ((off < _this->winsz)? true : false);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
864
l2tp_ctrl_resend_una_packets(ctrl, false);
usr.sbin/npppd/npppd/npppd_ctl.c
257
_this->responding = false;
usr.sbin/npppd/npppd/npppd_ctl.c
93
return (npppd_ctl_who0(_this, false));
usr.sbin/npppd/npppd/parse.y
1030
| NO { $$ = false; }
usr.sbin/npppd/npppd/parse.y
1645
auth->strip_atmark_realm = false;
usr.sbin/npppd/npppd/parse.y
897
curr_ipcpconf->dns_use_resolver = false;
usr.sbin/npppd/npppd/parse.y
903
curr_ipcpconf->dns_use_resolver = false;
usr.sbin/npppd/npppd/ppp.c
1120
.tcp_mss_adjust = false,
usr.sbin/npppd/npppd/ppp.c
1122
.ingress_filter = false,
usr.sbin/npppd/npppd/ppp.c
1123
.lcp_keepalive = false,
usr.sbin/npppd/npppd/ppp.c
1129
.mppe_required = false,
usr.sbin/npppd/npppd/ppp.c
1142
.require_ipsec = false,
usr.sbin/npppd/npppd/ppp.c
1145
.force_lcp_renegotiation = false,
usr.sbin/npppd/npppd/ppp.c
1155
.tcp_mss_adjust = false,
usr.sbin/npppd/npppd/ppp.c
1157
.ingress_filter = false,
usr.sbin/npppd/npppd/ppp.c
1181
.tcp_mss_adjust = false,
usr.sbin/npppd/npppd/ppp.c
1183
.ingress_filter = false,
usr.sbin/npppd/npppd/ppp.c
1190
.mppe_required = false,
usr.sbin/nsd/ixfr.c
2610
options.pretty_ttls = false;
usr.sbin/nsd/simdzone/src/generic/eui.h
22
return false;
usr.sbin/nsd/simdzone/src/generic/eui.h
41
eui_base16_dec_loop_generic_32_inner(input, rdata->octets, false) &&
usr.sbin/nsd/simdzone/src/generic/eui.h
42
eui_base16_dec_loop_generic_32_inner(input+6, rdata->octets+2, false) &&
usr.sbin/nsd/simdzone/src/generic/eui.h
59
eui_base16_dec_loop_generic_32_inner(input, rdata->octets, false) &&
usr.sbin/nsd/simdzone/src/generic/eui.h
60
eui_base16_dec_loop_generic_32_inner(input+6, rdata->octets+2, false) &&
usr.sbin/nsd/simdzone/src/generic/eui.h
61
eui_base16_dec_loop_generic_32_inner(input+12, rdata->octets+4, false) &&
usr.sbin/nsd/simdzone/src/generic/format.h
19
{ { { name, sizeof(name) - 1 }, 0 }, 0, false, false, fields, 0, 0 }
usr.sbin/nsd/simdzone/src/generic/parser.h
376
parser->file->start_of_line = false;
usr.sbin/nsd/simdzone/src/generic/parser.h
489
parser->file->grouped = false;
usr.sbin/nsd/simdzone/src/generic/parser.h
619
parser->file->grouped = false;
usr.sbin/nsd/simdzone/src/generic/parser.h
720
parser->file->grouped = false;
usr.sbin/nsd/simdzone/src/generic/parser.h
825
parser->file->grouped = false;
usr.sbin/nsd/simdzone/src/generic/parser.h
952
parser->file->grouped = false;
usr.sbin/nsd/simdzone/src/generic/svcb.h
679
bool out_of_order = false;
usr.sbin/nsd/simdzone/src/generic/svcb.h
770
bool missing_keys = false;
usr.sbin/nsd/simdzone/src/generic/svcb.h
864
bool out_of_order = false;
usr.sbin/nsd/simdzone/src/generic/types.h
64
{ { { name, sizeof(name) - 1 }, code }, _class, false, false, fields, check, parse }
usr.sbin/nsd/simdzone/src/generic/types.h
67
{ { { "", 0 }, code }, 0, false, false, { 0, NULL }, check_generic_rr, parse_unknown_rdata }
usr.sbin/nsd/simdzone/src/haswell/base32.h
53
valid = false;
usr.sbin/nsd/simdzone/src/isadetection.h
222
bool have_avx = false, have_xgetbv = false;
usr.sbin/nsd/simdzone/src/westmere/base32.h
48
valid = false;
usr.sbin/nsd/simdzone/src/westmere/time.h
102
if(yr < 1970 || mo > 11) { return false; } // unlikely branch
usr.sbin/nsd/simdzone/src/westmere/time.h
106
return false;
usr.sbin/nsd/simdzone/src/westmere/time.h
109
return false;
usr.sbin/nsd/simdzone/src/westmere/time.h
80
return false;
usr.sbin/radiusctl/radiusctl.c
395
radius_dump(stdout, reqpkt, false, res->secret);
usr.sbin/radiusd/parse.y
566
| NO { $$ = false; }
usr.sbin/radiusd/radiusd.c
125
bool noaction = false;
usr.sbin/radiusd/radiusd.c
1333
module->writeready = false;
usr.sbin/radiusd/radiusd.c
1744
userpass.has_pass = false;
usr.sbin/radiusd/radiusd.c
1892
arg.final = false;
usr.sbin/radiusd/radiusd.c
713
q->hasnext = false;
usr.sbin/radiusd/radiusd.c
887
q->prev->hasnext = false;
usr.sbin/radiusd/radiusd_bsdauth.c
135
bool authok = false;
usr.sbin/radiusd/radiusd_bsdauth.c
176
bool group_ok = false;
usr.sbin/radiusd/radiusd_eap2mschap.c
469
bool reset_username = false;
usr.sbin/radiusd/radiusd_eap2mschap.c
621
bool accept = false;
usr.sbin/radiusd/radiusd_ipcp.c
498
module->no_session_timeout = false;
usr.sbin/radiusd/radiusd_ipcp.c
501
module->no_session_timeout = false;
usr.sbin/radiusd/radiusd_ipcp.c
745
bool found = false;
usr.sbin/radiusd/radiusd_module.c
331
ans.final = false;
usr.sbin/radiusd/radiusd_module.c
644
base->writeready = false;
usr.sbin/radiusd/radiusd_module.c
651
base->ev_onhandler = false;
usr.sbin/radiusd/radiusd_standard.c
142
module->strip_atmark_realm = false;
usr.sbin/radiusd/radiusd_standard.c
152
module->strip_nt_domain = false;
