games/hunt/huntd/conf.h

54

void config(void);

games/hunt/huntd/driver.c

93

config();

lib/libtls/tls.c

155

tls_config_set_error(struct tls_config *config, int code, const char *fmt, ...)

lib/libtls/tls.c

163

rv = tls_error_vset(&config->error, code, errno_value, fmt, ap);

lib/libtls/tls.c

170

tls_config_set_errorx(struct tls_config *config, int code, const char *fmt, ...)

lib/libtls/tls.c

176

rv = tls_error_vset(&config->error, code, -1, fmt, ap);

lib/libtls/tls.c

264

tls_configure(struct tls *ctx, struct tls_config *config)

lib/libtls/tls.c

266

if (config == NULL)

lib/libtls/tls.c

267

config = tls_config_default;

lib/libtls/tls.c

269

pthread_mutex_lock(&config->mutex);

lib/libtls/tls.c

270

config->refcount++;

lib/libtls/tls.c

271

pthread_mutex_unlock(&config->mutex);

lib/libtls/tls.c

273

tls_config_free(ctx->config);

lib/libtls/tls.c

275

ctx->config = config;

lib/libtls/tls.c

276

ctx->keypair = config->keypair;

lib/libtls/tls.c

350

if (ctx->config->use_fake_private_key) {

lib/libtls/tls.c

363

ctx->config->use_fake_private_key ?

lib/libtls/tls.c

373

if (ctx->config->use_fake_private_key) {

lib/libtls/tls.c

411

if (!ctx->config->skip_private_key_check)

lib/libtls/tls.c

427

if (ctx->config->sign_cb != NULL) {

lib/libtls/tls.c

430

RSA_set_ex_data(rsa, 1, ctx->config) == 0 ||

lib/libtls/tls.c

451

if (ctx->config->sign_cb != NULL) {

lib/libtls/tls.c

454

EC_KEY_set_ex_data(eckey, 1, ctx->config) == 0 ||

lib/libtls/tls.c

521

if (!ctx->config->skip_private_key_check &&

lib/libtls/tls.c

552

if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_2) == 0)

lib/libtls/tls.c

554

if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_3) == 0)

lib/libtls/tls.c

557

if (ctx->config->alpn != NULL) {

lib/libtls/tls.c

558

if (SSL_CTX_set_alpn_protos(ssl_ctx, ctx->config->alpn,

lib/libtls/tls.c

559

ctx->config->alpn_len) != 0) {

lib/libtls/tls.c

566

if (ctx->config->ciphers != NULL) {

lib/libtls/tls.c

568

ctx->config->ciphers) != 1) {

lib/libtls/tls.c

575

if (ctx->config->verify_time == 0) {

lib/libtls/tls.c

596

if (ctx->config->verify_cert == 0)

lib/libtls/tls.c

619

size_t ca_len = ctx->config->ca_len;

lib/libtls/tls.c

620

char *ca_mem = ctx->config->ca_mem;

lib/libtls/tls.c

621

char *crl_mem = ctx->config->crl_mem;

lib/libtls/tls.c

622

size_t crl_len = ctx->config->crl_len;

lib/libtls/tls.c

634

if (ctx->config->verify_depth >= 0)

lib/libtls/tls.c

635

SSL_CTX_set_verify_depth(ssl_ctx, ctx->config->verify_depth);

lib/libtls/tls.c

637

if (ctx->config->verify_cert == 0)

lib/libtls/tls.c

641

if (ctx->config->ca_mem == NULL && ctx->config->ca_path == NULL) {

lib/libtls/tls.c

660

ctx->config->ca_path) != 1) {

lib/libtls/tls.c

725

tls_config_free(ctx->config);

lib/libtls/tls.c

726

ctx->config = NULL;

lib/libtls/tls_client.c

171

int sfd = ctx->config->session_fd;

lib/libtls/tls_client.c

234

int sfd = ctx->config->session_fd;

lib/libtls/tls_client.c

329

ctx->config->keypair, 0) != 0)

lib/libtls/tls_client.c

332

if (ctx->config->verify_name) {

lib/libtls/tls_client.c

343

if (ctx->config->ecdhecurves != NULL) {

lib/libtls/tls_client.c

344

if (SSL_CTX_set1_groups(ctx->ssl_ctx, ctx->config->ecdhecurves,

lib/libtls/tls_client.c

345

ctx->config->ecdhecurves_len) != 1) {

lib/libtls/tls_client.c

369

if (ctx->config->session_fd != -1) {

lib/libtls/tls_client.c

479

if (ctx->config->verify_name) {

lib/libtls/tls_client.c

498

if (ctx->config->session_fd != -1) {

lib/libtls/tls_config.c

102

if (pthread_mutex_init(&config->mutex, NULL) != 0)

lib/libtls/tls_config.c

105

config->refcount = 1;

lib/libtls/tls_config.c

106

config->session_fd = -1;

lib/libtls/tls_config.c

108

if ((config->keypair = tls_keypair_new()) == NULL)

lib/libtls/tls_config.c

114

if (tls_config_set_dheparams(config, "none") != 0)

lib/libtls/tls_config.c

116

if (tls_config_set_ecdhecurves(config, "default") != 0)

lib/libtls/tls_config.c

118

if (tls_config_set_ciphers(config, "secure") != 0)

lib/libtls/tls_config.c

121

if (tls_config_set_protocols(config, TLS_PROTOCOLS_DEFAULT) != 0)

lib/libtls/tls_config.c

123

if (tls_config_set_verify_depth(config, 6) != 0)

lib/libtls/tls_config.c

132

if (tls_config_set_session_id(config, sid, sizeof(sid)) != 0)

lib/libtls/tls_config.c

134

config->ticket_keyrev = arc4random();

lib/libtls/tls_config.c

135

config->ticket_autorekey = 1;

lib/libtls/tls_config.c

137

tls_config_prefer_ciphers_server(config);

lib/libtls/tls_config.c

139

tls_config_verify(config);

lib/libtls/tls_config.c

141

return (config);

lib/libtls/tls_config.c

144

tls_config_free(config);

lib/libtls/tls_config.c

158

tls_config_free(struct tls_config *config)

lib/libtls/tls_config.c

163

if (config == NULL)

lib/libtls/tls_config.c

166

pthread_mutex_lock(&config->mutex);

lib/libtls/tls_config.c

167

refcount = --config->refcount;

lib/libtls/tls_config.c

168

pthread_mutex_unlock(&config->mutex);

lib/libtls/tls_config.c

173

for (kp = config->keypair; kp != NULL; kp = nkp) {

lib/libtls/tls_config.c

178

free(config->error.msg);

lib/libtls/tls_config.c

180

free(config->alpn);

lib/libtls/tls_config.c

181

free((char *)config->ca_mem);

lib/libtls/tls_config.c

182

free((char *)config->ca_path);

lib/libtls/tls_config.c

183

free((char *)config->ciphers);

lib/libtls/tls_config.c

184

free((char *)config->crl_mem);

lib/libtls/tls_config.c

185

free(config->ecdhecurves);

lib/libtls/tls_config.c

187

pthread_mutex_destroy(&config->mutex);

lib/libtls/tls_config.c

189

free(config);

lib/libtls/tls_config.c

193

tls_config_keypair_add(struct tls_config *config, struct tls_keypair *keypair)

lib/libtls/tls_config.c

197

kp = config->keypair;

lib/libtls/tls_config.c

205

tls_config_error(struct tls_config *config)

lib/libtls/tls_config.c

207

return config->error.msg;

lib/libtls/tls_config.c

211

tls_config_error_code(struct tls_config *config)

lib/libtls/tls_config.c

213

return config->error.code;

lib/libtls/tls_config.c

217

tls_config_clear_keys(struct tls_config *config)

lib/libtls/tls_config.c

221

for (kp = config->keypair; kp != NULL; kp = kp->next)

lib/libtls/tls_config.c

291

tls_config_parse_alpn(struct tls_config *config, const char *alpn,

lib/libtls/tls_config.c

304

tls_config_set_errorx(config, TLS_ERROR_INVALID_ARGUMENT,

lib/libtls/tls_config.c

310

tls_config_set_errorx(config, TLS_ERROR_OUT_OF_MEMORY,

lib/libtls/tls_config.c

316

tls_config_set_errorx(config, TLS_ERROR_OUT_OF_MEMORY,

lib/libtls/tls_config.c

325

tls_config_set_errorx(config, TLS_ERROR_INVALID_ARGUMENT,

lib/libtls/tls_config.c

330

tls_config_set_errorx(config, TLS_ERROR_INVALID_ARGUMENT,

lib/libtls/tls_config.c

354

tls_config_set_alpn(struct tls_config *config, const char *alpn)

lib/libtls/tls_config.c

356

return tls_config_parse_alpn(config, alpn, &config->alpn,

lib/libtls/tls_config.c

357

&config->alpn_len);

lib/libtls/tls_config.c

361

tls_config_add_keypair_file_internal(struct tls_config *config,

lib/libtls/tls_config.c

368

if (tls_keypair_set_cert_file(keypair, &config->error, cert_file) != 0)

lib/libtls/tls_config.c

371

tls_keypair_set_key_file(keypair, &config->error, key_file) != 0)

lib/libtls/tls_config.c

374

tls_keypair_set_ocsp_staple_file(keypair, &config->error,

lib/libtls/tls_config.c

378

tls_config_keypair_add(config, keypair);

lib/libtls/tls_config.c

388

tls_config_add_keypair_mem_internal(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

396

if (tls_keypair_set_cert_mem(keypair, &config->error, cert, cert_len) != 0)

lib/libtls/tls_config.c

399

tls_keypair_set_key_mem(keypair, &config->error, key, key_len) != 0)

lib/libtls/tls_config.c

402

tls_keypair_set_ocsp_staple_mem(keypair, &config->error, staple,

lib/libtls/tls_config.c

406

tls_config_keypair_add(config, keypair);

lib/libtls/tls_config.c

416

tls_config_add_keypair_mem(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

419

return tls_config_add_keypair_mem_internal(config, cert, cert_len, key,

lib/libtls/tls_config.c

424

tls_config_add_keypair_file(struct tls_config *config,

lib/libtls/tls_config.c

427

return tls_config_add_keypair_file_internal(config, cert_file,

lib/libtls/tls_config.c

432

tls_config_add_keypair_ocsp_mem(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

436

return tls_config_add_keypair_mem_internal(config, cert, cert_len, key,

lib/libtls/tls_config.c

441

tls_config_add_keypair_ocsp_file(struct tls_config *config,

lib/libtls/tls_config.c

444

return tls_config_add_keypair_file_internal(config, cert_file,

lib/libtls/tls_config.c

449

tls_config_set_ca_file(struct tls_config *config, const char *ca_file)

lib/libtls/tls_config.c

451

return tls_config_load_file(&config->error, "CA", ca_file,

lib/libtls/tls_config.c

452

&config->ca_mem, &config->ca_len);

lib/libtls/tls_config.c

456

tls_config_set_ca_path(struct tls_config *config, const char *ca_path)

lib/libtls/tls_config.c

458

return tls_set_string(&config->ca_path, ca_path);

lib/libtls/tls_config.c

462

tls_config_set_ca_mem(struct tls_config *config, const uint8_t *ca, size_t len)

lib/libtls/tls_config.c

464

return tls_set_mem(&config->ca_mem, &config->ca_len, ca, len);

lib/libtls/tls_config.c

468

tls_config_set_cert_file(struct tls_config *config, const char *cert_file)

lib/libtls/tls_config.c

470

return tls_keypair_set_cert_file(config->keypair, &config->error,

lib/libtls/tls_config.c

475

tls_config_set_cert_mem(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

478

return tls_keypair_set_cert_mem(config->keypair, &config->error,

lib/libtls/tls_config.c

483

tls_config_set_ciphers(struct tls_config *config, const char *ciphers)

lib/libtls/tls_config.c

500

tls_config_set_errorx(config, TLS_ERROR_OUT_OF_MEMORY,

lib/libtls/tls_config.c

505

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

511

return tls_set_string(&config->ciphers, ciphers);

lib/libtls/tls_config.c

519

tls_config_set_crl_file(struct tls_config *config, const char *crl_file)

lib/libtls/tls_config.c

521

return tls_config_load_file(&config->error, "CRL", crl_file,

lib/libtls/tls_config.c

522

&config->crl_mem, &config->crl_len);

lib/libtls/tls_config.c

526

tls_config_set_crl_mem(struct tls_config *config, const uint8_t *crl,

lib/libtls/tls_config.c

529

return tls_set_mem(&config->crl_mem, &config->crl_len, crl, len);

lib/libtls/tls_config.c

533

tls_config_set_dheparams(struct tls_config *config, const char *params)

lib/libtls/tls_config.c

544

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

549

config->dheparams = keylen;

lib/libtls/tls_config.c

555

tls_config_set_ecdhecurve(struct tls_config *config, const char *curve)

lib/libtls/tls_config.c

562

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

567

return tls_config_set_ecdhecurves(config, curve);

lib/libtls/tls_config.c

571

tls_config_set_ecdhecurves(struct tls_config *config, const char *curves)

lib/libtls/tls_config.c

580

free(config->ecdhecurves);

lib/libtls/tls_config.c

581

config->ecdhecurves = NULL;

lib/libtls/tls_config.c

582

config->ecdhecurves_len = 0;

lib/libtls/tls_config.c

588

tls_config_set_errorx(config, TLS_ERROR_OUT_OF_MEMORY,

lib/libtls/tls_config.c

604

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

611

tls_config_set_errorx(config, TLS_ERROR_OUT_OF_MEMORY,

lib/libtls/tls_config.c

620

config->ecdhecurves = curves_list;

lib/libtls/tls_config.c

621

config->ecdhecurves_len = curves_num;

lib/libtls/tls_config.c

634

tls_config_set_key_file(struct tls_config *config, const char *key_file)

lib/libtls/tls_config.c

636

return tls_keypair_set_key_file(config->keypair, &config->error,

lib/libtls/tls_config.c

641

tls_config_set_key_mem(struct tls_config *config, const uint8_t *key,

lib/libtls/tls_config.c

644

return tls_keypair_set_key_mem(config->keypair, &config->error,

lib/libtls/tls_config.c

649

tls_config_set_keypair_file_internal(struct tls_config *config,

lib/libtls/tls_config.c

652

if (tls_config_set_cert_file(config, cert_file) != 0)

lib/libtls/tls_config.c

654

if (tls_config_set_key_file(config, key_file) != 0)

lib/libtls/tls_config.c

657

tls_config_set_ocsp_staple_file(config, ocsp_file) != 0)

lib/libtls/tls_config.c

664

tls_config_set_keypair_mem_internal(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

668

if (tls_config_set_cert_mem(config, cert, cert_len) != 0)

lib/libtls/tls_config.c

670

if (tls_config_set_key_mem(config, key, key_len) != 0)

lib/libtls/tls_config.c

673

(tls_config_set_ocsp_staple_mem(config, staple, staple_len) != 0))

lib/libtls/tls_config.c

680

tls_config_set_keypair_file(struct tls_config *config,

lib/libtls/tls_config.c

683

return tls_config_set_keypair_file_internal(config, cert_file, key_file,

lib/libtls/tls_config.c

688

tls_config_set_keypair_mem(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

691

return tls_config_set_keypair_mem_internal(config, cert, cert_len,

lib/libtls/tls_config.c

696

tls_config_set_keypair_ocsp_file(struct tls_config *config,

lib/libtls/tls_config.c

699

return tls_config_set_keypair_file_internal(config, cert_file, key_file,

lib/libtls/tls_config.c

704

tls_config_set_keypair_ocsp_mem(struct tls_config *config, const uint8_t *cert,

lib/libtls/tls_config.c

708

return tls_config_set_keypair_mem_internal(config, cert, cert_len,

lib/libtls/tls_config.c

714

tls_config_set_protocols(struct tls_config *config, uint32_t protocols)

lib/libtls/tls_config.c

716

config->protocols = protocols;

lib/libtls/tls_config.c

722

tls_config_set_session_fd(struct tls_config *config, int session_fd)

lib/libtls/tls_config.c

728

config->session_fd = session_fd;

lib/libtls/tls_config.c

733

tls_config_set_error(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

738

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

744

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

751

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

756

config->session_fd = session_fd;

lib/libtls/tls_config.c

762

tls_config_set_sign_cb(struct tls_config *config, tls_sign_cb cb, void *cb_arg)

lib/libtls/tls_config.c

764

config->use_fake_private_key = 1;

lib/libtls/tls_config.c

765

config->skip_private_key_check = 1;

lib/libtls/tls_config.c

766

config->sign_cb = cb;

lib/libtls/tls_config.c

767

config->sign_cb_arg = cb_arg;

lib/libtls/tls_config.c

773

tls_config_set_verify_depth(struct tls_config *config, int verify_depth)

lib/libtls/tls_config.c

775

config->verify_depth = verify_depth;

lib/libtls/tls_config.c

781

tls_config_prefer_ciphers_client(struct tls_config *config)

lib/libtls/tls_config.c

783

config->ciphers_server = 0;

lib/libtls/tls_config.c

787

tls_config_prefer_ciphers_server(struct tls_config *config)

lib/libtls/tls_config.c

789

config->ciphers_server = 1;

lib/libtls/tls_config.c

793

tls_config_insecure_noverifycert(struct tls_config *config)

lib/libtls/tls_config.c

795

config->verify_cert = 0;

lib/libtls/tls_config.c

799

tls_config_insecure_noverifyname(struct tls_config *config)

lib/libtls/tls_config.c

801

config->verify_name = 0;

lib/libtls/tls_config.c

805

tls_config_insecure_noverifytime(struct tls_config *config)

lib/libtls/tls_config.c

807

config->verify_time = 0;

lib/libtls/tls_config.c

811

tls_config_verify(struct tls_config *config)

lib/libtls/tls_config.c

813

config->verify_cert = 1;

lib/libtls/tls_config.c

814

config->verify_name = 1;

lib/libtls/tls_config.c

815

config->verify_time = 1;

lib/libtls/tls_config.c

819

tls_config_ocsp_require_stapling(struct tls_config *config)

lib/libtls/tls_config.c

821

config->ocsp_require_stapling = 1;

lib/libtls/tls_config.c

825

tls_config_verify_client(struct tls_config *config)

lib/libtls/tls_config.c

827

config->verify_client = 1;

lib/libtls/tls_config.c

831

tls_config_verify_client_optional(struct tls_config *config)

lib/libtls/tls_config.c

833

config->verify_client = 2;

lib/libtls/tls_config.c

837

tls_config_skip_private_key_check(struct tls_config *config)

lib/libtls/tls_config.c

839

config->skip_private_key_check = 1;

lib/libtls/tls_config.c

843

tls_config_use_fake_private_key(struct tls_config *config)

lib/libtls/tls_config.c

845

config->use_fake_private_key = 1;

lib/libtls/tls_config.c

846

config->skip_private_key_check = 1;

lib/libtls/tls_config.c

850

tls_config_set_ocsp_staple_file(struct tls_config *config, const char *staple_file)

lib/libtls/tls_config.c

852

return tls_keypair_set_ocsp_staple_file(config->keypair, &config->error,

lib/libtls/tls_config.c

857

tls_config_set_ocsp_staple_mem(struct tls_config *config, const uint8_t *staple,

lib/libtls/tls_config.c

860

return tls_keypair_set_ocsp_staple_mem(config->keypair, &config->error,

lib/libtls/tls_config.c

865

tls_config_set_session_id(struct tls_config *config,

lib/libtls/tls_config.c

869

tls_config_set_errorx(config, TLS_ERROR_INVALID_ARGUMENT,

lib/libtls/tls_config.c

873

memset(config->session_id, 0, sizeof(config->session_id));

lib/libtls/tls_config.c

874

memcpy(config->session_id, session_id, len);

lib/libtls/tls_config.c

879

tls_config_set_session_lifetime(struct tls_config *config, int lifetime)

lib/libtls/tls_config.c

882

tls_config_set_errorx(config, TLS_ERROR_INVALID_ARGUMENT,

lib/libtls/tls_config.c

887

tls_config_set_errorx(config, TLS_ERROR_INVALID_ARGUMENT,

lib/libtls/tls_config.c

892

config->session_lifetime = lifetime;

lib/libtls/tls_config.c

897

tls_config_add_ticket_key(struct tls_config *config, uint32_t keyrev,

lib/libtls/tls_config.c

905

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

919

struct tls_ticket_key *tk = &config->ticket_keys[i];

lib/libtls/tls_config.c

929

tls_config_set_errorx(config, TLS_ERROR_UNKNOWN,

lib/libtls/tls_config.c

934

memmove(&config->ticket_keys[1], &config->ticket_keys[0],

lib/libtls/tls_config.c

935

sizeof(config->ticket_keys) - sizeof(config->ticket_keys[0]));

lib/libtls/tls_config.c

936

config->ticket_keys[0] = newkey;

lib/libtls/tls_config.c

938

config->ticket_autorekey = 0;

lib/libtls/tls_config.c

944

tls_config_ticket_autorekey(struct tls_config *config)

lib/libtls/tls_config.c

950

rv = tls_config_add_ticket_key(config, config->ticket_keyrev++, key,

lib/libtls/tls_config.c

952

config->ticket_autorekey = 1;

lib/libtls/tls_config.c

96

struct tls_config *config;

lib/libtls/tls_config.c

99

if ((config = calloc(1, sizeof(*config))) == NULL)

lib/libtls/tls_internal.h

184

struct tls_config *config;

lib/libtls/tls_internal.h

258

int tls_config_ticket_autorekey(struct tls_config *config);

lib/libtls/tls_internal.h

327

void tls_config_skip_private_key_check(struct tls_config *config);

lib/libtls/tls_internal.h

328

void tls_config_use_fake_private_key(struct tls_config *config);

lib/libtls/tls_ocsp.c

330

if (ctx->config->ocsp_require_stapling) {

lib/libtls/tls_ocsp.c

342

if (ctx->config->verify_cert == 0 || ctx->config->verify_time == 0)

lib/libtls/tls_server.c

143

tls_server_ticket_key(struct tls_config *config, unsigned char *keyname)

lib/libtls/tls_server.c

150

if (config->ticket_autorekey == 1) {

lib/libtls/tls_server.c

151

if (now - 3 * (config->session_lifetime / 4) >

lib/libtls/tls_server.c

152

config->ticket_keys[0].time) {

lib/libtls/tls_server.c

153

if (tls_config_ticket_autorekey(config) == -1)

lib/libtls/tls_server.c

158

struct tls_ticket_key *tk = &config->ticket_keys[i];

lib/libtls/tls_server.c

159

if (now - config->session_lifetime > tk->time)

lib/libtls/tls_server.c

182

key = tls_server_ticket_key(tls_ctx->config, NULL);

lib/libtls/tls_server.c

206

key = tls_server_ticket_key(tls_ctx->config, keyname);

lib/libtls/tls_server.c

224

if (key != &tls_ctx->config->ticket_keys[0])

lib/libtls/tls_server.c

259

if (ctx->config->verify_client != 0) {

lib/libtls/tls_server.c

261

if (ctx->config->verify_client == 1)

lib/libtls/tls_server.c

267

if (ctx->config->alpn != NULL)

lib/libtls/tls_server.c

271

if (ctx->config->dheparams == -1)

lib/libtls/tls_server.c

273

else if (ctx->config->dheparams == 1024)

lib/libtls/tls_server.c

276

if (ctx->config->ecdhecurves != NULL) {

lib/libtls/tls_server.c

278

if (SSL_CTX_set1_groups(*ssl_ctx, ctx->config->ecdhecurves,

lib/libtls/tls_server.c

279

ctx->config->ecdhecurves_len) != 1) {

lib/libtls/tls_server.c

286

if (ctx->config->ciphers_server == 1)

lib/libtls/tls_server.c

295

if (ctx->config->session_lifetime > 0) {

lib/libtls/tls_server.c

297

SSL_CTX_set_timeout(*ssl_ctx, ctx->config->session_lifetime);

lib/libtls/tls_server.c

307

if (SSL_CTX_set_session_id_context(*ssl_ctx, ctx->config->session_id,

lib/libtls/tls_server.c

308

sizeof(ctx->config->session_id)) != 1) {

lib/libtls/tls_server.c

329

if (ctx->config->keypair->next == NULL)

lib/libtls/tls_server.c

334

for (kp = ctx->config->keypair->next; kp != NULL; kp = kp->next) {

lib/libtls/tls_server.c

358

ctx->config->keypair) == -1)

lib/libtls/tls_server.c

57

pthread_mutex_lock(&ctx->config->mutex);

lib/libtls/tls_server.c

58

ctx->config->refcount++;

lib/libtls/tls_server.c

59

pthread_mutex_unlock(&ctx->config->mutex);

lib/libtls/tls_server.c

61

conn_ctx->config = ctx->config;

lib/libtls/tls_server.c

62

conn_ctx->keypair = ctx->config->keypair;

lib/libtls/tls_server.c

74

ctx->config->alpn, ctx->config->alpn_len, in, inlen) ==

lib/libtls/tls_signer.c

330

struct tls_config *config;

lib/libtls/tls_signer.c

343

config = RSA_get_ex_data(rsa, 1);

lib/libtls/tls_signer.c

345

if (pubkey_hash == NULL || config == NULL)

lib/libtls/tls_signer.c

359

if (config->sign_cb(config->sign_cb_arg, pubkey_hash, from, from_len,

lib/libtls/tls_signer.c

403

struct tls_config *config;

lib/libtls/tls_signer.c

416

config = EC_KEY_get_ex_data(eckey, 1);

lib/libtls/tls_signer.c

418

if (pubkey_hash == NULL || config == NULL)

lib/libtls/tls_signer.c

424

if (config->sign_cb(config->sign_cb_arg, pubkey_hash, dgst, dgst_len,

lib/libz/deflate.c

103

local const config configuration_table[2] = {

lib/libz/deflate.c

108

local const config configuration_table[10] = {

libexec/spamd/spamd.c

422

read_configline(FILE *config)

libexec/spamd/spamd.c

427

if ((buf = fgetln(config, &len))) {

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

205

peer_config_to_ssl_ctx(const struct peer_config *config)

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

210

fprintf(stderr, "SSL_CTX_new(%s) failed\n", config->name);

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

213

if (!SSL_CTX_set_max_proto_version(ctx, config->max_version)) {

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

214

fprintf(stderr, "max_proto_version(%s) failed\n", config->name);

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

217

if (!SSL_CTX_set_min_proto_version(ctx, config->min_version)) {

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

218

fprintf(stderr, "min_proto_version(%s) failed\n", config->name);

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

221

if (!SSL_CTX_set_cipher_list(ctx, config->ciphers)) {

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

222

fprintf(stderr, "set_cipher_list(%s) failed\n", config->name);

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

226

if (config->server) {

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

230

config->name);

regress/lib/libssl/unit/ssl_get_shared_ciphers.c

236

config->name);

regress/lib/libssl/verify/verify.c

140

peer_config_to_ssl_ctx(const struct peer_config *config)

regress/lib/libssl/verify/verify.c

145

fprintf(stderr, "SSL_CTX_new(%s) failed\n", config->name);

regress/lib/libssl/verify/verify.c

149

if (config->server) {

regress/lib/libssl/verify/verify.c

150

if (!SSL_CTX_use_certificate_file(ctx, config->cert,

regress/lib/libssl/verify/verify.c

153

config->name);

regress/lib/libssl/verify/verify.c

156

if (config->key != NULL && !SSL_CTX_use_PrivateKey_file(ctx,

regress/lib/libssl/verify/verify.c

157

config->key, SSL_FILETYPE_PEM)) {

regress/lib/libssl/verify/verify.c

159

config->name);

regress/lib/libssl/verify/verify.c

164

if (config->ca_file != NULL) {

regress/lib/libssl/verify/verify.c

165

if (!SSL_CTX_load_verify_locations(ctx, config->ca_file, NULL)) {

regress/lib/libssl/verify/verify.c

167

config->name);

regress/usr.bin/openssl/options/optionstest.c

29

CONF *config;

sbin/mount_vnd/mount_vnd.c

114

rv = config(argv[1], argv[0], dp, key, keylen);

sbin/mount_vnd/mount_vnd.c

57

int config(char *, char *, struct disklabel *, char *, size_t);

sbin/unwind/libunbound/util/config_file.c

2486

config_apply(struct config_file* config)

sbin/unwind/libunbound/util/config_file.c

2488

MAX_TTL = (time_t)config->max_ttl;

sbin/unwind/libunbound/util/config_file.c

2489

MIN_TTL = (time_t)config->min_ttl;

sbin/unwind/libunbound/util/config_file.c

2490

SERVE_EXPIRED = config->serve_expired;

sbin/unwind/libunbound/util/config_file.c

2491

SERVE_EXPIRED_TTL = (time_t)config->serve_expired_ttl;

sbin/unwind/libunbound/util/config_file.c

2492

SERVE_EXPIRED_TTL_RESET = config->serve_expired_ttl_reset;

sbin/unwind/libunbound/util/config_file.c

2493

SERVE_EXPIRED_REPLY_TTL = (time_t)config->serve_expired_reply_ttl;

sbin/unwind/libunbound/util/config_file.c

2494

SERVE_ORIGINAL_TTL = config->serve_original_ttl;

sbin/unwind/libunbound/util/config_file.c

2495

MAX_NEG_TTL = (time_t)config->max_negative_ttl;

sbin/unwind/libunbound/util/config_file.c

2496

MIN_NEG_TTL = (time_t)config->min_negative_ttl;

sbin/unwind/libunbound/util/config_file.c

2497

RTT_MIN_TIMEOUT = config->infra_cache_min_rtt;

sbin/unwind/libunbound/util/config_file.c

2498

RTT_MAX_TIMEOUT = config_apply_max_rtt(config->infra_cache_max_rtt);

sbin/unwind/libunbound/util/config_file.c

2499

EDNS_ADVERTISED_SIZE = (uint16_t)config->edns_buffer_size;

sbin/unwind/libunbound/util/config_file.c

2500

MINIMAL_RESPONSES = config->minimal_responses;

sbin/unwind/libunbound/util/config_file.c

2501

RRSET_ROUNDROBIN = config->rrset_roundrobin;

sbin/unwind/libunbound/util/config_file.c

2502

LOG_TAG_QUERYREPLY = config->log_tag_queryreply;

sbin/unwind/libunbound/util/config_file.c

2503

MAX_GLOBAL_QUOTA = config->max_global_quota;

sbin/unwind/libunbound/util/config_file.c

2504

UNKNOWN_SERVER_NICENESS = config->unknown_server_time_limit;

sbin/unwind/libunbound/util/config_file.c

2505

log_set_time_asc(config->log_time_ascii);

sbin/unwind/libunbound/util/config_file.c

2506

log_set_time_iso(config->log_time_iso);

sbin/unwind/libunbound/util/config_file.c

2507

autr_permit_small_holddown = config->permit_small_holddown;

sbin/unwind/libunbound/util/config_file.c

2508

stream_wait_max = config->stream_wait_size;

sbin/unwind/libunbound/util/config_file.c

2509

http2_query_buffer_max = config->http_query_buffer_size;

sbin/unwind/libunbound/util/config_file.c

2510

http2_response_buffer_max = config->http_response_buffer_size;

sbin/unwind/libunbound/util/config_file.h

1004

void config_apply(struct config_file* config);

sbin/unwind/libunbound/util/config_file.h

1014

void config_lookup_uid(struct config_file* config);

sbin/unwind/libunbound/util/config_file.h

1024

int config_set_option(struct config_file* config, const char* option,

sbin/unwind/libunbound/util/config_file.h

981

void config_auto_slab_values(struct config_file* config);

sbin/unwind/libunbound/util/config_file.h

991

int config_read(struct config_file* config, const char* filename,

sbin/unwind/libunbound/util/config_file.h

998

void config_delete(struct config_file* config);

sbin/unwind/libunbound/util/edns.c

103

for(c=config->edns_client_strings; c; c=c->next) {

sbin/unwind/libunbound/util/edns.c

121

edns_strings->client_string_opcode = config->edns_client_string_opcode;

sbin/unwind/libunbound/util/edns.c

97

struct config_file* config)

sbin/unwind/libunbound/util/edns.h

131

struct config_file* config);

sbin/vnconfig/vnconfig.c

147

rv = config(file, vnd, dp, key, keylen);

sbin/vnconfig/vnconfig.c

64

int config(char *, char *, struct disklabel *, char *, size_t);

sys/arch/arm64/arm64/machdep.c

817

void *config = abp->arg2;

sys/arch/arm64/arm64/machdep.c

845

startpa = trunc_page((paddr_t)config);

sys/arch/arm64/arm64/machdep.c

846

endpa = round_page((paddr_t)config + sizeof(struct fdt_head));

sys/arch/arm64/arm64/machdep.c

849

fh = (void *)(vstart + ((paddr_t)config - startpa));

sys/arch/arm64/arm64/machdep.c

854

endpa = round_page((paddr_t)config + betoh32(fh->fh_size));

sys/arch/arm64/arm64/machdep.c

857

config = (void *)(vstart + ((paddr_t)config - startpa));

sys/arch/arm64/arm64/machdep.c

860

if (!fdt_init(config))

sys/arch/arm64/arm64/machdep.c

943

if (fdt_get_size(config) != 0) {

sys/arch/arm64/arm64/machdep.c

944

uint32_t csize, size = round_page(fdt_get_size(config));

sys/arch/arm64/arm64/machdep.c

949

memcpy((void *)pa, config, size); /* copy to physical */

sys/arch/arm64/dev/apldart.c

260

uint32_t config, maj, min, params2, params3, params4, tcr, ttbr;

sys/arch/arm64/dev/apldart.c

317

config = HREAD4(sc, DART_T8110_PROTECT);

sys/arch/arm64/dev/apldart.c

318

if (config & DART_T8110_PROTECT_TTBR_TCR)

sys/arch/arm64/dev/apldart.c

321

config = HREAD4(sc, DART_T8020_CONFIG);

sys/arch/arm64/dev/apldart.c

322

if (config & DART_T8020_CONFIG_LOCK)

sys/arch/arm64/dev/aplpinctrl.c

218

aplpinctrl_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/arm64/dev/aplpinctrl.c

229

if (config & GPIO_CONFIG_OUTPUT)

sys/arch/arm64/dev/rpigpio.c

345

rpigpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/arm64/dev/rpigpio.c

359

if (config & GPIO_CONFIG_OUTPUT)

sys/arch/armv7/armv7/armv7_machdep.c

371

void *config;

sys/arch/armv7/armv7/armv7_machdep.c

410

(bus_space_handle_t *)&config);

sys/arch/armv7/armv7/armv7_machdep.c

412

if (!fdt_init(config) || fdt_get_size(config) == 0)

sys/arch/armv7/armv7/armv7_machdep.c

566

size = fdt_get_size(config);

sys/arch/armv7/armv7/armv7_machdep.c

568

memcpy((void *)fdt.pv_pa, config, size);

sys/arch/armv7/exynos/ec_commands.h

983

struct ec_cros_ec_config config;

sys/arch/armv7/exynos/ec_commands.h

987

struct ec_cros_ec_config config;

sys/arch/armv7/exynos/exgpio.c

281

exgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/armv7/exynos/exgpio.c

291

func = (config & GPIO_CONFIG_OUTPUT) ? GPXCON_OUTPUT : GPXCON_INPUT;

sys/arch/armv7/omap/omgpio.c

403

omgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/armv7/omap/omgpio.c

411

if (config & GPIO_CONFIG_OUTPUT)

sys/arch/octeon/dev/if_ogx.c

1462

uint64_t config;

sys/arch/octeon/dev/if_ogx.c

1522

config = PORT_RD_8(sc, BGX_CMR_CONFIG);

sys/arch/octeon/dev/if_ogx.c

1523

config &= ~BGX_CMR_CONFIG_DATA_PKT_RX_EN;

sys/arch/octeon/dev/if_ogx.c

1524

config &= ~BGX_CMR_CONFIG_DATA_PKT_TX_EN;

sys/arch/octeon/dev/if_ogx.c

1525

PORT_WR_8(sc, BGX_CMR_CONFIG, config);

sys/arch/octeon/dev/if_ogx.c

1589

config = PORT_RD_8(sc, BGX_CMR_CONFIG);

sys/arch/octeon/dev/if_ogx.c

1590

config |= BGX_CMR_CONFIG_ENABLE |

sys/arch/octeon/dev/if_ogx.c

1593

PORT_WR_8(sc, BGX_CMR_CONFIG, config);

sys/arch/octeon/dev/octgpio.c

139

octgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/octeon/dev/octgpio.c

153

if (config & GPIO_CONFIG_OUTPUT) {

sys/arch/octeon/dev/octgpio.c

156

switch (config & GPIO_CONFIG_MD_OUTPUT_SEL_MASK) {

sys/arch/riscv64/dev/mpfgpio.c

149

mpfgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/mpfgpio.c

159

if (config & GPIO_CONFIG_OUTPUT) {

sys/arch/riscv64/dev/mpfgpio.c

237

uint32_t config = 0;

sys/arch/riscv64/dev/mpfgpio.c

243

config |= GPIO_CONFIG_OUTPUT;

sys/arch/riscv64/dev/mpfgpio.c

245

mpfgpio_config_pin(sc, cells, config);

sys/arch/riscv64/dev/sfgpio.c

159

sfgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/sfgpio.c

167

if (config & GPIO_CONFIG_OUTPUT) {

sys/arch/riscv64/dev/smtgpio.c

123

smtgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/smtgpio.c

133

if (config & GPIO_CONFIG_OUTPUT)

sys/arch/riscv64/dev/stfpinctrl.c

184

stfpinctrl_jh7100_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/stfpinctrl.c

193

if (config & GPIO_CONFIG_OUTPUT) {

sys/arch/riscv64/dev/stfpinctrl.c

246

stfpinctrl_jh7110_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/stfpinctrl.c

259

if (config & GPIO_CONFIG_OUTPUT) {

sys/arch/riscv64/riscv64/machdep.c

553

void *config = (void *)rbp->dtbp_phys;

sys/arch/riscv64/riscv64/machdep.c

577

startpa = trunc_page((paddr_t)config);

sys/arch/riscv64/riscv64/machdep.c

578

endpa = round_page((paddr_t)config + sizeof(struct fdt_head));

sys/arch/riscv64/riscv64/machdep.c

581

fh = (void *)(vstart + ((paddr_t)config - startpa));

sys/arch/riscv64/riscv64/machdep.c

586

endpa = round_page((paddr_t)config + betoh32(fh->fh_size));

sys/arch/riscv64/riscv64/machdep.c

589

config = (void *)(vstart + ((paddr_t)config - startpa));

sys/arch/riscv64/riscv64/machdep.c

592

if (!fdt_init(config))

sys/arch/riscv64/riscv64/machdep.c

689

if (fdt_get_size(config) != 0) {

sys/arch/riscv64/riscv64/machdep.c

690

uint32_t csize, size = round_page(fdt_get_size(config));

sys/arch/riscv64/riscv64/machdep.c

695

memcpy((void *)PHYS_TO_DMAP(pa), config, size);

sys/arch/sparc64/dev/lom.c

238

uint8_t reg, fw_rev, config, config2, config3;

sys/arch/sparc64/dev/lom.c

272

lom_read(sc, LOM_IDX_CONFIG, &config))

sys/arch/sparc64/dev/lom.c

296

sc->sc_num_fan = min((config >> 5) & 0x7, LOM_MAX_FAN);

sys/arch/sparc64/dev/lom.c

297

sc->sc_num_psu = min((config >> 3) & 0x3, LOM_MAX_PSU);

sys/dev/acpi/acpihpet.c

123

sc->sc_save.timers[0].config = acpihpet_r(sc->sc_iot,

sys/dev/acpi/acpihpet.c

129

sc->sc_save.timers[1].config = acpihpet_r(sc->sc_iot,

sys/dev/acpi/acpihpet.c

135

sc->sc_save.timers[2].config = acpihpet_r(sc->sc_iot,

sys/dev/acpi/acpihpet.c

154

HPET_TIMER0_CONFIG, sc->sc_save.timers[0].config);

sys/dev/acpi/acpihpet.c

160

HPET_TIMER1_CONFIG, sc->sc_save.timers[1].config);

sys/dev/acpi/acpihpet.c

166

HPET_TIMER2_CONFIG, sc->sc_save.timers[2].config);

sys/dev/acpi/acpihpet.c

60

uint64_t config;

sys/dev/ata/atascsi.h

70

u_int16_t config; /* 0 */

sys/dev/fdt/amlpinctrl.c

640

amlpinctrl_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/amlpinctrl.c

665

config &= ~GPIO_CONFIG_OUTPUT;

sys/dev/fdt/amlpinctrl.c

670

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/bcm2835_gpio.c

236

bcmgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/bcm2835_gpio.c

244

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/bcm2835_gpio.c

248

if (config & GPIO_CONFIG_PULL_UP)

sys/dev/fdt/bcm2835_gpio.c

250

else if (config & GPIO_CONFIG_PULL_DOWN)

sys/dev/fdt/bcm2835_gpio.c

336

uint32_t config;

sys/dev/fdt/bcm2835_gpio.c

341

config = 0;

sys/dev/fdt/bcm2835_gpio.c

343

config |= GPIO_CONFIG_OUTPUT;

sys/dev/fdt/bcm2835_gpio.c

345

config |= GPIO_CONFIG_PULL_UP;

sys/dev/fdt/bcm2835_gpio.c

347

config |= GPIO_CONFIG_PULL_DOWN;

sys/dev/fdt/bcm2835_gpio.c

349

bcmgpio_config_pin(sc, cells, config);

sys/dev/fdt/bcmstbgpio.c

159

bcmstbgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/bcmstbgpio.c

168

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/cwfg.c

257

uint8_t config, mode, val;

sys/dev/fdt/cwfg.c

262

if ((error = cwfg_read(sc, CONFIG_REG, &config)) != 0)

sys/dev/fdt/cwfg.c

270

need_update = !(config & CONFIG_UFG);

sys/dev/fdt/cwfg.c

292

if ((error = cwfg_read(sc, CONFIG_REG, &config)) != 0)

sys/dev/fdt/cwfg.c

294

config |= CONFIG_UFG;

sys/dev/fdt/cwfg.c

295

if ((error = cwfg_write(sc, CONFIG_REG, config)) != 0)

sys/dev/fdt/dwpcie.c

392

int atu, config, ctrl, glue;

sys/dev/fdt/dwpcie.c

408

config = OF_getindex(faa->fa_node, "config", "reg-names");

sys/dev/fdt/dwpcie.c

409

if (config < 0 || config >= faa->fa_nreg) {

sys/dev/fdt/dwpcie.c

414

sc->sc_conf_base = faa->fa_reg[config].addr;

sys/dev/fdt/dwpcie.c

415

sc->sc_conf_size = faa->fa_reg[config].size;

sys/dev/fdt/imxgpio.c

150

imxgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/imxgpio.c

160

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/mvgpio.c

101

mvgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/mvgpio.c

109

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/mvpinctrl.c

280

mvpinctrl_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/mvpinctrl.c

288

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/plgpio.c

104

plgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/plgpio.c

112

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/qcgpio_fdt.c

201

qcgpio_fdt_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/qcgpio_fdt.c

209

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/qcpmicgpio.c

170

qcpmicgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/qcpmicgpio.c

180

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/rkgpio.c

206

rkgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/rkgpio.c

217

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/rkgpio.c

221

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/fdt/sxipio.c

404

sxipio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/sxipio.c

414

mux = (config & GPIO_CONFIG_OUTPUT) ? 1 : 0;

sys/dev/i2c/pca9554.c

163

pcagpio_config_pin(void *arg, uint32_t *cells, int config)

sys/dev/i2c/pca9554.c

181

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/i2c/w83l784r.c

164

u_int8_t cmd, data, config;

sys/dev/i2c/w83l784r.c

229

config = wbenv_readreg(sc, W83L784R_CONFIG);

sys/dev/i2c/w83l784r.c

230

wbenv_writereg(sc, W83L784R_CONFIG, config | 0x01);

sys/dev/ic/ciss.c

1075

if (pdid->config & CISS_PD_SPARE)

sys/dev/ic/cissreg.h

243

u_int8_t config;

sys/dev/ic/iha.c

2464

u_int8_t config = sc->HCS_Tcs[target].TCS_SConfig0;

sys/dev/ic/iha.c

2474

if ((config & ALTPD) == 0)

sys/dev/ic/lm78.c

457

u_int i, config;

sys/dev/ic/lm78.c

475

config = sc->lm_readreg(sc, LM_CONFIG);

sys/dev/ic/lm78.c

476

sc->lm_writereg(sc, LM_CONFIG, config | 0x01);

sys/dev/ic/pgt.c

2533

uint32_t mode, bsstype, config, profile, channel, slot, preamble;

sys/dev/ic/pgt.c

2538

config = PGT_CONFIG_MANUAL_RUN | PGT_CONFIG_RX_ANNEX;

sys/dev/ic/pgt.c

2584

config |= PGT_CONFIG_WDS;

sys/dev/ic/pgt.c

2653

config = htole32(config);

sys/dev/ic/pgt.c

2688

SETOID(PGT_OID_CONFIG, &config, sizeof(config));

sys/dev/ic/qwx.c

1227

struct target_resource_config *config)

sys/dev/ic/qwx.c

1229

config->num_vdevs = 4;

sys/dev/ic/qwx.c

1230

config->num_peers = 16;

sys/dev/ic/qwx.c

1231

config->num_tids = 32;

sys/dev/ic/qwx.c

1233

config->num_offload_peers = 3;

sys/dev/ic/qwx.c

1234

config->num_offload_reorder_buffs = 3;

sys/dev/ic/qwx.c

1235

config->num_peer_keys = TARGET_NUM_PEER_KEYS;

sys/dev/ic/qwx.c

1236

config->ast_skid_limit = TARGET_AST_SKID_LIMIT;

sys/dev/ic/qwx.c

1237

config->tx_chain_mask = (1 << sc->target_caps.num_rf_chains) - 1;

sys/dev/ic/qwx.c

1238

config->rx_chain_mask = (1 << sc->target_caps.num_rf_chains) - 1;

sys/dev/ic/qwx.c

1239

config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwx.c

1240

config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwx.c

1241

config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwx.c

1242

config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;

sys/dev/ic/qwx.c

1243

config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;

sys/dev/ic/qwx.c

1244

config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;

sys/dev/ic/qwx.c

1245

config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwx.c

1246

config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwx.c

1247

config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;

sys/dev/ic/qwx.c

1248

config->num_mcast_groups = 0;

sys/dev/ic/qwx.c

1249

config->num_mcast_table_elems = 0;

sys/dev/ic/qwx.c

1250

config->mcast2ucast_mode = 0;

sys/dev/ic/qwx.c

1251

config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;

sys/dev/ic/qwx.c

1252

config->num_wds_entries = 0;

sys/dev/ic/qwx.c

1253

config->dma_burst_size = 0;

sys/dev/ic/qwx.c

1254

config->rx_skip_defrag_timeout_dup_detection_check = 0;

sys/dev/ic/qwx.c

1255

config->vow_config = TARGET_VOW_CONFIG;

sys/dev/ic/qwx.c

1256

config->gtk_offload_max_vdev = 2;

sys/dev/ic/qwx.c

1257

config->num_msdu_desc = 0x400;

sys/dev/ic/qwx.c

1258

config->beacon_tx_offload_max_vdev = 2;

sys/dev/ic/qwx.c

1259

config->rx_batchmode = TARGET_RX_BATCHMODE;

sys/dev/ic/qwx.c

1261

config->peer_map_unmap_v2_support = 0;

sys/dev/ic/qwx.c

1262

config->use_pdev_id = 1;

sys/dev/ic/qwx.c

1263

config->max_frag_entries = 0xa;

sys/dev/ic/qwx.c

1264

config->num_tdls_vdevs = 0x1;

sys/dev/ic/qwx.c

1265

config->num_tdls_conn_table_entries = 8;

sys/dev/ic/qwx.c

1266

config->beacon_tx_offload_max_vdev = 0x2;

sys/dev/ic/qwx.c

1267

config->num_multicast_filter_entries = 0x20;

sys/dev/ic/qwx.c

1268

config->num_wow_filters = 0x16;

sys/dev/ic/qwx.c

1269

config->num_keep_alive_pattern = 0;

sys/dev/ic/qwx.c

1270

config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;

sys/dev/ic/qwx.c

1318

struct target_resource_config *config)

sys/dev/ic/qwx.c

1320

config->num_vdevs = sc->num_radios * TARGET_NUM_VDEVS(sc);

sys/dev/ic/qwx.c

1323

config->num_peers = TARGET_NUM_PEERS(sc, DBS);

sys/dev/ic/qwx.c

1324

config->num_tids = TARGET_NUM_TIDS(sc, DBS);

sys/dev/ic/qwx.c

1326

config->num_peers = TARGET_NUM_PEERS(sc, DBS_SBS);

sys/dev/ic/qwx.c

1327

config->num_tids = TARGET_NUM_TIDS(sc, DBS_SBS);

sys/dev/ic/qwx.c

1330

config->num_peers = TARGET_NUM_PEERS(sc, SINGLE);

sys/dev/ic/qwx.c

1331

config->num_tids = TARGET_NUM_TIDS(sc, SINGLE);

sys/dev/ic/qwx.c

1333

config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;

sys/dev/ic/qwx.c

1334

config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;

sys/dev/ic/qwx.c

1335

config->num_peer_keys = TARGET_NUM_PEER_KEYS;

sys/dev/ic/qwx.c

1336

config->ast_skid_limit = TARGET_AST_SKID_LIMIT;

sys/dev/ic/qwx.c

1337

config->tx_chain_mask = (1 << sc->target_caps.num_rf_chains) - 1;

sys/dev/ic/qwx.c

1338

config->rx_chain_mask = (1 << sc->target_caps.num_rf_chains) - 1;

sys/dev/ic/qwx.c

1339

config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwx.c

1340

config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwx.c

1341

config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwx.c

1342

config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;

sys/dev/ic/qwx.c

1345

config->rx_decap_mode = TARGET_DECAP_MODE_RAW;

sys/dev/ic/qwx.c

1347

config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;

sys/dev/ic/qwx.c

1349

config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;

sys/dev/ic/qwx.c

1350

config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwx.c

1351

config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwx.c

1352

config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;

sys/dev/ic/qwx.c

1353

config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;

sys/dev/ic/qwx.c

1354

config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;

sys/dev/ic/qwx.c

1355

config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;

sys/dev/ic/qwx.c

1356

config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;

sys/dev/ic/qwx.c

1357

config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;

sys/dev/ic/qwx.c

1358

config->dma_burst_size = TARGET_DMA_BURST_SIZE;

sys/dev/ic/qwx.c

1359

config->rx_skip_defrag_timeout_dup_detection_check =

sys/dev/ic/qwx.c

1361

config->vow_config = TARGET_VOW_CONFIG;

sys/dev/ic/qwx.c

1362

config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwx.c

1363

config->num_msdu_desc = TARGET_NUM_MSDU_DESC;

sys/dev/ic/qwx.c

1364

config->beacon_tx_offload_max_vdev = sc->num_radios * TARGET_MAX_BCN_OFFLD;

sys/dev/ic/qwx.c

1365

config->rx_batchmode = TARGET_RX_BATCHMODE;

sys/dev/ic/qwx.c

1366

config->peer_map_unmap_v2_support = 1;

sys/dev/ic/qwx.c

1367

config->twt_ap_pdev_count = sc->num_radios;

sys/dev/ic/qwx.c

1368

config->twt_ap_sta_count = 1000;

sys/dev/ic/qwx.c

1369

config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;

sys/dev/ic/qwx.c

1370

config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI;

sys/dev/ic/qwx.c

1371

config->ema_max_vap_cnt = sc->num_radios;

sys/dev/ic/qwx.c

1372

config->ema_max_profile_period = TARGET_EMA_MAX_PROFILE_PERIOD;

sys/dev/ic/qwx.c

1373

config->beacon_tx_offload_max_vdev += config->ema_max_vap_cnt;

sys/dev/ic/qwx.c

19737

struct target_resource_config config;

sys/dev/ic/qwx.c

19740

memset(&config, 0, sizeof(config));

sys/dev/ic/qwx.c

19742

sc->hw_params.hw_ops->wmi_init_config(sc, &config);

sys/dev/ic/qwx.c

19745

config.is_reg_cc_ext_event_supported = 1;

sys/dev/ic/qwx.c

19747

memcpy(&wmi_sc->wlan_resource_config, &config, sizeof(config));

sys/dev/ic/qwxreg.h

5695

uint32_t config; /* enum wmi_fils_discovery_cmd_type */

sys/dev/ic/qwxvar.h

261

struct target_resource_config *config);

sys/dev/ic/qwz.c

1000

config->peer_map_unmap_version = 0x1;

sys/dev/ic/qwz.c

1001

config->use_pdev_id = 1;

sys/dev/ic/qwz.c

1002

config->max_frag_entries = 0xa;

sys/dev/ic/qwz.c

1003

config->num_tdls_vdevs = 0x1;

sys/dev/ic/qwz.c

1004

config->num_tdls_conn_table_entries = 8;

sys/dev/ic/qwz.c

1005

config->beacon_tx_offload_max_vdev = 0x2;

sys/dev/ic/qwz.c

1006

config->num_multicast_filter_entries = 0x20;

sys/dev/ic/qwz.c

1007

config->num_wow_filters = 0x16;

sys/dev/ic/qwz.c

1008

config->num_keep_alive_pattern = 0;

sys/dev/ic/qwz.c

966

struct wmi_resource_config_arg *config)

sys/dev/ic/qwz.c

968

config->num_vdevs = 4;

sys/dev/ic/qwz.c

969

config->num_peers = 16;

sys/dev/ic/qwz.c

970

config->num_tids = 32;

sys/dev/ic/qwz.c

972

config->num_offload_peers = 3;

sys/dev/ic/qwz.c

973

config->num_offload_reorder_buffs = 3;

sys/dev/ic/qwz.c

974

config->num_peer_keys = TARGET_NUM_PEER_KEYS;

sys/dev/ic/qwz.c

975

config->ast_skid_limit = TARGET_AST_SKID_LIMIT;

sys/dev/ic/qwz.c

976

config->tx_chain_mask = (1 << sc->target_caps.num_rf_chains) - 1;

sys/dev/ic/qwz.c

977

config->rx_chain_mask = (1 << sc->target_caps.num_rf_chains) - 1;

sys/dev/ic/qwz.c

978

config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwz.c

979

config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwz.c

980

config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;

sys/dev/ic/qwz.c

981

config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;

sys/dev/ic/qwz.c

982

config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;

sys/dev/ic/qwz.c

983

config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;

sys/dev/ic/qwz.c

984

config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwz.c

985

config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;

sys/dev/ic/qwz.c

986

config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;

sys/dev/ic/qwz.c

987

config->num_mcast_groups = 0;

sys/dev/ic/qwz.c

988

config->num_mcast_table_elems = 0;

sys/dev/ic/qwz.c

989

config->mcast2ucast_mode = 0;

sys/dev/ic/qwz.c

990

config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;

sys/dev/ic/qwz.c

991

config->num_wds_entries = 0;

sys/dev/ic/qwz.c

992

config->dma_burst_size = 0;

sys/dev/ic/qwz.c

993

config->rx_skip_defrag_timeout_dup_detection_check = 0;

sys/dev/ic/qwz.c

994

config->vow_config = TARGET_VOW_CONFIG;

sys/dev/ic/qwz.c

995

config->gtk_offload_max_vdev = 2;

sys/dev/ic/qwz.c

996

config->num_msdu_desc = 0x400;

sys/dev/ic/qwz.c

997

config->beacon_tx_offload_max_vdev = 2;

sys/dev/ic/qwz.c

998

config->rx_batchmode = TARGET_RX_BATCHMODE;

sys/dev/ic/qwzreg.h

5749

uint32_t config; /* enum wmi_fils_discovery_cmd_type */

sys/dev/ic/qwzvar.h

237

struct wmi_resource_config_arg *config);

sys/dev/isa/uha_isa.c

149

u_int16_t model, config;

sys/dev/isa/uha_isa.c

158

config = (bus_space_read_1(iot, ioh, U14_CONFIG + 0) << 8) |

sys/dev/isa/uha_isa.c

163

switch (config & U14_DMA_MASK) {

sys/dev/isa/uha_isa.c

175

config & U14_DMA_MASK);

sys/dev/isa/uha_isa.c

188

switch (config & U14_IRQ_MASK) {

sys/dev/isa/uha_isa.c

203

config & U14_IRQ_MASK);

sys/dev/isa/uha_isa.c

223

sc->sc_scsi_dev = config & U14_HOSTID_MASK;

sys/dev/ofw/ofw_gpio.c

46

int len, config, active;

sys/dev/ofw/ofw_gpio.c

60

config = GPIO_CONFIG_INPUT;

sys/dev/ofw/ofw_gpio.c

63

config = GPIO_CONFIG_OUTPUT;

sys/dev/ofw/ofw_gpio.c

66

config = GPIO_CONFIG_OUTPUT;

sys/dev/ofw/ofw_gpio.c

76

gc->gc_config_pin(gc->gc_cookie, gpio, config);

sys/dev/ofw/ofw_gpio.c

77

if (config & GPIO_CONFIG_OUTPUT)

sys/dev/ofw/ofw_gpio.c

87

gpio_controller_config_pin(uint32_t *cells, int config)

sys/dev/ofw/ofw_gpio.c

98

gc->gc_config_pin(gc->gc_cookie, &cells[1], config);

sys/dev/ofw/ofw_pinctrl.c

100

pinctrl_byname(int node, const char *config)

sys/dev/ofw/ofw_pinctrl.c

104

id = OF_getindex(node, config, "pinctrl-names");

sys/dev/pci/azalia.c

1696

switch (CORB_CD_PORT(w->d.pin.config)) {

sys/dev/pci/azalia.c

1728

CORB_CD_LOC_GEO(w->d.pin.config) ==

sys/dev/pci/azalia.c

1930

loc = CORB_CD_LOC_GEO(w->d.pin.config);

sys/dev/pci/azalia.c

3296

this->d.pin.config = result;

sys/dev/pci/azalia.c

3352

if (CORB_CD_PORT(this->d.pin.config) == CORB_CD_NONE)

sys/dev/pci/azalia.c

3612

printf("\t[%2.2d/%2.2d] ", CORB_CD_ASSOCIATION(this->d.pin.config),

sys/dev/pci/azalia.c

3613

CORB_CD_SEQUENCE(this->d.pin.config));

sys/dev/pci/azalia.c

3614

printf("color=%s ", pin_colors[CORB_CD_COLOR(this->d.pin.config)]);

sys/dev/pci/azalia.c

3615

printf("device=%s ", pin_devices[CORB_CD_DEVICE(this->d.pin.config)]);

sys/dev/pci/azalia.c

3616

printf("conn=%s ", pin_conn[CORB_CD_PORT(this->d.pin.config)]);

sys/dev/pci/azalia.c

3617

printf("conntype=%s\n", pin_conntype[CORB_CD_CONNECTION(this->d.pin.config)]);

sys/dev/pci/azalia.c

3618

printf("\tlocation=%s ", pin_geo[CORB_CD_LOC_GEO(this->d.pin.config)]);

sys/dev/pci/azalia.c

3619

printf("chassis=%s ", pin_chass[CORB_CD_LOC_CHASS(this->d.pin.config)]);

sys/dev/pci/azalia.c

3621

if (CORB_CD_LOC_GEO(this->d.pin.config) == CORB_CD_LOC_SPEC0) {

sys/dev/pci/azalia.c

3622

if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_EXTERNAL)

sys/dev/pci/azalia.c

3624

else if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_INTERNAL)

sys/dev/pci/azalia.c

3626

else if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_LOC_OTHER)

sys/dev/pci/azalia.c

3628

} else if (CORB_CD_LOC_GEO(this->d.pin.config) == CORB_CD_LOC_SPEC1) {

sys/dev/pci/azalia.c

3629

if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_EXTERNAL)

sys/dev/pci/azalia.c

3631

else if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_INTERNAL)

sys/dev/pci/azalia.c

3633

else if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_LOC_OTHER)

sys/dev/pci/azalia.c

3635

} else if (CORB_CD_LOC_GEO(this->d.pin.config) == CORB_CD_LOC_SPEC2) {

sys/dev/pci/azalia.c

3636

if (CORB_CD_LOC_CHASS(this->d.pin.config) == CORB_CD_INTERNAL)

sys/dev/pci/azalia.h

575

uint32_t config;

sys/dev/pci/azalia_codec.c

2604

w->d.pin.config &= ~(mask);

sys/dev/pci/azalia_codec.c

2605

w->d.pin.config |= val << offset;

sys/dev/pci/azalia_codec.c

2651

w->d.pin.config = 0x23a11040;

sys/dev/pci/azalia_codec.c

2658

w->d.pin.config = 0x2121103f;

sys/dev/pci/azalia_codec.c

2665

w->d.pin.config = 0x21211010;

sys/dev/pci/azalia_codec.c

2672

w->d.pin.config = 0x21a11010;

sys/dev/pci/azalia_codec.c

2679

w->d.pin.config = 0x21a190f0;

sys/dev/pci/azalia_codec.c

2686

w->d.pin.config = 0x212140ff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

340

struct tile_config *config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1044

se_cnt = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3199

struct tile_config *config)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3201

config->gb_addr_config = adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3202

config->tile_config_ptr = adev->gfx.config.tile_mode_array;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3203

config->num_tile_configs =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3204

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3205

config->macro_tile_config_ptr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3206

adev->gfx.config.macrotile_mode_array;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3207

config->num_macro_tile_configs =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3208

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3211

config->num_banks = adev->gfx.config.num_banks;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3212

config->num_ranks = adev->gfx.config.num_ranks;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

744

adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

745

adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

746

adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

747

adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

748

adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

749

adev->gfx.config.max_texture_channel_caches =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

834

adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

835

adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

836

adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

837

adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

838

adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

839

adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

840

adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

841

adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

842

adev->gfx.config.gs_prim_buffer_depth =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

844

adev->gfx.config.double_offchip_lds_buf =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

852

adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

853

adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

854

adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

855

adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

856

adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

857

adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

858

adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

859

adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

860

adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

861

adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

873

adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

874

adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

875

adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

876

adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

877

adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

130

if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

131

(se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

256

if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

257

(rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

884

uint32_t *config, no_regs = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

889

config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

890

if (!config)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

894

config[no_regs++] = 5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

895

config[no_regs++] = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

896

config[no_regs++] = adev->gfx.config.max_tile_pipes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

897

config[no_regs++] = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

898

config[no_regs++] = adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

899

config[no_regs++] = adev->gfx.config.max_backends_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

900

config[no_regs++] = adev->gfx.config.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

901

config[no_regs++] = adev->gfx.config.max_gprs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

902

config[no_regs++] = adev->gfx.config.max_gs_threads;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

903

config[no_regs++] = adev->gfx.config.max_hw_contexts;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

904

config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

905

config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

906

config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

907

config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

908

config[no_regs++] = adev->gfx.config.num_tile_pipes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

909

config[no_regs++] = adev->gfx.config.backend_enable_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

910

config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

911

config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

912

config[no_regs++] = adev->gfx.config.shader_engine_tile_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

913

config[no_regs++] = adev->gfx.config.num_gpus;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

914

config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

915

config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

916

config[no_regs++] = adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

917

config[no_regs++] = adev->gfx.config.num_rbs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

920

config[no_regs++] = adev->rev_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

921

config[no_regs++] = adev->pg_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

922

config[no_regs++] = lower_32_bits(adev->cg_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

925

config[no_regs++] = adev->family;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

926

config[no_regs++] = adev->external_rev_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

929

config[no_regs++] = adev->pdev->device;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

930

config[no_regs++] = adev->pdev->revision;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

931

config[no_regs++] = adev->pdev->subsystem_device;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

932

config[no_regs++] = adev->pdev->subsystem_vendor;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

935

config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

938

config[no_regs++] = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

939

config[no_regs++] = upper_32_bits(adev->cg_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

944

value = config[*pos >> 2];

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

947

kfree(config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

957

kfree(config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2723

adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2724

adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2725

adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2726

adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2727

adev->gfx.config.max_texture_channel_caches =

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2729

adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2730

adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2731

adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2732

adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2733

adev->gfx.config.double_offchip_lds_buf =

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2745

adev->gfx.config.num_sc_per_sh =

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2747

adev->gfx.config.num_packer_per_sc =

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4857

adev->gfx.config.max_shader_engines,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4858

adev->gfx.config.max_sh_per_se,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4859

adev->gfx.config.max_cu_per_sh,

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

47

int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

49

int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

51

void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1614

adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1615

adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1617

adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1618

adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1619

adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1620

adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1621

adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1622

adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1623

adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1624

adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1629

adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1631

adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1633

adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1634

adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1635

adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1638

adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1639

adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1640

adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1641

adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1642

adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1643

adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1644

adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1645

adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1648

adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1649

adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1650

adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1651

adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1652

adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1653

adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1654

adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1655

adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1659

adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1660

adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1661

adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1662

adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1663

adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1664

adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1665

adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1666

adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1667

adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1668

adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1673

adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1675

adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1677

adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1678

adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1679

adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1680

adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1681

adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1682

adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1683

adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

758

num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

759

num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

837

packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

842

ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

848

rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

849

ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

851

ilog2(adev->gfx.config.gb_addr_config_fields.num_se));

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

853

ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

408

struct amdgpu_gfx_config config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1003

adev->gfx.config.pa_sc_tile_steering_override;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1005

dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1021

dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1022

dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1023

dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1024

dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1025

dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1026

adev->gfx.config.gc_gl1c_per_sa;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1027

dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

918

dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

919

dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

935

dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

936

dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

937

adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

938

dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

946

if (adev->gfx.config.ta_cntl2_truncate_coord_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

992

adev->gfx.config.double_offchip_lds_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

994

dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

995

dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

996

dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

997

dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

998

dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

999

dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

115

{ .name = "event", .config = "config:0-7" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

116

{ .name = "instance", .config = "config:8-15" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

117

{ .name = "umask", .config = "config:16-23"},

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

118

{ .name = "type", .config = "config:56-63"}

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

124

.config = "event=0x7,instance=0x46,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

126

.config = "event=0x7,instance=0x47,umask=0x2" }

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

145

{ .name = "event", .config = "config:0-7" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

146

{ .name = "instance", .config = "config:8-15" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

147

{ .name = "umask", .config = "config:16-23"}

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

152

.config = "event=0x7,instance=0x46,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

154

.config = "event=0x7,instance=0x47,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

156

.config = "event=0x7,instance=0x46,umask=0x4" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

158

.config = "event=0x7,instance=0x47,umask=0x4" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

160

.config = "event=0xb,instance=0x46,umask=0x4" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

162

.config = "event=0xb,instance=0x47,umask=0x4" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

164

.config = "event=0xb,instance=0x46,umask=0x8" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

166

.config = "event=0xb,instance=0x47,umask=0x8" }

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

181

.config = "event=0x7,instance=0x4b,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

183

.config = "event=0x7,instance=0x4c,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

185

.config = "event=0x7,instance=0x4d,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

187

.config = "event=0x7,instance=0x4e,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

189

.config = "event=0x7,instance=0x4f,umask=0x2" },

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

191

.config = "event=0x7,instance=0x50,umask=0x2" }

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

218

hwc->config = event->attr.config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

248

hwc->config, 0 /* unused */,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

256

pe->adev->df.funcs->pmc_start(pe->adev, hwc->config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

285

hwc->config, hwc->idx, &count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

314

pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

349

hwc->config_base = (hwc->config >>

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

361

hwc->config, 0 /* unused */,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

398

pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

426

pmu_attr->event_str = events[i].config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

447

struct amdgpu_pmu_config *config)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

449

*fmt_attr = kcalloc(config->num_formats, sizeof(**fmt_attr),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

455

fmt_attr_group->attrs = kcalloc(config->num_formats + 1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

461

*evt_attr = kcalloc(config->num_events, sizeof(**evt_attr), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

466

evt_attr_group->attrs = kcalloc(config->num_events + 1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

484

struct amdgpu_pmu_config *config)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

508

config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

514

config->formats, config->num_formats);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

519

for (i = 0; i < config->num_types; i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

523

config->events,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

526

config->types[i].num_of_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

527

config->types[i].type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

528

total_num_events += config->types[i].num_of_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

533

config->events, config->num_events);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

534

total_num_events = config->num_events;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

80

const char *config;

sys/dev/pci/drm/amd/amdgpu/cik.c

1133

return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/cik.c

1135

return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/cik.c

1137

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;

sys/dev/pci/drm/amd/amdgpu/cik.c

1139

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;

sys/dev/pci/drm/amd/amdgpu/cik.c

1157

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/cik.c

1159

return adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/cik.c

1193

return adev->gfx.config.tile_mode_array[idx];

sys/dev/pci/drm/amd/amdgpu/cik.c

1211

return adev->gfx.config.macrotile_mode_array[idx];

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

448

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

349

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

353

return ((config & 0x0FFFFFFUL) ==

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

360

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

366

if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

394

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

399

df_v3_6_pmc_get_addr(adev, config, counter_idx, 0, lo_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

405

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

417

df_v3_6_pmc_get_addr(adev, config, counter_idx, 1, lo_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

426

eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

427

unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

428

instance = DF_V3_6_GET_INSTANCE(config);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

439

config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

446

uint64_t config)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

453

config & 0x0FFFFFFUL;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

463

uint64_t config, int counter_idx,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

467

if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

481

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

484

return (df_v3_6_pmc_has_counter(adev, config, counter_idx) &&

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

492

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

495

if (df_v3_6_pmc_has_counter(adev, config, counter_idx))

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

501

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

506

df_v3_6_pmc_get_read_settings(adev, config, counter_idx, &lo_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

516

static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

526

return df_v3_6_pmc_add_cntr(adev, config);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

529

config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

547

ret = df_v3_6_pmc_set_deferred(adev, config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

558

static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

568

config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

583

df_v3_6_reset_perfmon_cntr(adev, config, counter_idx);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

584

df_v3_6_pmc_release_cntr(adev, config, counter_idx);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

596

uint64_t config,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

606

df_v3_6_pmc_get_read_settings(adev, config, counter_idx,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

613

if (df_v3_6_pmc_is_deferred(adev, config, counter_idx)) {

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

621

df_v3_6_pmc_set_deferred(adev, config, counter_idx,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

634

config, lo_base_addr, hi_base_addr, lo_val, hi_val);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10040

unsigned int total_cu = adev->gfx.config.max_cu_per_sh *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10041

adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10042

adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10081

~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10129

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10130

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10131

bitmap = i * adev->gfx.config.max_sh_per_se + j;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10152

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10154

if (counter < adev->gfx.config.max_cu_per_sh)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10188

max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10189

adev->gfx.config.max_shader_engines);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10203

max_sa_per_se = adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10205

max_shader_engines = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4341

buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4588

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4589

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4590

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4591

adev->gfx.config.sc_hiz_tile_fifo_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4592

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4603

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4604

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4605

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4606

adev->gfx.config.sc_hiz_tile_fifo_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4607

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4609

adev->gfx.config.gb_addr_config_fields.num_pkrs =

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4614

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4615

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4616

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4617

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4618

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4626

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4628

adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4629

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4632

adev->gfx.config.max_tile_pipes =

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4633

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4635

adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4636

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4638

adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4639

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4641

adev->gfx.config.gb_addr_config_fields.num_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4642

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4644

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4645

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5093

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5094

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5105

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5106

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5109

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5110

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5111

bitmap = i * adev->gfx.config.max_sh_per_se + j;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5122

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5129

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5130

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5149

num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5150

adev->gfx.config.num_sc_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5154

num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5156

num_packer_per_sc = adev->gfx.config.num_packer_per_sc;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5257

int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5282

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5283

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5334

adev->gfx.config.tcc_disabled_mask =

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5350

adev->gfx.config.pa_sc_tile_steering_override =

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6373

adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6410

amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1090

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1091

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1092

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1093

adev->gfx.config.sc_hiz_tile_fifo_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1094

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1098

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1099

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1100

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1101

adev->gfx.config.sc_hiz_tile_fifo_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1102

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1110

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1111

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1112

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1113

adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1114

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1986

sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1987

adev->gfx.config.max_shader_engines);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2005

rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2006

adev->gfx.config.max_shader_engines);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2027

max_sa = adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2028

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2029

rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2030

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2039

adev->gfx.config.backend_enable_mask = active_rb_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2040

adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2118

adev->gfx.config.tcc_disabled_mask =

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2134

adev->gfx.config.pa_sc_tile_steering_override = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2138

adev->gfx.config.ta_cntl2_truncate_coord_mode =

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3611

adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3649

amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4699

adev->gfx.config.gb_addr_config_fields.num_pkrs =

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4702

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4704

adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4705

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4708

adev->gfx.config.max_tile_pipes =

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4709

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4711

adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4712

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4714

adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4715

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4717

adev->gfx.config.gb_addr_config_fields.num_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4718

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4720

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4721

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7401

unsigned total_cu = adev->gfx.config.max_cu_per_sh *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7402

adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7403

adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7449

amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7485

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7486

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7487

bitmap = i * adev->gfx.config.max_sh_per_se + j;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7515

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

869

buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1700

sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1701

adev->gfx.config.max_shader_engines);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1719

rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1720

adev->gfx.config.max_shader_engines);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1741

max_sa = adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1742

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1743

rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1744

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1753

adev->gfx.config.backend_enable_mask = active_rb_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1754

adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1811

adev->gfx.config.pa_sc_tile_steering_override = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2664

adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3544

adev->gfx.config.gb_addr_config_fields.num_pkrs =

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3547

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3549

adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3550

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3553

adev->gfx.config.max_tile_pipes =

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3554

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3556

adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3557

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3559

adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3560

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3562

adev->gfx.config.gb_addr_config_fields.num_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3563

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3565

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3566

REG_GET_FIELD(adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5693

amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5729

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5730

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5731

bitmap = i * adev->gfx.config.max_sh_per_se + j;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5759

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

947

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

948

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

949

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

950

adev->gfx.config.sc_hiz_tile_fifo_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

951

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1338

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1339

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1380

unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1381

unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1472

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1473

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1477

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1478

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1482

((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1488

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1489

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1491

num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1492

adev->gfx.config.max_shader_engines, 16);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1496

if (!adev->gfx.config.backend_enable_mask ||

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1497

adev->gfx.config.num_rbs >= num_rb_pipes)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1501

adev->gfx.config.backend_enable_mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1505

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1506

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1508

adev->gfx.config.rb_config[i][j].rb_backend_disable =

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1510

adev->gfx.config.rb_config[i][j].user_rb_backend_disable =

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1512

adev->gfx.config.rb_config[i][j].raster_config =

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1541

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1553

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1554

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1576

adev->gfx.config.double_offchip_lds_buf = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1589

adev->gfx.config.max_shader_engines = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1590

adev->gfx.config.max_tile_pipes = 12;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1591

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1592

adev->gfx.config.max_sh_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1593

adev->gfx.config.max_backends_per_se = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1594

adev->gfx.config.max_texture_channel_caches = 12;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1595

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1596

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1597

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1599

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1600

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1601

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1602

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1606

adev->gfx.config.max_shader_engines = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1607

adev->gfx.config.max_tile_pipes = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1608

adev->gfx.config.max_cu_per_sh = 5;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1609

adev->gfx.config.max_sh_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1610

adev->gfx.config.max_backends_per_se = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1611

adev->gfx.config.max_texture_channel_caches = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1612

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1613

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1614

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1616

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1617

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1618

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1619

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1623

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1624

adev->gfx.config.max_tile_pipes = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1625

adev->gfx.config.max_cu_per_sh = 5;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1626

adev->gfx.config.max_sh_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1627

adev->gfx.config.max_backends_per_se = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1628

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1629

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1630

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1631

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1633

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1634

adev->gfx.config.sc_prim_fifo_size_backend = 0x40;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1635

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1636

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1640

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1641

adev->gfx.config.max_tile_pipes = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1642

adev->gfx.config.max_cu_per_sh = 6;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1643

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1644

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1645

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1646

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1647

adev->gfx.config.max_gs_threads = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1648

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1650

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1651

adev->gfx.config.sc_prim_fifo_size_backend = 0x40;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1652

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1653

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1657

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1658

adev->gfx.config.max_tile_pipes = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1659

adev->gfx.config.max_cu_per_sh = 5;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1660

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1661

adev->gfx.config.max_backends_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1662

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1663

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1664

adev->gfx.config.max_gs_threads = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1665

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1667

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1668

adev->gfx.config.sc_prim_fifo_size_backend = 0x40;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1669

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1670

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1684

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1685

mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1687

adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1688

adev->gfx.config.mem_max_burst_length_bytes = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1690

adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1691

if (adev->gfx.config.mem_row_size_in_kb > 4)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1692

adev->gfx.config.mem_row_size_in_kb = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1693

adev->gfx.config.shader_engine_tile_size = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1694

adev->gfx.config.num_gpus = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1695

adev->gfx.config.multi_gpu_tile_size = 64;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1698

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1711

if (adev->gfx.config.max_shader_engines == 2)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1713

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1752

WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1753

(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1754

(adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1755

(adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2019

amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2872

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3554

ao_cu_num = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3561

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3562

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3573

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

402

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

405

memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

406

tilemode = adev->gfx.config.tile_mode_array;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

408

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1002

tile = adev->gfx.config.tile_mode_array;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1003

macrotile = adev->gfx.config.macrotile_mode_array;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1005

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1602

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1603

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1645

unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1646

unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1762

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1763

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1767

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1768

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1771

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1777

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1778

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1780

num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1781

adev->gfx.config.max_shader_engines, 16);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1785

if (!adev->gfx.config.backend_enable_mask ||

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1786

adev->gfx.config.num_rbs >= num_rb_pipes) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1791

adev->gfx.config.backend_enable_mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1796

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1797

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1799

adev->gfx.config.rb_config[i][j].rb_backend_disable =

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1801

adev->gfx.config.rb_config[i][j].user_rb_backend_disable =

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1803

adev->gfx.config.rb_config[i][j].raster_config =

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1805

adev->gfx.config.rb_config[i][j].raster_config_1 =

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1880

adev->gfx.config.double_offchip_lds_buf = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1899

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1900

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1901

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1985

((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1986

(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1987

(adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1988

(adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2468

WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2508

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2509

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3271

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3272

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3749

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3899

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3900

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4142

adev->gfx.config.max_shader_engines = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4143

adev->gfx.config.max_tile_pipes = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4144

adev->gfx.config.max_cu_per_sh = 7;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4145

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4146

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4147

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4148

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4149

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4150

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4152

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4153

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4154

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4155

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4159

adev->gfx.config.max_shader_engines = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4160

adev->gfx.config.max_tile_pipes = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4161

adev->gfx.config.max_cu_per_sh = 11;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4162

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4163

adev->gfx.config.max_backends_per_se = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4164

adev->gfx.config.max_texture_channel_caches = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4165

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4166

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4167

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4169

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4170

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4171

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4172

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4176

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4177

adev->gfx.config.max_tile_pipes = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4178

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4179

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4180

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4181

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4182

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4183

adev->gfx.config.max_gs_threads = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4184

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4186

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4187

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4188

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4189

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4195

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4196

adev->gfx.config.max_tile_pipes = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4197

adev->gfx.config.max_cu_per_sh = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4198

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4199

adev->gfx.config.max_backends_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4200

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4201

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4202

adev->gfx.config.max_gs_threads = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4203

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4205

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4206

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4207

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4208

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4213

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4214

mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4216

adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4218

adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4221

adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4222

adev->gfx.config.mem_max_burst_length_bytes = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4246

adev->gfx.config.mem_row_size_in_kb = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4248

adev->gfx.config.mem_row_size_in_kb = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4251

adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4252

if (adev->gfx.config.mem_row_size_in_kb > 4)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4253

adev->gfx.config.mem_row_size_in_kb = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4256

adev->gfx.config.shader_engine_tile_size = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4257

adev->gfx.config.num_gpus = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4258

adev->gfx.config.multi_gpu_tile_size = 64;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4262

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4274

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5032

ao_cu_num = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5039

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5040

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5051

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

996

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

998

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1237

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1238

buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1648

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1649

adev->gfx.config.max_tile_pipes = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1650

adev->gfx.config.max_cu_per_sh = 6;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1651

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1652

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1653

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1654

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1655

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1656

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1658

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1659

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1660

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1661

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1665

adev->gfx.config.max_shader_engines = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1666

adev->gfx.config.max_tile_pipes = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1667

adev->gfx.config.max_cu_per_sh = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1668

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1669

adev->gfx.config.max_backends_per_se = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1670

adev->gfx.config.max_texture_channel_caches = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1671

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1672

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1673

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1675

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1676

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1677

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1678

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1686

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1687

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1688

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1690

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1691

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1692

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1693

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1701

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1702

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1703

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1705

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1706

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1707

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1708

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1712

adev->gfx.config.max_shader_engines = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1713

adev->gfx.config.max_tile_pipes = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1714

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1715

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1716

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1717

adev->gfx.config.max_texture_channel_caches = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1718

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1719

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1720

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1722

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1723

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1724

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1725

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1729

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1730

adev->gfx.config.max_tile_pipes = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1731

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1732

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1733

adev->gfx.config.max_cu_per_sh = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1734

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1735

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1736

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1737

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1739

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1740

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1741

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1742

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1746

adev->gfx.config.max_shader_engines = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1747

adev->gfx.config.max_tile_pipes = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1748

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1749

adev->gfx.config.max_backends_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1750

adev->gfx.config.max_cu_per_sh = 3;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1751

adev->gfx.config.max_texture_channel_caches = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1752

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1753

adev->gfx.config.max_gs_threads = 16;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1754

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1756

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1757

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1758

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1759

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1763

adev->gfx.config.max_shader_engines = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1764

adev->gfx.config.max_tile_pipes = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1765

adev->gfx.config.max_cu_per_sh = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1766

adev->gfx.config.max_sh_per_se = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1767

adev->gfx.config.max_backends_per_se = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1768

adev->gfx.config.max_texture_channel_caches = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1769

adev->gfx.config.max_gprs = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1770

adev->gfx.config.max_gs_threads = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1771

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1773

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1774

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1775

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1776

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1781

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1782

mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1784

adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1786

adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1789

adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1790

adev->gfx.config.mem_max_burst_length_bytes = 256;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1814

adev->gfx.config.mem_row_size_in_kb = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1816

adev->gfx.config.mem_row_size_in_kb = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1819

adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1820

if (adev->gfx.config.mem_row_size_in_kb > 4)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1821

adev->gfx.config.mem_row_size_in_kb = 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1824

adev->gfx.config.shader_engine_tile_size = 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1825

adev->gfx.config.num_gpus = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1826

adev->gfx.config.multi_gpu_tile_size = 64;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1829

switch (adev->gfx.config.mem_row_size_in_kb) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1841

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2067

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2068

const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2071

modearray = adev->gfx.config.tile_mode_array;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2072

mod2array = adev->gfx.config.macrotile_mode_array;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3426

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3427

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3478

unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3479

unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3588

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3589

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3593

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3594

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3597

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3603

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3604

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3606

num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3607

adev->gfx.config.max_shader_engines, 16);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3611

if (!adev->gfx.config.backend_enable_mask ||

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3612

adev->gfx.config.num_rbs >= num_rb_pipes) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3617

adev->gfx.config.backend_enable_mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3622

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3623

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3625

adev->gfx.config.rb_config[i][j].rb_backend_disable =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3627

adev->gfx.config.rb_config[i][j].user_rb_backend_disable =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3629

adev->gfx.config.rb_config[i][j].raster_config =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3631

adev->gfx.config.rb_config[i][j].raster_config_1 =

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3713

adev->gfx.config.double_offchip_lds_buf = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3717

adev->gfx.config.double_offchip_lds_buf = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3728

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3729

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3730

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3785

(adev->gfx.config.sc_prim_fifo_size_frontend <<

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3787

(adev->gfx.config.sc_prim_fifo_size_backend <<

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3789

(adev->gfx.config.sc_hiz_tile_fifo_size <<

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3791

(adev->gfx.config.sc_earlyz_tile_fifo_size <<

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3811

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3812

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4138

WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4174

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4175

amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7040

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7058

ao_cu_num = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7063

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7064

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7075

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1681

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1682

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1688

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2028

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2029

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2030

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2031

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2032

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2036

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2037

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2038

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2039

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2040

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2046

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2047

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2048

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2049

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2050

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2061

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2062

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2063

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2064

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2065

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2073

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2074

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2075

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2076

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2077

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2083

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2084

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2085

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2086

adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2087

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2094

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2095

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2096

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2097

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2098

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2112

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2114

adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2116

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2120

adev->gfx.config.max_tile_pipes =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2121

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2123

adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2125

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2128

adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2130

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2133

adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2135

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2138

adev->gfx.config.gb_addr_config_fields.num_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2140

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2143

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2145

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2531

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2532

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2542

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2543

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2546

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2547

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2550

active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2557

adev->gfx.config.backend_enable_mask = active_rbs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2558

adev->gfx.config.num_rbs = hweight32(active_rbs);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2675

adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2718

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2719

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3326

WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4629

int compute_dim_x = adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4630

adev->gfx.config.max_cu_per_sh *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4631

adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4633

int gpr_reg_size = adev->gfx.config.max_shader_engines + 6;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7752

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7770

if (adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7771

adev->gfx.config.max_sh_per_se > 16)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7775

adev->gfx.config.max_shader_engines,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7776

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7779

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7780

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7786

adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7803

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7805

if (counter < adev->gfx.config.max_cu_per_sh)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1808

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1874

for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1876

for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1879

cu_idx < adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1907

for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1909

for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1912

cu_idx < adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

433

for (se = 0; se < adev->gfx.config.max_shader_engines; se++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

465

for (se = 0; se < adev->gfx.config.max_shader_engines; se++)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

493

int wb_size = adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

637

int wb_size = adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1350

adev->gfx.config.db_debug2 =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1470

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1471

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4534

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4899

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4918

if (adev->gfx.config.max_shader_engines *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4919

adev->gfx.config.max_sh_per_se > 16)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4923

adev->gfx.config.max_shader_engines,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4924

adev->gfx.config.max_sh_per_se);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4929

for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4930

for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4937

disable_masks[i * adev->gfx.config.max_sh_per_se + j],

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4943

for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4945

if (counter < adev->gfx.config.max_cu_per_sh)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

925

adev->gfx.config.max_hw_contexts = 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

926

adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

927

adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

928

adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

929

adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

930

adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

932

adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

934

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

938

adev->gfx.config.max_tile_pipes =

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

939

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

941

adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

943

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

946

adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

948

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

951

adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

953

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

956

adev->gfx.config.gb_addr_config_fields.num_se = 1 <<

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

958

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

961

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

963

adev->gfx.config.gb_addr_config,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

515

adev->gfx.config.max_sh_per_se *

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

516

adev->gfx.config.max_shader_engines);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

578

max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

351

WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

353

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

355

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

369

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

371

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

406

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

563

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

565

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

452

adev->gfx.config.gb_addr_config, indirect);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

537

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

362

adev->gfx.config.gb_addr_config, indirect);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

365

adev->gfx.config.gb_addr_config, 1);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

448

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

380

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/nv.c

382

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

422

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

662

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/pci/drm/amd/amdgpu/si.c

1189

return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/si.c

1191

return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/si.c

1193

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;

sys/dev/pci/drm/amd/amdgpu/si.c

1211

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/si.c

1213

return adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/si.c

1247

return adev->gfx.config.tile_mode_array[idx];

sys/dev/pci/drm/amd/amdgpu/soc15.c

429

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/soc15.c

431

return adev->gfx.config.db_debug2;

sys/dev/pci/drm/amd/amdgpu/soc21.c

302

if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)

sys/dev/pci/drm/amd/amdgpu/soc21.c

303

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/soc24.c

162

adev->gfx.config.gb_addr_config)

sys/dev/pci/drm/amd/amdgpu/soc24.c

163

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

270

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

271

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

272

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

604

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

605

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

606

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

307

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

308

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

309

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

633

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

634

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

635

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

722

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

724

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

726

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1123

tmp = adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

397

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

399

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

401

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

403

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

405

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

407

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

409

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

411

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

413

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

415

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

417

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

419

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

474

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

476

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

478

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

480

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

482

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

484

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

486

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

488

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

490

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

492

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

435

WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

533

UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1242

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1244

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

746

VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1276

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

668

UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1221

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

608

adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1263

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1265

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

631

VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

633

VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1133

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

565

adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

524

adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

861

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1027

adev->gfx.config.gb_addr_config);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

587

VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vi.c

755

return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/vi.c

757

return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/vi.c

759

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;

sys/dev/pci/drm/amd/amdgpu/vi.c

761

return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;

sys/dev/pci/drm/amd/amdgpu/vi.c

779

return adev->gfx.config.gb_addr_config;

sys/dev/pci/drm/amd/amdgpu/vi.c

781

return adev->gfx.config.mc_arb_ramcfg;

sys/dev/pci/drm/amd/amdgpu/vi.c

815

return adev->gfx.config.tile_mode_array[idx];

sys/dev/pci/drm/amd/amdgpu/vi.c

833

return adev->gfx.config.macrotile_mode_array[idx];

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

931

struct tile_config config;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

940

amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

942

args->gb_addr_config = config.gb_addr_config;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

943

args->num_banks = config.num_banks;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

944

args->num_ranks = config.num_ranks;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

946

if (args->num_tile_configs > config.num_tile_configs)

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

947

args->num_tile_configs = config.num_tile_configs;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

949

config.tile_config_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

956

if (args->num_macro_tile_configs > config.num_macro_tile_configs)

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

958

config.num_macro_tile_configs;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

960

config.macro_tile_config_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1433

if (adev->gfx.config.gc_tcp_l1_size) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1434

pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1439

pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1440

pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1446

if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1448

adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1453

pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1454

pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1460

if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1461

pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1466

pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1467

pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1473

if (adev->gfx.config.gc_gl1c_per_sa &&

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1474

adev->gfx.config.gc_gl1c_size_per_instance) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1475

pcache_info[i].cache_size = adev->gfx.config.gc_gl1c_per_sa *

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1476

adev->gfx.config.gc_gl1c_size_per_instance;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1481

pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1487

if (adev->gfx.config.gc_gl2c_per_gpu) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1488

pcache_info[i].cache_size = adev->gfx.config.gc_gl2c_per_gpu;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1493

pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1494

pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1506

pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1520

if (adev->gfx.config.gc_tcp_size_per_cu) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1521

pcache_info[i].cache_size = adev->gfx.config.gc_tcp_size_per_cu;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1532

if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1534

adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1540

pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1544

if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1545

pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1551

pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1555

if (adev->gfx.config.gc_tcc_size) {

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1556

pcache_info[i].cache_size = adev->gfx.config.gc_tcc_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1562

pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1573

pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2237

struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

103

struct amdgpu_gfx_config *gfx_info = &mm->dev->adev->gfx.config;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1796

struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

2043

struct amdgpu_gfx_config *gfx_info = &gpu->adev->gfx.config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11101

struct mod_freesync_config config = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11120

config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11121

config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11122

config.vsif_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11123

config.btr = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11126

config.state = VRR_STATE_ACTIVE_FIXED;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11127

config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11130

config.state = VRR_STATE_ACTIVE_VARIABLE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11132

config.state = VRR_STATE_INACTIVE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11135

config.state = VRR_STATE_UNSUPPORTED;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11138

new_crtc_state->freesync_config = config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13126

amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13127

amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2125

adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9100

struct drm_vblank_crtc_config config = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9130

config.offdelay_ms = offdelay ?: 30;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9143

config.offdelay_ms = offdelay ?: 30;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9146

config.offdelay_ms = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9147

config.disable_immediate = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9151

&config);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9466

struct mod_freesync_config config = new_crtc_state->freesync_config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9485

config.min_refresh_in_uhz &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9486

config.max_refresh_in_uhz) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9491

if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9494

vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9495

vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9496

vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9499

config.state = new_crtc_state->base.vrr_enabled ?

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9504

config.state = VRR_STATE_UNSUPPORTED;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9509

&config, &vrr_params);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9511

new_crtc_state->freesync_config = config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9513

acrtc->dm_irq_params.freesync_config = config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9654

if (pr->config.replay_supported && !pr->replay_feature_enabled)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9664

(psr->psr_feature_enabled || pr->config.replay_supported)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

159

(dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

315

pr->config.replay_supported;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

325

dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

326

sr_supported && vblank->config.disable_immediate)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1020

if (link->replay_settings.config.replay_supported) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1036

seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2679

seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3179

*val = adev->dm.dc->config.allow_edp_hotplug_detection;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3192

adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

219

psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

498

struct psp_context *psp = hdcp.config.psp.handle;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

526

static void update_config(void *handle, struct cp_psp_stream_config *config)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

529

struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

538

if (config->dpms_off) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

557

display->controller = CONTROLLER_ID_D0 + config->otg_inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

558

display->dig_fe = config->dig_fe;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

559

link->dig_be = config->dig_be;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

561

display->stream_enc_idx = config->stream_enc_idx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

562

link->link_enc_idx = config->link_enc_idx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

563

link->dio_output_id = config->dio_output_idx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

564

link->phy_idx = config->phy_idx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

570

link->dp.assr_enabled = config->assr_enabled;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

571

link->dp.mst_enabled = config->mst_enabled;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

572

link->dp.dp2_enabled = config->dp2_enabled;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

573

link->dp.usb4_enabled = config->usb4_enabled;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

656

if (!psp_set_srm(work->hdcp.config.psp.handle, work->srm_temp, pos + count, &srm_version)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

682

srm = psp_get_srm(work->hdcp.config.psp.handle, &srm_version, &srm_size);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

769

struct mod_hdcp_config *config = &hdcp_work[i].hdcp.config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

770

struct mod_hdcp_ddc_funcs *ddc_funcs = &config->ddc.funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

772

config->psp.handle = &adev->psp;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

783

config->psp.caps.dtm_v3_supported = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

785

config->ddc.handle = dc_get_link_at_index(dc, i);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

792

config->debug.lc_enable_sw_fallback = dc->debug.hdcp_lc_enable_sw_fallback;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

218

adev->gfx.config.gb_addr_config_fields.num_pipes;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

220

adev->gfx.config.gb_addr_config_fields.num_banks;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

222

adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

224

adev->gfx.config.gb_addr_config_fields.num_se;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

226

adev->gfx.config.gb_addr_config_fields.max_compress_frags;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

228

adev->gfx.config.gb_addr_config_fields.num_rb_per_se;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

231

tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

406

int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

453

int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

455

ilog2(adev->gfx.config.gb_addr_config_fields.num_se));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

457

ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

458

int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

459

ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

560

int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

561

int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

128

pr_config = &link->replay_settings.config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

86

if (link->replay_settings.config.replay_supported)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3055

if (ctx->dc->config.multi_mon_pp_mclk_switch)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1424

if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3104

else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3115

if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3116

info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

382

if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

321

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

157

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

756

if (ctx->dc->config.is_single_rank_dimm)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

778

if (ctx->dc->config.is_asymmetric_memory)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

301

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

1031

if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

811

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

843

if (dc->config.enable_auto_dpm_test_logs) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1512

if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1528

if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1540

if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1543

ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1546

ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

214

if (!dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

413

if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1157

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1244

if (dc->config.enable_auto_dpm_test_logs)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1049

dc->config = init_params->flags;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1551

if (dc->config.edp_not_connected) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1704

if (dc->config.use_pipe_ctx_sync_logic) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2078

if (!dc->config.set_pipe_unlock_order)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2413

if (res == DC_OK && dc->res_pool->funcs->link_encs_assign && !dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2588

struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),

sys/dev/pci/drm/amd/display/dc/core/dc.c

2591

if (!config)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2596

kfree(config);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2606

kfree(config);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2612

config->enable_output_from_mux = enable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2613

config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2616

gpio_result = dal_mux_setup_config(generic, config);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2621

kfree(config);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2626

kfree(config);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3744

if (stream->link->replay_settings.config.replay_supported)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4609

if (!dc->config.is_vmin_only_asic) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4630

if (!dc->config.is_vmin_only_asic)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5577

dc->config.disable_ips = disable_ips;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5598

if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5645

if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5738

if (!dc->config.dc_mode_clk_limit_support)

sys/dev/pci/drm/amd/display/dc/core/dc.c

935

!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

447

*color = sm_ver_colors[dc->config.smart_mux_version];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1478

if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2876

if (stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3754

if (!dc->config.allow_seamless_boot_optimization)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3941

if (dc->config.unify_link_enc_assignment && is_dio_encoder)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4852

if (!dc->config.disable_disp_pll_sharing)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4921

if (pipe_ctx_old->stream->ctx->dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5245

dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5523

if (pipe_ctx->link_res.dio_link_enc == NULL && dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

567

if (stream1->ctx->dc->config.vblank_alignment_dto_params &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

568

stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

594

if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

205

!new_stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dc.h

1706

struct dc_config config;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1020

if (pipe_ctx->stream->link->replay_settings.config.replay_supported)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1215

if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1266

if (dc->config.disable_ips == DMUB_IPS_ENABLE ||

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1267

dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1274

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1276

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1280

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1285

} else if (dc->config.disable_ips == DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1302

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_Z8_RETENTION) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1309

if (dc->config.disable_ips_rcg == DMUB_IPS_RCG_ENABLE) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1312

} else if (dc->config.disable_ips_rcg == DMUB_IPS0_RCG_DISABLE) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1314

} else if (dc->config.disable_ips_rcg == DMUB_IPS1_RCG_DISABLE) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1318

if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1320

} else if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_ALL) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1709

memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub_cmd_fams2_global_config));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1712

global_cmd->config.global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1713

global_cmd->config.global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1714

global_cmd->config.global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1733

memcpy(&stream_base_cmd->config,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1737

memcpy(&stream_sub_state_cmd->config,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1744

global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1745

global_cmd->config.global.features.bits.enable = enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1761

struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1765

memset(config, 0, sizeof(*config));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1772

cmd.ib_fams2_config.ib_data.size = sizeof(*config);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1776

config->global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1777

config->global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1778

config->global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1781

memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1787

memcpy(&config->stream_v1[i].base,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1789

sizeof(config->stream_v1[i].base));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1792

memcpy(&config->stream_v1[i].sub_state,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1794

sizeof(config->stream_v1[i].sub_state));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1798

config->global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1799

config->global.features.bits.enable = enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1881

cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

144

spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1163

struct replay_config config;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1206

clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1293

clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

382

const struct dc_config *config = &dmcu->ctx->dc->config;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

443

(config->disable_fractional_pwm == false) ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1277

enum csc_color_mode config,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1285

if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1358

enum csc_color_mode config =

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1365

configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1374

enum csc_color_mode config =

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1398

config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1408

configure_graphics_mode(xfm_dce, config,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

59

uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

167

copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

171

copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

172

copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

194

copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

195

if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

360

enum csc_color_mode config,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

375

if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

676

enum csc_color_mode config =

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

700

config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

713

configure_graphics_mode_v(xfm_dce, config,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

725

enum csc_color_mode config =

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

732

configure_graphics_mode_v(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

76

void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config)

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

79

VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_start_addr >> 32) & 0xF);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

81

VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, config->page_table_start_addr & 0xFFFFFFFF);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

84

VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_end_addr >> 32) & 0xF);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

86

VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, config->page_table_end_addr & 0xFFFFFFFF);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

89

VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

90

VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

93

VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

96

VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

75

void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

176

if (dcn31_panel_cntl->base.ctx->dc->config.support_edp0_on_dp1) {

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

307

if (!enc->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

322

if (!enc->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

336

if (!enc->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dm_cp_psp.h

52

void (*update_stream_config)(void *handle, struct cp_psp_stream_config *config);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

207

struct dc_panel_config *config,

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

211

struct dc_panel_config *config);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1309

if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1767

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

485

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

474

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

547

if (dc->config.forced_clocks || dc->debug.max_disp_clk) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

194

if (dc->config.use_default_clock_table == false) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

394

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

399

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1347

if (dc->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1948

if (dc->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2227

&& !dc->config.enable_windowed_mpo_odm

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2253

if (!dc->config.enable_windowed_mpo_odm)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2602

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3056

dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

614

dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

531

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

537

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

564

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

570

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

139

if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

140

stream->ctx->dc->config.enable_fpo_flicker_detection == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

141

timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

15

const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

20

pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

487

dml_ctx->config.callbacks.build_scaling_params(temp_pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

556

} else if ((plane_state->ctx->dc->config.use_spl == true) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

58

const struct dml2_configuration_options *config,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

624

plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

63

if (config->use_native_soc_bb_construction) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

64

in_dc->soc_and_ip_translator->translator_funcs->get_soc_bb(&dml_init->soc_bb, in_dc, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

67

dml_init->soc_bb = config->external_socbb_ip_params->soc_bb;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

68

dml_init->ip_caps = config->external_socbb_ip_params->ip_params;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

71

dml21_populate_pmo_options(&dml_init->options.pmo_options, in_dc, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

736

dml_dispcfg->gpuvm_enable = dml_ctx->config.gpuvm_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

787

if (dml_ctx->config.pmo.force_pstate_method_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

789

dml21_force_pstate_method_to_uclk_state_change_strategy(dml_ctx->config.pmo.force_pstate_method_values[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

20

void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

108

dc_main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, main_stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

109

dc_main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

118

num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc_main_pipes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

121

struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

123

num_pipes = dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

127

dc_phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

129

dc_phantom_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

137

dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &context->res_ctx, dc_phantom_pipes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

152

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

175

if (in_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, dc_pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

220

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

250

phantom_stream = dml_ctx->config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

273

dml_ctx->config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

287

phantom_plane = dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

315

dml_ctx->config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

334

main_stream = dml_ctx->config.callbacks.get_stream_from_id(context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

337

main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

403

dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

459

phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

463

phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

75

struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

77

*pipe_regs_idx = dml_ctx->config.callbacks.get_odm_slice_index(opp_head);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

80

*pipe_regs_idx += dml_ctx->config.callbacks.get_mpc_slice_index(pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

223

dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

224

dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

240

if (result && !dml_ctx->config.skip_hw_state_mapping) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

251

dml_ctx->config.callbacks.allocate_mcache(context, mcache_params);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

256

if (result && !dml_ctx->config.skip_hw_state_mapping) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

280

dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

281

dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

40

const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

42

dml_ctx->config = *config;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

46

dml_ctx->config.pmo.force_pstate_method_enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

466

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

468

dml21_init(in_dc, dml_ctx, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

48

dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

50

dml_ctx->config.pmo.force_pstate_method_enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

54

static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

59

dml21_populate_configuration_options(in_dc, dml_ctx, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

63

dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

70

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

76

dml21_init(in_dc, *dml_ctx, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

31

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

37

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12779

base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12794

base_programming->config.bits.min_ttu_vblank_usable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12799

base_programming->config.bits.min_ttu_vblank_usable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12815

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12825

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12839

base_programming->config.bits.clamp_vtotal_min = display_cfg->display_config.num_streams == 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12857

sub_programming->subvp.config.bits.is_multi_planar =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12859

sub_programming->subvp.config.bits.is_yuv420 =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12868

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

20

static double get_max_reserved_time_on_all_planes_with_stream_index(struct display_configuation_with_meta *config, unsigned int stream_index)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

25

for (unsigned int i = 0; i < config->display_config.num_planes; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

26

plane_descriptor = &config->display_config.plane_descriptors[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

37

static void set_reserved_time_on_all_planes_with_stream_index(struct display_configuation_with_meta *config, unsigned int stream_index, double reserved_time_us)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

41

for (unsigned int i = 0; i < config->display_config.num_planes; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

42

plane_descriptor = &config->display_config.plane_descriptors[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1003

result &= ctx->config.callbacks.update_pipes_for_stream_with_slice_count(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1006

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1050

if (ctx->config.map_dc_pipes_with_callbacks)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

113

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1157

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1161

if (!ctx->config.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1166

if (ctx->config.callbacks.build_test_pattern_params &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1170

ctx->config.callbacks.build_test_pattern_params(&state->res_ctx, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

129

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

148

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

357

find_preferred_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, preferred_pipe_candidates);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

360

find_last_resort_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, last_resort_pipe_candidates);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

375

for (i = ctx->config.dcn_pipe_count - 1; pipes_needed > 0 && i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

423

find_preferred_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, preferred_pipe_candidates);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

426

find_last_resort_pipe_candidates(existing_state, ctx->config.dcn_pipe_count, stream_id, last_resort_pipe_candidates);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

441

for (i = ctx->config.dcn_pipe_count - 1; pipes_needed > 0 && i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

588

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

706

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

749

ctx->config.callbacks.acquire_secondary_pipe_for_mpc_odm(ctx->config.callbacks.dc, state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

783

ctx->config.callbacks.acquire_secondary_pipe_for_mpc_odm(ctx->config.callbacks.dc, state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

809

if (ctx->config.svp_pstate.callbacks.get_stream_subvp_type(state, stream) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

814

main_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(state, stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

820

main_stream_status = ctx->config.callbacks.get_stream_status(state, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

871

if (ctx->config.svp_pstate.callbacks.get_stream_subvp_type(state, stream) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

875

main_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(state, stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

899

struct pipe_ctx *otg_master = ctx->config.callbacks.get_otg_master_for_stream(&state->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

904

return ctx->config.callbacks.get_odm_slice_count(otg_master);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

912

int dpp_pipe_count = ctx->config.callbacks.get_dpp_pipes_for_plane(plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

916

return ctx->config.callbacks.get_mpc_slice_count(dpp_pipes[0]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

967

result &= ctx->config.callbacks.update_pipes_for_plane_with_slice_count(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

970

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

974

result &= ctx->config.callbacks.update_pipes_for_stream_with_slice_count(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

977

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

996

result &= ctx->config.callbacks.update_pipes_for_plane_with_slice_count(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

999

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h

137

struct dml2_configuration_options config;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h

40

struct dml2_configuration_options *config;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

106

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

125

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

150

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

191

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

202

free_pipes = ctx->config.dcn_pipe_count - num_pipes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

237

for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

256

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_NONE && refresh_rate < 120 &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

312

unsigned int min_pipe_split = ctx->config.dcn_pipe_count + 1; // init as max number of pipes + 1

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

315

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

320

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

336

if (free_pipes >= min_pipe_split && free_pipes < ctx->config.dcn_pipe_count)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

367

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

375

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

376

phantom = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

383

ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

384

ctx->config.svp_pstate.subvp_fw_processing_delay_us + 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

448

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

457

if (ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

461

phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

466

ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

49

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

533

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

535

pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

54

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

556

phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, subvp_pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

56

mblk_width = ctx->config.mall_cfg.mblk_width_pixels;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

564

ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

57

mblk_height = bytes_per_pixel == 4 ? mblk_width = ctx->config.mall_cfg.mblk_height_4bpe_pixels : ctx->config.mall_cfg.mblk_height_8bpe_pixels;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

609

for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

611

enum mall_stream_type pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

664

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

675

pstate_width_fw_delay_lines = ((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

676

ctx->config.svp_pstate.subvp_pstate_allow_width_us) / 1000000) *

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

685

phantom_vactive = svp_height + pstate_width_fw_delay_lines + ctx->config.svp_pstate.subvp_swath_height_margin_lines;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

716

struct dc_stream_state *phantom_stream = ctx->config.svp_pstate.callbacks.create_phantom_stream(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

717

ctx->config.svp_pstate.callbacks.dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

727

ctx->config.svp_pstate.callbacks.add_phantom_stream(ctx->config.svp_pstate.callbacks.dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

747

phantom_plane = ctx->config.svp_pstate.callbacks.create_phantom_plane(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

748

ctx->config.svp_pstate.callbacks.dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

775

ctx->config.svp_pstate.callbacks.add_phantom_plane(ctx->config.svp_pstate.callbacks.dc, phantom_stream, phantom_plane, state);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

793

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

80

bytes_in_mall = num_mblks * ctx->config.mall_cfg.mblk_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

800

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

803

if (!ctx->config.svp_pstate.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

83

cache_lines_per_plane = bytes_in_mall / ctx->config.mall_cfg.cache_line_size_bytes + 2;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

832

if (!ctx->config.svp_pstate.callbacks.remove_phantom_plane(ctx->config.svp_pstate.callbacks.dc, stream, del_planes[i], context))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

834

ctx->config.svp_pstate.callbacks.release_phantom_plane(ctx->config.svp_pstate.callbacks.dc, context, del_planes[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

846

for (i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

849

if (pipe->plane_state && pipe->stream && ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

853

ctx->config.svp_pstate.callbacks.remove_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

854

ctx->config.svp_pstate.callbacks.release_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

879

if (ctx->config.svp_pstate.force_disable_subvp)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

890

for (int i = 0; i < ctx->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

896

ctx->config.svp_pstate.callbacks.build_scaling_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

92

total_cache_lines = ctx->config.mall_cfg.max_cab_allocation_bytes / ctx->config.mall_cfg.cache_line_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

93

lines_per_way = total_cache_lines / ctx->config.mall_cfg.cache_num_ways;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

198

out->max_num_dpp = dml2->config.dcn_pipe_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

199

out->max_num_otg = dml2->config.dcn_pipe_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

247

out->dprefclk_mhz = dml2->config.bbox_overrides.dprefclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

248

out->xtalclk_mhz = dml2->config.bbox_overrides.xtalclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

250

out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

274

out->dispclk_dppclk_vco_speed_mhz = dml2->config.bbox_overrides.disp_pll_vco_speed_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

275

out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64 or 32 MB;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

316

out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

320

if (dml2->config.bbox_overrides.dram_num_chan)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

321

out->num_chans = dml2->config.bbox_overrides.dram_num_chan;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

323

if (dml2->config.bbox_overrides.dram_chanel_width_bytes)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

324

out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

466

if (dml2->config.bbox_overrides.sr_exit_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

468

dml2->config.bbox_overrides.sr_exit_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

471

if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

473

dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

476

if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

478

dml2->config.bbox_overrides.sr_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

481

if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

483

dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

486

if (dml2->config.bbox_overrides.urgent_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

488

dml2->config.bbox_overrides.urgent_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

491

if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

493

dml2->config.bbox_overrides.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

496

if (dml2->config.bbox_overrides.fclk_change_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

498

dml2->config.bbox_overrides.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

520

if (dml2->config.bbox_overrides.clks_table.num_states) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

521

p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

522

for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

523

p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

526

p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

528

p->dcfclk_stas_mhz[4] = dml2->config.bbox_overrides.clks_table.clk_entries[i-1].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

530

for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

532

dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

535

for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

537

dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

540

for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

542

dml2->config.bbox_overrides.clks_table.clk_entries[i].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

545

for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

546

if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

548

dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

551

for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

553

dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

555

dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

63

out->max_num_dpp = dml2->config.dcn_pipe_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

64

out->max_num_otg = dml2->config.dcn_pipe_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

369

if (dc->config.forced_clocks || dc->debug.max_disp_clk) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

487

max_det_size = in_ctx->config.det_segment_size * in_ctx->config.max_segments_per_hubp;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

493

if (in_ctx->config.override_det_buffer_size_kbytes)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

494

dml_dispcfg->plane.DETSizeOverride[plane_index] = max_det_size / in_ctx->config.dcn_pipe_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

501

if (dml_dispcfg->plane.DETSizeOverride[plane_index] % in_ctx->config.det_segment_size != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

517

max_det_size = in_ctx->config.det_segment_size * in_ctx->config.max_segments_per_hubp;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

137

if (largest_blend_and_timing == 0 && p->cur_policy->ODMUse[0] == dml_odm_use_policy_combine_as_needed && dml2->config.minimize_dispclk_using_odm) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

138

odms_needed = dml2_util_get_maximum_odm_combine_for_output(dml2->config.optimize_odm_4to1,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

173

for (i = 0; i < dml2->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

182

if (!dml2->config.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

257

if (!ctx->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

281

for (i = 0; i < dml2->config.dcn_pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

290

if (!dml2->config.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

298

if (!dml2->config.skip_hw_state_mapping)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

313

s->optimize_configuration_params.config = &dml2->config;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

38

if (dml2->config.use_native_soc_bb_construction)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

440

if (result && !dml2->config.skip_hw_state_mapping)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

448

if (result && !dml2->config.skip_hw_state_mapping) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

453

if (!dml2->config.skip_hw_state_mapping) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

46

if (dml2->config.use_native_soc_bb_construction)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

465

if (in_dc->config.use_default_clock_table &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

479

if (!dml2->config.skip_hw_state_mapping) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

527

if (!dml2->config.skip_hw_state_mapping)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

544

dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

55

if (dml2->config.use_native_soc_bb_construction)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

581

static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

584

dml21_reinit(in_dc, *dml2, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

589

(*dml2)->config = *config;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

626

bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

630

return dml21_create(in_dc, dml2, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

638

dml2_init(in_dc, config, dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

695

const struct dml2_configuration_options *config,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

699

dml21_reinit(in_dc, *dml2, config);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

703

dml2_init(in_dc, config, dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

259

const struct dml2_configuration_options *config,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

268

const struct dml2_configuration_options *config,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1094

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1143

if (dpp->base.ctx->dc->config.prefer_easf)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1183

if (dpp->base.ctx->dc->config.prefer_easf)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

288

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

521

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

472

struct dc_dsc_config config = {0};

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

488

&options, link_encoding, min_dsc_slice_count, &config);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

492

config.num_slices_h, &dsc_common_caps, timing, link_encoding, range);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

171

void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

173

DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

174

DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

176

config->dc_dsc_cfg.bits_per_pixel,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

177

config->dc_dsc_cfg.bits_per_pixel / 16,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

178

((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

179

DC_LOG_DSC("\tcolor_depth %d", config->color_depth);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

573

const struct dsc_config *config);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

219

struct gpio_generic_mux_config *config)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

223

if (!config)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

226

config_data.config.generic_mux = *config;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

430

struct gpio_hpd_config *config)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

434

if (!config)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

438

config_data.config.hpd = *config;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

591

config_data.config.ddc.type = config_type;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

596

config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

597

config_data.config.ddc.clock_en_bit_present = hw_clock->store.en != 0;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

660

config_data.config.ddc.type = config_type;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

661

config_data.config.ddc.data_en_bit_present = false;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

662

config_data.config.ddc.clock_en_bit_present = false;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

139

if (config_data->config.ddc.data_en_bit_present ||

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

140

config_data->config.ddc.clock_en_bit_present)

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

89

switch (config_data->config.ddc.type) {

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

77

GENERIC_EN, config_data->config.generic_mux.enable_output_from_mux,

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

78

GENERIC_SEL, config_data->config.generic_mux.mux_select);

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

98

DC_HPD_CONNECT_INT_DELAY, config_data->config.hpd.delay_on_connect / 10,

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

99

DC_HPD_DISCONNECT_INT_DELAY, config_data->config.hpd.delay_on_disconnect / 10);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

135

if (!hubbub1->base.ctx->dc->config.skip_riommu_prefetch_wa) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1012

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1044

!link->dc->config.edp_no_power_sequencing &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1057

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1162

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1253

!link->dc->config.edp_no_power_sequencing) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1615

if (dc->config.disable_hbr_audio_dp2)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1622

if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1693

((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2463

if (dc->config.use_pipe_ctx_sync_logic)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2972

if (dc->config.gpu_vm_support)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

327

if (dc->config.gpu_vm_support)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1846

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2405

if (dc->config.vblank_alignment_dto_params &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2408

(dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2410

(dc->config.vblank_alignment_dto_params >> 48) & 0x7FFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2412

dc->config.vblank_alignment_dto_params & 0xFFFFFFFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2754

if (dc->config.gpu_vm_support)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2667

struct dcn_hubbub_virt_addr_config config;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2674

config.page_table_start_addr = va_config->page_table_start_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2675

config.page_table_end_addr = va_config->page_table_end_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2676

config.page_table_block_size = va_config->page_table_block_size_in_bytes;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2677

config.page_table_depth = va_config->page_table_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2678

config.page_table_base_addr = va_config->page_table_base_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2680

dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2685

struct dcn_hubbub_phys_addr_config config;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2687

config.system_aperture.fb_top = pa_config->system_aperture.fb_top;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2688

config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2689

config.system_aperture.fb_base = pa_config->system_aperture.fb_base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2690

config.system_aperture.agp_top = pa_config->system_aperture.agp_top;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2691

config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2692

config.system_aperture.agp_base = pa_config->system_aperture.agp_base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2693

config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2694

config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2695

config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2696

config.page_table_default_page_addr = pa_config->page_table_default_page_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2698

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3038

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

52

static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

63

config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

69

struct dcn_hubbub_phys_addr_config config = {0};

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

71

config.system_aperture.fb_top = pa_config->system_aperture.fb_top;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

72

config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

73

config.system_aperture.fb_base = pa_config->system_aperture.fb_base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

74

config.system_aperture.agp_top = pa_config->system_aperture.agp_top;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

75

config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

76

config.system_aperture.agp_base = pa_config->system_aperture.agp_base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

77

config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

78

config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

79

config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

81

mmhub_update_page_table_config(&config, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

83

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

663

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

733

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

745

if (!dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

190

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

489

struct dcn_hubbub_phys_addr_config config = {0};

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

491

config.system_aperture.fb_top = pa_config->system_aperture.fb_top;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

492

config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

493

config.system_aperture.fb_base = pa_config->system_aperture.fb_base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

494

config.system_aperture.agp_top = pa_config->system_aperture.agp_top;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

495

config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

496

config.system_aperture.agp_base = pa_config->system_aperture.agp_base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

497

config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

498

config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

502

config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

506

config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

508

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

585

((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

656

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

77

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

869

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

900

if (!dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

982

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

983

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1431

dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

222

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

310

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

311

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

83

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

238

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

269

if (!dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

351

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

352

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

962

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/inc/soc_and_ip_translator.h

12

void (*get_soc_bb)(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

127

if (link->dc->config.disable_hbr_audio_dp2 &&

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

160

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

187

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

205

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

223

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

239

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

330

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

54

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

84

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

132

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

128

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

132

if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

167

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

44

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

69

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

95

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

99

if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1256

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1282

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

825

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

840

!link->dc->config.enable_dpia_pre_training)) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

895

(!link->dc->config.allow_edp_hotplug_detection)) &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

959

if (dc->config.enable_mipi_converter_optimization &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

964

dc->config.edp_no_power_sequencing = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2071

!link->dc->config.enable_dpia_pre_training)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2090

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2490

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

666

struct cp_psp_stream_config config = {0};

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

672

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

679

config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

682

config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

685

config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

687

config.stream_enc_idx =

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

691

config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

694

config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

696

config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

700

config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

702

config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

706

config.phy_idx = resource_transmitter_to_phy_idx(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

710

config.phy_idx = 0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

713

config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

714

config.mst_enabled = (pipe_ctx->stream->signal ==

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

716

config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

717

config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

719

config.dpms_off = dpms_off;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

722

config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

724

cp_psp->funcs.update_stream_config(cp_psp->handle, &config);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

751

struct dsc_optc_config *config)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

754

uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

755

uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

767

config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

768

DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

769

DC_LOG_DSC("\tslice_width %d", config->slice_width);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

546

if (!(!link->dc->config.smart_mux_version || dc_ctx->dc_edp_id_count == 0))

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

552

if (!link->dc->config.allow_edp_hotplug_detection

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

556

switch (link->dc->config.allow_edp_hotplug_detection) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2218

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2252

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

347

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

230

link->replay_settings.config.replay_error_status.raw |= replay_error_status.raw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

236

if (link->replay_settings.config.force_disable_desync_error_check)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

450

!link->dc->config.enable_dpia_pre_training)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

149

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

184

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1680

if (!link->dc->config.consolidated_dpia_dp_lt && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1734

!link->dc->config.enable_dpia_pre_training) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

813

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

174

if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

967

if (!link->dc->config.consolidated_dpia_dp_lt)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1011

if (!(link->replay_settings.config.replay_supported))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1014

link->replay_settings.config.replay_error_status.raw = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1048

replay_context.os_request_force_ffu = link->replay_settings.config.os_request_force_ffu;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1056

link->replay_settings.config.replay_timing_sync_supported;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1063

alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1065

if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1078

link->replay_settings.config.replay_video_conferencing_optimization_enabled = false;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1232

if (!link->dc->config.smart_mux_version)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1247

if (!pDC->config.use_assr_psp_message)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1284

if (link->dc->config.use_assr_psp_message) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

414

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

433

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

222

struct gpio_hpd_config config;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

224

config.delay_on_connect = delay_on_connect_in_ms;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

225

config.delay_on_disconnect = delay_on_disconnect_in_ms;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

227

dal_irq_setup_hpd_filter(hpd, &config);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

80

struct gpio_hpd_config config;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

82

config.delay_on_connect = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

83

config.delay_on_disconnect = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

85

dal_irq_setup_hpd_filter(hpd, &config);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1504

if (dc->config.fbc_support)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1473

if (!dc->config.is_vmin_only_asic)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1485

dc->config.is_vmin_only_asic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1232

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1900

&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1517

if (!dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1531

if (dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1541

if (dc->config.disable_dmcu)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

747

if (pool->base.abm->ctx->dc->config.disable_dmcu)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1511

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1699

if (!dc->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

968

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1220

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

913

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1703

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1707

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1915

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1963

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1964

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1844

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1896

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1788

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1792

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1884

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1673

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1677

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1760

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1930

if (dc->config.enable_windowed_mpo_odm &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2233

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2280

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2282

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2283

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2284

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2551

if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2552

dc->config.sdpif_request_limit_words_per_umc = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2808

if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

477

if (fpo_candidate_stream->ctx->dc->config.enable_fpo_flicker_detection == 1 &&

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1780

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1782

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1783

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1784

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1863

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1930

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1933

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2180

if (dc->config.EnableMinDispClkODM)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2182

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2191

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2192

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1836

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1899

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1903

dc->config.use_assr_psp_message = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2153

if (dc->config.EnableMinDispClkODM)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2155

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2164

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2165

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1836

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1903

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1905

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2153

if (dc->config.EnableMinDispClkODM)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2155

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2164

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2165

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1705

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1956

dc->config.use_spl = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1957

dc->config.prefer_easf = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1959

dc->config.dcn_sharpness_range.sdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1960

dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1961

dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1962

dc->config.dcn_sharpness_range.sdr_yuv_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1963

dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1964

dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1965

dc->config.dcn_sharpness_range.hdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1966

dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1967

dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1969

dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1970

dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1971

dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1972

dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1973

dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1974

dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1975

dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1976

dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1977

dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1979

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1980

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1981

dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2213

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2214

dc->config.sdpif_request_limit_words_per_umc = 16;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

209

void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

219

config->use_clock_dc_limits);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

271

static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

278

dcn401_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc, config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

283

void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

288

apply_soc_bb_updates(soc_bb, dc, config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

17

void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

18

void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1975

} config;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2205

} config;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2238

} config;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2290

} config;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2322

} config;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2391

union dmub_cmd_fams2_config config;

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

64

struct gpio_generic_mux_config *config);

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

94

struct gpio_hpd_config *config);

sys/dev/pci/drm/amd/display/include/gpio_types.h

329

} config;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

291

struct mod_hdcp_config *config)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

297

hdcp->config = *config;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

200

struct mod_hdcp_config config;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_execution.c

500

const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_execution.c

501

&& hdcp->config.ddc.funcs.atomic_write_poll_read_aux

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

188

const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

203

if (use_fw && hdcp->config.debug.lc_enable_sw_fallback) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

514

const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_aux

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

524

if (use_fw && hdcp->config.debug.lc_enable_sw_fallback) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

172

success = hdcp->config.ddc.funcs.read_dpcd(hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

188

success = hdcp->config.ddc.funcs.read_i2c(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

189

hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

243

success = hdcp->config.ddc.funcs.write_dpcd(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

244

hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

262

success = hdcp->config.ddc.funcs.write_i2c(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

263

hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

685

return hdcp->config.ddc.funcs.write_dpcd(hdcp->config.ddc.handle, cp_irq_addrs,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

710

return hdcp->config.ddc.funcs.atomic_write_poll_read_aux(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

711

hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

747

return hdcp->config.ddc.funcs.atomic_write_poll_read_i2c(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

748

hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

106

hdcp->config.index, msg_name,\

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

111

hdcp->config.index, i)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

114

hdcp->config.index, i)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

117

hdcp->config.index)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

120

hdcp->config.index)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

122

HDCP_LOG_TOP(hdcp, "[Link %d]\treset authentication", hdcp->config.index)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

124

HDCP_LOG_TOP(hdcp, "[Link %d]\treset connection", hdcp->config.index)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

127

HDCP_LOG_TOP(hdcp, "[Link %d] %s", hdcp->config.index, __func__); \

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

131

HDCP_LOG_TOP(hdcp, "[Link %d] %s display %d", hdcp->config.index, __func__, i); \

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

39

hdcp->config.index, \

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

46

hdcp->config.index, displayIndex)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

50

hdcp->config.index, displayIndex)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

54

hdcp->config.index, displayIndex)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

58

hdcp->config.index, displayIndex)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

64

hdcp->config.index, displayIndex)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

68

hdcp->config.index, str)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

72

hdcp->config.index, str)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

77

hdcp->config.index, \

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

81

"[Link %d] > %s", hdcp->config.index, \

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

85

HDCP_LOG_FSM(hdcp, "[Link %d] --> TIMEOUT", hdcp->config.index)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

87

HDCP_LOG_FSM(hdcp, "[Link %d] --> CPIRQ", hdcp->config.index)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.h

99

HDCP_LOG_DDC(hdcp, "[Link %d] Read %s%s", hdcp->config.index, \

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

125

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

172

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

229

if (hdcp->config.psp.caps.dtm_v3_supported)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

242

if (hdcp->config.psp.caps.dtm_v3_supported)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

253

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

295

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

328

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

369

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

399

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

441

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

477

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

503

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

51

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

550

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

583

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

615

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

675

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

721

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

754

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

789

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

834

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

865

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

87

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

918

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

962

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

998

struct psp_context *psp = hdcp->config.psp.handle;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

318

struct mod_hdcp_config *config);

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

152

else if (stream->link->replay_settings.config.replay_supported)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

697

struct abm_config_table config;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

706

memset(&config, 0, sizeof(config));

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

712

config.crgb_thresh[i] = ram_table.crgb_thresh[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

713

config.crgb_offset[i] = ram_table.crgb_offset[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

714

config.crgb_slope[i] = ram_table.crgb_slope[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

718

config.backlight_thresholds[i] = ram_table.backlight_thresholds[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

719

config.backlight_offsets[i] = ram_table.backlight_offsets[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

723

config.iir_curve[i] = ram_table.iir_curve[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

727

config.min_reduction[i][j] = ram_table.min_reduction[i][j];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

728

config.max_reduction[i][j] = ram_table.max_reduction[i][j];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

729

config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

730

config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

735

config.hybrid_factor[i] = ram_table.hybrid_factor[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

736

config.contrast_factor[i] = ram_table.contrast_factor[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

737

config.deviation_gain[i] = ram_table.deviation_gain[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

738

config.min_knee[i] = ram_table.min_knee[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

739

config.max_knee[i] = ram_table.max_knee[i];

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

744

config.blRampReduction[i] = params.backlight_ramping_reduction;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

745

config.blRampStart[i] = params.backlight_ramping_start;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

749

config.blRampReduction[i] = abm_settings[set][i].blRampReduction;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

750

config.blRampStart[i] = abm_settings[set][i].blRampStart;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

754

config.min_abm_backlight = ram_table.min_abm_backlight;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

758

res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

761

res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

935

link->replay_settings.config = *pr_config;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

945

struct psr_config *config)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

950

config->dsc_slice_height = 0;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

965

config->dsc_slice_height = slice_height;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

968

if (config->su_y_granularity &&

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

969

(slice_height % config->su_y_granularity)) {

sys/dev/pci/drm/amd/display/modules/power/power_helpers.h

77

struct psr_config *config);

sys/dev/pci/drm/amd/include/atomfirmware.h

4445

uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

966

num_se = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1001

num_se = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1049

num_se = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

889

num_se = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

940

num_se = adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1914

uint16_t config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1916

config = VR_SVI2_PLANE_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1917

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1920

config = VR_SVI2_PLANE_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1921

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1927

config = VR_SVI2_PLANE_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1928

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1930

config = VR_SMIO_PATTERN_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1931

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1935

config = VR_SMIO_PATTERN_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1936

table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1821

uint16_t config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1823

config = VR_MERGED_WITH_VDDC;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1824

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1828

config = VR_SVI2_PLANE_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1829

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1837

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1838

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1840

config = VR_SMIO_PATTERN_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1841

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1843

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1844

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1848

config = VR_SVI2_PLANE_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1849

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1851

config = VR_SMIO_PATTERN_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1852

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1854

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1855

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1716

uint16_t config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1718

config = VR_MERGED_WITH_VDDC;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1719

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1723

config = VR_SVI2_PLANE_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1724

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1726

config = VR_SMIO_PATTERN_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1727

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1735

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1736

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1738

config = VR_SMIO_PATTERN_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1739

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1741

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1742

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1746

if (config != VR_SVI2_PLANE_2) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1747

config = VR_SVI2_PLANE_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1748

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1752

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1753

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1756

config = VR_SMIO_PATTERN_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1757

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1761

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1762

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1750

uint16_t config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1754

config = VR_SVI2_PLANE_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1755

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1758

config = VR_SVI2_PLANE_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1759

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1766

config = VR_MERGED_WITH_VDDC;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1767

table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1771

config = VR_SVI2_PLANE_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1772

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1781

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1782

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1784

config = VR_SMIO_PATTERN_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1785

table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1790

config = VR_SMIO_PATTERN_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1791

table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1673

uint16_t config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1675

config = VR_MERGED_WITH_VDDC;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1676

table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1680

config = VR_SVI2_PLANE_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1681

table->VRConfig |= config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1689

config = VR_SVI2_PLANE_2; /* only in merged mode */

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1690

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1692

config = VR_SMIO_PATTERN_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1693

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1695

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1696

table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1700

if (config != VR_SVI2_PLANE_2) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1701

config = VR_SVI2_PLANE_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1702

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1711

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1712

table->VRConfig = (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1715

config = VR_SMIO_PATTERN_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1716

table->VRConfig = (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1723

config = VR_STATIC_VOLTAGE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1724

table->VRConfig |= (config << VRCONF_MVDD_SHIFT);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2225

uint32_t total_cu = adev->gfx.config.max_cu_per_sh *

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2226

adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2255

aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;

sys/dev/pci/drm/display/drm_scdc_helper.c

186

u8 config;

sys/dev/pci/drm/display/drm_scdc_helper.c

189

ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);

sys/dev/pci/drm/display/drm_scdc_helper.c

198

config |= SCDC_SCRAMBLING_ENABLE;

sys/dev/pci/drm/display/drm_scdc_helper.c

200

config &= ~SCDC_SCRAMBLING_ENABLE;

sys/dev/pci/drm/display/drm_scdc_helper.c

202

ret = drm_scdc_writeb(connector->ddc, SCDC_TMDS_CONFIG, config);

sys/dev/pci/drm/display/drm_scdc_helper.c

246

u8 config;

sys/dev/pci/drm/display/drm_scdc_helper.c

249

ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);

sys/dev/pci/drm/display/drm_scdc_helper.c

258

config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;

sys/dev/pci/drm/display/drm_scdc_helper.c

260

config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;

sys/dev/pci/drm/display/drm_scdc_helper.c

262

ret = drm_scdc_writeb(connector->ddc, SCDC_TMDS_CONFIG, config);

sys/dev/pci/drm/drm_atomic.c

1137

struct drm_mode_config *config = &connector->dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

1142

ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx);

sys/dev/pci/drm/drm_atomic.c

1150

int alloc = max(index + 1, config->num_connector);

sys/dev/pci/drm/drm_atomic.c

1374

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

1385

ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx);

sys/dev/pci/drm/drm_atomic.c

1473

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

1520

if (config->funcs->atomic_check) {

sys/dev/pci/drm/drm_atomic.c

1521

ret = config->funcs->atomic_check(state->dev, state);

sys/dev/pci/drm/drm_atomic.c

1583

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

1596

return config->funcs->atomic_commit(state->dev, state, false);

sys/dev/pci/drm/drm_atomic.c

1616

struct drm_mode_config *config = &state->dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

1625

return config->funcs->atomic_commit(state->dev, state, true);

sys/dev/pci/drm/drm_atomic.c

168

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

170

if (!config->funcs->atomic_state_alloc) {

sys/dev/pci/drm/drm_atomic.c

183

return config->funcs->atomic_state_alloc(dev);

sys/dev/pci/drm/drm_atomic.c

1854

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

1864

list_for_each_entry(plane, &config->plane_list, head) {

sys/dev/pci/drm/drm_atomic.c

1872

list_for_each_entry(crtc, &config->crtc_list, head) {

sys/dev/pci/drm/drm_atomic.c

1889

list_for_each_entry(obj, &config->privobj_list, head) {

sys/dev/pci/drm/drm_atomic.c

198

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

218

for (i = 0; i < config->num_crtc; i++) {

sys/dev/pci/drm/drm_atomic.c

238

for (i = 0; i < config->num_total_plane; i++) {

sys/dev/pci/drm/drm_atomic.c

288

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

290

if (config->funcs->atomic_state_clear)

sys/dev/pci/drm/drm_atomic.c

291

config->funcs->atomic_state_clear(state);

sys/dev/pci/drm/drm_atomic.c

308

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic.c

314

if (config->funcs->atomic_state_free) {

sys/dev/pci/drm/drm_atomic.c

315

config->funcs->atomic_state_free(state);

sys/dev/pci/drm/drm_atomic_uapi.c

1072

struct drm_mode_config *config = &plane->dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

1088

if (ret && prop != config->prop_fb_id &&

sys/dev/pci/drm/drm_atomic_uapi.c

1089

prop != config->prop_in_fence_fd &&

sys/dev/pci/drm/drm_atomic_uapi.c

1090

prop != config->prop_fb_damage_clips) {

sys/dev/pci/drm/drm_atomic_uapi.c

373

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

377

if (property == config->prop_active)

sys/dev/pci/drm/drm_atomic_uapi.c

379

else if (property == config->prop_mode_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

385

} else if (property == config->prop_vrr_enabled) {

sys/dev/pci/drm/drm_atomic_uapi.c

387

} else if (property == config->degamma_lut_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

395

} else if (property == config->ctm_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

403

} else if (property == config->gamma_lut_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

411

} else if (property == config->prop_out_fence_ptr) {

sys/dev/pci/drm/drm_atomic_uapi.c

442

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

444

if (property == config->prop_active)

sys/dev/pci/drm/drm_atomic_uapi.c

446

else if (property == config->prop_mode_id)

sys/dev/pci/drm/drm_atomic_uapi.c

448

else if (property == config->prop_vrr_enabled)

sys/dev/pci/drm/drm_atomic_uapi.c

450

else if (property == config->degamma_lut_property)

sys/dev/pci/drm/drm_atomic_uapi.c

452

else if (property == config->ctm_property)

sys/dev/pci/drm/drm_atomic_uapi.c

454

else if (property == config->gamma_lut_property)

sys/dev/pci/drm/drm_atomic_uapi.c

456

else if (property == config->prop_out_fence_ptr)

sys/dev/pci/drm/drm_atomic_uapi.c

478

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

482

if (property == config->prop_fb_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

489

} else if (property == config->prop_in_fence_fd) {

sys/dev/pci/drm/drm_atomic_uapi.c

500

} else if (property == config->prop_crtc_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

510

} else if (property == config->prop_crtc_x) {

sys/dev/pci/drm/drm_atomic_uapi.c

512

} else if (property == config->prop_crtc_y) {

sys/dev/pci/drm/drm_atomic_uapi.c

514

} else if (property == config->prop_crtc_w) {

sys/dev/pci/drm/drm_atomic_uapi.c

516

} else if (property == config->prop_crtc_h) {

sys/dev/pci/drm/drm_atomic_uapi.c

518

} else if (property == config->prop_src_x) {

sys/dev/pci/drm/drm_atomic_uapi.c

520

} else if (property == config->prop_src_y) {

sys/dev/pci/drm/drm_atomic_uapi.c

522

} else if (property == config->prop_src_w) {

sys/dev/pci/drm/drm_atomic_uapi.c

524

} else if (property == config->prop_src_h) {

sys/dev/pci/drm/drm_atomic_uapi.c

544

} else if (property == config->prop_fb_damage_clips) {

sys/dev/pci/drm/drm_atomic_uapi.c

590

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

592

if (property == config->prop_fb_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

594

} else if (property == config->prop_in_fence_fd) {

sys/dev/pci/drm/drm_atomic_uapi.c

596

} else if (property == config->prop_crtc_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

598

} else if (property == config->prop_crtc_x) {

sys/dev/pci/drm/drm_atomic_uapi.c

600

} else if (property == config->prop_crtc_y) {

sys/dev/pci/drm/drm_atomic_uapi.c

602

} else if (property == config->prop_crtc_w) {

sys/dev/pci/drm/drm_atomic_uapi.c

604

} else if (property == config->prop_crtc_h) {

sys/dev/pci/drm/drm_atomic_uapi.c

606

} else if (property == config->prop_src_x) {

sys/dev/pci/drm/drm_atomic_uapi.c

608

} else if (property == config->prop_src_y) {

sys/dev/pci/drm/drm_atomic_uapi.c

610

} else if (property == config->prop_src_w) {

sys/dev/pci/drm/drm_atomic_uapi.c

612

} else if (property == config->prop_src_h) {

sys/dev/pci/drm/drm_atomic_uapi.c

626

} else if (property == config->prop_fb_damage_clips) {

sys/dev/pci/drm/drm_atomic_uapi.c

676

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

680

if (property == config->prop_crtc_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

690

} else if (property == config->dpms_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

699

} else if (property == config->tv_select_subconnector_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

701

} else if (property == config->tv_subconnector_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

703

} else if (property == config->tv_left_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

705

} else if (property == config->tv_right_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

707

} else if (property == config->tv_top_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

709

} else if (property == config->tv_bottom_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

711

} else if (property == config->legacy_tv_mode_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

713

} else if (property == config->tv_mode_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

715

} else if (property == config->tv_brightness_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

717

} else if (property == config->tv_contrast_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

719

} else if (property == config->tv_flicker_reduction_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

721

} else if (property == config->tv_overscan_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

723

} else if (property == config->tv_saturation_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

725

} else if (property == config->tv_hue_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

727

} else if (property == config->link_status_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

741

} else if (property == config->hdr_output_metadata_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

748

} else if (property == config->aspect_ratio_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

750

} else if (property == config->content_type_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

754

} else if (property == config->content_protection_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

760

} else if (property == config->hdcp_content_type_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

764

} else if (property == config->writeback_fb_id_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

773

} else if (property == config->writeback_out_fence_ptr_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

804

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

806

if (property == config->prop_crtc_id) {

sys/dev/pci/drm/drm_atomic_uapi.c

808

} else if (property == config->dpms_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

813

} else if (property == config->tv_select_subconnector_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

815

} else if (property == config->tv_subconnector_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

817

} else if (property == config->tv_left_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

819

} else if (property == config->tv_right_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

821

} else if (property == config->tv_top_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

823

} else if (property == config->tv_bottom_margin_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

825

} else if (property == config->legacy_tv_mode_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

827

} else if (property == config->tv_mode_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

829

} else if (property == config->tv_brightness_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

831

} else if (property == config->tv_contrast_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

833

} else if (property == config->tv_flicker_reduction_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

835

} else if (property == config->tv_overscan_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

837

} else if (property == config->tv_saturation_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

839

} else if (property == config->tv_hue_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

841

} else if (property == config->link_status_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

843

} else if (property == config->aspect_ratio_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

845

} else if (property == config->content_type_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

851

} else if (property == config->hdr_output_metadata_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

854

} else if (property == config->content_protection_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

856

} else if (property == config->hdcp_content_type_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

858

} else if (property == config->writeback_fb_id_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

861

} else if (property == config->writeback_out_fence_ptr_property) {

sys/dev/pci/drm/drm_color_mgmt.c

172

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_color_mgmt.c

176

config->degamma_lut_property, 0);

sys/dev/pci/drm/drm_color_mgmt.c

178

config->degamma_lut_size_property,

sys/dev/pci/drm/drm_color_mgmt.c

184

config->ctm_property, 0);

sys/dev/pci/drm/drm_color_mgmt.c

188

config->gamma_lut_property, 0);

sys/dev/pci/drm/drm_color_mgmt.c

190

config->gamma_lut_size_property,

sys/dev/pci/drm/drm_connector.c

1072

struct drm_mode_config *config = &conn->dev->mode_config;

sys/dev/pci/drm/drm_connector.c

1074

lockdep_assert_held(&config->connector_list_lock);

sys/dev/pci/drm/drm_connector.c

1079

llist_add(&conn->free_node, &config->connector_free_list);

sys/dev/pci/drm/drm_connector.c

1080

schedule_work(&config->connector_free_work);

sys/dev/pci/drm/drm_connector.c

1094

struct drm_mode_config *config = &iter->dev->mode_config;

sys/dev/pci/drm/drm_connector.c

1098

spin_lock_irqsave(&config->connector_list_lock, flags);

sys/dev/pci/drm/drm_connector.c

1099

lhead = old_conn ? &old_conn->head : &config->connector_list;

sys/dev/pci/drm/drm_connector.c

1102

if (lhead->next == &config->connector_list) {

sys/dev/pci/drm/drm_connector.c

1115

spin_unlock_irqrestore(&config->connector_list_lock, flags);

sys/dev/pci/drm/drm_connector.c

1132

struct drm_mode_config *config = &iter->dev->mode_config;

sys/dev/pci/drm/drm_connector.c

1137

spin_lock_irqsave(&config->connector_list_lock, flags);

sys/dev/pci/drm/drm_connector.c

1139

spin_unlock_irqrestore(&config->connector_list_lock, flags);

sys/dev/pci/drm/drm_connector.c

210

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_connector.c

214

spin_lock_irqsave(&config->connector_list_lock, flags);

sys/dev/pci/drm/drm_connector.c

215

freed = llist_del_all(&config->connector_free_list);

sys/dev/pci/drm/drm_connector.c

216

spin_unlock_irqrestore(&config->connector_list_lock, flags);

sys/dev/pci/drm/drm_connector.c

230

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_connector.c

250

ret = ida_alloc_max(&config->connector_ida, 31, GFP_KERNEL);

sys/dev/pci/drm/drm_connector.c

303

config->dpms_property, 0);

sys/dev/pci/drm/drm_connector.c

306

config->link_status_property,

sys/dev/pci/drm/drm_connector.c

310

config->non_desktop_property,

sys/dev/pci/drm/drm_connector.c

313

config->tile_property,

sys/dev/pci/drm/drm_connector.c

317

drm_object_attach_property(&connector->base, config->prop_crtc_id, 0);

sys/dev/pci/drm/drm_connector.c

326

ida_free(&config->connector_ida, connector->index);

sys/dev/pci/drm/drm_connector.c

337

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_connector.c

342

spin_lock_irq(&config->connector_list_lock);

sys/dev/pci/drm/drm_connector.c

343

list_add_tail(&connector->head, &config->connector_list);

sys/dev/pci/drm/drm_connector.c

344

config->num_connector++;

sys/dev/pci/drm/drm_connector.c

345

spin_unlock_irq(&config->connector_list_lock);

sys/dev/pci/drm/drm_connector.c

650

struct drm_mode_config *config = &connector->dev->mode_config;

sys/dev/pci/drm/drm_connector.c

653

config->edid_property,

sys/dev/pci/drm/drm_crtc.c

241

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_crtc.c

248

if (WARN_ON(config->num_crtc >= 32))

sys/dev/pci/drm/drm_crtc.c

269

crtc->name = kasprintf(GFP_KERNEL, "crtc-%d", config->num_crtc);

sys/dev/pci/drm/drm_crtc.c

283

list_add_tail(&crtc->head, &config->crtc_list);

sys/dev/pci/drm/drm_crtc.c

284

crtc->index = config->num_crtc++;

sys/dev/pci/drm/drm_crtc.c

300

drm_object_attach_property(&crtc->base, config->prop_active, 0);

sys/dev/pci/drm/drm_crtc.c

301

drm_object_attach_property(&crtc->base, config->prop_mode_id, 0);

sys/dev/pci/drm/drm_crtc.c

303

config->prop_out_fence_ptr, 0);

sys/dev/pci/drm/drm_crtc.c

305

config->prop_vrr_enabled, 0);

sys/dev/pci/drm/drm_crtc.c

695

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_crtc.c

824

if (crtc_req->count_connectors > config->num_connector) {

sys/dev/pci/drm/drm_fb_helper.c

1649

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_fb_helper.c

1662

if (sizes->surface_height > config->max_height) {

sys/dev/pci/drm/drm_fb_helper.c

1664

config->max_height);

sys/dev/pci/drm/drm_fb_helper.c

1665

sizes->surface_height = config->max_height;

sys/dev/pci/drm/drm_framebuffer.c

264

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_framebuffer.c

274

if ((config->min_width > r->width) || (r->width > config->max_width)) {

sys/dev/pci/drm/drm_framebuffer.c

276

r->width, config->min_width, config->max_width);

sys/dev/pci/drm/drm_framebuffer.c

279

if ((config->min_height > r->height) || (r->height > config->max_height)) {

sys/dev/pci/drm/drm_framebuffer.c

281

r->height, config->min_height, config->max_height);

sys/dev/pci/drm/drm_modeset_lock.c

147

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_modeset_lock.c

159

mutex_lock(&config->mutex);

sys/dev/pci/drm/drm_modeset_lock.c

177

WARN_ON(config->acquire_ctx);

sys/dev/pci/drm/drm_modeset_lock.c

183

config->acquire_ctx = ctx;

sys/dev/pci/drm/drm_modeset_lock.c

205

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_modeset_lock.c

206

struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;

sys/dev/pci/drm/drm_modeset_lock.c

211

config->acquire_ctx = NULL;

sys/dev/pci/drm/drm_plane.c

1657

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_plane.c

1659

drm_object_attach_property(&plane->base, config->prop_fb_damage_clips,

sys/dev/pci/drm/drm_plane.c

1703

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_plane.c

1707

config->prop_fb_damage_clips->base.id))

sys/dev/pci/drm/drm_plane.c

1804

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_plane.c

1817

drm_object_attach_property(&plane->base, config->size_hints_property,

sys/dev/pci/drm/drm_plane.c

370

struct drm_mode_config *config = &dev->mode_config;

sys/dev/pci/drm/drm_plane.c

379

if (WARN_ON(config->num_total_plane >= 32))

sys/dev/pci/drm/drm_plane.c

423

drm_WARN_ON(dev, config->fb_modifiers_not_supported &&

sys/dev/pci/drm/drm_plane.c

458

list_add_tail(&plane->head, &config->plane_list);

sys/dev/pci/drm/drm_plane.c

459

plane->index = config->num_total_plane++;

sys/dev/pci/drm/drm_plane.c

462

config->plane_type_property,

sys/dev/pci/drm/drm_plane.c

466

drm_object_attach_property(&plane->base, config->prop_fb_id, 0);

sys/dev/pci/drm/drm_plane.c

467

drm_object_attach_property(&plane->base, config->prop_in_fence_fd, -1);

sys/dev/pci/drm/drm_plane.c

468

drm_object_attach_property(&plane->base, config->prop_crtc_id, 0);

sys/dev/pci/drm/drm_plane.c

469

drm_object_attach_property(&plane->base, config->prop_crtc_x, 0);

sys/dev/pci/drm/drm_plane.c

470

drm_object_attach_property(&plane->base, config->prop_crtc_y, 0);

sys/dev/pci/drm/drm_plane.c

471

drm_object_attach_property(&plane->base, config->prop_crtc_w, 0);

sys/dev/pci/drm/drm_plane.c

472

drm_object_attach_property(&plane->base, config->prop_crtc_h, 0);

sys/dev/pci/drm/drm_plane.c

473

drm_object_attach_property(&plane->base, config->prop_src_x, 0);

sys/dev/pci/drm/drm_plane.c

474

drm_object_attach_property(&plane->base, config->prop_src_y, 0);

sys/dev/pci/drm/drm_plane.c

475

drm_object_attach_property(&plane->base, config->prop_src_w, 0);

sys/dev/pci/drm/drm_plane.c

476

drm_object_attach_property(&plane->base, config->prop_src_h, 0);

sys/dev/pci/drm/drm_plane.c

488

config->modifiers_property,

sys/dev/pci/drm/drm_plane.c

497

config->async_modifiers_property,

sys/dev/pci/drm/drm_vblank.c

1246

int vblank_offdelay = vblank->config.offdelay_ms;

sys/dev/pci/drm/drm_vblank.c

1260

else if (!vblank->config.disable_immediate)

sys/dev/pci/drm/drm_vblank.c

1499

const struct drm_vblank_crtc_config *config)

sys/dev/pci/drm/drm_vblank.c

1512

vblank->config = *config;

sys/dev/pci/drm/drm_vblank.c

1526

if (atomic_read(&vblank->refcount) != 0 || !vblank->config.offdelay_ms)

sys/dev/pci/drm/drm_vblank.c

1546

const struct drm_vblank_crtc_config config = {

sys/dev/pci/drm/drm_vblank.c

1551

drm_crtc_vblank_on_config(crtc, &config);

sys/dev/pci/drm/drm_vblank.c

1617

drm_WARN_ON_ONCE(dev, !vblank->config.disable_immediate);

sys/dev/pci/drm/drm_vblank.c

1808

if (vblank->config.disable_immediate &&

sys/dev/pci/drm/drm_vblank.c

1972

disable_irq = (vblank->config.disable_immediate &&

sys/dev/pci/drm/drm_vblank.c

1973

vblank->config.offdelay_ms > 0 &&

sys/dev/pci/drm/drm_vblank.c

2046

vblank_enabled = READ_ONCE(vblank->config.disable_immediate) &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

2146

&crtc->config->hw.pipe_mode;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2149

int pixel_rate = crtc->config->pixel_rate;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2257

planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2284

planeb_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2320

&crtc->config->hw.pipe_mode;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2323

int pixel_rate = crtc->config->pixel_rate;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2378

planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2591

const struct intel_wm_config *config,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2598

if (is_sprite && !config->sprites_enabled)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2602

if (level == 0 || config->num_pipes_active > 1) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2614

if (config->sprites_enabled) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2632

const struct intel_wm_config *config)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2635

if (level > 0 && config->num_pipes_active > 1)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2644

const struct intel_wm_config *config,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2648

max->pri = ilk_plane_wm_max(display, level, config, ddb_partitioning, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2649

max->spr = ilk_plane_wm_max(display, level, config, ddb_partitioning, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2650

max->cur = ilk_cursor_wm_max(display, level, config);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2902

const struct intel_wm_config config = {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2910

ilk_compute_wm_maximums(display, 0, &config, INTEL_DDB_PART_1_2, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3111

const struct intel_wm_config *config,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3120

config->num_pipes_active > 1)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3418

struct intel_wm_config *config)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3429

config->sprites_enabled |= wm->sprites_enabled;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3430

config->sprites_scaled |= wm->sprites_scaled;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3431

config->num_pipes_active++;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3439

struct intel_wm_config config = {};

sys/dev/pci/drm/i915/display/i9xx_wm.c

3443

ilk_compute_wm_config(display, &config);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3445

ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_1_2, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3446

ilk_wm_merge(display, &config, &max, &lp_wm_1_2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3450

config.num_pipes_active == 1 && config.sprites_enabled) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3451

ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_5_6, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3452

ilk_wm_merge(display, &config, &max, &lp_wm_5_6);

sys/dev/pci/drm/i915/display/i9xx_wm.c

635

crtc->config->hw.adjusted_mode.crtc_clock;

sys/dev/pci/drm/i915/display/i9xx_wm.c

671

int pixel_rate = crtc->config->pixel_rate;

sys/dev/pci/drm/i915/display/icl_dsi.c

1618

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/icl_dsi.c

1863

struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;

sys/dev/pci/drm/i915/display/icl_dsi.c

2010

if (intel_connector->panel.vbt.dsi.config->dual_link)

sys/dev/pci/drm/i915/display/intel_audio.c

1208

hsw_audio_config_update(encoder, crtc->config);

sys/dev/pci/drm/i915/display/intel_audio.c

224

hdmi_audio_clock[i].config);

sys/dev/pci/drm/i915/display/intel_audio.c

226

return hdmi_audio_clock[i].config;

sys/dev/pci/drm/i915/display/intel_audio.c

89

u32 config;

sys/dev/pci/drm/i915/display/intel_backlight.c

1565

if (connector->panel.vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {

sys/dev/pci/drm/i915/display/intel_bios.c

1654

if (!panel->vbt.dsi.config->dual_link || display->vbt.version < 197) {

sys/dev/pci/drm/i915/display/intel_bios.c

1656

if (panel->vbt.dsi.config->cabc_supported)

sys/dev/pci/drm/i915/display/intel_bios.c

1662

switch (panel->vbt.dsi.config->dl_dcs_backlight_ports) {

sys/dev/pci/drm/i915/display/intel_bios.c

1675

if (!panel->vbt.dsi.config->cabc_supported)

sys/dev/pci/drm/i915/display/intel_bios.c

1678

switch (panel->vbt.dsi.config->dl_dcs_cabc_ports) {

sys/dev/pci/drm/i915/display/intel_bios.c

1698

const struct mipi_config *config;

sys/dev/pci/drm/i915/display/intel_bios.c

1723

config = &start->config[panel_type];

sys/dev/pci/drm/i915/display/intel_bios.c

1727

panel->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);

sys/dev/pci/drm/i915/display/intel_bios.c

1728

if (!panel->vbt.dsi.config)

sys/dev/pci/drm/i915/display/intel_bios.c

1733

kfree(panel->vbt.dsi.config);

sys/dev/pci/drm/i915/display/intel_bios.c

1740

switch (config->rotation) {

sys/dev/pci/drm/i915/display/intel_bios.c

1975

if (panel->vbt.dsi.config->is_cmd_mode ||

sys/dev/pci/drm/i915/display/intel_bios.c

3318

kfree(panel->vbt.dsi.config);

sys/dev/pci/drm/i915/display/intel_bios.c

3319

panel->vbt.dsi.config = NULL;

sys/dev/pci/drm/i915/display/intel_bios.c

3501

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_crtc.c

205

crtc->config = crtc_state;

sys/dev/pci/drm/i915/display/intel_cursor.c

75

const struct drm_mode_config *config =

sys/dev/pci/drm/i915/display/intel_cursor.c

80

return width > 0 && width <= config->cursor_width &&

sys/dev/pci/drm/i915/display/intel_cursor.c

81

height > 0 && height <= config->cursor_height;

sys/dev/pci/drm/i915/display/intel_cursor.c

982

const struct drm_mode_config *config = &display->drm->mode_config;

sys/dev/pci/drm/i915/display/intel_cursor.c

986

max_size = min(config->cursor_width, config->cursor_height);

sys/dev/pci/drm/i915/display/intel_ddi.c

4684

u8 config;

sys/dev/pci/drm/i915/display/intel_ddi.c

4721

ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config);

sys/dev/pci/drm/i915/display/intel_ddi.c

4728

if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==

sys/dev/pci/drm/i915/display/intel_ddi.c

4730

!!(config & SCDC_SCRAMBLING_ENABLE) ==

sys/dev/pci/drm/i915/display/intel_display.c

5394

PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);

sys/dev/pci/drm/i915/display/intel_display.c

5395

PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);

sys/dev/pci/drm/i915/display/intel_display.c

5396

PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);

sys/dev/pci/drm/i915/display/intel_display.c

5397

PIPE_CONF_CHECK_BOOL(dsc.config.native_422);

sys/dev/pci/drm/i915/display/intel_display.c

5398

PIPE_CONF_CHECK_BOOL(dsc.config.native_420);

sys/dev/pci/drm/i915/display/intel_display.c

5399

PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);

sys/dev/pci/drm/i915/display/intel_display.c

5400

PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);

sys/dev/pci/drm/i915/display/intel_display.c

5401

PIPE_CONF_CHECK_I(dsc.config.bits_per_component);

sys/dev/pci/drm/i915/display/intel_display.c

5402

PIPE_CONF_CHECK_I(dsc.config.pic_width);

sys/dev/pci/drm/i915/display/intel_display.c

5403

PIPE_CONF_CHECK_I(dsc.config.pic_height);

sys/dev/pci/drm/i915/display/intel_display.c

5404

PIPE_CONF_CHECK_I(dsc.config.slice_width);

sys/dev/pci/drm/i915/display/intel_display.c

5405

PIPE_CONF_CHECK_I(dsc.config.slice_height);

sys/dev/pci/drm/i915/display/intel_display.c

5406

PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);

sys/dev/pci/drm/i915/display/intel_display.c

5407

PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);

sys/dev/pci/drm/i915/display/intel_display.c

5408

PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);

sys/dev/pci/drm/i915/display/intel_display.c

5409

PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);

sys/dev/pci/drm/i915/display/intel_display.c

5410

PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);

sys/dev/pci/drm/i915/display/intel_display.c

5411

PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5412

PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);

sys/dev/pci/drm/i915/display/intel_display.c

5413

PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);

sys/dev/pci/drm/i915/display/intel_display.c

5414

PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5415

PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5416

PIPE_CONF_CHECK_I(dsc.config.initial_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5417

PIPE_CONF_CHECK_I(dsc.config.final_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5418

PIPE_CONF_CHECK_I(dsc.config.rc_model_size);

sys/dev/pci/drm/i915/display/intel_display.c

5419

PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);

sys/dev/pci/drm/i915/display/intel_display.c

5420

PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);

sys/dev/pci/drm/i915/display/intel_display.c

5421

PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);

sys/dev/pci/drm/i915/display/intel_display.c

5422

PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5423

PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

7402

crtc->config = new_crtc_state;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1023

seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);

sys/dev/pci/drm/i915/display/intel_display_power.c

1623

int config, i;

sys/dev/pci/drm/i915/display/intel_display_power.c

1636

for (config = 0; table[config].page_mask != 0; config++)

sys/dev/pci/drm/i915/display/intel_display_power.c

1637

if (table[config].num_channels == dram_info->num_channels &&

sys/dev/pci/drm/i915/display/intel_display_power.c

1638

table[config].type == dram_info->type)

sys/dev/pci/drm/i915/display/intel_display_power.c

1641

if (table[config].page_mask == 0) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1650

table[config].page_mask);

sys/dev/pci/drm/i915/display/intel_display_types.h

1277

struct drm_dsc_config config;

sys/dev/pci/drm/i915/display/intel_display_types.h

1413

struct intel_crtc_state *config;

sys/dev/pci/drm/i915/display/intel_display_types.h

379

struct mipi_config *config;

sys/dev/pci/drm/i915/display/intel_dp.c

1888

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

774

struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

915

struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;

sys/dev/pci/drm/i915/display/intel_load_detect.c

57

struct drm_mode_config *config = &display->drm->mode_config;

sys/dev/pci/drm/i915/display/intel_load_detect.c

67

drm_WARN_ON(display->drm, !drm_modeset_is_locked(&config->connection_mutex));

sys/dev/pci/drm/i915/display/intel_overlay.c

1181

if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&

sys/dev/pci/drm/i915/display/intel_overlay.c

1182

crtc->config->gmch_pfit.control & PFIT_ENABLE) {

sys/dev/pci/drm/i915/display/intel_overlay.c

828

overlay->crtc->config;

sys/dev/pci/drm/i915/display/intel_overlay.c

940

if (crtc->config->double_wide)

sys/dev/pci/drm/i915/display/intel_overlay.c

977

overlay->crtc->config;

sys/dev/pci/drm/i915/display/intel_psr.c

1272

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_psr.c

2573

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1528

struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175+ */

sys/dev/pci/drm/i915/display/intel_vdsc.c

1057

drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);

sys/dev/pci/drm/i915/display/intel_vdsc.c

265

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

275

struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

458

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

714

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

737

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

759

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

903

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1028

adjusted_mode_sw = &crtc->config->hw.adjusted_mode;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1596

struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1971

if (connector->panel.vbt.dsi.config->dual_link)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

110

config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

111

config->dsi_pll.div =

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

119

struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

130

pll_ctl = config->dsi_pll.ctrl;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

131

pll_div = config->dsi_pll.div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

176

struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

185

ret = dsi_calc_mnp(display, config, dsi_clk);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

192

config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

195

config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

197

config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

200

config->dsi_pll.div, config->dsi_pll.ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

202

pclk = vlv_dsi_pclk(encoder, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

203

config->port_clock = pclk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

206

config->hw.adjusted_mode.crtc_clock = pclk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

208

config->hw.adjusted_mode.crtc_clock *= 2;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

214

const struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

225

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

227

config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

234

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

329

struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

341

config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

342

config->dsi_pll.div = pll_div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

344

return vlv_dsi_pclk(encoder, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

348

const struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

354

dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

361

struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

366

config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

368

config->dsi_pll.ctrl &= ~BXT_DSIC_16X_MASK;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

370

pclk = bxt_dsi_pclk(encoder, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

389

const struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

399

pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

435

const struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

454

pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

487

struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

525

config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

527

config->dsi_pll.ctrl |= BXT_DSIC_16X_BY2;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

533

config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

535

pclk = bxt_dsi_pclk(encoder, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

536

config->port_clock = pclk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

539

config->hw.adjusted_mode.crtc_clock = pclk;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

541

config->hw.adjusted_mode.crtc_clock *= 2;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

547

const struct intel_crtc_state *config)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

556

intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

562

bxt_dsi_program_clocks(display, port, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

564

glk_dsi_program_esc_clock(display, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

63

struct intel_crtc_state *config,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

17

struct intel_crtc_state *config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

19

const struct intel_crtc_state *config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

22

struct intel_crtc_state *config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

26

struct intel_crtc_state *config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

28

const struct intel_crtc_state *config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

31

struct intel_crtc_state *config);

sys/dev/pci/drm/i915/i915_perf.c

3650

struct i915_oa_config *config;

sys/dev/pci/drm/i915/i915_perf.c

3653

config = i915_perf_get_oa_config(stream->perf, metrics_set);

sys/dev/pci/drm/i915/i915_perf.c

3654

if (!config)

sys/dev/pci/drm/i915/i915_perf.c

3657

if (config != stream->oa_config) {

sys/dev/pci/drm/i915/i915_perf.c

3669

err = emit_oa_config(stream, config, oa_context(stream), NULL);

sys/dev/pci/drm/i915/i915_perf.c

3671

config = xchg(&stream->oa_config, config);

sys/dev/pci/drm/i915/i915_perf.c

3676

i915_oa_config_put(config);

sys/dev/pci/drm/i915/i915_pmu.c

1013

u64 config = ___I915_PMU_OTHER(j, events[i].counter);

sys/dev/pci/drm/i915/i915_pmu.c

1015

if (!config_status(i915, config))

sys/dev/pci/drm/i915/i915_pmu.c

103

static unsigned int config_bit(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

1049

u64 config = ___I915_PMU_OTHER(j, events[i].counter);

sys/dev/pci/drm/i915/i915_pmu.c

105

if (is_engine_config(config))

sys/dev/pci/drm/i915/i915_pmu.c

1052

if (config_status(i915, config))

sys/dev/pci/drm/i915/i915_pmu.c

106

return engine_config_sample(config);

sys/dev/pci/drm/i915/i915_pmu.c

1064

i915_iter = add_i915_attr(i915_iter, str, config);

sys/dev/pci/drm/i915/i915_pmu.c

108

return other_bit(config);

sys/dev/pci/drm/i915/i915_pmu.c

111

static __always_inline u32 config_mask(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

113

unsigned int bit = config_bit(config);

sys/dev/pci/drm/i915/i915_pmu.c

129

return is_engine_config(event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

134

return config_bit(event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

41

static u8 engine_config_sample(u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

43

return config & I915_PMU_SAMPLE_MASK;

sys/dev/pci/drm/i915/i915_pmu.c

48

return engine_config_sample(event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

53

return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;

sys/dev/pci/drm/i915/i915_pmu.c

569

config_status(struct drm_i915_private *i915, u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

573

unsigned int gt_id = config_gt_id(config);

sys/dev/pci/drm/i915/i915_pmu.c

579

switch (config_counter(config)) {

sys/dev/pci/drm/i915/i915_pmu.c

58

return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;

sys/dev/pci/drm/i915/i915_pmu.c

61

static bool is_engine_config(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

63

return config < __I915_PMU_OTHER(0);

sys/dev/pci/drm/i915/i915_pmu.c

645

ret = config_status(i915, event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

66

static unsigned int config_gt_id(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

68

return config >> __I915_PMU_GT_SHIFT;

sys/dev/pci/drm/i915/i915_pmu.c

683

const unsigned int gt_id = config_gt_id(event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

684

const u64 config = config_counter(event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

686

switch (config) {

sys/dev/pci/drm/i915/i915_pmu.c

71

static u64 config_counter(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

73

return config & ~(~0ULL << __I915_PMU_GT_SHIFT);

sys/dev/pci/drm/i915/i915_pmu.c

76

static unsigned int other_bit(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

80

switch (config_counter(config)) {

sys/dev/pci/drm/i915/i915_pmu.c

954

add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

960

attr->val = config;

sys/dev/pci/drm/i915/i915_pmu.c

99

config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +

sys/dev/pci/drm/i915/i915_query.c

286

if (get_user(config_id, &user_query_config_ptr->config))

sys/dev/pci/drm/i915/i915_query.c

441

if (put_user(n_configs, &user_query_config_ptr->config)) {

sys/dev/pci/drm/include/drm/drm_vblank.h

230

struct drm_vblank_crtc_config config;

sys/dev/pci/drm/include/drm/drm_vblank.h

282

const struct drm_vblank_crtc_config *config);

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

3412

__u64 config;

sys/dev/pci/drm/radeon/atombios_crtc.c

1290

num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;

sys/dev/pci/drm/radeon/atombios_crtc.c

1305

num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;

sys/dev/pci/drm/radeon/atombios_crtc.c

1312

tmp = rdev->config.cayman.tile_config;

sys/dev/pci/drm/radeon/atombios_crtc.c

1314

tmp = rdev->config.evergreen.tile_config;

sys/dev/pci/drm/radeon/atombios_crtc.c

1346

u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;

sys/dev/pci/drm/radeon/cik.c

2322

u32 *tile = rdev->config.cik.tile_mode_array;

sys/dev/pci/drm/radeon/cik.c

2323

u32 *macrotile = rdev->config.cik.macrotile_mode_array;

sys/dev/pci/drm/radeon/cik.c

2325

ARRAY_SIZE(rdev->config.cik.tile_mode_array);

sys/dev/pci/drm/radeon/cik.c

2327

ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);

sys/dev/pci/drm/radeon/cik.c

2330

u32 num_rbs = rdev->config.cik.max_backends_per_se *

sys/dev/pci/drm/radeon/cik.c

2331

rdev->config.cik.max_shader_engines;

sys/dev/pci/drm/radeon/cik.c

2333

switch (rdev->config.cik.mem_row_size_in_kb) {

sys/dev/pci/drm/radeon/cik.c

2346

num_pipe_configs = rdev->config.cik.max_tile_pipes;

sys/dev/pci/drm/radeon/cik.c

3129

rdev->config.cik.backend_enable_mask = enabled_rbs;

sys/dev/pci/drm/radeon/cik.c

3178

rdev->config.cik.max_shader_engines = 2;

sys/dev/pci/drm/radeon/cik.c

3179

rdev->config.cik.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/cik.c

3180

rdev->config.cik.max_cu_per_sh = 7;

sys/dev/pci/drm/radeon/cik.c

3181

rdev->config.cik.max_sh_per_se = 1;

sys/dev/pci/drm/radeon/cik.c

3182

rdev->config.cik.max_backends_per_se = 2;

sys/dev/pci/drm/radeon/cik.c

3183

rdev->config.cik.max_texture_channel_caches = 4;

sys/dev/pci/drm/radeon/cik.c

3184

rdev->config.cik.max_gprs = 256;

sys/dev/pci/drm/radeon/cik.c

3185

rdev->config.cik.max_gs_threads = 32;

sys/dev/pci/drm/radeon/cik.c

3186

rdev->config.cik.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/cik.c

3188

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/cik.c

3189

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/radeon/cik.c

3190

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/cik.c

3191

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/cik.c

3195

rdev->config.cik.max_shader_engines = 4;

sys/dev/pci/drm/radeon/cik.c

3196

rdev->config.cik.max_tile_pipes = 16;

sys/dev/pci/drm/radeon/cik.c

3197

rdev->config.cik.max_cu_per_sh = 11;

sys/dev/pci/drm/radeon/cik.c

3198

rdev->config.cik.max_sh_per_se = 1;

sys/dev/pci/drm/radeon/cik.c

3199

rdev->config.cik.max_backends_per_se = 4;

sys/dev/pci/drm/radeon/cik.c

3200

rdev->config.cik.max_texture_channel_caches = 16;

sys/dev/pci/drm/radeon/cik.c

3201

rdev->config.cik.max_gprs = 256;

sys/dev/pci/drm/radeon/cik.c

3202

rdev->config.cik.max_gs_threads = 32;

sys/dev/pci/drm/radeon/cik.c

3203

rdev->config.cik.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/cik.c

3205

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/cik.c

3206

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/radeon/cik.c

3207

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/cik.c

3208

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/cik.c

3212

rdev->config.cik.max_shader_engines = 1;

sys/dev/pci/drm/radeon/cik.c

3213

rdev->config.cik.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/cik.c

3214

rdev->config.cik.max_cu_per_sh = 8;

sys/dev/pci/drm/radeon/cik.c

3215

rdev->config.cik.max_backends_per_se = 2;

sys/dev/pci/drm/radeon/cik.c

3216

rdev->config.cik.max_sh_per_se = 1;

sys/dev/pci/drm/radeon/cik.c

3217

rdev->config.cik.max_texture_channel_caches = 4;

sys/dev/pci/drm/radeon/cik.c

3218

rdev->config.cik.max_gprs = 256;

sys/dev/pci/drm/radeon/cik.c

3219

rdev->config.cik.max_gs_threads = 16;

sys/dev/pci/drm/radeon/cik.c

3220

rdev->config.cik.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/cik.c

3222

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/cik.c

3223

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/radeon/cik.c

3224

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/cik.c

3225

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/cik.c

3231

rdev->config.cik.max_shader_engines = 1;

sys/dev/pci/drm/radeon/cik.c

3232

rdev->config.cik.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/cik.c

3233

rdev->config.cik.max_cu_per_sh = 2;

sys/dev/pci/drm/radeon/cik.c

3234

rdev->config.cik.max_sh_per_se = 1;

sys/dev/pci/drm/radeon/cik.c

3235

rdev->config.cik.max_backends_per_se = 1;

sys/dev/pci/drm/radeon/cik.c

3236

rdev->config.cik.max_texture_channel_caches = 2;

sys/dev/pci/drm/radeon/cik.c

3237

rdev->config.cik.max_gprs = 256;

sys/dev/pci/drm/radeon/cik.c

3238

rdev->config.cik.max_gs_threads = 16;

sys/dev/pci/drm/radeon/cik.c

3239

rdev->config.cik.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/cik.c

3241

rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/cik.c

3242

rdev->config.cik.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/radeon/cik.c

3243

rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/cik.c

3244

rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/cik.c

3267

rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;

sys/dev/pci/drm/radeon/cik.c

3268

rdev->config.cik.mem_max_burst_length_bytes = 256;

sys/dev/pci/drm/radeon/cik.c

3270

rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/pci/drm/radeon/cik.c

3271

if (rdev->config.cik.mem_row_size_in_kb > 4)

sys/dev/pci/drm/radeon/cik.c

3272

rdev->config.cik.mem_row_size_in_kb = 4;

sys/dev/pci/drm/radeon/cik.c

3274

rdev->config.cik.shader_engine_tile_size = 32;

sys/dev/pci/drm/radeon/cik.c

3275

rdev->config.cik.num_gpus = 1;

sys/dev/pci/drm/radeon/cik.c

3276

rdev->config.cik.multi_gpu_tile_size = 64;

sys/dev/pci/drm/radeon/cik.c

3280

switch (rdev->config.cik.mem_row_size_in_kb) {

sys/dev/pci/drm/radeon/cik.c

3300

rdev->config.cik.tile_config = 0;

sys/dev/pci/drm/radeon/cik.c

3301

switch (rdev->config.cik.num_tile_pipes) {

sys/dev/pci/drm/radeon/cik.c

3303

rdev->config.cik.tile_config |= (0 << 0);

sys/dev/pci/drm/radeon/cik.c

3306

rdev->config.cik.tile_config |= (1 << 0);

sys/dev/pci/drm/radeon/cik.c

3309

rdev->config.cik.tile_config |= (2 << 0);

sys/dev/pci/drm/radeon/cik.c

3314

rdev->config.cik.tile_config |= (3 << 0);

sys/dev/pci/drm/radeon/cik.c

3317

rdev->config.cik.tile_config |=

sys/dev/pci/drm/radeon/cik.c

3319

rdev->config.cik.tile_config |=

sys/dev/pci/drm/radeon/cik.c

3321

rdev->config.cik.tile_config |=

sys/dev/pci/drm/radeon/cik.c

3335

cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,

sys/dev/pci/drm/radeon/cik.c

3336

rdev->config.cik.max_sh_per_se,

sys/dev/pci/drm/radeon/cik.c

3337

rdev->config.cik.max_backends_per_se);

sys/dev/pci/drm/radeon/cik.c

3339

rdev->config.cik.active_cus = 0;

sys/dev/pci/drm/radeon/cik.c

3340

for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

sys/dev/pci/drm/radeon/cik.c

3341

for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

sys/dev/pci/drm/radeon/cik.c

3342

rdev->config.cik.active_cus +=

sys/dev/pci/drm/radeon/cik.c

3376

WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |

sys/dev/pci/drm/radeon/cik.c

3377

SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |

sys/dev/pci/drm/radeon/cik.c

3378

SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |

sys/dev/pci/drm/radeon/cik.c

3379

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));

sys/dev/pci/drm/radeon/cik.c

3977

WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);

sys/dev/pci/drm/radeon/cik.c

5786

for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

sys/dev/pci/drm/radeon/cik.c

5787

for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

sys/dev/pci/drm/radeon/cik.c

6539

for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {

sys/dev/pci/drm/radeon/cik.c

6553

for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

sys/dev/pci/drm/radeon/cik.c

6554

for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

sys/dev/pci/drm/radeon/cik.c

6558

for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {

sys/dev/pci/drm/radeon/evergreen.c

3010

radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);

sys/dev/pci/drm/radeon/evergreen.c

3156

rdev->config.evergreen.num_ses = 2;

sys/dev/pci/drm/radeon/evergreen.c

3157

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3158

rdev->config.evergreen.max_tile_pipes = 8;

sys/dev/pci/drm/radeon/evergreen.c

3159

rdev->config.evergreen.max_simds = 10;

sys/dev/pci/drm/radeon/evergreen.c

3160

rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3161

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3162

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3163

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3164

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/pci/drm/radeon/evergreen.c

3165

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3166

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3167

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3168

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3169

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/evergreen.c

3170

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3172

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/evergreen.c

3173

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3174

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3178

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3179

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3180

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3181

rdev->config.evergreen.max_simds = 10;

sys/dev/pci/drm/radeon/evergreen.c

3182

rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3183

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3184

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3185

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3186

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/pci/drm/radeon/evergreen.c

3187

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3188

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3189

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3190

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3191

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/evergreen.c

3192

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3194

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/evergreen.c

3195

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3196

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3200

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3201

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3202

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3203

rdev->config.evergreen.max_simds = 5;

sys/dev/pci/drm/radeon/evergreen.c

3204

rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3205

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3206

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3207

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3208

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/pci/drm/radeon/evergreen.c

3209

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3210

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3211

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3212

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3213

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/evergreen.c

3214

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3216

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/evergreen.c

3217

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3218

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3223

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3224

rdev->config.evergreen.max_pipes = 2;

sys/dev/pci/drm/radeon/evergreen.c

3225

rdev->config.evergreen.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/evergreen.c

3226

rdev->config.evergreen.max_simds = 2;

sys/dev/pci/drm/radeon/evergreen.c

3227

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3228

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3229

rdev->config.evergreen.max_threads = 192;

sys/dev/pci/drm/radeon/evergreen.c

3230

rdev->config.evergreen.max_gs_threads = 16;

sys/dev/pci/drm/radeon/evergreen.c

3231

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/pci/drm/radeon/evergreen.c

3232

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3233

rdev->config.evergreen.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/evergreen.c

3234

rdev->config.evergreen.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/evergreen.c

3235

rdev->config.evergreen.sx_max_export_smx_size = 96;

sys/dev/pci/drm/radeon/evergreen.c

3236

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/evergreen.c

3237

rdev->config.evergreen.sq_num_cf_insts = 1;

sys/dev/pci/drm/radeon/evergreen.c

3239

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/evergreen.c

3240

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3241

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3245

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3246

rdev->config.evergreen.max_pipes = 2;

sys/dev/pci/drm/radeon/evergreen.c

3247

rdev->config.evergreen.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/evergreen.c

3248

rdev->config.evergreen.max_simds = 2;

sys/dev/pci/drm/radeon/evergreen.c

3249

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3250

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3251

rdev->config.evergreen.max_threads = 192;

sys/dev/pci/drm/radeon/evergreen.c

3252

rdev->config.evergreen.max_gs_threads = 16;

sys/dev/pci/drm/radeon/evergreen.c

3253

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/pci/drm/radeon/evergreen.c

3254

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3255

rdev->config.evergreen.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/evergreen.c

3256

rdev->config.evergreen.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/evergreen.c

3257

rdev->config.evergreen.sx_max_export_smx_size = 96;

sys/dev/pci/drm/radeon/evergreen.c

3258

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/evergreen.c

3259

rdev->config.evergreen.sq_num_cf_insts = 1;

sys/dev/pci/drm/radeon/evergreen.c

3261

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/evergreen.c

3262

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3263

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3267

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3268

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3269

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3271

rdev->config.evergreen.max_simds = 3;

sys/dev/pci/drm/radeon/evergreen.c

3274

rdev->config.evergreen.max_simds = 4;

sys/dev/pci/drm/radeon/evergreen.c

3276

rdev->config.evergreen.max_simds = 5;

sys/dev/pci/drm/radeon/evergreen.c

3277

rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3278

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3279

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3280

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3281

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/pci/drm/radeon/evergreen.c

3282

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3283

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3284

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3285

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3286

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/evergreen.c

3287

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3289

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/evergreen.c

3290

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3291

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3295

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3296

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3297

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3298

rdev->config.evergreen.max_simds = 2;

sys/dev/pci/drm/radeon/evergreen.c

3299

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3300

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3301

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3302

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3303

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/pci/drm/radeon/evergreen.c

3304

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3305

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3306

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3307

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3308

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/evergreen.c

3309

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3311

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/evergreen.c

3312

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3313

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3317

rdev->config.evergreen.num_ses = 2;

sys/dev/pci/drm/radeon/evergreen.c

3318

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3319

rdev->config.evergreen.max_tile_pipes = 8;

sys/dev/pci/drm/radeon/evergreen.c

3320

rdev->config.evergreen.max_simds = 7;

sys/dev/pci/drm/radeon/evergreen.c

3321

rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3322

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3323

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3324

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3325

rdev->config.evergreen.max_stack_entries = 512;

sys/dev/pci/drm/radeon/evergreen.c

3326

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3327

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3328

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3329

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3330

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/evergreen.c

3331

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3333

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/evergreen.c

3334

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3335

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3339

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3340

rdev->config.evergreen.max_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3341

rdev->config.evergreen.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/evergreen.c

3342

rdev->config.evergreen.max_simds = 6;

sys/dev/pci/drm/radeon/evergreen.c

3343

rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3344

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3345

rdev->config.evergreen.max_threads = 248;

sys/dev/pci/drm/radeon/evergreen.c

3346

rdev->config.evergreen.max_gs_threads = 32;

sys/dev/pci/drm/radeon/evergreen.c

3347

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/pci/drm/radeon/evergreen.c

3348

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3349

rdev->config.evergreen.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/evergreen.c

3350

rdev->config.evergreen.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/evergreen.c

3351

rdev->config.evergreen.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/evergreen.c

3352

rdev->config.evergreen.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/evergreen.c

3353

rdev->config.evergreen.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/evergreen.c

3355

rdev->config.evergreen.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/evergreen.c

3356

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3357

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3361

rdev->config.evergreen.num_ses = 1;

sys/dev/pci/drm/radeon/evergreen.c

3362

rdev->config.evergreen.max_pipes = 2;

sys/dev/pci/drm/radeon/evergreen.c

3363

rdev->config.evergreen.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/evergreen.c

3364

rdev->config.evergreen.max_simds = 2;

sys/dev/pci/drm/radeon/evergreen.c

3365

rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/evergreen.c

3366

rdev->config.evergreen.max_gprs = 256;

sys/dev/pci/drm/radeon/evergreen.c

3367

rdev->config.evergreen.max_threads = 192;

sys/dev/pci/drm/radeon/evergreen.c

3368

rdev->config.evergreen.max_gs_threads = 16;

sys/dev/pci/drm/radeon/evergreen.c

3369

rdev->config.evergreen.max_stack_entries = 256;

sys/dev/pci/drm/radeon/evergreen.c

3370

rdev->config.evergreen.sx_num_of_sets = 4;

sys/dev/pci/drm/radeon/evergreen.c

3371

rdev->config.evergreen.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/evergreen.c

3372

rdev->config.evergreen.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/evergreen.c

3373

rdev->config.evergreen.sx_max_export_smx_size = 96;

sys/dev/pci/drm/radeon/evergreen.c

3374

rdev->config.evergreen.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/evergreen.c

3375

rdev->config.evergreen.sq_num_cf_insts = 1;

sys/dev/pci/drm/radeon/evergreen.c

3377

rdev->config.evergreen.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/evergreen.c

3378

rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/evergreen.c

3379

rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/evergreen.c

3414

rdev->config.evergreen.tile_config = 0;

sys/dev/pci/drm/radeon/evergreen.c

3415

switch (rdev->config.evergreen.max_tile_pipes) {

sys/dev/pci/drm/radeon/evergreen.c

3418

rdev->config.evergreen.tile_config |= (0 << 0);

sys/dev/pci/drm/radeon/evergreen.c

3421

rdev->config.evergreen.tile_config |= (1 << 0);

sys/dev/pci/drm/radeon/evergreen.c

3424

rdev->config.evergreen.tile_config |= (2 << 0);

sys/dev/pci/drm/radeon/evergreen.c

3427

rdev->config.evergreen.tile_config |= (3 << 0);

sys/dev/pci/drm/radeon/evergreen.c

3432

rdev->config.evergreen.tile_config |= 1 << 4;

sys/dev/pci/drm/radeon/evergreen.c

3436

rdev->config.evergreen.tile_config |= 0 << 4;

sys/dev/pci/drm/radeon/evergreen.c

3439

rdev->config.evergreen.tile_config |= 1 << 4;

sys/dev/pci/drm/radeon/evergreen.c

3443

rdev->config.evergreen.tile_config |= 2 << 4;

sys/dev/pci/drm/radeon/evergreen.c

3447

rdev->config.evergreen.tile_config |= 0 << 8;

sys/dev/pci/drm/radeon/evergreen.c

3448

rdev->config.evergreen.tile_config |=

sys/dev/pci/drm/radeon/evergreen.c

3461

for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {

sys/dev/pci/drm/radeon/evergreen.c

3474

for (i = 0; i < rdev->config.evergreen.max_backends; i++)

sys/dev/pci/drm/radeon/evergreen.c

3478

for (i = 0; i < rdev->config.evergreen.max_backends; i++)

sys/dev/pci/drm/radeon/evergreen.c

3482

for (i = 0; i < rdev->config.evergreen.num_ses; i++) {

sys/dev/pci/drm/radeon/evergreen.c

3488

simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;

sys/dev/pci/drm/radeon/evergreen.c

3492

rdev->config.evergreen.active_simds = hweight32(~tmp);

sys/dev/pci/drm/radeon/evergreen.c

3505

if ((rdev->config.evergreen.max_backends == 1) &&

sys/dev/pci/drm/radeon/evergreen.c

3516

tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,

sys/dev/pci/drm/radeon/evergreen.c

3519

rdev->config.evergreen.backend_map = tmp;

sys/dev/pci/drm/radeon/evergreen.c

3545

smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);

sys/dev/pci/drm/radeon/evergreen.c

3551

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |

sys/dev/pci/drm/radeon/evergreen.c

3552

POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |

sys/dev/pci/drm/radeon/evergreen.c

3553

SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));

sys/dev/pci/drm/radeon/evergreen.c

3555

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |

sys/dev/pci/drm/radeon/evergreen.c

3556

SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |

sys/dev/pci/drm/radeon/evergreen.c

3557

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));

sys/dev/pci/drm/radeon/evergreen.c

3564

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |

sys/dev/pci/drm/radeon/evergreen.c

3596

sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 12 / 32);

sys/dev/pci/drm/radeon/evergreen.c

3597

sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);

sys/dev/pci/drm/radeon/evergreen.c

3599

sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);

sys/dev/pci/drm/radeon/evergreen.c

3600

sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);

sys/dev/pci/drm/radeon/evergreen.c

3601

sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);

sys/dev/pci/drm/radeon/evergreen.c

3602

sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);

sys/dev/pci/drm/radeon/evergreen.c

3617

sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/pci/drm/radeon/evergreen.c

3618

sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/pci/drm/radeon/evergreen.c

3619

sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/pci/drm/radeon/evergreen.c

3620

sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/pci/drm/radeon/evergreen.c

3621

sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

sys/dev/pci/drm/radeon/evergreen.c

3623

sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/pci/drm/radeon/evergreen.c

3624

sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/pci/drm/radeon/evergreen.c

3625

sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/pci/drm/radeon/evergreen.c

3626

sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/pci/drm/radeon/evergreen.c

3627

sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/pci/drm/radeon/evergreen.c

3628

sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

sys/dev/pci/drm/radeon/evergreen.c

4395

3 | (3 << (16 * rdev->config.cayman.max_shader_engines));

sys/dev/pci/drm/radeon/evergreen.c

4398

tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;

sys/dev/pci/drm/radeon/evergreen.c

4400

if (tmp == rdev->config.cayman.max_simds_per_se) {

sys/dev/pci/drm/radeon/evergreen_cs.c

2777

tmp = p->rdev->config.cayman.tile_config;

sys/dev/pci/drm/radeon/evergreen_cs.c

2780

tmp = p->rdev->config.evergreen.tile_config;

sys/dev/pci/drm/radeon/ni.c

1001

rdev->config.cayman.shader_engine_tile_size = 32;

sys/dev/pci/drm/radeon/ni.c

1002

rdev->config.cayman.num_gpus = 1;

sys/dev/pci/drm/radeon/ni.c

1003

rdev->config.cayman.multi_gpu_tile_size = 64;

sys/dev/pci/drm/radeon/ni.c

1006

rdev->config.cayman.num_tile_pipes = (1 << tmp);

sys/dev/pci/drm/radeon/ni.c

1008

rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;

sys/dev/pci/drm/radeon/ni.c

1010

rdev->config.cayman.num_shader_engines = tmp + 1;

sys/dev/pci/drm/radeon/ni.c

1012

rdev->config.cayman.num_gpus = tmp + 1;

sys/dev/pci/drm/radeon/ni.c

1014

rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;

sys/dev/pci/drm/radeon/ni.c

1016

rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;

sys/dev/pci/drm/radeon/ni.c

1026

rdev->config.cayman.tile_config = 0;

sys/dev/pci/drm/radeon/ni.c

1027

switch (rdev->config.cayman.num_tile_pipes) {

sys/dev/pci/drm/radeon/ni.c

1030

rdev->config.cayman.tile_config |= (0 << 0);

sys/dev/pci/drm/radeon/ni.c

1033

rdev->config.cayman.tile_config |= (1 << 0);

sys/dev/pci/drm/radeon/ni.c

1036

rdev->config.cayman.tile_config |= (2 << 0);

sys/dev/pci/drm/radeon/ni.c

1039

rdev->config.cayman.tile_config |= (3 << 0);

sys/dev/pci/drm/radeon/ni.c

1045

rdev->config.cayman.tile_config |= 1 << 4;

sys/dev/pci/drm/radeon/ni.c

1049

rdev->config.cayman.tile_config |= 0 << 4;

sys/dev/pci/drm/radeon/ni.c

1052

rdev->config.cayman.tile_config |= 1 << 4;

sys/dev/pci/drm/radeon/ni.c

1056

rdev->config.cayman.tile_config |= 2 << 4;

sys/dev/pci/drm/radeon/ni.c

1060

rdev->config.cayman.tile_config |=

sys/dev/pci/drm/radeon/ni.c

1062

rdev->config.cayman.tile_config |=

sys/dev/pci/drm/radeon/ni.c

1066

for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {

sys/dev/pci/drm/radeon/ni.c

1078

for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)

sys/dev/pci/drm/radeon/ni.c

1082

for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)

sys/dev/pci/drm/radeon/ni.c

1086

for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {

sys/dev/pci/drm/radeon/ni.c

1092

simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;

sys/dev/pci/drm/radeon/ni.c

1096

rdev->config.cayman.active_simds = hweight32(~tmp);

sys/dev/pci/drm/radeon/ni.c

1112

if ((rdev->config.cayman.max_backends_per_se == 1) &&

sys/dev/pci/drm/radeon/ni.c

1124

rdev->config.cayman.max_backends_per_se *

sys/dev/pci/drm/radeon/ni.c

1125

rdev->config.cayman.max_shader_engines,

sys/dev/pci/drm/radeon/ni.c

1128

rdev->config.cayman.backend_map = tmp;

sys/dev/pci/drm/radeon/ni.c

1132

for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)

sys/dev/pci/drm/radeon/ni.c

1154

smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);

sys/dev/pci/drm/radeon/ni.c

1170

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |

sys/dev/pci/drm/radeon/ni.c

1171

POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |

sys/dev/pci/drm/radeon/ni.c

1172

SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));

sys/dev/pci/drm/radeon/ni.c

1174

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |

sys/dev/pci/drm/radeon/ni.c

1175

SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |

sys/dev/pci/drm/radeon/ni.c

1176

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));

sys/dev/pci/drm/radeon/ni.c

1183

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |

sys/dev/pci/drm/radeon/ni.c

1537

radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);

sys/dev/pci/drm/radeon/ni.c

880

rdev->config.cayman.max_shader_engines = 2;

sys/dev/pci/drm/radeon/ni.c

881

rdev->config.cayman.max_pipes_per_simd = 4;

sys/dev/pci/drm/radeon/ni.c

882

rdev->config.cayman.max_tile_pipes = 8;

sys/dev/pci/drm/radeon/ni.c

883

rdev->config.cayman.max_simds_per_se = 12;

sys/dev/pci/drm/radeon/ni.c

884

rdev->config.cayman.max_backends_per_se = 4;

sys/dev/pci/drm/radeon/ni.c

885

rdev->config.cayman.max_texture_channel_caches = 8;

sys/dev/pci/drm/radeon/ni.c

886

rdev->config.cayman.max_gprs = 256;

sys/dev/pci/drm/radeon/ni.c

887

rdev->config.cayman.max_threads = 256;

sys/dev/pci/drm/radeon/ni.c

888

rdev->config.cayman.max_gs_threads = 32;

sys/dev/pci/drm/radeon/ni.c

889

rdev->config.cayman.max_stack_entries = 512;

sys/dev/pci/drm/radeon/ni.c

890

rdev->config.cayman.sx_num_of_sets = 8;

sys/dev/pci/drm/radeon/ni.c

891

rdev->config.cayman.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/ni.c

892

rdev->config.cayman.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/ni.c

893

rdev->config.cayman.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/ni.c

894

rdev->config.cayman.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/ni.c

895

rdev->config.cayman.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/ni.c

897

rdev->config.cayman.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/ni.c

898

rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/ni.c

899

rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/ni.c

904

rdev->config.cayman.max_shader_engines = 1;

sys/dev/pci/drm/radeon/ni.c

905

rdev->config.cayman.max_pipes_per_simd = 4;

sys/dev/pci/drm/radeon/ni.c

906

rdev->config.cayman.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/ni.c

921

rdev->config.cayman.max_simds_per_se = 6;

sys/dev/pci/drm/radeon/ni.c

922

rdev->config.cayman.max_backends_per_se = 2;

sys/dev/pci/drm/radeon/ni.c

923

rdev->config.cayman.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/ni.c

924

rdev->config.cayman.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/ni.c

925

rdev->config.cayman.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/ni.c

926

rdev->config.cayman.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/ni.c

935

rdev->config.cayman.max_simds_per_se = 4;

sys/dev/pci/drm/radeon/ni.c

936

rdev->config.cayman.max_backends_per_se = 2;

sys/dev/pci/drm/radeon/ni.c

937

rdev->config.cayman.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/ni.c

938

rdev->config.cayman.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/ni.c

939

rdev->config.cayman.sx_max_export_pos_size = 64;

sys/dev/pci/drm/radeon/ni.c

940

rdev->config.cayman.sx_max_export_smx_size = 192;

sys/dev/pci/drm/radeon/ni.c

949

rdev->config.cayman.max_simds_per_se = 3;

sys/dev/pci/drm/radeon/ni.c

950

rdev->config.cayman.max_backends_per_se = 1;

sys/dev/pci/drm/radeon/ni.c

951

rdev->config.cayman.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/ni.c

952

rdev->config.cayman.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/ni.c

953

rdev->config.cayman.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/ni.c

954

rdev->config.cayman.sx_max_export_smx_size = 96;

sys/dev/pci/drm/radeon/ni.c

956

rdev->config.cayman.max_simds_per_se = 2;

sys/dev/pci/drm/radeon/ni.c

957

rdev->config.cayman.max_backends_per_se = 1;

sys/dev/pci/drm/radeon/ni.c

958

rdev->config.cayman.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/ni.c

959

rdev->config.cayman.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/ni.c

960

rdev->config.cayman.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/ni.c

961

rdev->config.cayman.sx_max_export_smx_size = 96;

sys/dev/pci/drm/radeon/ni.c

963

rdev->config.cayman.max_texture_channel_caches = 2;

sys/dev/pci/drm/radeon/ni.c

964

rdev->config.cayman.max_gprs = 256;

sys/dev/pci/drm/radeon/ni.c

965

rdev->config.cayman.max_threads = 256;

sys/dev/pci/drm/radeon/ni.c

966

rdev->config.cayman.max_gs_threads = 32;

sys/dev/pci/drm/radeon/ni.c

967

rdev->config.cayman.max_stack_entries = 512;

sys/dev/pci/drm/radeon/ni.c

968

rdev->config.cayman.sx_num_of_sets = 8;

sys/dev/pci/drm/radeon/ni.c

969

rdev->config.cayman.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/ni.c

971

rdev->config.cayman.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/ni.c

972

rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/ni.c

973

rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/ni.c

997

rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/pci/drm/radeon/ni.c

998

if (rdev->config.cayman.mem_row_size_in_kb > 4)

sys/dev/pci/drm/radeon/ni.c

999

rdev->config.cayman.mem_row_size_in_kb = 4;

sys/dev/pci/drm/radeon/r100.c

2081

p->rdev->config.r100.reg_safe_bm,

sys/dev/pci/drm/radeon/r100.c

2082

p->rdev->config.r100.reg_safe_bm_size,

sys/dev/pci/drm/radeon/r100.c

2086

p->rdev->config.r100.reg_safe_bm,

sys/dev/pci/drm/radeon/r100.c

2087

p->rdev->config.r100.reg_safe_bm_size,

sys/dev/pci/drm/radeon/r100.c

2938

rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;

sys/dev/pci/drm/radeon/r100.c

2939

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);

sys/dev/pci/drm/radeon/r100.c

2941

rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;

sys/dev/pci/drm/radeon/r100.c

2942

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);

sys/dev/pci/drm/radeon/r100.c

3938

rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/r100.c

861

radeon_ring_write(ring, rdev->config.r100.hdp_cntl |

sys/dev/pci/drm/radeon/r100.c

864

radeon_ring_write(ring, rdev->config.r100.hdp_cntl);

sys/dev/pci/drm/radeon/r200.c

548

rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;

sys/dev/pci/drm/radeon/r200.c

549

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);

sys/dev/pci/drm/radeon/r300.c

1301

p->rdev->config.r300.reg_safe_bm,

sys/dev/pci/drm/radeon/r300.c

1302

p->rdev->config.r300.reg_safe_bm_size,

sys/dev/pci/drm/radeon/r300.c

1323

rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;

sys/dev/pci/drm/radeon/r300.c

1324

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);

sys/dev/pci/drm/radeon/r300.c

1421

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/r300.c

235

radeon_ring_write(ring, rdev->config.r300.hdp_cntl |

sys/dev/pci/drm/radeon/r300.c

238

radeon_ring_write(ring, rdev->config.r300.hdp_cntl);

sys/dev/pci/drm/radeon/r420.c

218

radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);

sys/dev/pci/drm/radeon/r420.c

222

radeon_ring_write(ring, rdev->config.r300.resync_scratch);

sys/dev/pci/drm/radeon/r420.c

240

radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);

sys/dev/pci/drm/radeon/r420.c

286

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/r420.c

86

rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;

sys/dev/pci/drm/radeon/r420.c

87

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);

sys/dev/pci/drm/radeon/r520.c

203

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/r600.c

2004

rdev->config.r600.tiling_group_size = 256;

sys/dev/pci/drm/radeon/r600.c

2007

rdev->config.r600.max_pipes = 4;

sys/dev/pci/drm/radeon/r600.c

2008

rdev->config.r600.max_tile_pipes = 8;

sys/dev/pci/drm/radeon/r600.c

2009

rdev->config.r600.max_simds = 4;

sys/dev/pci/drm/radeon/r600.c

2010

rdev->config.r600.max_backends = 4;

sys/dev/pci/drm/radeon/r600.c

2011

rdev->config.r600.max_gprs = 256;

sys/dev/pci/drm/radeon/r600.c

2012

rdev->config.r600.max_threads = 192;

sys/dev/pci/drm/radeon/r600.c

2013

rdev->config.r600.max_stack_entries = 256;

sys/dev/pci/drm/radeon/r600.c

2014

rdev->config.r600.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/r600.c

2015

rdev->config.r600.max_gs_threads = 16;

sys/dev/pci/drm/radeon/r600.c

2016

rdev->config.r600.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/r600.c

2017

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/pci/drm/radeon/r600.c

2018

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/pci/drm/radeon/r600.c

2019

rdev->config.r600.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/r600.c

2023

rdev->config.r600.max_pipes = 2;

sys/dev/pci/drm/radeon/r600.c

2024

rdev->config.r600.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/r600.c

2025

rdev->config.r600.max_simds = 3;

sys/dev/pci/drm/radeon/r600.c

2026

rdev->config.r600.max_backends = 1;

sys/dev/pci/drm/radeon/r600.c

2027

rdev->config.r600.max_gprs = 128;

sys/dev/pci/drm/radeon/r600.c

2028

rdev->config.r600.max_threads = 192;

sys/dev/pci/drm/radeon/r600.c

2029

rdev->config.r600.max_stack_entries = 128;

sys/dev/pci/drm/radeon/r600.c

2030

rdev->config.r600.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/r600.c

2031

rdev->config.r600.max_gs_threads = 4;

sys/dev/pci/drm/radeon/r600.c

2032

rdev->config.r600.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/r600.c

2033

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/pci/drm/radeon/r600.c

2034

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/pci/drm/radeon/r600.c

2035

rdev->config.r600.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/r600.c

2041

rdev->config.r600.max_pipes = 1;

sys/dev/pci/drm/radeon/r600.c

2042

rdev->config.r600.max_tile_pipes = 1;

sys/dev/pci/drm/radeon/r600.c

2043

rdev->config.r600.max_simds = 2;

sys/dev/pci/drm/radeon/r600.c

2044

rdev->config.r600.max_backends = 1;

sys/dev/pci/drm/radeon/r600.c

2045

rdev->config.r600.max_gprs = 128;

sys/dev/pci/drm/radeon/r600.c

2046

rdev->config.r600.max_threads = 192;

sys/dev/pci/drm/radeon/r600.c

2047

rdev->config.r600.max_stack_entries = 128;

sys/dev/pci/drm/radeon/r600.c

2048

rdev->config.r600.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/r600.c

2049

rdev->config.r600.max_gs_threads = 4;

sys/dev/pci/drm/radeon/r600.c

2050

rdev->config.r600.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/r600.c

2051

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/pci/drm/radeon/r600.c

2052

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/pci/drm/radeon/r600.c

2053

rdev->config.r600.sq_num_cf_insts = 1;

sys/dev/pci/drm/radeon/r600.c

2056

rdev->config.r600.max_pipes = 4;

sys/dev/pci/drm/radeon/r600.c

2057

rdev->config.r600.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/r600.c

2058

rdev->config.r600.max_simds = 4;

sys/dev/pci/drm/radeon/r600.c

2059

rdev->config.r600.max_backends = 4;

sys/dev/pci/drm/radeon/r600.c

2060

rdev->config.r600.max_gprs = 192;

sys/dev/pci/drm/radeon/r600.c

2061

rdev->config.r600.max_threads = 192;

sys/dev/pci/drm/radeon/r600.c

2062

rdev->config.r600.max_stack_entries = 256;

sys/dev/pci/drm/radeon/r600.c

2063

rdev->config.r600.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/r600.c

2064

rdev->config.r600.max_gs_threads = 16;

sys/dev/pci/drm/radeon/r600.c

2065

rdev->config.r600.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/r600.c

2066

rdev->config.r600.sx_max_export_pos_size = 16;

sys/dev/pci/drm/radeon/r600.c

2067

rdev->config.r600.sx_max_export_smx_size = 128;

sys/dev/pci/drm/radeon/r600.c

2068

rdev->config.r600.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/r600.c

2088

switch (rdev->config.r600.max_tile_pipes) {

sys/dev/pci/drm/radeon/r600.c

2104

rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;

sys/dev/pci/drm/radeon/r600.c

2105

rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);

sys/dev/pci/drm/radeon/r600.c

2120

tmp = rdev->config.r600.max_simds -

sys/dev/pci/drm/radeon/r600.c

2122

rdev->config.r600.active_simds = tmp;

sys/dev/pci/drm/radeon/r600.c

2126

for (i = 0; i < rdev->config.r600.max_backends; i++)

sys/dev/pci/drm/radeon/r600.c

2130

for (i = 0; i < rdev->config.r600.max_backends; i++)

sys/dev/pci/drm/radeon/r600.c

2134

tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,

sys/dev/pci/drm/radeon/r600.c

2137

rdev->config.r600.backend_map = tmp;

sys/dev/pci/drm/radeon/r600.c

2139

rdev->config.r600.tile_config = tiling_config;

sys/dev/pci/drm/radeon/r600.c

2313

tmp = rdev->config.r600.max_pipes * 16;

sys/dev/pci/drm/radeon/r600.c

2701

radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);

sys/dev/pci/drm/radeon/r600.c

2704

radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);

sys/dev/pci/drm/radeon/r600_cs.c

2290

track->npipes = p->rdev->config.r600.tiling_npipes;

sys/dev/pci/drm/radeon/r600_cs.c

2291

track->nbanks = p->rdev->config.r600.tiling_nbanks;

sys/dev/pci/drm/radeon/r600_cs.c

2292

track->group_size = p->rdev->config.r600.tiling_group_size;

sys/dev/pci/drm/radeon/r600_cs.c

2294

track->npipes = p->rdev->config.rv770.tiling_npipes;

sys/dev/pci/drm/radeon/r600_cs.c

2295

track->nbanks = p->rdev->config.rv770.tiling_nbanks;

sys/dev/pci/drm/radeon/r600_cs.c

2296

track->group_size = p->rdev->config.rv770.tiling_group_size;

sys/dev/pci/drm/radeon/radeon.h

2351

union radeon_asic_config config;

sys/dev/pci/drm/radeon/radeon_kms.c

303

*value = rdev->config.cik.tile_config;

sys/dev/pci/drm/radeon/radeon_kms.c

305

*value = rdev->config.si.tile_config;

sys/dev/pci/drm/radeon/radeon_kms.c

307

*value = rdev->config.cayman.tile_config;

sys/dev/pci/drm/radeon/radeon_kms.c

309

*value = rdev->config.evergreen.tile_config;

sys/dev/pci/drm/radeon/radeon_kms.c

311

*value = rdev->config.rv770.tile_config;

sys/dev/pci/drm/radeon/radeon_kms.c

313

*value = rdev->config.r600.tile_config;

sys/dev/pci/drm/radeon/radeon_kms.c

357

*value = rdev->config.cik.max_backends_per_se *

sys/dev/pci/drm/radeon/radeon_kms.c

358

rdev->config.cik.max_shader_engines;

sys/dev/pci/drm/radeon/radeon_kms.c

360

*value = rdev->config.si.max_backends_per_se *

sys/dev/pci/drm/radeon/radeon_kms.c

361

rdev->config.si.max_shader_engines;

sys/dev/pci/drm/radeon/radeon_kms.c

363

*value = rdev->config.cayman.max_backends_per_se *

sys/dev/pci/drm/radeon/radeon_kms.c

364

rdev->config.cayman.max_shader_engines;

sys/dev/pci/drm/radeon/radeon_kms.c

366

*value = rdev->config.evergreen.max_backends;

sys/dev/pci/drm/radeon/radeon_kms.c

368

*value = rdev->config.rv770.max_backends;

sys/dev/pci/drm/radeon/radeon_kms.c

370

*value = rdev->config.r600.max_backends;

sys/dev/pci/drm/radeon/radeon_kms.c

377

*value = rdev->config.cik.max_tile_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

379

*value = rdev->config.si.max_tile_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

381

*value = rdev->config.cayman.max_tile_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

383

*value = rdev->config.evergreen.max_tile_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

385

*value = rdev->config.rv770.max_tile_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

387

*value = rdev->config.r600.max_tile_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

397

*value = rdev->config.cik.backend_map;

sys/dev/pci/drm/radeon/radeon_kms.c

399

*value = rdev->config.si.backend_map;

sys/dev/pci/drm/radeon/radeon_kms.c

401

*value = rdev->config.cayman.backend_map;

sys/dev/pci/drm/radeon/radeon_kms.c

403

*value = rdev->config.evergreen.backend_map;

sys/dev/pci/drm/radeon/radeon_kms.c

405

*value = rdev->config.rv770.backend_map;

sys/dev/pci/drm/radeon/radeon_kms.c

407

*value = rdev->config.r600.backend_map;

sys/dev/pci/drm/radeon/radeon_kms.c

426

*value = rdev->config.cik.max_cu_per_sh;

sys/dev/pci/drm/radeon/radeon_kms.c

428

*value = rdev->config.si.max_cu_per_sh;

sys/dev/pci/drm/radeon/radeon_kms.c

430

*value = rdev->config.cayman.max_pipes_per_simd;

sys/dev/pci/drm/radeon/radeon_kms.c

432

*value = rdev->config.evergreen.max_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

434

*value = rdev->config.rv770.max_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

436

*value = rdev->config.r600.max_pipes;

sys/dev/pci/drm/radeon/radeon_kms.c

452

*value = rdev->config.cik.max_shader_engines;

sys/dev/pci/drm/radeon/radeon_kms.c

454

*value = rdev->config.si.max_shader_engines;

sys/dev/pci/drm/radeon/radeon_kms.c

456

*value = rdev->config.cayman.max_shader_engines;

sys/dev/pci/drm/radeon/radeon_kms.c

458

*value = rdev->config.evergreen.num_ses;

sys/dev/pci/drm/radeon/radeon_kms.c

464

*value = rdev->config.cik.max_sh_per_se;

sys/dev/pci/drm/radeon/radeon_kms.c

466

*value = rdev->config.si.max_sh_per_se;

sys/dev/pci/drm/radeon/radeon_kms.c

499

value = rdev->config.cik.tile_mode_array;

sys/dev/pci/drm/radeon/radeon_kms.c

502

value = rdev->config.si.tile_mode_array;

sys/dev/pci/drm/radeon/radeon_kms.c

511

value = rdev->config.cik.macrotile_mode_array;

sys/dev/pci/drm/radeon/radeon_kms.c

523

*value = rdev->config.cik.backend_enable_mask;

sys/dev/pci/drm/radeon/radeon_kms.c

525

*value = rdev->config.si.backend_enable_mask;

sys/dev/pci/drm/radeon/radeon_kms.c

563

*value = rdev->config.cik.active_cus;

sys/dev/pci/drm/radeon/radeon_kms.c

565

*value = rdev->config.si.active_cus;

sys/dev/pci/drm/radeon/radeon_kms.c

567

*value = rdev->config.cayman.active_simds;

sys/dev/pci/drm/radeon/radeon_kms.c

569

*value = rdev->config.evergreen.active_simds;

sys/dev/pci/drm/radeon/radeon_kms.c

571

*value = rdev->config.rv770.active_simds;

sys/dev/pci/drm/radeon/radeon_kms.c

573

*value = rdev->config.r600.active_simds;

sys/dev/pci/drm/radeon/rs400.c

457

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/rs600.c

1019

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/rs600.c

956

rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;

sys/dev/pci/drm/radeon/rs600.c

957

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);

sys/dev/pci/drm/radeon/rs690.c

730

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/rv515.c

523

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

sys/dev/pci/drm/radeon/rv515.c

583

rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;

sys/dev/pci/drm/radeon/rv515.c

584

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);

sys/dev/pci/drm/radeon/rv770.c

1191

rdev->config.rv770.tiling_group_size = 256;

sys/dev/pci/drm/radeon/rv770.c

1194

rdev->config.rv770.max_pipes = 4;

sys/dev/pci/drm/radeon/rv770.c

1195

rdev->config.rv770.max_tile_pipes = 8;

sys/dev/pci/drm/radeon/rv770.c

1196

rdev->config.rv770.max_simds = 10;

sys/dev/pci/drm/radeon/rv770.c

1197

rdev->config.rv770.max_backends = 4;

sys/dev/pci/drm/radeon/rv770.c

1198

rdev->config.rv770.max_gprs = 256;

sys/dev/pci/drm/radeon/rv770.c

1199

rdev->config.rv770.max_threads = 248;

sys/dev/pci/drm/radeon/rv770.c

1200

rdev->config.rv770.max_stack_entries = 512;

sys/dev/pci/drm/radeon/rv770.c

1201

rdev->config.rv770.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/rv770.c

1202

rdev->config.rv770.max_gs_threads = 16 * 2;

sys/dev/pci/drm/radeon/rv770.c

1203

rdev->config.rv770.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/rv770.c

1204

rdev->config.rv770.sx_max_export_pos_size = 16;

sys/dev/pci/drm/radeon/rv770.c

1205

rdev->config.rv770.sx_max_export_smx_size = 112;

sys/dev/pci/drm/radeon/rv770.c

1206

rdev->config.rv770.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/rv770.c

1208

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/pci/drm/radeon/rv770.c

1209

rdev->config.rv770.sc_prim_fifo_size = 0xF9;

sys/dev/pci/drm/radeon/rv770.c

1210

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/rv770.c

1211

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/pci/drm/radeon/rv770.c

1214

rdev->config.rv770.max_pipes = 2;

sys/dev/pci/drm/radeon/rv770.c

1215

rdev->config.rv770.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/rv770.c

1216

rdev->config.rv770.max_simds = 8;

sys/dev/pci/drm/radeon/rv770.c

1217

rdev->config.rv770.max_backends = 2;

sys/dev/pci/drm/radeon/rv770.c

1218

rdev->config.rv770.max_gprs = 128;

sys/dev/pci/drm/radeon/rv770.c

1219

rdev->config.rv770.max_threads = 248;

sys/dev/pci/drm/radeon/rv770.c

1220

rdev->config.rv770.max_stack_entries = 256;

sys/dev/pci/drm/radeon/rv770.c

1221

rdev->config.rv770.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/rv770.c

1222

rdev->config.rv770.max_gs_threads = 16 * 2;

sys/dev/pci/drm/radeon/rv770.c

1223

rdev->config.rv770.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/rv770.c

1224

rdev->config.rv770.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/rv770.c

1225

rdev->config.rv770.sx_max_export_smx_size = 224;

sys/dev/pci/drm/radeon/rv770.c

1226

rdev->config.rv770.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/rv770.c

1228

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/pci/drm/radeon/rv770.c

1229

rdev->config.rv770.sc_prim_fifo_size = 0xf9;

sys/dev/pci/drm/radeon/rv770.c

1230

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/rv770.c

1231

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/pci/drm/radeon/rv770.c

1232

if (rdev->config.rv770.sx_max_export_pos_size > 16) {

sys/dev/pci/drm/radeon/rv770.c

1233

rdev->config.rv770.sx_max_export_pos_size -= 16;

sys/dev/pci/drm/radeon/rv770.c

1234

rdev->config.rv770.sx_max_export_smx_size += 16;

sys/dev/pci/drm/radeon/rv770.c

1238

rdev->config.rv770.max_pipes = 2;

sys/dev/pci/drm/radeon/rv770.c

1239

rdev->config.rv770.max_tile_pipes = 2;

sys/dev/pci/drm/radeon/rv770.c

1240

rdev->config.rv770.max_simds = 2;

sys/dev/pci/drm/radeon/rv770.c

1241

rdev->config.rv770.max_backends = 1;

sys/dev/pci/drm/radeon/rv770.c

1242

rdev->config.rv770.max_gprs = 256;

sys/dev/pci/drm/radeon/rv770.c

1243

rdev->config.rv770.max_threads = 192;

sys/dev/pci/drm/radeon/rv770.c

1244

rdev->config.rv770.max_stack_entries = 256;

sys/dev/pci/drm/radeon/rv770.c

1245

rdev->config.rv770.max_hw_contexts = 4;

sys/dev/pci/drm/radeon/rv770.c

1246

rdev->config.rv770.max_gs_threads = 8 * 2;

sys/dev/pci/drm/radeon/rv770.c

1247

rdev->config.rv770.sx_max_export_size = 128;

sys/dev/pci/drm/radeon/rv770.c

1248

rdev->config.rv770.sx_max_export_pos_size = 16;

sys/dev/pci/drm/radeon/rv770.c

1249

rdev->config.rv770.sx_max_export_smx_size = 112;

sys/dev/pci/drm/radeon/rv770.c

1250

rdev->config.rv770.sq_num_cf_insts = 1;

sys/dev/pci/drm/radeon/rv770.c

1252

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/pci/drm/radeon/rv770.c

1253

rdev->config.rv770.sc_prim_fifo_size = 0x40;

sys/dev/pci/drm/radeon/rv770.c

1254

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/rv770.c

1255

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/pci/drm/radeon/rv770.c

1258

rdev->config.rv770.max_pipes = 4;

sys/dev/pci/drm/radeon/rv770.c

1259

rdev->config.rv770.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/rv770.c

1260

rdev->config.rv770.max_simds = 8;

sys/dev/pci/drm/radeon/rv770.c

1261

rdev->config.rv770.max_backends = 4;

sys/dev/pci/drm/radeon/rv770.c

1262

rdev->config.rv770.max_gprs = 256;

sys/dev/pci/drm/radeon/rv770.c

1263

rdev->config.rv770.max_threads = 248;

sys/dev/pci/drm/radeon/rv770.c

1264

rdev->config.rv770.max_stack_entries = 512;

sys/dev/pci/drm/radeon/rv770.c

1265

rdev->config.rv770.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/rv770.c

1266

rdev->config.rv770.max_gs_threads = 16 * 2;

sys/dev/pci/drm/radeon/rv770.c

1267

rdev->config.rv770.sx_max_export_size = 256;

sys/dev/pci/drm/radeon/rv770.c

1268

rdev->config.rv770.sx_max_export_pos_size = 32;

sys/dev/pci/drm/radeon/rv770.c

1269

rdev->config.rv770.sx_max_export_smx_size = 224;

sys/dev/pci/drm/radeon/rv770.c

1270

rdev->config.rv770.sq_num_cf_insts = 2;

sys/dev/pci/drm/radeon/rv770.c

1272

rdev->config.rv770.sx_num_of_sets = 7;

sys/dev/pci/drm/radeon/rv770.c

1273

rdev->config.rv770.sc_prim_fifo_size = 0x100;

sys/dev/pci/drm/radeon/rv770.c

1274

rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/rv770.c

1275

rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;

sys/dev/pci/drm/radeon/rv770.c

1277

if (rdev->config.rv770.sx_max_export_pos_size > 16) {

sys/dev/pci/drm/radeon/rv770.c

1278

rdev->config.rv770.sx_max_export_pos_size -= 16;

sys/dev/pci/drm/radeon/rv770.c

1279

rdev->config.rv770.sx_max_export_smx_size += 16;

sys/dev/pci/drm/radeon/rv770.c

1317

tmp = rdev->config.rv770.max_simds -

sys/dev/pci/drm/radeon/rv770.c

1319

rdev->config.rv770.active_simds = tmp;

sys/dev/pci/drm/radeon/rv770.c

1321

switch (rdev->config.rv770.max_tile_pipes) {

sys/dev/pci/drm/radeon/rv770.c

1336

rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;

sys/dev/pci/drm/radeon/rv770.c

1340

for (i = 0; i < rdev->config.rv770.max_backends; i++)

sys/dev/pci/drm/radeon/rv770.c

1344

for (i = 0; i < rdev->config.rv770.max_backends; i++)

sys/dev/pci/drm/radeon/rv770.c

1348

tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,

sys/dev/pci/drm/radeon/rv770.c

1351

rdev->config.rv770.backend_map = tmp;

sys/dev/pci/drm/radeon/rv770.c

1361

rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);

sys/dev/pci/drm/radeon/rv770.c

1374

rdev->config.rv770.tile_config = gb_tiling_config;

sys/dev/pci/drm/radeon/rv770.c

1412

smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);

sys/dev/pci/drm/radeon/rv770.c

1445

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |

sys/dev/pci/drm/radeon/rv770.c

1446

POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |

sys/dev/pci/drm/radeon/rv770.c

1447

SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));

sys/dev/pci/drm/radeon/rv770.c

1449

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |

sys/dev/pci/drm/radeon/rv770.c

1450

SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |

sys/dev/pci/drm/radeon/rv770.c

1451

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));

sys/dev/pci/drm/radeon/rv770.c

1461

sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |

sys/dev/pci/drm/radeon/rv770.c

1498

WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |

sys/dev/pci/drm/radeon/rv770.c

1499

NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |

sys/dev/pci/drm/radeon/rv770.c

1500

NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));

sys/dev/pci/drm/radeon/rv770.c

1502

WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |

sys/dev/pci/drm/radeon/rv770.c

1503

NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));

sys/dev/pci/drm/radeon/rv770.c

1505

sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |

sys/dev/pci/drm/radeon/rv770.c

1506

NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |

sys/dev/pci/drm/radeon/rv770.c

1507

NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));

sys/dev/pci/drm/radeon/rv770.c

1508

if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)

sys/dev/pci/drm/radeon/rv770.c

1509

sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);

sys/dev/pci/drm/radeon/rv770.c

1511

sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);

sys/dev/pci/drm/radeon/rv770.c

1514

WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |

sys/dev/pci/drm/radeon/rv770.c

1515

NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));

sys/dev/pci/drm/radeon/rv770.c

1517

WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |

sys/dev/pci/drm/radeon/rv770.c

1518

NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));

sys/dev/pci/drm/radeon/rv770.c

1520

sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |

sys/dev/pci/drm/radeon/rv770.c

1521

SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |

sys/dev/pci/drm/radeon/rv770.c

1522

SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |

sys/dev/pci/drm/radeon/rv770.c

1523

SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));

sys/dev/pci/drm/radeon/rv770.c

1557

num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;

sys/dev/pci/drm/radeon/si.c

2471

u32 *tile = rdev->config.si.tile_mode_array;

sys/dev/pci/drm/radeon/si.c

2473

ARRAY_SIZE(rdev->config.si.tile_mode_array);

sys/dev/pci/drm/radeon/si.c

2476

switch (rdev->config.si.mem_row_size_in_kb) {

sys/dev/pci/drm/radeon/si.c

3044

rdev->config.si.backend_enable_mask = enabled_rbs;

sys/dev/pci/drm/radeon/si.c

3080

rdev->config.si.max_shader_engines = 2;

sys/dev/pci/drm/radeon/si.c

3081

rdev->config.si.max_tile_pipes = 12;

sys/dev/pci/drm/radeon/si.c

3082

rdev->config.si.max_cu_per_sh = 8;

sys/dev/pci/drm/radeon/si.c

3083

rdev->config.si.max_sh_per_se = 2;

sys/dev/pci/drm/radeon/si.c

3084

rdev->config.si.max_backends_per_se = 4;

sys/dev/pci/drm/radeon/si.c

3085

rdev->config.si.max_texture_channel_caches = 12;

sys/dev/pci/drm/radeon/si.c

3086

rdev->config.si.max_gprs = 256;

sys/dev/pci/drm/radeon/si.c

3087

rdev->config.si.max_gs_threads = 32;

sys/dev/pci/drm/radeon/si.c

3088

rdev->config.si.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/si.c

3090

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/si.c

3091

rdev->config.si.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/radeon/si.c

3092

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/si.c

3093

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/si.c

3097

rdev->config.si.max_shader_engines = 2;

sys/dev/pci/drm/radeon/si.c

3098

rdev->config.si.max_tile_pipes = 8;

sys/dev/pci/drm/radeon/si.c

3099

rdev->config.si.max_cu_per_sh = 5;

sys/dev/pci/drm/radeon/si.c

3100

rdev->config.si.max_sh_per_se = 2;

sys/dev/pci/drm/radeon/si.c

3101

rdev->config.si.max_backends_per_se = 4;

sys/dev/pci/drm/radeon/si.c

3102

rdev->config.si.max_texture_channel_caches = 8;

sys/dev/pci/drm/radeon/si.c

3103

rdev->config.si.max_gprs = 256;

sys/dev/pci/drm/radeon/si.c

3104

rdev->config.si.max_gs_threads = 32;

sys/dev/pci/drm/radeon/si.c

3105

rdev->config.si.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/si.c

3107

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/si.c

3108

rdev->config.si.sc_prim_fifo_size_backend = 0x100;

sys/dev/pci/drm/radeon/si.c

3109

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/si.c

3110

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/si.c

3115

rdev->config.si.max_shader_engines = 1;

sys/dev/pci/drm/radeon/si.c

3116

rdev->config.si.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/si.c

3117

rdev->config.si.max_cu_per_sh = 5;

sys/dev/pci/drm/radeon/si.c

3118

rdev->config.si.max_sh_per_se = 2;

sys/dev/pci/drm/radeon/si.c

3119

rdev->config.si.max_backends_per_se = 4;

sys/dev/pci/drm/radeon/si.c

3120

rdev->config.si.max_texture_channel_caches = 4;

sys/dev/pci/drm/radeon/si.c

3121

rdev->config.si.max_gprs = 256;

sys/dev/pci/drm/radeon/si.c

3122

rdev->config.si.max_gs_threads = 32;

sys/dev/pci/drm/radeon/si.c

3123

rdev->config.si.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/si.c

3125

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/si.c

3126

rdev->config.si.sc_prim_fifo_size_backend = 0x40;

sys/dev/pci/drm/radeon/si.c

3127

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/si.c

3128

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/si.c

3132

rdev->config.si.max_shader_engines = 1;

sys/dev/pci/drm/radeon/si.c

3133

rdev->config.si.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/si.c

3134

rdev->config.si.max_cu_per_sh = 6;

sys/dev/pci/drm/radeon/si.c

3135

rdev->config.si.max_sh_per_se = 1;

sys/dev/pci/drm/radeon/si.c

3136

rdev->config.si.max_backends_per_se = 2;

sys/dev/pci/drm/radeon/si.c

3137

rdev->config.si.max_texture_channel_caches = 4;

sys/dev/pci/drm/radeon/si.c

3138

rdev->config.si.max_gprs = 256;

sys/dev/pci/drm/radeon/si.c

3139

rdev->config.si.max_gs_threads = 16;

sys/dev/pci/drm/radeon/si.c

3140

rdev->config.si.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/si.c

3142

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/si.c

3143

rdev->config.si.sc_prim_fifo_size_backend = 0x40;

sys/dev/pci/drm/radeon/si.c

3144

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/si.c

3145

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/si.c

3149

rdev->config.si.max_shader_engines = 1;

sys/dev/pci/drm/radeon/si.c

3150

rdev->config.si.max_tile_pipes = 4;

sys/dev/pci/drm/radeon/si.c

3151

rdev->config.si.max_cu_per_sh = 5;

sys/dev/pci/drm/radeon/si.c

3152

rdev->config.si.max_sh_per_se = 1;

sys/dev/pci/drm/radeon/si.c

3153

rdev->config.si.max_backends_per_se = 1;

sys/dev/pci/drm/radeon/si.c

3154

rdev->config.si.max_texture_channel_caches = 2;

sys/dev/pci/drm/radeon/si.c

3155

rdev->config.si.max_gprs = 256;

sys/dev/pci/drm/radeon/si.c

3156

rdev->config.si.max_gs_threads = 16;

sys/dev/pci/drm/radeon/si.c

3157

rdev->config.si.max_hw_contexts = 8;

sys/dev/pci/drm/radeon/si.c

3159

rdev->config.si.sc_prim_fifo_size_frontend = 0x20;

sys/dev/pci/drm/radeon/si.c

3160

rdev->config.si.sc_prim_fifo_size_backend = 0x40;

sys/dev/pci/drm/radeon/si.c

3161

rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

sys/dev/pci/drm/radeon/si.c

3162

rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

sys/dev/pci/drm/radeon/si.c

3187

rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;

sys/dev/pci/drm/radeon/si.c

3188

rdev->config.si.mem_max_burst_length_bytes = 256;

sys/dev/pci/drm/radeon/si.c

3190

rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

sys/dev/pci/drm/radeon/si.c

3191

if (rdev->config.si.mem_row_size_in_kb > 4)

sys/dev/pci/drm/radeon/si.c

3192

rdev->config.si.mem_row_size_in_kb = 4;

sys/dev/pci/drm/radeon/si.c

3194

rdev->config.si.shader_engine_tile_size = 32;

sys/dev/pci/drm/radeon/si.c

3195

rdev->config.si.num_gpus = 1;

sys/dev/pci/drm/radeon/si.c

3196

rdev->config.si.multi_gpu_tile_size = 64;

sys/dev/pci/drm/radeon/si.c

3200

switch (rdev->config.si.mem_row_size_in_kb) {

sys/dev/pci/drm/radeon/si.c

3220

rdev->config.si.tile_config = 0;

sys/dev/pci/drm/radeon/si.c

3221

switch (rdev->config.si.num_tile_pipes) {

sys/dev/pci/drm/radeon/si.c

3223

rdev->config.si.tile_config |= (0 << 0);

sys/dev/pci/drm/radeon/si.c

3226

rdev->config.si.tile_config |= (1 << 0);

sys/dev/pci/drm/radeon/si.c

3229

rdev->config.si.tile_config |= (2 << 0);

sys/dev/pci/drm/radeon/si.c

3234

rdev->config.si.tile_config |= (3 << 0);

sys/dev/pci/drm/radeon/si.c

3239

rdev->config.si.tile_config |= 0 << 4;

sys/dev/pci/drm/radeon/si.c

3242

rdev->config.si.tile_config |= 1 << 4;

sys/dev/pci/drm/radeon/si.c

3246

rdev->config.si.tile_config |= 2 << 4;

sys/dev/pci/drm/radeon/si.c

3249

rdev->config.si.tile_config |=

sys/dev/pci/drm/radeon/si.c

3251

rdev->config.si.tile_config |=

sys/dev/pci/drm/radeon/si.c

3268

si_setup_rb(rdev, rdev->config.si.max_shader_engines,

sys/dev/pci/drm/radeon/si.c

3269

rdev->config.si.max_sh_per_se,

sys/dev/pci/drm/radeon/si.c

3270

rdev->config.si.max_backends_per_se);

sys/dev/pci/drm/radeon/si.c

3272

si_setup_spi(rdev, rdev->config.si.max_shader_engines,

sys/dev/pci/drm/radeon/si.c

3273

rdev->config.si.max_sh_per_se,

sys/dev/pci/drm/radeon/si.c

3274

rdev->config.si.max_cu_per_sh);

sys/dev/pci/drm/radeon/si.c

3276

rdev->config.si.active_cus = 0;

sys/dev/pci/drm/radeon/si.c

3277

for (i = 0; i < rdev->config.si.max_shader_engines; i++) {

sys/dev/pci/drm/radeon/si.c

3278

for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {

sys/dev/pci/drm/radeon/si.c

3279

rdev->config.si.active_cus +=

sys/dev/pci/drm/radeon/si.c

3294

WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |

sys/dev/pci/drm/radeon/si.c

3295

SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |

sys/dev/pci/drm/radeon/si.c

3296

SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |

sys/dev/pci/drm/radeon/si.c

3297

SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));

sys/dev/pci/drm/radeon/si.c

3551

radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);

sys/dev/pci/drm/radeon/si.c

5294

for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {

sys/dev/pci/drm/radeon/si.c

5308

for (i = 0; i < rdev->config.si.max_shader_engines; i++) {

sys/dev/pci/drm/radeon/si.c

5309

for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {

sys/dev/pci/drm/radeon/si.c

5313

for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {

sys/dev/pci/if_iavf.c

1246

struct iavf_vc_queue_config_info *config;

sys/dev/pci/if_iavf.c

1257

iaq.iaq_datalen = htole16(sizeof(*config) +

sys/dev/pci/if_iavf.c

1261

config = IAVF_DMA_KVA(&sc->sc_scratch);

sys/dev/pci/if_iavf.c

1262

config->vsi_id = htole16(sc->sc_vsi_id);

sys/dev/pci/if_iavf.c

1263

config->num_queue_pairs = htole16(iavf_nqueues(sc));

sys/dev/pci/if_iavf.c

1269

txq = &config->qpair[i].txq;

sys/dev/pci/if_iavf.c

1277

rxq = &config->qpair[i].rxq;

sys/dev/pci/if_icereg.h

12970

uint32_t config; /* NVM command configuration */

sys/dev/pci/if_ipw.c

1813

struct ipw_configuration config;

sys/dev/pci/if_ipw.c

1862

config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK |

sys/dev/pci/if_ipw.c

1866

config.flags |= htole32(IPW_CFG_IBSS_AUTO_START);

sys/dev/pci/if_ipw.c

1869

config.flags |= htole32(IPW_CFG_PROMISCUOUS);

sys/dev/pci/if_ipw.c

1870

config.bss_chan = htole32(0x3fff); /* channels 1-14 */

sys/dev/pci/if_ipw.c

1871

config.ibss_chan = htole32(0x7ff); /* channels 1-11 */

sys/dev/pci/if_ipw.c

1872

DPRINTF(("Setting configuration 0x%x\n", config.flags));

sys/dev/pci/if_ipw.c

1873

error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config);

sys/dev/pci/if_iwi.c

1771

struct iwi_configuration config;

sys/dev/pci/if_iwi.c

1784

bzero(&config, sizeof config);

sys/dev/pci/if_iwi.c

1785

config.multicast_enabled = 1;

sys/dev/pci/if_iwi.c

1786

config.silence_threshold = 30;

sys/dev/pci/if_iwi.c

1787

config.report_noise = 1;

sys/dev/pci/if_iwi.c

1788

config.answer_pbreq =

sys/dev/pci/if_iwi.c

1794

error = iwi_cmd(sc, IWI_CMD_SET_CONFIG, &config, sizeof config, 0);

sys/dev/pci/if_iwi.c

2016

struct iwi_configuration config;

sys/dev/pci/if_iwi.c

2026

bzero(&config, sizeof config);

sys/dev/pci/if_iwi.c

2027

config.multicast_enabled = 1;

sys/dev/pci/if_iwi.c

2028

config.disable_unicast_decryption = 1;

sys/dev/pci/if_iwi.c

2029

config.disable_multicast_decryption = 1;

sys/dev/pci/if_iwi.c

2030

config.silence_threshold = 30;

sys/dev/pci/if_iwi.c

2031

config.report_noise = 1;

sys/dev/pci/if_iwi.c

2032

config.allow_mgt = 1;

sys/dev/pci/if_iwi.c

2033

config.answer_pbreq =

sys/dev/pci/if_iwi.c

2039

config.bg_autodetection = 1;

sys/dev/pci/if_iwi.c

2041

error = iwi_cmd(sc, IWI_CMD_SET_CONFIG, &config, sizeof config, 1);

sys/dev/pci/if_iwxreg.h

460

uint32_t config;

sys/dev/pci/if_ixl.c

699

uint8_t config;

sys/dev/spdmem.c

475

uint8_t config, rows, cols, cl;

sys/dev/spdmem.c

516

config = s->sm_data[SPDMEM_FPM_CONFIG];

sys/dev/spdmem.c

519

if (config == 1 || config == 2)

sys/dev/spdmem.c

546

uint8_t config;

sys/dev/spdmem.c

583

config = s->sm_data[SPDMEM_FPM_CONFIG];

sys/dev/spdmem.c

585

if ((config & 0x03) != 0)

sys/dev/spi/spivar.h

48

#define spi_config(sc, config) \

sys/dev/spi/spivar.h

49

(*(sc)->sc_config)((sc)->sc_cookie, (config))

sys/dev/usb/if_rsu.c

1035

bss->config.len = htole32(sizeof(bss->config));

sys/dev/usb/if_rsu.c

1036

bss->config.bintval = htole32(ni->ni_intval);

sys/dev/usb/if_rsu.c

1037

bss->config.dsconfig = htole32(ieee80211_chan2ieee(ic, ni->ni_chan));

sys/dev/usb/if_rsu.c

1061

ether_sprintf(bss->macaddr), letoh32(bss->config.dsconfig)));

sys/dev/usb/if_rsu.c

1097

letoh32(bss->config.dsconfig), letoh32(bss->inframode),

sys/dev/usb/if_rsureg.h

425

struct ndis_802_11_configuration config;

sys/dev/usb/usb_subr.c

1310

di->udi_config = dev->config;

sys/dev/usb/usb_subr.c

634

if (dev->config != USB_UNCONFIG_NO) {

sys/dev/usb/usb_subr.c

644

dev->config = USB_UNCONFIG_NO;

sys/dev/usb/usb_subr.c

772

dev->config = cdp->bConfigurationValue;

sys/dev/usb/usbdi.c

131

"power=%d langid=%d\n", dev->address, dev->config, dev->depth,

sys/dev/usb/usbdivar.h

148

u_int8_t config; /* current configuration # */

sys/dev/usb/uslhcom.c

277

uslhcom_set_config(struct uslhcom_softc *sc, struct uslhcom_uart_config *config)

sys/dev/usb/uslhcom.c

281

len = sizeof(*config);

sys/dev/usb/uslhcom.c

284

GET_SET_UART_CONFIG, config, len) != len;

sys/dev/usb/uslhcom.c

288

uslhcom_set_baud_rate(struct uslhcom_uart_config *config, u_int32_t baud_rate)

sys/dev/usb/uslhcom.c

290

config->baud_rate[0] = baud_rate >> 24;

sys/dev/usb/uslhcom.c

291

config->baud_rate[1] = baud_rate >> 16;

sys/dev/usb/uslhcom.c

292

config->baud_rate[2] = baud_rate >> 8;

sys/dev/usb/uslhcom.c

293

config->baud_rate[3] = baud_rate >> 0;

sys/dev/usb/uslhcom.c

297

uslhcom_create_config(struct uslhcom_uart_config *config, struct termios *t)

sys/dev/usb/uslhcom.c

303

uslhcom_set_baud_rate(config, t->c_ospeed);

sys/dev/usb/uslhcom.c

307

config->parity = UART_CONFIG_PARITY_ODD;

sys/dev/usb/uslhcom.c

309

config->parity = UART_CONFIG_PARITY_EVEN;

sys/dev/usb/uslhcom.c

311

config->parity = UART_CONFIG_PARITY_NONE;

sys/dev/usb/uslhcom.c

314

config->data_control = UART_CONFIG_DATA_CONTROL_HARD;

sys/dev/usb/uslhcom.c

316

config->data_control = UART_CONFIG_DATA_CONTROL_NONE;

sys/dev/usb/uslhcom.c

320

config->data_bits = UART_CONFIG_DATA_BITS_5;

sys/dev/usb/uslhcom.c

323

config->data_bits = UART_CONFIG_DATA_BITS_6;

sys/dev/usb/uslhcom.c

326

config->data_bits = UART_CONFIG_DATA_BITS_7;

sys/dev/usb/uslhcom.c

329

config->data_bits = UART_CONFIG_DATA_BITS_8;

sys/dev/usb/uslhcom.c

336

config->stop_bits = UART_CONFIG_STOP_BITS_2;

sys/dev/usb/uslhcom.c

338

config->stop_bits = UART_CONFIG_STOP_BITS_1;

sys/dev/usb/uslhcom.c

344

uslhcom_setup(struct uslhcom_softc *sc, struct uslhcom_uart_config *config)

sys/dev/usb/uslhcom.c

351

if (uslhcom_set_config(sc, config))

sys/dev/usb/uslhcom.c

405

struct uslhcom_uart_config config;

sys/dev/usb/uslhcom.c

411

ret = uslhcom_create_config(&config, t);

sys/dev/usb/uslhcom.c

415

ret = uslhcom_setup(sc, &config);

sys/dev/usb/uslhcom.c

426

struct uslhcom_uart_config config;

sys/dev/usb/uslhcom.c

434

uslhcom_set_baud_rate(&config, 9600);

sys/dev/usb/uslhcom.c

435

config.parity = UART_CONFIG_PARITY_NONE;

sys/dev/usb/uslhcom.c

436

config.data_control = UART_CONFIG_DATA_CONTROL_NONE;

sys/dev/usb/uslhcom.c

437

config.data_bits = UART_CONFIG_DATA_BITS_8;

sys/dev/usb/uslhcom.c

438

config.stop_bits = UART_CONFIG_STOP_BITS_1;

sys/dev/usb/uslhcom.c

440

ret = uslhcom_set_config(sc, &config);

sys/lib/libz/deflate.c

103

local const config configuration_table[2] = {

sys/lib/libz/deflate.c

108

local const config configuration_table[10] = {

sys/scsi/safte.c

229

struct safte_config *config = NULL;

sys/scsi/safte.c

235

config = dma_alloc(sizeof(*config), PR_NOWAIT);

sys/scsi/safte.c

236

if (config == NULL)

sys/scsi/safte.c

247

xs->data = (void *)config;

sys/scsi/safte.c

248

xs->datalen = sizeof(*config);

sys/scsi/safte.c

256

cmd->length = htobe16(sizeof(*config));

sys/scsi/safte.c

267

" alarm: %d celsius: %d ntherm: %d\n", DEVNAME(sc), config->nfans,

sys/scsi/safte.c

268

config->npwrsup, config->nslots, config->doorlock, config->ntemps,

sys/scsi/safte.c

269

config->alarm, SAFTE_CFG_CELSIUS(config->therm),

sys/scsi/safte.c

270

SAFTE_CFG_NTHERM(config->therm)));

sys/scsi/safte.c

272

sc->sc_encbuflen = config->nfans * sizeof(u_int8_t) + /* fan status */

sys/scsi/safte.c

273

config->npwrsup * sizeof(u_int8_t) + /* power supply status */

sys/scsi/safte.c

274

config->nslots * sizeof(u_int8_t) + /* device scsi id (lun) */

sys/scsi/safte.c

277

config->ntemps * sizeof(u_int8_t) + /* temp sensors */

sys/scsi/safte.c

286

sc->sc_nsensors = config->nfans + config->npwrsup + config->ntemps +

sys/scsi/safte.c

287

(config->doorlock ? 1 : 0) + (config->alarm ? 1 : 0);

sys/scsi/safte.c

304

for (i = 0; i < config->nfans; i++) {

sys/scsi/safte.c

313

j = config->nfans;

sys/scsi/safte.c

315

for (i = 0; i < config->npwrsup; i++) {

sys/scsi/safte.c

324

j += config->npwrsup;

sys/scsi/safte.c

327

sc->sc_nslots = config->nslots;

sys/scsi/safte.c

330

j += config->nslots;

sys/scsi/safte.c

332

if (config->doorlock) {

sys/scsi/safte.c

343

if (config->alarm) {

sys/scsi/safte.c

357

sc->sc_ntemps = (config->ntemps > 15) ? 15 : config->ntemps;

sys/scsi/safte.c

359

sc->sc_celsius = SAFTE_CFG_CELSIUS(config->therm);

sys/scsi/safte.c

360

for (i = 0; i < config->ntemps; i++) {

sys/scsi/safte.c

367

j += config->ntemps;

sys/scsi/safte.c

371

dma_free(config, sizeof(*config));

sys/sys/audioio.h

82

char config[MAX_AUDIO_DEV_LEN];

usr.bin/dig/lib/isc/unix/socket.c

528

goto config;

usr.bin/dig/lib/isc/unix/socket.c

561

config:

usr.bin/dig/lib/isc/unix/socket.c

726

goto config;

usr.bin/dig/lib/isc/unix/socket.c

754

config:

usr.bin/newsyslog/newsyslog.c

179

struct entrylist config, runlist;

usr.bin/newsyslog/newsyslog.c

192

TAILQ_INIT(&config);

usr.bin/newsyslog/newsyslog.c

195

ret = parse_file(&config, &listlen);

usr.bin/newsyslog/newsyslog.c

197

TAILQ_CONCAT(&runlist, &config, next);

usr.bin/newsyslog/newsyslog.c

202

TAILQ_FOREACH_SAFE(q, &config, next, tmp)

usr.bin/newsyslog/newsyslog.c

204

TAILQ_REMOVE(&config, q, next);

usr.bin/openssl/apps.c

1052

cnf = config;

usr.bin/openssl/apps.h

137

extern CONF *config;

usr.bin/openssl/openssl.c

342

CONF *config = NULL;

usr.bin/openssl/openssl.c

408

config = NCONF_new(NULL);

usr.bin/openssl/openssl.c

409

i = NCONF_load(config, p, &errline);

usr.bin/openssl/openssl.c

416

NCONF_free(config);

usr.bin/openssl/openssl.c

417

config = NULL;

usr.bin/openssl/openssl.c

420

NCONF_free(config);

usr.bin/openssl/openssl.c

451

if (config != NULL) {

usr.bin/openssl/openssl.c

452

NCONF_free(config);

usr.bin/openssl/openssl.c

453

config = NULL;

usr.bin/openssl/req.c

1098

if ((req_conf != NULL) && (req_conf != config))

usr.bin/openssl/req.c

605

req_conf = config;

usr.bin/ssh/ssh.c

1057

config = optarg;

usr.bin/ssh/ssh.c

122

char *config = NULL;

usr.bin/ssh/ssh.c

1313

config == NULL ? "" : " -F ",

usr.bin/ssh/ssh.c

1314

config == NULL ? "" : config,

usr.bin/ssh/ssh.c

559

if (config != NULL) {

usr.bin/ssh/ssh.c

560

if (strcasecmp(config, "none") != 0 &&

usr.bin/ssh/ssh.c

561

!read_config_file(config, pw, host, host_name, cmd,

usr.bin/ssh/ssh.c

566

"%.100s", config, strerror(errno));

usr.bin/ssh/sshd.c

1004

if (children[i].config)

usr.bin/ssh/sshd.c

1005

buf = children[i].config;

usr.bin/ssh/sshd.c

1026

if (children[i].config == buf) {

usr.bin/ssh/sshd.c

1028

children[i].config = NULL;

usr.bin/ssh/sshd.c

1066

if (children[i].config) {

usr.bin/ssh/sshd.c

167

struct sshbuf *config;

usr.bin/ssh/sshd.c

1679

config = pack_config(cfg);

usr.bin/ssh/sshd.c

1680

if (sshbuf_len(config) > MONITOR_MAX_CFGLEN) {

usr.bin/ssh/sshd.c

1682

sshbuf_len(config), MONITOR_MAX_CFGLEN);

usr.bin/ssh/sshd.c

175

struct sshbuf *config; /* packed */

usr.bin/ssh/sshd.c

224

children[i].config != NULL ||

usr.bin/ssh/sshd.c

237

if ((child->config = sshbuf_fromb(config)) == NULL)

usr.bin/ssh/sshd.c

274

sshbuf_free(child->config);

usr.bin/ssh/sshd.c

332

if (child->config)

usr.bin/ssh/sshd.c

472

if (children[i].config)

usr.bin/ssh/sshd.c

773

sshbuf_len(config));

usr.bin/ssh/sshd.c

775

mlen = sshbuf_len(config);

usr.bin/ssh/sshd.c

776

if (atomicio(vwrite, fd, sshbuf_mutable_ptr(config), mlen) != mlen)

usr.bin/ssh/sshd.c

981

if (children[i].config != NULL ||

usr.sbin/authpf/authpf.c

297

if (read_config(config)) {

usr.sbin/authpf/authpf.c

85

FILE *config;

usr.sbin/authpf/authpf.c

97

config = fopen(PATH_CONFFILE, "r");

usr.sbin/authpf/authpf.c

98

if (config == NULL) {

usr.sbin/config/config.h

292

extern struct config *allcf; /* list of configured kernels */

usr.sbin/config/config.h

83

struct config *cf_next; /* linked list */

usr.sbin/config/gram.y

63

static struct config conf; /* at most one active at a time */

usr.sbin/config/main.c

102

struct config *allcf; /* list of configured kernels */

usr.sbin/config/main.c

572

cfcrosscheck(struct config *cf, const char *what, struct nvlist *nv)

usr.sbin/config/main.c

618

struct config *cf;

usr.sbin/config/main.c

73

static int cfcrosscheck(struct config *, const char *, struct nvlist *);

usr.sbin/config/mkmakefile.c

472

struct config *cf;

usr.sbin/config/mkswap.c

57

static int mkoneswap(struct config *);

usr.sbin/config/mkswap.c

65

struct config *cf;

usr.sbin/config/mkswap.c

87

mkoneswap(struct config *cf)

usr.sbin/config/sem.c

612

addconf(struct config *cf0)

usr.sbin/config/sem.c

614

struct config *cf;

usr.sbin/config/sem.c

72

static struct config **nextcf;

usr.sbin/config/sem.h

56

void addconf(struct config *);

usr.sbin/config/ukc.c

161

if (config()) {

usr.sbin/config/ukc.h

114

int config(void);

usr.sbin/hostapd/hostapd.c

375

char *config = NULL;

usr.sbin/hostapd/hostapd.c

388

config = optarg;

usr.sbin/hostapd/hostapd.c

411

if (config == NULL)

usr.sbin/hostapd/hostapd.c

414

ret = strlcpy(cfg->c_config, config, sizeof(cfg->c_config));

usr.sbin/inetd/inetd.c

265

void config(int, short, void *);

usr.sbin/inetd/inetd.c

371

config(0, 0, NULL);

usr.sbin/inetd/inetd.c

373

signal_set(&evsig_hup, SIGHUP, config, NULL);

usr.sbin/installboot/efi_installboot.c

358

if (config && gp)

usr.sbin/installboot/i386_installboot.c

465

if (config && gp)

usr.sbin/installboot/installboot.c

32

int config;

usr.sbin/installboot/installboot.c

71

config = 1;

usr.sbin/installboot/installboot.h

22

extern int config;

usr.sbin/iscsid/connection.c

178

log_sockaddr(&c->config.TargetAddr));

usr.sbin/iscsid/connection.c

373

(dst)->value = (src)->config.k; \

usr.sbin/iscsid/connection.c

382

(dst)->value = ((src)->config.k == SESSION_TYPE_DISCOVERY)\

usr.sbin/iscsid/connection.c

499

c->session->config.SessionName,

usr.sbin/iscsid/connection.c

506

c->session->config.SessionName, conn_state(ns));

usr.sbin/iscsid/connection.c

512

c->session->config.SessionName, conn_state(c->state),

usr.sbin/iscsid/connection.c

522

log_sockaddr(&c->config.TargetAddr));

usr.sbin/iscsid/connection.c

526

if (c->config.LocalAddr.ss_len != 0) {

usr.sbin/iscsid/connection.c

527

if (bind(c->fd, (struct sockaddr *)&c->config.LocalAddr,

usr.sbin/iscsid/connection.c

528

c->config.LocalAddr.ss_len) == -1) {

usr.sbin/iscsid/connection.c

530

log_sockaddr(&c->config.LocalAddr));

usr.sbin/iscsid/connection.c

535

if (connect(c->fd, (struct sockaddr *)&c->config.TargetAddr,

usr.sbin/iscsid/connection.c

536

c->config.TargetAddr.ss_len) == -1) {

usr.sbin/iscsid/connection.c

543

log_sockaddr(&c->config.TargetAddr));

usr.sbin/iscsid/connection.c

67

c->config = *cc;

usr.sbin/iscsid/connection.c

69

if (s->config.HeaderDigest != 0)

usr.sbin/iscsid/connection.c

70

c->mine.HeaderDigest = s->config.HeaderDigest;

usr.sbin/iscsid/connection.c

71

if (s->config.DataDigest != 0)

usr.sbin/iscsid/connection.c

72

c->mine.DataDigest = s->config.DataDigest;

usr.sbin/iscsid/connection.c

90

c->fd = socket(c->config.TargetAddr.ss_family, SOCK_STREAM, 0);

usr.sbin/iscsid/initiator.c

104

return &initiator->config;

usr.sbin/iscsid/initiator.c

140

s->isid_base = initiator->config.isid_base;

usr.sbin/iscsid/initiator.c

141

s->isid_qual = initiator->config.isid_qual;

usr.sbin/iscsid/initiator.c

168

if (strcmp(s->config.SessionName, name) == 0)

usr.sbin/iscsid/initiator.c

339

if (c->session->config.SessionType == SESSION_TYPE_DISCOVERY) {

usr.sbin/iscsid/initiator.c

612

tl->c->session->config.SessionName,

usr.sbin/iscsid/initiator.c

71

initiator->config.isid_base =

usr.sbin/iscsid/initiator.c

73

initiator->config.isid_qual = arc4random_uniform(0xffff);

usr.sbin/iscsid/initiator.c

98

initiator->config = *ic;

usr.sbin/iscsid/iscsid.c

291

cdv[0].buf = &s->config;

usr.sbin/iscsid/iscsid.c

292

cdv[0].len = sizeof(s->config);

usr.sbin/iscsid/iscsid.c

294

if (s->config.TargetName) {

usr.sbin/iscsid/iscsid.c

295

cdv[1].buf = s->config.TargetName;

usr.sbin/iscsid/iscsid.c

297

strlen(s->config.TargetName) + 1;

usr.sbin/iscsid/iscsid.c

299

if (s->config.InitiatorName) {

usr.sbin/iscsid/iscsid.c

300

cdv[2].buf = s->config.InitiatorName;

usr.sbin/iscsid/iscsid.c

302

strlen(s->config.InitiatorName) + 1;

usr.sbin/iscsid/iscsid.h

227

struct initiator_config config;

usr.sbin/iscsid/iscsid.h

243

struct session_config config;

usr.sbin/iscsid/iscsid.h

276

struct connection_config config;

usr.sbin/iscsid/session.c

101

s->config.InitiatorName = strdup(sc->InitiatorName);

usr.sbin/iscsid/session.c

102

if (s->config.InitiatorName == NULL)

usr.sbin/iscsid/session.c

105

s->config.InitiatorName = default_initiator_name();

usr.sbin/iscsid/session.c

172

s->config.SessionName, sess_state(s->state),

usr.sbin/iscsid/session.c

214

s->config.SessionName, sess_state(s->state),

usr.sbin/iscsid/session.c

221

s->config.SessionName,

usr.sbin/iscsid/session.c

229

"[%s, %s]", s->config.SessionName,

usr.sbin/iscsid/session.c

239

log_sockaddr(&s->config.connection.TargetAddr));

usr.sbin/iscsid/session.c

246

if (s->config.SessionType != SESSION_TYPE_DISCOVERY &&

usr.sbin/iscsid/session.c

247

s->config.MaxConnections)

usr.sbin/iscsid/session.c

248

s->mine.MaxConnections = s->config.MaxConnections;

usr.sbin/iscsid/session.c

250

conn_new(s, &s->config.connection);

usr.sbin/iscsid/session.c

265

if (s->config.SessionType == SESSION_TYPE_DISCOVERY) {

usr.sbin/iscsid/session.c

381

s->config.SessionName, conn_state(c->state));

usr.sbin/iscsid/session.c

59

free(s->config.TargetName);

usr.sbin/iscsid/session.c

60

free(s->config.InitiatorName);

usr.sbin/iscsid/session.c

67

log_debug("session[%s] going down", s->config.SessionName);

usr.sbin/iscsid/session.c

88

free(s->config.TargetName);

usr.sbin/iscsid/session.c

89

s->config.TargetName = NULL;

usr.sbin/iscsid/session.c

90

free(s->config.InitiatorName);

usr.sbin/iscsid/session.c

91

s->config.InitiatorName = NULL;

usr.sbin/iscsid/session.c

93

s->config = *sc;

usr.sbin/iscsid/session.c

96

s->config.TargetName = strdup(sc->TargetName);

usr.sbin/iscsid/session.c

97

if (s->config.TargetName == NULL)

usr.sbin/ldapd/ldapd.h

242

struct tls_config *config;

usr.sbin/ldapd/ldape.c

440

if (tls_configure(l->tls, l->ssl->config)) {

usr.sbin/ldapd/parse.y

1261

s->config = tls_config_new();

usr.sbin/ldapd/parse.y

1262

if (s->config == NULL)

usr.sbin/ldapd/parse.y

1269

if (tls_config_set_protocols(s->config, tls_protocols) != 0) {

usr.sbin/ldapd/parse.y

1271

tls_config_error(s->config));

usr.sbin/ldapd/parse.y

1274

if (tls_config_set_ciphers(s->config, tls_ciphers)) {

usr.sbin/ldapd/parse.y

1276

tls_config_error(s->config));

usr.sbin/ldapd/parse.y

1298

if (tls_config_set_cert_mem(s->config, s->ssl_cert, s->ssl_cert_len)) {

usr.sbin/ldapd/parse.y

1300

tls_config_error(s->config));

usr.sbin/ldapd/parse.y

1322

if (tls_config_set_key_mem(s->config, s->ssl_key, s->ssl_key_len)) {

usr.sbin/ldapd/parse.y

1324

tls_config_error(s->config));

usr.sbin/ldapd/parse.y

1334

tls_config_free(s->config);

usr.sbin/mailwrapper/mailwrapper.c

103

if (config == NULL) {

usr.sbin/mailwrapper/mailwrapper.c

115

if ((line = fparseln(config, &len, &lineno, NULL, 0)) == NULL) {

usr.sbin/mailwrapper/mailwrapper.c

116

if (feof(config))

usr.sbin/mailwrapper/mailwrapper.c

150

(void)fclose(config);

usr.sbin/mailwrapper/mailwrapper.c

81

FILE *config;

usr.sbin/mailwrapper/mailwrapper.c

98

config = fopen(_PATH_MAILERCONF, "r");

usr.sbin/relayd/relay.c

2141

void tls_config_use_fake_private_key(struct tls_config *config);

usr.sbin/smtpd/lka_filter.c

1046

if (filter->config->rdns_table == NULL)

usr.sbin/smtpd/lka_filter.c

1049

if (table_match(filter->config->rdns_table, kind, key) > 0)

usr.sbin/smtpd/lka_filter.c

1052

return filter->config->not_rdns_table < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1060

if (filter->config->rdns_regex == NULL)

usr.sbin/smtpd/lka_filter.c

1063

if (table_match(filter->config->rdns_regex, K_REGEX, key) > 0)

usr.sbin/smtpd/lka_filter.c

1065

return filter->config->not_rdns_regex < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1073

if (filter->config->src_table == NULL)

usr.sbin/smtpd/lka_filter.c

1076

if (table_match(filter->config->src_table, kind, key) > 0)

usr.sbin/smtpd/lka_filter.c

1078

return filter->config->not_src_table < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

108

struct filter_config *config;

usr.sbin/smtpd/lka_filter.c

1086

if (filter->config->src_regex == NULL)

usr.sbin/smtpd/lka_filter.c

1089

if (table_match(filter->config->src_regex, K_REGEX, key) > 0)

usr.sbin/smtpd/lka_filter.c

1091

return filter->config->not_src_regex < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1099

if (filter->config->helo_table == NULL)

usr.sbin/smtpd/lka_filter.c

1102

if (table_match(filter->config->helo_table, kind, key) > 0)

usr.sbin/smtpd/lka_filter.c

1104

return filter->config->not_helo_table < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1112

if (filter->config->helo_regex == NULL)

usr.sbin/smtpd/lka_filter.c

1115

if (table_match(filter->config->helo_regex, K_REGEX, key) > 0)

usr.sbin/smtpd/lka_filter.c

1117

return filter->config->not_helo_regex < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1125

if (!filter->config->auth)

usr.sbin/smtpd/lka_filter.c

1130

return filter->config->not_auth < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1138

if (filter->config->auth_table == NULL)

usr.sbin/smtpd/lka_filter.c

1141

if (key && table_match(filter->config->auth_table, kind, key) > 0)

usr.sbin/smtpd/lka_filter.c

1144

return filter->config->not_auth_table < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1152

if (filter->config->auth_regex == NULL)

usr.sbin/smtpd/lka_filter.c

1155

if (key && table_match(filter->config->auth_regex, K_REGEX, key) > 0)

usr.sbin/smtpd/lka_filter.c

1157

return filter->config->not_auth_regex < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1166

if (filter->config->mail_from_table == NULL)

usr.sbin/smtpd/lka_filter.c

1169

if (table_match(filter->config->mail_from_table, kind, key) > 0)

usr.sbin/smtpd/lka_filter.c

1171

return filter->config->not_mail_from_table < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1179

if (filter->config->mail_from_regex == NULL)

usr.sbin/smtpd/lka_filter.c

1182

if (table_match(filter->config->mail_from_regex, K_REGEX, key) > 0)

usr.sbin/smtpd/lka_filter.c

1184

return filter->config->not_mail_from_regex < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1192

if (filter->config->rcpt_to_table == NULL)

usr.sbin/smtpd/lka_filter.c

1195

if (table_match(filter->config->rcpt_to_table, kind, key) > 0)

usr.sbin/smtpd/lka_filter.c

1197

return filter->config->not_rcpt_to_table < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1205

if (filter->config->rcpt_to_regex == NULL)

usr.sbin/smtpd/lka_filter.c

1208

if (table_match(filter->config->rcpt_to_regex, K_REGEX, key) > 0)

usr.sbin/smtpd/lka_filter.c

1210

return filter->config->not_rcpt_to_regex < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1218

if (!filter->config->fcrdns)

usr.sbin/smtpd/lka_filter.c

1222

return filter->config->not_fcrdns < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1231

if (!filter->config->rdns)

usr.sbin/smtpd/lka_filter.c

1237

return filter->config->not_rdns < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

1243

return filter->config->not_rdns < 0 ? !ret : ret;

usr.sbin/smtpd/lka_filter.c

373

filter->config = filter_config;

usr.sbin/smtpd/lka_filter.c

383

filter->config = filter_config;

usr.sbin/smtpd/lka_filter.c

403

filter->config = filter_config;

usr.sbin/smtpd/lka_filter.c

756

if (filter->config->rewrite) {

usr.sbin/smtpd/lka_filter.c

762

filter->config->rewrite);

usr.sbin/smtpd/lka_filter.c

763

filter_result_rewrite(reqid, filter->config->rewrite);

usr.sbin/smtpd/lka_filter.c

766

else if (filter->config->disconnect) {

usr.sbin/smtpd/lka_filter.c

772

filter->config->disconnect);

usr.sbin/smtpd/lka_filter.c

773

filter_result_disconnect(reqid, filter->config->disconnect);

usr.sbin/smtpd/lka_filter.c

776

else if (filter->config->junk) {

usr.sbin/smtpd/lka_filter.c

784

} else if (filter->config->report) {

usr.sbin/smtpd/lka_filter.c

789

param, filter->config->report);

usr.sbin/smtpd/lka_filter.c

793

"smtp-in", &tv, filter->config->report);

usr.sbin/smtpd/lka_filter.c

794

} else if (filter->config->bypass) {

usr.sbin/smtpd/lka_filter.c

808

filter->config->reject);

usr.sbin/smtpd/lka_filter.c

809

filter_result_reject(reqid, filter->config->reject);

usr.sbin/smtpd/mta.c

132

void tls_config_use_fake_private_key(struct tls_config *config);

usr.sbin/smtpd/mta.c

475

struct tls_config *config;

usr.sbin/smtpd/mta.c

486

if ((config = tls_config_new()) == NULL)

usr.sbin/smtpd/mta.c

492

if (ciphers && tls_config_set_ciphers(config, ciphers) == -1)

usr.sbin/smtpd/mta.c

493

fatalx("%s", tls_config_error(config));

usr.sbin/smtpd/mta.c

500

if (tls_config_set_protocols(config, protos) == -1)

usr.sbin/smtpd/mta.c

501

fatalx("%s", tls_config_error(config));

usr.sbin/smtpd/mta.c

509

tls_config_set_dheparams(config, dheparams[pki->pki_dhe]);

usr.sbin/smtpd/mta.c

510

tls_config_use_fake_private_key(config);

usr.sbin/smtpd/mta.c

511

if (tls_config_set_keypair_mem(config, pki->pki_cert,

usr.sbin/smtpd/mta.c

514

tls_config_error(config));

usr.sbin/smtpd/mta.c

519

if (tls_config_set_ca_mem(config, ca->ca_cert, ca->ca_cert_len)

usr.sbin/smtpd/mta.c

522

tls_config_error(config));

usr.sbin/smtpd/mta.c

524

else if (tls_config_set_ca_file(config, tls_default_ca_cert_file())

usr.sbin/smtpd/mta.c

527

tls_config_error(config));

usr.sbin/smtpd/mta.c

530

tls_config_verify(config);

usr.sbin/smtpd/mta.c

532

tls_config_insecure_noverifycert(config);

usr.sbin/smtpd/mta.c

533

tls_config_insecure_noverifyname(config);

usr.sbin/smtpd/mta.c

534

tls_config_insecure_noverifytime(config);

usr.sbin/smtpd/mta.c

537

remote->tls_config = config;

usr.sbin/smtpd/parse.y

2570

char *p, *backend, *config;

usr.sbin/smtpd/parse.y

2575

config = $3;

usr.sbin/smtpd/parse.y

2579

config = NULL;

usr.sbin/smtpd/parse.y

2585

config = p+1;

usr.sbin/smtpd/parse.y

2588

if (config != NULL && *config != '/') {

usr.sbin/smtpd/parse.y

2595

table = table_create(conf, backend, $2, config);

usr.sbin/smtpd/parse.y

2598

config, table->t_name);

usr.sbin/smtpd/smtp.c

155

struct tls_config *config;

usr.sbin/smtpd/smtp.c

162

if ((config = tls_config_new()) == NULL)

usr.sbin/smtpd/smtp.c

168

if (ciphers && tls_config_set_ciphers(config, ciphers) == -1)

usr.sbin/smtpd/smtp.c

169

fatalx("%s", tls_config_error(config));

usr.sbin/smtpd/smtp.c

175

if (tls_config_set_protocols(config, protos) == -1)

usr.sbin/smtpd/smtp.c

176

fatalx("%s", tls_config_error(config));

usr.sbin/smtpd/smtp.c

183

if (tls_config_set_dheparams(config, dheparams[pki->pki_dhe]) == -1)

usr.sbin/smtpd/smtp.c

185

tls_config_error(config));

usr.sbin/smtpd/smtp.c

187

tls_config_use_fake_private_key(config);

usr.sbin/smtpd/smtp.c

191

if (tls_config_set_keypair_mem(config, pki->pki_cert,

usr.sbin/smtpd/smtp.c

194

tls_config_error(config));

usr.sbin/smtpd/smtp.c

196

if (tls_config_add_keypair_mem(config, pki->pki_cert,

usr.sbin/smtpd/smtp.c

199

tls_config_error(config));

usr.sbin/smtpd/smtp.c

207

if (tls_config_set_ca_mem(config, ca->ca_cert, ca->ca_cert_len)

usr.sbin/smtpd/smtp.c

210

tls_config_error(config));

usr.sbin/smtpd/smtp.c

212

else if (tls_config_set_ca_file(config, tls_default_ca_cert_file())

usr.sbin/smtpd/smtp.c

217

tls_config_verify_client(config);

usr.sbin/smtpd/smtp.c

222

if (tls_configure(l->tls, config) == -1) {

usr.sbin/smtpd/smtp.c

225

tls_config_free(config);

usr.sbin/smtpd/smtp.c

54

void tls_config_use_fake_private_key(struct tls_config *config);

usr.sbin/smtpd/smtpd.h

367

int (*config)(struct table *);

usr.sbin/smtpd/table.c

217

const char *config)

usr.sbin/smtpd/table.c

237

if (config) {

usr.sbin/smtpd/table.c

239

if (strlcat(path, config, sizeof(path))

usr.sbin/smtpd/table.c

243

config = path;

usr.sbin/smtpd/table.c

254

if (config) {

usr.sbin/smtpd/table.c

255

if (strlcpy(t->t_config, config, sizeof t->t_config)

usr.sbin/smtpd/table.c

288

if (t->t_backend->config == NULL)

usr.sbin/smtpd/table.c

290

return (t->t_backend->config(t));

usr.sbin/smtpd/table_db.c

48

.config = table_db_config,

usr.sbin/smtpd/table_getpwnam.c

32

.config = table_getpwnam_config,

usr.sbin/smtpd/table_proc.c

310

.config = NULL,

usr.sbin/smtpd/table_static.c

50

.config = table_static_config,

usr.sbin/unbound/util/config_file.c

2486

config_apply(struct config_file* config)

usr.sbin/unbound/util/config_file.c

2488

MAX_TTL = (time_t)config->max_ttl;

usr.sbin/unbound/util/config_file.c

2489

MIN_TTL = (time_t)config->min_ttl;

usr.sbin/unbound/util/config_file.c

2490

SERVE_EXPIRED = config->serve_expired;

usr.sbin/unbound/util/config_file.c

2491

SERVE_EXPIRED_TTL = (time_t)config->serve_expired_ttl;

usr.sbin/unbound/util/config_file.c

2492

SERVE_EXPIRED_TTL_RESET = config->serve_expired_ttl_reset;

usr.sbin/unbound/util/config_file.c

2493

SERVE_EXPIRED_REPLY_TTL = (time_t)config->serve_expired_reply_ttl;

usr.sbin/unbound/util/config_file.c

2494

SERVE_ORIGINAL_TTL = config->serve_original_ttl;

usr.sbin/unbound/util/config_file.c

2495

MAX_NEG_TTL = (time_t)config->max_negative_ttl;

usr.sbin/unbound/util/config_file.c

2496

MIN_NEG_TTL = (time_t)config->min_negative_ttl;

usr.sbin/unbound/util/config_file.c

2497

RTT_MIN_TIMEOUT = config->infra_cache_min_rtt;

usr.sbin/unbound/util/config_file.c

2498

RTT_MAX_TIMEOUT = config_apply_max_rtt(config->infra_cache_max_rtt);

usr.sbin/unbound/util/config_file.c

2499

EDNS_ADVERTISED_SIZE = (uint16_t)config->edns_buffer_size;

usr.sbin/unbound/util/config_file.c

2500

MINIMAL_RESPONSES = config->minimal_responses;

usr.sbin/unbound/util/config_file.c

2501

RRSET_ROUNDROBIN = config->rrset_roundrobin;

usr.sbin/unbound/util/config_file.c

2502

LOG_TAG_QUERYREPLY = config->log_tag_queryreply;

usr.sbin/unbound/util/config_file.c

2503

MAX_GLOBAL_QUOTA = config->max_global_quota;

usr.sbin/unbound/util/config_file.c

2504

UNKNOWN_SERVER_NICENESS = config->unknown_server_time_limit;

usr.sbin/unbound/util/config_file.c

2505

log_set_time_asc(config->log_time_ascii);

usr.sbin/unbound/util/config_file.c

2506

log_set_time_iso(config->log_time_iso);

usr.sbin/unbound/util/config_file.c

2507

autr_permit_small_holddown = config->permit_small_holddown;

usr.sbin/unbound/util/config_file.c

2508

stream_wait_max = config->stream_wait_size;

usr.sbin/unbound/util/config_file.c

2509

http2_query_buffer_max = config->http_query_buffer_size;

usr.sbin/unbound/util/config_file.c

2510

http2_response_buffer_max = config->http_response_buffer_size;

usr.sbin/unbound/util/config_file.h

1004

void config_apply(struct config_file* config);

usr.sbin/unbound/util/config_file.h

1014

void config_lookup_uid(struct config_file* config);

usr.sbin/unbound/util/config_file.h

1024

int config_set_option(struct config_file* config, const char* option,

usr.sbin/unbound/util/config_file.h

981

void config_auto_slab_values(struct config_file* config);

usr.sbin/unbound/util/config_file.h

991

int config_read(struct config_file* config, const char* filename,

usr.sbin/unbound/util/config_file.h

998

void config_delete(struct config_file* config);

usr.sbin/unbound/util/edns.c

103

for(c=config->edns_client_strings; c; c=c->next) {

usr.sbin/unbound/util/edns.c

121

edns_strings->client_string_opcode = config->edns_client_string_opcode;

usr.sbin/unbound/util/edns.c

97

struct config_file* config)

usr.sbin/unbound/util/edns.h

131

struct config_file* config);