Symbol: MIPS_INT_MASK_2
sys/arch/algor/algor/algor_intr.c
141
if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
sys/arch/algor/algor/algor_intr.c
79
|MIPS_INT_MASK_2|MIPS_INT_MASK_3,
sys/arch/arc/arc/c_magnum.c
97
| MIPS_INT_MASK_2
sys/arch/arc/arc/c_nec_eisa.c
119
| MIPS_INT_MASK_2,
sys/arch/arc/arc/c_nec_pci.c
124
| MIPS_INT_MASK_2,
sys/arch/arc/dti/arcsisabr.c
120
(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
sys/arch/arc/dti/tyneisabr.c
121
(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
sys/arch/arc/isa/isabus.c
461
return MIPS_INT_MASK_2;
sys/arch/arc/jazz/jazzisabr.c
121
(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
sys/arch/arc/pci/necpb.c
274
(*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, ARC_INTPRI_PCIISA);
sys/arch/arc/pci/necpb.c
524
return handled ? MIPS_INT_MASK_2 : 0;
sys/arch/cobalt/cobalt/interrupt.c
455
if (pending & MIPS_INT_MASK_2) {
sys/arch/emips/include/intr.h
54
#define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
sys/arch/evbmips/gdium/gdium_intr.c
151
MIPS_INT_MASK_2 |
sys/arch/evbmips/gdium/gdium_intr.c
158
MIPS_INT_MASK_2 |
sys/arch/evbmips/ingenic/intr.c
212
if (ipending & MIPS_INT_MASK_2) {
sys/arch/evbmips/ingenic/intr.c
80
MIPS_INT_MASK_2 |
sys/arch/evbmips/loongson/loongson_intr.c
81
MIPS_INT_MASK_2 |
sys/arch/evbmips/loongson/loongson_intr.c
88
MIPS_INT_MASK_2 |
sys/arch/evbmips/mipssim/mipssim_intr.c
54
| MIPS_INT_MASK_2,
sys/arch/evbmips/mipssim/mipssim_intr.c
57
| MIPS_INT_MASK_2 | MIPS_INT_MASK_5,
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
204
if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
60
| MIPS_INT_MASK_2
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
64
| MIPS_INT_MASK_2
sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
234
if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
sys/arch/hpcmips/tx/tx39icu.c
335
!(ipending & MIPS_INT_MASK_2)) {
sys/arch/hpcmips/tx/tx39icu.c
350
if (ipending & MIPS_INT_MASK_2) {
sys/arch/hpcmips/tx/tx39icu.c
91
| MIPS_INT_MASK_2
sys/arch/hpcmips/tx/tx39icu.c
94
| MIPS_INT_MASK_2
sys/arch/mips/alchemy/au_icu.c
105
MIPS_INT_MASK_2 |
sys/arch/mips/atheros/ar5312.c
374
| MIPS_INT_MASK_1 | MIPS_INT_MASK_2
sys/arch/mips/atheros/ar5315.c
359
| MIPS_INT_MASK_1 | MIPS_INT_MASK_2,
sys/arch/mips/atheros/ar7100.c
83
MIPS_INT_MASK_2 | /* GMAC0 */
sys/arch/mips/atheros/ar7100.c
88
MIPS_INT_MASK_2 | /* GMAC0 */
sys/arch/mips/atheros/ar9344.c
375
MIPS_INT_MASK_2 | /* GMAC0 */
sys/arch/mips/cavium/octeon_intr.c
491
if (ipending & MIPS_INT_MASK_2) {
sys/arch/mipsco/mipsco/mips_3x30.c
110
if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */
sys/arch/mipsco/mipsco/mips_3x30.c
66
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
sys/arch/newsmips/newsmips/news3400.c
76
| MIPS_INT_MASK_2,
sys/arch/newsmips/newsmips/news3400.c
94
if (ipending & MIPS_INT_MASK_2) {
sys/arch/newsmips/newsmips/news4000.c
67
| MIPS_INT_MASK_2,
sys/arch/newsmips/newsmips/news4000.c
83
if (ipending & MIPS_INT_MASK_2) {
sys/arch/newsmips/newsmips/news5000.c
72
| MIPS_INT_MASK_2,
sys/arch/newsmips/newsmips/news5000.c
89
if (ipending & MIPS_INT_MASK_2) {
sys/arch/pmax/include/intr.h
49
#define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
sys/arch/pmax/pmax/dec_3100.c
215
CALLINTR(SYS_DEV_SCC0, MIPS_INT_MASK_2);
sys/arch/pmax/pmax/dec_3min.c
250
mask = MIPS_INT_MASK_2;
sys/arch/pmax/pmax/dec_3min.c
423
if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) {
sys/arch/pmax/pmax/dec_5100.c
100
mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2);
sys/arch/pmax/pmax/dec_5100.c
171
if (ipending & MIPS_INT_MASK_2) {
sys/arch/pmax/pmax/dec_maxine.c
359
if (ipending & MIPS_INT_MASK_2) {
sys/arch/pmax/pmax/interrupt.c
96
if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
sys/arch/sgimips/sgimips/cpu.c
137
if (pending & MIPS_INT_MASK_2) {
sys/arch/sgimips/sgimips/machdep.c
136
[IPL_SCHED] = MIPS_INT_MASK_4|MIPS_INT_MASK_2|
sys/arch/sgimips/sgimips/machdep.c
143
[IPL_VM] = MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0|
sys/arch/sgimips/sgimips/machdep.c
145
[IPL_SCHED] = MIPS_INT_MASK_4|MIPS_INT_MASK_3|MIPS_INT_MASK_2|