sys/arch/evbppc/ev64260/machdep.c

301

out32rb(gt_base + GTMPSC_MRR, GTMPSC_MRR_RES);

sys/arch/evbppc/ev64260/machdep.c

305

out32rb(gt_base + GTMPSC_RCRR, cr);

sys/arch/evbppc/ev64260/machdep.c

306

out32rb(gt_base + GTMPSC_TCRR, cr);

sys/arch/evbppc/ev64260/machdep.c

309

out32rb(gt_base + BRG_BCR(brg),

sys/arch/evbppc/ev64260/machdep.c

418

out32rb(gt_base + GT_PCI0_Mem0_Low_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

423

out32rb(gt_base + GT_PCI0_Mem0_High_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

444

out32rb(gt_base + GT_PCI1_IO_Remap, 0);

sys/arch/evbppc/ev64260/machdep.c

451

out32rb(gt_base + GT_PCI0_IO_Low_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

456

out32rb(gt_base + GT_PCI0_IO_High_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

471

out32rb(gt_base + GT_PCI1_Mem0_Low_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

476

out32rb(gt_base + GT_PCI1_Mem0_High_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

497

out32rb(gt_base + GT_PCI1_IO_Remap, 0);

sys/arch/evbppc/ev64260/machdep.c

504

out32rb(gt_base + GT_PCI1_IO_Low_Decode, datal);

sys/arch/evbppc/ev64260/machdep.c

509

out32rb(gt_base + GT_PCI1_IO_High_Decode, datal);

sys/arch/ibmnws/ibmnws/machdep.c

102

out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK0_START);

sys/arch/ibmnws/ibmnws/machdep.c

105

out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK0_END);

sys/arch/ibmnws/ibmnws/machdep.c

109

out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK_ENABLE);

sys/arch/ibmnws/ibmnws/machdep.c

113

out32rb(PCI_MODE1_ADDRESS_REG, 0);

sys/arch/macppc/dev/awacs.c

1009

out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_odmacmd));

sys/arch/macppc/dev/dbdma.c

103

out32rb(&dmap->d_control,

sys/arch/macppc/dev/dbdma.c

71

out32rb(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) |

sys/arch/macppc/dev/dbdma.c

81

out32rb(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));

sys/arch/macppc/dev/dbdma.c

89

out32rb(&dmap->d_control,

sys/arch/macppc/dev/dbdma.h

122

out32rb(&(d)->d_address, address); \

sys/arch/macppc/dev/dbdma.h

133

#define DBDMA_ST4_ENDIAN(a, x) out32rb(a, x)

sys/arch/macppc/dev/if_bm.c

421

out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_rxcmd));

sys/arch/macppc/dev/if_gm.c

265

out32rb(sc->sc_reg + reg, val);

sys/arch/macppc/dev/if_mc.c

319

out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd));

sys/arch/macppc/dev/if_mc.c

349

out32rb(&dmareg->d_cmdptrhi, 0);

sys/arch/macppc/dev/if_mc.c

350

out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd));

sys/arch/macppc/dev/lightbar.c

196

out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_odmacmd));

sys/arch/macppc/dev/mediabay.c

181

out32rb(sc->sc_fcr, fcr);

sys/arch/macppc/dev/mediabay.c

185

out32rb(sc->sc_fcr, fcr);

sys/arch/macppc/dev/mediabay.c

189

out32rb(sc->sc_fcr, fcr);

sys/arch/macppc/dev/mediabay.c

197

out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_RESET);

sys/arch/macppc/dev/mediabay.c

198

out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_POWER);

sys/arch/macppc/dev/mediabay.c

201

out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_ENABLE);

sys/arch/macppc/dev/mediabay.c

204

out32rb(sc->sc_addr,

sys/arch/macppc/dev/mediabay.c

208

out32rb(sc->sc_addr, in32rb(sc->sc_addr) | MBCR_MEDIABAY0_RESET);

sys/arch/macppc/dev/mediabay.c

211

out32rb(sc->sc_fcr, in32rb(sc->sc_fcr) | FCR1_EIDE0_RESET);

sys/arch/macppc/dev/mediabay.c

212

out32rb(sc->sc_fcr, in32rb(sc->sc_fcr) | FCR1_EIDE0_ENABLE);

sys/arch/macppc/dev/mediabay.c

215

out32rb(sc->sc_addr, in32rb(sc->sc_addr) | MBCR_MEDIABAY0_ENABLE);

sys/arch/macppc/dev/mediabay.c

219

out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~0xf);

sys/arch/macppc/dev/mediabay.c

259

out32rb(sc->sc_fcr, fcr);

sys/arch/macppc/dev/mediabay.c

315

out32rb(sc->sc_fcr, fcr);

sys/arch/macppc/dev/snapper.c

1412

out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_odmacmd));

sys/arch/macppc/dev/snapper.c

1463

out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_idmacmd));

sys/arch/macppc/dev/wdc_obio.c

256

out32rb(OHARE_FEATURE_REG, x);

sys/arch/macppc/macppc/pic_heathrow.c

131

out32rb(INT_ENABLE_REG_L, 0);

sys/arch/macppc/macppc/pic_heathrow.c

132

out32rb(INT_CLEAR_REG_L, 0xffffffff);

sys/arch/macppc/macppc/pic_heathrow.c

133

out32rb(INT_ENABLE_REG_H, 0);

sys/arch/macppc/macppc/pic_heathrow.c

134

out32rb(INT_CLEAR_REG_H, 0xffffffff);

sys/arch/macppc/macppc/pic_heathrow.c

146

out32rb(INT_ENABLE_REG_H, heathrow->enable_mask_h);

sys/arch/macppc/macppc/pic_heathrow.c

149

out32rb(INT_ENABLE_REG_L, heathrow->enable_mask_l);

sys/arch/macppc/macppc/pic_heathrow.c

162

out32rb(INT_ENABLE_REG_H, heathrow->enable_mask_h);

sys/arch/macppc/macppc/pic_heathrow.c

166

out32rb(INT_CLEAR_REG_H, mask);

sys/arch/macppc/macppc/pic_heathrow.c

170

out32rb(INT_ENABLE_REG_L, heathrow->enable_mask_l);

sys/arch/macppc/macppc/pic_heathrow.c

174

out32rb(INT_CLEAR_REG_L, mask);

sys/arch/macppc/macppc/pic_heathrow.c

187

out32rb(INT_ENABLE_REG_H, heathrow->enable_mask_h);

sys/arch/macppc/macppc/pic_heathrow.c

190

out32rb(INT_ENABLE_REG_L, heathrow->enable_mask_l);

sys/arch/macppc/macppc/pic_heathrow.c

206

out32rb(INT_CLEAR_REG_L, events | irqs);

sys/arch/macppc/macppc/pic_heathrow.c

214

out32rb(INT_CLEAR_REG_H, events);

sys/arch/macppc/macppc/pic_ohare.c

148

out32rb(INT_ENABLE_REG, 0);

sys/arch/macppc/macppc/pic_ohare.c

149

out32rb(INT_CLEAR_REG, 0xffffffff);

sys/arch/macppc/macppc/pic_ohare.c

171

out32rb(INT_ENABLE_REG, ohare->enable_mask);

sys/arch/macppc/macppc/pic_ohare.c

182

out32rb(INT_ENABLE_REG, ohare->enable_mask);

sys/arch/macppc/macppc/pic_ohare.c

186

out32rb(INT_CLEAR_REG, mask);

sys/arch/macppc/macppc/pic_ohare.c

197

out32rb(INT_ENABLE_REG, ohare->enable_mask);

sys/arch/macppc/macppc/pic_ohare.c

211

out32rb(INT_CLEAR_REG, events | irqs);

sys/arch/macppc/macppc/pic_u3_ht.c

362

out32rb(base + 0x04, tmp);

sys/arch/macppc/macppc/pic_u3_ht.c

499

out32rb(irqmap->im_base + 0x04, x | HTAPIC_MASK);

sys/arch/macppc/macppc/pic_u3_ht.c

512

out32rb(irqmap->im_base + 0x04, x);

sys/arch/macppc/macppc/pic_u3_ht.c

524

out32rb(irqmap->im_base + 0x04, x);

sys/arch/macppc/macppc/pic_u3_ht.c

538

out32rb(irqmap->im_base + 0x04, x);

sys/arch/macppc/macppc/pic_u3_ht.c

548

out32rb(irqmap->im_apple_base + ((irqmap->im_index >> 3) & ~0x03),

sys/arch/macppc/macppc/pic_u3_ht.c

552

out32rb(irqmap->im_base + 0x04, irqmap->im_data);

sys/arch/macppc/macppc/pic_u3_ht.c

618

out32rb(addr, val);

sys/arch/macppc/pci/bandit.c

188

out32rb(pc->pc_addr, x);

sys/arch/macppc/pci/bandit.c

194

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/bandit.c

226

out32rb(pc->pc_addr, x);

sys/arch/macppc/pci/bandit.c

228

out32rb(pc->pc_data, data);

sys/arch/macppc/pci/bandit.c

230

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/grackle.c

164

out32rb(pc->pc_addr, tag | reg);

sys/arch/macppc/pci/grackle.c

168

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/grackle.c

186

out32rb(pc->pc_addr, tag | reg);

sys/arch/macppc/pci/grackle.c

187

out32rb(pc->pc_data, data);

sys/arch/macppc/pci/grackle.c

188

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/u3.c

243

out32rb(x, data);

sys/arch/macppc/pci/uninorth.c

224

out32rb(pc->pc_addr, x);

sys/arch/macppc/pci/uninorth.c

229

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/uninorth.c

265

out32rb(pc->pc_addr, x);

sys/arch/macppc/pci/uninorth.c

267

out32rb(daddr, data);

sys/arch/macppc/pci/uninorth.c

268

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/uninorth.c

302

out32rb(pc->pc_addr, x);

sys/arch/macppc/pci/uninorth.c

308

out32rb(pc->pc_addr, 0);

sys/arch/macppc/pci/uninorth.c

342

out32rb(pc->pc_addr, x);

sys/arch/macppc/pci/uninorth.c

344

out32rb(daddr, data);

sys/arch/macppc/pci/uninorth.c

345

out32rb(pc->pc_addr, 0);

sys/arch/powerpc/include/openpic.h

53

out32rb(addr, val);

sys/arch/powerpc/mpc5200/mpc5200_pci.c

123

out32rb(pc->pc_data, data); /* config data: little-endian */

sys/arch/powerpc/pci/pchb.c

266

out32rb(python+0x30, v);

sys/arch/powerpc/pci/pciconf_indirect.c

110

out32rb(pc->pc_addr, tag | reg);

sys/arch/powerpc/pci/pciconf_indirect.c

112

out32rb(pc->pc_addr, 0);

sys/arch/powerpc/pci/pciconf_indirect.c

128

out32rb(pc->pc_addr, tag | reg);

sys/arch/powerpc/pci/pciconf_indirect.c

129

out32rb(pc->pc_data, data);

sys/arch/powerpc/pci/pciconf_indirect.c

130

out32rb(pc->pc_addr, 0);

sys/arch/powerpc/pic/pic_distopenpic.c

167

out32rb(addr, val);

sys/arch/prep/pci/prep_pciconf_direct.c

219

out32rb(PCI_DCONF_BASE | tag | reg, data);

sys/arch/rs6000/rs6000/pic_iocc.c

108

out32rb(RS6000_BUS_SPACE_IO + IOCC_IEE, mask);

sys/arch/rs6000/rs6000/pic_iocc.c

119

out32rb(RS6000_BUS_SPACE_IO + IOCC_IEE, mask);

sys/arch/rs6000/rs6000/pic_iocc.c

126

out32rb(RS6000_BUS_SPACE_IO + IOCC_EOI(irq), 0x1); /* val is ignored */

sys/arch/rs6000/rs6000/pic_iocc.c

137

out32rb(RS6000_BUS_SPACE_IO + IOCC_XIVR(irq), x);

sys/arch/sandpoint/pci/pci_machdep.c

219

out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);

sys/arch/sandpoint/pci/pci_machdep.c

221

out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);

sys/arch/sandpoint/pci/pci_machdep.c

232

out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);

sys/arch/sandpoint/pci/pci_machdep.c

233

out32rb(SANDPOINT_PCI_CONFIG_DATA, data);

sys/arch/sandpoint/pci/pci_machdep.c

234

out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);

sys/arch/sandpoint/sandpoint/machdep.c

527

out32rb(0xfec00000, (1U<<31) | MPC107_MEMEN);

sys/arch/sandpoint/sandpoint/machdep.c

541

out32rb(0xfec00000, (1U<<31) | MPC107_EXTMEMENDADDR1); /* bit 29:28 */

sys/arch/sandpoint/sandpoint/machdep.c

544

out32rb(0xfec00000, (1U<<31) | MPC107_MEMENDADDR1); /* bit 27:20 */

sys/arch/sandpoint/stand/altboot/dsk.c

58

#define CSR_WRITE_4(r,v) out32rb(r,v)

sys/arch/sandpoint/stand/altboot/fxp.c

93

#define CSR_WRITE_4(l, r, v) out32rb((l)->iobase+(r), (v))

sys/arch/sandpoint/stand/altboot/globals.h

63

void out32rb(unsigned, unsigned);

sys/arch/sandpoint/stand/altboot/kse.c

48

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/nvt.c

51

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/pcn.c

48

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/rge.c

51

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/siisata.c

42

#define CSR_WRITE_4(r,v) out32rb(r,v)

sys/arch/sandpoint/stand/altboot/sip.c

48

#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/skg.c

50

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/sme.c

48

#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/stg.c

45

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/tlp.c

48

#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/vge.c

51

#define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))

sys/arch/sandpoint/stand/altboot/wm.c

50

#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))