clr
typeset(var, set, clr, field, base)
Tflag clr, set;
&& (val || clr || (set & ~EXPORT)))
if (set | clr) {
|| ((t->flag & INTEGER) && (clr & INTEGER))
t->flag = (t->flag | set) & ~clr;
local void gzcopy(char *name, int clr, unsigned long *crc, unsigned long *tot,
if (last && clr)
if (last && clr)
if (last && clr)
if (pos == 0 || !clr)
if (!clr) {
clr %l3; /* NULL fpstate */ \
clr(static_cast<EDGE>(e));
void clr(int e);
int *ip, clr[] = {
int nclr = __arraycount(clr);
if (clr[j] == COLOR_BLACK && attr[i] != A_BOLD)
if (init_pair(nc + 1, clr[j], -1) == ERR)
goto clr;
clr:
gpt_attr_update(gpt_t gpt, u_int entry, uint64_t set, uint64_t clr)
if (entry == 0 || (set == 0 && clr == 0)) {
ent->ent_attr &= ~clr;
ent->ent_attr &= ~clr;
meson_sdhc_set_clear(struct meson_sdhc_softc *sc, bus_addr_t reg, uint32_t set, uint32_t clr)
const uint32_t new = set | (old & ~clr);
stb_setbits(struct bcmstb_softc *sc, int r, uint32_t clr, uint32_t set)
w = (w & ~clr) | set;
#define SETCLR4(sc, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
#define CEC_SET_CLEAR(sc, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
#define HDMI_SET_CLEAR(enc, reg, set, clr) \
tegra_reg_set_clear((enc)->bst, (enc)->bsh, (reg), (set), (clr))
#define DC_SET_CLEAR(crtc, reg, set, clr) \
tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr))
#define MC_SET_CLEAR(sc, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
#define SOCTHERM_SET_CLEAR(sc, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
#define SENSOR_SET_CLEAR(sc, s, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr))
#define TIMER_SET_CLEAR(sc, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
#define WAIT_FOR_CLR(sc, reg, clr) \
wait_for_bits(sc, reg, 0, clr, 0)
uint32_t set, uint32_t clr, uint32_t fail)
if ((val & set) || !(val & clr))
a64_acodec_pr_set_clear(struct a64_acodec_softc *sc, u_int addr, u_int set, u_int clr)
new = set | (old & ~clr);
h3_codec_pr_set_clear(struct h3_codec_softc *csc, u_int addr, u_int set, u_int clr)
new = set | (old & ~clr);
v3s_codec_pr_set_clear(struct v3s_codec_softc *csc, u_int addr, u_int set, u_int clr)
new = set | (old & ~clr);
#define PHY_SET_CLEAR(sc, reg, set, clr) \
_tval &= ~(clr); \
#define PHY_CLEAR(sc, reg, clr) \
PHY_SET_CLEAR(sc, reg, 0, clr)
uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
memset(clr, 0, ETHER_ADDR_LEN);
clr[i] |= enm->enm_addrlo[i];
mask[i] = set[i] | ~clr[i];
u_int set, clr;
set = clr = 0;
clr |= IFPGA_SC_CTRL_UART0RTS;
clr |= IFPGA_SC_CTRL_UART0DTR;
clr |= IFPGA_SC_CTRL_UART1RTS;
clr |= IFPGA_SC_CTRL_UART1DTR;
if (clr)
clr);
#define CSR_CLR_1(reg,clr) \
_r &= ~(clr); \
#define CSR_CLR_2(reg,clr) \
_r &= ~(clr); \
#define CSR_CLR_1(reg,clr) \
_r &= ~(clr); \
#define CSR_CLR_2(reg,clr) \
_r &= ~(clr); \
uint8_t *fr, clr[2];
clr[0] = (uint8_t)ri->ri_devcmap[(attr >> 16) & 0xf];
clr[1] = (uint8_t)ri->ri_devcmap[(attr >> 24) & 0xf];
uint16_t c = clr[0];
uint16_t c = clr[(fb >> 31) & 1];
uint16_t c = clr[1];
int sh, clr, mask, i;
clr = 2 - sh / 32;
for (i = 2; i > clr; i--) {
clr.l %d0; /* doesn't change CCR[X] */ \
clr.l %d0; /* doesn't change CCR[X] */ \
[clr] "r" (MMUCR_STS | MMUCR_STID)
[clr] "r" (MMUCR_STS | MMUCR_STID), [i] "r" (i),
[clr] "r" (MMUCR_STS | MMUCR_STID), [i] "r" (tlb_nreserved),
: [clr] "r" (MMUCR_STS | MMUCR_STID), [i] "r" (tlb_nreserved),
#define SCUPD4(sc, off, clr, set) \
SCWR4((sc), (off), (SCRD4((sc), (off)) & ~(clr)) | (set))
#define UPD4(sc, off, clr, set) \
WR4((sc), (off), (RD4((sc), (off)) & ~(clr)) | (set))
struct jh71x0_clkc_clk *jcc, uint32_t set, uint32_t clr)
val &= ~clr;
const uint32_t new = (old & ~clr) | set;
uint32_t clr, uint32_t set)
uint8_t clr, int flags)
new = set | (old & ~clr);
gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr,
if ((reg & clr) == 0 && (reg & set) == set)
uint32_t clr, uint32_t set)
if ((reg & clr) == 0 && (reg & set) == set)
uint8_t clr;
clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0);
clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) &
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr);
clr[0] = bg & COLOR_MASK;
clr[1] = fg & COLOR_MASK;
clr[0] = bg & COLOR_MASK;
clr[1] = fg & COLOR_MASK;
(tmp) |= clr[(fb >> 31) & 1] >> bit; \
c = clr[1]; \
c = clr[0]; \
c = (w * clr[1] + (0xff - w) * clr[0]) >> 8; \
uint32_t bg, fg, lbg, rbg, clr[2], lmask, rmask, tmp;
COLOR_TYPE clr[2];
clr[0] = (COLOR_TYPE)ATTR_BG(ri, attr);
clr[1] = (COLOR_TYPE)ATTR_FG(ri, attr);
#define SET_COLOR(p, index) *(p)++ = clr[index]
COLOR_TYPE c = clr[index]; \
int clr;
clr = asoc->mapping_array_size;
clr = (at >> 3) + 1;
if (clr > asoc->mapping_array_size)
clr = asoc->mapping_array_size;
memset(asoc->mapping_array, 0, clr);
int i, flip, clr, set;
clr = 0377;
clr = 0177; /* turn off bit 7 */
partab[i] = ((evenpartab[i] ^ flip) | set) & clr;
set_all_none(menudesc *menu, void *arg, int set, int clr)
set_status[dist->set] = (set_status[dist->set] & ~clr) | set;