Symbol: REGVAL
sys/arch/algor/algor/algor_p4032_intr.c
240
REGVAL(p4032_irqregs[i].addr) = p4032_irqregs[i].val;
sys/arch/algor/algor/algor_p4032_intr.c
260
REGVAL(p4032_irqsteer[i].addr) = p4032_irqsteer[i].val;
sys/arch/algor/algor/algor_p4032_intr.c
292
REGVAL(P4032_IRR0) = IRR0_RTC;
sys/arch/algor/algor/algor_p4032_intr.c
306
irr = REGVAL(P4032_IRR0);
sys/arch/algor/algor/algor_p4032_intr.c
322
REGVAL(P4032_IRR0) = 0;
sys/arch/algor/algor/algor_p4032_intr.c
374
REGVAL(p4032_irqregs[irqmap->irqreg].addr) =
sys/arch/algor/algor/algor_p4032_intr.c
405
REGVAL(p4032_irqregs[irqmap->irqreg].addr) =
sys/arch/algor/algor/algor_p4032_intr.c
424
irr[IRQREG_ERROR] = REGVAL(p4032_irqregs[IRQREG_ERROR].addr);
sys/arch/algor/algor/algor_p4032_intr.c
442
REGVAL(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR];
sys/arch/algor/algor/algor_p4032_intr.c
462
irr[i] = REGVAL(p4032_irqregs[i].addr) & p4032_irqregs[i].val;
sys/arch/algor/algor/algor_p5064_intr.c
319
REGVAL(p5064_irqregs[i].addr) = p5064_irqregs[i].val;
sys/arch/algor/algor/algor_p5064_intr.c
339
REGVAL(p5064_irqsteer[i].addr) = p5064_irqsteer[i].val;
sys/arch/algor/algor/algor_p5064_intr.c
378
REGVAL(P5064_LOCINT) = LOCINT_RTC;
sys/arch/algor/algor/algor_p5064_intr.c
392
irr = REGVAL(P5064_LOCINT);
sys/arch/algor/algor/algor_p5064_intr.c
408
REGVAL(P5064_LOCINT) = 0;
sys/arch/algor/algor/algor_p5064_intr.c
467
REGVAL(p5064_irqregs[irqmap->irqreg].addr) =
sys/arch/algor/algor/algor_p5064_intr.c
498
REGVAL(p5064_irqregs[irqmap->irqreg].addr) =
sys/arch/algor/algor/algor_p5064_intr.c
517
irr[IRQREG_PANIC] = REGVAL(p5064_irqregs[IRQREG_PANIC].addr);
sys/arch/algor/algor/algor_p5064_intr.c
539
REGVAL(p5064_irqregs[IRQREG_PANIC].addr) = irr[IRQREG_PANIC];
sys/arch/algor/algor/algor_p5064_intr.c
550
irr[i] = REGVAL(p5064_irqregs[i].addr) & p5064_irqregs[i].val;
sys/arch/algor/algor/algor_p6032_intr.c
216
REGVAL(BONITO_INTENCLR) = irqmap->intbit;
sys/arch/algor/algor/algor_p6032_intr.c
219
REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE;
sys/arch/algor/algor/algor_p6032_intr.c
220
REGVAL(BONITO_INTEDGE) = bc->bc_intEdge;
sys/arch/algor/algor/algor_p6032_intr.c
221
REGVAL(BONITO_INTSTEER) = bc->bc_intSteer;
sys/arch/algor/algor/algor_p6032_intr.c
222
REGVAL(BONITO_INTPOL) = bc->bc_intPol;
sys/arch/algor/algor/algor_p6032_intr.c
336
REGVAL(BONITO_INTENSET) = irqmap->intbit;
sys/arch/algor/algor/algor_p6032_intr.c
364
REGVAL(BONITO_INTENCLR) = irqmap->intbit;
sys/arch/algor/algor/algor_p6032_intr.c
397
isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
sys/arch/algor/dev/bonito_mainbus.c
94
rev = PCI_REVISION(REGVAL(BONITO_PCICLASS));
sys/arch/alpha/alpha/dec_550.c
105
REGVAL(PYXIS_GPO) = DEC_550_PYXIS_GPO_POWERDOWN;
sys/arch/alpha/jensenio/jensenio.c
120
REGVAL(JENSEN_HAE) = 0;
sys/arch/alpha/pci/apecs.c
116
(REGVAL(COMANCHE_ED) & COMANCHE_ED_PASS2) != 0;
sys/arch/alpha/pci/apecs.c
118
(REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64;
sys/arch/alpha/pci/apecs.c
120
(REGVAL(EPIC_DCSR) & EPIC_DCSR_PASS2) != 0;
sys/arch/alpha/pci/apecs.c
122
acp->ac_haxr1 = REGVAL(EPIC_HAXR1);
sys/arch/alpha/pci/apecs.c
123
acp->ac_haxr2 = REGVAL(EPIC_HAXR2);
sys/arch/alpha/pci/apecs_dma.c
155
REGVAL(EPIC_PCI_BASE_1) = 0;
sys/arch/alpha/pci/apecs_dma.c
169
REGVAL(EPIC_PCI_BASE_1) = APECS_SGMAP_MAPPED_BASE |
sys/arch/alpha/pci/apecs_dma.c
173
REGVAL(EPIC_PCI_MASK_1) = EPIC_PCI_MASK_8M;
sys/arch/alpha/pci/apecs_dma.c
179
REGVAL(EPIC_TBASE_1) = tbase;
sys/arch/alpha/pci/apecs_dma.c
87
REGVAL(EPIC_TBIA) = 0; \
sys/arch/alpha/pci/apecs_pci.c
122
old_haxr2 = REGVAL(EPIC_HAXR2);
sys/arch/alpha/pci/apecs_pci.c
124
REGVAL(EPIC_HAXR2) = old_haxr2 | 0x1;
sys/arch/alpha/pci/apecs_pci.c
141
REGVAL(EPIC_HAXR2) = old_haxr2;
sys/arch/alpha/pci/apecs_pci.c
74
old_haxr2 = REGVAL(EPIC_HAXR2);
sys/arch/alpha/pci/apecs_pci.c
76
REGVAL(EPIC_HAXR2) = old_haxr2 | 0x1;
sys/arch/alpha/pci/apecs_pci.c
91
REGVAL(EPIC_HAXR2) = old_haxr2;
sys/arch/alpha/pci/cia.c
154
ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
sys/arch/alpha/pci/cia.c
155
ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
sys/arch/alpha/pci/cia.c
156
ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
sys/arch/alpha/pci/cia.c
175
ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
sys/arch/alpha/pci/cia.c
203
ctrl = REGVAL(CIA_CSR_CTRL);
sys/arch/alpha/pci/cia.c
205
REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
sys/arch/alpha/pci/cia.c
325
ctrl = REGVAL(CIA_CSR_CTRL);
sys/arch/alpha/pci/cia.c
327
REGVAL(CIA_CSR_CTRL) = ctrl;
sys/arch/alpha/pci/cia_dma.c
113
REGVAL(CIA_PCI_W0BASE + (i * 0x100)) =
sys/arch/alpha/pci/cia_dma.c
116
REGVAL(CIA_PCI_W0MASK + (i * 0x100)) =
sys/arch/alpha/pci/cia_dma.c
119
REGVAL(CIA_PCI_T0BASE + (i * 0x100)) =
sys/arch/alpha/pci/cia_dma.c
139
REGVAL(CIA_PCI_W0BASE + (i * 0x100));
sys/arch/alpha/pci/cia_dma.c
141
REGVAL(CIA_PCI_W0MASK + (i * 0x100));
sys/arch/alpha/pci/cia_dma.c
143
REGVAL(CIA_PCI_T0BASE + (i * 0x100));
sys/arch/alpha/pci/cia_dma.c
240
REGVAL(CIA_PCI_W1BASE) = CIA_DIRECT_MAPPED_BASE | CIA_PCI_WnBASE_W_EN;
sys/arch/alpha/pci/cia_dma.c
242
REGVAL(CIA_PCI_W1MASK) = CIA_PCI_WnMASK_1G;
sys/arch/alpha/pci/cia_dma.c
244
REGVAL(CIA_PCI_T1BASE) = 0;
sys/arch/alpha/pci/cia_dma.c
264
REGVAL(CIA_PCI_W0BASE) = CIA_SGMAP_MAPPED_LO_BASE |
sys/arch/alpha/pci/cia_dma.c
268
REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M;
sys/arch/alpha/pci/cia_dma.c
274
REGVAL(CIA_PCI_T0BASE) = tbase;
sys/arch/alpha/pci/cia_dma.c
282
REGVAL(CIA_PCI_W3BASE) = CIA_SGMAP_MAPPED_HI_BASE |
sys/arch/alpha/pci/cia_dma.c
286
REGVAL(CIA_PCI_W3MASK) = CIA_PCI_WnMASK_1G;
sys/arch/alpha/pci/cia_dma.c
292
REGVAL(CIA_PCI_T3BASE) = tbase;
sys/arch/alpha/pci/cia_dma.c
295
REGVAL(CIA_PCI_W3BASE) = 0;
sys/arch/alpha/pci/cia_dma.c
319
REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE |
sys/arch/alpha/pci/cia_dma.c
323
REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M;
sys/arch/alpha/pci/cia_dma.c
330
REGVAL(CIA_PCI_T2BASE) = tbase;
sys/arch/alpha/pci/cia_dma.c
345
REGVAL(CIA_PCI_W2BASE) = 0;
sys/arch/alpha/pci/cia_dma.c
524
REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL;
sys/arch/alpha/pci/cia_dma.c
543
ctrl = REGVAL(CIA_CSR_CTRL);
sys/arch/alpha/pci/cia_dma.c
544
REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
sys/arch/alpha/pci/cia_dma.c
567
REGVAL(CIA_CSR_CTRL) = ctrl;
sys/arch/alpha/pci/cia_pci.c
127
REGVAL(CIA_CSR_CFG) = old_cfg;
sys/arch/alpha/pci/cia_pci.c
134
errbits = REGVAL(CIA_CSR_CIA_ERR);
sys/arch/alpha/pci/cia_pci.c
141
REGVAL(CIA_CSR_CIA_ERR) = errbits;
sys/arch/alpha/pci/cia_pci.c
174
old_cfg = REGVAL(CIA_CSR_CFG);
sys/arch/alpha/pci/cia_pci.c
176
REGVAL(CIA_CSR_CFG) = old_cfg | 0x1;
sys/arch/alpha/pci/cia_pci.c
208
REGVAL(CIA_CSR_CFG) = old_cfg;
sys/arch/alpha/pci/cia_pci.c
83
REGVAL(CIA_CSR_CIA_ERR) = CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT;
sys/arch/alpha/pci/cia_pci.c
91
old_cfg = REGVAL(CIA_CSR_CFG);
sys/arch/alpha/pci/cia_pci.c
93
REGVAL(CIA_CSR_CFG) = old_cfg | 0x1;
sys/arch/alpha/pci/dwlpx.c
122
pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
205
REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
sys/arch/alpha/pci/dwlpx.c
225
ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
258
REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT;
sys/arch/alpha/pci/dwlpx.c
259
REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec;
sys/arch/alpha/pci/dwlpx.c
266
ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
292
REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
sys/arch/alpha/pci/dwlpx.c
298
REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
sys/arch/alpha/pci/dwlpx.c
315
hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
316
hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
364
REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
sys/arch/alpha/pci/dwlpx_dma.c
224
REGVAL(PCIA_WMASK_A(i) + ccp->cc_sysbase) = PCIA_WMASK_2G;
sys/arch/alpha/pci/dwlpx_dma.c
225
REGVAL(PCIA_TBASE_A(i) + ccp->cc_sysbase) = 0;
sys/arch/alpha/pci/dwlpx_dma.c
226
REGVAL(PCIA_WBASE_A(i) + ccp->cc_sysbase) =
sys/arch/alpha/pci/dwlpx_dma.c
229
REGVAL(PCIA_WMASK_B(i) + ccp->cc_sysbase) = 0;
sys/arch/alpha/pci/dwlpx_dma.c
230
REGVAL(PCIA_TBASE_B(i) + ccp->cc_sysbase) = 0;
sys/arch/alpha/pci/dwlpx_dma.c
231
REGVAL(PCIA_WBASE_B(i) + ccp->cc_sysbase) = 0;
sys/arch/alpha/pci/dwlpx_dma.c
233
REGVAL(PCIA_WMASK_C(i) + ccp->cc_sysbase) = wmask;
sys/arch/alpha/pci/dwlpx_dma.c
234
REGVAL(PCIA_TBASE_C(i) + ccp->cc_sysbase) = 0;
sys/arch/alpha/pci/dwlpx_dma.c
235
REGVAL(PCIA_WBASE_C(i) + ccp->cc_sysbase) =
sys/arch/alpha/pci/dwlpx_pci.c
139
rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
sys/arch/alpha/pci/dwlpx_pci.c
142
REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
sys/arch/alpha/pci/dwlpx_pci.c
161
rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
sys/arch/alpha/pci/dwlpx_pci.c
164
REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
sys/arch/alpha/pci/dwlpx_pci.c
207
rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
sys/arch/alpha/pci/dwlpx_pci.c
210
REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
sys/arch/alpha/pci/dwlpx_pci.c
228
rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
sys/arch/alpha/pci/dwlpx_pci.c
231
REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
sys/arch/alpha/pci/irongate_pci.c
106
REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
sys/arch/alpha/pci/irongate_pci.c
108
data = REGVAL(PCI_CONF_DATA);
sys/arch/alpha/pci/irongate_pci.c
110
REGVAL(PCI_CONF_ADDR) = 0;
sys/arch/alpha/pci/irongate_pci.c
126
REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
sys/arch/alpha/pci/irongate_pci.c
128
REGVAL(PCI_CONF_DATA) = data;
sys/arch/alpha/pci/irongate_pci.c
130
REGVAL(PCI_CONF_ADDR) = 0;
sys/arch/alpha/pci/lca_pci.c
111
REGVAL(LCA_IOC_CONF) = 0x00;
sys/arch/alpha/pci/lca_pci.c
142
REGVAL(LCA_IOC_CONF) = 0x01;
sys/arch/alpha/pci/lca_pci.c
158
REGVAL(LCA_IOC_CONF) = 0x00;
sys/arch/alpha/pci/lca_pci.c
93
REGVAL(LCA_IOC_CONF) = 0x01;
sys/arch/alpha/pci/mcpcia.c
163
ctl = REGVAL(MCPCIA_PCI_REV(ccp));
sys/arch/alpha/pci/mcpcia.c
196
REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF;
sys/arch/alpha/pci/mcpcia.c
227
if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) {
sys/arch/alpha/pci/mcpcia.c
262
REGVAL(MCPCIA_INT_MASK0(ccp)) = 0;
sys/arch/alpha/pci/mcpcia.c
263
REGVAL(MCPCIA_INT_MASK1(ccp)) = 0;
sys/arch/alpha/pci/mcpcia.c
264
REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF;
sys/arch/alpha/pci/mcpcia.c
272
ctl = REGVAL(MCPCIA_WHOAMI(ccp));
sys/arch/alpha/pci/mcpcia.c
293
REGVAL(MCPCIA_CAP_DIAG(ccp)) |= CAP_DIAG_MC_ADRPE;
sys/arch/alpha/pci/mcpcia.c
317
ctl = REGVAL(MCPCIA_INT_MASK0(ccp));
sys/arch/alpha/pci/mcpcia.c
319
REGVAL(MCPCIA_INT_MASK0(ccp)) = ctl;
sys/arch/alpha/pci/mcpcia.c
323
ctl = REGVAL(MCPCIA_INT_MASK0(ccp));
sys/arch/alpha/pci/mcpcia_dma.c
196
REGVAL(MCPCIA_W0_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
197
REGVAL(MCPCIA_W1_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
198
REGVAL(MCPCIA_W2_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
199
REGVAL(MCPCIA_W3_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
200
REGVAL(MCPCIA_T0_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
201
REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
202
REGVAL(MCPCIA_T2_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
203
REGVAL(MCPCIA_T3_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
209
REGVAL(MCPCIA_W0_MASK(ccp)) = MCPCIA_WMASK_8M;
sys/arch/alpha/pci/mcpcia_dma.c
210
REGVAL(MCPCIA_T0_BASE(ccp)) =
sys/arch/alpha/pci/mcpcia_dma.c
213
REGVAL(MCPCIA_W0_BASE(ccp)) =
sys/arch/alpha/pci/mcpcia_dma.c
223
REGVAL(MCPCIA_W1_MASK(ccp)) = MCPCIA_WMASK_2G;
sys/arch/alpha/pci/mcpcia_dma.c
224
REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
sys/arch/alpha/pci/mcpcia_dma.c
226
REGVAL(MCPCIA_W1_BASE(ccp)) =
sys/arch/alpha/pci/mcpcia_dma.c
234
REGVAL(MCPCIA_W2_MASK(ccp)) = MCPCIA_WMASK_1G;
sys/arch/alpha/pci/mcpcia_dma.c
235
REGVAL(MCPCIA_T2_BASE(ccp)) =
sys/arch/alpha/pci/mcpcia_dma.c
238
REGVAL(MCPCIA_W2_BASE(ccp)) =
sys/arch/alpha/pci/mcpcia_dma.c
90
REGVAL(MCPCIA_SG_TBIA(ccp)) = 0xdeadbeef; \
sys/arch/alpha/pci/pci_kn20aa.c
176
REGVAL(0x8780000000L + 0x40L) |= (1 << irq); /* XXX */
sys/arch/alpha/pci/pci_kn20aa.c
185
REGVAL(0x8780000000L + 0x40L) &= ~(1 << irq); /* XXX */
sys/arch/alpha/pci/pci_kn300.c
123
if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) {
sys/arch/alpha/pci/pci_kn300.c
304
REGVAL(MCPCIA_INT_MASK0(ccp)) |= (1 << irq);
sys/arch/alpha/pci/pci_kn300.c
312
REGVAL(MCPCIA_INT_MASK0(ccp)) &= ~(1 << irq);
sys/arch/alpha/pci/pci_kn8ae.c
243
REGVAL(PCIA_DEVVEC(hpc, device, pin) + ccp->cc_sysbase) = vec;
sys/arch/alpha/pci/pci_kn8ae.c
318
REGVAL(PCIA_IMASK(hpc) + paddr) = val;
sys/arch/alpha/pci/ttwogareg.h
178
#define _T2GA(b, r) REGVAL((T2_CBUS_TTWOGA_BASE + (T2_SIZE * (b))) + (r))
sys/arch/evbmips/gdium/bonito_mainbus.c
79
rev = PCI_REVISION(REGVAL(BONITO_PCICLASS));
sys/arch/evbmips/gdium/gdium_intr.c
209
REGVAL(BONITO_INTENCLR) = intbit;
sys/arch/evbmips/gdium/gdium_intr.c
212
REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE;
sys/arch/evbmips/gdium/gdium_intr.c
213
REGVAL(BONITO_INTEDGE) = bc->bc_intEdge;
sys/arch/evbmips/gdium/gdium_intr.c
214
REGVAL(BONITO_INTSTEER) = bc->bc_intSteer;
sys/arch/evbmips/gdium/gdium_intr.c
215
REGVAL(BONITO_INTPOL) = bc->bc_intPol;
sys/arch/evbmips/gdium/gdium_intr.c
260
REGVAL(BONITO_INTENSET) = (1 << ih->ih_irq);
sys/arch/evbmips/gdium/gdium_intr.c
289
REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq);
sys/arch/evbmips/gdium/gdium_intr.c
308
isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
sys/arch/evbmips/gdium/machdep.c
434
REGVAL(BONITO_GPIODATA) |= 2;
sys/arch/evbmips/gdium/machdep.c
435
REGVAL(BONITO_GPIOIE) &= ~2;
sys/arch/evbmips/gdium/machdep.c
452
REGVAL(BONITO_GPIODATA) &= ~4;
sys/arch/evbmips/gdium/machdep.c
453
REGVAL(BONITO_GPIOIE) &= ~4;
sys/arch/evbmips/loongson/bonito_mainbus.c
93
rev = PCI_REVISION(REGVAL(BONITO_PCICLASS));
sys/arch/evbmips/loongson/dev/kb3310.c
470
ykbec_chip_config = REGVAL(LOONGSON_CHIP_CONFIG0);
sys/arch/evbmips/loongson/dev/kb3310.c
472
REGVAL(LOONGSON_CHIP_CONFIG0) = ykbec_chip_config & ~0x7;
sys/arch/evbmips/loongson/dev/kb3310.c
473
(void)REGVAL(LOONGSON_CHIP_CONFIG0);
sys/arch/evbmips/loongson/dev/kb3310.c
492
REGVAL(LOONGSON_CHIP_CONFIG0) = ykbec_chip_config;
sys/arch/evbmips/loongson/dev/kb3310.c
493
(void)REGVAL(LOONGSON_CHIP_CONFIG0);
sys/arch/evbmips/loongson/gdium_machdep.c
312
REGVAL(BONITO_GPIODATA) |= 0x00000002;
sys/arch/evbmips/loongson/gdium_machdep.c
313
REGVAL(BONITO_GPIOIE) &= ~0x00000002;
sys/arch/evbmips/loongson/gdium_machdep.c
321
REGVAL(BONITO_GPIODATA) &= ~0x00000002;
sys/arch/evbmips/loongson/gdium_machdep.c
322
REGVAL(BONITO_GPIOIE) &= ~0x00000002;
sys/arch/evbmips/loongson/generic2e_machdep.c
361
REGVAL(BONITO_BONGENCFG) &= ~BONITO_BONGENCFG_CPUSELFRESET;
sys/arch/evbmips/loongson/generic2e_machdep.c
362
REGVAL(BONITO_BONGENCFG) |= BONITO_BONGENCFG_CPUSELFRESET;
sys/arch/evbmips/loongson/loongson_clock.c
174
REGVAL(LS2F_CHIPCFG0) =
sys/arch/evbmips/loongson/loongson_clock.c
175
(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 7;
sys/arch/evbmips/loongson/loongson_clock.c
224
REGVAL(LS2F_CHIPCFG0) =
sys/arch/evbmips/loongson/loongson_clock.c
225
(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) |
sys/arch/evbmips/loongson/loongson_intr.c
117
REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE;
sys/arch/evbmips/loongson/loongson_intr.c
118
REGVAL(BONITO_INTEDGE) = bc->bc_intEdge;
sys/arch/evbmips/loongson/loongson_intr.c
120
REGVAL(BONITO_INTPOL) = bc->bc_intPol;
sys/arch/evbmips/loongson/loongson_intr.c
121
REGVAL(BONITO_INTENCLR) = 0xffffffff;
sys/arch/evbmips/loongson/loongson_intr.c
122
(void)REGVAL(BONITO_INTENCLR);
sys/arch/evbmips/loongson/loongson_intr.c
150
isr0 = REGVAL(BONITO_INTISR);
sys/arch/evbmips/loongson/loongson_intr.c
151
imr = REGVAL(BONITO_INTEN);
sys/arch/evbmips/loongson/loongson_intr.c
156
REGVAL(BONITO_INTENCLR) = isr;
sys/arch/evbmips/loongson/loongson_intr.c
157
(void)REGVAL(BONITO_INTENCLR);
sys/arch/evbmips/loongson/loongson_intr.c
171
REGVAL(BONITO_INTENSET) = isr;
sys/arch/evbmips/loongson/loongson_intr.c
172
(void)REGVAL(BONITO_INTENSET);
sys/arch/evbmips/loongson/loongson_intr.c
308
DPRINTF((" inten 0x%x", REGVAL(BONITO_INTEN)));
sys/arch/evbmips/loongson/loongson_intr.c
310
REGVAL(BONITO_INTENSET) = (1 << ih->ih_irq);
sys/arch/evbmips/loongson/loongson_intr.c
311
DPRINTF((" now 0x%x\n", REGVAL(BONITO_INTEN)));
sys/arch/evbmips/loongson/loongson_intr.c
328
REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq);
sys/arch/evbmips/loongson/yeeloong_machdep.c
513
REGVAL(gpiobase + GCSC_GPIOL_OUT_EN) = GCSC_GPIO_ATOMIC_VALUE(13, 1);
sys/arch/evbmips/loongson/yeeloong_machdep.c
515
REGVAL(gpiobase + GCSC_GPIOL_OUT_VAL) = GCSC_GPIO_ATOMIC_VALUE(13, 0);
sys/arch/evbmips/loongson/yeeloong_machdep.c
522
REGVAL(BONITO_GPIODATA) &= ~0x00000001;
sys/arch/evbmips/loongson/yeeloong_machdep.c
523
REGVAL(BONITO_GPIOIE) &= ~0x00000001;
sys/arch/evbmips/malta/machdep.c
362
REGVAL(MALTA_SOFTRES) = MALTA_GORESET;
sys/arch/mips/alchemy/au_icu.c
170
REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
171
REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
172
REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
173
REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
174
REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
175
REGVAL(ic0_base + IC_TEST_BIT) = 0;
sys/arch/mips/alchemy/au_icu.c
177
REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
178
REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
179
REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
180
REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
181
REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff;
sys/arch/mips/alchemy/au_icu.c
182
REGVAL(ic1_base + IC_TEST_BIT) = 0;
sys/arch/mips/alchemy/au_icu.c
236
REGVAL(icu_base + IC_CONFIG2_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
237
REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
238
REGVAL(icu_base + IC_CONFIG0_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
241
REGVAL(icu_base + IC_CONFIG2_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
242
REGVAL(icu_base + IC_CONFIG1_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
243
REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
250
REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
252
REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
255
REGVAL(icu_base + IC_SOURCE_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
258
REGVAL(icu_base + IC_MASK_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
261
REGVAL(icu_base + IC_WAKEUP_SET) = irq;
sys/arch/mips/alchemy/au_icu.c
296
REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
297
REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
298
REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
301
REGVAL(icu_base + IC_MASK_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
302
REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq;
sys/arch/mips/alchemy/au_icu.c
340
irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
sys/arch/mips/alchemy/au_icu.c
344
irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
sys/arch/mips/alchemy/au_icu.c
348
irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
sys/arch/mips/alchemy/au_icu.c
352
irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
sys/arch/mips/alchemy/au_icu.c
355
irqmask = REGVAL(icu_base + IC_MASK_READ);
sys/arch/mips/alchemy/au_icu.c
364
if (REGVAL(icu_base + IC_MASK_READ) & mask) {
sys/arch/mips/alchemy/au_icu.c
365
REGVAL(icu_base + IC_MASK_CLEAR) = mask;
sys/arch/mips/alchemy/au_icu.c
366
REGVAL(icu_base + IC_MASK_SET) = mask;
sys/arch/mips/alchemy/au_icu.c
396
REGVAL(icu_base + IC_MASK_SET) = mask;
sys/arch/mips/alchemy/au_icu.c
397
REGVAL(icu_base + IC_WAKEUP_SET) = mask;
sys/arch/mips/alchemy/au_icu.c
417
REGVAL(icu_base + IC_MASK_CLEAR) = mask;
sys/arch/mips/alchemy/au_icu.c
418
REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask;
sys/arch/mips/alchemy/dev/aurtc.c
88
#define GETREG(x) (REGVAL(x))
sys/arch/mips/alchemy/dev/aurtc.c
89
#define PUTREG(x,v) (REGVAL(x) = (v))
sys/arch/mips/atheros/ar5312_board.c
74
fctl = REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_0) &
sys/arch/mips/atheros/ar5312_board.c
85
REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_0) = fctl;
sys/arch/mips/atheros/ar5312_board.c
87
REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_1) &=
sys/arch/mips/atheros/ar5312_board.c
90
REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_2) &=
sys/arch/mips/atheros/ar5315.c
84
#define GETSYSREG(x) REGVAL((x) + AR5315_SYSREG_BASE)
sys/arch/mips/atheros/ar5315.c
85
#define PUTSYSREG(x,v) (REGVAL((x) + AR5315_SYSREG_BASE)) = (v)
sys/arch/mips/atheros/ar5315.c
86
#define GETPCIREG(x) REGVAL((x) + AR5315_PCI_BASE)
sys/arch/mips/atheros/ar5315.c
87
#define PUTPCIREG(x,v) (REGVAL((x) + AR5315_PCI_BASE)) = (v)
sys/arch/mips/atheros/ar5315.c
88
#define GETSDRAMREG(x) REGVAL((x) + AR5315_SDRAMCTL_BASE)
sys/arch/mips/atheros/ar7100.c
132
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_0) = 0x10000000;
sys/arch/mips/atheros/ar7100.c
133
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_1) = 0x11000000;
sys/arch/mips/atheros/ar7100.c
134
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_2) = 0x12000000;
sys/arch/mips/atheros/ar7100.c
135
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_3) = 0x13000000;
sys/arch/mips/atheros/ar7100.c
136
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_4) = 0x14000000;
sys/arch/mips/atheros/ar7100.c
137
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_5) = 0x15000000;
sys/arch/mips/atheros/ar7100.c
138
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_6) = 0x16000000;
sys/arch/mips/atheros/ar7100.c
139
REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_7) = 0x07000000;
sys/arch/mips/atheros/ar_intr.c
104
REGVAL(platformsw->apsw_misc_intmask) = v;
sys/arch/mips/atheros/ar_intr.c
86
return REGVAL(platformsw->apsw_misc_intstat);
sys/arch/mips/atheros/ar_intr.c
92
REGVAL(platformsw->apsw_misc_intstat) = v;
sys/arch/mips/atheros/ar_intr.c
98
return REGVAL(platformsw->apsw_misc_intmask);
sys/arch/mips/atheros/dev/ehci_arbus.c
111
REGVAL(AR9344_USB_CONFIG_BASE) = 0x20c00; /* magic */
sys/arch/mips/atheros/include/ar5312reg.h
173
#define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE)
sys/arch/mips/atheros/include/ar5312reg.h
174
#define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v)
sys/arch/mips/atheros/include/ar5312reg.h
175
#define GETSDRAMREG(x) REGVAL((x) + AR5312_SDRAMCTL_BASE)
sys/arch/mips/atheros/include/ar5312reg.h
176
#define PUTSDRAMREG(x,v) (REGVAL((x) + AR5312_SDRAMCTL_BASE)) = (v)
sys/arch/mips/atheros/include/ar9344reg.h
347
#define GETRESETREG(x) REGVAL((x) + ARCHIP_RESET_BASE)
sys/arch/mips/atheros/include/ar9344reg.h
348
#define PUTRESETREG(x,v) (REGVAL((x) + ARCHIP_RESET_BASE)) = (v)
sys/arch/mips/atheros/include/ar9344reg.h
349
#define GETPLLREG(x) REGVAL((x) + ARCHIP_PLL_BASE)
sys/arch/mips/atheros/include/ar9344reg.h
350
#define PUTPLLREG(x,v) (REGVAL((x) + ARCHIP_PLL_BASE)) = (v)
sys/arch/mips/atheros/include/ar9344reg.h
351
#define GETDDRREG(x) REGVAL((x) + ARCHIP_DDR_BASE)
sys/arch/mips/atheros/include/ar9344reg.h
352
#define PUTDDRREG(x,v) (REGVAL((x) + ARCHIP_DDR_BASE)) = (v)
sys/arch/mips/bonito/bonito_iobc.c
113
tag = REGVAL(BONITO_PCICACHETAG);
sys/arch/mips/bonito/bonito_iobc.c
142
tag = REGVAL(BONITO_PCICACHETAG);
sys/arch/mips/bonito/bonito_iobc.c
83
REGVAL(BONITO_PCICACHECTRL) = ctrl;
sys/arch/mips/bonito/bonito_iobc.c
86
REGVAL(BONITO_PCICACHECTRL) = ctrl | BONITO_PCICACHECTRL_CMDEXEC;
sys/arch/mips/bonito/bonito_iobc.c
89
while (REGVAL(BONITO_PCICACHECTRL) & BONITO_PCICACHECTRL_CMDEXEC)
sys/arch/mips/bonito/bonito_iobc.c
92
REGVAL(BONITO_PCICACHECTRL) = ctrl;
sys/arch/mips/bonito/bonito_pci.c
154
REGVAL(BONITO_PCICMD) |=
sys/arch/mips/bonito/bonito_pci.c
158
REGVAL(BONITO_PCIMAP_CFG) = (cfgoff >> 16) | pcimap_cfg;
sys/arch/mips/bonito/bonito_pci.c
162
(void)REGVAL(BONITO_PCIMAP_CFG);
sys/arch/mips/bonito/bonito_pci.c
165
data = REGVAL(BONITO_PCICFG_BASE + (cfgoff & 0xfffc));
sys/arch/mips/bonito/bonito_pci.c
168
if (REGVAL(BONITO_PCICMD) &
sys/arch/mips/bonito/bonito_pci.c
190
REGVAL(BONITO_PCICMD) |=
sys/arch/mips/bonito/bonito_pci.c
194
REGVAL(BONITO_PCIMAP_CFG) = (cfgoff >> 16) | pcimap_cfg;
sys/arch/mips/bonito/bonito_pci.c
198
(void)REGVAL(BONITO_PCIMAP_CFG);
sys/arch/mips/bonito/bonito_pci.c
201
REGVAL(BONITO_PCICFG_BASE + (cfgoff & 0xfffc)) = data;
sys/dev/pci/voyager/pwmclock.c
157
REGVAL(LS2F_CHIPCFG0) =
sys/dev/pci/voyager/pwmclock.c
158
(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | clk;
sys/dev/pci/voyager/pwmclock.c
234
REGVAL(LS2F_CHIPCFG0) =
sys/dev/pci/voyager/pwmclock.c
235
(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 7;
sys/dev/pci/voyager/pwmclock.c
294
REGVAL(LS2F_CHIPCFG0) =
sys/dev/pci/voyager/pwmclock.c
295
(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) |