PMAP_WIRED
pmap_enter(pmap_efirt(), va, pa, prot, flags | PMAP_WIRED);
if (flags & PMAP_WIRED)
_pmap_enter(pmap_kernel(), va, pa, prot, flags | PMAP_WIRED, true);
} else if (flags & PMAP_WIRED) {
if (flags & PMAP_WIRED)
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
const bool wired = (flags & PMAP_WIRED) != 0;
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
VM_PROT_READ, VM_PROT_READ|PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
pmap_enter(pmap_efirt(), va, pa, prot, flags | PMAP_WIRED);
u_int pmap_flags = PMAP_WIRED;
VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED);
KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0);
if (flags & PMAP_WIRED)
VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED |
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
VM_PROT_READ, VM_PROT_READ|PMAP_WIRED);
VM_PROT_READ, VM_PROT_READ|PMAP_WIRED);
VM_PROT_READ, VM_PROT_READ|PMAP_WIRED);
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
bool wired = (flags & PMAP_WIRED) != 0;
VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
wired = (flags & PMAP_WIRED) != 0;
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED |
VM_PROT_WRITE|PMAP_WIRED);
if (flags & PMAP_WIRED) {
const pt_entry_t npte = pmap_make_pte(pa, prot, flags | PMAP_WIRED);
(pte_wired_p(pte) ? PMAP_WIRED : 0) |
const int flags = MMU_IS_HP_CLASS ? PMAP_NOCACHE|PMAP_WIRED
: PMAP_WIRED;
const int flags = MMU_IS_HP_CLASS ? PMAP_NOCACHE|PMAP_WIRED
: PMAP_WIRED;
PMAP_WIRED | PMAP_NOCACHE);
PMAP_WIRED | PMAP_NOCACHE);
bool wired = (flags & PMAP_WIRED) != 0;
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
PMAP_WIRED);
(flags & BUS_SPACE_MAP_CACHEABLE) ? PMAP_WIRED
: (PMAP_WIRED | PMAP_NOCACHE);
VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED);
VM_PROT_ALL, VM_PROT_ALL|PMAP_WIRED);
VM_PROT_READ, VM_PROT_READ|PMAP_WIRED);
PMAP_WIRED | VM_PROT_READ | VM_PROT_WRITE);
PMAP_WIRED);
if (flags & PMAP_WIRED) {
if (flags & PMAP_WIRED)
if (tte && ((flags & PMAP_WIRED) == 0)) {
VM_PROT_ALL | PMAP_WIRED);
PMAP_NOCACHE | PMAP_WIRED);
VM_PROT_ALL|PMAP_WIRED);
if (flags & PMAP_WIRED)
NULL, va, pa, pte_lo, prot|PMAP_WIRED);
PMAP_WIRED |
u_int pmap_flags = PMAP_WIRED;
PMAP_WIRED);
if (flags & PMAP_WIRED)
VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
if (pte & PG_WIRED && (flags & PMAP_WIRED) == 0) {
} else if ((pte & PG_WIRED) == 0 && flags & PMAP_WIRED) {
if (flags & PMAP_WIRED) {
if ((flags & PMAP_WIRED) != 0)
if (flags & PMAP_WIRED) {
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
bool wired = (flags & PMAP_WIRED) != 0;
VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
bool wired = (flags & PMAP_WIRED) != 0;
VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
bool wired = (flags & PMAP_WIRED) != 0;
wired = ((flags & PMAP_WIRED) != 0);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
pmap_do_enter(pmap_kernel(), va, pa, prot, prot | PMAP_WIRED, 1);
if (flags & PMAP_WIRED)
prot, prot | PMAP_WIRED);
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
pmap, v, p, prot, (flags & PMAP_WIRED) != 0, flags & VM_PROT_ALL));
if (flags & PMAP_WIRED)
if ((flags & PMAP_WIRED) != 0)
if (flags & PMAP_WIRED)
VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
u_int pmapflags = PMAP_WIRED | VM_PROT_READ | VM_PROT_WRITE;
bool wired = (flags & PMAP_WIRED) != 0;
bool wired = (flags & PMAP_WIRED) != 0;
pmapflags | PMAP_WIRED |
pmap_kenter_pa(kva + poff, pa, prot, PMAP_WIRED);
const bool wired = (flags & PMAP_WIRED) != 0;
PMAP_CANFAIL | (flt->wire_mapping ? PMAP_WIRED : 0));
(flt->wire_mapping ? PMAP_WIRED : 0)) != 0) {
PMAP_CANFAIL | (flt->wire_mapping ? (mapprot | PMAP_WIRED) : 0);
(flt->wire_mapping ? PMAP_WIRED : 0)) != 0) {
pmap_enter(pmap_kernel(), sva, pa, prot, PMAP_WIRED);