drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h

root/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h
/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */

#ifndef _clk_15_0_0_OFFSET_HEADER
#define _clk_15_0_0_OFFSET_HEADER

// addressBlock: clk_clk8_0_SmuClkDec
// base address: 0x6e000
#define regCLK8_CLK0_DS_CNTL                                                                            0x4c14
#define regCLK8_CLK0_DS_CNTL_BASE_IDX                                                                   0
#define regCLK8_CLK1_DS_CNTL                                                                            0x4c1c
#define regCLK8_CLK1_DS_CNTL_BASE_IDX                                                                   0
#define regCLK8_CLK2_DS_CNTL                                                                            0x4c24
#define regCLK8_CLK2_DS_CNTL_BASE_IDX                                                                   0
#define regCLK8_CLK3_DS_CNTL                                                                            0x4c2c
#define regCLK8_CLK3_DS_CNTL_BASE_IDX                                                                   0
#define regCLK8_CLK4_DS_CNTL                                                                            0x4c34
#define regCLK8_CLK4_DS_CNTL_BASE_IDX                                                                   0
#define regCLK8_CLK0_BYPASS_CNTL                                                                        0x4c1a
#define regCLK8_CLK0_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK8_CLK1_BYPASS_CNTL                                                                        0x4c22
#define regCLK8_CLK1_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK8_CLK2_BYPASS_CNTL                                                                        0x4c2a
#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK8_CLK3_BYPASS_CNTL                                                                        0x4c32
#define regCLK8_CLK3_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK8_CLK4_BYPASS_CNTL                                                                        0x4c3a
#define regCLK8_CLK4_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK8_CLK_TICK_CNT_CONFIG_REG                                                                 0x4c51
#define regCLK8_CLK_TICK_CNT_CONFIG_REG_BASE_IDX                                                        0
#define regCLK8_CLK_TICK_CNT_STATUS                                                                     0x4c52
#define regCLK8_CLK_TICK_CNT_STATUS_BASE_IDX                                                            0
#define regCLK8_CLK0_CURRENT_CNT                                                                        0x4c53
#define regCLK8_CLK0_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK8_CLK1_CURRENT_CNT                                                                        0x4c54
#define regCLK8_CLK1_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK8_CLK2_CURRENT_CNT                                                                        0x4c55
#define regCLK8_CLK2_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK8_CLK3_CURRENT_CNT                                                                        0x4c56
#define regCLK8_CLK3_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK8_CLK4_CURRENT_CNT                                                                        0x4c57
#define regCLK8_CLK4_CURRENT_CNT_BASE_IDX                                                               0

#endif
Linux
