drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h

root/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h
// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.

#ifndef _clk_15_0_5_SH_MASK_HEADER
#define _clk_15_0_5_SH_MASK_HEADER


// addressBlock: clk_clk5_0_SmuClkDec
//CLK5_CLK_TICK_CNT_CONFIG_REG
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT                                                  0x0
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK                                                    0x00FFFFFFL
//CLK5_CLK0_BYPASS_CNTL
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK1_BYPASS_CNTL
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK2_BYPASS_CNTL
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK3_BYPASS_CNTL
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK0_DS_CNTL
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK                                                                 0x00000010L
//CLK5_CLK1_DS_CNTL
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK                                                                 0x00000010L
//CLK5_CLK2_DS_CNTL
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK                                                                 0x00000010L
//CLK5_CLK3_DS_CNTL
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK                                                                 0x00000010L

#endif
Linux
