mb
#define mb() __asm__ __volatile__("mb": : :"memory")
#define mb() asm volatile("dmb 3\n" : : : "memory")
#define mb() asm volatile("sync\n" : : : "memory")
#define mb() __arm_heavy_mb()
#define mb() barrier()
#define mb() asm volatile ("sync\n":::"memory")
#define mb() c_sync()
#define mb() __asm__ __volatile__ ("mbar 1" : : : "memory")
#define mb() wbflush()
#define mb() fast_mb()
#define mb() asm volatile ("l.msync" ::: "memory")
#define mb() do { synchronize_caches(); } while (0)
#define mb() barrier()
#define mb() __asm__ __volatile__ ("synco": : :"memory")
#define mb() membar_safe("#StoreLoad")
#define mb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "mfence", \
#define mb() alternative("lock addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
#define mb() asm volatile("mfence" : : : "memory")
#define mb() do { kcsan_mb(); __mb(); } while (0)
#define mb() barrier()
#define mb() __asm__ __volatile__("mb": : :"memory")
#define mb() ((void(*)(void))0xffff0fa0)()
#define mb() asm volatile("dmb ish" ::: "memory")
#define mb() asm volatile( \
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
#define mb() RISCV_FENCE(iorw, iorw)
#define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
#define mb() __asm__ __volatile__ ("synco": : :"memory")
#define mb() membar_safe("#StoreLoad")
#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define mb() asm volatile("mfence" ::: "memory")
#define mb() ({ __asm__ __volatile__("memw" : : : "memory"); })
#define mb() barrier()
#define mb() asm volatile("sync" : : : "memory");
# define mb() abort()
# define mb() abort()