/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef __IRIS_VPU_REGISTER_DEFINES_H__
#define __IRIS_VPU_REGISTER_DEFINES_H__

#define VCODEC_BASE_OFFS                        0x00000000
#define AON_MVP_NOC_RESET                       0x0001F000
#define CPU_BASE_OFFS                           0x000A0000
#define WRAPPER_BASE_OFFS                       0x000B0000
#define WRAPPER_TZ_BASE_OFFS                    0x000C0000
#define AON_BASE_OFFS                           0x000E0000

#define VCODEC_SS_IDLE_STATUSN                  (VCODEC_BASE_OFFS + 0x70)

#define AON_WRAPPER_MVP_NOC_RESET_REQ           (AON_MVP_NOC_RESET + 0x000)
#define VIDEO_NOC_RESET_REQ                     (BIT(0) | BIT(1))

#define AON_WRAPPER_MVP_NOC_RESET_ACK           (AON_MVP_NOC_RESET + 0x004)

#define CPU_CS_BASE_OFFS                        (CPU_BASE_OFFS)
#define CPU_IC_BASE_OFFS                        (CPU_BASE_OFFS)

#define CPU_CS_A2HSOFTINTCLR                    (CPU_CS_BASE_OFFS + 0x1C)
#define CLEAR_XTENSA2HOST_INTR                  BIT(0)

#define CPU_CS_H2XSOFTINTEN                     (CPU_CS_BASE_OFFS + 0x148)
#define HOST2XTENSA_INTR_ENABLE                 BIT(0)

#define CPU_IC_SOFTINT                          (CPU_IC_BASE_OFFS + 0x150)
#define CPU_IC_SOFTINT_H2A_SHFT                 0x0

#define CPU_CS_AHB_BRIDGE_SYNC_RESET            (CPU_CS_BASE_OFFS + 0x160)
#define CORE_BRIDGE_SW_RESET                    BIT(0)
#define CORE_BRIDGE_HW_RESET_DISABLE            BIT(1)

#define CPU_CS_X2RPMH                           (CPU_CS_BASE_OFFS + 0x168)
#define MSK_SIGNAL_FROM_TENSILICA               BIT(0)
#define MSK_CORE_POWER_ON                       BIT(1)

#define WRAPPER_INTR_STATUS                     (WRAPPER_BASE_OFFS + 0x0C)
#define WRAPPER_INTR_STATUS_A2HWD_BMSK          BIT(3)
#define WRAPPER_INTR_STATUS_A2H_BMSK            BIT(2)

#define WRAPPER_INTR_MASK                       (WRAPPER_BASE_OFFS + 0x10)
#define WRAPPER_INTR_MASK_A2HWD_BMSK            BIT(3)
#define WRAPPER_INTR_MASK_A2HCPU_BMSK           BIT(2)

#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL        (WRAPPER_BASE_OFFS + 0x54)
#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS         (WRAPPER_BASE_OFFS + 0x58)
#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL        (WRAPPER_BASE_OFFS + 0x5C)
#define REQ_POWER_DOWN_PREP                     BIT(0)

#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS         (WRAPPER_BASE_OFFS + 0x60)
#define NOC_LPI_STATUS_DONE                     BIT(0) /* Indicates the NOC handshake is complete */
#define NOC_LPI_STATUS_DENY                     BIT(1) /* Indicates the NOC handshake is denied */
#define NOC_LPI_STATUS_ACTIVE                   BIT(2) /* Indicates the NOC is active */

#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
#define WRAPPER_CORE_POWER_STATUS               (WRAPPER_BASE_OFFS + 0x80)
#define WRAPPER_CORE_CLOCK_CONFIG               (WRAPPER_BASE_OFFS + 0x88)
#define CORE_CLK_RUN                            0x0

#define WRAPPER_TZ_CPU_STATUS                   (WRAPPER_TZ_BASE_OFFS + 0x10)

#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG         (WRAPPER_TZ_BASE_OFFS + 0x14)
#define CTL_AXI_CLK_HALT                        BIT(0)
#define CTL_CLK_HALT                            BIT(1)

#define WRAPPER_TZ_QNS4PDXFIFO_RESET            (WRAPPER_TZ_BASE_OFFS + 0x18)
#define RESET_HIGH                              BIT(0)

#define AON_WRAPPER_MVP_NOC_LPI_CONTROL         (AON_BASE_OFFS)
#define AON_WRAPPER_MVP_NOC_LPI_STATUS          (AON_BASE_OFFS + 0x4)

#endif