drivers/gpu/drm/i915/display/intel_cx0_phy.c

3127

disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

266

#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

270

#define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

283

#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

308

#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

312

#define PHY_C20_HDMI_RATE(val) REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

315

#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

376

#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

24

#define LT_PHY_TX_SWING_LEVEL(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val)

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

26

#define LT_PHY_TX_SWING(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val)

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

32

#define LT_PHY_TX_CURSOR(val) REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)