arch/arm/include/asm/hw_breakpoint.h

110

#define ARM_DBG_READ(N, M, OP2, VAL) do {\

arch/arm/include/asm/hw_breakpoint.h

111

asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\

arch/arm/include/asm/hw_breakpoint.h

114

#define ARM_DBG_WRITE(N, M, OP2, VAL) do {\

arch/arm/include/asm/hw_breakpoint.h

115

asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\

arch/arm/kernel/hw_breakpoint.c

49

#define READ_WB_REG_CASE(OP2, M, VAL) \

arch/arm/kernel/hw_breakpoint.c

51

ARM_DBG_READ(c0, c ## M, OP2, VAL); \

arch/arm/kernel/hw_breakpoint.c

54

#define WRITE_WB_REG_CASE(OP2, M, VAL) \

arch/arm/kernel/hw_breakpoint.c

56

ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \

arch/arm/kernel/hw_breakpoint.c

59

#define GEN_READ_WB_REG_CASES(OP2, VAL) \

arch/arm/kernel/hw_breakpoint.c

60

READ_WB_REG_CASE(OP2, 0, VAL); \

arch/arm/kernel/hw_breakpoint.c

61

READ_WB_REG_CASE(OP2, 1, VAL); \

arch/arm/kernel/hw_breakpoint.c

62

READ_WB_REG_CASE(OP2, 2, VAL); \

arch/arm/kernel/hw_breakpoint.c

63

READ_WB_REG_CASE(OP2, 3, VAL); \

arch/arm/kernel/hw_breakpoint.c

64

READ_WB_REG_CASE(OP2, 4, VAL); \

arch/arm/kernel/hw_breakpoint.c

65

READ_WB_REG_CASE(OP2, 5, VAL); \

arch/arm/kernel/hw_breakpoint.c

66

READ_WB_REG_CASE(OP2, 6, VAL); \

arch/arm/kernel/hw_breakpoint.c

67

READ_WB_REG_CASE(OP2, 7, VAL); \

arch/arm/kernel/hw_breakpoint.c

68

READ_WB_REG_CASE(OP2, 8, VAL); \

arch/arm/kernel/hw_breakpoint.c

69

READ_WB_REG_CASE(OP2, 9, VAL); \

arch/arm/kernel/hw_breakpoint.c

70

READ_WB_REG_CASE(OP2, 10, VAL); \

arch/arm/kernel/hw_breakpoint.c

71

READ_WB_REG_CASE(OP2, 11, VAL); \

arch/arm/kernel/hw_breakpoint.c

72

READ_WB_REG_CASE(OP2, 12, VAL); \

arch/arm/kernel/hw_breakpoint.c

73

READ_WB_REG_CASE(OP2, 13, VAL); \

arch/arm/kernel/hw_breakpoint.c

74

READ_WB_REG_CASE(OP2, 14, VAL); \

arch/arm/kernel/hw_breakpoint.c

75

READ_WB_REG_CASE(OP2, 15, VAL)

arch/arm/kernel/hw_breakpoint.c

77

#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \

arch/arm/kernel/hw_breakpoint.c

78

WRITE_WB_REG_CASE(OP2, 0, VAL); \

arch/arm/kernel/hw_breakpoint.c

79

WRITE_WB_REG_CASE(OP2, 1, VAL); \

arch/arm/kernel/hw_breakpoint.c

80

WRITE_WB_REG_CASE(OP2, 2, VAL); \

arch/arm/kernel/hw_breakpoint.c

81

WRITE_WB_REG_CASE(OP2, 3, VAL); \

arch/arm/kernel/hw_breakpoint.c

82

WRITE_WB_REG_CASE(OP2, 4, VAL); \

arch/arm/kernel/hw_breakpoint.c

83

WRITE_WB_REG_CASE(OP2, 5, VAL); \

arch/arm/kernel/hw_breakpoint.c

84

WRITE_WB_REG_CASE(OP2, 6, VAL); \

arch/arm/kernel/hw_breakpoint.c

85

WRITE_WB_REG_CASE(OP2, 7, VAL); \

arch/arm/kernel/hw_breakpoint.c

86

WRITE_WB_REG_CASE(OP2, 8, VAL); \

arch/arm/kernel/hw_breakpoint.c

87

WRITE_WB_REG_CASE(OP2, 9, VAL); \

arch/arm/kernel/hw_breakpoint.c

88

WRITE_WB_REG_CASE(OP2, 10, VAL); \

arch/arm/kernel/hw_breakpoint.c

89

WRITE_WB_REG_CASE(OP2, 11, VAL); \

arch/arm/kernel/hw_breakpoint.c

90

WRITE_WB_REG_CASE(OP2, 12, VAL); \

arch/arm/kernel/hw_breakpoint.c

91

WRITE_WB_REG_CASE(OP2, 13, VAL); \

arch/arm/kernel/hw_breakpoint.c

92

WRITE_WB_REG_CASE(OP2, 14, VAL); \

arch/arm/kernel/hw_breakpoint.c

93

WRITE_WB_REG_CASE(OP2, 15, VAL)

arch/arm64/include/asm/barrier.h

199

__unqual_scalar_typeof(*ptr) VAL; \

arch/arm64/include/asm/barrier.h

201

VAL = READ_ONCE(*__PTR); \

arch/arm64/include/asm/barrier.h

204

__cmpwait_relaxed(__PTR, VAL); \

arch/arm64/include/asm/barrier.h

206

(typeof(*ptr))VAL; \

arch/arm64/include/asm/barrier.h

212

__unqual_scalar_typeof(*ptr) VAL; \

arch/arm64/include/asm/barrier.h

214

VAL = smp_load_acquire(__PTR); \

arch/arm64/include/asm/barrier.h

217

__cmpwait_relaxed(__PTR, VAL); \

arch/arm64/include/asm/barrier.h

219

(typeof(*ptr))VAL; \

arch/arm64/include/asm/hw_breakpoint.h

102

#define AARCH64_DBG_WRITE(N, REG, VAL) do {\

arch/arm64/include/asm/hw_breakpoint.h

103

write_sysreg(VAL, dbg##REG##N##_el1);\

arch/arm64/include/asm/hw_breakpoint.h

98

#define AARCH64_DBG_READ(N, REG, VAL) do {\

arch/arm64/include/asm/hw_breakpoint.h

99

VAL = read_sysreg(dbg##REG##N##_el1);\

arch/arm64/include/asm/mte.h

207

smp_cond_load_acquire(&folio->flags.f, VAL & (1UL << PG_mte_tagged));

arch/arm64/include/asm/mte.h

93

smp_cond_load_acquire(&page->flags.f, VAL & (1UL << PG_mte_tagged));

arch/arm64/include/asm/rqspinlock.h

36

__unqual_scalar_typeof(*ptr) VAL; \

arch/arm64/include/asm/rqspinlock.h

39

VAL = READ_ONCE(*__PTR); \

arch/arm64/include/asm/rqspinlock.h

49

(typeof(*ptr))VAL; \

arch/arm64/include/asm/rqspinlock.h

56

__unqual_scalar_typeof(*ptr) VAL; \

arch/arm64/include/asm/rqspinlock.h

58

VAL = smp_load_acquire(__PTR); \

arch/arm64/include/asm/rqspinlock.h

61

__cmpwait_relaxed(__PTR, VAL); \

arch/arm64/include/asm/rqspinlock.h

65

(typeof(*ptr))VAL; \

arch/arm64/kernel/hw_breakpoint.c

100

WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

101

WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

102

WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

103

WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

104

WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

105

WRITE_WB_REG_CASE(OFF, 15, REG, VAL)

arch/arm64/kernel/hw_breakpoint.c

61

#define READ_WB_REG_CASE(OFF, N, REG, VAL) \

arch/arm64/kernel/hw_breakpoint.c

63

AARCH64_DBG_READ(N, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

66

#define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \

arch/arm64/kernel/hw_breakpoint.c

68

AARCH64_DBG_WRITE(N, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

71

#define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \

arch/arm64/kernel/hw_breakpoint.c

72

READ_WB_REG_CASE(OFF, 0, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

73

READ_WB_REG_CASE(OFF, 1, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

74

READ_WB_REG_CASE(OFF, 2, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

75

READ_WB_REG_CASE(OFF, 3, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

76

READ_WB_REG_CASE(OFF, 4, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

77

READ_WB_REG_CASE(OFF, 5, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

78

READ_WB_REG_CASE(OFF, 6, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

79

READ_WB_REG_CASE(OFF, 7, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

80

READ_WB_REG_CASE(OFF, 8, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

81

READ_WB_REG_CASE(OFF, 9, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

82

READ_WB_REG_CASE(OFF, 10, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

83

READ_WB_REG_CASE(OFF, 11, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

84

READ_WB_REG_CASE(OFF, 12, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

85

READ_WB_REG_CASE(OFF, 13, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

86

READ_WB_REG_CASE(OFF, 14, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

87

READ_WB_REG_CASE(OFF, 15, REG, VAL)

arch/arm64/kernel/hw_breakpoint.c

89

#define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \

arch/arm64/kernel/hw_breakpoint.c

90

WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

91

WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

92

WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

93

WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

94

WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

95

WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

96

WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

97

WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

98

WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \

arch/arm64/kernel/hw_breakpoint.c

99

WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \

arch/arm64/mm/mmu.c

922

smp_cond_load_acquire(&idmap_kpti_bbml2_flag, VAL == num_online_cpus());

arch/loongarch/include/asm/hw_breakpoint.h

57

#define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \

arch/loongarch/include/asm/hw_breakpoint.h

60

VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \

arch/loongarch/include/asm/hw_breakpoint.h

62

VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \

arch/loongarch/include/asm/hw_breakpoint.h

65

#define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \

arch/loongarch/include/asm/hw_breakpoint.h

68

csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \

arch/loongarch/include/asm/hw_breakpoint.h

70

csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \

arch/loongarch/kernel/hw_breakpoint.c

36

#define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \

arch/loongarch/kernel/hw_breakpoint.c

38

LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

41

#define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \

arch/loongarch/kernel/hw_breakpoint.c

43

LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

46

#define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \

arch/loongarch/kernel/hw_breakpoint.c

47

READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

48

READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

49

READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

50

READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

51

READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

52

READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

53

READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

54

READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

55

READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

56

READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

57

READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

58

READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

59

READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

60

READ_WB_REG_CASE(OFF, 13, REG, T, VAL);

arch/loongarch/kernel/hw_breakpoint.c

62

#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \

arch/loongarch/kernel/hw_breakpoint.c

63

WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

64

WRITE_WB_REG_CASE(OFF, 1, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

65

WRITE_WB_REG_CASE(OFF, 2, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

66

WRITE_WB_REG_CASE(OFF, 3, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

67

WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

68

WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

69

WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

70

WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

71

WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

72

WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

73

WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

74

WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

75

WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \

arch/loongarch/kernel/hw_breakpoint.c

76

WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);

arch/riscv/include/asm/barrier.h

72

__unqual_scalar_typeof(*ptr) VAL; \

arch/riscv/include/asm/barrier.h

74

VAL = READ_ONCE(*__PTR); \

arch/riscv/include/asm/barrier.h

77

__cmpwait_relaxed(ptr, VAL); \

arch/riscv/include/asm/barrier.h

79

(typeof(*ptr))VAL; \

arch/sparc/include/asm/tsb.h

113

#define TSB_STORE(ADDR, VAL) \

arch/sparc/include/asm/tsb.h

114

661: stxa VAL, [ADDR] ASI_N; \

arch/sparc/include/asm/tsb.h

117

stxa VAL, [ADDR] ASI_PHYS_USE_EC; \

arch/x86/kernel/alternative.c

3070

atomic_cond_read_acquire(refs, !VAL);

drivers/accel/ivpu/ivpu_mmu.c

441

return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);

drivers/accel/ivpu/ivpu_mmu.c

448

return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);

drivers/accel/ivpu/ivpu_mmu.c

468

ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod,

drivers/accel/ivpu/ivpu_mmu.c

883

return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);

drivers/comedi/drivers/s626.h

447

#define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))

drivers/comedi/drivers/s626.h

448

#define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))

drivers/comedi/drivers/s626.h

449

#define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))

drivers/gpio/gpio-it87.c

103

outb(ldn, VAL);

drivers/gpio/gpio-it87.c

109

return inb(VAL);

drivers/gpio/gpio-it87.c

115

outb(val, VAL);

drivers/gpio/gpio-it87.c

123

val = inb(VAL) << 8;

drivers/gpio/gpio-it87.c

125

val |= inb(VAL);

drivers/gpio/gpio-it87.c

96

outb(0x02, VAL);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/msgfn.h

12

# define E(RPC, VAL) NV_VGPU_MSG_EVENT_##RPC = VAL,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/rpcfn.h

12

# define X(UNIT, RPC, VAL) NV_VGPU_MSG_FUNCTION_##RPC = VAL,

drivers/gpu/drm/panel/panel-novatek-nt39016.c

70

#define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }

drivers/hwmon/smsc47b397.c

47

outb(val, VAL);

drivers/hwmon/smsc47b397.c

53

return inb(VAL);

drivers/hwmon/smsc47m1.c

50

outb(val, VAL);

drivers/hwmon/smsc47m1.c

57

return inb(VAL);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

509

atomic_cond_read_relaxed(&cmdq->lock, VAL > 0);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

626

atomic_long_cond_read_relaxed(ptr, (VAL & mask) == valid);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

698

smp_cond_load_relaxed(cmd, !VAL || (ret = queue_poll(&qp)));

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

867

atomic_cond_read_relaxed(&cmdq->owner_prod, VAL == llq.prod);

drivers/media/platform/rockchip/rkcif/rkcif-regs.h

14

#define RKCIF_FETCH_Y(VAL) ((VAL) & 0x1fff)

drivers/net/ethernet/freescale/fs_enet/mac-fcc.c

68

#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))

drivers/net/ethernet/freescale/fs_enet/mii-fec.c

46

#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

625

errcode = CMDQ_WQE_ERRCODE_GET(be32_to_cpu(status->status_info), VAL);

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

203

*cmd_info->errcode = CMDQ_WQE_ERRCODE_GET(status_info, VAL);

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

950

#define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

951

#define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

952

#define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

953

#define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

954

#define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

955

#define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

956

#define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f)

drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h

991

#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)

drivers/net/ethernet/qlogic/qlcnic/qlcnic.h

880

#define QLCNIC_IS_LB_CONFIGURED(VAL) \

drivers/net/ethernet/qlogic/qlcnic/qlcnic.h

881

(VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h

405

#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h

406

#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

641

#define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

642

#define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

643

#define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

644

#define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

645

#define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

647

#define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4)))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

648

#define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

678

#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)

drivers/pinctrl/pinctrl-rockchip.c

288

#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \

drivers/pinctrl/pinctrl-rockchip.c

294

.route_val = VAL, \

drivers/pinctrl/pinctrl-rockchip.c

298

#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \

drivers/pinctrl/pinctrl-rockchip.c

299

PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)

drivers/pinctrl/pinctrl-rockchip.c

301

#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \

drivers/pinctrl/pinctrl-rockchip.c

302

PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)

drivers/pinctrl/pinctrl-rockchip.c

304

#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \

drivers/pinctrl/pinctrl-rockchip.c

305

PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)

drivers/scsi/aha152x.h

289

#define SETPORT(PORT, VAL) outb( (VAL), (PORT) )

drivers/scsi/esp_scsi.c

117

#define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)

drivers/scsi/mac_esp.c

50

#define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)

drivers/scsi/qla2xxx/qla_nx.h

708

#define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)

drivers/scsi/qla2xxx/qla_nx.h

709

#define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)

drivers/scsi/qla4xxx/ql4_nx.h

746

#define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)

drivers/scsi/qla4xxx/ql4_nx.h

747

#define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)

drivers/scsi/sun3x_esp.c

45

#define dma_write32(VAL, REG) \

drivers/scsi/sun3x_esp.c

46

writel((VAL), esp->dma_regs + (REG))

drivers/scsi/sun3x_esp.c

50

#define dma_write32(VAL, REG) \

drivers/scsi/sun3x_esp.c

51

do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)

drivers/scsi/sun_esp.c

34

#define dma_write32(VAL, REG) \

drivers/scsi/sun_esp.c

35

sbus_writel((VAL), esp->dma_regs + (REG))

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1038

pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1042

pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1046

pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1051

pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1053

pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1063

pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1068

pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1084

(pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) &&

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1085

(pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) &&

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1086

(pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) &&

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1087

(pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1095

PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[path][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[path][IDX_0xC94][VAL]);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1096

PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[path][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[path][IDX_0xC80][VAL]);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1097

PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[path][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[path][IDX_0xC4C][VAL]);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1099

PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[path][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[path][IDX_0xC14][VAL]);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

1100

PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[path][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[path][IDX_0xCA0][VAL]);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

960

pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

964

pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

968

pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

973

pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

976

pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

987

pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord);

drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

992

pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);

drivers/watchdog/it8712f_wdt.c

101

outb(val, VAL);

drivers/watchdog/it8712f_wdt.c

108

val = inb(VAL) << 8;

drivers/watchdog/it8712f_wdt.c

110

val |= inb(VAL);

drivers/watchdog/it8712f_wdt.c

117

outb(ldn, VAL);

drivers/watchdog/it8712f_wdt.c

138

outb(0x02, VAL);

drivers/watchdog/it8712f_wdt.c

95

return inb(VAL);

drivers/watchdog/it87_wdt.c

136

outb(0x02, VAL);

drivers/watchdog/it87_wdt.c

143

outb(ldn, VAL);

drivers/watchdog/it87_wdt.c

149

return inb(VAL);

drivers/watchdog/it87_wdt.c

155

outb(val, VAL);

drivers/watchdog/it87_wdt.c

163

val = inb(VAL) << 8;

drivers/watchdog/it87_wdt.c

165

val |= inb(VAL);

include/asm-generic/barrier.h

248

__unqual_scalar_typeof(*ptr) VAL; \

include/asm-generic/barrier.h

250

VAL = READ_ONCE(*__PTR); \

include/asm-generic/barrier.h

255

(typeof(*ptr))VAL; \

include/asm-generic/ticket_spinlock.h

49

atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);

include/linux/dma-mapping.h

771

#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))

include/linux/dma-mapping.h

773

#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))

include/linux/dma-mapping.h

779

#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) \

include/linux/dma-mapping.h

783

#define dma_unmap_len_set(PTR, LEN_NAME, VAL) \

include/linux/netdevice.h

5674

#define DEV_STATS_ADD(DEV, FIELD, VAL) \

include/linux/netdevice.h

5675

atomic_long_add((VAL), &(DEV)->stats.__##FIELD)

include/net/netmem.h

423

#define netmem_dma_unmap_addr_set(NETMEM, PTR, ADDR_NAME, VAL) \

include/net/netmem.h

426

dma_unmap_addr_set(PTR, ADDR_NAME, VAL); \

include/uapi/linux/btf.h

93

#define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24)

include/uapi/linux/btf.h

94

#define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16)

include/uapi/linux/btf.h

95

#define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff)

kernel/bpf/helpers.c

317

atomic_cond_read_relaxed(l, !VAL);

kernel/bpf/rqspinlock.c

362

(VAL != _Q_PENDING_VAL) || !cnt--);

kernel/bpf/rqspinlock.c

409

res_smp_cond_load_acquire(&lock->locked, !VAL || RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_MASK));

kernel/bpf/rqspinlock.c

570

val = res_atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK) ||

kernel/bpf/rqspinlock.c

576

next = smp_cond_load_relaxed(&node->next, (VAL));

kernel/bpf/rqspinlock.c

608

next = smp_cond_load_relaxed(&node->next, VAL);

kernel/bpf/rqspinlock.c

647

next = smp_cond_load_relaxed(&node->next, (VAL));

kernel/futex/requeue.c

189

(void)atomic_cond_read_relaxed(&q->requeue_state, VAL != Q_REQUEUE_PI_WAIT);

kernel/locking/mcs_spinlock.h

27

smp_cond_load_acquire(l, VAL)

kernel/locking/osq_lock.c

146

if (smp_cond_load_relaxed(&node->locked, VAL || need_resched() ||

kernel/locking/qrwlock.c

33

atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED));

kernel/locking/qrwlock.c

51

atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED));

kernel/locking/qrwlock.c

85

cnts = atomic_cond_read_relaxed(&lock->cnts, VAL == _QW_WAITING);

kernel/locking/qspinlock.c

153

(VAL != _Q_PENDING_VAL) || !cnt--);

kernel/locking/qspinlock.c

197

smp_cond_load_acquire(&lock->locked, !VAL);

kernel/locking/qspinlock.c

328

val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK));

kernel/locking/qspinlock.c

368

next = smp_cond_load_relaxed(&node->next, (VAL));

kernel/rcu/rcuscale.c

879

smp_cond_load_relaxed(&rcu_lazy_test1_cb_called, VAL == 1);

kernel/sched/core.c

3749

smp_cond_load_acquire(&p->on_cpu, !VAL);

kernel/sched/core.c

4228

smp_cond_load_acquire(&p->on_cpu, !VAL);

kernel/sched/core.c

4278

smp_cond_load_acquire(&p->on_cpu, !VAL);

kernel/smp.c

342

smp_cond_load_acquire(&csd->node.u_flags, !(VAL & CSD_FLAG_LOCK));

kernel/smp.c

351

smp_cond_load_acquire(&csd->node.u_flags, !(VAL & CSD_FLAG_LOCK));

tools/include/uapi/linux/btf.h

93

#define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24)

tools/include/uapi/linux/btf.h

94

#define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16)

tools/include/uapi/linux/btf.h

95

#define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff)

tools/testing/selftests/bpf/bpf_atomic.h

107

__unqual_typeof(*(p)) VAL; \

tools/testing/selftests/bpf/bpf_atomic.h

109

VAL = (__unqual_typeof(*(p)))READ_ONCE(*__ptr); \

tools/testing/selftests/bpf/bpf_atomic.h

115

(typeof(*(p)))VAL; \

tools/testing/selftests/bpf/bpf_experimental.h

257

#define __bpf_assert(LHS, op, cons, RHS, VAL) \

tools/testing/selftests/bpf/bpf_experimental.h

261

: : [lhs] "r"(LHS), [rhs] cons(RHS), [value] "ri"(VAL) : ); \

tools/testing/selftests/bpf/bpf_experimental.h

264

#define __bpf_assert_op_sign(LHS, op, cons, RHS, VAL, supp_sign) \

tools/testing/selftests/bpf/bpf_experimental.h

268

__bpf_assert(LHS, "s" #op, cons, RHS, VAL); \

tools/testing/selftests/bpf/bpf_experimental.h

270

__bpf_assert(LHS, #op, cons, RHS, VAL); \

tools/testing/selftests/bpf/bpf_experimental.h

273

#define __bpf_assert_op(LHS, op, RHS, VAL, supp_sign) \

tools/testing/selftests/bpf/bpf_experimental.h

277

__bpf_assert_op_sign(LHS, op, "r", rhs_var, VAL, supp_sign); \

tools/testing/selftests/bpf/bpf_experimental.h

279

__bpf_assert_op_sign(LHS, op, "i", RHS, VAL, supp_sign); \

tools/testing/selftests/bpf/progs/arena_atomics.c

373

#define STORE_RELEASE_ARENA(SIZEOP, DST, VAL) \

tools/testing/selftests/bpf/progs/arena_atomics.c

375

"r1 = " VAL ";" \

tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h

10

#define arch_mcs_spin_lock_contended_label(l, label) smp_cond_load_acquire_label(l, VAL, label)

tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h

260

(VAL != _Q_PENDING_VAL) || !cnt--,

tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h

305

(void)smp_cond_load_acquire_label(&lock->locked, !VAL, release_err);

tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h

404

val = atomic_cond_read_acquire_label(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK),

tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h

444

next = smp_cond_load_relaxed_label(&node->next, (VAL), release_node_err);