PCI_COMMAND_IO
pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_IO;
newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
conf_data |= PCI_COMMAND_IO;
conf_data |= PCI_COMMAND_IO;
if (value & PCI_COMMAND_IO)
conf_data |= PCI_COMMAND_IO;
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))
== (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
disabled = !(command & PCI_COMMAND_IO);
if (command & PCI_COMMAND_IO)
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER | PCI_COMMAND_IO);
pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
cmd &= ~PCI_COMMAND_IO;
cmd &= ~PCI_COMMAND_IO;
| PCI_COMMAND_IO;
data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_IO;
if ((command_bits & PCI_COMMAND_IO) == 0)
cmdreg|PCI_COMMAND_IO);
if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
disabled = !(command & PCI_COMMAND_IO);
PCI_COMMAND_IO |
PCI_COMMAND_IO |
if (!(command & PCI_COMMAND_IO))
PCI_COMMAND_PARITY | PCI_COMMAND_IO |
if (!(pci_command & PCI_COMMAND_IO)) {
vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
} while ((PCI_COMMAND_IO) & cmd);
} while ((PCI_COMMAND_IO) & cmd);
} while ((PCI_COMMAND_IO) & cmd);
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
#define ALX_PCI_CMD (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
PCI_COMMAND_IO);
cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
if (cmd & PCI_COMMAND_IO)
cmd &= ~PCI_COMMAND_IO;
word |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_IO;
value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
val |= PCI_COMMAND_IO;
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;
bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
cmd &= ~PCI_COMMAND_IO;
if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
cmd |= PCI_COMMAND_IO;
pci_bits |= PCI_COMMAND_IO;
if (pci_bits & PCI_COMMAND_IO)
pci_bits |= PCI_COMMAND_IO;
if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
if (boot_cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
if (cmd & PCI_COMMAND_IO)
PCI_COMMAND_IO |
} else if (cmd_reg & PCI_COMMAND_IO) {
#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
phys_io = !!(phys_cmd & PCI_COMMAND_IO);
virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
new_io = !!(new_cmd & PCI_COMMAND_IO);
u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
if ((le16_to_cpu(virtvdev->pci_cmd) & PCI_COMMAND_IO) &&
val16 |= cpu_to_le16(PCI_COMMAND_IO);
if (!(le16_to_cpu(virtvdev->pci_cmd) & PCI_COMMAND_IO))
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
return (flags & PCI_COMMAND_IO);
PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
if ((cmdw & PCI_COMMAND_IO) != PCI_COMMAND_IO) {
cmdw |= PCI_COMMAND_IO;
pci_write_config_word(pci, PCI_COMMAND, word | PCI_COMMAND_IO);