PCI_BASE_ADDRESS_0
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
regbase = ioremap(readq(base + PCI_BASE_ADDRESS_0) & ~0xffull, SZ_64K);
ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0);
if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz);
grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr);
grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
pcic->pcic_regs+PCI_BASE_ADDRESS_0);
addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
bar0 = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_0 + 1:
case PCI_BASE_ADDRESS_0 + 2:
case PCI_BASE_ADDRESS_0 + 3:
PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
((reg & ~3) == PCI_BASE_ADDRESS_0))
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
(where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0;
bar0 = readl(addr + PCI_BASE_ADDRESS_0);
ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
[PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos,
if (index != PCI_BASE_ADDRESS_0)
intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += PCI_REG_STRIDE, i++)
pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, ddata->bmc_pci_data.base_address0);
for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += PCI_REG_STRIDE, i++)
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &ddata->bmc_pci_data.base_address0);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &cfg);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ~0);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &size);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, cfg);
for (off = PCI_BASE_ADDRESS_0;
pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_0, &data32);
return t4_get_window(adap, PCI_BASE_ADDRESS_0,
pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, bar0);
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);
pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0,
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);
P54U_WRITE(NET2280_BRG_CFG_U32, PCI_BASE_ADDRESS_0,
P54U_WRITE(NET2280_DEV_CFG_U32, 0x10000 | PCI_BASE_ADDRESS_0,
if (((bar_no >= 0) && ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0))) ||
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags);
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
reg = PCI_BASE_ADDRESS_0 + (4 * bar);
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
PCI_BASE_ADDRESS_0 + (4 * i),
PCI_BASE_ADDRESS_0 + (4 * i),
PCI_BASE_ADDRESS_0 + (4 * i),
PCI_BASE_ADDRESS_0,
iowrite32(val, reg + PCI_BASE_ADDRESS_0);
writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_0);
if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
(offset == PCI_BASE_ADDRESS_0))
PCI_BASE_ADDRESS_0);
writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0);
(offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0,
[PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
__pci_size_stdbars(dev, howmany, PCI_BASE_ADDRESS_0, stdbars);
reg = PCI_BASE_ADDRESS_0 + (pos << 2);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
reg = PCI_BASE_ADDRESS_0 + 4 * resno;
config_writel(socket, PCI_BASE_ADDRESS_0, region.start);
if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low);
gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
if (bar != PCI_BASE_ADDRESS_0) {
bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, ~0);
sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, val);
val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, ~0);
sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, val);
vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
if (vfio_pci_core_range_intersect_range(pos, count, PCI_BASE_ADDRESS_0,
if (vfio_pci_core_range_intersect_range(pos, count, PCI_BASE_ADDRESS_0,
int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
minfo->devflags.fbResource = PCI_BASE_ADDRESS_0;
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
(offs < PCI_BASE_ADDRESS_0 ||
newhpa = pci_resource_start (sti->pd, (offs - PCI_BASE_ADDRESS_0) / 4);
unsigned int pos = (offset - PCI_BASE_ADDRESS_0) / 4;
pos = (offset - PCI_BASE_ADDRESS_0) / 4;
CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
STORE_LE32((u32 *) &mdev_state->vconfig[PCI_BASE_ADDRESS_0],
int index = (offset - PCI_BASE_ADDRESS_0) / 0x04;
case PCI_BASE_ADDRESS_0:
STORE_LE32((u32 *) &mdev_state->vconfig[PCI_BASE_ADDRESS_0],
case PCI_BASE_ADDRESS_0:
pos = PCI_BASE_ADDRESS_0;
pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);