arch/alpha/include/asm/cache.h

21

#define SMP_CACHE_BYTES L1_CACHE_BYTES

arch/arc/include/asm/cache.h

17

#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))

arch/arc/mm/cache.c

1003

if (ic->line_len != L1_CACHE_BYTES)

arch/arc/mm/cache.c

1005

ic->line_len, L1_CACHE_BYTES);

arch/arc/mm/cache.c

1023

if (dc->line_len != L1_CACHE_BYTES)

arch/arc/mm/cache.c

1025

dc->line_len, L1_CACHE_BYTES);

arch/arc/mm/cache.c

1037

BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES,

arch/arc/mm/cache.c

213

num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);

arch/arc/mm/cache.c

235

paddr += L1_CACHE_BYTES;

arch/arc/mm/cache.c

239

vaddr += L1_CACHE_BYTES;

arch/arc/mm/cache.c

272

num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);

arch/arc/mm/cache.c

292

paddr += L1_CACHE_BYTES;

arch/arc/mm/cache.c

325

sz += L1_CACHE_BYTES - 1;

arch/arm/common/bL_switcher.c

127

stack = PTR_ALIGN(stack, L1_CACHE_BYTES);

arch/arm/include/asm/cache.h

18

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/arm/include/asm/module.h

12

#define PLT_ENT_STRIDE L1_CACHE_BYTES

arch/arm/kernel/bios32.c

325

L1_CACHE_BYTES >> 2);

arch/arm/kernel/module-plts.c

264

mod->arch.core.plt->sh_addralign = L1_CACHE_BYTES;

arch/arm/kernel/module-plts.c

272

mod->arch.init.plt->sh_addralign = L1_CACHE_BYTES;

arch/arm64/kernel/module-plts.c

349

pltsec->sh_addralign = L1_CACHE_BYTES;

arch/arm64/kernel/module-plts.c

357

pltsec->sh_addralign = L1_CACHE_BYTES;

arch/csky/include/asm/cache.h

11

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/csky/mm/cachev1.c

67

i = start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev1.c

68

for (; i < end; i += L1_CACHE_BYTES) {

arch/csky/mm/cachev2.c

106

unsigned long i = start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev2.c

108

for (; i < end; i += L1_CACHE_BYTES)

arch/csky/mm/cachev2.c

115

unsigned long i = start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev2.c

117

for (; i < end; i += L1_CACHE_BYTES)

arch/csky/mm/cachev2.c

26

unsigned long i = start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev2.c

28

for (; i < end; i += L1_CACHE_BYTES)

arch/csky/mm/cachev2.c

49

unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev2.c

54

for (; i < param->end; i += L1_CACHE_BYTES)

arch/csky/mm/cachev2.c

81

unsigned long i = start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev2.c

83

for (; i < end; i += L1_CACHE_BYTES)

arch/csky/mm/cachev2.c

97

unsigned long i = start & ~(L1_CACHE_BYTES - 1);

arch/csky/mm/cachev2.c

99

for (; i < end; i += L1_CACHE_BYTES)

arch/hexagon/include/asm/cache.h

15

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/hexagon/include/asm/cache.h

17

#define __cacheline_aligned __aligned(L1_CACHE_BYTES)

arch/hexagon/include/asm/cache.h

18

#define ____cacheline_aligned __aligned(L1_CACHE_BYTES)

arch/loongarch/kernel/module-sections.c

157

got_sec->sh_addralign = L1_CACHE_BYTES;

arch/loongarch/kernel/module-sections.c

165

plt_sec->sh_addralign = L1_CACHE_BYTES;

arch/loongarch/kernel/module-sections.c

173

plt_idx_sec->sh_addralign = L1_CACHE_BYTES;

arch/m68k/include/asm/cache.h

12

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/microblaze/include/asm/cache.h

19

#define SMP_CACHE_BYTES L1_CACHE_BYTES

arch/microblaze/include/asm/cache.h

22

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/microblaze/include/asm/cache.h

24

#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES

arch/mips/include/asm/mach-n64/kmalloc.h

6

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/mips/include/asm/mach-tx49xx/kmalloc.h

5

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/nios2/include/asm/cache.h

21

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/openrisc/include/asm/cacheflush.h

52

local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)

arch/openrisc/include/asm/cacheflush.h

54

local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)

arch/openrisc/include/asm/cacheflush.h

56

local_icache_range_inv(addr, addr + L1_CACHE_BYTES)

arch/openrisc/mm/cache.c

39

paddr += L1_CACHE_BYTES;

arch/openrisc/mm/cache.c

49

paddr &= ~(L1_CACHE_BYTES - 1);

arch/parisc/include/asm/atomic.h

30

# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))

arch/parisc/include/asm/cache.h

21

#define SMP_CACHE_BYTES L1_CACHE_BYTES

arch/powerpc/include/asm/cache.h

32

#define SMP_CACHE_BYTES L1_CACHE_BYTES

arch/powerpc/include/asm/cache.h

37

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/powerpc/include/asm/cache.h

89

return L1_CACHE_BYTES;

arch/powerpc/include/asm/cache.h

99

return L1_CACHE_BYTES;

arch/powerpc/include/asm/page_32.h

44

WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1));

arch/powerpc/include/asm/page_32.h

46

for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)

arch/powerpc/kernel/misc_32.S

199

#if L1_CACHE_BYTES >= 32

arch/powerpc/kernel/misc_32.S

201

#if L1_CACHE_BYTES >= 64

arch/powerpc/kernel/misc_32.S

204

#if L1_CACHE_BYTES >= 128

arch/powerpc/kernel/paca.c

163

s = alloc_paca_data(sizeof(*s), L1_CACHE_BYTES, limit, cpu);

arch/powerpc/kernel/paca.c

273

paca = alloc_paca_data(sizeof(struct paca_struct), L1_CACHE_BYTES,

arch/powerpc/kvm/book3s_hv.c

534

if (addr & (L1_CACHE_BYTES - 1))

arch/powerpc/kvm/book3s_hv.c

582

if ((vpa & (L1_CACHE_BYTES - 1)) || !vpa)

arch/powerpc/kvm/book3s_hv_rm_mmu.c

945

for (i = 0; i < SZ_4K; i += L1_CACHE_BYTES, pa += L1_CACHE_BYTES)

arch/powerpc/lib/checksum_32.S

195

#if L1_CACHE_BYTES >= 32

arch/powerpc/lib/checksum_32.S

197

#if L1_CACHE_BYTES >= 64

arch/powerpc/lib/checksum_32.S

200

#if L1_CACHE_BYTES >= 128

arch/powerpc/lib/checksum_32.S

255

#if L1_CACHE_BYTES >= 32

arch/powerpc/lib/checksum_32.S

257

#if L1_CACHE_BYTES >= 64

arch/powerpc/lib/checksum_32.S

260

#if L1_CACHE_BYTES >= 128

arch/powerpc/lib/copy_32.S

211

#if L1_CACHE_BYTES >= 32

arch/powerpc/lib/copy_32.S

213

#if L1_CACHE_BYTES >= 64

arch/powerpc/lib/copy_32.S

216

#if L1_CACHE_BYTES >= 128

arch/powerpc/lib/copy_32.S

390

#if L1_CACHE_BYTES >= 32

arch/powerpc/lib/copy_32.S

392

#if L1_CACHE_BYTES >= 64

arch/powerpc/lib/copy_32.S

395

#if L1_CACHE_BYTES >= 128

arch/powerpc/lib/copy_32.S

448

#if L1_CACHE_BYTES >= 32

arch/powerpc/lib/copy_32.S

450

#if L1_CACHE_BYTES >= 64

arch/powerpc/lib/copy_32.S

453

#if L1_CACHE_BYTES >= 128

arch/powerpc/mm/dma-noncoherent.c

35

if ((start | end) & (L1_CACHE_BYTES - 1))

arch/powerpc/platforms/powermac/pci.c

1013

L1_CACHE_BYTES >> 2);

arch/powerpc/platforms/pseries/papr_scm.c

1301

u64 aligned_addr = ALIGN_DOWN(phys_addr, L1_CACHE_BYTES);

arch/powerpc/platforms/pseries/papr_scm.c

1303

if (nvdimm_bus_add_badrange(bus, aligned_addr, L1_CACHE_BYTES)) {

arch/powerpc/platforms/pseries/papr_scm.c

1309

aligned_addr, aligned_addr + L1_CACHE_BYTES);

arch/powerpc/xmon/xmon.c

1933

nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;

arch/powerpc/xmon/xmon.c

1939

for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)

arch/powerpc/xmon/xmon.c

1942

for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)

arch/riscv/errata/thead/errata.c

122

riscv_cbom_block_size = L1_CACHE_BYTES;

arch/riscv/include/asm/cache.h

15

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/riscv/include/asm/set_memory.h

57

#define SECTION_ALIGN L1_CACHE_BYTES

arch/riscv/kernel/module-sections.c

194

mod->arch.plt.shdr->sh_addralign = L1_CACHE_BYTES;

arch/riscv/kernel/module-sections.c

201

mod->arch.got.shdr->sh_addralign = L1_CACHE_BYTES;

arch/riscv/kernel/module-sections.c

208

mod->arch.got_plt.shdr->sh_addralign = L1_CACHE_BYTES;

arch/sh/include/asm/cache.h

21

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

arch/sh/include/asm/processor.h

87

} __attribute__ ((aligned(L1_CACHE_BYTES)));

arch/sh/include/asm/processor_32.h

188

#define PREFETCH_STRIDE L1_CACHE_BYTES

arch/sh/kernel/cpu/sh2/probe.c

38

boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;

arch/sh/kernel/cpu/sh2a/probe.c

47

boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;

arch/sh/kernel/cpu/sh3/probe.c

52

boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;

arch/sh/kernel/cpu/sh4/probe.c

245

boot_cpu_data.scache.linesz = L1_CACHE_BYTES;

arch/sh/kernel/cpu/sh4/probe.c

39

boot_cpu_data.icache.linesz = L1_CACHE_BYTES;

arch/sh/kernel/cpu/sh4/probe.c

48

boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;

arch/sh/mm/cache-sh2.c

23

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2.c

24

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh2.c

25

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2.c

26

for (v = begin; v < end; v+=L1_CACHE_BYTES) {

arch/sh/mm/cache-sh2.c

44

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2.c

45

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh2.c

46

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2.c

48

for (v = begin; v < end; v+=L1_CACHE_BYTES)

arch/sh/mm/cache-sh2.c

75

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2.c

76

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh2.c

77

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2.c

79

for (v = begin; v < end; v+=L1_CACHE_BYTES)

arch/sh/mm/cache-sh2a.c

104

for (v = begin; v < end; v+=L1_CACHE_BYTES) {

arch/sh/mm/cache-sh2a.c

127

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

128

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh2a.c

129

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

139

for (v = begin; v < end; v += L1_CACHE_BYTES)

arch/sh/mm/cache-sh2a.c

157

start = data->addr1 & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

158

end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

173

for (v = start; v < end; v += L1_CACHE_BYTES)

arch/sh/mm/cache-sh2a.c

57

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

58

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh2a.c

59

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

70

for (v = begin; v < end; v += L1_CACHE_BYTES) {

arch/sh/mm/cache-sh2a.c

78

for (v = begin; v < end; v += L1_CACHE_BYTES)

arch/sh/mm/cache-sh2a.c

97

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh2a.c

98

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh2a.c

99

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh3.c

38

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh3.c

39

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh3.c

40

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh3.c

42

for (v = begin; v < end; v+=L1_CACHE_BYTES) {

arch/sh/mm/cache-sh3.c

76

begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh3.c

77

end = ((unsigned long)start + size + L1_CACHE_BYTES-1)

arch/sh/mm/cache-sh3.c

78

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh3.c

80

for (v = begin; v < end; v+=L1_CACHE_BYTES) {

arch/sh/mm/cache-sh4.c

60

start &= ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh4.c

61

end += L1_CACHE_BYTES-1;

arch/sh/mm/cache-sh4.c

62

end &= ~(L1_CACHE_BYTES-1);

arch/sh/mm/cache-sh4.c

67

for (v = start; v < end; v += L1_CACHE_BYTES) {

arch/sh/mm/flush-sh4.c

101

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

19

v = aligned_start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/flush-sh4.c

20

end = (aligned_start + size + L1_CACHE_BYTES-1)

arch/sh/mm/flush-sh4.c

21

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/flush-sh4.c

22

cnt = (end - v) / L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

25

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

26

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

27

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

28

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

29

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

30

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

31

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

32

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

37

__ocbwb(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

53

v = aligned_start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/flush-sh4.c

54

end = (aligned_start + size + L1_CACHE_BYTES-1)

arch/sh/mm/flush-sh4.c

55

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/flush-sh4.c

56

cnt = (end - v) / L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

59

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

60

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

61

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

62

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

63

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

64

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

65

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

66

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

70

__ocbp(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

83

v = aligned_start & ~(L1_CACHE_BYTES-1);

arch/sh/mm/flush-sh4.c

84

end = (aligned_start + size + L1_CACHE_BYTES-1)

arch/sh/mm/flush-sh4.c

85

& ~(L1_CACHE_BYTES-1);

arch/sh/mm/flush-sh4.c

86

cnt = (end - v) / L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

89

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

90

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

91

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

92

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

93

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

94

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

95

__ocbi(v); v += L1_CACHE_BYTES;

arch/sh/mm/flush-sh4.c

96

__ocbi(v); v += L1_CACHE_BYTES;

arch/um/kernel/um_arch.c

288

boot_cpu_data.cache_alignment = L1_CACHE_BYTES;

arch/um/kernel/um_arch.c

61

.cache_alignment = L1_CACHE_BYTES,

arch/x86/kernel/apic/x2apic_cluster.c

211

slots = max_t(u32, L1_CACHE_BYTES/sizeof(u32), nr_cpu_ids);

arch/x86/platform/uv/uv_time.c

283

offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;

arch/xtensa/include/asm/cache.h

18

#define SMP_CACHE_BYTES L1_CACHE_BYTES

arch/xtensa/include/asm/cache.h

32

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

drivers/ata/pata_hpt366.c

344

pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));

drivers/ata/pata_hpt37x.c

891

pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));

drivers/ata/pata_hpt3x2n.c

538

pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));

drivers/char/uv_mmtimer.c

101

ret = ((uv_blade_processor_id() * L1_CACHE_BYTES) %

drivers/hid/intel-ish-hid/ishtp-fw-loader.c

533

(fw_info->ldr_capability.max_dma_buf_size % L1_CACHE_BYTES)) {

drivers/hid/intel-ish-hid/ishtp-fw-loader.c

662

payload_max_size &= ~(L1_CACHE_BYTES - 1);

drivers/hsi/clients/cmt_speech.c

891

hi->slot_size, hi->buf_size, L1_CACHE_BYTES);

drivers/hsi/clients/cmt_speech.c

896

data_start, sizeof(*hi->mmap_cfg), L1_CACHE_BYTES);

drivers/infiniband/hw/hfi1/sdma.c

1444

dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;

drivers/infiniband/hw/hfi1/sdma.c

1471

curr_head += L1_CACHE_BYTES;

drivers/infiniband/hw/hfi1/user_sdma.c

150

L1_CACHE_BYTES,

drivers/md/dm-table.c

30

#define NODE_SIZE L1_CACHE_BYTES

drivers/md/dm-vdo/cpu.h

50

unsigned int offset = ((uintptr_t) address % L1_CACHE_BYTES);

drivers/md/dm-vdo/cpu.h

51

unsigned int cache_lines = (1 + ((size + offset) / L1_CACHE_BYTES));

drivers/md/dm-vdo/cpu.h

55

address += L1_CACHE_BYTES;

drivers/md/dm-vdo/funnel-queue.h

56

struct __aligned(L1_CACHE_BYTES) funnel_queue {

drivers/md/dm-vdo/funnel-queue.h

64

struct funnel_queue_entry *oldest __aligned(L1_CACHE_BYTES);

drivers/md/dm-vdo/indexer/delta-index.h

78

} __aligned(L1_CACHE_BYTES);

drivers/md/dm-vdo/indexer/index-session.h

27

struct __aligned(L1_CACHE_BYTES) session_stats {

drivers/md/dm-vdo/indexer/sparse-cache.c

89

struct __aligned(L1_CACHE_BYTES) cached_index_counters {

drivers/md/dm-vdo/indexer/sparse-cache.c

93

struct __aligned(L1_CACHE_BYTES) cached_chapter_index {

drivers/md/dm-vdo/indexer/volume-index.h

55

} __aligned(L1_CACHE_BYTES);

drivers/md/dm-vdo/indexer/volume-index.h

91

} __aligned(L1_CACHE_BYTES);

drivers/md/dm-vdo/indexer/volume.h

48

struct __aligned(L1_CACHE_BYTES) search_pending_counter {

drivers/md/dm-vdo/memory-alloc.h

112

return vdo_allocate_memory(size, L1_CACHE_BYTES, what, ptr);

drivers/media/platform/renesas/rcar_jpu.c

47

#define JPU_JPEG_HDR_SIZE (ALIGN(0x258, L1_CACHE_BYTES))

drivers/misc/sgi-xp/xpc_main.c

379

*base = kzalloc(size + L1_CACHE_BYTES, flags);

drivers/misc/sgi-xp/xpc_partition.c

55

*base = kmalloc(size + L1_CACHE_BYTES, flags);

drivers/misc/sgi-xp/xpnet.c

121

#define XPNET_MAX_MTU (0x800000UL - L1_CACHE_BYTES)

drivers/misc/sgi-xp/xpnet.c

170

skb = dev_alloc_skb(msg->size + L1_CACHE_BYTES);

drivers/misc/sgi-xp/xpnet.c

173

msg->size + L1_CACHE_BYTES);

drivers/misc/sgi-xp/xpnet.c

187

skb_reserve(skb, (L1_CACHE_BYTES - ((u64)skb->data &

drivers/misc/sgi-xp/xpnet.c

188

(L1_CACHE_BYTES - 1)) +

drivers/misc/sgi-xp/xpnet.c

209

dst = (void *)((u64)skb->data & ~(L1_CACHE_BYTES - 1));

drivers/misc/sgi-xp/xpnet.c

445

start_addr = ((u64)skb->data & ~(L1_CACHE_BYTES - 1));

drivers/net/ethernet/atheros/ag71xx.c

302

L1_CACHE_BYTES)

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

4282

t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);

drivers/net/ethernet/hisilicon/hns/hns_enet.c

451

truesize = ALIGN(size, L1_CACHE_BYTES);

drivers/net/ethernet/ibm/ibmvnic.c

1117

rx_pool->buff_size = ALIGN(buff_size, L1_CACHE_BYTES);

drivers/net/ethernet/ibm/ibmvnic.c

1356

buff_size = ALIGN(buff_size, L1_CACHE_BYTES);

drivers/net/ethernet/intel/idpf/idpf_txrx.c

3464

u32 copy = data_len <= L1_CACHE_BYTES ? data_len : ETH_HLEN;

drivers/net/ethernet/intel/idpf/idpf_txrx.h

215

#define IDPF_TX_DESCS_PER_CACHE_LINE (L1_CACHE_BYTES / \

drivers/net/ethernet/mellanox/mlx5/core/en.h

216

#if L1_CACHE_BYTES >= 128

drivers/net/ethernet/meta/fbnic/fbnic_mac.c

60

cls = ilog2(L1_CACHE_BYTES) - 6;

drivers/net/ethernet/qlogic/qed/qed_dev.c

2598

cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);

drivers/net/ethernet/qlogic/qed/qed_dev.c

2618

if (wr_mbs < L1_CACHE_BYTES)

drivers/net/ethernet/qlogic/qed/qed_dev.c

2621

L1_CACHE_BYTES, wr_mbs);

drivers/net/ethernet/qlogic/qed/qed_ll2.c

2595

L1_CACHE_BYTES + params->mtu;

drivers/net/ethernet/sfc/efx_common.c

381

BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);

drivers/net/ethernet/sfc/falcon/efx.c

609

BUILD_BUG_ON(EF4_RX_USR_BUF_SIZE % L1_CACHE_BYTES);

drivers/net/ethernet/sfc/falcon/net_driver.h

89

#define EF4_RX_BUF_ALIGNMENT L1_CACHE_BYTES

drivers/net/ethernet/sfc/net_driver.h

93

#define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES

drivers/net/ethernet/sfc/siena/efx_common.c

385

BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);

drivers/net/ethernet/sfc/siena/net_driver.h

93

#define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES

drivers/net/ethernet/sfc/tx.c

122

u8 buf[L1_CACHE_BYTES];

drivers/net/ethernet/sfc/tx.c

240

BUILD_BUG_ON(L1_CACHE_BYTES >

drivers/net/ethernet/sfc/tx.c

243

ALIGN(skb->len, L1_CACHE_BYTES) >> 3);

drivers/net/ethernet/sfc/tx.c

29

#define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)

drivers/net/ethernet/wangxun/libwx/wx_lib.c

232

unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);

drivers/net/virtio_net.c

2759

return ALIGN(len, L1_CACHE_BYTES);

drivers/net/wireless/ath/ath5k/ahb.c

32

*csz = L1_CACHE_BYTES >> 2;

drivers/net/wireless/ath/ath5k/pci.c

215

csz = L1_CACHE_BYTES >> 2;

drivers/net/wireless/ath/ath5k/pci.c

72

*csz = L1_CACHE_BYTES >> 2; /* Use the default size */

drivers/net/wireless/ath/ath6kl/init.c

225

reserved = roundup((2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +

drivers/net/wireless/ath/ath6kl/init.c

230

skb_reserve(skb, reserved - L1_CACHE_BYTES);

drivers/net/wireless/ath/ath6kl/sdio.c

359

size = 2 * L1_CACHE_BYTES +

drivers/net/wireless/ath/ath9k/ahb.c

40

*csz = L1_CACHE_BYTES >> 2;

drivers/net/wireless/ath/ath9k/htc_drv_init.c

516

*csz = L1_CACHE_BYTES >> 2;

drivers/net/wireless/ath/ath9k/pci.c

916

csz = L1_CACHE_BYTES / sizeof(u32);

drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h

143

u8 dummy1[L1_CACHE_BYTES];

drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.h

152

u8 dummy2[L1_CACHE_BYTES];

drivers/nvdimm/btt.c

1087

u32 idx = (premap * MAP_ENT_SIZE / L1_CACHE_BYTES) % arena->nfree;

drivers/nvdimm/btt.c

1095

u32 idx = (premap * MAP_ENT_SIZE / L1_CACHE_BYTES) % arena->nfree;

drivers/nvdimm/btt.h

127

u8 cacheline_padding[L1_CACHE_BYTES];

drivers/parisc/ccio-dma.c

753

if ((size % L1_CACHE_BYTES) || (addr % L1_CACHE_BYTES))

drivers/parisc/dino.c

573

PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);

drivers/parisc/sba_iommu.c

1733

&(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);

drivers/pci/pci.c

141

u8 pci_dfl_cache_line_size __ro_after_init = L1_CACHE_BYTES >> 2;

drivers/pcmcia/yenta_socket.c

1061

config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4);

drivers/s390/virtio/virtio_ccw.c

173

#define VIRTIO_IV_BITS (L1_CACHE_BYTES * 8)

drivers/scsi/csiostor/csio_wr.c

1312

uint32_t clsz = L1_CACHE_BYTES;

drivers/soc/fsl/qbman/dpaa_sys.h

71

#if (L1_CACHE_BYTES == 32)

drivers/soc/fsl/qbman/qman_test_stash.c

376

u8 res = (offset + (L1_CACHE_BYTES - 1))

drivers/soc/fsl/qbman/qman_test_stash.c

377

/ (L1_CACHE_BYTES);

drivers/soc/fsl/qbman/qman_test_stash.c

572

sizeof(struct hp_handler), L1_CACHE_BYTES,

drivers/tty/hvc/hvc_console.c

52

#define __ALIGNED__ __attribute__((__aligned__(L1_CACHE_BYTES)))

fs/dcache.c

129

hash += (unsigned long) parent / L1_CACHE_BYTES;

fs/file.c

225

2 * nr / BITS_PER_BYTE + BITBIT_SIZE(nr), L1_CACHE_BYTES),

fs/inode.c

680

L1_CACHE_BYTES;

fs/namespace.c

200

unsigned long tmp = ((unsigned long)mnt / L1_CACHE_BYTES);

fs/namespace.c

201

tmp += ((unsigned long)dentry / L1_CACHE_BYTES);

fs/namespace.c

208

unsigned long tmp = ((unsigned long)dentry / L1_CACHE_BYTES);

fs/smb/server/vfs_cache.c

164

L1_CACHE_BYTES;

include/linux/cache.h

10

#define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)

include/linux/cache.h

104

#define cache_line_size() L1_CACHE_BYTES

include/linux/netdevice.h

2637

#if L1_CACHE_BYTES < 128

include/linux/netdevice.h

2638

prefetch((u8 *)p + L1_CACHE_BYTES);

include/linux/netdevice.h

2645

#if L1_CACHE_BYTES < 128

include/linux/netdevice.h

2646

prefetchw((u8 *)p + L1_CACHE_BYTES);

include/linux/prefetch.h

47

#define PREFETCH_STRIDE (4*L1_CACHE_BYTES)

include/linux/skbuff.h

3303

#define NET_SKB_PAD max(32, L1_CACHE_BYTES)

include/vdso/cache.h

8

#define SMP_CACHE_BYTES L1_CACHE_BYTES

init/init_task.c

96

struct task_struct init_task __aligned(L1_CACHE_BYTES) = {

io_uring/query.c

41

e->rq_hdr_alignment = L1_CACHE_BYTES;

io_uring/zcrx.c

372

offsets->rqes = ALIGN(sizeof(struct io_uring), L1_CACHE_BYTES);

kernel/audit_tree.c

223

unsigned long n = key / L1_CACHE_BYTES;

kernel/fork.c

855

int align = max_t(int, L1_CACHE_BYTES, ARCH_MIN_TASKALIGN);

lib/atomic64.c

29

char pad[L1_CACHE_BYTES];

lib/btree.c

46

#define NODESIZE MAX(L1_CACHE_BYTES, 128)

lib/crypto/aes.c

189

for (size_t i = 0; i < len; i += L1_CACHE_BYTES)

mm/shmem.c

5015

L1_CACHE_BYTES), GFP_KERNEL);

net/core/dev.c

2889

if (maps_sz < L1_CACHE_BYTES)

net/core/dev.c

2890

maps_sz = L1_CACHE_BYTES;

net/core/dev_addr_lists.c

58

if (alloc_size < L1_CACHE_BYTES)

net/core/dev_addr_lists.c

59

alloc_size = L1_CACHE_BYTES;

net/core/net-sysfs.c

989

RPS_MAP_SIZE(cpumask_weight(mask)), L1_CACHE_BYTES),

net/core/skbuff.c

115

(SKB_SMALL_HEAD_SIZE + L1_CACHE_BYTES) : \

net/core/skbuff.c

3837

skb_headlen(from) < L1_CACHE_BYTES ||

net/ipv4/esp4.c

422

if (ALIGN(tailen, L1_CACHE_BYTES) > PAGE_SIZE ||

net/ipv4/esp4.c

423

ALIGN(skb->data_len, L1_CACHE_BYTES) > PAGE_SIZE)

net/ipv4/esp4.c

441

allocsize = ALIGN(tailen, L1_CACHE_BYTES);

net/ipv4/esp4.c

551

allocsize = ALIGN(skb->data_len, L1_CACHE_BYTES);

net/ipv4/fib_frontend.c

1576

size = max_t(size_t, size, L1_CACHE_BYTES);

net/ipv4/inet_hashtables.c

1309

nblocks = max(2U * L1_CACHE_BYTES / locksz, 1U) * num_possible_cpus();

net/ipv6/esp6.c

451

if (ALIGN(tailen, L1_CACHE_BYTES) > PAGE_SIZE ||

net/ipv6/esp6.c

452

ALIGN(skb->data_len, L1_CACHE_BYTES) > PAGE_SIZE)

net/ipv6/esp6.c

470

allocsize = ALIGN(tailen, L1_CACHE_BYTES);

net/ipv6/esp6.c

582

allocsize = ALIGN(skb->data_len, L1_CACHE_BYTES);

net/ipv6/ip6_fib.c

2491

size = max_t(size_t, size, L1_CACHE_BYTES);

net/packet/internal.h

100

#define ROLLOVER_HLEN (L1_CACHE_BYTES / sizeof(u32))

net/rxrpc/txbuf.c

36

data_align = umax(data_align, L1_CACHE_BYTES);

net/xfrm/xfrm_iptfs.c

94

#define XFRM_IPTFS_MIN_L2HEADROOM (L1_CACHE_BYTES > 64 ? 64 : 64 + 16)

tools/include/linux/cache.h

8

#define SMP_CACHE_BYTES L1_CACHE_BYTES