arch/x86/events/amd/brs.c

190

wrmsrq(brs_to(0), BRS_POISON);

arch/x86/events/amd/brs.c

374

wrmsrq(brs_to(idx), BRS_POISON);

arch/x86/events/amd/core.c

568

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);

arch/x86/events/amd/core.c

574

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,

arch/x86/events/amd/core.c

656

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl);

arch/x86/events/amd/core.c

677

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status);

arch/x86/events/amd/ibs.c

439

wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask);

arch/x86/events/amd/ibs.c

441

wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask);

arch/x86/events/amd/ibs.c

456

wrmsrq(hwc->config_base, config);

arch/x86/events/amd/ibs.c

458

wrmsrq(hwc->config_base, config);

arch/x86/events/amd/lbr.c

337

wrmsrq(MSR_AMD64_LBR_SELECT, 0);

arch/x86/events/amd/lbr.c

400

wrmsrq(MSR_AMD64_LBR_SELECT, lbr_select);

arch/x86/events/amd/lbr.c

405

wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);

arch/x86/events/amd/lbr.c

409

wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);

arch/x86/events/amd/lbr.c

65

wrmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2, val);

arch/x86/events/amd/lbr.c

70

wrmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val);

arch/x86/events/amd/uncore.c

173

wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count));

arch/x86/events/amd/uncore.c

177

wrmsrq(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE));

arch/x86/events/amd/uncore.c

187

wrmsrq(hwc->config_base, hwc->config);

arch/x86/events/amd/uncore.c

948

wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count));

arch/x86/events/amd/uncore.c

952

wrmsrq(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC));

arch/x86/events/core.c

1449

wrmsrq(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);

arch/x86/events/core.c

1456

wrmsrq(x86_pmu_event_addr(idx + 1), 0xffff);

arch/x86/events/core.c

2563

wrmsrq(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0);

arch/x86/events/core.c

2565

wrmsrq(x86_pmu_event_addr(i), 0);

arch/x86/events/core.c

720

wrmsrq(x86_pmu_config_addr(idx), val);

arch/x86/events/core.c

722

wrmsrq(x86_pmu_config_addr(idx + 1), 0);

arch/x86/events/intel/core.c

2512

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);

arch/x86/events/intel/core.c

2533

wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);

arch/x86/events/intel/core.c

2537

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL,

arch/x86/events/intel/core.c

2653

wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);

arch/x86/events/intel/core.c

2654

wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);

arch/x86/events/intel/core.c

2657

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);

arch/x86/events/intel/core.c

2658

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);

arch/x86/events/intel/core.c

2668

wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);

arch/x86/events/intel/core.c

2685

wrmsrq(MSR_TSX_FORCE_ABORT, val);

arch/x86/events/intel/core.c

2723

wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);

arch/x86/events/intel/core.c

2791

wrmsrq(msr, ext);

arch/x86/events/intel/core.c

2890

wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);

arch/x86/events/intel/core.c

2891

wrmsrq(MSR_PERF_METRICS, 0);

arch/x86/events/intel/core.c

2897

wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);

arch/x86/events/intel/core.c

2898

wrmsrq(MSR_PERF_METRICS, hwc->saved_metric);

arch/x86/events/intel/core.c

3044

wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);

arch/x86/events/intel/core.c

3045

wrmsrq(MSR_PERF_METRICS, 0);

arch/x86/events/intel/core.c

3256

wrmsrq(MSR_IA32_PEBS_INDEX, new.whole);

arch/x86/events/intel/core.c

3395

wrmsrq(event->hw.event_base, 0);

arch/x86/events/intel/core.c

3449

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);

arch/x86/events/intel/core.c

3558

wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);

arch/x86/events/intel/core.c

6544

wrmsrq(msr, val_old);

arch/x86/events/intel/ds.c

1866

wrmsrq(base + idx, value);

arch/x86/events/intel/ds.c

1910

wrmsrq(MSR_PEBS_DATA_CFG, pebs_data_cfg);

arch/x86/events/intel/ds.c

1981

wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);

arch/x86/events/intel/ds.c

1989

wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);

arch/x86/events/intel/ds.c

3256

wrmsrq(MSR_IA32_PEBS_INDEX, index.whole);

arch/x86/events/intel/ds.c

3452

wrmsrq(MSR_IA32_DS_AREA, (unsigned long)ds);

arch/x86/events/intel/knc.c

165

wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);

arch/x86/events/intel/knc.c

174

wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);

arch/x86/events/intel/knc.c

211

wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack);

arch/x86/events/intel/lbr.c

141

wrmsrq(MSR_LBR_SELECT, lbr_select);

arch/x86/events/intel/lbr.c

159

wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);

arch/x86/events/intel/lbr.c

162

wrmsrq(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN);

arch/x86/events/intel/lbr.c

170

wrmsrq(x86_pmu.lbr_from + i, 0);

arch/x86/events/intel/lbr.c

178

wrmsrq(x86_pmu.lbr_from + i, 0);

arch/x86/events/intel/lbr.c

179

wrmsrq(x86_pmu.lbr_to + i, 0);

arch/x86/events/intel/lbr.c

181

wrmsrq(x86_pmu.lbr_info + i, 0);

arch/x86/events/intel/lbr.c

188

wrmsrq(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr);

arch/x86/events/intel/lbr.c

203

wrmsrq(MSR_LBR_SELECT, 0);

arch/x86/events/intel/lbr.c

286

wrmsrq(x86_pmu.lbr_from + idx, val);

arch/x86/events/intel/lbr.c

291

wrmsrq(x86_pmu.lbr_to + idx, val);

arch/x86/events/intel/lbr.c

296

wrmsrq(x86_pmu.lbr_info + idx, val);

arch/x86/events/intel/lbr.c

384

wrmsrq(x86_pmu.lbr_tos, tos);

arch/x86/events/intel/lbr.c

387

wrmsrq(MSR_LBR_SELECT, task_ctx->lbr_sel);

arch/x86/events/intel/p4.c

1028

wrmsrq(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);

arch/x86/events/intel/p4.c

865

wrmsrq(hwc->config_base, v & ~P4_CCCR_OVF);

arch/x86/events/intel/p6.c

148

wrmsrq(MSR_P6_EVNTSEL0, val);

arch/x86/events/intel/p6.c

158

wrmsrq(MSR_P6_EVNTSEL0, val);

arch/x86/events/intel/pt.c

1590

wrmsrq(MSR_IA32_RTIT_CTL, event->hw.aux_config);

arch/x86/events/intel/pt.c

431

wrmsrq(MSR_IA32_RTIT_CTL, ctl);

arch/x86/events/intel/pt.c

490

wrmsrq(pt_address_ranges[range].msr_a, filter->msr_a);

arch/x86/events/intel/pt.c

495

wrmsrq(pt_address_ranges[range].msr_b, filter->msr_b);

arch/x86/events/intel/pt.c

514

wrmsrq(MSR_IA32_RTIT_STATUS, 0);

arch/x86/events/intel/pt.c

574

wrmsrq(MSR_IA32_RTIT_CTL, ctl);

arch/x86/events/intel/pt.c

663

wrmsrq(MSR_IA32_RTIT_OUTPUT_BASE, reg);

arch/x86/events/intel/pt.c

669

wrmsrq(MSR_IA32_RTIT_OUTPUT_MASK, reg);

arch/x86/events/intel/pt.c

975

wrmsrq(MSR_IA32_RTIT_STATUS, status);

arch/x86/events/intel/uncore_discovery.c

488

wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT);

arch/x86/events/intel/uncore_discovery.c

493

wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ);

arch/x86/events/intel/uncore_discovery.c

498

wrmsrq(intel_generic_uncore_box_ctl(box), 0);

arch/x86/events/intel/uncore_discovery.c

506

wrmsrq(hwc->config_base, hwc->config);

arch/x86/events/intel/uncore_discovery.c

514

wrmsrq(hwc->config_base, 0);

arch/x86/events/intel/uncore_nhmex.c

1125

wrmsrq(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);

arch/x86/events/intel/uncore_nhmex.c

1128

wrmsrq(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);

arch/x86/events/intel/uncore_nhmex.c

1132

wrmsrq(NHMEX_R_MSR_PORTN_QLX_CFG(port),

arch/x86/events/intel/uncore_nhmex.c

1136

wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),

arch/x86/events/intel/uncore_nhmex.c

1138

wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);

arch/x86/events/intel/uncore_nhmex.c

1139

wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);

arch/x86/events/intel/uncore_nhmex.c

1142

wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),

arch/x86/events/intel/uncore_nhmex.c

1144

wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);

arch/x86/events/intel/uncore_nhmex.c

1145

wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);

arch/x86/events/intel/uncore_nhmex.c

1149

wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |

arch/x86/events/intel/uncore_nhmex.c

204

wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);

arch/x86/events/intel/uncore_nhmex.c

209

wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0);

arch/x86/events/intel/uncore_nhmex.c

223

wrmsrq(msr, config);

arch/x86/events/intel/uncore_nhmex.c

238

wrmsrq(msr, config);

arch/x86/events/intel/uncore_nhmex.c

244

wrmsrq(event->hw.config_base, 0);

arch/x86/events/intel/uncore_nhmex.c

252

wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);

arch/x86/events/intel/uncore_nhmex.c

254

wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);

arch/x86/events/intel/uncore_nhmex.c

256

wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);

arch/x86/events/intel/uncore_nhmex.c

386

wrmsrq(reg1->reg, reg1->config);

arch/x86/events/intel/uncore_nhmex.c

387

wrmsrq(reg1->reg + 1, reg2->config);

arch/x86/events/intel/uncore_nhmex.c

389

wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |

arch/x86/events/intel/uncore_nhmex.c

471

wrmsrq(reg1->reg, 0);

arch/x86/events/intel/uncore_nhmex.c

472

wrmsrq(reg1->reg + 1, reg1->config);

arch/x86/events/intel/uncore_nhmex.c

473

wrmsrq(reg1->reg + 2, reg2->config);

arch/x86/events/intel/uncore_nhmex.c

474

wrmsrq(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);

arch/x86/events/intel/uncore_nhmex.c

476

wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);

arch/x86/events/intel/uncore_nhmex.c

846

wrmsrq(__BITS_VALUE(reg1->reg, 0, 16),

arch/x86/events/intel/uncore_nhmex.c

850

wrmsrq(__BITS_VALUE(reg1->reg, 1, 16),

arch/x86/events/intel/uncore_nhmex.c

854

wrmsrq(reg2->reg, 0);

arch/x86/events/intel/uncore_nhmex.c

856

wrmsrq(reg2->reg + 1,

arch/x86/events/intel/uncore_nhmex.c

858

wrmsrq(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &

arch/x86/events/intel/uncore_nhmex.c

860

wrmsrq(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);

arch/x86/events/intel/uncore_nhmex.c

864

wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);

arch/x86/events/intel/uncore_snb.c

1334

wrmsrq(NHM_UNC_PERF_GLOBAL_CTL, 0);

arch/x86/events/intel/uncore_snb.c

1339

wrmsrq(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);

arch/x86/events/intel/uncore_snb.c

1347

wrmsrq(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);

arch/x86/events/intel/uncore_snb.c

1349

wrmsrq(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);

arch/x86/events/intel/uncore_snb.c

288

wrmsrq(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);

arch/x86/events/intel/uncore_snb.c

290

wrmsrq(hwc->config_base, SNB_UNC_CTL_EN);

arch/x86/events/intel/uncore_snb.c

295

wrmsrq(event->hw.config_base, 0);

arch/x86/events/intel/uncore_snb.c

301

wrmsrq(SNB_UNC_PERF_GLOBAL_CTL,

arch/x86/events/intel/uncore_snb.c

308

wrmsrq(SNB_UNC_PERF_GLOBAL_CTL,

arch/x86/events/intel/uncore_snb.c

315

wrmsrq(SNB_UNC_PERF_GLOBAL_CTL, 0);

arch/x86/events/intel/uncore_snb.c

400

wrmsrq(SKL_UNC_PERF_GLOBAL_CTL,

arch/x86/events/intel/uncore_snb.c

411

wrmsrq(SKL_UNC_PERF_GLOBAL_CTL,

arch/x86/events/intel/uncore_snb.c

418

wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, 0);

arch/x86/events/intel/uncore_snb.c

553

wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);

arch/x86/events/intel/uncore_snb.c

569

wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);

arch/x86/events/intel/uncore_snb.c

574

wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);

arch/x86/events/intel/uncore_snb.c

580

wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, 0);

arch/x86/events/intel/uncore_snb.c

586

wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, 0);

arch/x86/events/intel/uncore_snb.c

719

wrmsrq(uncore_msr_box_ctl(box), SNB_UNC_GLOBAL_CTL_EN);

arch/x86/events/intel/uncore_snb.c

786

wrmsrq(LNL_UNC_MSR_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);

arch/x86/events/intel/uncore_snbep.c

1520

wrmsrq(msr, IVBEP_PMON_BOX_CTL_INT);

arch/x86/events/intel/uncore_snbep.c

1771

wrmsrq(reg1->reg, filter & 0xffffffff);

arch/x86/events/intel/uncore_snbep.c

1772

wrmsrq(reg1->reg + 6, filter >> 32);

arch/x86/events/intel/uncore_snbep.c

1775

wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);

arch/x86/events/intel/uncore_snbep.c

2755

wrmsrq(reg1->reg, filter & 0xffffffff);

arch/x86/events/intel/uncore_snbep.c

2756

wrmsrq(reg1->reg + 1, filter >> 32);

arch/x86/events/intel/uncore_snbep.c

2759

wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);

arch/x86/events/intel/uncore_snbep.c

2804

wrmsrq(msr, flags);

arch/x86/events/intel/uncore_snbep.c

3647

wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);

arch/x86/events/intel/uncore_snbep.c

4579

wrmsrq(reg1->reg, reg1->config);

arch/x86/events/intel/uncore_snbep.c

4581

wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);

arch/x86/events/intel/uncore_snbep.c

5772

wrmsrq(reg1->reg, reg1->config);

arch/x86/events/intel/uncore_snbep.c

5774

wrmsrq(hwc->config_base, hwc->config);

arch/x86/events/intel/uncore_snbep.c

5784

wrmsrq(reg1->reg, 0);

arch/x86/events/intel/uncore_snbep.c

5786

wrmsrq(hwc->config_base, 0);

arch/x86/events/intel/uncore_snbep.c

647

wrmsrq(msr, config);

arch/x86/events/intel/uncore_snbep.c

660

wrmsrq(msr, config);

arch/x86/events/intel/uncore_snbep.c

670

wrmsrq(reg1->reg, uncore_shared_reg_config(box, 0));

arch/x86/events/intel/uncore_snbep.c

672

wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);

arch/x86/events/intel/uncore_snbep.c

680

wrmsrq(hwc->config_base, hwc->config);

arch/x86/events/intel/uncore_snbep.c

688

wrmsrq(msr, SNBEP_PMON_BOX_CTL_INT);

arch/x86/events/perf_event.h

1274

wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config);

arch/x86/events/perf_event.h

1281

wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);

arch/x86/events/perf_event.h

1283

wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);

arch/x86/events/perf_event.h

1299

wrmsrq(hwc->config_base, hwc->config & ~disable_mask);

arch/x86/events/perf_event.h

1302

wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0);

arch/x86/events/perf_event.h

1477

wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);

arch/x86/events/perf_event.h

1481

wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);

arch/x86/events/perf_event.h

1622

wrmsrq(MSR_IA32_PEBS_ENABLE, 0);

arch/x86/events/perf_event.h

1627

wrmsrq(MSR_ARCH_LBR_CTL, 0);

arch/x86/events/perf_event.h

1636

wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);

arch/x86/events/zhaoxin/core.c

258

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);

arch/x86/events/zhaoxin/core.c

263

wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);

arch/x86/events/zhaoxin/core.c

277

wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);

arch/x86/events/zhaoxin/core.c

299

wrmsrq(hwc->config_base, ctrl_val);

arch/x86/events/zhaoxin/core.c

336

wrmsrq(hwc->config_base, ctrl_val);

arch/x86/hyperv/hv_apic.c

101

wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK);

arch/x86/hyperv/hv_apic.c

53

wrmsrq(HV_X64_MSR_ICR, reg_val);

arch/x86/hyperv/hv_apic.c

84

wrmsrq(HV_X64_MSR_EOI, val);

arch/x86/hyperv/hv_apic.c

87

wrmsrq(HV_X64_MSR_TPR, val);

arch/x86/hyperv/hv_init.c

170

wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);

arch/x86/hyperv/hv_init.c

201

wrmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);

arch/x86/hyperv/hv_init.c

249

wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl));

arch/x86/hyperv/hv_init.c

250

wrmsrq(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl));

arch/x86/hyperv/hv_init.c

265

wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl);

arch/x86/hyperv/hv_init.c

303

wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);

arch/x86/hyperv/hv_init.c

323

wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl));

arch/x86/hyperv/hv_init.c

382

wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);

arch/x86/hyperv/hv_init.c

401

wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);

arch/x86/hyperv/hv_init.c

516

wrmsrq(HV_X64_MSR_GUEST_OS_ID, guest_id);

arch/x86/hyperv/hv_init.c

549

wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);

arch/x86/hyperv/hv_init.c

562

wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);

arch/x86/hyperv/hv_init.c

611

wrmsrq(HV_X64_MSR_GUEST_OS_ID, 0);

arch/x86/hyperv/hv_init.c

632

wrmsrq(HV_X64_MSR_GUEST_OS_ID, 0);

arch/x86/hyperv/hv_init.c

676

wrmsrq(HV_X64_MSR_CRASH_P0, err);

arch/x86/hyperv/hv_init.c

677

wrmsrq(HV_X64_MSR_CRASH_P1, guest_id);

arch/x86/hyperv/hv_init.c

678

wrmsrq(HV_X64_MSR_CRASH_P2, regs->ip);

arch/x86/hyperv/hv_init.c

679

wrmsrq(HV_X64_MSR_CRASH_P3, regs->ax);

arch/x86/hyperv/hv_init.c

680

wrmsrq(HV_X64_MSR_CRASH_P4, regs->sp);

arch/x86/hyperv/hv_init.c

685

wrmsrq(HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_CRASH_NOTIFY);

arch/x86/include/asm/apic.h

208

wrmsrq(APIC_BASE_MSR + (reg >> 4), v);

arch/x86/include/asm/apic.h

229

wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);

arch/x86/include/asm/debugreg.h

194

wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);

arch/x86/include/asm/fsgsbase.h

73

wrmsrq(MSR_FS_BASE, fsbase);

arch/x86/include/asm/msr.h

289

wrmsrq(msr_no, q);

arch/x86/include/asm/msr.h

331

#define wrmsrl(msr, val) wrmsrq(msr, val)

arch/x86/include/asm/switch_to.h

64

wrmsrq(MSR_IA32_SYSENTER_CS, thread->sysenter_cs);

arch/x86/kernel/apic/apic.c

1724

wrmsrq(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));

arch/x86/kernel/apic/apic.c

1725

wrmsrq(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);

arch/x86/kernel/apic/apic.c

1736

wrmsrq(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);

arch/x86/kernel/apic/apic.c

431

wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));

arch/x86/kernel/apic/apic.c

455

wrmsrq(MSR_IA32_TSC_DEADLINE, 0);

arch/x86/kernel/cpu/amd.c

1283

wrmsrq(amd_msr_dr_addr_masks[dr], mask);

arch/x86/kernel/cpu/bugs.c

109

wrmsrq(MSR_IA32_SPEC_CTRL, val);

arch/x86/kernel/cpu/bugs.c

227

wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);

arch/x86/kernel/cpu/bugs.c

229

wrmsrq(MSR_AMD64_LS_CFG, msrval);

arch/x86/kernel/cpu/bugs.c

777

wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);

arch/x86/kernel/cpu/bugs.c

90

wrmsrq(MSR_IA32_SPEC_CTRL, val);

arch/x86/kernel/cpu/bugs.c

919

wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);

arch/x86/kernel/cpu/bus_lock.c

150

wrmsrq(MSR_TEST_CTRL, msr_test_ctrl_cache);

arch/x86/kernel/cpu/bus_lock.c

167

wrmsrq(MSR_TEST_CTRL, test_ctrl_val);

arch/x86/kernel/cpu/bus_lock.c

316

wrmsrq(MSR_IA32_DEBUGCTLMSR, val);

arch/x86/kernel/cpu/common.c

1919

wrmsrq(MSR_FS_BASE, 1);

arch/x86/kernel/cpu/common.c

1922

wrmsrq(MSR_FS_BASE, old_base);

arch/x86/kernel/cpu/common.c

2145

wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1);

arch/x86/kernel/cpu/common.c

2146

wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));

arch/x86/kernel/cpu/common.c

2147

wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32);

arch/x86/kernel/cpu/common.c

2262

wrmsrq(MSR_CSTAR, val);

arch/x86/kernel/cpu/common.c

2267

wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);

arch/x86/kernel/cpu/common.c

2292

wrmsrq(MSR_SYSCALL_MASK,

arch/x86/kernel/cpu/common.c

2357

wrmsrq(MSR_TSC_AUX, cpudata);

arch/x86/kernel/cpu/common.c

2484

wrmsrq(MSR_FS_BASE, 0);

arch/x86/kernel/cpu/common.c

2485

wrmsrq(MSR_KERNEL_GS_BASE, 0);

arch/x86/kernel/cpu/common.c

612

wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);

arch/x86/kernel/cpu/common.c

626

wrmsrq(MSR_IA32_S_CET, msr);

arch/x86/kernel/cpu/common.c

650

wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN);

arch/x86/kernel/cpu/common.c

652

wrmsrq(MSR_IA32_S_CET, 0);

arch/x86/kernel/cpu/common.c

658

wrmsrq(MSR_IA32_S_CET, 0);

arch/x86/kernel/cpu/common.c

669

wrmsrq(MSR_IA32_S_CET, 0);

arch/x86/kernel/cpu/common.c

670

wrmsrq(MSR_IA32_U_CET, 0);

arch/x86/kernel/cpu/common.c

809

wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));

arch/x86/kernel/cpu/feat_ctl.c

169

wrmsrq(MSR_IA32_FEAT_CTL, msr);

arch/x86/kernel/cpu/intel.c

512

wrmsrq(MSR_MISC_FEATURES_ENABLES, msr);

arch/x86/kernel/cpu/intel_epb.c

114

wrmsrq(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val);

arch/x86/kernel/cpu/mce/amd.c

656

wrmsrq(MSR_K7_HWCR, hwcr | BIT(18));

arch/x86/kernel/cpu/mce/amd.c

664

wrmsrq(MSR_K7_HWCR, hwcr);

arch/x86/kernel/cpu/mce/core.c

1922

wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);

arch/x86/kernel/cpu/mce/core.c

1923

wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

2423

wrmsrq(mca_msr_reg(i, MCA_CTL), 0);

arch/x86/kernel/cpu/mce/core.c

2779

wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);

arch/x86/kernel/cpu/mce/inject.c

479

wrmsrq(MSR_IA32_MCG_STATUS, m.mcgstatus);

arch/x86/kernel/cpu/mce/inject.c

483

wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status);

arch/x86/kernel/cpu/mce/inject.c

484

wrmsrq(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr);

arch/x86/kernel/cpu/mce/inject.c

486

wrmsrq(MSR_AMD64_SMCA_MCx_STATUS(b), m.status);

arch/x86/kernel/cpu/mce/inject.c

487

wrmsrq(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr);

arch/x86/kernel/cpu/mce/inject.c

490

wrmsrq(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);

arch/x86/kernel/cpu/mce/inject.c

493

wrmsrq(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);

arch/x86/kernel/cpu/mce/inject.c

495

wrmsrq(MSR_IA32_MCx_STATUS(b), m.status);

arch/x86/kernel/cpu/mce/inject.c

496

wrmsrq(MSR_IA32_MCx_ADDR(b), m.addr);

arch/x86/kernel/cpu/mce/inject.c

499

wrmsrq(MSR_IA32_MCx_MISC(b), m.misc);

arch/x86/kernel/cpu/mce/intel.c

146

wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh);

arch/x86/kernel/cpu/mce/intel.c

235

wrmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

329

wrmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

436

wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);

arch/x86/kernel/cpu/mce/intel.c

448

wrmsrq(MSR_IA32_MCG_EXT_CTL, val);

arch/x86/kernel/cpu/mshyperv.c

675

wrmsrq(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);

arch/x86/kernel/cpu/resctrl/core.c

318

wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]);

arch/x86/kernel/cpu/resctrl/core.c

343

wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res));

arch/x86/kernel/cpu/resctrl/core.c

353

wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]);

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

218

wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr);

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

254

wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

350

wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);

arch/x86/kernel/cpu/resctrl/rdtgroup.c

115

wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config);

arch/x86/kernel/cpu/resctrl/rdtgroup.c

122

wrmsrq(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);

arch/x86/kernel/cpu/resctrl/rdtgroup.c

129

wrmsrq(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);

arch/x86/kernel/cpu/sgx/main.c

879

wrmsrq(MSR_IA32_SGXLEPUBKEYHASH0 + i, lepubkeyhash[i]);

arch/x86/kernel/cpu/tsx.c

131

wrmsrq(MSR_TSX_FORCE_ABORT, msr);

arch/x86/kernel/cpu/tsx.c

135

wrmsrq(MSR_IA32_TSX_CTRL, msr);

arch/x86/kernel/cpu/tsx.c

164

wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl);

arch/x86/kernel/cpu/tsx.c

51

wrmsrq(MSR_IA32_TSX_CTRL, tsx);

arch/x86/kernel/cpu/tsx.c

70

wrmsrq(MSR_IA32_TSX_CTRL, tsx);

arch/x86/kernel/cpu/umwait.c

36

wrmsrq(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached));

arch/x86/kernel/cpu/umwait.c

74

wrmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached);

arch/x86/kernel/fpu/xstate.c

233

wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() |

arch/x86/kernel/fpu/xstate.c

687

wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor());

arch/x86/kernel/fpu/xstate.c

696

wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() | mask);

arch/x86/kernel/fpu/xstate.c

985

wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() |

arch/x86/kernel/fpu/xstate.c

990

wrmsrq(MSR_IA32_XFD, x86_task_fpu(current)->fpstate->xfd);

arch/x86/kernel/fpu/xstate.h

185

wrmsrq(MSR_IA32_XFD, xfd);

arch/x86/kernel/fred.c

47

wrmsrq(MSR_IA32_FRED_CONFIG,

arch/x86/kernel/fred.c

53

wrmsrq(MSR_IA32_FRED_STKLVLS, 0);

arch/x86/kernel/fred.c

59

wrmsrq(MSR_IA32_FRED_RSP0, __this_cpu_read(fred_rsp0));

arch/x86/kernel/fred.c

61

wrmsrq(MSR_IA32_FRED_RSP1, 0);

arch/x86/kernel/fred.c

62

wrmsrq(MSR_IA32_FRED_RSP2, 0);

arch/x86/kernel/fred.c

63

wrmsrq(MSR_IA32_FRED_RSP3, 0);

arch/x86/kernel/fred.c

83

wrmsrq(MSR_IA32_FRED_STKLVLS,

arch/x86/kernel/fred.c

90

wrmsrq(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB));

arch/x86/kernel/fred.c

91

wrmsrq(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI));

arch/x86/kernel/fred.c

92

wrmsrq(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF));

arch/x86/kernel/kvm.c

1012

wrmsrq(MSR_KVM_MIGRATION_CONTROL,

arch/x86/kernel/kvm.c

1165

wrmsrq(MSR_KVM_POLL_CONTROL, 0);

arch/x86/kernel/kvm.c

1170

wrmsrq(MSR_KVM_POLL_CONTROL, 1);

arch/x86/kernel/kvm.c

319

wrmsrq(MSR_KVM_ASYNC_PF_ACK, 1);

arch/x86/kernel/kvm.c

345

wrmsrq(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED));

arch/x86/kernel/kvm.c

379

wrmsrq(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR);

arch/x86/kernel/kvm.c

381

wrmsrq(MSR_KVM_ASYNC_PF_EN, pa);

arch/x86/kernel/kvm.c

394

wrmsrq(MSR_KVM_PV_EOI_EN, pa);

arch/x86/kernel/kvm.c

406

wrmsrq(MSR_KVM_ASYNC_PF_EN, 0);

arch/x86/kernel/kvm.c

417

wrmsrq(MSR_KVM_STEAL_TIME, 0);

arch/x86/kernel/kvm.c

469

wrmsrq(MSR_KVM_PV_EOI_EN, 0);

arch/x86/kernel/kvm.c

471

wrmsrq(MSR_KVM_MIGRATION_CONTROL, 0);

arch/x86/kernel/kvm.c

633

wrmsrq(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY);

arch/x86/kernel/kvm.c

758

wrmsrq(MSR_KVM_POLL_CONTROL, 0);

arch/x86/kernel/kvmclock.c

177

wrmsrq(msr_kvm_system_time, pa);

arch/x86/kernel/kvmclock.c

64

wrmsrq(msr_kvm_wall_clock, slow_virt_to_phys(&wall_clock));

arch/x86/kernel/mmconf-fam10h_64.c

215

wrmsrq(address, val);

arch/x86/kernel/process.c

355

wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval);

arch/x86/kernel/process.c

583

wrmsrq(MSR_AMD64_LS_CFG, msr);

arch/x86/kernel/process.c

600

wrmsrq(MSR_AMD64_LS_CFG, msr);

arch/x86/kernel/process.c

610

wrmsrq(MSR_AMD64_LS_CFG, msr);

arch/x86/kernel/process.c

619

wrmsrq(MSR_AMD64_LS_CFG, msr);

arch/x86/kernel/process.c

629

wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));

arch/x86/kernel/process.c

736

wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);

arch/x86/kernel/process_64.c

226

wrmsrq(MSR_KERNEL_GS_BASE, gsbase);

arch/x86/kernel/process_64.c

356

wrmsrq(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE,

arch/x86/kernel/process_64.c

481

wrmsrq(MSR_KERNEL_GS_BASE, gsbase);

arch/x86/kernel/reboot_fixups_32.c

30

wrmsrq(MSR_DIVIL_SOFT_RESET, 1ULL);

arch/x86/kernel/shstk.c

176

wrmsrq(MSR_IA32_PL3_SSP, addr + size);

arch/x86/kernel/shstk.c

177

wrmsrq(MSR_IA32_U_CET, CET_SHSTK_EN);

arch/x86/kernel/shstk.c

263

wrmsrq(MSR_IA32_PL3_SSP, ssp + SS_FRAME_SIZE);

arch/x86/kernel/shstk.c

283

wrmsrq(MSR_IA32_PL3_SSP, ssp);

arch/x86/kernel/shstk.c

416

wrmsrq(MSR_IA32_PL3_SSP, ssp);

arch/x86/kernel/shstk.c

440

wrmsrq(MSR_IA32_PL3_SSP, ssp);

arch/x86/kernel/shstk.c

517

wrmsrq(MSR_IA32_U_CET, msrval);

arch/x86/kernel/shstk.c

536

wrmsrq(MSR_IA32_U_CET, 0);

arch/x86/kernel/shstk.c

537

wrmsrq(MSR_IA32_PL3_SSP, 0);

arch/x86/kernel/traps.c

1253

wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);

arch/x86/kernel/traps.c

1521

wrmsrq(MSR_IA32_XFD_ERR, 0);

arch/x86/kernel/traps.c

874

wrmsrq(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID);

arch/x86/kernel/tsc_sync.c

146

wrmsrq(MSR_IA32_TSC_ADJUST, 0);

arch/x86/kernel/tsc_sync.c

233

wrmsrq(MSR_IA32_TSC_ADJUST, ref->adjusted);

arch/x86/kernel/tsc_sync.c

522

wrmsrq(MSR_IA32_TSC_ADJUST, cur->adjusted);

arch/x86/kernel/tsc_sync.c

74

wrmsrq(MSR_IA32_TSC_ADJUST, adj->adjusted);

arch/x86/kvm/pmu.c

1350

wrmsrq(kvm_pmu_ops.PERF_GLOBAL_CTRL, 0);

arch/x86/kvm/pmu.c

1374

wrmsrq(gp_counter_msr(i), 0);

arch/x86/kvm/pmu.c

1376

wrmsrq(gp_eventsel_msr(i), 0);

arch/x86/kvm/pmu.c

1384

wrmsrq(fixed_counter_msr(i), 0);

arch/x86/kvm/svm/avic.c

452

wrmsrq(MSR_AMD64_SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpu));

arch/x86/kvm/svm/pmu.c

245

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, global_status);

arch/x86/kvm/svm/pmu.c

247

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, pmu->global_status);

arch/x86/kvm/svm/pmu.c

248

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, pmu->global_ctrl);

arch/x86/kvm/svm/pmu.c

255

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);

arch/x86/kvm/svm/pmu.c

260

wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, pmu->global_status);

arch/x86/kvm/svm/svm.c

471

wrmsrq(MSR_AMD64_TSC_RATIO, multiplier);

arch/x86/kvm/svm/svm.c

484

wrmsrq(MSR_VM_HSAVE_PA, 0);

arch/x86/kvm/svm/svm.c

492

wrmsrq(MSR_EFER, efer & ~EFER_SVME);

arch/x86/kvm/svm/svm.c

531

wrmsrq(MSR_EFER, efer | EFER_SVME);

arch/x86/kvm/svm/svm.c

533

wrmsrq(MSR_VM_HSAVE_PA, sd->save_area_pa);

arch/x86/kvm/vmx/pmu_intel.c

314

wrmsrq(index, msr_info->data);

arch/x86/kvm/vmx/pmu_intel.c

797

wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, global_status & toggle);

arch/x86/kvm/vmx/pmu_intel.c

799

wrmsrq(MSR_CORE_PERF_GLOBAL_STATUS_SET, pmu->global_status & toggle);

arch/x86/kvm/vmx/pmu_intel.c

801

wrmsrq(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl_hw);

arch/x86/kvm/vmx/pmu_intel.c

813

wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, pmu->global_status);

arch/x86/kvm/vmx/pmu_intel.c

821

wrmsrq(MSR_CORE_PERF_FIXED_CTR_CTRL, 0);

arch/x86/kvm/vmx/vmx.c

1148

wrmsrq(MSR_IA32_PEBS_ENABLE, 0);

arch/x86/kvm/vmx/vmx.c

1263

wrmsrq(MSR_IA32_RTIT_STATUS, ctx->status);

arch/x86/kvm/vmx/vmx.c

1264

wrmsrq(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);

arch/x86/kvm/vmx/vmx.c

1265

wrmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);

arch/x86/kvm/vmx/vmx.c

1266

wrmsrq(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);

arch/x86/kvm/vmx/vmx.c

1268

wrmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);

arch/x86/kvm/vmx/vmx.c

1269

wrmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);

arch/x86/kvm/vmx/vmx.c

1298

wrmsrq(MSR_IA32_RTIT_CTL, 0);

arch/x86/kvm/vmx/vmx.c

1319

wrmsrq(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);

arch/x86/kvm/vmx/vmx.c

1410

wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);

arch/x86/kvm/vmx/vmx.c

1454

wrmsrq(MSR_KERNEL_GS_BASE, vmx->vt.msr_host_kernel_gs_base);

arch/x86/kvm/x86.c

11343

wrmsrq(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);

arch/x86/kvm/x86.c

11458

wrmsrq(MSR_IA32_XFD_ERR, 0);

arch/x86/kvm/x86.c

1228

wrmsrq(MSR_IA32_XSS, load_guest ? vcpu->arch.ia32_xss : kvm_host.xss);

arch/x86/kvm/x86.c

14102

wrmsrq(MSR_IA32_SPEC_CTRL, saved_value);

arch/x86/kvm/x86.c

3890

wrmsrq(msr_info->index, msr_info->data);

arch/x86/kvm/x86.c

3986

wrmsrq(MSR_IA32_PRED_CMD, data);

arch/x86/kvm/x86.c

3999

wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);

arch/x86/kvm/x86.c

604

wrmsrq(kvm_uret_msrs_list[slot], values->host);

arch/x86/mm/pat/memtype.c

236

wrmsrq(MSR_IA32_CR_PAT, pat_msr_val);

arch/x86/mm/tlb.c

633

wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);

arch/x86/pci/amd_bus.c

347

wrmsrq(MSR_AMD64_NB_CFG, reg);

arch/x86/platform/olpc/olpc-xo1-sci.c

328

wrmsrq(0x51400020, lo);

arch/x86/power/cpu.c

202

wrmsrq(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);

arch/x86/power/cpu.c

212

wrmsrq(MSR_EFER, ctxt->efer);

arch/x86/power/cpu.c

235

wrmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base);

arch/x86/power/cpu.c

271

wrmsrq(MSR_FS_BASE, ctxt->fs_base);

arch/x86/power/cpu.c

272

wrmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);

arch/x86/power/cpu.c

60

wrmsrq(msr->info.msr_no, msr->info.reg.q);

arch/x86/virt/svm/sev.c

144

wrmsrq(MSR_AMD64_SYSCFG, val);

arch/x86/virt/svm/sev.c

166

wrmsrq(MSR_AMD64_SYSCFG, val);

arch/x86/xen/suspend.c

43

wrmsrq(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl));

arch/x86/xen/suspend.c

61

wrmsrq(MSR_IA32_SPEC_CTRL, 0);

drivers/cpufreq/acpi-cpufreq.c

120

wrmsrq(msr_addr, val);

drivers/cpufreq/amd-pstate.c

263

wrmsrq(MSR_AMD_CPPC_REQ, value);

drivers/cpufreq/e_powersaver.c

230

wrmsrq(MSR_IA32_MISC_ENABLE, val);

drivers/cpufreq/intel_pstate.c

1406

wrmsrq(MSR_IA32_POWER_CTL, power_ctl);

drivers/cpufreq/intel_pstate.c

2412

wrmsrq(MSR_HWP_REQUEST, hwp_req);

drivers/cpufreq/intel_pstate.c

2425

wrmsrq(MSR_HWP_REQUEST, cpu->hwp_req_cached);

drivers/cpufreq/intel_pstate.c

2581

wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));

drivers/cpufreq/intel_pstate.c

3165

wrmsrq(MSR_HWP_REQUEST, value);

drivers/cpufreq/intel_pstate.c

3174

wrmsrq(MSR_IA32_PERF_CTL,

drivers/cpufreq/longhaul.c

147

wrmsrq(MSR_VIA_BCR2, bcr2.val);

drivers/cpufreq/longhaul.c

156

wrmsrq(MSR_VIA_BCR2, bcr2.val);

drivers/cpufreq/longhaul.c

183

wrmsrq(MSR_VIA_LONGHAUL, longhaul.val);

drivers/cpufreq/longhaul.c

197

wrmsrq(MSR_VIA_LONGHAUL, longhaul.val);

drivers/cpufreq/longhaul.c

202

wrmsrq(MSR_VIA_LONGHAUL, longhaul.val);

drivers/cpufreq/longhaul.c

215

wrmsrq(MSR_VIA_LONGHAUL, longhaul.val);

drivers/cpufreq/longhaul.c

220

wrmsrq(MSR_VIA_LONGHAUL, longhaul.val);

drivers/cpufreq/longhaul.c

234

wrmsrq(MSR_VIA_LONGHAUL, longhaul.val);

drivers/cpufreq/powernow-k7.c

228

wrmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val);

drivers/cpufreq/powernow-k7.c

243

wrmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val);

drivers/crypto/ccp/sev-dev.c

1081

wrmsrq(MSR_VM_HSAVE_PA, 0);

drivers/idle/intel_idle.c

2090

wrmsrq(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);

drivers/idle/intel_idle.c

2091

wrmsrq(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);

drivers/idle/intel_idle.c

2246

wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);

drivers/idle/intel_idle.c

2255

wrmsrq(MSR_IA32_POWER_CTL, msr_bits);

drivers/idle/intel_idle.c

2264

wrmsrq(MSR_IA32_POWER_CTL, msr_bits);

drivers/platform/x86/intel/ifs/load.c

131

wrmsrq(msrs->copy_hashes, ifs_hash_ptr);

drivers/platform/x86/intel/ifs/load.c

153

wrmsrq(msrs->copy_chunks, linear_addr);

drivers/platform/x86/intel/ifs/load.c

199

wrmsrq(msrs->copy_hashes, ifs_hash_ptr);

drivers/platform/x86/intel/ifs/load.c

220

wrmsrq(msrs->test_ctrl, INVALIDATE_STRIDE);

drivers/platform/x86/intel/ifs/load.c

242

wrmsrq(msrs->copy_chunks, (u64)chunk_table);

drivers/platform/x86/intel/ifs/runtest.c

213

wrmsrq(MSR_ACTIVATE_SCAN, params->activate->data);

drivers/platform/x86/intel/ifs/runtest.c

325

wrmsrq(MSR_ARRAY_BIST, command->data);

drivers/platform/x86/intel/ifs/runtest.c

378

wrmsrq(MSR_ARRAY_TRIGGER, ARRAY_GEN1_TEST_ALL_ARRAYS);

drivers/platform/x86/intel/ifs/runtest.c

530

wrmsrq(MSR_ACTIVATE_SBAF, run_params->activate->data);

drivers/platform/x86/intel/pmc/cnp.c

234

wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);

drivers/platform/x86/intel/pmc/cnp.c

243

wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, per_cpu(pkg_cst_config, cpunum));

drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c

56

wrmsrq(MSR_OS_MAILBOX_DATA, command_data);

drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c

63

wrmsrq(MSR_OS_MAILBOX_INTERFACE, data);

drivers/platform/x86/intel_ips.c

1601

wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);

drivers/platform/x86/intel_ips.c

1602

wrmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);

drivers/platform/x86/intel_ips.c

385

wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);

drivers/platform/x86/intel_ips.c

390

wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);

drivers/platform/x86/intel_ips.c

420

wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);

drivers/platform/x86/intel_ips.c

425

wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);

drivers/platform/x86/intel_ips.c

443

wrmsrq(IA32_PERF_CTL, perf_ctl);

drivers/platform/x86/intel_ips.c

481

wrmsrq(IA32_PERF_CTL, perf_ctl);

drivers/thermal/intel/intel_hfi.c

361

wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);

drivers/thermal/intel/intel_hfi.c

371

wrmsrq(MSR_IA32_HW_FEEDBACK_PTR, msr_val);

drivers/thermal/intel/intel_hfi.c

382

wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);

drivers/thermal/intel/therm_throt.c

277

wrmsrq(msr, msr_val);

drivers/video/fbdev/geode/lxfb_ops.c

375

wrmsrq(MSR_LX_GLD_MSR_CONFIG, msrval);

drivers/video/fbdev/geode/lxfb_ops.c

431

wrmsrq(MSR_LX_SPARE_MSR, msrval);

drivers/video/fbdev/geode/lxfb_ops.c

668

wrmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare);

drivers/video/fbdev/geode/lxfb_ops.c

733

wrmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);

drivers/video/fbdev/geode/lxfb_ops.c

734

wrmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel);

drivers/video/fbdev/geode/suspend_gx.c

136

wrmsrq(MSR_GX_MSR_PADSEL, par->msr.padsel);

drivers/video/fbdev/geode/video_gx.c

154

wrmsrq(MSR_GLCP_DOTPLL, dotpll);

drivers/video/fbdev/geode/video_gx.c

162

wrmsrq(MSR_GLCP_SYS_RSTPLL, sys_rstpll);

drivers/video/fbdev/geode/video_gx.c

166

wrmsrq(MSR_GLCP_DOTPLL, dotpll);

drivers/video/fbdev/geode/video_gx.c

186

wrmsrq(MSR_GX_MSR_PADSEL, val);