wrmsr
wrmsr
wrmsr
extern void __noreturn ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr);
static inline void __noreturn ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
wrmsr(msr_no, l, h);
wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);
wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr(MSR_K6_WHCR, l, h);
wrmsr(MSR_K6_WHCR, l, h);
wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
wrmsr(MSR_IDT_FCR1, newlo, hi);
wrmsr(MSR_VIA_FCR, lo, hi);
wrmsr(MSR_VIA_RNG, lo, hi);
wrmsr(MSR_VIA_FCR, lo, hi);
wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
wrmsr(smca_config, low, high);
wrmsr(tr->b->address, lo, hi);
wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
if (wrmsr) {
wrmsr(MSR_IDT_FCR1, lo, hi);
wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
wrmsr(MSR_IDT_MCR0 + reg, low, high);
wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID,
wrmsr(MSR_IA32_QM_EVTSEL, eventid, prmid);
wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id);
wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
wrmsr(0x80860004, ~0, uk);
wrmsr(0x80860004, cap_mask, uk);
wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
II(ImplicitOps | Priv, em_wrmsr, wrmsr),
wrmsr(rv->msr_no, reg->l, reg->h);
struct pt_regs *regs, bool wrmsr, bool safe, int reg)
if (__ONCE_LITE_IF(!safe && wrmsr)) {
if (__ONCE_LITE_IF(!safe && !wrmsr)) {
if (!wrmsr) {
wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
wrmsr(MSR_IDE_CFG + reg, val, 0);
wrmsr(SYSCFG, sys_lo, sys_hi);
wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
wrmsr(MSR_VIA_RNG, lo, hi);
wrmsr(MSR_IA32_PERF_CTL, lo, hi);
wrmsr(MSR_AMD_PERF_CTL, val, 0);
wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
wrmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
wrmsr(MSR_TMTA_LRTI_READOUT, msr_hi, msr_hi);
wrmsr(MSR_TMTA_LRTI_READOUT, 0, msr_hi);
wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
wrmsr(MSR_TMTA_LONGRUN_CTRL, save_lo, save_hi);
wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
wrmsr(MSR_FIDVID_CTL, lo, hi);
wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS);
wrmsr(MSR_IA32_MISC_ENABLE, l, h);
wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
wrmsr(MSR_MFGPT_SETUP, val, dummy);
wrmsr(msr, value, dummy);
wrmsr(MSR_IA32_THERM_INTERRUPT,
wrmsr(MSR_IA32_THERM_INTERRUPT,
wrmsr(MSR_IA32_THERM_INTERRUPT,
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
wrmsr(MSR_IA32_APICBASE,
wrmsr(MSR_IA32_APICBASE,
wrmsr(MSR_IA32_APICBASE, val | MSR_IA32_APICBASE_ENABLE);
wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) |
wrmsr(HV_X64_MSR_VP_ASSIST_PAGE, val);
wrmsr(MSR_EFER, efer | EFER_SVME);
wrmsr(MSR_VM_HSAVE_PA, svm->save_area_gpa);
wrmsr(MSR_IA32_FEAT_CTL, feature_control | required);
wrmsr(MSR_IA32_XFD, 0);
wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILE_DATA);
wrmsr(MSR_IA32_XFD, 0);
wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILE_DATA);
wrmsr(MSR_IA32_XFD_ERR, 0);
wrmsr(MSR_IA32_XFD, 0);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_REFERENCE_TSC, tsc_page_gpa);
wrmsr(HV_X64_MSR_REFERENCE_TSC, tsc_page_gpa | 0x1);
wrmsr(HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0x1 << 16 | 0xff);
wrmsr(HV_X64_MSR_TSC_EMULATION_CONTROL, 0x1);
wrmsr(HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
wrmsr(HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
wrmsr(HV_X64_MSR_REFERENCE_TSC, 0);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_HYPERCALL, hv_hcall_page_gpa);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_HYPERCALL, in_pg_gpa);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa);
wrmsr(HV_X64_MSR_EOI, 1);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(HV_X64_MSR_HYPERCALL, data->hcall_gpa);
wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
wrmsr(MSR_KVM_SYSTEM_TIME_NEW, pvti_pa | KVM_MSR_ENABLED);
wrmsr(MSR_IA32_MISC_ENABLE, val);
wrmsr(MSR_IA32_TSC, l1_tsc - TSC_ADJUST_VALUE);
wrmsr(MSR_IA32_TSC, rdtsc() - TSC_ADJUST_VALUE);
wrmsr(MSR_AMD64_TSC_RATIO, L2_SCALE_FACTOR << 32);
wrmsr(MSR_KERNEL_GS_BASE, 0xaaaa);
wrmsr(MSR_KERNEL_GS_BASE, 0);
wrmsr(pmc_msr, 0xdead);
wrmsr(_pmc_msr, 0); \
wrmsr(MSR_P6_EVNTSEL0 + i, 0);
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i));
wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(i, FIXED_PMC_KERNEL));
wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0);
wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(i, FIXED_PMC_KERNEL));
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, FIXED_PMC_GLOBAL_CTRL_ENABLE(i));
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
wrmsr(MSR_P6_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_P6_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
wrmsr(MSR_K7_EVNTSEL0, 0);
wrmsr(MSR_K7_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_K7_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
wrmsr(MSR_P6_EVNTSEL0 + 0, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_P6_EVNTSEL0 + 1, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_P6_EVNTSEL0 + 2, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x7);
wrmsr(MSR_K7_EVNTSEL0, 0);
wrmsr(MSR_K7_EVNTSEL1, 0);
wrmsr(MSR_K7_EVNTSEL2, 0);
wrmsr(MSR_K7_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_K7_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_K7_EVNTSEL2, ARCH_PERFMON_EVENTSEL_ENABLE |
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
wrmsr(MSR_CORE_PERF_FIXED_CTR0 + idx, 0);
wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(idx, FIXED_PMC_KERNEL));
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, FIXED_PMC_GLOBAL_CTRL_ENABLE(idx));
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
wrmsr(msr, v);
wrmsr(msr, v);
wrmsr(msr, val);
wrmsr(MSR_AMD64_SEV_ES_GHCB, GHCB_MSR_TERM_REQ);
wrmsr(MSR_AMD64_SEV_ES_GHCB, GHCB_MSR_TERM_REQ);
wrmsr(MSR_IA32_APICBASE, apicbase | X2APIC_ENABLE);
wrmsr(MSR_IA32_BNDCFGS, BIT_ULL(0));
wrmsr(MSR_IA32_BNDCFGS, 0);
wrmsr(MSR_IA32_TSC, val);
wrmsr(MSR_IA32_TSC_ADJUST, val);
wrmsr(MSR_IA32_TSC_ADJUST, val);
wrmsr(MSR_IA32_TSC, val);
wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT);
wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN);
wrmsr(MSR_SYSCALL_MASK, 0);
wrmsr(MSR_IA32_POWER_CTL, 0x1234);
wrmsr(0xdeadbeef, 0x1234);
wrmsr(MSR_GS_BASE, LA57_GS_BASE);