arch/powerpc/platforms/powermac/low_i2c.c

490

u32 steps;

arch/powerpc/platforms/powermac/low_i2c.c

516

steps = psteps ? (*psteps) : 0x10;

arch/powerpc/platforms/powermac/low_i2c.c

517

for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)

arch/powerpc/platforms/powermac/low_i2c.c

518

steps >>= 1;

block/sed-opal.c

2684

const struct opal_step steps[] = {

block/sed-opal.c

2695

ret = execute_steps(dev, steps, ARRAY_SIZE(steps));

block/sed-opal.c

2827

const struct opal_step steps[] = {

block/sed-opal.c

2859

ret = execute_steps(dev, steps, ARRAY_SIZE(steps));

block/sed-opal.c

538

const struct opal_step *steps, size_t n_steps)

block/sed-opal.c

549

error = execute_step(dev, &steps[state], state);

drivers/block/drbd/drbd_worker.c

505

int steps; /* Number of time steps to plan ahead */

drivers/block/drbd/drbd_worker.c

513

steps = plan->size; /* (dc->c_plan_ahead * 10 * SLEEP_TIME) / HZ; */

drivers/block/drbd/drbd_worker.c

516

want = ((dc->resync_rate * 2 * SLEEP_TIME) / HZ) * steps;

drivers/block/drbd/drbd_worker.c

525

cps = correction / steps;

drivers/block/drbd/drbd_worker.c

527

plan->total += cps * steps;

drivers/comedi/drivers/usbduxfast.c

355

unsigned int steps;

drivers/comedi/drivers/usbduxfast.c

402

steps = (cmd->convert_arg * 30) / 1000;

drivers/comedi/drivers/usbduxfast.c

404

err2 |= comedi_check_trigger_arg_min(&steps,

drivers/comedi/drivers/usbduxfast.c

407

err2 |= comedi_check_trigger_arg_min(&steps, 1);

drivers/comedi/drivers/usbduxfast.c

408

err2 |= comedi_check_trigger_arg_max(&steps, MAX_SAMPLING_PERIOD);

drivers/comedi/drivers/usbduxfast.c

411

arg = (steps * 1000) / 30;

drivers/comedi/drivers/usbduxfast.c

471

long steps, steps_tmp;

drivers/comedi/drivers/usbduxfast.c

485

steps = (cmd->convert_arg * 30) / 1000;

drivers/comedi/drivers/usbduxfast.c

513

if (steps < MIN_SAMPLING_PERIOD) {

drivers/comedi/drivers/usbduxfast.c

515

if (steps <= 1) {

drivers/comedi/drivers/usbduxfast.c

534

usbduxfast_cmd_data(dev, 1, steps - 1,

drivers/comedi/drivers/usbduxfast.c

550

steps = steps - 1;

drivers/comedi/drivers/usbduxfast.c

554

steps / 2, 0x00, rngmask, 0x00);

drivers/comedi/drivers/usbduxfast.c

557

usbduxfast_cmd_data(dev, 2, steps - steps / 2,

drivers/comedi/drivers/usbduxfast.c

585

steps_tmp = steps - 1;

drivers/comedi/drivers/usbduxfast.c

608

steps_tmp = steps - 2;

drivers/comedi/drivers/usbduxfast.c

644

usbduxfast_cmd_data(dev, index, steps / 2,

drivers/comedi/drivers/usbduxfast.c

655

usbduxfast_cmd_data(dev, index + 1, steps - steps / 2,

drivers/comedi/drivers/usbduxfast.c

660

steps_tmp = steps - 2;

drivers/comedi/drivers/usbduxfast.c

714

steps = steps - 2;

drivers/comedi/drivers/usbduxfast.c

717

usbduxfast_cmd_data(dev, 2, steps / 2,

drivers/comedi/drivers/usbduxfast.c

721

usbduxfast_cmd_data(dev, 3, steps - steps / 2,

drivers/crypto/hisilicon/sec/sec_algs.c

549

int *steps, gfp_t gfp)

drivers/crypto/hisilicon/sec/sec_algs.c

555

*steps = roundup(length, SEC_REQ_LIMIT) / SEC_REQ_LIMIT;

drivers/crypto/hisilicon/sec/sec_algs.c

556

sizes = kzalloc_objs(*sizes, *steps, gfp);

drivers/crypto/hisilicon/sec/sec_algs.c

560

for (i = 0; i < *steps - 1; i++)

drivers/crypto/hisilicon/sec/sec_algs.c

562

sizes[*steps - 1] = length - SEC_REQ_LIMIT * (*steps - 1);

drivers/crypto/hisilicon/sec/sec_algs.c

569

int steps, struct scatterlist ***splits,

drivers/crypto/hisilicon/sec/sec_algs.c

580

*splits = kzalloc_objs(struct scatterlist *, steps, gfp);

drivers/crypto/hisilicon/sec/sec_algs.c

585

*splits_nents = kzalloc_objs(int, steps, gfp);

drivers/crypto/hisilicon/sec/sec_algs.c

592

ret = sg_split(sgl, count, 0, steps, split_sizes,

drivers/crypto/hisilicon/sec/sec_algs.c

615

static void sec_unmap_sg_on_err(struct scatterlist *sgl, int steps,

drivers/crypto/hisilicon/sec/sec_algs.c

621

for (i = 0; i < steps; i++)

drivers/crypto/hisilicon/sec/sec_algs.c

716

int i, ret, steps;

drivers/crypto/hisilicon/sec/sec_algs.c

733

&steps, gfp);

drivers/crypto/hisilicon/sec/sec_algs.c

736

sec_req->num_elements = steps;

drivers/crypto/hisilicon/sec/sec_algs.c

737

ret = sec_map_and_split_sg(skreq->src, split_sizes, steps, &splits_in,

drivers/crypto/hisilicon/sec/sec_algs.c

745

ret = sec_map_and_split_sg(skreq->dst, split_sizes, steps,

drivers/crypto/hisilicon/sec/sec_algs.c

772

for (i = 0; i < steps; i++) {

drivers/crypto/hisilicon/sec/sec_algs.c

810

if ((!sec_queue_can_enqueue(queue, steps) &&

drivers/crypto/hisilicon/sec/sec_algs.c

812

kfifo_avail(&queue->softqueue) > steps)) ||

drivers/crypto/hisilicon/sec/sec_algs.c

850

sec_unmap_sg_on_err(skreq->dst, steps, splits_out,

drivers/crypto/hisilicon/sec/sec_algs.c

854

sec_unmap_sg_on_err(skreq->src, steps, splits_in, splits_in_nents,

drivers/gpu/drm/amd/display/dc/core/dc.c

4032

&seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/core/dc.c

4035

&seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

4079

struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps };

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1687

seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1688

seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1689

seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1690

seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1703

seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1704

seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1705

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1719

seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1720

seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1721

seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1722

seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1735

seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1736

seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1737

seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1751

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1752

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1753

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1754

seq_state->steps[*seq_state->num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1766

seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1767

seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1778

seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1779

seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1791

seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1792

seq_state->steps[*seq_state->num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1806

seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1807

seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1808

seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1809

seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1823

seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1824

seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1825

seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1826

seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1840

seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1841

seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1842

seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1843

seq_state->steps[*seq_state->num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1858

seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1859

seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1860

seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1861

seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1862

seq_state->steps[*seq_state->num_steps].func = MPC_SET_OUTPUT_CSC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1877

seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1878

seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1879

seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.color_space = colorspace;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1880

seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1881

seq_state->steps[*seq_state->num_steps].func = MPC_SET_OCSC_DEFAULT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1895

seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.ctx = ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1896

seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.cmd = cmd;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1897

seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.wait_type = wait_type;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1898

seq_state->steps[*seq_state->num_steps].func = DMUB_SEND_DMCUB_CMD;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1912

seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1913

seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.addr = addr;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1914

seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1915

seq_state->steps[*seq_state->num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1928

seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1929

seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1930

seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1942

seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1943

seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_PIPE_READ_START;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1955

seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1956

seq_state->steps[*seq_state->num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1970

seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1971

seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.context = context;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1972

seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1973

seq_state->steps[*seq_state->num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1986

seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1987

memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1988

seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1989

seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1990

seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1991

seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_COMBINE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2003

seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2004

seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2005

seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2031

seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2032

seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2033

seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2034

seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2035

seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2036

seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2037

seq_state->steps[*seq_state->num_steps].func = TG_PROGRAM_GLOBAL_SYNC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2050

seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2051

seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.state = state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2052

seq_state->steps[*seq_state->num_steps].func = TG_WAIT_FOR_STATE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2066

seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2067

seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2068

seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2069

seq_state->steps[*seq_state->num_steps].func = TG_SET_VTG_PARAMS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2081

seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2082

seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.start_line = start_line;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2083

seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.end_line = end_line;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2084

seq_state->steps[*seq_state->num_steps].func = OTG_SETUP_VERTICAL_INTERRUPT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2096

seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2097

seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2098

seq_state->steps[*seq_state->num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2110

seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2111

seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2112

seq_state->steps[*seq_state->num_steps].func = DPP_SET_HDR_MULTIPLIER;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2126

seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubbub = hubbub;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2127

seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubp_inst = hubp_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2128

seq_state->steps[*seq_state->num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2129

seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SIZE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2139

seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2140

seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2141

seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_MCACHE_ID;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2152

seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2153

seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2154

seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.wait = wait;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2155

seq_state->steps[*seq_state->num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2169

seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubbub = hubbub;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2170

seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubp_inst = hubp_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2171

seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.det_size = det_size;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2172

seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SEGMENTS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2187

seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2188

seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_space = color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2189

seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2190

seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.signal = signal;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2191

seq_state->steps[*seq_state->num_steps].func = OPP_SET_DYN_EXPANSION;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2205

seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2206

seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2207

seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.clamping = clamping;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2208

seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_FMT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2219

seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2220

seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2221

seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2222

seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2235

seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2236

seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2237

seq_state->steps[*seq_state->num_steps].func = ABM_SET_PIPE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2250

seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm = abm;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2251

seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm_level = abm_level;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2252

seq_state->steps[*seq_state->num_steps].func = ABM_SET_LEVEL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2264

seq_state->steps[*seq_state->num_steps].params.tg_enable_crtc_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2265

seq_state->steps[*seq_state->num_steps].func = TG_ENABLE_CRTC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2279

seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2280

seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2281

seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2282

seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FLIP_PENDING;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2296

seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2297

seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2298

seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2299

seq_state->steps[*seq_state->num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2308

seq_state->steps[*seq_state->num_steps].params.hubp_enable_3dlut_fl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2309

seq_state->steps[*seq_state->num_steps].func = HUBP_ENABLE_3DLUT_FL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3856

seq_state->steps[*seq_state->num_steps].func = DCCG_SET_DTO_DSCCLK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3857

seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3858

seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3859

seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3868

seq_state->steps[*seq_state->num_steps].func = DSC_CALCULATE_AND_SET_CONFIG;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3869

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3870

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3871

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3880

seq_state->steps[*seq_state->num_steps].func = MPC_REMOVE_MPCC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3881

seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3882

seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3883

seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3892

seq_state->steps[*seq_state->num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3893

seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3894

seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3895

seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3904

seq_state->steps[*seq_state->num_steps].func = HUBP_DISCONNECT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3905

seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3914

seq_state->steps[*seq_state->num_steps].func = DSC_ENABLE_WITH_OPP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3915

seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3924

seq_state->steps[*seq_state->num_steps].func = TG_SET_DSC_CONFIG;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3925

seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3926

seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3927

seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3936

seq_state->steps[*seq_state->num_steps].func = DSC_DISCONNECT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3937

seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3946

seq_state->steps[*seq_state->num_steps].func = DC_SET_OPTIMIZED_REQUIRED;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3947

seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3948

seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3957

seq_state->steps[*seq_state->num_steps].func = ABM_SET_IMMEDIATE_DISABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3958

seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3959

seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3976

seq_state->steps[*seq_state->num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3977

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3978

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3979

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3980

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3981

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3982

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3983

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.width = width;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3984

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.height = height;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3985

seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.offset = offset;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3999

seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_BLENDING;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4000

seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4001

seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4002

seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4020

seq_state->steps[*seq_state->num_steps].func = MPC_INSERT_PLANE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4021

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4022

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4023

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4024

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4025

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4026

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4027

seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4040

seq_state->steps[*seq_state->num_steps].func = MPC_ASSERT_IDLE_MPCC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4041

seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4042

seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4055

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4056

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4057

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.blank = blank;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4068

seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4069

seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4070

seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4071

seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4082

seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4083

seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4084

seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4085

seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4095

seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4096

seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4097

seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4107

seq_state->steps[*seq_state->num_steps].func = DWBC_UPDATE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4108

seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb = dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4109

seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb_params = dwb_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4120

seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_BUF;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4121

seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4122

seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4123

seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4133

seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_ARB;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4134

seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4135

seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4144

seq_state->steps[*seq_state->num_steps].func = MCIF_WB_ENABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4145

seq_state->steps[*seq_state->num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4154

seq_state->steps[*seq_state->num_steps].func = MCIF_WB_DISABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4155

seq_state->steps[*seq_state->num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4166

seq_state->steps[*seq_state->num_steps].func = MPC_SET_DWB_MUX;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4167

seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4168

seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4169

seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4179

seq_state->steps[*seq_state->num_steps].func = MPC_DISABLE_DWB_MUX;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4180

seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4181

seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4191

seq_state->steps[*seq_state->num_steps].func = DWBC_ENABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4192

seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb = dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4193

seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb_params = dwb_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4202

seq_state->steps[*seq_state->num_steps].func = DWBC_DISABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4203

seq_state->steps[*seq_state->num_steps].params.dwbc_disable_params.dwb = dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4213

seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4214

seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4215

seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.gsl = gsl;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4226

seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL_SOURCE_SELECT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4227

seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4228

seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4229

seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4240

seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_MALL_SEL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4241

seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4242

seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4243

seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4253

seq_state->steps[*seq_state->num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4254

seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4255

seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4265

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK_EN;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4266

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4267

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4277

seq_state->steps[*seq_state->num_steps].func = HUBP_DISABLE_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4278

seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4279

seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.disable = disable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4290

seq_state->steps[*seq_state->num_steps].func = HUBBUB_SOFT_RESET;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4291

seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub = hubbub;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4292

seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4293

seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.reset = reset;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4303

seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4304

seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4305

seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4316

seq_state->steps[*seq_state->num_steps].func = DPP_DPPCLK_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4317

seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4318

seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4319

seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4328

seq_state->steps[*seq_state->num_steps].func = DISABLE_PHANTOM_CRTC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4329

seq_state->steps[*seq_state->num_steps].params.disable_phantom_crtc_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4340

seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4341

seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4342

seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4343

seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4353

seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4354

seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4355

seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4365

seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4366

seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4367

seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4378

seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4379

seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4380

seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4381

seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4392

seq_state->steps[*seq_state->num_steps].func = DPP_ROOT_CLOCK_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4393

seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.hws = hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4394

seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4395

seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.clock_on = clock_on;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4406

seq_state->steps[*seq_state->num_steps].func = DPP_PG_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4407

seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.hws = hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4408

seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4409

seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.power_on = power_on;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4420

seq_state->steps[*seq_state->num_steps].func = HUBP_PG_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4421

seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hws = hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4422

seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4423

seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.power_on = power_on;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4432

seq_state->steps[*seq_state->num_steps].func = HUBP_INIT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4433

seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4442

seq_state->steps[*seq_state->num_steps].func = HUBP_RESET;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4443

seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4452

seq_state->steps[*seq_state->num_steps].func = DPP_RESET;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4453

seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4463

seq_state->steps[*seq_state->num_steps].func = OPP_PIPE_CLOCK_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4464

seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.opp = opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4465

seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4477

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4478

seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4479

seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4480

seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4481

seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4490

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_INT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4491

seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4502

seq_state->steps[*seq_state->num_steps].func = DCCG_UPDATE_DPP_DTO;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4503

seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4504

seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4505

seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4515

seq_state->steps[*seq_state->num_steps].func = HUBP_VTG_SEL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4516

seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4517

seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4529

seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP2;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4530

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4531

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4532

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.global_sync = global_sync;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4533

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4546

seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4547

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4548

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4549

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4550

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4551

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.pipe_dest = pipe_dest;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4561

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4562

seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4563

seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4573

seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT2;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4574

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4575

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4586

seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4587

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4588

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4589

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4605

seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4606

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4607

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.format = format;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4608

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4609

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.plane_size = plane_size;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4610

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.rotation = rotation;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4611

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4612

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4613

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.compat_level = compat_level;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4622

seq_state->steps[*seq_state->num_steps].func = DPP_SETUP_DPP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4623

seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4634

seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_MATRIX;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4635

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4636

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4637

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4647

seq_state->steps[*seq_state->num_steps].func = DPP_SET_SCALER;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4648

seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4649

seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4660

seq_state->steps[*seq_state->num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4661

seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4662

seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport = viewport;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4663

seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4673

seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4674

seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4675

seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4685

seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_ATTRIBUTE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4686

seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4687

seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4697

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4698

seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4699

seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.attributes = attributes;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4709

seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_ATTRIBUTES;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4710

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4711

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.attributes = attributes;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4721

seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_POSITION;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4722

seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4723

seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4733

seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4734

seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4735

seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4748

seq_state->steps[*seq_state->num_steps].func = PROGRAM_OUTPUT_CSC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4749

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4750

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4751

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.colorspace = colorspace;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4752

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.matrix = matrix;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4753

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.opp_id = opp_id;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4762

seq_state->steps[*seq_state->num_steps].func = PHANTOM_HUBP_POST_ENABLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4763

seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4773

seq_state->steps[*seq_state->num_steps].func = UPDATE_FORCE_PSTATE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4774

seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4775

seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.context = context;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4784

seq_state->steps[*seq_state->num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4785

seq_state->steps[*seq_state->num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4796

seq_state->steps[*seq_state->num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4797

seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4798

seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4799

seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4809

seq_state->steps[*seq_state->num_steps].func = TG_GET_FRAME_COUNT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4810

seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.tg = tg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4811

seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.frame_count = frame_count;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4821

seq_state->steps[*seq_state->num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4822

seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4823

seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4838

seq_state->steps[*seq_state->num_steps].func = HWSS_CURSOR_LOCK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4839

seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4840

seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4841

seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.lock = lock;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4851

seq_state->steps[*seq_state->num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4852

seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4853

seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = index;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4863

seq_state->steps[*seq_state->num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4864

seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4865

seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4875

seq_state->steps[*seq_state->num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4876

seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4877

seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4886

seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_HDMI_INFO_PACKETS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4887

seq_state->steps[*seq_state->num_steps].params.stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4896

seq_state->steps[*seq_state->num_steps].func = HPO_FRL_STREAM_ENC_UPDATE_HDMI_INFO_PACKETS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4897

seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4906

seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4907

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4916

seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4917

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4926

seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4927

seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4936

seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4937

seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4948

seq_state->steps[*seq_state->num_steps].func = DSC_SET_CONFIG_SIMPLE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4949

seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc = dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4950

seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_cfg = *dsc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4951

seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_optc_cfg = *dsc_optc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4961

seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_CONFIG;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4962

seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.stream_enc = stream_enc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4963

seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4975

seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4976

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc = hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4977

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4978

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4979

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4991

seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4992

seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc = stream_enc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4993

seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4994

seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4995

seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5006

seq_state->steps[*seq_state->num_steps].func = HPO_FRL_STREAM_ENC_SET_DSC_CONFIG;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5007

seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.hpo_frl_stream_enc = hpo_frl_stream_enc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5008

seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.timing = timing;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5009

seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.dsc_packed_pps = dsc_packed_pps;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5019

seq_state->steps[*seq_state->num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5020

seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5021

seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5031

seq_state->steps[*seq_state->num_steps].func = DP_TRACE_SOURCE_SEQUENCE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5032

seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.link = link;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5033

seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.source = source;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5043

&seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.attr;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5052

seq_state->steps[*seq_state->num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5053

seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.hubp =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5064

seq_state->steps[*seq_state->num_steps].func = LINK_INCREASE_MST_PAYLOAD;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5065

seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5066

seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.mst_stream_bw = mst_stream_bw;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5076

seq_state->steps[*seq_state->num_steps].func = LINK_REDUCE_MST_PAYLOAD;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5077

seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5078

seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.mst_stream_bw = mst_stream_bw;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5092

seq_state->steps[*seq_state->num_steps].func = DP_SET_TEST_PATTERN;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5093

seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.link = link;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5094

seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern = test_pattern;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5095

seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern_color_space = test_pattern_color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5096

seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_link_settings = p_link_settings;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5097

seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_custom_pattern = p_custom_pattern;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5098

seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.cust_pattern_size = cust_pattern_size;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5107

seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_OFF;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5108

seq_state->steps[*seq_state->num_steps].params.link_set_dpms_off_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5117

seq_state->steps[*seq_state->num_steps].func = DISABLE_AUDIO_STREAM;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5118

seq_state->steps[*seq_state->num_steps].params.disable_audio_stream_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5128

seq_state->steps[*seq_state->num_steps].func = PREPARE_BANDWIDTH;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5129

seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5130

seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.context = context;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5140

seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_ON;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5141

seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.state = state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5142

seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1765

&seq_state->steps[last_dsc_calc].params.dsc_calculate_and_set_config_params.dsc_optc_cfg, true);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1222

struct block_sequence *steps;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

341

#define BEND_IDX(steps) ((50 + (steps)) / 5)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

373

static void lpt_bend_clkout_dp(struct intel_display *display, int steps)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

376

int idx = BEND_IDX(steps);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

378

if (drm_WARN_ON(display->drm, steps % 5 != 0))

drivers/gpu/drm/i915/display/intel_pch_refclk.c

386

if (steps % 10 != 0)

drivers/gpu/drm/radeon/rv770_dpm.c

1237

u32 steps = 0;

drivers/gpu/drm/radeon/rv770_dpm.c

1245

steps = (max - min) / step + 1;

drivers/gpu/drm/radeon/rv770_dpm.c

1247

if (steps > MAX_NO_VREG_STEPS)

drivers/gpu/drm/radeon/rv770_dpm.c

1250

for (i = 0; i < steps; i++) {

drivers/gpu/drm/radeon/rv770_dpm.c

1271

pi->valid_vddc_entries = (u8)steps;

drivers/iio/accel/mma8452.c

892

int ret, reg, steps;

drivers/iio/accel/mma8452.c

911

steps = (val * USEC_PER_SEC + val2) /

drivers/iio/accel/mma8452.c

915

if (steps < 0 || steps > 0xff)

drivers/iio/accel/mma8452.c

918

return mma8452_change_config(data, ev_regs->ev_count, steps);

drivers/iio/adc/ti_am335x_adc.c

110

int i, steps = 0;

drivers/iio/adc/ti_am335x_adc.c

135

tiadc_writel(adc_dev, REG_STEPCONFIG(steps),

drivers/iio/adc/ti_am335x_adc.c

140

tiadc_writel(adc_dev, REG_STEPDELAY(steps),

drivers/iio/adc/ti_am335x_adc.c

144

adc_dev->channel_step[i] = steps;

drivers/iio/adc/ti_am335x_adc.c

145

steps++;

drivers/iio/dummy/iio_simple_dummy.c

311

*val = st->steps;

drivers/iio/dummy/iio_simple_dummy.c

466

st->steps = val;

drivers/iio/dummy/iio_simple_dummy.c

561

st->steps = 47;

drivers/iio/dummy/iio_simple_dummy.h

40

int steps;

drivers/input/keyboard/lm8323.c

443

int div512, perstep, steps, hz, up, kill;

drivers/input/keyboard/lm8323.c

460

steps = abs(pwm->desired_brightness - pwm->brightness);

drivers/input/keyboard/lm8323.c

466

if ((pwm->fade_time / steps) > (32768 / 512)) {

drivers/input/keyboard/lm8323.c

474

perstep = (hz * pwm->fade_time) / (steps * 1000);

drivers/input/keyboard/lm8323.c

481

while (steps) {

drivers/input/keyboard/lm8323.c

484

s = min(126, steps);

drivers/input/keyboard/lm8323.c

486

steps -= s;

drivers/input/misc/max7360-rotary.c

129

&max7360_rotary->steps);

drivers/input/misc/max7360-rotary.c

131

max7360_rotary->steps = MAX7360_ROTARY_DEFAULT_STEPS;

drivers/input/misc/max7360-rotary.c

151

input_set_abs_params(input, max7360_rotary->axis, 0, max7360_rotary->steps, 0, 1);

drivers/input/misc/max7360-rotary.c

30

u32 steps;

drivers/input/misc/max7360-rotary.c

36

static void max7360_rotary_report_event(struct max7360_rotary *max7360_rotary, int steps)

drivers/input/misc/max7360-rotary.c

39

input_report_rel(max7360_rotary->input, max7360_rotary->axis, steps);

drivers/input/misc/max7360-rotary.c

42

int maxval = max7360_rotary->steps;

drivers/input/misc/max7360-rotary.c

50

pos += steps % maxval;

drivers/input/misc/rotary_encoder.c

194

device_property_read_u32(dev, "rotary-encoder,steps", &encoder->steps);

drivers/input/misc/rotary_encoder.c

252

encoder->axis, 0, encoder->steps, 0, 1);

drivers/input/misc/rotary_encoder.c

38

u32 steps;

drivers/input/misc/rotary_encoder.c

85

pos += encoder->steps;

drivers/input/misc/rotary_encoder.c

90

if (encoder->rollover || pos < encoder->steps)

drivers/input/misc/rotary_encoder.c

95

pos %= encoder->steps;

drivers/input/touchscreen/ti_am335x_tsc.c

500

u32 steps;

drivers/input/touchscreen/ti_am335x_tsc.c

507

steps = 2 * ts_dev->coordinate_readouts + 2;

drivers/input/touchscreen/ti_am335x_tsc.c

508

steps = (1 << steps) - 1;

drivers/input/touchscreen/ti_am335x_tsc.c

509

am335x_tsc_se_clr(ts_dev->mfd_tscadc, steps);

drivers/media/dvb-frontends/dib0090.c

1738

if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {

drivers/media/dvb-frontends/sp887x.c

441

int steps = (sync0x200 >> 4) & 0x00f;

drivers/media/dvb-frontends/sp887x.c

442

if (steps & 0x008)

drivers/media/dvb-frontends/sp887x.c

443

steps = -steps;

drivers/media/dvb-frontends/sp887x.c

445

steps);

drivers/media/dvb-frontends/stb0899_algo.c

1004

STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);

drivers/media/dvb-frontends/stb0899_algo.c

970

s32 steps, step_size;

drivers/media/dvb-frontends/stb0899_algo.c

991

steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));

drivers/media/dvb-frontends/stb0899_algo.c

992

steps = (steps + 6) / 10;

drivers/media/dvb-frontends/stb0899_algo.c

993

steps = (steps == 0) ? 1 : steps;

drivers/media/dvb-frontends/stb0899_algo.c

994

if (steps % 2 == 0)

drivers/media/dvb-frontends/stv0900_sw.c

117

*steps = max_steps;

drivers/media/dvb-frontends/stv0900_sw.c

56

s32 *steps,

drivers/media/dvb-frontends/stv090x.c

1593

s32 i, j, steps, dir;

drivers/media/dvb-frontends/stv090x.c

1616

steps = state->search_range / 1000000;

drivers/media/dvb-frontends/stv090x.c

1617

if (steps <= 0)

drivers/media/dvb-frontends/stv090x.c

1618

steps = 1;

drivers/media/dvb-frontends/stv090x.c

1624

for (i = 0; i < steps; i++) {

drivers/media/dvb-frontends/stv090x.c

1688

s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;

drivers/media/dvb-frontends/stv090x.c

1750

steps = -1 + ((state->search_range / 1000) / car_step);

drivers/media/dvb-frontends/stv090x.c

1751

steps /= 2;

drivers/media/dvb-frontends/stv090x.c

1752

steps = (2 * steps) + 1;

drivers/media/dvb-frontends/stv090x.c

1753

if (steps < 0)

drivers/media/dvb-frontends/stv090x.c

1754

steps = 1;

drivers/media/dvb-frontends/stv090x.c

1755

else if (steps > 10) {

drivers/media/dvb-frontends/stv090x.c

1756

steps = 11;

drivers/media/dvb-frontends/stv090x.c

1763

while ((!tmg_lock) && (cur_step < steps)) {

drivers/media/dvb-frontends/stv090x.c

1792

else if (cur_step < steps) {

drivers/media/dvb-frontends/stv090x.c

2137

s32 car_step, steps, cur_step, dir, freq, timeout_lock;

drivers/media/dvb-frontends/stv090x.c

2169

steps = (state->search_range / 1000) / car_step;

drivers/media/dvb-frontends/stv090x.c

2170

steps /= 2;

drivers/media/dvb-frontends/stv090x.c

2171

steps = 2 * (steps + 1);

drivers/media/dvb-frontends/stv090x.c

2172

if (steps < 0)

drivers/media/dvb-frontends/stv090x.c

2173

steps = 2;

drivers/media/dvb-frontends/stv090x.c

2174

else if (steps > 12)

drivers/media/dvb-frontends/stv090x.c

2175

steps = 12;

drivers/media/dvb-frontends/stv090x.c

2182

while ((cur_step <= steps) && (!lock)) {

drivers/media/dvb-frontends/stv090x.c

2246

static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)

drivers/media/dvb-frontends/stv090x.c

2301

*steps = steps_max;

drivers/media/i2c/ov08x40.c

1858

u64 steps;

drivers/media/i2c/ov08x40.c

1894

steps = mode->exposure_shift == 1 ? 4 : 1;

drivers/media/i2c/ov08x40.c

1899

steps,

drivers/media/i2c/s5c73m3/s5c73m3-core.c

462

unsigned int delay, unsigned int steps)

drivers/media/i2c/s5c73m3/s5c73m3-core.c

466

while (steps-- > 0) {

drivers/media/platform/renesas/rcar-csi2.c

1662

struct phtw_value steps[] = {

drivers/media/platform/renesas/rcar-csi2.c

1674

steps[1].data = (info->osc_freq & 0x00ff) >> 0;

drivers/media/platform/renesas/rcar-csi2.c

1675

steps[2].data = (info->osc_freq & 0x0f00) >> 8;

drivers/media/platform/renesas/rcar-csi2.c

1677

return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps));

drivers/media/usb/gspca/autogain_functions.c

103

int steps, retval = 0;

drivers/media/usb/gspca/autogain_functions.c

118

steps = (desired_avg_lum - avg_lum) / deadzone;

drivers/media/usb/gspca/autogain_functions.c

121

avg_lum, desired_avg_lum, steps);

drivers/media/usb/gspca/autogain_functions.c

123

if ((gain + steps) > gain_high &&

drivers/media/usb/gspca/autogain_functions.c

128

} else if ((gain + steps) < gain_low &&

drivers/media/usb/gspca/autogain_functions.c

134

gain += steps;

drivers/media/usb/gspca/autogain_functions.c

23

int i, steps, retval = 0;

drivers/media/usb/gspca/autogain_functions.c

33

steps = abs(desired_avg_lum - avg_lum) / deadzone;

drivers/media/usb/gspca/autogain_functions.c

36

avg_lum, desired_avg_lum, steps);

drivers/media/usb/gspca/autogain_functions.c

38

for (i = 0; i < steps; i++) {

drivers/mtd/nand/ecc-mxic.c

104

int steps;

drivers/mtd/nand/ecc-mxic.c

140

if (section < 0 || section >= ctx->steps)

drivers/mtd/nand/ecc-mxic.c

155

if (section < 0 || section >= ctx->steps)

drivers/mtd/nand/ecc-mxic.c

226

int step_size = 0, strength = 0, desired_correction = 0, steps, idx;

drivers/mtd/nand/ecc-mxic.c

261

steps = mtd->writesize / step_size;

drivers/mtd/nand/ecc-mxic.c

262

desired_correction = steps * strength;

drivers/mtd/nand/ecc-mxic.c

267

steps = mtd->writesize / conf->step_size;

drivers/mtd/nand/ecc-mxic.c

269

ctx->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);

drivers/mtd/nand/ecc-mxic.c

274

strength = desired_correction / steps;

drivers/mtd/nand/ecc-mxic.c

289

if (spare_size[idx] * steps <= mtd->oobsize)

drivers/mtd/nand/ecc-mxic.c

302

ctx->steps = steps;

drivers/mtd/nand/ecc-mxic.c

303

ctx->data_step_sz = mtd->writesize / steps;

drivers/mtd/nand/ecc-mxic.c

304

ctx->oob_step_sz = mtd->oobsize / steps;

drivers/mtd/nand/ecc-mxic.c

310

(ctx->steps * STAT_BYTES);

drivers/mtd/nand/ecc-mxic.c

315

ctx->oobwithstat = kmalloc(mtd->oobsize + (ctx->steps * STAT_BYTES),

drivers/mtd/nand/ecc-mxic.c

400

writel(ctx->steps, mxic->regs + CHUNK_CNT);

drivers/mtd/nand/ecc-mxic.c

487

for (step = 0; step < ctx->steps; step++) {

drivers/mtd/nand/ecc-mxic.c

501

for (step = 0; step < ctx->steps; step++)

drivers/mtd/nand/ecc-mxic.c

513

for (step = 0; step < ctx->steps; step++)

drivers/mtd/nand/ecc-mxic.c

529

for (step = 0; step < ctx->steps; step++) {

drivers/mtd/nand/ecc-mxic.c

574

req->ooblen + (ctx->steps * STAT_BYTES));

drivers/mtd/nand/ecc-mxic.c

582

for (step = 0; step < ctx->steps; step++) {

drivers/mtd/nand/ecc-mxic.c

600

for (step = 0; step < ctx->steps; step++) {

drivers/mtd/nand/ecc-mxic.c

632

req->ooblen + (ctx->steps * STAT_BYTES));

drivers/mtd/nand/ecc-mxic.c

639

for (step = 0; step < ctx->steps; step++) {

drivers/mtd/nand/ecc-mxic.c

686

req->ooblen + (ctx->steps * STAT_BYTES));

drivers/mtd/nand/ecc-realtek.c

119

if (section < 0 || section >= ctx->steps)

drivers/mtd/nand/ecc-realtek.c

122

oobregion->offset = ctx->steps * RTL_ECC_FREE_SIZE + section * ctx->parity_size;

drivers/mtd/nand/ecc-realtek.c

135

if (section < 0 || section >= ctx->steps)

drivers/mtd/nand/ecc-realtek.c

241

parity = req->oobbuf.in + ctx->steps * RTL_ECC_FREE_SIZE;

drivers/mtd/nand/ecc-realtek.c

243

for (int i = 0; i < ctx->steps; i++) {

drivers/mtd/nand/ecc-realtek.c

276

parity = req->oobbuf.in + ctx->steps * RTL_ECC_FREE_SIZE;

drivers/mtd/nand/ecc-realtek.c

278

for (int i = 0 ; i < ctx->steps; i++) {

drivers/mtd/nand/ecc-realtek.c

361

ctx->steps = mtd->writesize / RTL_ECC_BLOCK_SIZE;

drivers/mtd/nand/ecc-realtek.c

371

conf->strength, ctx->steps, conf->step_size,

drivers/mtd/nand/ecc-realtek.c

372

ctx->steps, ctx->steps, ctx->parity_size);

drivers/mtd/nand/ecc-realtek.c

89

int steps;

drivers/mtd/nand/raw/arasan-nand-controller.c

1166

ecc->steps = mtd->writesize / ecc->size;

drivers/mtd/nand/raw/arasan-nand-controller.c

1170

anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);

drivers/mtd/nand/raw/arasan-nand-controller.c

142

int steps;

drivers/mtd/nand/raw/arasan-nand-controller.c

281

static int anfc_pkt_len_config(unsigned int len, unsigned int *steps,

drivers/mtd/nand/raw/arasan-nand-controller.c

295

if (steps)

drivers/mtd/nand/raw/arasan-nand-controller.c

296

*steps = nb;

drivers/mtd/nand/raw/arasan-nand-controller.c

405

PKT_STEPS(chip->ecc.steps),

drivers/mtd/nand/raw/arasan-nand-controller.c

452

for (step = 0; step < chip->ecc.steps; step++) {

drivers/mtd/nand/raw/arasan-nand-controller.c

523

PKT_STEPS(chip->ecc.steps),

drivers/mtd/nand/raw/arasan-nand-controller.c

649

ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps,

drivers/mtd/nand/raw/arasan-nand-controller.c

669

PKT_STEPS(nfc_op->steps);

drivers/mtd/nand/raw/arasan-nand-controller.c

682

unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;

drivers/mtd/nand/raw/arasan-nand-controller.c

688

for (i = 0; i < nfc_op->steps; i++) {

drivers/mtd/nand/raw/atmel/nand-controller.c

840

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/atmel/nand-controller.c

876

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/brcmnand/brcmnand.c

2164

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/cadence-nand-controller.c

1569

int ecc_steps = chip->ecc.steps;

drivers/mtd/nand/raw/cadence-nand-controller.c

1762

int ecc_steps = chip->ecc.steps;

drivers/mtd/nand/raw/denali.c

214

iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS);

drivers/mtd/nand/raw/denali.c

251

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/denali.c

296

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/denali.c

299

if (i == ecc->steps - 1)

drivers/mtd/nand/raw/denali.c

417

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/denali.c

456

*uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);

drivers/mtd/nand/raw/fsl_elbc_nand.c

103

if (section < chip->ecc.steps)

drivers/mtd/nand/raw/fsl_elbc_nand.c

74

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/fsl_elbc_nand.c

803

chip->ecc.steps);

drivers/mtd/nand/raw/fsl_elbc_nand.c

92

if (section > chip->ecc.steps)

drivers/mtd/nand/raw/fsl_ifc_nand.c

215

int sector_start = bufnum * chip->ecc.steps;

drivers/mtd/nand/raw/fsl_ifc_nand.c

216

int sector_end = sector_start + chip->ecc.steps - 1;

drivers/mtd/nand/raw/fsl_ifc_nand.c

651

for (i = 0; i < chip->ecc.steps; ++i) {

drivers/mtd/nand/raw/fsl_ifc_nand.c

762

chip->ecc.steps);

drivers/mtd/nand/raw/fsmc_nand.c

172

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/fsmc_nand.c

186

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/fsmc_nand.c

191

if (section < chip->ecc.steps - 1)

drivers/mtd/nand/raw/fsmc_nand.c

215

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/fsmc_nand.c

233

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/fsmc_nand.c

238

if (section < chip->ecc.steps - 1)

drivers/mtd/nand/raw/fsmc_nand.c

713

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/lpc32xx_mlc.c

134

if (section >= nand_chip->ecc.steps)

drivers/mtd/nand/raw/lpc32xx_mlc.c

148

if (section >= nand_chip->ecc.steps)

drivers/mtd/nand/raw/lpc32xx_slc.c

537

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/lpc32xx_slc.c

541

mtd->writesize / chip->ecc.steps, dir);

drivers/mtd/nand/raw/lpc32xx_slc.c

546

if (i == chip->ecc.steps - 1)

drivers/mtd/nand/raw/lpc32xx_slc.c

578

host->ecc_buf[chip->ecc.steps - 1] =

drivers/mtd/nand/raw/lpc32xx_slc.c

621

status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);

drivers/mtd/nand/raw/lpc32xx_slc.c

627

lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);

drivers/mtd/nand/raw/lpc32xx_slc.c

636

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/lpc32xx_slc.c

665

chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps);

drivers/mtd/nand/raw/lpc32xx_slc.c

688

error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);

drivers/mtd/nand/raw/lpc32xx_slc.c

701

lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);

drivers/mtd/nand/raw/lpc32xx_slc.c

721

chip->ecc.size * chip->ecc.steps);

drivers/mtd/nand/raw/marvell_nand.c

2292

ecc->steps = l->nchunks;

drivers/mtd/nand/raw/meson_nand.c

1101

if (section >= nand->ecc.steps)

drivers/mtd/nand/raw/meson_nand.c

1115

if (section >= nand->ecc.steps)

drivers/mtd/nand/raw/meson_nand.c

421

for (i = 0; i < nand->ecc.steps; i++) {

drivers/mtd/nand/raw/meson_nand.c

440

for (i = 0; i < nand->ecc.steps; i++) {

drivers/mtd/nand/raw/meson_nand.c

540

for (i = 0, count = 0; i < nand->ecc.steps; i++, count += (2 + nand->ecc.bytes)) {

drivers/mtd/nand/raw/meson_nand.c

553

for (i = 0, count = 0; i < nand->ecc.steps; i++, count += (2 + nand->ecc.bytes)) {

drivers/mtd/nand/raw/meson_nand.c

568

for (i = 0; i < nand->ecc.steps; i++) {

drivers/mtd/nand/raw/meson_nand.c

760

info_len = nand->ecc.steps * PER_INFO_BYTE;

drivers/mtd/nand/raw/meson_nand.c

801

memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);

drivers/mtd/nand/raw/meson_nand.c

815

neccpages = raw ? 1 : nand->ecc.steps;

drivers/mtd/nand/raw/meson_nand.c

839

info_len = nand->ecc.steps * PER_INFO_BYTE;

drivers/mtd/nand/raw/meson_nand.c

906

for (i = 0; i < nand->ecc.steps ; i++) {

drivers/mtd/nand/raw/mtk_nand.c

1068

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/mtk_nand.c

686

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/mtk_nand.c

716

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/mtk_nand.c

757

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/mtk_nand.c

793

nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);

drivers/mtd/nand/raw/mtk_nand.c

812

ADDRCNTR_SEC(reg) >= chip->ecc.steps,

drivers/mtd/nand/raw/mxc_nand.c

894

if (section >= nand_chip->ecc.steps)

drivers/mtd/nand/raw/mxc_nand.c

908

if (section > nand_chip->ecc.steps)

drivers/mtd/nand/raw/mxc_nand.c

921

if (section < nand_chip->ecc.steps)

drivers/mtd/nand/raw/mxc_nand.c

942

if (section >= nand_chip->ecc.steps)

drivers/mtd/nand/raw/mxc_nand.c

957

if (section >= nand_chip->ecc.steps)

drivers/mtd/nand/raw/nand_base.c

2889

int steps, size, ret;

drivers/mtd/nand/raw/nand_base.c

2895

for (steps = chip->ecc.steps; steps > 0; steps--) {

drivers/mtd/nand/raw/nand_base.c

2950

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

2966

eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

3109

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

3139

eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

3182

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

3248

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

3656

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/nand_base.c

3716

int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

3725

pos = steps * (eccsize + chunk);

drivers/mtd/nand/raw/nand_base.c

3726

steps = 0;

drivers/mtd/nand/raw/nand_base.c

3734

for (i = 0; i < steps; i++) {

drivers/mtd/nand/raw/nand_base.c

4000

int steps, size, ret;

drivers/mtd/nand/raw/nand_base.c

4006

for (steps = chip->ecc.steps; steps > 0; steps--) {

drivers/mtd/nand/raw/nand_base.c

4060

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

4089

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

4138

int ecc_steps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

4206

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/nand_base.c

5665

chip->ecc.steps = nanddev_get_ecc_nsteps(base);

drivers/mtd/nand/raw/nand_base.c

5719

chip->ecc.steps = nanddev_get_ecc_nsteps(base);

drivers/mtd/nand/raw/nand_base.c

6348

if (!ecc->steps)

drivers/mtd/nand/raw/nand_base.c

6349

ecc->steps = mtd->writesize / ecc->size;

drivers/mtd/nand/raw/nand_base.c

6351

base->ecc.ctx.nsteps = ecc->steps;

drivers/mtd/nand/raw/nand_base.c

6358

if (ecc->steps * ecc->size != mtd->writesize)

drivers/mtd/nand/raw/nand_base.c

6362

ecc->total = ecc->steps * ecc->bytes;

drivers/mtd/nand/raw/nand_base.c

6391

switch (ecc->steps) {

drivers/mtd/nand/raw/nand_micron.c

247

for (step = 0; step < chip->ecc.steps; step++) {

drivers/mtd/nand/raw/nand_toshiba.c

40

NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0),

drivers/mtd/nand/raw/nand_toshiba.c

62

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

254

chip->ecc.steps = mtd->writesize / chip->ecc.size;

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

255

nvtnand->eccstatus = (chip->ecc.steps < 4) ? 1 : chip->ecc.steps / 4;

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

260

chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH8;

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

264

chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH12;

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

268

chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH24;

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

276

chip->ecc.bytes = chip->ecc.total / chip->ecc.steps;

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

376

(parity_len * chip->ecc.steps) +

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

576

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/omap2.c

2062

chip->ecc.steps = mtd->writesize / chip->ecc.size;

drivers/mtd/nand/raw/omap2.c

2063

info->neccpg = chip->ecc.steps / ERROR_VECTOR_MAX;

drivers/mtd/nand/raw/omap2.c

2068

info->nsteps_per_eccpg = chip->ecc.steps;

drivers/mtd/nand/raw/omap2.c

932

nsectors = chip->ecc.steps;

drivers/mtd/nand/raw/omap2.c

952

nsectors = chip->ecc.steps;

drivers/mtd/nand/raw/omap2.c

965

nsectors = chip->ecc.steps;

drivers/mtd/nand/raw/pl35x-nand-controller.c

162

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/pl35x-nand-controller.c

176

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/pl35x-nand-controller.c

454

for (chunk = 0; chunk < chip->ecc.steps;

drivers/mtd/nand/raw/pl35x-nand-controller.c

476

for (chunk = 0; chunk < chip->ecc.steps;

drivers/mtd/nand/raw/pl35x-nand-controller.c

914

chip->ecc.steps = mtd->writesize / chip->ecc.size;

drivers/mtd/nand/raw/pl35x-nand-controller.c

920

nfc->ecc_buf = devm_kmalloc(nfc->dev, chip->ecc.bytes * chip->ecc.steps,

drivers/mtd/nand/raw/qcom_nandc.c

1000

oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +

drivers/mtd/nand/raw/qcom_nandc.c

1008

i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);

drivers/mtd/nand/raw/qcom_nandc.c

1062

update_rw_regs(host, ecc->steps, false, 0);

drivers/mtd/nand/raw/qcom_nandc.c

1065

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/qcom_nandc.c

1069

data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

1074

((ecc->steps - 1) << 2);

drivers/mtd/nand/raw/qcom_nandc.c

1075

oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +

drivers/mtd/nand/raw/qcom_nandc.c

1136

data_size = ecc->size - ((ecc->steps - 1) << 2);

drivers/mtd/nand/raw/qcom_nandc.c

1144

set_address(host, host->cw_size * (ecc->steps - 1), page);

drivers/mtd/nand/raw/qcom_nandc.c

1189

bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

1220

set_address(host, host->cw_size * (ecc->steps - 1), page);

drivers/mtd/nand/raw/qcom_nandc.c

1221

update_rw_regs(host, 1, false, ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

1333

oobregion->length = (ecc->bytes * (ecc->steps - 1)) +

drivers/mtd/nand/raw/qcom_nandc.c

1354

oobregion->length = ecc->steps * 4;

drivers/mtd/nand/raw/qcom_nandc.c

1355

oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size;

drivers/mtd/nand/raw/qcom_nandc.c

149

return cw == (ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

1707

num_cw = nandc->exec_opwrite ? ecc->steps : 1;

drivers/mtd/nand/raw/qcom_nandc.c

489

raw_cw = ecc->steps - 1;

drivers/mtd/nand/raw/qcom_nandc.c

496

data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

501

((ecc->steps - 1) * 4);

drivers/mtd/nand/raw/qcom_nandc.c

502

oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +

drivers/mtd/nand/raw/qcom_nandc.c

578

for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {

drivers/mtd/nand/raw/qcom_nandc.c

580

data_size = ecc->size - ((ecc->steps - 1) * 4);

drivers/mtd/nand/raw/qcom_nandc.c

581

oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;

drivers/mtd/nand/raw/qcom_nandc.c

635

for (i = 0; i < ecc->steps; i++, buf++) {

drivers/mtd/nand/raw/qcom_nandc.c

640

data_len = ecc->size - ((ecc->steps - 1) << 2);

drivers/mtd/nand/raw/qcom_nandc.c

641

oob_len = ecc->steps << 2;

drivers/mtd/nand/raw/qcom_nandc.c

734

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/qcom_nandc.c

738

data_size = ecc->size - ((ecc->steps - 1) << 2);

drivers/mtd/nand/raw/qcom_nandc.c

739

oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +

drivers/mtd/nand/raw/qcom_nandc.c

816

set_address(host, host->cw_size * (ecc->steps - 1), page);

drivers/mtd/nand/raw/qcom_nandc.c

817

update_rw_regs(host, 1, true, ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

819

config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);

drivers/mtd/nand/raw/qcom_nandc.c

911

update_rw_regs(host, ecc->steps, true, 0);

drivers/mtd/nand/raw/qcom_nandc.c

934

for (cw = 0; cw < ecc->steps; cw++) {

drivers/mtd/nand/raw/qcom_nandc.c

962

update_rw_regs(host, ecc->steps, true, 0);

drivers/mtd/nand/raw/qcom_nandc.c

992

update_rw_regs(host, ecc->steps, false, 0);

drivers/mtd/nand/raw/qcom_nandc.c

995

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/qcom_nandc.c

999

data_size = ecc->size - ((ecc->steps - 1) << 2);

drivers/mtd/nand/raw/renesas-nand-controller.c

1072

chip->ecc.steps = mtd->writesize / chip->ecc.size;

drivers/mtd/nand/raw/renesas-nand-controller.c

458

for (i = 0; i < chip->ecc.steps; i++) {

drivers/mtd/nand/raw/renesas-nand-controller.c

982

unsigned int eccbytes = round_up(chip->ecc.bytes, 4) * chip->ecc.steps;

drivers/mtd/nand/raw/renesas-nand-controller.c

997

unsigned int eccbytes = round_up(chip->ecc.bytes, 4) * chip->ecc.steps;

drivers/mtd/nand/raw/rockchip-nand-controller.c

1005

max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 /

drivers/mtd/nand/raw/rockchip-nand-controller.c

1022

ecc->steps = mtd->writesize / ecc->size;

drivers/mtd/nand/raw/rockchip-nand-controller.c

1051

rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps;

drivers/mtd/nand/raw/rockchip-nand-controller.c

1071

new_oob_len = ecc->steps * NFC_MAX_OOB_PER_STEP;

drivers/mtd/nand/raw/rockchip-nand-controller.c

529

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/rockchip-nand-controller.c

571

rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),

drivers/mtd/nand/raw/rockchip-nand-controller.c

643

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/rockchip-nand-controller.c

645

oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;

drivers/mtd/nand/raw/rockchip-nand-controller.c

663

ecc->steps * oob_step,

drivers/mtd/nand/raw/rockchip-nand-controller.c

673

rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data,

drivers/mtd/nand/raw/rockchip-nand-controller.c

688

dma_unmap_single(nfc->dev, dma_oob, ecc->steps * oob_step,

drivers/mtd/nand/raw/rockchip-nand-controller.c

729

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/rockchip-nand-controller.c

738

memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),

drivers/mtd/nand/raw/rockchip-nand-controller.c

786

ecc->steps * oob_step,

drivers/mtd/nand/raw/rockchip-nand-controller.c

808

rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data,

drivers/mtd/nand/raw/rockchip-nand-controller.c

823

dma_unmap_single(nfc->dev, dma_oob, ecc->steps * oob_step,

drivers/mtd/nand/raw/rockchip-nand-controller.c

832

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/rockchip-nand-controller.c

834

oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;

drivers/mtd/nand/raw/rockchip-nand-controller.c

849

for (i = 0; i < (ecc->steps / 2); i++) {

drivers/mtd/nand/raw/rockchip-nand-controller.c

999

ecc->steps = mtd->writesize / ecc->size;

drivers/mtd/nand/raw/sh_flctl.c

67

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/sh_flctl.c

81

if (section >= chip->ecc.steps)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

1051

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/stm32_fmc2_nand.c

701

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/stm32_fmc2_nand.c

810

cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);

drivers/mtd/nand/raw/stm32_fmc2_nand.c

863

int eccsteps = chip->ecc.steps;

drivers/mtd/nand/raw/sunxi_nand.c

1150

int offset = sunxi_get_oob_offset(sunxi_nand, ecc, ecc->steps);

drivers/mtd/nand/raw/sunxi_nand.c

1360

int offset = sunxi_get_oob_offset(sunxi_nand, ecc, ecc->steps);

drivers/mtd/nand/raw/sunxi_nand.c

1394

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/sunxi_nand.c

1429

nand->ecc.steps);

drivers/mtd/nand/raw/sunxi_nand.c

1513

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/sunxi_nand.c

1590

ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,

drivers/mtd/nand/raw/sunxi_nand.c

1596

for (i = 0; i < ecc->steps; i++) {

drivers/mtd/nand/raw/sunxi_nand.c

1868

if (section >= ecc->steps)

drivers/mtd/nand/raw/sunxi_nand.c

1889

if (section >= ecc->steps)

drivers/mtd/nand/raw/tegra_nand.c

214

oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);

drivers/mtd/nand/raw/tegra_nand.c

241

oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);

drivers/mtd/nand/raw/tegra_nand.c

710

if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) {

drivers/mtd/nand/raw/tegra_nand.c

726

for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) {

drivers/mtd/nand/raw/tegra_nand.c

870

bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4);

drivers/mtd/nand/raw/tegra_nand.c

929

chip->ecc.steps = mtd->writesize / chip->ecc.size;

drivers/phy/xilinx/phy-zynqmp.c

193

u32 steps;

drivers/phy/xilinx/phy-zynqmp.c

462

STEPS_0_MASK, ssc->steps & STEPS_0_MASK);

drivers/phy/xilinx/phy-zynqmp.c

467

(ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);

drivers/pmdomain/qcom/cpr.c

825

int step_size_uV, steps, uV;

drivers/pmdomain/qcom/cpr.c

833

steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);

drivers/pmdomain/qcom/cpr.c

836

steps = -steps;

drivers/pmdomain/qcom/cpr.c

840

uV = fdata->ref_uV + steps * step_size_uV;

drivers/rtc/rtc-rs5c372.c

591

long steps = LONG_MIN;

drivers/rtc/rtc-rs5c372.c

608

steps = DIV_ROUND_CLOSEST(offset, 1017);

drivers/rtc/rtc-rs5c372.c

609

if (steps >= -0x3E && steps <= 0x3E) {

drivers/rtc/rtc-rs5c372.c

619

steps = LONG_MIN;

drivers/rtc/rtc-rs5c372.c

626

if (steps == LONG_MIN) {

drivers/rtc/rtc-rs5c372.c

627

steps = DIV_ROUND_CLOSEST(offset, ppb_per_step);

drivers/rtc/rtc-rs5c372.c

628

if (steps > 0x3E || steps < -0x3E)

drivers/rtc/rtc-rs5c372.c

632

if (steps > 0) {

drivers/rtc/rtc-rs5c372.c

633

val |= steps + 1;

drivers/rtc/rtc-rs5c372.c

636

val |= (~(-steps - 1)) & 0x3F;

drivers/rtc/rtc-rs5c372.c

639

if (!steps || !(val & 0x3E)) {

drivers/rtc/rtc-rv3028.c

472

int ret, value, steps;

drivers/rtc/rtc-rv3028.c

478

steps = sign_extend32(value << 1, 8);

drivers/rtc/rtc-rv3028.c

484

steps += value >> 7;

drivers/rtc/rtc-rv3028.c

486

*offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);

drivers/rtc/rtc-rv3032.c

373

int ret, value, steps;

drivers/rtc/rtc-rv3032.c

379

steps = FIELD_GET_SIGNED(RV3032_OFFSET_MSK, value);

drivers/rtc/rtc-rv3032.c

381

*offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);

drivers/rtc/rtc-rzn1.c

316

int stepsh, stepsl, steps;

drivers/rtc/rtc-rzn1.c

332

steps = stepsh;

drivers/rtc/rtc-rzn1.c

336

steps = stepsl;

drivers/rtc/rtc-rzn1.c

341

if (!steps)

drivers/rtc/rtc-rzn1.c

344

if (steps > 0) {

drivers/rtc/rtc-rzn1.c

345

subu |= steps + 1;

drivers/rtc/rtc-rzn1.c

348

subu |= (~(-steps - 1)) & 0x3F;

drivers/scsi/aic7xxx/aic79xx_core.c

3414

int steps;

drivers/scsi/aic7xxx/aic79xx_core.c

3428

steps = 0;

drivers/scsi/aic7xxx/aic79xx_core.c

3455

if (steps > AHD_MAX_STEPS) {

drivers/scsi/aic7xxx/aic79xx_core.c

3464

steps++;

drivers/scsi/aic7xxx/aic7xxx_core.c

1968

int steps;

drivers/scsi/aic7xxx/aic7xxx_core.c

1976

steps = 0;

drivers/scsi/aic7xxx/aic7xxx_core.c

2003

if (steps > AHC_MAX_STEPS) {

drivers/scsi/aic7xxx/aic7xxx_core.c

2010

steps++;

drivers/spi/spi-mtk-snfi.c

667

int step_size = 0, strength = 0, desired_correction = 0, steps;

drivers/spi/spi-mtk-snfi.c

694

steps = mtd->writesize / step_size;

drivers/spi/spi-mtk-snfi.c

695

desired_correction = steps * strength;

drivers/spi/spi-qpic-snand.c

213

oobregion->length = qecc->bytes * (qecc->steps - 1) +

drivers/spi/spi-qpic-snand.c

217

oobregion->offset = qecc->bytes * (qecc->steps - 1) +

drivers/spi/spi-qpic-snand.c

219

qecc->steps * 4;

drivers/spi/spi-qpic-snand.c

237

oobregion->length = qecc->steps * 4;

drivers/spi/spi-qpic-snand.c

238

oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;

drivers/spi/spi-qpic-snand.c

321

ecc_cfg->steps = cwperpage;

drivers/spi/spi-qpic-snand.c

86

int steps;

include/linux/crush/crush.h

90

struct crush_rule_step steps[];

include/linux/font.h

115

unsigned int charcount, unsigned int steps,

include/linux/mtd/rawnand.h

353

int steps;

lib/fonts/font_rotate.c

205

unsigned int charcount, unsigned int steps,

lib/fonts/font_rotate.c

214

steps %= 4;

lib/fonts/font_rotate.c

216

switch (steps) {

lib/fonts/font_rotate.c

243

switch (steps) {

net/ceph/crush/mapper.c

943

const struct crush_rule_step *curstep = &rule->steps[step];

net/ceph/osdmap.c

601

r = kmalloc_flex(*r, steps, yes, GFP_NOFS);

net/ceph/osdmap.c

610

r->steps[j].op = ceph_decode_32(p);

net/ceph/osdmap.c

611

r->steps[j].arg1 = ceph_decode_32(p);

net/ceph/osdmap.c

612

r->steps[j].arg2 = ceph_decode_32(p);

sound/soc/atmel/mchp-pdmc.c

619

u32 tmp, steps = 16;

sound/soc/atmel/mchp-pdmc.c

633

while (steps--)

sound/soc/codecs/cs35l33.c

746

int ret = 0, steps = 0;

sound/soc/codecs/cs35l33.c

764

steps++;

sound/soc/codecs/cs35l33.c

768

steps+0x70);

sound/soc/meson/axg-pdm.c

302

val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps);

sound/soc/meson/axg-pdm.c

339

val |= PDM_HPF_SFT_STEPS(hpf->steps);

sound/soc/meson/axg-pdm.c

544

.steps = 7,

sound/soc/meson/axg-pdm.c

549

.steps = 13,

sound/soc/meson/axg-pdm.c

71

unsigned int steps;

sound/soc/meson/axg-pdm.c

77

unsigned int steps;

sound/usb/mixer.c

1797

int range, steps, threshold;

sound/usb/mixer.c

1820

steps = range / cval->res;

sound/usb/mixer.c

1846

if (steps > threshold) {

sound/usb/mixer.c

1849

steps);

tools/bpf/bpf_dbg.c

1096

int steps, ret;

tools/bpf/bpf_dbg.c

1101

steps = strtol(num, NULL, 10);

tools/bpf/bpf_dbg.c

1102

if (steps == 0 || strlen(num) == 0)

tools/bpf/bpf_dbg.c

1103

steps = 1;

tools/bpf/bpf_dbg.c

1104

if (steps < 0) {

tools/bpf/bpf_dbg.c

1105

if (!bpf_restore_regs(steps))

tools/bpf/bpf_dbg.c

1107

steps = 1;

tools/bpf/bpf_dbg.c

1113

hdr->caplen, hdr->len, steps);

tools/testing/selftests/mm/uffd-unit-tests.c

659

volatile int steps = 1;

tools/testing/selftests/mm/uffd-unit-tests.c

664

if (steps == 1 && nr == lastnr)

tools/testing/selftests/mm/uffd-unit-tests.c

669

if (steps == 1) {

tools/testing/selftests/mm/uffd-unit-tests.c

671

steps++;

tools/testing/selftests/mm/uffd-unit-tests.c

676

assert(steps == 2);