readb_relaxed
extern u8 readb_relaxed(const volatile void __iomem *addr);
#define readb_relaxed readb_relaxed
EXPORT_SYMBOL(readb_relaxed);
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
irr = readb_relaxed(d->base + IRR);
if (readb_relaxed(d->base + WHOAMI) != 0x11) {
readb_relaxed(d->base + WHOAMI));
#define readb(c) ({ u8 __v = readb_relaxed(c); rmb(); __v; })
#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
*val = readb_relaxed(vaddr);
prev_val = readb_relaxed(vaddr);
return readb_relaxed(ctx->regs + reg);
if (!(readb_relaxed(timer->control) & MASK_TCS_TC))
u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
return readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]) & MSC313_GPIO_IN;
u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
gpio->saved[i] = readb_relaxed(gpio->base + gpio->gpio_data->offsets[i]) & MSC313_GPIO_BITSTOSAVE;
stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
revision = readb_relaxed(data->base + HDMI_REVISION_ID);
*dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
value = readb_relaxed(dev->base + AT91_TWI_RHR);
return readb_relaxed(i2c->regs + II_DATA);
u8 cmd = readb_relaxed(i2c->regs + II_COMMAND);
val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
*f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
readb_relaxed(base + STM32F7_I2C_RXDR);
if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
ptr[i] = readb_relaxed(pmecc->regs.base +
buf[i] = readb_relaxed(host->data_va);
return readb_relaxed(nfc->regs + reg);
buf[i] = readb_relaxed(nfc->regs + nfc->band_offset +
*(u8 *)buf = readb_relaxed(io_addr_r);
*(u8 *)buf = readb_relaxed(io_addr_r);
*buf8++ = readb_relaxed(priv->base + i);
*val = readb_relaxed(conf_data + (where & 3));
return readb_relaxed(pcie->cra_base + reg);
*value = readb_relaxed(addr);
val = readb_relaxed(base + MIPHY_BOUNDARY_2);
val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
val = readb_relaxed(base + MIPHY_BOUNDARY_2);
val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
reg = readb_relaxed(pmap->regs + reg_off);
reg = readb_relaxed(pmap->regs + reg_off);
drive = readb_relaxed(pmap->regs + reg_off);
drive = readb_relaxed(pmap->regs + reg_off);
input = readb_relaxed(pmap->regs + reg_off);
output = readb_relaxed(pmap->regs + reg_off);
hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
return readb_relaxed(addr);
readb_relaxed((port)->regs + US_##reg)
rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD);
*((u8 *)val) = readb_relaxed(addr);
*((u8 *)val) = readb_relaxed(addr);
*rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR);
*rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR);
*rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
ch = readb_relaxed(port->membase + UA_EMI_REC);
status = readb_relaxed(port->membase + UA_STATUS);
u8 int_status = readb_relaxed(port->membase + UA_INT_STATUS);
u8 status = readb_relaxed(port->membase + UA_STATUS);
status = readb_relaxed(port->membase + UA_STATUS);
return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &
return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &
u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
return readb_relaxed(portaddr(port, reg));
val = readb_relaxed(drvdata->base + GXP_WDT_CTRL_OFS);
while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
csra = readb_relaxed(priv->base + RWTCSRA);
val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
#ifndef readb_relaxed
#define readb_relaxed readb_relaxed
readx_poll_timeout(readb_relaxed, addr, val, cond, delay_us, timeout_us)
readx_poll_timeout_atomic(readb_relaxed, addr, val, cond, delay_us, timeout_us)
return readb_relaxed(addr);
#ifndef readb_relaxed
#define readb_relaxed readb_relaxed