rdmsrq_safe
if (rdmsrq_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) {
ret = rdmsrq_safe(reg, &val);
ret = rdmsrq_safe(reg, &val);
if (rdmsrq_safe(reg, &val))
ret |= rdmsrq_safe(reg, &val_new);
if (rdmsrq_safe(msr, &val_old))
rdmsrq_safe(msr, &val_new))
if (rdmsrq_safe(msr[bit].msr, &val))
if (rdmsrq_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits))
if (rdmsrq_safe(MSR_IA32_APICBASE, &msr))
return rdmsrq_safe(msr_no, q);
rdmsrq_safe(MSR_FAM10H_MMIO_CONF_BASE, &msr))
if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
if (!rdmsrq_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
err = rdmsrq_safe(MSR_IA32_MISC_ENABLE, &misc_en);
err = rdmsrq_safe(MSR_ATOM_CORE_RATIOS, base_freq);
err = rdmsrq_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
err = rdmsrq_safe(MSR_PLATFORM_INFO, base_freq);
err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT, &msr);
err = rdmsrq_safe(MSR_PLATFORM_INFO, base_freq);
err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
err = rdmsrq_safe(MSR_PLATFORM_INFO, base_freq);
err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT, &msr);
if (rdmsrq_safe(MSR_TEST_CTRL, &ctrl))
if (rdmsrq_safe(info->msr_ppin_ctl, &val))
rdmsrq_safe(info->msr_ppin_ctl, &val);
if (rdmsrq_safe(MSR_IA32_FEAT_CTL, &msr)) {
if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
if (!rdmsrq_safe(MSR_PLATFORM_INFO, &msr)) {
if (rdmsrq_safe(MSR_MISC_FEATURES_ENABLES, &msr))
if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg))
rdmsrq_safe(mca_msr_reg(bank, MCA_STATUS), &status);
if (rdmsrq_safe(MSR_ERROR_CONTROL, &error_control))
rdmsrq_safe(MSR_IA32_SGXLEPUBKEYHASH0, &sgx_pubkey_hash[0])) {
rdmsrq_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
if (rdmsrq_safe(MSR_IA32_CR_PAT, &host_pat) ||
rdmsrq_safe(MSR_EFER, &kvm_host.efer);
if (rdmsrq_safe(MSR_IA32_SPEC_CTRL, &saved_value))
rdmsrq_safe(index, data);
ret = rdmsrq_safe(msr, &val);
rdmsrq_safe(kvm_uret_msrs_list[i], &value);
err = rdmsrq_safe(msr, &val);
ctxt->misc_enable_saved = !rdmsrq_safe(MSR_IA32_MISC_ENABLE,
msr_array[i].valid = !rdmsrq_safe(msr_id[j], &dummy);
ret = rdmsrq_safe(MSR_INTEGRITY_CAPS, &msr_integrity_caps);
if (rdmsrq_safe(MSR_IA32_MCG_CAP, &cap) ||
err = rdmsrq_safe(residency_info_ffh.gaddr.address, counter);
ret = rdmsrq_safe(MSR_AMD_CPPC_ENABLE, &cppc_enable);
if (rdmsrq_safe(MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &val))
rdmsrq_safe(MSR_HWP_STATUS, &value);
if (rdmsrq_safe(MSR_RAPL_POWER_UNIT, &power))
if (rdmsrq_safe(MSR_PP1_ENERGY_STATUS, &power))
rdmsrq_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
rdmsrq_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
if (rdmsrq_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
if (rdmsrq_safe(MSR_IA32_CORE_CAPS, &msrval))
if (rdmsrq_safe(MSR_INTEGRITY_CAPS, &msrval))
if (rdmsrq_safe(map[index].bit_mask, &pcstate_count))
if (rdmsrq_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i]))
if (rdmsrq_safe(deepest_pkgc_msr, &deepest_pkgc_residency))
if (!rdmsrq_safe(msr_map[i].bit_mask, &pc_cnt)) {
ret = rdmsrq_safe(MSR_CPU_BUS_NUMBER, &data);
ret = rdmsrq_safe(MSR_PM_LOGICAL_ID, &data);
ret = rdmsrq_safe(MSR_THREAD_ID_INFO, &data);
if (rdmsrq_safe(MSR_OS_MAILBOX_INTERFACE, &data) ||
rdmsrq_safe(MSR_OS_MAILBOX_DATA, &data))
ret = rdmsrq_safe(MSR_OS_MAILBOX_INTERFACE, &data);
ret = rdmsrq_safe(MSR_OS_MAILBOX_DATA, &data);
ret = rdmsrq_safe(MSR_PM_LOGICAL_ID, &data);
ret = rdmsrq_safe(MSR_PM_LOGICAL_ID, &data);
ret = rdmsrq_safe(MSR_OC_MAILBOX, &value);
ra->err = rdmsrq_safe(ra->reg.msr, &val);
err = rdmsrq_safe(MSR_PLATFORM_INFO, &val);
if (!rdmsrq_safe(info->msr_index, &val))
if (!rdmsrq_safe(info->msr_index, &val))
err = rdmsrq_safe(MSR_PLATFORM_INFO, &val);
err = rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val);
return rdmsrq_safe(MSR_IA32_PCM0, msr_result);