drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11222

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11247

if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11248

pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1298

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1302

pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1303

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1304

pipe_ctx->stream->link == link)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1311

if (pipe_ctx && pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1312

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1313

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1573

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1583

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1584

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1585

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1586

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1587

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1591

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1652

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1685

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1686

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1687

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1688

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1689

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1693

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1759

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1769

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1770

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1771

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1772

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1773

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1777

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1832

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1869

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1870

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1871

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1872

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1873

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1877

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1901

pipe_ctx->stream->timing.h_addressable,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1943

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1953

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1954

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1955

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1956

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1957

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1961

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2020

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2053

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2054

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2055

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2056

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2057

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2061

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2085

pipe_ctx->stream->timing.v_addressable,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2123

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2133

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2134

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2135

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2136

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2137

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2141

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2197

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2230

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2231

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2232

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2233

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2234

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2238

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2298

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2308

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2309

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2310

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2311

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2312

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2316

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2352

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2362

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2363

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2364

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2365

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2366

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2370

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2421

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2431

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2432

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2433

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2434

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2435

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2439

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2490

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2500

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2501

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2502

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2503

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2504

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2508

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1417

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1418

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1431

pipe_ctx = &pipes[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1436

if (pipe_ctx == NULL)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1497

&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1499

&& pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1502

pipe_ctx->stream->timing.display_color_depth,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1503

pipe_ctx->stream->timing.pixel_encoding,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1506

pipe_ctx->stream->timing.display_color_depth = requestColorDepth;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1507

pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1509

dc_link_update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1514

*aconnector->timing_requested = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1520

pipe_ctx->stream->test_pattern.type = test_pattern;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1521

pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

53

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

55

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

57

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

62

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

64

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

66

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

71

bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

73

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

75

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

77

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

33

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

35

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

37

bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2786

const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3009

static bool all_displays_in_sync(const struct pipe_ctx pipe[],

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3012

const struct pipe_ctx *active_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3044

const struct pipe_ctx pipe[],

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

174

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

176

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

180

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

183

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

184

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

189

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

190

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

191

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

126

const struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

129

if (stream == context->res_ctx.pipe_ctx[k].stream) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

130

pipe_ctx = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

134

ASSERT(pipe_ctx != NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

141

cfg->signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

142

cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

164

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

166

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

170

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

117

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

153

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

156

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

160

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

174

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

184

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

186

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

191

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

202

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

120

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

123

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

158

struct pipe_ctx *pipe = safe_to_lower

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

159

? &context->res_ctx.pipe_ctx[i]

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

160

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

109

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

93

static bool should_disable_otg(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

112

struct pipe_ctx *pipe = safe_to_lower

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

113

? &context->res_ctx.pipe_ctx[i]

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

114

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

279

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

280

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

281

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

283

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

286

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

287

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

288

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

290

if (pipe_ctx->stream_res.audio != NULL)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

294

if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

295

dc_is_dvi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

335

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

337

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

338

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

339

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

344

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

384

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

387

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

391

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

405

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

438

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

440

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

445

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

456

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

502

static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

526

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

530

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

532

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

533

pipe_ctx_list[active_pipe_count] = pipe_ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

584

struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

199

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

200

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

203

struct pipe_ctx *pipe = safe_to_lower

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

204

? &context->res_ctx.pipe_ctx[i]

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

205

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

265

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

269

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

270

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

271

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

273

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

276

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

277

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

278

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

280

if (pipe_ctx->stream_res.audio != NULL)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

284

if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

285

dc_is_dvi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

305

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

307

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

308

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

309

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

314

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

331

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1099

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

396

static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

419

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

423

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

425

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

426

pipe_ctx_list[active_pipe_count] = pipe_ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

475

struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

532

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

570

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

571

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

572

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

577

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

178

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

180

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

181

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

182

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

187

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

204

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc.c

1161

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1162

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1165

if (stream == pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1166

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1167

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

1168

dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);

drivers/gpu/drm/amd/display/dc/core/dc.c

1174

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1177

memcpy(&pipe_ctx->visual_confirm_color, &pipe_ctx->plane_state->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/core/dc.c

1178

sizeof(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1183

memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1186

get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1188

get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1190

get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1192

get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1194

get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1198

dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1202

get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1204

get_subvp_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1206

get_mclk_switch_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1208

get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1210

get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1212

get_refresh_rate_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1223

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1235

pipe_ctx = dc_stream_get_pipe_ctx(stream_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

1236

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1238

dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

1252

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1313

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1344

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1352

dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/core/dc.c

1356

if ((context->res_ctx.pipe_ctx[i].top_pipe) &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1357

(dc->current_state->res_ctx.pipe_ctx[i].top_pipe))

drivers/gpu/drm/amd/display/dc/core/dc.c

1358

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=

drivers/gpu/drm/amd/display/dc/core/dc.c

1359

dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1361

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=

drivers/gpu/drm/amd/display/dc/core/dc.c

1362

dc->current_state->res_ctx.pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1374

if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1375

!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1376

struct pipe_ctx *old_pipe, *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1378

old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1379

new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1387

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1457

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1459

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1619

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1622

if (!ctx->res_ctx.pipe_ctx[i].stream ||

drivers/gpu/drm/amd/display/dc/core/dc.c

1623

!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)

drivers/gpu/drm/amd/display/dc/core/dc.c

1625

if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)

drivers/gpu/drm/amd/display/dc/core/dc.c

1627

multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1645

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1648

if (!ctx->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

1649

|| ctx->res_ctx.pipe_ctx[i].top_pipe

drivers/gpu/drm/amd/display/dc/core/dc.c

1650

|| ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/core/dc.c

1653

unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1659

struct pipe_ctx *pipe_set[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

2082

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

2085

return (pipe_ctx->stream && pipe_ctx->stream == stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

2090

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

2093

return (pipe_ctx->plane_state == plane_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

2103

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2109

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2112

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2139

if (context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

2169

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

2177

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2187

resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2208

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2218

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2244

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2289

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2327

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2364

pipe = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/core/dc.c

2453

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2501

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2590

if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2592

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

2612

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2615

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2673

if (context->res_ctx.pipe_ctx[i].stream == NULL ||

drivers/gpu/drm/amd/display/dc/core/dc.c

2674

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2675

context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i;

drivers/gpu/drm/amd/display/dc/core/dc.c

2676

dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

2755

const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

2757

if (plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3772

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

3774

if (pipe_ctx->plane_state != surface)

drivers/gpu/drm/amd/display/dc/core/dc.c

3777

resource_build_scaling_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3831

struct pipe_ctx *pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

3835

struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/core/dc.c

3879

struct pipe_ctx *pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

3883

struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/core/dc.c

3919

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

3925

if (!pipe_ctx || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

3928

if (pipe_ctx->stream_res.stream_enc == NULL &&

drivers/gpu/drm/amd/display/dc/core/dc.c

3929

pipe_ctx->stream_res.hpo_frl_stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/core/dc.c

3932

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/core/dc.c

3933

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/core/dc.c

3935

is_hdmi_frl = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/core/dc.c

3940

hwss_add_stream_enc_update_hdmi_info_packets(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3945

hwss_add_hpo_frl_stream_enc_update_hdmi_info_packets(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3950

if (dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3951

hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3952

hwss_add_hpo_dp_stream_enc_update_dp_info_packets(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3954

hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3955

hwss_add_stream_enc_update_dp_info_packets(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3962

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

3966

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3967

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc.c

3970

struct pipe_ctx *top_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

3971

struct pipe_ctx *odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

4029

if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/core/dc.c

4031

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4052

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/core/dc.c

4054

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4058

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4063

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4085

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4087

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4090

hwss_add_setup_periodic_interrupt(&seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4100

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4101

add_update_info_frame_sequence(&seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4103

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/core/dc.c

4105

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/core/dc.c

4112

pipe_ctx->stream->dmdata_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

4113

hwss_add_set_dmdata_attributes(&seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4116

hwss_add_dpp_program_gamut_remap(&seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4119

hwss_add_program_output_csc(&seq_state, dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4122

pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/core/dc.c

4125

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

4126

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

4127

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

4128

hwss_add_opp_program_fmt(&seq_state, pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/core/dc.c

4155

pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4163

pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4167

pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4192

resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4197

struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4212

} else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space

drivers/gpu/drm/amd/display/dc/core/dc.c

4213

&& !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4218

hwss_add_link_set_dpms_on(&seq_state, dc->current_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4221

if (stream_update->abm_level && pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4225

if (pipe_ctx->stream_res.tg->funcs->is_blanked)

drivers/gpu/drm/amd/display/dc/core/dc.c

4226

if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))

drivers/gpu/drm/amd/display/dc/core/dc.c

4231

hwss_add_abm_set_immediate_disable(&seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4233

hwss_add_abm_set_level(&seq_state, pipe_ctx->stream_res.abm, stream->abm_level);

drivers/gpu/drm/amd/display/dc/core/dc.c

4267

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4269

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4272

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4282

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4283

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4285

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/core/dc.c

4287

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/core/dc.c

4294

pipe_ctx->stream->dmdata_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

4295

dc->hwss.set_dmdata_attributes(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4304

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

4305

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

4306

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

4307

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/core/dc.c

4329

dc->link_srv->update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4333

dc->link_srv->increase_mst_payload(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4336

dc->link_srv->reduce_mst_payload(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

434

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4360

resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4364

struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4393

if (stream_update->abm_level && pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4397

if (pipe_ctx->stream_res.tg->funcs->is_blanked)

drivers/gpu/drm/amd/display/dc/core/dc.c

4398

if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))

drivers/gpu/drm/amd/display/dc/core/dc.c

4403

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4405

pipe_ctx->stream_res.abm->funcs->set_abm_level(

drivers/gpu/drm/amd/display/dc/core/dc.c

4406

pipe_ctx->stream_res.abm, stream->abm_level);

drivers/gpu/drm/amd/display/dc/core/dc.c

4475

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4477

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

4479

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4484

update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

4537

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4539

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

4541

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4545

update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

4611

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4613

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

4616

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4620

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

4621

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4643

struct pipe_ctx *top_pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

4683

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4698

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4700

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4702

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4705

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4708

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

471

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4710

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4763

struct pipe_ctx *top_pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

4785

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc.c

4817

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc.c

4826

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc.c

4835

struct pipe_ctx *mpcc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

4836

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

4932

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4936

pipe_ctx->stream && pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4941

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4942

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/core/dc.c

4952

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4953

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4955

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4957

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4960

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4962

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4974

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4976

if (!pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4977

!pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4978

should_update_pipe_for_stream(context, pipe_ctx, stream)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4981

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4989

stream_get_status(context, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4993

dc, pipe_ctx->stream, pipe_stream_status->plane_count, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4998

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

5000

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

5007

ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5011

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5021

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

5023

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5029

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc.c

5035

&context->res_ctx.pipe_ctx[pipe_idx].rq_regs,

drivers/gpu/drm/amd/display/dc/core/dc.c

5036

&context->res_ctx.pipe_ctx[pipe_idx].dlg_regs,

drivers/gpu/drm/amd/display/dc/core/dc.c

5037

&context->res_ctx.pipe_ctx[pipe_idx].ttu_regs);

drivers/gpu/drm/amd/display/dc/core/dc.c

5049

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

5051

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

5054

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

5058

dc->hwss.set_flip_control_gsl(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

5059

pipe_ctx->plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/core/dc.c

5068

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

5070

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

5073

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

5082

dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5088

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5090

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

5091

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5174

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

5176

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

5179

if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||

drivers/gpu/drm/amd/display/dc/core/dc.c

5180

!pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||

drivers/gpu/drm/amd/display/dc/core/dc.c

5181

!pipe_ctx->plane_state->update_flags.bits.addr_update ||

drivers/gpu/drm/amd/display/dc/core/dc.c

5182

pipe_ctx->plane_state->skip_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc.c

5186

dc->hwss.program_cursor_offload_now(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5187

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc.c

5188

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/core/dc.c

5262

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

532

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

5361

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

537

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5375

pipe_ctx = &new_context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5377

if (pipe_ctx->plane_state && pipe_ctx->stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

5378

pipe_ctx->plane_state->force_full_update = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

5554

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5564

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5576

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

598

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

603

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6194

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6195

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

6197

if (!pipe_ctx->plane_state || !pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/core/dc.c

6200

if (pipe_ctx->stream_res.tg->inst != otg_inst)

drivers/gpu/drm/amd/display/dc/core/dc.c

6373

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

6410

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6469

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

6473

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

648

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

6493

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6739

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

6750

res_ctx->pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6751

res_ctx->pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6752

res_ctx->pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6753

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6754

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6760

if (pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

6761

otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6765

if (dc->hwss.set_pipe && pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

6766

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

6792

if (status && pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

6793

pipe_ctx->stream->firmware_controlled_hdr_info_packet = enable;

drivers/gpu/drm/amd/display/dc/core/dc.c

7020

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

7033

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7074

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

7083

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

722

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

728

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7305

if (res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7311

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7314

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7320

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/core/dc.c

7321

state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7323

state->hubp[i].hubp_clock_enable = (pipe_ctx->plane_res.hubp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7326

if (pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7328

state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;

drivers/gpu/drm/amd/display/dc/core/dc.c

7329

state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/core/dc.c

7330

state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7333

if (pipe_ctx->plane_state->plane_size.surface_size.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7334

state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7335

state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7339

if (pipe_ctx->plane_state->src_rect.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7340

state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7341

state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7342

state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

7343

state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

7347

state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7348

state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/core/dc.c

7349

state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/core/dc.c

7352

state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7353

state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7354

state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7355

state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

7358

state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7359

state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7360

state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7361

state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7364

state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

7365

state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

7369

if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7371

state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/core/dc.c

7372

state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

7373

state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;

drivers/gpu/drm/amd/display/dc/core/dc.c

7374

state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;

drivers/gpu/drm/amd/display/dc/core/dc.c

7375

state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;

drivers/gpu/drm/amd/display/dc/core/dc.c

7376

state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;

drivers/gpu/drm/amd/display/dc/core/dc.c

7377

state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;

drivers/gpu/drm/amd/display/dc/core/dc.c

7382

if (pipe_ctx->rq_regs.rq_regs_l.chunk_size > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7383

state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7384

state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7385

state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7386

state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7387

state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7388

state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7389

state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7390

state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

7394

if (pipe_ctx->rq_regs.rq_regs_c.chunk_size > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7395

state->hubp[i].rq_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7396

state->hubp[i].rq_min_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7397

state->hubp[i].rq_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7398

state->hubp[i].rq_min_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7399

state->hubp[i].rq_dpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7400

state->hubp[i].rq_mpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7401

state->hubp[i].rq_swath_height_c = pipe_ctx->rq_regs.rq_regs_c.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7402

state->hubp[i].rq_pte_row_height_c = pipe_ctx->rq_regs.rq_regs_c.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

7406

state->hubp[i].drq_expansion_mode = pipe_ctx->rq_regs.drq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7407

state->hubp[i].prq_expansion_mode = pipe_ctx->rq_regs.prq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7408

state->hubp[i].mrq_expansion_mode = pipe_ctx->rq_regs.mrq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7409

state->hubp[i].crq_expansion_mode = pipe_ctx->rq_regs.crq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7412

state->hubp[i].dst_y_per_vm_vblank = pipe_ctx->dlg_regs.dst_y_per_vm_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

7413

state->hubp[i].dst_y_per_row_vblank = pipe_ctx->dlg_regs.dst_y_per_row_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

7414

state->hubp[i].dst_y_per_vm_flip = pipe_ctx->dlg_regs.dst_y_per_vm_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

7415

state->hubp[i].dst_y_per_row_flip = pipe_ctx->dlg_regs.dst_y_per_row_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

7418

state->hubp[i].dst_y_prefetch = pipe_ctx->dlg_regs.dst_y_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7419

state->hubp[i].vratio_prefetch = pipe_ctx->dlg_regs.vratio_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7420

state->hubp[i].vratio_prefetch_c = pipe_ctx->dlg_regs.vratio_prefetch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

7423

state->hubp[i].qos_level_low_wm = pipe_ctx->ttu_regs.qos_level_low_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

7424

state->hubp[i].qos_level_high_wm = pipe_ctx->ttu_regs.qos_level_high_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

7425

state->hubp[i].qos_level_flip = pipe_ctx->ttu_regs.qos_level_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

7426

state->hubp[i].min_ttu_vblank = pipe_ctx->ttu_regs.min_ttu_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

7433

uint32_t det_size = res_ctx->pipe_ctx[i].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/core/dc.c

7457

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7459

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7462

state->dpp[i].dpp_clock_enable = (pipe_ctx->plane_res.dpp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7464

if (pipe_ctx->plane_state && pipe_ctx->plane_res.scl_data.recout.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7466

struct dscl_prog_data *dscl_data = &pipe_ctx->plane_res.scl_data.dscl_prog_data;

drivers/gpu/drm/amd/display/dc/core/dc.c

749

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

7498

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7499

if (pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7502

state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/core/dc.c

7506

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

drivers/gpu/drm/amd/display/dc/core/dc.c

7507

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7525

struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

7526

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

754

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

7540

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc.c

7541

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7545

if (pipe_ctx->stream_res.hpo_frl_stream_enc && pipe_ctx->link_res.hpo_frl_link_enc) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7546

int hpo_le_inst = pipe_ctx->link_res.hpo_frl_link_enc->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7556

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7558

if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

756

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7563

struct dc_dsc_config *dsc_cfg = &pipe_ctx->stream->timing.dsc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc.c

7569

if (pipe_ctx->stream_res.opp) {

drivers/gpu/drm/amd/display/dc/core/dc.c

757

pipe_ctx->stream_res.opp->dyn_expansion = option;

drivers/gpu/drm/amd/display/dc/core/dc.c

7571

state->dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

758

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/core/dc.c

7584

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7586

if (pipe_ctx->plane_state && pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7587

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

759

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/core/dc.c

7600

if (pipe_ctx->bottom_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7601

state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc.c

7605

state->mpc.mpcc_top_sel[i] = pipe_ctx->pipe_idx; /* This pipe's DPP ID */

drivers/gpu/drm/amd/display/dc/core/dc.c

7619

if (pipe_ctx->stream_res.opp) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7620

state->mpc.mpcc_opp_id[i] = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7652

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7654

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7657

if (pipe_ctx->stream_res.opp) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7658

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/core/dc.c

7664

if (pipe_ctx->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {

drivers/gpu/drm/amd/display/dc/core/dc.c

772

struct pipe_ctx *pipes = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

7735

if (pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7755

state->opp[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

776

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

drivers/gpu/drm/amd/display/dc/core/dc.c

7770

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7772

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7775

if (pipe_ctx->stream_res.tg) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7776

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/core/dc.c

7778

state->optc[i].otg_master_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

778

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7794

state->optc[i].otg_h_timing_div_mode = (pipe_ctx->next_odm_pipe) ? 1 : 0; /* ODM divide mode */

drivers/gpu/drm/amd/display/dc/core/dc.c

7813

if (pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7814

state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7815

state->optc[i].optc_seg1_src_sel = pipe_ctx->next_odm_pipe->stream_res.opp ? pipe_ctx->next_odm_pipe->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7818

state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7842

state->optc[i].optc_segment_width = (pipe_ctx->next_odm_pipe) ? (timing->h_addressable / 2) : timing->h_addressable;

drivers/gpu/drm/amd/display/dc/core/dc.c

812

struct pipe_ctx *pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

817

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

818

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

831

struct pipe_ctx *pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

836

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

839

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

858

struct pipe_ctx *pipes_affected[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

867

if (dc->current_state->res_ctx.pipe_ctx[j].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

870

&dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1003

block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1009

block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1017

current_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1039

block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1055

block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1062

block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1071

block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1076

block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1081

block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1108

block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1116

block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1152

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1172

current_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1183

block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1188

block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1215

params->pipe_control_lock_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1225

params->program_triplebuffer_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1230

params->update_plane_addr_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1234

params->set_input_transfer_func_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1266

params->set_output_transfer_func_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1271

params->update_visual_confirm_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1309

params->program_cursor_update_now_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1316

dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1321

params->update_phantom_vp_position_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1683

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1688

seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1715

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1720

seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1732

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1736

seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1747

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1752

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1763

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1766

seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1775

void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1778

seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1788

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1791

seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1802

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1807

seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1819

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1824

seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1925

struct pipe_ctx *top_pipe_to_program)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1952

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1955

seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1967

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1972

seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2232

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2236

seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2316

struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2318

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2319

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2324

struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2325

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2326

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2344

struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2345

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2346

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2445

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2450

struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2475

struct pipe_ctx *opp_head;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2483

opp_head = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2495

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2500

otg_master = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2521

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2552

const struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2555

pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2557

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2564

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2565

dc->hwss.wait_for_all_pending_updates(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2568

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2707

struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2708

struct pipe_ctx *top_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2712

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2713

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2742

struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2743

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2746

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2793

struct pipe_ctx *pipe_ctx = params->update_info_frame_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2796

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2801

struct pipe_ctx *pipe_ctx = params->setup_periodic_interrupt_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2804

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2880

struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2886

resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2913

struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2915

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2930

struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2933

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

320

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

332

struct pipe_ctx *top_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

341

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3445

struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3449

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

346

switch (pipe_ctx->plane_res.scl_data.format) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

350

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3508

struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3511

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3517

struct pipe_ctx *pipe_ctx = params->cursor_lock_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3521

dc->hwss.cursor_lock(dc, pipe_ctx, lock);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3527

struct pipe_ctx *pipe_ctx = params->begin_cursor_offload_update_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3530

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3536

struct pipe_ctx *pipe_ctx = params->commit_cursor_offload_update_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3539

dc->hwss.commit_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3545

struct pipe_ctx *pipe_ctx = params->update_cursor_offload_pipe_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3548

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3553

struct pipe_ctx *pipe_ctx = params->send_cursor_info_to_dmu_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3556

dc_send_update_cursor_info_to_dmu(pipe_ctx, (uint8_t)pipe_idx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3562

struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3565

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3589

struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3592

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3598

struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

360

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3601

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3606

struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3609

dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3615

struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3621

dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3643

if (params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3644

params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3645

params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3646

params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3647

&params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3652

if (params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3653

params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->update_hdmi_info_packets)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3654

params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3655

params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3656

&params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3661

if (params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3662

params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3663

params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3664

params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3665

&params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3670

if (params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3671

params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3672

params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3673

params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3674

&params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3679

if (params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3680

params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3681

params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3682

params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3683

&params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3688

if (params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3689

params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3690

params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3691

params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3692

&params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3771

struct pipe_ctx *pipe_ctx = params->link_increase_mst_payload_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3774

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3775

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3776

pipe_ctx->stream->link->dc->link_srv->increase_mst_payload)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3777

pipe_ctx->stream->link->dc->link_srv->increase_mst_payload(pipe_ctx, mst_stream_bw);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3782

struct pipe_ctx *pipe_ctx = params->link_reduce_mst_payload_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3785

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3786

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3787

pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3788

pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload(pipe_ctx, mst_stream_bw);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

379

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3809

struct pipe_ctx *pipe_ctx = params->link_set_dpms_off_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3811

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3812

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3813

pipe_ctx->stream->link->dc->link_srv->set_dpms_off)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3814

pipe_ctx->stream->link->dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3821

params->disable_audio_stream_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3834

struct pipe_ctx *pipe_ctx = params->link_set_dpms_on_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3836

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3837

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3838

pipe_ctx->stream->link->dc->link_srv->set_dpms_on)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3839

pipe_ctx->stream->link->dc->link_srv->set_dpms_on(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3865

struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3869

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

391

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3911

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3915

seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3954

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3959

seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

398

struct pipe_ctx *top_pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4065

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4071

seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4619

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4623

seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

466

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4670

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4675

seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4682

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4687

seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4718

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

472

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4723

seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

473

if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4730

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4735

seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

474

edp_link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4742

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4750

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4818

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4823

seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4830

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4834

if (!pipe_ctx || pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4840

seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4847

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4852

seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4860

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4865

seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4872

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4877

seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4883

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4887

seq_state->steps[*seq_state->num_steps].params.stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4893

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4897

seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4903

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4907

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4913

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4917

seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4923

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4927

seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4933

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4937

seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5016

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5021

seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

503

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5039

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5047

attr->dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5048

attr->address.quad_part = pipe_ctx->stream->dmdata_address.quad_part;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5054

pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5060

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5065

seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

507

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5072

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5077

seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

508

switch (pipe_ctx->p_state_type) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5104

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5108

seq_state->steps[*seq_state->num_steps].params.link_set_dpms_off_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5114

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5118

seq_state->steps[*seq_state->num_steps].params.disable_audio_stream_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5137

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5142

seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5148

void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5153

if (pipe_ctx && pipe_ctx->stream && color) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5154

refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5156

uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5157

uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5162

pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5163

pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5164

pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

531

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

536

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

537

switch (pipe_ctx->p_state_type) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

575

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

580

if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

593

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

598

if (!pipe_ctx->plane_state->dcc.enable) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

612

uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

613

uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

641

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

646

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

649

pipe_ctx->p_state_type = P_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

653

if (!pipe_ctx->has_vactive_margin) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

655

pipe_ctx->p_state_type = P_STATE_V_BLANK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

659

pipe_ctx->p_state_type = P_STATE_FPO;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

663

pipe_ctx->p_state_type = P_STATE_V_ACTIVE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

670

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

675

pipe_ctx->p_state_type = P_STATE_SUB_VP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

678

if (pipe_ctx->stream == pipe->stream)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

684

if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

685

if (pipe_ctx->stream->allow_freesync == 1) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

687

pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

690

pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

697

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

702

if (pipe_ctx && pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

703

pipe_ctx->stream_res.tg->funcs->set_drr)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

704

pipe_ctx->stream_res.tg->funcs->set_drr(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

705

pipe_ctx->stream_res.tg, params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

714

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

719

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

736

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

740

struct dc_plane_state *plane = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

741

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

743

struct pipe_ctx *current_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

744

struct pipe_ctx *current_mpc_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

755

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

780

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

795

block_sequence[*num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

801

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

803

block_sequence[*num_steps].params.update_info_frame_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

807

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

808

block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

816

stream->use_dynamic_meta && pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

820

attr.dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

821

attr.address.quad_part = pipe_ctx->stream->dmdata_address.quad_part;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

829

block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

844

struct pipe_ctx *cursor_pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

847

current_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

857

block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

863

block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

870

block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

894

block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

903

block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

910

block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

921

block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

927

block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

934

block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

946

struct pipe_ctx *cursor_pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

949

current_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

963

block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

969

block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

977

block_sequence[*num_steps].params.set_cursor_position_params.pipe_ctx = current_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

983

block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

990

block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

165

bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

167

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

169

return link->dc->link_srv->update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1011

static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1014

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1018

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1021

*dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1022

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1032

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1036

calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1043

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1047

calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1058

static void calculate_recout(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1186

plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1187

&pipe_ctx->plane_state->clip_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1190

&pipe_ctx->stream->dst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1192

pipe_ctx, &plane_clip);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1193

odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1200

pipe_ctx->plane_res.scl_data.recout = shift_rec(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1204

&pipe_ctx->plane_res.scl_data.recout,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1205

pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1208

memset(&pipe_ctx->plane_res.scl_data.recout, 0,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1214

static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1216

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1217

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1225

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1226

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1229

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1232

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1237

pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1239

pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1241

pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1242

pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1243

pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1244

pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1246

pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1247

pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1249

if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1250

|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1251

pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1252

pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1254

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1255

pipe_ctx->plane_res.scl_data.ratios.horz, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1256

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1257

pipe_ctx->plane_res.scl_data.ratios.vert, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1258

pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1259

pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1260

pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1261

pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1330

static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1332

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1333

struct scaler_data *data = &pipe_ctx->plane_res.scl_data;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1339

struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1347

pipe_ctx, &plane_state->dst_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1486

struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1488

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1519

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1521

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1522

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1523

const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1527

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1544

pipe_ctx->stream->dst.x += timing->h_border_left;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1545

pipe_ctx->stream->dst.y += timing->v_border_top;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1548

pipe_ctx->plane_res.scl_data.h_active = odm_slice_src.width;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1549

pipe_ctx->plane_res.scl_data.v_active = odm_slice_src.height;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1550

pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1551

pipe_ctx->plane_state->format);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1554

if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1555

struct spl_in *spl_in = &pipe_ctx->plane_res.spl_in;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1556

struct spl_out *spl_out = &pipe_ctx->plane_res.spl_out;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1559

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1561

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1563

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1566

translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1568

calculate_adjust_recout_for_visual_confirm(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1572

spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1576

translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1584

calculate_recout(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1586

calculate_scaling_ratios(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1601

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1603

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1605

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1609

pipe_ctx->plane_res.scl_data.viewport.width = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1610

pipe_ctx->plane_res.scl_data.viewport.height = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1611

pipe_ctx->plane_res.scl_data.viewport_c.width = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1612

pipe_ctx->plane_res.scl_data.viewport_c.height = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1613

if (pipe_ctx->plane_res.xfm != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1614

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1615

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1617

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1618

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1619

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1621

temp = pipe_ctx->plane_res.scl_data.taps;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1623

calculate_inits_and_viewports(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1625

if (pipe_ctx->plane_res.xfm != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1626

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1627

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1629

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1630

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1631

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1636

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1638

if (pipe_ctx->plane_res.xfm != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1639

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1640

pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1641

&pipe_ctx->plane_res.scl_data,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1644

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1645

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1646

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1647

&pipe_ctx->plane_res.scl_data,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1655

if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1656

pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1657

pipe_ctx->plane_res.scl_data.taps.v_taps_c != temp.v_taps_c ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1658

pipe_ctx->plane_res.scl_data.taps.h_taps_c != temp.h_taps_c))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1659

calculate_inits_and_viewports(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1666

if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1668

(pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1669

pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1670

if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1671

pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1672

else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1673

pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1677

if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1678

pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1679

if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1680

pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1687

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1688

pipe_ctx->plane_res.scl_data.viewport.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1689

pipe_ctx->plane_res.scl_data.viewport.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1690

pipe_ctx->plane_res.scl_data.viewport.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1691

pipe_ctx->plane_res.scl_data.viewport.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1692

pipe_ctx->plane_res.scl_data.recout.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1693

pipe_ctx->plane_res.scl_data.recout.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1694

pipe_ctx->plane_res.scl_data.recout.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1695

pipe_ctx->plane_res.scl_data.recout.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1696

pipe_ctx->plane_res.scl_data.h_active,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1697

pipe_ctx->plane_res.scl_data.v_active,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1711

pipe_ctx->stream->dst.x -= timing->h_border_left;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1712

pipe_ctx->stream->dst.y -= timing->v_border_top;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1717

bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1719

struct pipe_ctx *test_pipe, *split_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1720

struct rect r1 = pipe_ctx->plane_res.scl_data.recout;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1722

unsigned int cur_layer = pipe_ctx->plane_state->layer_index;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1724

reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1733

for (test_pipe = pipe_ctx->top_pipe; test_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1752

for (split_pipe = pipe_ctx->top_pipe; split_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1782

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1783

context->res_ctx.pipe_ctx[i].stream != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1784

if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1791

struct pipe_ctx *resource_find_free_secondary_pipe_legacy(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1794

const struct pipe_ctx *primary_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1797

struct pipe_ctx *secondary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1829

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1830

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1841

if (res_ctx->pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1842

secondary_pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1854

const struct pipe_ctx *cur_otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1857

const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1858

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1862

new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1876

const struct pipe_ctx *cur_opp_head)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1879

const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1880

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1888

new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1905

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1909

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1910

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1928

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1932

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1933

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1951

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1955

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1956

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1975

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1979

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1980

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1998

const struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2002

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2013

bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2017

return !pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2018

!pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2019

pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2021

return !pipe_ctx->top_pipe && pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2023

return pipe_ctx->plane_state && pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2025

return !pipe_ctx->plane_state && !pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2031

struct pipe_ctx *resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2038

if (res_ctx->pipe_ctx[i].stream == stream &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2039

resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2040

return &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2045

int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2047

struct pipe_ctx *opp_heads[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2049

struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2070

int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2072

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2074

struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2091

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2094

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2097

pipe = &res_ctx->pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2120

struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2122

struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2129

struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2131

struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2139

struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2141

struct pipe_ctx *pri_dpp_pipe = (struct pipe_ctx *) dpp_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2153

int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2155

struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2158

while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2166

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2169

const struct pipe_ctx *other_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2184

int resource_get_odm_slice_count(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2197

int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2201

pipe_ctx = resource_get_opp_head(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2202

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2205

while (pipe_ctx->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2207

pipe_ctx = pipe_ctx->prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2213

int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2251

struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2253

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2254

bool is_last_odm_slice = pipe_ctx->next_odm_pipe == NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2255

struct pipe_ctx *otg_master = resource_get_otg_master(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2256

int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2270

struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2274

struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2284

opp, pipe_ctx->stream->timing.pixel_encoding,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2299

const struct pipe_ctx *pipe_a, *pipe_b;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2305

pipe_a = &state_a->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2306

pipe_b = &state_b->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2341

bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2342

const struct pipe_ctx *otg_master_b)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2344

const struct pipe_ctx *opp_head_a = otg_master_a;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2345

const struct pipe_ctx *opp_head_b = otg_master_b;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2383

static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2457

struct pipe_ctx *otg_master, int stream_idx, bool is_phantom_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2459

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2460

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2515

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2557

static struct pipe_ctx *get_tail_pipe(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2558

struct pipe_ctx *head_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2560

struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2570

static struct pipe_ctx *get_last_opp_head(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2571

struct pipe_ctx *opp_head)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2579

static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2580

struct pipe_ctx *dpp_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2590

struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2595

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2599

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2618

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2622

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2637

struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2764

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2780

pipe_ctx->link_res.hpo_frl_link_enc = pool->hpo_frl_link_enc[enc_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2782

return pipe_ctx->link_res.hpo_frl_link_enc != NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2786

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2795

pipe_ctx->link_res.hpo_frl_link_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2903

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2919

pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2921

return pipe_ctx->link_res.hpo_dp_link_enc != NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2925

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2934

pipe_ctx->link_res.hpo_dp_link_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2969

if ((res_ctx->pipe_ctx[i].stream == stream) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2970

(res_ctx->pipe_ctx[i].stream_res.stream_enc != NULL)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2971

stream_enc_inst = res_ctx->pipe_ctx[i].stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3052

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3054

if (pipe_ctx && pipe_ctx->link_res.dio_link_enc == pool->link_encoders[old_encoder])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3055

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[new_encoder];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3062

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3098

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[enc_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3100

return pipe_ctx->link_res.dio_link_enc != NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3104

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3114

pipe_ctx->link_res.dio_link_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3124

if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3143

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3221

static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3226

struct pipe_ctx *opp_head_pipe = otg_master_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3272

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3278

struct pipe_ctx *sec_pipe, *tail_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3279

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3323

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3355

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3357

if (pipe_ctx->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3358

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3359

pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3365

if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3366

pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3372

if (!pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3373

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3375

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3414

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3419

struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3420

struct pipe_ctx *new_opp_head;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3421

struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3494

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3498

struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3499

struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3553

struct pipe_ctx *dpp_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3558

struct pipe_ctx *last_dpp_pipe =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3560

struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3561

struct pipe_ctx *new_dpp_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3616

struct pipe_ctx *dpp_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3620

struct pipe_ctx *last_dpp_pipe =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3648

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3685

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3971

if (!res_ctx->pipe_ctx[tg_inst].stream) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3972

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3974

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3977

if (pipe_ctx->stream_res.tg->funcs->get_optc_source)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3978

pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3991

pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3993

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3994

pipe_ctx->plane_res.mi = pool->mis[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3995

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3996

pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3997

pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3998

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3999

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4002

pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4007

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4010

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4014

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4018

pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4021

pipe_ctx->pipe_idx = (uint8_t)id_src[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4026

pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4027

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4030

pipe_ctx->stream = stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4035

res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4036

res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4037

res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4038

res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4096

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4135

pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4136

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4137

pipe_ctx->pipe_idx = (uint8_t)pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4138

pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4139

pipe_ctx->plane_res.mi = pool->mis[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4140

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4141

pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4142

pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4143

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4144

pipe_ctx->stream_res.opp = pool->opps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4146

pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4151

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4152

pipe_ctx->stream_res.opp = pool->opps[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4155

pipe_ctx->stream = stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4171

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4197

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4199

if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4202

pipe_ctx->stream_res.stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4206

if (!pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4211

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4216

pipe_ctx->stream_res.hpo_frl_stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4220

if (!pipe_ctx->stream_res.hpo_frl_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4228

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4230

pipe_ctx->link_res.hpo_frl_link_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4231

pipe_ctx->stream->link->hpo_frl_link_enc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4232

if (!pipe_ctx->link_res.hpo_frl_link_enc) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4233

if (!add_hpo_frl_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4236

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4247

&pipe_ctx->link_config.dp_link_settings))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4251

&pipe_ctx->link_config.dp_tunnel_settings);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4254

&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4255

pipe_ctx->stream_res.hpo_dp_stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4259

if (!pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4264

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4266

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4272

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4277

dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4281

pipe_ctx->stream_res.audio = find_first_free_audio(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4282

&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4289

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4291

pipe_ctx->stream_res.audio, true);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4295

if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4297

pipe_ctx->stream_res.abm = pool->abm;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4299

pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4304

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4305

context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4306

if (pipe_ctx->stream_res.hpo_frl_stream_enc != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4307

context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4309

pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4647

static void calculate_timing_params_for_dsc_with_padding(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4651

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4654

stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4655

pipe_ctx->dsc_padding_params.dsc_hactive_padding = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4656

pipe_ctx->dsc_padding_params.dsc_htotal_padding = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4659

pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz = stream->timing.pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4675

pipe_ctx->dsc_padding_params.dsc_hactive_padding =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4678

if (stream->timing.h_total - hactive - pipe_ctx->dsc_padding_params.dsc_hactive_padding < 32)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4679

pipe_ctx->dsc_padding_params.dsc_hactive_padding = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4681

dc_update_modified_pix_clock_for_dsc_with_padding(stream, &stream->timing, &pipe_ctx->dsc_padding_params);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4721

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4723

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4728

calculate_timing_params_for_dsc_with_padding(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4731

pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4732

pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4733

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4742

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4748

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4750

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4754

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4788

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4790

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4798

unsigned int vic = pipe_ctx->stream->timing.vic;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4799

unsigned int rid = pipe_ctx->stream->timing.rid;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4800

unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4811

color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4953

if (pipe_ctx->stream->timing.hdmi_vic != 0)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4959

switch (pipe_ctx->stream->timing.hdmi_vic) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5175

void resource_build_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5178

struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5191

signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5193

if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5194

vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5198

set_avi_info_frame(&info->avi, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5200

set_vendor_info_packet(&info->vendor, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5201

set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5202

set_vtem_info_packet(&info->vtem, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5204

set_spd_info_packet(&info->spd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5206

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5212

set_vsc_info_packet(&info->vsc, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5214

set_spd_info_packet(&info->spd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5216

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5218

pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5233

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5236

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5239

if (dc_is_dp_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5240

|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5241

pipe_ctx->clock_source = pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5243

pipe_ctx->clock_source = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5246

pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5248

pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5250

if (pipe_ctx->clock_source == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5251

pipe_ctx->clock_source =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5257

if (pipe_ctx->clock_source == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5262

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5273

struct pipe_ctx *pipe_ctx_old,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5274

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5279

if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5282

if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5285

if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5288

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5289

&& pipe_ctx_old->stream != pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5292

if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5295

if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5298

if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5305

if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5308

if (pipe_ctx_old->stream_res.hpo_frl_stream_enc != pipe_ctx->stream_res.hpo_frl_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5310

if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5312

if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5317

if (pipe_ctx_old->link_res.dio_link_enc != pipe_ctx->link_res.dio_link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5325

if (link_enc_prev != pipe_ctx->stream->link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5663

struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5667

pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5668

pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5673

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5674

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5678

pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5692

struct pipe_ctx *pipe_ctx, *pipe_ctx_check;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5694

pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5695

if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5696

!IS_PIPE_SYNCD_VALID(pipe_ctx))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5697

SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5701

pipe_ctx_check = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5705

struct pipe_ctx *first_pipe = pipe_ctx_check;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5726

struct pipe_ctx *pipe_ctx_reset;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5730

pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5842

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5843

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5847

struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5896

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5898

if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5899

if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5900

pipe_ctx->stream_res.hpo_dp_stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5902

&context->res_ctx, dc->res_pool, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5904

if (!pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5909

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5913

if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5914

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5918

if (pipe_ctx->stream_res.hpo_dp_stream_enc) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5921

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5923

pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5925

if (pipe_ctx->link_res.hpo_dp_link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5926

remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5929

if (pipe_ctx->link_res.dio_link_enc == NULL && dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5930

if (!add_dio_link_enc_to_ctx(dc, context, dc->res_pool, pipe_ctx, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5936

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5938

return &pipe_ctx->plane_res.scl_data.dscl_prog_data;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5988

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5990

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5991

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

735

const struct pipe_ctx *pipe_with_clk_src,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

736

const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

767

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

772

if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

773

return res_ctx->pipe_ctx[i].clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

886

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

950

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

976

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

979

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

980

int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

981

int mpc_slice_idx = resource_get_mpc_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

152

struct pipe_ctx *cur_pipe = &dst_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

155

cur_pipe->top_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

158

cur_pipe->bottom_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

161

cur_pipe->prev_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

164

cur_pipe->next_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

443

struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_state.c

505

struct pipe_ctx *otg_master_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

706

const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

708

return dc_state_get_stream_subvp_type(state, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

961

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

309

struct pipe_ctx *pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

318

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

320

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

324

pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

327

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

335

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

337

dc_send_update_cursor_info_to_dmu(pipe_ctx, i);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

339

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

341

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

456

struct pipe_ctx *pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

465

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

467

if (pipe_ctx->stream != stream ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

468

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

469

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

470

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

471

(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

475

pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

478

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

483

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

485

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

488

dc_send_update_cursor_info_to_dmu(pipe_ctx, i);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

555

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

558

if (stream == pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

559

get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

562

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

563

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

564

pipe_ctx->plane_res.hubp->mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

574

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

577

if (stream == pipe_ctx->stream &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

578

pipe_ctx->stream_res.tg->funcs->program_manual_trigger) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

579

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

580

pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

769

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

771

if (res_ctx->pipe_ctx[i].stream != stream || !tg)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

799

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

801

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

805

dc->hwss.send_immediate_sdp_message(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

837

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

839

if (res_ctx->pipe_ctx[i].stream != stream || !tg)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

857

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

864

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

881

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

894

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

895

if (pipe_ctx->stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

902

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

906

pipe_ctx->stream->dmdata_address = attr->address;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

910

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

913

pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

931

struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

936

struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

135

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

136

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

138

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

141

if (pipe_ctx->plane_state && flags.bits.address)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

142

pipe_ctx->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

143

if (pipe_ctx->plane_state && flags.bits.histogram)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

144

memset(&pipe_ctx->plane_state->status.cm_hist, 0,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

145

sizeof(pipe_ctx->plane_state->status.cm_hist));

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

153

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

154

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

156

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

160

dc->hwss.update_pending_status(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

162

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

165

dpp->funcs->dpp_cm_hist_read(dpp, &pipe_ctx->plane_state->status.cm_hist);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

300

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

302

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

306

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

75

struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

77

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

78

pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/dc.h

2437

bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1022

static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1024

if (pipe_ctx->plane_state != NULL) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1025

if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1026

resource_can_pipe_disable_cursor(pipe_ctx))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1030

if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1031

pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1032

pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1035

if (pipe_ctx->stream->link->replay_settings.config.replay_supported)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1042

struct pipe_ctx *pipe_ctx, uint8_t p_idx,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1045

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1046

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1054

pipe_ctx->stream->link, &panel_inst))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1071

payload->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1115

struct pipe_ctx *pCtx, uint8_t pipe_idx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1241

struct pipe_ctx const *pipe_ctx;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1251

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1252

if (!pipe_ctx || !pipe_ctx->stream_res.tg || pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1263

cntl->data.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1275

void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

421

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

430

struct pipe_ctx *head_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

438

struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

470

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

489

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

541

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

546

if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

587

struct pipe_ctx *subvp_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

588

struct pipe_ctx *vblank_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

668

struct pipe_ctx *vblank_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

672

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

678

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

725

struct pipe_ctx *subvp_pipes[])

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

790

struct pipe_ctx *subvp_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

855

struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

890

struct pipe_ctx *subvp_pipes[2];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

902

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

915

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

103

void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

34

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

354

void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

93

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

101

populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

122

resource_get_mpc_slice_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

127

spl_in->basic_in.mpc_h_slice_index = resource_get_mpc_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

131

spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

134

stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

139

pipe_ctx->stream->ctx->dc->debug.max_downscale_src_width;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

140

spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

142

spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

143

spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

147

spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

149

if (pipe_ctx->stream->ctx->dc->debug.force_easf == 1)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

151

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

153

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 3)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

156

unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

157

unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

189

if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

190

spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

194

if (pipe_ctx->stream->ctx->dc->debug.force_cositing)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

195

spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

202

spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

203

spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

207

(enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

212

spl_in->is_fullscreen = pipe_ctx->stream->sharpening_required;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

213

spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

220

void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

223

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

225

populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

227

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

229

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->viewport_c);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

231

populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

233

populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

77

void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

79

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

80

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

81

struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.h

15

void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.h

21

void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

38

const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_stream.h

615

struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_trace.h

26

#define TRACE_DC_PIPE_STATE(pipe_ctx, max_pipes) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

28

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \

drivers/gpu/drm/amd/display/dc/dc_trace.h

29

if (pipe_ctx->plane_state) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

30

trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \

drivers/gpu/drm/amd/display/dc/dc_trace.h

31

pipe_ctx->stream, &pipe_ctx->plane_res, \

drivers/gpu/drm/amd/display/dc/dc_trace.h

32

pipe_ctx->update_flags.raw); \

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

301

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

306

if (res_ctx->pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

307

res_ctx->pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

308

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

309

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

315

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

319

if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

341

copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

343

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

347

if (pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

348

copy_settings_data->opp_inst = (uint8_t)pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

351

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

352

copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

382

copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

124

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

130

res_ctx->pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

131

res_ctx->pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

132

res_ctx->pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

133

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

134

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

140

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

153

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

158

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

159

copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

179

copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

435

pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1203

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1238

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

302

const struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

455

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

525

struct pipe_ctx *primary_pipe,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

526

struct pipe_ctx *secondary_pipe)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

712

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

897

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1001

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1043

wb_arb_params->time_per_pixel = (unsigned int)(16.0 * 1000.0 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000)); /* 4 bit fraction, ms */

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1050

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1052

if (dc_is_hdmi_frl_signal(context->res_ctx.pipe_ctx[i].stream->signal))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1054

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1067

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1184

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1186

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1193

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1195

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1196

context->res_ctx.pipe_ctx[i].unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1198

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1199

context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1204

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1206

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1208

context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1210

&context->res_ctx.pipe_ctx[i].stream->timing,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1211

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1231

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1239

&context->res_ctx.pipe_ctx[i].dlg_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1240

&context->res_ctx.pipe_ctx[i].ttu_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1249

&context->res_ctx.pipe_ctx[i].rq_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1332

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1340

if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1345

res_ctx->pipe_ctx[pipe_cnt].stream,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1346

res_ctx->pipe_ctx[i].stream) &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1348

res_ctx->pipe_ctx[pipe_cnt].stream,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1349

res_ctx->pipe_ctx[i].stream))) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1356

struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1362

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1377

pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1379

pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1380

if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1388

dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1415

(unsigned char)res_ctx->pipe_ctx[i].stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1419

pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1420

pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1421

switch (resource_get_odm_slice_count(&res_ctx->pipe_ctx[i])) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1431

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1432

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1433

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1434

struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1438

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1446

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1448

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1449

} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1450

struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1457

switch (res_ctx->pipe_ctx[i].stream->signal) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1461

if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1482

switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1512

switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1523

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1524

!res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1535

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1536

pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1541

get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1547

if (res_ctx->pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1548

(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1549

dc_state_get_pipe_subvp_type(context, &res_ctx->pipe_ctx[i]) == SUBVP_PHANTOM))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1557

if (!res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1598

struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1599

struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1602

pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1603

|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1610

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1666

struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1672

split_pipe = res_ctx->pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1753

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2264

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2499

struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2512

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

999

struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

196

struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

209

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

484

if (!context->res_ctx.pipe_ctx[pipe_i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

469

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

541

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

544

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

576

if (context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

577

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

580

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

583

context->res_ctx.pipe_ctx[i].det_buffer_size_kb =

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

585

if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

586

context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

587

total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

314

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

327

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

329

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

413

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1052

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1102

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1104

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1105

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1106

pipe_ctx->subvp_index = (uint8_t)index++;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1108

pipe_ctx->subvp_index = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1121

struct pipe_ctx *pri_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1149

struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1152

struct pipe_ctx *pri_dpp_pipe = resource_get_primary_dpp_pipe(dpp_pipe);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1175

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1176

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1228

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1236

pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1609

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1611

if (dc_is_hdmi_frl_signal(context->res_ctx.pipe_ctx[i].stream->signal))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1613

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1676

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1678

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1689

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1691

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1692

context->res_ctx.pipe_ctx[i].unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1694

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = (int)get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1696

context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1701

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1702

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1704

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1705

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1707

context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = (unsigned int)get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1710

context->res_ctx.pipe_ctx[i].has_vactive_margin = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1712

context->res_ctx.pipe_ctx[i].has_vactive_margin = false;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1716

if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1717

(context->res_ctx.pipe_ctx[i].top_pipe == NULL ||

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1718

context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1719

context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1721

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1722

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1724

if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1726

context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1730

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1760

if (context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1761

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1766

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1770

&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1773

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1779

static struct pipe_ctx *dcn32_find_split_pipe(

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1784

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1787

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1788

pipe = &context->res_ctx.pipe_ctx[old_index];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1794

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1795

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1796

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1797

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1811

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1812

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1824

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1825

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1930

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1983

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1984

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2004

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2005

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2006

struct pipe_ctx *hsplit_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2047

struct pipe_ctx *pipe_4to1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2090

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2099

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2191

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2192

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2569

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3368

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3410

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3424

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3426

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3428

refresh_rate = (unsigned int)((pipe_ctx->stream->timing.pix_clk_100hz * 100 +

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3429

pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3430

/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total));

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

346

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3507

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3546

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

471

struct pipe_ctx *ref_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

478

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

491

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

568

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

613

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

647

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

690

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

731

struct pipe_ctx *subvp_pipes[2] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

740

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

804

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

805

struct pipe_ctx *drr_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

822

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

839

drr_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

903

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

904

struct pipe_ctx *subvp_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

928

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

950

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

998

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

41

struct pipe_ctx *ref_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

446

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

460

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

463

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

554

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

584

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

478

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

492

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

495

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

586

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

613

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

1001

pipe_ctx->p_state_type = P_STATE_FPO;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

1004

pipe_ctx->p_state_type = P_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

102

timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

108

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

109

timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

112

timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

119

timing->h_blank_end = hblank_start - stream->timing.h_addressable - pipe_ctx->dsc_padding_params.dsc_hactive_padding

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

138

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

139

pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

200

struct dc_stream_state *stream, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

494

struct pipe_ctx *temp_pipe = &dml_ctx->v21.scratch.temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

496

memset(temp_pipe, 0, sizeof(struct pipe_ctx));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

499

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

823

populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

824

populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

93

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

961

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

966

mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

967

mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

969

mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

970

mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

977

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

984

pipe_ctx->p_state_type = P_STATE_V_ACTIVE;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

989

pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

991

pipe_ctx->p_state_type = P_STATE_V_BLANK;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

995

pipe_ctx->p_state_type = P_STATE_SUB_VP;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

999

pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

13

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

25

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

26

void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

103

memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

104

memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

122

struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

148

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

153

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

158

memcpy(&pipe_ctx->global_sync,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

166

struct pipe_ctx *dc_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

187

bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

190

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

191

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

192

pipe_ctx->link_res.hpo_dp_link_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

193

dc_is_dp_signal(pipe_ctx->stream->signal));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

202

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

204

if (pipe_ctx->stream && dc_state_get_paired_subvp_stream(context, pipe_ctx->stream) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

205

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

213

void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

218

dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

219

find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

221

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

222

memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

223

pipe_ctx->unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

224

pipe_ctx->det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

226

memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

227

pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

228

pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

231

pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

232

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

233

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

235

dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

237

bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

239

dml21_set_dc_p_state_type(pipe_ctx, stream_prog, sub_vp_enabled);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

434

if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

435

context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == stream->stream_id &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

436

context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == context->stream_status[dc_stream_idx].plane_states[dc_plane_idx]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

473

if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

474

context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == phantom_stream->stream_id &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

475

context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == phantom_status->plane_states[dc_plane_idx]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

73

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

75

struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

87

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

88

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

11

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

24

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

29

struct pipe_ctx *dc_pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

30

bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

33

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

37

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

38

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

42

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

277

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

278

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

59

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

60

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

109

static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

114

if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

115

if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

116

return &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1173

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

123

static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

130

if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

131

state->res_ctx.pipe_ctx[i].stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

132

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

134

return &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

149

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

160

struct pipe_ctx *mpc_pipe = pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

231

static bool is_plane_using_pipe(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

239

static bool is_pipe_free(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

271

if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

272

struct pipe_ctx *head_pipe =

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

273

resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ?

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

274

resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) :

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

280

if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

281

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

282

(existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

283

existing_state->res_ctx.pipe_ctx[i].next_odm_pipe))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

313

struct pipe_ctx *head_pipe =

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

314

resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ?

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

315

resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) :

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

321

if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

322

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

323

existing_state->res_ctx.pipe_ctx[i].stream_res.tg)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

353

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

370

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

387

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

399

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

422

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

439

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

456

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

468

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

48

struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

52

struct pipe_ctx *prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

550

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

558

pipe = &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

569

static struct pipe_ctx *add_plane_to_blend_tree(struct dml2_context *ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

574

struct pipe_ctx *top_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

582

top_pipe->bottom_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

586

state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].top_pipe = top_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

587

state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

589

top_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

603

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

617

static struct pipe_ctx *assign_pipes_to_stream(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

623

struct pipe_ctx *master_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

651

static struct pipe_ctx *assign_pipes_to_plane(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

660

struct pipe_ctx *master_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

709

static void free_pipe(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

711

memset(pipe, 0, sizeof(struct pipe_ctx));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

721

if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

722

state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

724

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

725

!is_pipe_used(pool, state->res_ctx.pipe_ctx[i].pipe_idx)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

726

free_pipe(&state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

734

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

738

pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][0]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

753

struct pipe_ctx *master_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

765

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][0]], true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

774

struct pipe_ctx *master_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

799

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]], true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

914

struct pipe_ctx *otg_master = ctx->config.callbacks.get_otg_master_for_stream(&state->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

926

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

122

struct pipe_ctx temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

108

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

130

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

131

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

152

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

193

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

239

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

264

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

317

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

360

struct pipe_ctx *subvp_pipes[2] = { NULL, NULL };

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

369

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

444

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

458

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

51

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

523

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

524

struct pipe_ctx *subvp_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

548

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

574

if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

576

schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

581

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

635

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

676

struct pipe_ctx *ref_pipe,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

684

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

690

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

740

struct pipe_ctx *ref_pipe = &state->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

766

struct pipe_ctx *curr_pipe = &state->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

825

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

878

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

927

struct pipe_ctx *pipe_ctx = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

929

if (!pipe_ctx->plane_state || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

932

ctx->config.svp_pstate.callbacks.build_scaling_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

936

if (state->res_ctx.pipe_ctx[dc_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

940

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx, state->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1218

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1283

struct pipe_ctx *current_pipe_context;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1292

current_pipe_context = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1308

struct pipe_ctx *current_pipe_context;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1333

if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1334

current_pipe_context = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1442

struct pipe_ctx *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

786

const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

993

struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

995

memset(temp_pipe, 0, sizeof(struct pipe_ctx));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

998

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

38

void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

39

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

156

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

158

if (pipe_ctx == NULL || pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

162

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

164

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

165

pipe_ctx->link_res.hpo_dp_link_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

166

dc_is_dp_signal(pipe_ctx->stream->signal));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

174

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

176

if (dc_is_hdmi_frl_signal(context->res_ctx.pipe_ctx[i].stream->signal))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

178

if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

242

static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

245

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

249

hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

250

vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

255

pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

256

pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

257

pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

258

pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

260

ASSERT(pipe_ctx->stream_res.tg->inst <= 0xFF);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

261

pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

263

pipe_ctx->pipe_dlg_param.hactive = hactive;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

264

pipe_ctx->pipe_dlg_param.vactive = vactive;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

265

pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

266

pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

267

pipe_ctx->pipe_dlg_param.hblank_end = hblank_end;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

268

pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

269

pipe_ctx->pipe_dlg_param.hblank_start = hblank_start;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

270

pipe_ctx->pipe_dlg_param.vblank_start = vblank_start;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

271

pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

272

pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

273

pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

274

pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

275

pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

276

pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

277

pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

278

pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

279

pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

302

if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

308

if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

309

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

310

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

313

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

319

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

324

populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

326

pipe_mall_type = dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[dc_pipe_ctx_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

329

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

330

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

332

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

334

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

337

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

338

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = (int)(dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

339

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

340

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

344

dml2_update_pipe_ctx_dchub_regs(&s->rq_regs, &s->disp_dlg_regs, &s->disp_ttu_regs, &out_new_hw_state->pipe_ctx[dc_pipe_ctx_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

346

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

350

if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

351

(context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

352

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

353

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

356

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

359

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

443

if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

446

(1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

524

if (!display_state->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

526

if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

527

display_state->res_ctx.pipe_ctx[i].stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

528

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

531

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state->res_ctx.pipe_ctx[i].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

100

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

103

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

116

bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

142

enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

37

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

74

bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

75

void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

77

bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

90

int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

91

int (*get_odm_slice_count)(const struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

92

int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

93

int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

94

struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

95

struct pipe_ctx *(*get_otg_master_for_stream)(

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

98

int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

182

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

290

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

48

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

90

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1287

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1294

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1302

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

154

void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

158

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

49

void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1124

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1132

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1135

if (dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1138

dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1140

link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1142

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1145

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1148

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1156

pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1158

link_hwss->enable_audio_packet(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1160

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1161

pipe_ctx->stream_res.audio->enabled = true;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1165

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1171

if (!pipe_ctx || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1174

if (dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1177

dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1179

link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1181

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1184

link_hwss->disable_audio_packet(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1186

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1187

pipe_ctx->stream_res.audio->enabled = false;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1201

void dce110_disable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1203

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1205

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1206

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1208

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1211

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1212

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1217

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1218

pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1219

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1220

pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1221

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1224

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1225

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->stop_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1226

pipe_ctx->stream_res.hpo_frl_stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1227

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1228

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1229

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1230

} else if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1231

pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1232

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1234

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1236

link_hwss->reset_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1238

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1240

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1241

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1251

if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_FRL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1260

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1264

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1269

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1272

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1273

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1280

void dce110_blank_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1282

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1292

link->dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1295

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1297

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1298

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1299

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1300

pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1302

if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1311

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1323

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1324

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_blank(pipe_ctx->stream_res.hpo_frl_stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1332

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1338

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1340

if (pipe_ctx == NULL || pipe_ctx->stream_res.stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1343

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1344

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1351

if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1354

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1356

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1357

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1384

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1387

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1392

&pipe_ctx->link_config.dp_link_settings);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1394

dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1395

dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1398

&pipe_ctx->link_config.dp_link_settings));

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1419

struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1477

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1480

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1481

audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1483

audio_output->signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1517

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1520

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1532

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1535

if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1539

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1543

if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1544

switch (pipe_ctx->stream->link->frl_link_settings.frl_link_rate) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1567

(pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1568

pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1569

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1577

pipe_ctx->stream_res.tg->inst + 1);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1583

pipe_ctx->pll_settings.ss_percentage;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1585

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1586

populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1591

const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1596

if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1600

get_surface_visual_confirm_color(pipe_ctx, &color);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1603

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1606

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1607

pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1608

pipe_ctx->plane_res.scl_data.lb_params.depth,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1609

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1611

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1617

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1620

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1621

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1625

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1626

&pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1630

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1635

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1636

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1637

pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1645

pipe_ctx->stream_res.tg->funcs->set_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1646

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1653

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1655

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1656

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1657

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1658

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1659

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1672

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1673

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1680

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1685

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1686

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1696

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1700

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1704

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1707

link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1711

hws->funcs.disable_stream_gating(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1714

if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1717

build_audio_output(context, pipe_ctx, &audio_output);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1719

link_hwss->setup_audio_output(pipe_ctx, &audio_output,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1720

pipe_ctx->stream_res.audio->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1722

pipe_ctx->stream_res.audio->funcs->az_configure(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1723

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1724

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1726

&pipe_ctx->stream->audio_info,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1730

if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1731

dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1732

pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1736

if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1737

check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1739

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1740

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1744

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1745

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1769

if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1772

if (!pipe_ctx->stream->apply_seamless_boot_optimization)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1773

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1776

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1780

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1789

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1790

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1791

pipe_ctx->stream_res.tg, event_triggers, 2);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1793

if (!dc_is_virtual_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1794

!dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1795

pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1796

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1797

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1799

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1806

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1807

if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1810

(dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1811

dc_is_virtual_signal(pipe_ctx->stream->signal)))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1812

dc->link_srv->set_dsc_enable(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1816

dc->link_srv->set_dpms_on(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1823

if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1824

if (!pipe_ctx->stream->apply_seamless_boot_optimization)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1825

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1828

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1834

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1835

pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1836

pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1931

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1933

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2020

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2027

if (pipe_ctx == NULL || pipe_ctx->stream_res.tg == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2029

tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2061

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2108

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2109

if (pipe_ctx &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2111

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2115

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2116

&pipe_ctx->pixel_rate_divider.div_factor1,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2117

&pipe_ctx->pixel_rate_divider.div_factor2);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2121

pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2123

dc_hwss_enable_otg_pwa(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2210

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2213

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2217

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2218

pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2219

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2227

pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2228

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2251

if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2254

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2255

res_ctx->pipe_ctx[i].plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2263

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2264

res_ctx->pipe_ctx[i].plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2277

static void set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2299

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2302

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2311

static void get_position(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2320

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2323

static void set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2339

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2346

pipe_ctx[i]->stream_res.tg->funcs->

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2347

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2359

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2375

if (res_ctx->pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2377

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2380

if (pipe_ctx->pipe_idx != underlay_idx) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2390

if (!pipe_ctx->stream->link)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2394

if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2398

if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2402

if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2406

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2410

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2429

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2431

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2432

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2433

params.inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2452

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2453

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2454

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2465

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2466

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2472

if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2541

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2543

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2546

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2548

if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2549

pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_FRL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2551

if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2554

build_audio_output(context, pipe_ctx, &audio_output);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2560

if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2573

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2574

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2575

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2580

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2581

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2582

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2592

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2594

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2597

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2600

if (!dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2603

if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2606

build_audio_output(context, pipe_ctx, &audio_output);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2614

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2626

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2627

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2628

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2633

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2634

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2635

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2673

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2674

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2675

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2677

if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2680

if (pipe_ctx->stream == pipe_ctx_old->stream) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2681

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2683

pipe_ctx->clock_source, i);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2702

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2703

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2704

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2706

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2709

if (pipe_ctx->stream == pipe_ctx_old->stream &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2710

pipe_ctx->stream->link->link_state_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2714

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2717

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2721

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2738

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2740

if (pipe_ctx && pipe_ctx->stream != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2741

dc_hwss_enable_otg_pwa(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2757

static void set_default_colors(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2762

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2763

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2765

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2769

pipe_ctx->stream->timing.display_color_depth;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2772

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2774

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2775

pipe_ctx->plane_res.xfm, &default_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2799

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2804

if (pipe_ctx->bottom_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2807

ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2809

if (pipe_ctx->bottom_pipe->plane_state->visible) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2810

if (pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2815

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2818

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2821

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2822

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2826

static void program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2834

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2839

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2842

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2845

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2848

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2853

pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2854

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

286

dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2861

static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2863

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2869

pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2870

pipe_ctx->plane_res.mi);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2873

pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2875

plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2876

if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2877

pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2879

!pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

290

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2932

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2979

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3125

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3127

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3128

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3141

set_default_colors(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3142

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3145

pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3149

pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3151

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3152

(pipe_ctx->plane_res.xfm, &tbl_entry);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3155

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3160

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3163

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3165

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3167

program_scaler(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3178

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3182

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3188

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3189

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3190

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3191

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3193

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3194

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3202

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3203

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3204

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3205

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3206

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3207

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3208

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3209

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3210

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3211

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3212

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3213

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3214

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3215

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3216

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3217

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3223

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3224

pipe_ctx->plane_res.scl_data.viewport.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3225

pipe_ctx->plane_res.scl_data.viewport.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3226

pipe_ctx->plane_res.scl_data.viewport.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3227

pipe_ctx->plane_res.scl_data.viewport.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3228

pipe_ctx->plane_res.scl_data.recout.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3229

pipe_ctx->plane_res.scl_data.recout.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3230

pipe_ctx->plane_res.scl_data.recout.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3231

pipe_ctx->plane_res.scl_data.recout.y);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3249

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3251

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3255

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3256

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3257

pipe_ctx->stream->timing.h_total,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3258

pipe_ctx->stream->timing.v_total,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3259

pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3262

dce110_program_front_end_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3264

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3266

program_surface_visibility(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3282

static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3286

int fe_idx = pipe_ctx->plane_res.mi ?

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3287

pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3290

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3303

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3307

(void)pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3312

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3324

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3325

enum dc_color_space color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3328

tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3332

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3333

pipe_ctx->plane_res.xfm, &tbl_entry);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3337

static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3339

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3340

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3341

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3343

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3344

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3345

.viewport = pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3346

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3347

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3348

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3349

.mirror = pipe_ctx->plane_state->horizontal_mirror

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3365

pos_cpy.x += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3366

pos_cpy.y += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3369

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3373

if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3382

static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3384

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3386

if (pipe_ctx->plane_res.ipp &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3387

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3388

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3389

pipe_ctx->plane_res.ipp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3391

if (pipe_ctx->plane_res.mi &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3392

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3393

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3394

pipe_ctx->plane_res.mi, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3396

if (pipe_ctx->plane_res.xfm &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3397

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3398

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3399

pipe_ctx->plane_res.xfm, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3402

bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3407

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3409

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3416

uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3437

void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3439

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3440

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3444

pipe_ctx->stream->link->panel_cntl->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3450

void dce110_set_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3452

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3453

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3454

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3508

struct pipe_ctx *pipes =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3509

link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

610

dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

614

struct transform *xfm = pipe_ctx->plane_res.xfm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

635

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

640

ASSERT(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

642

if (pipe_ctx->stream_res.stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

645

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

646

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

652

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

653

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

654

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

656

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

657

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

658

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

659

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

661

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

662

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

663

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

721

void dce110_enable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

724

pipe_ctx->stream->link->cur_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

725

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

726

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

728

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

731

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

733

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

735

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

115

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

119

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

43

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

47

void dce110_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

49

void dce110_disable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

51

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

54

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

56

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

57

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

59

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

61

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

90

bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

92

void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

93

void dce110_set_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

101

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

105

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

124

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

126

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

127

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

128

params.inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

143

static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

148

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

149

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

151

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

155

pipe_ctx->stream->timing.display_color_depth;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

158

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

160

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

161

pipe_ctx->plane_res.xfm, &default_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

182

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

188

if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

192

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

197

static void dce60_get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

200

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

202

switch (pipe_ctx->plane_res.scl_data.format) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

233

const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

240

dce60_get_surface_visual_confirm_color(pipe_ctx, &color);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

243

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

246

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

247

pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

248

pipe_ctx->plane_res.scl_data.lb_params.depth,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

249

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

251

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

257

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

260

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

261

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

265

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

266

&pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

271

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

273

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

274

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

288

dce60_set_default_colors(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

289

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

292

pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

296

pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

298

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

299

(pipe_ctx->plane_res.xfm, &tbl_entry);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

302

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

307

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

310

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

312

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

314

dce60_program_scaler(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

325

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

329

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

335

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

336

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

337

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

340

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

341

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

349

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

350

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

351

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

352

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

353

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

354

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

355

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

356

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

357

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

358

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

359

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

360

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

361

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

362

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

363

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

364

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

370

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

371

pipe_ctx->plane_res.scl_data.viewport.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

372

pipe_ctx->plane_res.scl_data.viewport.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

373

pipe_ctx->plane_res.scl_data.viewport.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

374

pipe_ctx->plane_res.scl_data.viewport.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

375

pipe_ctx->plane_res.scl_data.recout.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

376

pipe_ctx->plane_res.scl_data.recout.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

377

pipe_ctx->plane_res.scl_data.recout.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

378

pipe_ctx->plane_res.scl_data.recout.y);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

396

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

398

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

402

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

403

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

404

pipe_ctx->stream->timing.h_total,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

405

pipe_ctx->stream->timing.v_total,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

406

pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

409

dce60_program_front_end_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

411

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

413

dce60_program_surface_visibility(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

55

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

71

if (res_ctx->pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

73

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

75

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

79

if (pipe_ctx->pipe_idx != underlay_idx) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

89

if (!pipe_ctx->stream->link)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

93

if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

97

if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

103

void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

106

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

112

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

113

!pipe_ctx->stream_res.tg ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

114

!pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

117

if (pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

118

pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1182

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1197

static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1199

struct pipe_ctx *other_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

121

if (!pipe_ctx->wait_is_required)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1224

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1229

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1237

if (pipe_ctx->top_pipe != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

124

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1245

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1247

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1248

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1249

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1250

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1251

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1264

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1265

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1267

calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1268

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1269

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1270

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1271

pipe_ctx->pipe_dlg_param.pstate_keepout,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1272

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1279

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1281

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1282

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

129

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1298

if (pipe_ctx->stream_res.tg->funcs->set_blank_color)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1299

pipe_ctx->stream_res.tg->funcs->set_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1300

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1303

if (pipe_ctx->stream_res.tg->funcs->is_blanked &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1304

!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1305

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1306

hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1307

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1311

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

132

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1329

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1336

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1337

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1341

link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1348

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1349

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1350

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1351

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1353

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1355

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1362

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1363

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

137

if (frame_count - pipe_ctx->wait_frame_count > 2)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1371

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1373

if (pipe_ctx->stream_res.abm)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1374

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1376

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1378

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1379

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1380

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1381

pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1385

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1391

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1393

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

140

vblank_start = pipe_ctx->pipe_dlg_param.vblank_start;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1414

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1415

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1416

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1417

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1427

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1428

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1429

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1430

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1437

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1438

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1439

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1440

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1449

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1450

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1451

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1452

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1474

TRACE_DC_PIPE_STATE(pipe_ctx, MAX_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1487

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1490

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1491

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1495

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1507

if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1508

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1565

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1568

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1569

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1572

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1578

if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1579

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1580

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1587

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1588

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1590

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1591

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1592

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1593

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1594

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1595

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1598

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1604

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1607

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

161

pipe_ctx->wait_is_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1612

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1632

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1638

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1658

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1662

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1675

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1678

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

168

pipe_ctx->next_vupdate = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1689

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

169

pipe_ctx->wait_frame_count = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1696

pipe_ctx->stream != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1697

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1698

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

170

pipe_ctx->wait_is_required = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1710

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1715

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1716

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1718

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1719

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1720

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1727

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1728

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1730

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1735

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1737

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1738

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

179

void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

186

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

187

!pipe_ctx->stream_res.tg ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

188

!pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

191

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

194

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

197

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2001

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2002

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2003

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2011

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2012

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2025

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2027

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2028

bool sec_split = pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2029

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2031

(pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2033

pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2040

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2052

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2057

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2062

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2064

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2065

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

207

pipe_ctx->next_vupdate = vupdate_start;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2075

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2078

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2082

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

212

pipe_ctx->wait_frame_count = cur_frame;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

215

pipe_ctx->wait_frame_count = cur_frame + 1 - max_frame_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2157

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2160

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

217

pipe_ctx->wait_frame_count = cur_frame + 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2197

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

220

pipe_ctx->wait_is_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2238

static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2240

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2249

if (!pipe_ctx->stream_res.stream_enc || !pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2252

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2255

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

227

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

228

struct pipe_ctx *old_pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2286

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

233

old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

234

pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

235

tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2399

static bool is_low_refresh_rate(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2408

static uint8_t get_clock_divider(struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

241

if (pipe_ctx->top_pipe ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

242

!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

243

(!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2430

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

245

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

249

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

251

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2522

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2589

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2671

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2779

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2792

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2795

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2798

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2799

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2803

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2809

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2810

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2811

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2812

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2813

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2817

void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2825

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2829

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2830

} else if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2831

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2835

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2838

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2842

static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2844

if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2845

if (pipe_ctx->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2846

struct pipe_ctx *top = pipe_ctx->top_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2860

static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2868

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2875

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2882

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2883

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2896

if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2897

dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2899

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2903

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2904

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2927

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2933

mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2937

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2939

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2941

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2945

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2955

pipe_ctx->stream->output_color_space)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2956

&& pipe_ctx->plane_state->pre_multiplied_alpha);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2957

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2959

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2968

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2969

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2984

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2986

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3008

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3011

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3015

static void update_scaler(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3018

pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3020

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3021

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3023

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3024

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3029

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3033

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3034

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3035

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3088

pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3100

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3104

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3105

&pipe_ctx->ttu_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3106

&pipe_ctx->rq_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3107

&pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3110

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3111

&pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3114

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3123

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3130

update_scaler(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3138

&pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3139

&pipe_ctx->plane_res.scl_data.viewport_c);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3142

if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3144

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3146

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3147

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3150

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3155

dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3158

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3159

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3160

pipe_ctx->stream->csc_color_matrix.matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3161

pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3186

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3188

if (is_pipe_tree_visible(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3194

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3199

struct stream_resource *stream_res = &pipe_ctx->stream_res;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3200

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3224

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3228

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3236

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3250

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3251

pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3256

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3261

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3262

bool blank = !is_pipe_tree_visible(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3264

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3265

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3266

calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3267

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3268

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3269

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3270

pipe_ctx->pipe_dlg_param.pstate_keepout);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3272

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3273

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3276

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3278

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3281

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3282

dcn10_enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3284

dcn10_update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3286

hws->funcs.set_hdr_multiplier(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3288

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3289

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3290

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3291

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3299

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3300

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3306

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3311

pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3312

tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3318

if (pipe_ctx->top_pipe ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3319

!pipe_ctx->stream || !pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3330

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3331

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3342

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3344

if (!pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3345

!pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3346

pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3347

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3350

false_optc_underflow_wa(dc, pipe_ctx->stream, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3355

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3356

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3359

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3461

void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3484

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3487

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3496

void dcn10_get_position(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3505

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3508

void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3522

pipe_ctx[i]->stream_res.tg->funcs->

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3523

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3569

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3572

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3583

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3584

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3588

pipe_ctx->stream_res.tg->funcs->program_stereo(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3589

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3611

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3620

if (!pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3624

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3627

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3628

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3630

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3654

void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3656

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3657

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3659

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3664

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3665

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3675

!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3700

void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3702

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3703

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3704

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3706

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3707

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3708

.viewport = pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3709

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3710

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3711

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3712

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3713

.stream = pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3716

bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3717

(pipe_ctx->prev_odm_pipe != NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3719

int x_plane = pipe_ctx->plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3720

int y_plane = pipe_ctx->plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3723

bool is_primary_plane = (pipe_ctx->plane_state->layer_index == 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3727

? param.viewport.x : pipe_ctx->plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3728

int clip_width = pipe_ctx->plane_state->clip_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3730

if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3731

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3732

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3755

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3756

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3757

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3758

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3760

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3761

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3762

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3763

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3764

clip_x = (clip_x - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3765

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3766

clip_width = clip_width * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3767

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3783

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3784

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3805

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3809

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3832

pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3833

(pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3840

pipe_ctx->plane_res.scl_data.viewport.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3842

pipe_ctx->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3862

if (pipe_ctx->bottom_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3864

pipe_ctx->bottom_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3867

pipe_ctx->top_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3870

if (pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3872

pipe_ctx->next_odm_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3875

pipe_ctx->prev_odm_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3916

pos_cpy.y = (2 * pipe_ctx->plane_res.scl_data.viewport.y) +

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3917

pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3924

void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3926

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3928

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3929

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3930

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3931

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3934

void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3936

uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3942

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3957

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3958

pipe_ctx->plane_res.dpp, &opt_attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3979

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3981

const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4002

pipe_ctx->pipe_dlg_param.vstartup_start + 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4007

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4011

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4012

int vupdate_pos = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4023

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4027

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4028

int vline_pos = pipe_ctx->stream->periodic_interrupt.lines_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4030

if (pipe_ctx->stream->periodic_interrupt.ref_point == START_V_UPDATE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4036

vline_pos += dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4042

} else if (pipe_ctx->stream->periodic_interrupt.ref_point == START_V_SYNC) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4052

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4054

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4058

dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4063

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4065

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4066

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4077

void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4081

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4086

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4090

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4093

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4101

void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4105

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4106

pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4107

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4189

void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4193

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

857

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

860

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

861

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

104

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

109

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

111

void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

120

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

122

void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

130

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

135

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

139

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

140

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

141

void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

144

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

145

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

146

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

152

void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

154

void dcn10_get_position(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

157

void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

159

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

160

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

171

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

183

void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

184

void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

185

void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

188

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

196

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

207

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

214

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

217

void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

36

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

39

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

42

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

44

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

55

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

59

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

62

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

64

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

67

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

69

void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

72

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

76

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

78

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

80

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

81

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

85

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1002

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1007

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1022

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1025

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1026

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1037

if (pipe_ctx->top_pipe == NULL

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1041

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1063

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1065

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1083

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1085

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1109

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1113

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1121

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1122

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1184

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1188

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1190

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1191

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1192

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1194

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1200

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1201

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1205

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1206

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1211

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1215

struct stream_resource *stream_res = &pipe_ctx->stream_res;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1216

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1220

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1230

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1240

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1269

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1277

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1284

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1293

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1296

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1303

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1307

void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1314

dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1317

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1320

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1323

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1324

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1373

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1376

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1377

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1378

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1379

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1380

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1389

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1392

struct pipe_ctx *temp_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1489

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1490

struct pipe_ctx *new_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1677

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1681

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1682

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1683

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1686

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1688

if (pipe_ctx->update_flags.bits.dppclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1691

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1692

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1699

if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1700

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1705

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1706

&pipe_ctx->global_sync,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1707

&pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1711

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1712

&pipe_ctx->ttu_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1713

&pipe_ctx->rq_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1714

&pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1718

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1719

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1721

if (pipe_ctx->update_flags.bits.hubp_interdependent) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1725

&pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1729

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1730

&pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1734

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1735

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1761

if (pipe_ctx->update_flags.bits.mpcc

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1762

|| pipe_ctx->update_flags.bits.plane_changed

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1766

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1769

if (pipe_ctx->update_flags.bits.scaler ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1773

pipe_ctx->stream->update_flags.bits.scaling) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1774

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1775

ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1777

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1778

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1781

if (pipe_ctx->update_flags.bits.viewport ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1784

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1788

&pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1789

&pipe_ctx->plane_res.scl_data.viewport_c);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1794

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1797

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1798

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1799

pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1801

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1803

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1804

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1807

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1812

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1813

|| pipe_ctx->update_flags.bits.plane_changed

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1814

|| pipe_ctx->stream->update_flags.bits.gamut_remap

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1816

|| pipe_ctx->stream->update_flags.bits.out_csc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1818

dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1822

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1823

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1824

pipe_ctx->stream->csc_color_matrix.matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1828

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1829

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1830

pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1841

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1854

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1855

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1857

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1862

params.subvp_save_surf_addr.addr = &pipe_ctx->plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1863

params.subvp_save_surf_addr.subvp_index = pipe_ctx->subvp_index;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1866

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1869

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1876

static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1878

struct pipe_ctx *other_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1904

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1908

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1909

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1910

dcn20_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1911

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1912

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1913

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1914

pipe_ctx->pipe_dlg_param.pstate_keepout);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1916

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1917

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1919

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1920

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1923

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1928

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1934

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1935

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1936

pipe_ctx->update_flags.bits.odm ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1937

pipe_ctx->stream->update_flags.bits.abm_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1938

hws->funcs.blank_pixel_data(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1939

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1940

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1944

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1945

&& !pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1946

dcn20_program_tg(dc, pipe_ctx, context, hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1948

if (pipe_ctx->update_flags.bits.odm)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1949

hws->funcs.update_odm(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1951

if (pipe_ctx->update_flags.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1953

hws->funcs.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1955

dcn20_enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1961

if (pipe_ctx->update_flags.bits.det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1964

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1968

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1971

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1972

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1973

pipe_ctx->stream->update_flags.raw))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1974

dcn20_update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1976

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1977

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1978

hws->funcs.set_hdr_multiplier(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1980

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1981

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1982

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1983

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1984

pipe_ctx->update_flags.bits.enable))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1985

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1991

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1992

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1993

pipe_ctx->stream->update_flags.bits.out_tf)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1994

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2001

if (pipe_ctx->update_flags.bits.enable

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2002

|| pipe_ctx->update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2004

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2005

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2007

pipe_ctx->stream->timing.display_color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2008

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2010

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2011

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2012

&pipe_ctx->stream->bit_depth_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2013

&pipe_ctx->stream->clamping);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2017

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2018

if (pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2019

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2020

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2021

pipe_ctx->stream->abm_level);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2025

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2026

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2032

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2033

pipe_ctx->stream_res.test_pattern_params.test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2034

pipe_ctx->stream_res.test_pattern_params.color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2035

pipe_ctx->stream_res.test_pattern_params.color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2037

pipe_ctx->stream_res.test_pattern_params.width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2038

pipe_ctx->stream_res.test_pattern_params.height,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2039

pipe_ctx->stream_res.test_pattern_params.offset);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2051

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2060

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2072

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2074

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2087

dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2088

&context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2094

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2096

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2098

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2100

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2112

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2113

&& !context->res_ctx.pipe_ctx[i].top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2114

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2115

&& context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2116

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2120

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2121

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2130

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2131

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2132

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i])

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2136

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2139

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2142

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2143

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2148

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2161

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2186

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

221

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2211

struct pipe_ctx *opp_head)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2254

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2255

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2257

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2260

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2261

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2270

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2284

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2285

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2310

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

233

if (pipe_ctx->stream_res.gsl_group > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

238

pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2388

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2432

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2475

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2477

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2478

&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2479

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2480

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2481

pipe_ctx->dlg_regs.min_dst_y_next_start);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2502

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2504

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2507

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2508

bool blank = !is_pipe_tree_visible(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2510

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2511

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2512

dcn20_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2513

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2514

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2515

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2516

pipe_ctx->pipe_dlg_param.pstate_keepout);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2518

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2519

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2521

if (pipe_ctx->prev_odm_pipe == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2522

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2525

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2528

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2529

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2530

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2531

&pipe_ctx->ttu_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2532

&pipe_ctx->rq_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2533

&pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

260

group_idx = pipe_ctx->stream_res.gsl_group;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2604

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2606

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2613

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2617

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2620

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2628

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2632

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2633

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2635

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

264

pipe_ctx->stream_res.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2643

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2646

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2650

dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2652

pipe_ctx->stream->dmdata_address.quad_part;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2706

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2708

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2709

bool sec_split = pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2710

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2712

(pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2714

pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2722

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2733

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2737

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2742

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2746

(uint8_t)pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2748

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2749

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2759

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2762

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2766

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2769

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2771

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2775

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2779

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2783

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2785

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2786

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2787

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2788

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2791

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2792

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2793

pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2794

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2797

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2803

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2804

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2805

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2812

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2814

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2815

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2826

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2830

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2831

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2836

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2837

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2847

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2848

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2849

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2850

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2853

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2855

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2862

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2863

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2871

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2873

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2875

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2877

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2878

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2879

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

288

if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2880

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2882

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2887

if (dc_is_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

289

pipe_ctx->stream_res.tg->funcs->set_gsl(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2891

&pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2894

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2896

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2897

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

290

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2908

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2909

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2910

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2911

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2912

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2914

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

292

if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2926

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2927

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2928

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

293

pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2936

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2937

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

294

pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2949

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2951

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2953

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2957

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2963

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2964

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2966

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2975

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2976

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2986

if (pipe_ctx->plane_state->format

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

300

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3001

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3002

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3004

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3026

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3029

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

303

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3033

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3036

pipe_ctx->stream->link->cur_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3038

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3039

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

304

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3043

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3044

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3045

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

305

pipe_ctx->plane_res.hubp, flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3051

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3052

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3057

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3059

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3060

dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3061

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3064

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3076

&& pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_FRL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3092

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3093

pipe_ctx->pixel_rate_divider.div_factor1,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3094

pipe_ctx->pixel_rate_divider.div_factor2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3096

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3098

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3100

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3103

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3105

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3123

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3125

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3126

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3128

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3134

if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3135

pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3215

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3219

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3220

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3222

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3223

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3224

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3228

pipe_ctx->stream_res.opp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3234

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3235

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3237

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3252

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3254

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3256

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3257

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3271

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3279

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

380

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

384

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

385

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

386

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

698

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

701

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

702

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

704

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

709

if (pipe_ctx->stream_res.gsl_group != 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

710

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

715

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

724

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

725

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

727

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

728

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

729

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

730

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

731

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

732

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

733

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

734

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

738

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

740

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

741

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

745

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

748

dcn20_plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

757

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

760

void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

762

dcn20_blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

806

static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

808

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

820

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

825

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

835

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

839

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

844

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

845

pipe_ctx->pixel_rate_divider.div_factor1,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

846

pipe_ctx->pixel_rate_divider.div_factor2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

852

if (pipe_ctx->top_pipe != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

857

opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

861

odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

862

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

864

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

865

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

872

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

874

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

875

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

876

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

877

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

878

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

883

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

885

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

892

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

893

dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

894

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

908

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

910

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

911

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

913

pipe_ctx->pipe_dlg_param.vready_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

914

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

915

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

916

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

917

pipe_ctx->pipe_dlg_param.pstate_keepout,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

918

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

922

if (pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

923

bool manual_mode = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) || !is_h_timing_divisible_by_2(stream) || dc_is_virtual_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

924

pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode(pipe_ctx->stream_res.tg, manual_mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

951

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

954

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

965

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

974

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

975

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

976

pipe_ctx->stream_res.tg, event_triggers, 2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

986

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

987

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

988

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

995

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

112

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

122

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

123

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

124

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

131

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

146

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

155

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

160

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

161

struct pipe_ctx *new_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

164

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

168

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

172

struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

34

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

36

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

43

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

44

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

45

bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

47

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

50

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

54

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

55

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

57

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

60

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

64

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

68

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

83

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

86

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

87

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

88

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

91

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

98

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

136

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

140

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

148

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

152

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

153

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

163

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

309

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

313

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

314

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

317

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

318

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

322

pipe_ctx->stream_res.opp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

326

res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

327

pipe_ctx->stream_res.opp = res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

329

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

344

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

346

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

348

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

349

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

380

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

383

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

384

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

388

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

414

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

425

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

427

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

429

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

434

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

438

pipe_ctx, &blnd_cfg.black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

441

pipe_ctx, &blnd_cfg.black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

444

dc, pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

455

if (pipe_ctx->plane_state->global_alpha_value)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

456

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

488

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

489

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

514

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

524

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

530

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

559

void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

561

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

563

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq, &attributes->address);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

565

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

566

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

567

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

568

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

571

void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

574

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

576

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

577

&pipe_ctx->stream->dmdata_address);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

581

dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

583

pipe_ctx->stream->dmdata_address.quad_part;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

594

void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

598

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

60

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

603

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

607

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

609

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing))

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

612

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

62

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

63

bool sec_split = pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

64

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

67

(pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

69

pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

76

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

31

void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

33

void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

35

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

36

void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

37

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

38

void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

41

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

128

void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

130

if (!pipe_ctx->stream->dpms_off)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

133

pipe_ctx->stream->dpms_off = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

134

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

135

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

136

pipe_ctx->stream->dpms_off = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

178

void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

180

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

181

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

182

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

183

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

187

if (pipe_ctx->stream->abm_level == 0 || pipe_ctx->stream->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

192

dce110_set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

211

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

213

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

214

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

215

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

216

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

225

dce110_set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

243

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

246

struct dc_context *dc = pipe_ctx->stream->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

247

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

248

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

249

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

260

dce110_set_backlight_level(pipe_ctx, backlight_level_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

293

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

295

if (pipe_ctx->stream == stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

296

(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

48

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

52

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

53

void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

54

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1211

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1233

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1241

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1267

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1269

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1283

if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

236

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

238

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

257

static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

260

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

261

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

262

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

263

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

318

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

322

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

347

if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

349

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

352

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

358

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

363

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

364

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

369

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

370

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

374

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

377

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

383

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

384

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

388

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

396

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

399

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

400

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

405

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

407

ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

411

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

609

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

611

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

614

if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

615

wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

836

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

838

if (pipe_ctx == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

841

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.hpo_frl_stream_enc != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

842

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->set_avmute(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

843

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

845

if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

846

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

847

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

855

if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

858

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

860

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

861

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

867

void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

873

ASSERT(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

875

if (pipe_ctx->stream_res.stream_enc == NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

876

pipe_ctx->stream_res.hpo_frl_stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

879

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

880

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

882

is_hdmi_frl = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

887

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

888

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

889

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

891

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

892

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

893

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

895

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

896

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

897

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

898

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

900

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

901

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

902

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

906

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

908

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

909

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

911

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

912

struct hpo_frl_stream_encoder *hpo_enc = pipe_ctx->stream_res.hpo_frl_stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

918

if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

919

pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

107

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

113

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

59

bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

63

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

66

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

69

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

71

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

72

void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

73

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

79

void dcn30_hw_set_fva_vrr_adj(struct dc *dc, struct pipe_ctx **pipe_ctx, int num_pipes,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

84

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

99

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

378

void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

384

ASSERT(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

386

if (pipe_ctx->stream_res.stream_enc == NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

387

pipe_ctx->stream_res.hpo_frl_stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

390

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

391

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

393

is_hdmi_frl = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

398

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

399

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

400

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

402

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

403

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

404

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

405

else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

406

if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

407

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

408

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

409

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

411

pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

412

= pipe_ctx->stream->firmware_controlled_hdr_info_packet;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

414

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

415

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

416

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

419

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

420

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

421

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

422

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

424

pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

425

= pipe_ctx->stream->firmware_controlled_hdr_info_packet;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

427

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

428

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

429

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

527

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

533

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

534

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

537

ASSERT(!pipe_ctx->top_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

539

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

541

link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

546

if ((!pipe_ctx->stream->dpms_off || link->link_status.link_active) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

548

dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

553

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

554

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

557

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

559

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

560

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

561

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

562

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

568

if (dc_is_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

571

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

573

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

575

link_hwss->disable_link_output(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

580

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

588

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

589

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

590

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

591

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

597

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

598

if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

601

(dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

602

dc_is_virtual_signal(pipe_ctx->stream->signal)))

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

603

dc->link_srv->set_dsc_enable(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

607

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

609

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

616

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

617

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

622

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

624

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

636

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

637

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

638

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

646

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

647

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

680

void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

694

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

721

bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

724

struct dc_context *dc = pipe_ctx->stream->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

725

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

726

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

727

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

44

void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

54

bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

61

void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

107

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

114

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

115

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

128

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

129

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

135

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

136

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

140

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

141

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

150

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

153

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

156

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

173

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

176

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

179

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

180

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

184

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

187

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

188

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

192

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

193

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

205

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

211

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

212

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

214

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

217

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

329

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

331

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

335

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

336

odm_combine_factor = get_odm_config(pipe_ctx, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

338

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

339

stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

342

} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

348

} else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

372

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

376

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

378

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

380

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

382

pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

383

pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

387

static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

404

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

409

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

411

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

432

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

434

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

441

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

486

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

491

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

492

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

493

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

494

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

495

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

497

&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

498

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

72

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

74

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

75

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

76

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

80

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

90

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

97

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

40

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1026

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1028

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1029

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1030

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1031

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1047

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1057

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1064

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1070

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1075

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1084

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1085

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1098

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1099

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1105

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1106

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1110

dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1111

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1122

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1125

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1128

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1145

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1148

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1151

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1152

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1154

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1157

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1158

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1162

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1163

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1165

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1171

pipe_ctx->stream->timing.pixel_encoding,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1175

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1176

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1178

dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1181

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1190

if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1195

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1198

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1200

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1205

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1206

odm_combine_factor = get_odm_config(pipe_ctx, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1208

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1209

stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1226

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1243

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1247

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1249

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1252

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1254

pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1255

pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1262

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1268

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1271

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1290

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1292

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1299

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1318

void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1322

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1325

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1328

params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1330

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1334

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1338

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1340

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1341

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1342

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1343

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1344

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1349

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1350

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1351

pipe_ctx->stream_res.stream_enc, params.pix_per_cycle > 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1352

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1355

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1358

else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || params.opp_cnt > 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1361

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1362

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1363

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1369

bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1371

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1373

if (!is_h_timing_divisible_by_2(pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1376

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1400

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1405

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1406

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1407

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1408

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1409

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1411

&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1412

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1456

struct pipe_ctx *phantom_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1462

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1487

void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1568

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1569

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1570

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1581

if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1582

(pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1602

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1603

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1620

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1621

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1622

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1624

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1627

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1630

if (pipe_ctx->stream == pipe_ctx_old->stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1631

pipe_ctx->stream->link->link_state_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1635

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1638

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1643

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1747

const struct pipe_ctx *cur_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1748

const struct pipe_ctx *new_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1767

const struct pipe_ctx *cur_pipe, *new_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1771

cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1772

new_pipe = &new_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1852

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1856

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

239

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

361

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

363

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

382

struct pipe_ctx *top_pipe_to_program,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

388

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

392

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

413

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

447

struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

449

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

450

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

451

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

452

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

484

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

486

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

487

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

488

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

530

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

535

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

561

if (pipe_ctx->stream_res.opp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

562

pipe_ctx->stream_res.opp->ctx &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

564

result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

570

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

574

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

575

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

580

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

582

ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

586

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

617

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

636

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

637

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

682

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

742

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

102

struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

104

void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

50

bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

54

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

58

struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

61

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

74

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

76

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

84

struct pipe_ctx *top_pipe_to_program,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

89

void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

92

bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1002

if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1003

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1012

if (pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1013

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1015

if (pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1016

update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1071

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1072

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1168

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[ui];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1452

void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1472

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1475

if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1476

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1477

struct dc *dc = pipe_ctx[i]->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1486

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1494

void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1507

pipe_ctx[i]->stream_res.tg->funcs->

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1508

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1512

void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1522

if (!pipe_ctx[i])

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1525

if (pipe_ctx[i]->stream) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1526

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1533

if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1534

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1535

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal(pipe_ctx[i]->stream_res.tg, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1540

static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1552

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1553

struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1554

const struct dc *dc = pipe_ctx->stream->link->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1556

if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1560

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1595

bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1597

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1599

if (!is_h_timing_divisible_by_2(pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1602

if (should_avoid_empty_tu(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1605

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1647

void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1675

void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1678

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1698

void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1702

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1727

void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1730

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1781

void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1789

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1793

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1794

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1795

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1796

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1797

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1799

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

329

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

331

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

332

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

333

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

339

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

349

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

356

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

365

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

372

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

373

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

386

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

387

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

393

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

394

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

398

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

399

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

408

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

411

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

414

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

431

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

434

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

437

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

438

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

442

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

444

if (!(pipe_ctx->stream_res.hpo_frl_stream_enc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

445

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_fifo_odm_enabled &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

446

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_fifo_odm_enabled(pipe_ctx->stream_res.hpo_frl_stream_enc))) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

448

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

449

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

453

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

454

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

466

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

473

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

474

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

476

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

479

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

657

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

663

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

683

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

687

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

700

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

703

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

714

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

721

pipe_ctx->stream != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

722

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

723

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

735

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

740

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

741

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

743

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

744

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

745

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

752

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

753

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

755

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

760

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

762

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

763

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

834

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

838

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

841

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

844

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

848

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

849

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

861

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

865

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

866

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

867

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

868

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

869

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

875

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

877

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

878

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

886

if (pipe_ctx->stream_res.gsl_group != 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

887

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

892

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

903

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

904

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

905

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

906

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

907

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

908

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

913

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

916

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

917

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

921

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

927

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

932

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

941

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

978

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[ui];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

983

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

986

if (pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

987

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

989

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

990

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

992

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

993

update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

995

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

996

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

998

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

999

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

102

bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

106

void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

107

void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

108

void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

109

void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

112

void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

63

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

64

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

66

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

93

void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

96

void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

99

void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

100

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1000

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1001

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1002

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1003

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1009

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

101

ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1010

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1015

dcn401_enable_stream_calc(pipe_ctx, &dp_hpo_inst, &phyd32clk,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1018

if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1019

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1032

link_hwss->setup_stream_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1037

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1042

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1044

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1046

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1049

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1051

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1076

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

108

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1080

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1081

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1082

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1083

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1084

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1086

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

109

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1125

void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1127

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1128

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1129

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

113

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1131

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1132

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1133

.viewport = pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1134

.recout = pipe_ctx->plane_res.scl_data.recout,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1135

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1136

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1137

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1138

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1139

.stream = pipe_ctx->stream

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1142

bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1143

(pipe_ctx->prev_odm_pipe != NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1145

struct pipe_ctx *prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1154

if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1155

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1156

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1181

x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1182

pipe_ctx->stream->src.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1183

y_pos = pipe_ctx->stream->dst.y + y_pos * pipe_ctx->stream->dst.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1184

pipe_ctx->stream->src.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1198

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1199

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1206

prev_odm_pipe = pipe_ctx->prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1237

pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1238

(pipe_ctx == pipe_ctx->top_pipe->bottom_pipe)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1240

bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1242

x_pos = pipe_ctx->plane_res.scl_data.recout.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1252

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

129

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

130

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1326

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

134

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1421

const struct pipe_ctx *top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1424

const struct pipe_ctx *pipe_ctx = top_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1427

while (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1428

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1429

pipe_ctx->plane_state->dcc.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1430

pipe_ctx->plane_state->flip_immediate &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1431

pipe_ctx->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1437

pipe_ctx = pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1548

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1550

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1551

&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1552

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1553

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1554

pipe_ctx->hubp_regs.dlg_regs.min_dst_y_next_start);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1613

struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1616

struct pipe_ctx *old_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1617

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1618

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1619

struct pipe_ctx *old_otg_master;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1622

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1643

new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1652

struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1654

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1697

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1699

struct pipe_ctx *old_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1700

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1701

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1702

struct pipe_ctx *old_otg_master;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1706

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1719

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1777

new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1789

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1791

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1833

void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1837

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1842

params.opp_cnt = resource_get_odm_slice_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1844

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1846

params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1848

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1849

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1850

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1851

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1852

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1853

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1856

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1858

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1859

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1860

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1896

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1898

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1899

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1916

struct pipe_ctx *dpp_pipe = dpp_pipes[dpp_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1933

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1938

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1950

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1960

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1972

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1985

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1993

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1996

struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1997

struct pipe_ctx *odm_pipe, *mpc_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2000

for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2012

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2013

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2020

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2021

if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2022

pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2029

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2030

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2032

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2048

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2052

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2053

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2055

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2056

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2066

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2067

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2068

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2069

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2072

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2074

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2081

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2082

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2090

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2092

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2094

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2096

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2097

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2098

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2099

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2101

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2107

if (dc_is_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2111

&pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2117

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2125

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2126

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2127

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2128

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2129

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2131

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2160

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2162

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2170

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2171

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2184

static unsigned int dcn401_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2186

struct pipe_ctx *other_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2212

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2216

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2217

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2218

dcn401_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2219

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2220

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2221

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2222

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2225

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2227

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2228

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2231

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2236

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2242

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2243

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2244

pipe_ctx->update_flags.bits.odm ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2245

pipe_ctx->stream->update_flags.bits.abm_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2246

hws->funcs.blank_pixel_data(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2247

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2248

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2252

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2253

&& !pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2254

dcn401_program_tg(dc, pipe_ctx, context, hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2256

if (pipe_ctx->update_flags.bits.odm)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2257

hws->funcs.update_odm(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2259

if (pipe_ctx->update_flags.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2261

hws->funcs.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2263

dc->hwss.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2269

if (pipe_ctx->update_flags.bits.det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2272

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2275

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2278

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2279

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2280

pipe_ctx->stream->update_flags.raw))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2281

dc->hwss.update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2283

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2284

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2285

hws->funcs.set_hdr_multiplier(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2287

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2288

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2289

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2290

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2291

pipe_ctx->update_flags.bits.enable))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2292

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2298

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2299

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2300

pipe_ctx->stream->update_flags.bits.out_tf)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2301

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2308

if (pipe_ctx->update_flags.bits.enable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2309

|| pipe_ctx->update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2311

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2312

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2314

pipe_ctx->stream->timing.display_color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2315

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2317

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2318

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2319

&pipe_ctx->stream->bit_depth_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2320

&pipe_ctx->stream->clamping);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2324

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2325

if (pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2326

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2327

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2328

pipe_ctx->stream->abm_level);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2332

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2333

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2339

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2340

pipe_ctx->stream_res.test_pattern_params.test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2341

pipe_ctx->stream_res.test_pattern_params.color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2342

pipe_ctx->stream_res.test_pattern_params.color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2344

pipe_ctx->stream_res.test_pattern_params.width,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2345

pipe_ctx->stream_res.test_pattern_params.height,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2346

pipe_ctx->stream_res.test_pattern_params.offset);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2348

if (pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2349

&& pipe_ctx->plane_state->update_flags.bits.cm_hist_change

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2351

hws->funcs.program_cm_hist(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2365

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2372

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2373

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2374

pipe_ctx->update_flags.bits.odm ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2375

pipe_ctx->stream->update_flags.bits.abm_level) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2377

dc->hwseq->funcs.blank_pixel_data_sequence(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2378

!pipe_ctx->plane_state || !pipe_ctx->plane_state->visible,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2384

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2385

&& !pipe_ctx->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2388

hwss_add_tg_program_global_sync(seq_state, pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2389

dcn401_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2390

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2391

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2392

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2393

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2396

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2397

hwss_add_tg_wait_for_state(seq_state, pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2400

hwss_add_tg_set_vtg_params(seq_state, pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2404

dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2407

if (pipe_ctx->update_flags.bits.odm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2409

hws->funcs.update_odm_sequence(dc, context, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2412

if (pipe_ctx->update_flags.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2414

dc->hwss.enable_plane_sequence(dc, pipe_ctx, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2417

if (pipe_ctx->update_flags.bits.det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2420

pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2425

pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2429

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2430

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2431

pipe_ctx->stream->update_flags.raw)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2434

dc->hwss.update_dchubp_dpp_sequence(dc, pipe_ctx, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2437

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2438

pipe_ctx->plane_state->update_flags.bits.hdr_mult)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2440

hws->funcs.set_hdr_multiplier_sequence(pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2443

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2444

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2445

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2446

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2447

pipe_ctx->update_flags.bits.enable)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2449

hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2456

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2457

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2458

pipe_ctx->stream->update_flags.bits.out_tf) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2459

hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2467

if (pipe_ctx->update_flags.bits.enable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2468

|| pipe_ctx->update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2470

hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2471

pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2473

hwss_add_opp_program_fmt(seq_state, pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2474

&pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2478

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2479

if (pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2480

hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2482

hwss_add_abm_set_level(seq_state, pipe_ctx->stream_res.abm, pipe_ctx->stream->abm_level);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2486

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2487

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2489

hwss_add_opp_program_bit_depth_reduction(seq_state, odm_opp, true, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2493

pipe_ctx->stream_res.test_pattern_params.test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2494

pipe_ctx->stream_res.test_pattern_params.color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2495

pipe_ctx->stream_res.test_pattern_params.color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2498

pipe_ctx->stream_res.test_pattern_params.width,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2499

pipe_ctx->stream_res.test_pattern_params.height,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2500

pipe_ctx->stream_res.test_pattern_params.offset);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2503

if (pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2504

&& pipe_ctx->plane_state->update_flags.bits.cm_hist_change

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2507

hwss_add_dpp_program_cm_hist(seq_state, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2508

pipe_ctx->plane_state->cm_hist_control, pipe_ctx->plane_state->color_space);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2520

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2527

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2541

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2543

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2556

dc->hwss.detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2557

&context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2563

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2565

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2567

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2569

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2581

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2582

&& !context->res_ctx.pipe_ctx[i].top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2583

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2584

&& context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2585

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2589

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2590

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2599

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2600

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2601

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) ==

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2605

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2608

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2611

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2612

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2617

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2630

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2655

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2686

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2687

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2689

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2692

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2693

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2702

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2716

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2717

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2743

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2823

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2825

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2828

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2829

bool blank = !is_pipe_tree_visible(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2831

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2832

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2833

dcn401_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2834

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2835

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2836

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2837

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2839

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2840

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2842

if (pipe_ctx->prev_odm_pipe == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2843

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2846

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2849

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2850

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2851

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2852

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2853

&pipe_ctx->global_sync,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2854

&pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2862

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2863

struct pipe_ctx *new_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3091

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3094

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3187

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3190

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3191

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3195

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3209

if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3211

hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx->plane_res.mpcc_inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3228

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3233

struct stream_resource *stream_res = &pipe_ctx->stream_res;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3234

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3238

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3249

hwss_add_abm_set_immediate_disable(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3259

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3297

hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3327

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3329

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3332

if (pipe_ctx->plane_state == wb_info->writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3333

mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3459

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3472

if (pipe_ctx->stream_res.gsl_group > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3477

pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3499

group_idx = pipe_ctx->stream_res.gsl_group;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3503

pipe_ctx->stream_res.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3526

hwss_add_tg_set_gsl(seq_state, pipe_ctx->stream_res.tg, gsl);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3527

hwss_add_tg_set_gsl_source_select(seq_state, pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3533

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3536

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3537

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3539

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3544

dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3549

if (pipe_ctx->stream_res.gsl_group != 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3550

dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3553

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3554

hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3557

hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3560

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3563

hwss_add_dpp_dppclk_control(seq_state, pipe_ctx->plane_res.dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3567

dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3568

pipe_ctx->plane_res.hubp, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3570

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3571

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3572

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3573

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3574

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3575

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3576

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3577

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3586

struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3630

void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3638

if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3646

hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3654

hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3658

hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3665

if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3666

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3669

if (pipe_ctx->plane_res.hubp->funcs->hubp_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3670

hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3673

if (pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3674

hwss_add_opp_pipe_clock_control(seq_state, pipe_ctx->stream_res.opp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3677

if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3678

hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx->plane_res.hubp, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3683

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3684

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3685

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3686

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3687

hwss_add_hubp_set_flip_int(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3692

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3697

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3698

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3699

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3702

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3708

if (pipe_ctx->update_flags.bits.dppclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3712

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3713

hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3716

if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3717

hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3721

hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3722

&pipe_ctx->global_sync, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3724

hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3725

&pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3730

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3731

hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3734

if (pipe_ctx->update_flags.bits.hubp_interdependent) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3736

hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3738

hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3742

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3743

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3748

hwss_add_dpp_setup_dpp(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3758

hwss_add_dpp_program_bias_and_scale(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3762

if (pipe_ctx->update_flags.bits.mpcc ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3763

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3769

hws->funcs.update_mpcc_sequence(dc, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3773

if (pipe_ctx->update_flags.bits.scaler ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3777

pipe_ctx->stream->update_flags.bits.scaling) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3778

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3779

ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3780

hwss_add_dpp_set_scaler(seq_state, pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3784

if (pipe_ctx->update_flags.bits.viewport ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3787

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3789

&pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3795

hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3798

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3799

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3800

pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3802

hwss_add_abort_cursor_offload_update(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3804

hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3807

hwss_add_set_cursor_position(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3811

hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3815

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3816

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3817

pipe_ctx->stream->update_flags.bits.gamut_remap ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3819

pipe_ctx->stream->update_flags.bits.out_csc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3822

hwss_add_dpp_program_gamut_remap(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3825

hwss_add_program_output_csc(seq_state, dc, pipe_ctx, pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3826

pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3830

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3831

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3832

pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3843

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3852

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3853

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3857

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_mall_type == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3859

&pipe_ctx->plane_state->address, pipe_ctx->subvp_index);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3863

hwss_add_hubp_update_plane_addr(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3867

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3876

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3879

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3885

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3887

if (!hubp || !pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3890

per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3897

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3898

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3900

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3909

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3910

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3920

if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3927

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3928

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3934

hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3954

hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3957

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3976

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3984

if (!pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3988

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3991

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3992

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3995

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4005

void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4008

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4009

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4018

void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4021

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4032

hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4046

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

408

static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4087

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4122

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4124

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4125

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4136

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4138

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4139

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4147

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4149

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4150

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

416

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4161

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4163

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4164

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

418

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

420

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

421

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

423

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

442

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

446

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

447

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

464

dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

642

void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

645

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

652

bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

655

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

656

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

657

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

664

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

669

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

706

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

710

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

711

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

716

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

718

ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

722

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

740

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

743

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

760

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

766

struct pipe_ctx *opp_heads[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

772

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

776

dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

778

*opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

790

if (pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

804

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

809

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

814

struct pipe_ctx *opp_heads[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

823

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

826

enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

831

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

838

odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

839

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

840

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

841

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

849

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

851

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DTBCLK0, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

858

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

860

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

861

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

862

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

863

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

864

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

870

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

874

patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

875

patched_crtc_timing.h_total = patched_crtc_timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

876

patched_crtc_timing.pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

879

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

880

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

882

(unsigned int)pipe_ctx->global_sync.dcn4x.vready_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

883

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

884

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

885

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

886

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

887

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

890

if (pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

891

pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode(pipe_ctx->stream_res.tg, manual_mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

902

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

903

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

906

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

909

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

914

hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

915

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

92

void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

921

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

922

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

923

pipe_ctx->stream_res.tg, event_triggers, 2);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

933

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

934

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

935

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

96

unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

960

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

967

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

968

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

97

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

970

pipe_ctx->stream->link->cur_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

973

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

974

*dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

975

*phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

978

if (dc_is_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

979

dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

997

void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

101

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

105

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

108

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

115

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

116

struct pipe_ctx *new_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

126

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

130

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

134

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

162

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

169

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

174

struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

179

void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

184

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

189

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

195

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

198

void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

201

void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

35

void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

39

bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

42

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

45

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

46

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

49

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

52

void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

54

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

63

void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

68

const struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

82

void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

85

struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

87

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

89

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

94

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1002

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1005

if (pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1006

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1008

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1009

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1011

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1012

update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1014

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1015

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1017

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1018

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1021

if (pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1022

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1024

if (pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1025

update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1027

if (pipe_ctx->link_res.dio_link_enc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1030

if (pipe_ctx->link_res.hpo_dp_link_enc

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1031

|| pipe_ctx->link_res.hpo_frl_link_enc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1118

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1119

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1466

void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1470

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1474

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1475

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1479

pipe_ctx->stream_res.tg->funcs->program_stereo(

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1480

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

298

void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

300

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

302

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

306

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

313

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

314

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

316

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

325

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

326

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

336

if (pipe_ctx->plane_state->format

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

351

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

352

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

354

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

376

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

379

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

385

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

389

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

479

static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

482

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

484

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

488

pipe_ctx->plane_state->mcm_location = (bPostBlend) ?

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

493

static void dcn42_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

501

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

503

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

505

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

506

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

508

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

560

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

567

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

583

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

594

dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

695

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

699

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

700

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

717

dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

723

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

731

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

893

bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

896

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

897

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

898

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

905

dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

910

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

997

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

11

void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

15

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

18

bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

22

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

28

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

52

void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

106

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

109

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

124

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

131

pipe_ctx->stream != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

132

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

133

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

145

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

150

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

151

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

153

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

154

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

155

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

162

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

163

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

165

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

170

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

172

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

173

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

63

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

69

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

89

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

93

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

113

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

117

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1242

void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1243

void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1245

void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1256

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1261

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1264

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

127

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1270

struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1271

void (*update_pending_status)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1273

void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1277

struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1280

void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1282

void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1285

void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1287

int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1290

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1294

int group_size, struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1298

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1301

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1303

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1304

void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1306

void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

131

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1311

void (*enable_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1312

void (*disable_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1313

void (*blank_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1314

void (*unblank_stream)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1323

void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1325

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1328

void (*update_info_frame)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1329

void (*set_dmdata_attributes)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1330

void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1331

bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1334

void (*set_cursor_position)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1335

void (*set_cursor_attribute)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1336

void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1337

void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1338

void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1339

void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1340

void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1343

void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1346

void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1347

void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1350

void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

136

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1386

void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1387

void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1390

void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1400

bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1403

void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1405

void (*set_pipe)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

142

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1455

struct pipe_ctx *top_pipe_to_program,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1465

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1476

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1480

struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1481

void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1497

const struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1505

void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1509

void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1512

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1513

struct pipe_ctx *new_pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1515

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1518

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1522

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1525

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1529

struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1532

struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1563

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1566

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1570

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1573

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1579

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1582

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1587

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1591

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1595

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1600

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1604

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1610

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1613

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1626

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

174

const struct pipe_ctx *top_pipe_to_program;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1920

struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1926

struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1929

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1932

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1935

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1938

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1941

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1944

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1947

struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1965

struct dc *dc, struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1971

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1974

struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2027

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2045

struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2057

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2066

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

207

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2082

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

215

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

220

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2275

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2311

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2315

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2327

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2331

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2335

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2374

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2378

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2382

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2387

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2391

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2394

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2397

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2400

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2403

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2406

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2409

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2439

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2446

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2449

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2453

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2465

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2468

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2476

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

281

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

288

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

293

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

330

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

357

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

377

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

38

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

394

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

404

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

409

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

708

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

71

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

729

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

734

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

740

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

744

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

750

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

765

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

770

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

775

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

792

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

797

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

802

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

806

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

810

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

814

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

818

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

82

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

822

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

826

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

871

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

876

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

88

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

890

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

894

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

904

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

93

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

98

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

105

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

108

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

112

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

118

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

119

void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

121

bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

132

void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

162

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

164

struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

174

void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

175

void (*set_hdr_multiplier_sequence)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

181

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

185

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

190

bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

192

bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

194

bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

197

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

199

void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

206

unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

213

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

216

bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

218

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

221

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

224

void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

225

void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

226

void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

229

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

56

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

77

void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

78

void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

83

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

86

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

88

void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

89

void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

92

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

95

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

143

struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

147

const struct pipe_ctx *opp_head_pipe);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

149

struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

153

const struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

156

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

221

void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

227

unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

236

struct pipe_ctx *pipes,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

487

struct pipe_ctx *top_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

488

struct pipe_ctx *bottom_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

489

struct pipe_ctx *next_odm_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

490

struct pipe_ctx *prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

534

struct pipe_ctx pipe_ctx[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

551

struct pipe_ctx temp_pipe;

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

35

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

484

const struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

42

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

38

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

49

void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

52

void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

77

void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

78

void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

79

void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

83

void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

85

void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

86

void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

158

void (*set_dpms_on)(struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

159

void (*set_dpms_off)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

165

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

167

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

168

void (*set_dsc_on_stream)(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

169

bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

170

bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

201

bool (*dp_is_128b_132b_signal)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

124

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

126

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

132

void resource_build_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

159

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

172

bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

295

bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);

drivers/gpu/drm/amd/display/dc/inc/resource.h

323

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/inc/resource.h

387

struct pipe_ctx *resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/inc/resource.h

397

int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/inc/resource.h

399

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

407

int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/inc/resource.h

409

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

418

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

425

struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

432

struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

438

struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

445

int resource_get_mpc_slice_index(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

452

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

459

int resource_get_odm_slice_count(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

462

int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/inc/resource.h

465

struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

468

struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

471

int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/inc/resource.h

485

bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,

drivers/gpu/drm/amd/display/dc/inc/resource.h

486

const struct pipe_ctx *otg_master_b);

drivers/gpu/drm/amd/display/dc/inc/resource.h

501

const struct pipe_ctx *cur_otg_master);

drivers/gpu/drm/amd/display/dc/inc/resource.h

513

const struct pipe_ctx *cur_opp_head);

drivers/gpu/drm/amd/display/dc/inc/resource.h

574

struct pipe_ctx *resource_find_free_secondary_pipe_legacy(

drivers/gpu/drm/amd/display/dc/inc/resource.h

577

const struct pipe_ctx *primary_pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

597

struct pipe_ctx *pipe_ctx_old,

drivers/gpu/drm/amd/display/dc/inc/resource.h

598

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

638

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/inc/resource.h

639

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/inc/resource.h

649

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

655

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

665

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

220

tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

199

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

200

struct pipe_ctx *pipe_ctx = &pipes[0];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

243

for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

456

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

462

enum dc_color_depth color_depth = pipe_ctx->

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

465

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

466

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

472

pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

473

controller_test_pattern = pipe_ctx->stream_res.test_pattern_params.test_pattern;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

483

pipe_ctx->stream->bit_depth_params = params;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

484

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

486

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

492

controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

499

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

521

resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

522

pipe_ctx->stream->bit_depth_params = params;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

523

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

525

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

531

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

631

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

632

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

647

pipe_ctx = &pipes[i];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

652

if (pipe_ctx == NULL)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

661

set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

662

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

668

pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

693

dp_set_hw_lane_settings(link, &pipe_ctx->link_res, p_link_settings, DPRX);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

70

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

705

link->dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

708

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

852

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

855

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

856

if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

861

inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

868

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

869

pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

872

pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

874

link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

875

pipe_ctx->stream->output_color_space = color_space;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

876

link_hwss->setup_stream_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

878

if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

880

pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

882

pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

885

pipe_ctx->stream->vsc_infopacket.sb[16] &= 0xf0;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

887

pipe_ctx->stream->vsc_infopacket.sb[16] |= 1;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

889

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

890

link->dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

894

set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

895

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

896

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

898

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

900

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

903

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

904

if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

909

inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

916

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

917

pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

934

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

949

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

101

pipe_ctx->stream->signal, false);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

103

if (!dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

106

pipe_ctx->stream_res.stream_enc->id,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

109

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

110

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

111

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

116

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

118

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

119

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

126

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

141

pipe_ctx->stream_res.audio != NULL);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

254

void setup_dio_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

257

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

258

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

259

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

261

&pipe_ctx->stream->audio_info);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

263

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

264

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

266

&pipe_ctx->stream->audio_info,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

270

void enable_dio_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

272

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

273

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

274

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

276

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

277

pipe_ctx->stream_res.stream_enc, false);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

279

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

280

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

281

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

285

void disable_dio_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

287

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

288

pipe_ctx->stream_res.stream_enc, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

290

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

291

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

292

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

293

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

295

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

296

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

299

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

300

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

301

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

39

void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

42

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

49

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

51

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

52

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

54

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

55

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

61

if (!dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

63

pipe_ctx->stream_res.stream_enc->id, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

64

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

65

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

69

pipe_ctx->stream->signal, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

75

pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

80

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

82

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

83

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

85

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

86

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

35

void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

37

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

38

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

39

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

55

void setup_dio_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

57

void enable_dio_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

58

void disable_dio_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

182

void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

186

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

187

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

189

&pipe_ctx->stream->audio_info);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

192

void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

194

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

195

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

198

void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

200

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

201

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

202

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

33

void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

37

pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

39

pipe_ctx->link_res.hpo_dp_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

46

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

51

pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

52

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

56

pipe_ctx->stream->link, link_settings);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

74

void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

76

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

77

struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

83

void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

85

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

90

void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

92

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

93

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

31

void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

33

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

36

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

39

void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

40

void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

41

void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

53

void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

55

void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

56

void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

29

static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

31

struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

32

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

33

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

41

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding) {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

42

temp_stream->timing.h_addressable = stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

43

temp_stream->timing.h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

47

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

67

static void setup_hpo_frl_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

70

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

71

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

73

&pipe_ctx->stream->audio_info,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

77

static void enable_hpo_frl_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

79

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->audio_mute_control(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

80

pipe_ctx->stream_res.hpo_frl_stream_enc, false);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

83

static void disable_hpo_frl_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

85

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->audio_mute_control(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

86

pipe_ctx->stream_res.hpo_frl_stream_enc, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

88

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

89

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

90

pipe_ctx->stream_res.hpo_frl_stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

28

void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

30

(void)pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

33

void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

35

(void)pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

38

void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

40

(void)pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h

30

void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h

31

void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h

32

void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

930

struct pipe_ctx *pipes =

drivers/gpu/drm/amd/display/dc/link/link_detection.c

931

link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1103

static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1108

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1113

kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1298

static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1300

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1305

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1318

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1320

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1335

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1336

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1340

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1345

remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1346

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1358

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1376

static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1378

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1385

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1401

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1402

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1406

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1420

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1439

pbn = get_pbn_from_timing(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1445

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1447

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

157

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1582

static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1585

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1590

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1600

link_hwss->ext.set_throttled_vcp_size(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1603

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1617

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1621

proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1634

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1651

link_hwss->ext.set_throttled_vcp_size(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1654

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1665

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1667

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1673

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1682

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1684

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1702

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1703

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1707

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1721

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1732

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1734

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1741

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1753

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1754

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1769

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1790

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1792

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1849

static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1851

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1859

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1860

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1871

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1872

unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1876

eng_id = pipe_ctx->stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1889

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1912

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1913

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1917

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1918

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1919

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1923

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1927

static enum dc_status enable_link_hdmi_frl(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1931

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1932

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1941

(!(pipe_ctx->stream_res.hpo_frl_stream_enc)))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1945

hdmi_frl_decide_link_settings(stream, &stream->link->frl_link_settings, &pipe_ctx->dsc_padding_params);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1949

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 166667;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1953

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 333333;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1956

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 444444;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1959

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 555555;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1962

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 666667;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1965

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 888889;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1968

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1111111;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1971

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1333333;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1977

stream->phy_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1988

(pipe_ctx->stream_res.hpo_frl_stream_enc->id - ENGINE_ID_HPO_0),

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1997

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2016

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2019

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_enable(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2020

pipe_ctx->stream_res.hpo_frl_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2021

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

203

const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2031

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2033

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2038

&pipe_ctx->link_config.dp_link_settings;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2073

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2077

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2082

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2092

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2120

pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2121

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2134

dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2155

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2157

return enable_link_dp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

216

struct pipe_ctx *pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2160

static void enable_link_lvds(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2162

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2173

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2174

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2181

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2183

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

219

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2205

return enable_link_dp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2208

static enum dc_status enable_link_analog(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2210

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2213

link, pipe_ctx->stream->timing.pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2218

static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2220

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2223

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2225

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2226

&pipe_ctx->link_config.dp_link_settings);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

223

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2232

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2235

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2249

disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2251

switch (pipe_ctx->stream->signal) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2253

status = enable_link_dp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2256

status = enable_link_edp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2259

status = enable_link_dp_mst(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2265

enable_link_hdmi(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2274

status = enable_link_hdmi_frl(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2277

enable_link_lvds(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2281

status = enable_link_analog(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2284

status = enable_link_virtual(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2291

pipe_ctx->stream->link->link_status.link_active = true;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2364

void link_set_dpms_off(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2366

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2367

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2369

struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2372

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2374

ASSERT(is_master_pipe_for_link(link, pipe_ctx));

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2376

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2377

vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2378

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2379

vpg = pipe_ctx->stream_res.hpo_frl_stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2380

if (dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2383

if (pipe_ctx->stream->sink) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2384

if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2385

pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2387

pipe_ctx->stream->sink->edid_caps.display_name,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2388

pipe_ctx->stream->signal, link->link_index, link->sink_count);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2394

if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2395

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2396

set_avmute(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2399

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2401

update_psp_stream_config(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2402

dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2404

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2405

deallocate_usb4_bandwidth(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2407

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2408

deallocate_mst_payload(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2409

else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2410

dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2411

update_sst_payload(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2413

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2415

enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2436

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2437

!dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2446

disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2447

dc->hwss.disable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2449

dc->hwss.disable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2450

disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2452

edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2454

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2455

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2456

link_set_dsc_enable(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2457

else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2458

link_set_dsc_on_stream(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2460

if (dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2461

if (pipe_ctx->stream_res.tg->funcs->set_out_mux)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2462

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2471

enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2479

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2481

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2482

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2485

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2487

struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2488

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2490

pipe_ctx->stream->apply_edp_fast_boot_optimization;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2492

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2494

ASSERT(is_master_pipe_for_link(link, pipe_ctx));

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2496

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2497

vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2498

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2499

vpg = pipe_ctx->stream_res.hpo_frl_stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2500

if (dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2503

if (pipe_ctx->stream->sink) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2504

if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2505

pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2507

pipe_ctx->stream->sink->edid_caps.display_name,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2508

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2519

if (!dc_is_virtual_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2520

&& !dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2521

&& !dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2525

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2528

pipe_ctx->stream->link->link_state_valid = true;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2530

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2531

hdmi_frl_decide_link_settings(stream, &stream->link->frl_link_settings, &pipe_ctx->dsc_padding_params);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2533

if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2534

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2536

else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2540

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2543

link_hwss->setup_stream_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2545

pipe_ctx->stream->apply_edp_fast_boot_optimization = false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2551

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2552

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2554

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2558

if (pipe_ctx->stream->apply_seamless_boot_optimization) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2559

pipe_ctx->stream->dpms_off = false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2562

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2563

enable_stream_features(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2564

dc->hwss.enable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2567

update_psp_stream_config(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2572

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2574

!pipe_ctx->stream->timing.flags.DSC &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2575

!pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2576

pipe_ctx->stream->dpms_off = false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2577

update_psp_stream_config(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2589

if (pipe_ctx->stream->dpms_off)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2607

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2608

if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2609

dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2610

link_set_dsc_enable(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2616

status = enable_link(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2620

pipe_ctx->stream->link->link_index,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2630

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2632

disable_link(stream->link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2633

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2639

if (pipe_ctx->stream->timing.flags.DSC &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2640

dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2642

link_set_dsc_on_stream(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2645

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2646

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2654

if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2655

dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2656

dp_is_128b_132b_signal(pipe_ctx))) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2661

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2665

dc->hwss.enable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2668

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2669

if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2670

dc_is_virtual_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2671

dp_set_dsc_on_rx(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2672

link_set_dsc_pps_packet(pipe_ctx, true, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2676

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2677

dp_set_hblank_reduction_on_rx(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2679

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2680

allocate_usb4_bandwidth(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2682

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2683

allocate_mst_payload(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2684

else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2685

dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2686

update_sst_payload(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2693

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2697

dc->hwss.unblank_stream(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2698

&pipe_ctx->stream->link->cur_link_settings);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2703

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2704

enable_stream_features(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2705

update_psp_stream_config(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2707

dc->hwss.enable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2709

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2710

set_avmute(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

531

static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

533

struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

534

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

537

dp_get_panel_mode(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

541

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

542

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

548

config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

551

config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

552

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

553

config.dig_fe = (uint8_t)pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

556

config.stream_enc_idx = (uint8_t)(pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

557

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

559

(uint8_t)(pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

560

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

562

(uint8_t)(pipe_ctx->stream_res.hpo_frl_stream_enc->id - ENGINE_ID_HPO_0);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

565

config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

566

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

567

config.dig_be = (uint8_t)pipe_ctx->stream_res.hpo_frl_stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

571

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

572

config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

573

if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

574

config.link_enc_idx = (uint8_t)pipe_ctx->stream->link->hpo_frl_link_enc->inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

577

if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

578

config.dio_output_idx = (uint8_t)(pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

585

pipe_ctx->stream->link->dc, link_enc->transmitter);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

586

if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

592

config.mst_enabled = (pipe_ctx->stream->signal ==

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

594

config.frl_enabled = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

595

config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

596

config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

601

config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

638

static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

640

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

642

if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

645

if (pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

648

dc->hwss.set_avmute(pipe_ctx, enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

686

static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

688

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

689

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

699

static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

701

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

702

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

716

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

721

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

722

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

723

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

724

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

740

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

749

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

754

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

763

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

764

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

774

dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

779

if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

780

DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

782

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

783

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

794

DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

803

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

804

pipe_ctx->stream_res.hpo_frl_stream_enc, &patched_crtc_timing, &dsc_packed_pps[0]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

808

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

810

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

816

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

817

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

822

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

823

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

824

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

829

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

830

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

831

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

833

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

834

pipe_ctx->stream_res.stream_enc, false, NULL, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

838

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

839

pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

842

for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

881

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

883

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

884

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

886

if (!pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

906

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

908

dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

913

DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

914

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

915

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

916

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

921

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

922

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

929

DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.hpo_frl_stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

930

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

931

pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, &dsc_packed_pps[0]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

937

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

938

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

939

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

944

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

945

pipe_ctx->stream_res.stream_enc, false, NULL, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

949

pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

950

pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

956

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

958

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

961

if (!pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

968

link_set_dsc_on_stream(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

972

dp_set_dsc_on_rx(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

973

link_set_dsc_on_stream(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

980

bool link_update_dsc_config(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

982

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

984

if (!pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

989

link_set_dsc_on_stream(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

990

link_set_dsc_pps_packet(pipe_ctx, true, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

994

static void enable_stream_features(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

996

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

998

if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

32

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

33

void link_set_dpms_off(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

42

struct pipe_ctx *pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

43

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

44

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

45

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

50

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

51

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

52

bool link_update_dsc_config(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

29

static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

31

struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc;

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

32

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

33

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

37

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/link/link_resource.c

36

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/link/link_resource.c

41

pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/link_validation.c

677

if (context->res_ctx.pipe_ctx[i].stream && (context->res_ctx.pipe_ctx[i].stream == stream)) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

678

dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

378

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

381

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

382

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

383

pipe_ctx->link_res.hpo_dp_link_enc &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

384

dc_is_dp_signal(pipe_ctx->stream->signal));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

68

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

328

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

127

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

133

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

218

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

219

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

221

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

222

*inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

280

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

286

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

287

dc->current_state->res_ctx.pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

288

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

289

dc_is_dp_sst_signal(dc->current_state->res_ctx.pipe_ctx[i].stream->link->connector_signal)) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

290

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

296

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

308

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

309

cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

312

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

313

cmd.pr_copy_settings.data.otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

321

cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

343

if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

344

cmd.pr_copy_settings.data.dsc_slice_height = (uint16_t)((pipe_ctx->stream->timing.v_addressable +

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

345

pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

346

pipe_ctx->stream->timing.dsc_cfg.num_slices_v);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

60

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

61

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

62

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1624

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1630

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1636

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1650

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1663

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1665

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1674

edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1679

dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1685

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1691

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1703

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1757

dp_disable_link_phy(link, &pipe_ctx->link_res, signal);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

35

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1032

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1038

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1195

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1196

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1199

abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1282

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1285

struct link_resource *link_res = &pipe_ctx->link_res;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1286

struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

527

static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

531

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

534

if (dc->current_state->res_ctx.pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

535

if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

536

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

542

return pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

556

struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

561

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

565

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

574

pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

799

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

806

pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

78

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

892

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

894

struct pipe_ctx *link_pipe = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

895

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

904

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

403

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

405

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

406

if (pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

531

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

533

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

534

if (pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

854

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

856

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

859

dce110_resource_build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

861

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

878

stream = context->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1131

static struct pipe_ctx *dce110_acquire_underlay(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1135

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1143

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1145

if (res_ctx->pipe_ctx[underlay_idx].stream)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1148

pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1149

pipe_ctx->plane_res.mi = pool->mis[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1151

pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1152

pipe_ctx->stream_res.opp = pool->opps[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1153

pipe_ctx->pipe_idx = (uint8_t)underlay_idx;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1155

pipe_ctx->stream = stream;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1157

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1163

(uint8_t)pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1171

pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1178

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1181

pipe_ctx->stream_res.tg->funcs->enable_advanced_request(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1182

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1186

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1194

pipe_ctx->stream_res.tg->funcs->set_blank_color(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1195

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1199

return pipe_ctx;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

888

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

891

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

899

if (dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

901

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

902

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

924

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

926

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

927

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

928

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

929

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

930

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

931

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

932

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

933

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

936

static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

938

if (pipe_ctx->pipe_idx != underlay_idx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

940

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

942

if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

952

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

954

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

957

if (!is_surface_pixel_format_supported(pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

961

dce110_resource_build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

965

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

986

context->res_ctx.pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h

41

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

881

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

883

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

886

dce110_resource_build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

888

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

909

context->res_ctx.pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

973

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

976

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

979

if (dc_is_dp_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

980

|| dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

981

pipe_ctx->clock_source =

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

983

else if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

984

pipe_ctx->clock_source =

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

988

pipe_ctx->clock_source = find_matching_pll(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

993

if (pipe_ctx->clock_source == NULL)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

999

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1030

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1033

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1036

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1037

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1064

static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1067

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1069

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1070

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1071

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1072

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1074

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1076

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1077

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1078

build_clamping_params(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1087

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1089

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1092

build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1115

static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1119

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1123

struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1124

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1304

unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1306

return pipe_ctx->pipe_dlg_param.vstartup_start;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

54

unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1252

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1255

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1256

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1259

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1260

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1263

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1273

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1274

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1290

else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1293

if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1300

if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1301

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1303

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1318

void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1320

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1321

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1322

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1323

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1324

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1327

static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1329

struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1332

pool->funcs->build_pipe_pix_clk_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1334

dcn20_build_pipe_pix_clk_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1337

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1339

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1340

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1341

build_clamping_params(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1350

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1352

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1356

status = build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1369

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1422

struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1424

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1427

if (pipe_ctx->stream != dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1430

if (pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1433

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1436

if (!pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1451

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1455

if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1456

pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1458

if (pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1459

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1463

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1518

struct pipe_ctx *prev_odm_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1519

struct pipe_ctx *next_odm_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1573

struct pipe_ctx *primary_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1574

struct pipe_ctx *secondary_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1578

struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1646

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1650

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1656

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1657

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1688

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1689

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1691

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1694

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1698

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1701

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1707

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1712

if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1718

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1721

const struct pipe_ctx *primary_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1724

struct pipe_ctx *secondary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1736

if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1737

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1738

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1739

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1744

dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1745

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1746

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1747

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1760

if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1761

&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1764

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1765

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1785

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1786

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1805

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1806

struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1813

struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1834

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1835

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1883

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1907

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1925

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1944

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1956

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2099

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2100

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2199

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2203

const struct pipe_ctx *opp_head)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2207

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2208

struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2266

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

139

struct pipe_ctx *primary_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

140

struct pipe_ctx *secondary_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

144

struct pipe_ctx *prev_odm_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

145

struct pipe_ctx *next_odm_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

150

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

153

const struct pipe_ctx *primary_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

168

void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

61

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

65

const struct pipe_ctx *opp_head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

67

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1033

static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1037

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1040

struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1041

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

856

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

857

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

880

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

881

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1490

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1547

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1551

struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1568

wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1682

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1683

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1741

static struct pipe_ctx *dcn30_find_split_pipe(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1746

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1749

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1750

pipe = &context->res_ctx.pipe_ctx[old_index];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1756

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1757

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1758

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1759

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1773

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1774

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1863

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1864

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1884

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1909

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1910

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1929

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1930

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1931

struct pipe_ctx *hsplit_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1972

struct pipe_ctx *pipe_4to1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2015

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1804

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1814

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1816

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2420

struct pipe_ctx *pipes,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

72

struct pipe_ctx *pipes,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1804

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1808

if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1809

res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1810

(res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1811

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1812

res_ctx->pipe_ctx[i].plane_state->src_rect.height

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1813

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1816

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1830

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1842

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1844

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1906

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1773

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1783

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1785

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1814

struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1859

struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1898

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2042

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2074

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2075

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2089

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2091

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2110

odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2814

const struct pipe_ctx *new_opp_head)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2816

const struct pipe_ctx *cur_opp_head;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2819

cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2847

static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2850

const struct pipe_ctx *primary_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2853

struct pipe_ctx *secondary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2854

struct pipe_ctx *next_odm_mpo_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2856

struct pipe_ctx *old_primary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2879

old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2885

if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2887

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2898

if ((res_ctx->pipe_ctx[i].stream == NULL) &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2900

secondary_pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2909

static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2913

const struct pipe_ctx *head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2916

struct pipe_ctx *idle_pipe, *pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2932

pipe = &old_ctx->pipe_ctx[head_index];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2933

if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2934

idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2958

const struct pipe_ctx *new_otg_master)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2960

const struct pipe_ctx *cur_otg_master;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2963

cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2981

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2985

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2989

struct pipe_ctx *free_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2999

free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3018

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3022

const struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3027

struct pipe_ctx *free_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3030

free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

118

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

137

bool dcn32_is_center_timing(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

138

bool dcn32_is_psr_capable(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

144

const struct pipe_ctx *new_opp_head);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

146

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

150

const struct pipe_ctx *opp_head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

152

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

156

const struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

159

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

171

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

179

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

115

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

137

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

138

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

160

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

177

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

202

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

213

bool dcn32_is_center_timing(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

234

bool dcn32_is_psr_capable(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

261

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

263

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

264

if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

266

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

276

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

278

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

279

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

341

if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

349

current_plane = context->res_ctx.pipe_ctx[j].plane_state;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

351

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

352

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

360

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

361

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

371

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

388

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

393

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

396

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

41

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

45

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

49

switch (pipe_ctx->stream->cursor_attributes.color_format) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

593

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

620

static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

658

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

68

if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

719

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

758

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

763

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

765

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1861

static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1863

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1865

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1866

struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1870

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1871

pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1873

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1878

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1879

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1901

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1902

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1903

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1904

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1940

unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1942

return pipe_ctx->global_sync.dcn4x.vstartup_lines;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

33

unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1655

static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1657

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1659

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1660

struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1664

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1665

pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1667

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1672

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1673

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1695

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1696

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1697

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1698

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

22

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1620

static void dcn42b_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1622

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1624

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1625

struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1629

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1630

pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1632

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1637

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1638

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1660

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1661

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1662

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1663

&pipe_ctx->pll_settings);