drivers/gpu/drm/i915/display/g4x_dp.c
1191
return intel_de_read(display, SDEISR) & bit;
drivers/gpu/drm/i915/display/g4x_dp.c
1214
return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
drivers/gpu/drm/i915/display/g4x_dp.c
1222
return intel_de_read(display, DEISR) & bit;
drivers/gpu/drm/i915/display/g4x_dp.c
124
intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
drivers/gpu/drm/i915/display/g4x_dp.c
1266
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
174
bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
drivers/gpu/drm/i915/display/g4x_dp.c
185
bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;
drivers/gpu/drm/i915/display/g4x_dp.c
258
u32 val = intel_de_read(display, TRANS_DP_CTL(p));
drivers/gpu/drm/i915/display/g4x_dp.c
282
val = intel_de_read(display, dp_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
349
tmp = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
354
u32 trans_dp = intel_de_read(display,
drivers/gpu/drm/i915/display/g4x_dp.c
394
if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)
drivers/gpu/drm/i915/display/g4x_dp.c
420
(intel_de_read(display, intel_dp->output_reg) &
drivers/gpu/drm/i915/display/g4x_dp.c
685
u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
159
tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
223
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
282
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
330
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
386
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/hsw_ips.c
281
crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
drivers/gpu/drm/i915/display/hsw_ips.c
351
if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
22
display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
23
display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
26
display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
29
display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
32
display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
33
display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
36
display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
74
display->restore.saveDSPARB = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_plane.c
1186
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1206
offset = intel_de_read(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1208
base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;
drivers/gpu/drm/i915/display/i9xx_plane.c
1211
offset = intel_de_read(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1214
offset = intel_de_read(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1216
base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;
drivers/gpu/drm/i915/display/i9xx_plane.c
1219
base = intel_de_read(display, DSPADDR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1225
val = intel_de_read(display, PIPESRC(display, pipe));
drivers/gpu/drm/i915/display/i9xx_plane.c
1229
val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
572
error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
573
error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
574
error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
584
error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
585
error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
595
error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
596
error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
739
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_wm.c
167
was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
drivers/gpu/drm/i915/display/i9xx_wm.c
171
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
175
val = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
184
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
195
was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
2381
fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;
drivers/gpu/drm/i915/display/i9xx_wm.c
295
dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
296
dsparb2 = intel_de_read(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
301
dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
302
dsparb2 = intel_de_read(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
307
dsparb2 = intel_de_read(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
308
dsparb3 = intel_de_read(display, DSPARB3);
drivers/gpu/drm/i915/display/i9xx_wm.c
326
u32 dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
342
u32 dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3500
hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));
drivers/gpu/drm/i915/display/i9xx_wm.c
359
u32 dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3666
tmp = intel_de_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3672
tmp = intel_de_read(display, DSPFW2(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3680
tmp = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3694
tmp = intel_de_read(display, VLV_DDL(pipe));
drivers/gpu/drm/i915/display/i9xx_wm.c
3706
tmp = intel_de_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3712
tmp = intel_de_read(display, DSPFW2(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3717
tmp = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3721
tmp = intel_de_read(display, DSPFW7_CHV);
drivers/gpu/drm/i915/display/i9xx_wm.c
3725
tmp = intel_de_read(display, DSPFW8_CHV);
drivers/gpu/drm/i915/display/i9xx_wm.c
3729
tmp = intel_de_read(display, DSPFW9_CHV);
drivers/gpu/drm/i915/display/i9xx_wm.c
3733
tmp = intel_de_read(display, DSPHOWM);
drivers/gpu/drm/i915/display/i9xx_wm.c
3745
tmp = intel_de_read(display, DSPFW7);
drivers/gpu/drm/i915/display/i9xx_wm.c
3749
tmp = intel_de_read(display, DSPHOWM);
drivers/gpu/drm/i915/display/i9xx_wm.c
3770
wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
3914
wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
drivers/gpu/drm/i915/display/i9xx_wm.c
4080
hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4081
hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4082
hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4084
hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4086
hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);
drivers/gpu/drm/i915/display/i9xx_wm.c
4087
hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);
drivers/gpu/drm/i915/display/i9xx_wm.c
4091
hw->partitioning = (intel_de_read(display, WM_MISC) &
drivers/gpu/drm/i915/display/i9xx_wm.c
4095
hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &
drivers/gpu/drm/i915/display/i9xx_wm.c
4100
!(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
drivers/gpu/drm/i915/display/i9xx_wm.c
680
reg = intel_de_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
707
reg = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/icl_dsi.c
1125
tmp = intel_de_read(display, UTIL_PIN_CTL);
drivers/gpu/drm/i915/display/icl_dsi.c
1187
tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1361
tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1555
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1610
!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
drivers/gpu/drm/i915/display/icl_dsi.c
1737
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1757
tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
201
tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
265
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
275
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
313
dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
drivers/gpu/drm/i915/display/icl_dsi.c
460
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
471
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/icl_dsi.c
491
tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
508
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
519
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
62
return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
drivers/gpu/drm/i915/display/icl_dsi.c
628
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
644
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
660
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
681
val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
69
return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
drivers/gpu/drm/i915/display/icl_dsi.c
712
tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
828
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_alpm.c
552
alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_audio.c
1332
aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);
drivers/gpu/drm/i915/display/intel_audio.c
250
tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
drivers/gpu/drm/i915/display/intel_audio.c
263
tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
drivers/gpu/drm/i915/display/intel_audio.c
273
eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);
drivers/gpu/drm/i915/display/intel_audio.c
314
(intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);
drivers/gpu/drm/i915/display/intel_audio.c
351
tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_audio.c
374
tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_audio.c
519
val = intel_de_read(display, AUD_CONFIG_BE);
drivers/gpu/drm/i915/display/intel_backlight.c
1147
if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {
drivers/gpu/drm/i915/display/intel_backlight.c
1240
alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
drivers/gpu/drm/i915/display/intel_backlight.c
1242
alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
drivers/gpu/drm/i915/display/intel_backlight.c
1245
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
1248
pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1251
cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1295
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
1298
pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1309
cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1326
ctl = intel_de_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
1368
ctl2 = intel_de_read(display, BLC_PWM_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1372
ctl = intel_de_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
1404
ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
1407
ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
1436
pwm_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_backlight.c
1441
val = intel_de_read(display, UTIL_PIN_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
1448
intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
1490
return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
drivers/gpu/drm/i915/display/intel_backlight.c
1515
pwm_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_backlight.c
1520
intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
153
return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
160
return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
169
val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
191
return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
199
return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
217
val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
227
tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
257
tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;
drivers/gpu/drm/i915/display/intel_backlight.c
268
tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
357
tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
482
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
528
cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
537
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
577
ctl = intel_de_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
619
ctl2 = intel_de_read(display, BLC_PWM_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
656
ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
690
val = intel_de_read(display, UTIL_PIN_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
706
pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
739
pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_bw.c
215
val = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
drivers/gpu/drm/i915/display/intel_bw.c
216
val2 = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
drivers/gpu/drm/i915/display/intel_casf.c
132
sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
drivers/gpu/drm/i915/display/intel_cdclk.c
1018
cdctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1194
cdclk_ctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1239
if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
drivers/gpu/drm/i915/display/intel_cdclk.c
1256
cdctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1268
intel_de_read(display, CDCLK_CTL), expected);
drivers/gpu/drm/i915/display/intel_cdclk.c
1723
u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
1753
val = intel_de_read(display, BXT_DE_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_cdclk.c
1771
ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
1797
divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
1818
squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1835
cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
drivers/gpu/drm/i915/display/intel_cdclk.c
2361
cdctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
2382
intel_de_read(display, CDCLK_CTL), expected);
drivers/gpu/drm/i915/display/intel_cdclk.c
3739
u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
3767
if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
drivers/gpu/drm/i915/display/intel_cdclk.c
3831
if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3857
return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
drivers/gpu/drm/i915/display/intel_cdclk.c
554
u32 lcpll = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
559
else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
drivers/gpu/drm/i915/display/intel_cdclk.c
662
intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
drivers/gpu/drm/i915/display/intel_cdclk.c
834
u32 lcpll = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
839
else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
drivers/gpu/drm/i915/display/intel_cdclk.c
883
(intel_de_read(display, LCPLL_CTL) &
drivers/gpu/drm/i915/display/intel_cdclk.c
973
val = intel_de_read(display, LCPLL1_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
980
val = intel_de_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_cmtg.c
106
val = intel_de_read(display, TRANS_CMTG_CTL_A);
drivers/gpu/drm/i915/display/intel_cmtg.c
110
val = intel_de_read(display, TRANS_CMTG_CTL_B);
drivers/gpu/drm/i915/display/intel_cmtg.c
96
val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));
drivers/gpu/drm/i915/display/intel_color.c
1064
return intel_de_read(display, GAMMA_MODE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
1071
return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
1082
tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/intel_color.c
1110
color = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
3497
crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
4096
if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
drivers/gpu/drm/i915/display/intel_color.c
4114
if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
156
return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
drivers/gpu/drm/i915/display/intel_combo_phy.c
158
return !(intel_de_read(display, ICL_PHY_MISC(phy)) &
drivers/gpu/drm/i915/display/intel_combo_phy.c
160
(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
drivers/gpu/drm/i915/display/intel_combo_phy.c
337
val = intel_de_read(display, ICL_PHY_MISC(phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
351
val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
357
val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
62
val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
98
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_crt.c
1025
adpa = intel_de_read(display, adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
1039
if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_crt.c
1134
display->fdi.rx_config = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
135
tmp = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
493
save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
517
adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
550
save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
566
adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
615
stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
drivers/gpu/drm/i915/display/intel_crt.c
716
save_bclrpat = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
718
save_vtotal = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
720
vblank = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
733
u32 transconf = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
761
u32 vsync = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
781
while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
drivers/gpu/drm/i915/display/intel_crt.c
783
while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
drivers/gpu/drm/i915/display/intel_crt.c
794
} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
drivers/gpu/drm/i915/display/intel_crt.c
974
adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
98
val = intel_de_read(display, adpa_reg);
drivers/gpu/drm/i915/display/intel_cursor.c
335
ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;
drivers/gpu/drm/i915/display/intel_cursor.c
744
val = intel_de_read(display, CURCNTR(display, plane->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
764
error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
765
error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
766
error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
775
error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
776
error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
177
if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2191
lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2208
max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2231
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
321
} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3299
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3379
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3535
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3601
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
drivers/gpu/drm/i915/display/intel_ddi.c
1083
tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);
drivers/gpu/drm/i915/display/intel_ddi.c
1192
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1247
val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1272
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1280
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1588
return !(intel_de_read(display, reg) & clk_off);
drivers/gpu/drm/i915/display/intel_ddi.c
1597
id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
drivers/gpu/drm/i915/display/intel_ddi.c
1740
val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1835
tmp = intel_de_read(display, DDI_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1888
tmp = intel_de_read(display, DDI_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1893
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/intel_ddi.c
1906
tmp = intel_de_read(display, DDI_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1994
return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
drivers/gpu/drm/i915/display/intel_ddi.c
2004
tmp = intel_de_read(display, DPLL_CTRL2);
drivers/gpu/drm/i915/display/intel_ddi.c
2045
return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
drivers/gpu/drm/i915/display/intel_ddi.c
2055
tmp = intel_de_read(display, PORT_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
2193
ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
drivers/gpu/drm/i915/display/intel_ddi.c
2194
ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
drivers/gpu/drm/i915/display/intel_ddi.c
2506
dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_ddi.c
3441
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_ddi.c
3741
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3795
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3827
temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3887
return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &
drivers/gpu/drm/i915/display/intel_ddi.c
391
u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
drivers/gpu/drm/i915/display/intel_ddi.c
3935
u32 ctl2 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3943
u32 ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
4033
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
drivers/gpu/drm/i915/display/intel_ddi.c
4062
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
drivers/gpu/drm/i915/display/intel_ddi.c
4067
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
4098
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
4112
ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
4888
return intel_de_read(display, SDEISR) & bit;
drivers/gpu/drm/i915/display/intel_ddi.c
4896
return intel_de_read(display, DEISR) & bit;
drivers/gpu/drm/i915/display/intel_ddi.c
4904
return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;
drivers/gpu/drm/i915/display/intel_ddi.c
4961
if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_ddi.c
5102
return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5104
return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5106
return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5108
return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5414
ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
692
ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
773
ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
drivers/gpu/drm/i915/display/intel_ddi.c
821
tmp = intel_de_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
826
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
866
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
925
tmp = intel_de_read(display, BXT_PHY_CTL(port));
drivers/gpu/drm/i915/display/intel_de.c
113
intel_de_read,
drivers/gpu/drm/i915/display/intel_de.c
95
intel_de_read,
drivers/gpu/drm/i915/display/intel_de.h
62
lower = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
63
upper = intel_de_read(display, upper_reg);
drivers/gpu/drm/i915/display/intel_display.c
2578
bool bios_lvds_use_ssc = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2865
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2868
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2880
tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2885
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2891
tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2895
tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2901
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2906
tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2918
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2936
pipe_config->min_hblank = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2963
tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
3045
tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
3080
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3322
tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
3367
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3368
m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3369
m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3370
m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3371
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
drivers/gpu/drm/i915/display/intel_display.c
3424
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3510
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3534
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_display.c
3562
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_display.c
3631
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_display.c
3793
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
380
u32 val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3899
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3906
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3942
tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
drivers/gpu/drm/i915/display/intel_display.c
3946
tmp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/intel_display.c
3999
tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
4021
u32 tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
4037
tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
4056
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
470
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
516
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
683
tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
drivers/gpu/drm/i915/display/intel_display.c
7808
if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)
drivers/gpu/drm/i915/display/intel_display.c
7811
if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))
drivers/gpu/drm/i915/display/intel_display.c
7826
intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
drivers/gpu/drm/i915/display/intel_display.c
7830
if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_display.c
7880
if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {
drivers/gpu/drm/i915/display/intel_display.c
7885
if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))
drivers/gpu/drm/i915/display/intel_display.c
7889
if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7892
if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7895
if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7898
if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7923
if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7925
if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
drivers/gpu/drm/i915/display/intel_display.c
7930
if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7932
if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
drivers/gpu/drm/i915/display/intel_display.c
7941
if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7943
if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7959
if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
drivers/gpu/drm/i915/display/intel_display.c
7974
if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
drivers/gpu/drm/i915/display/intel_display.c
7979
if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {
drivers/gpu/drm/i915/display/intel_display.c
7990
if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))
drivers/gpu/drm/i915/display/intel_display.c
8436
intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8438
intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8440
intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8442
intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
drivers/gpu/drm/i915/display/intel_display.c
8444
intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
105
intel_de_read(display, GEN9_CLKGATE_DIS_0) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
133
intel_de_read(display, GEN9_CLKGATE_DIS_0) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
207
intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
211
intel_de_read(display, DISP_ARB_CTL) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
234
intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
237
intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
240
intel_de_read(display, ILK_DSPCLK_GATE_D) |
drivers/gpu/drm/i915/display/intel_display_debugfs.c
101
sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
103
sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
105
sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
107
sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
98
sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
drivers/gpu/drm/i915/display/intel_display_device.c
1842
!(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) {
drivers/gpu/drm/i915/display/intel_display_device.c
1848
u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
drivers/gpu/drm/i915/display/intel_display_device.c
1849
u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);
drivers/gpu/drm/i915/display/intel_display_device.c
1873
u32 dfsm = intel_de_read(display, SKL_DFSM);
drivers/gpu/drm/i915/display/intel_display_device.c
1922
u32 cap = intel_de_read(display, XE2LPD_DE_CAP);
drivers/gpu/drm/i915/display/intel_display_device.c
1938
intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;
drivers/gpu/drm/i915/display/intel_display_irq.c
1277
u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);
drivers/gpu/drm/i915/display/intel_display_irq.c
1329
val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));
drivers/gpu/drm/i915/display/intel_display_irq.c
1341
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
drivers/gpu/drm/i915/display/intel_display_irq.c
1350
val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));
drivers/gpu/drm/i915/display/intel_display_irq.c
1386
*pch_iir = intel_de_read(display, SDEIIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1399
*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1417
iir = intel_de_read(display, GEN8_DE_MISC_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1428
iir = intel_de_read(display, GEN11_DE_HPD_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1439
iir = intel_de_read(display, GEN8_DE_PORT_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1496
iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
1587
iir = intel_de_read(display, GEN11_GU_MISC_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1612
disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);
drivers/gpu/drm/i915/display/intel_display_irq.c
1884
tmp = intel_de_read(display, DPINVGTT);
drivers/gpu/drm/i915/display/intel_display_irq.c
1923
*eir = intel_de_read(display, VLV_EIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1935
emr = intel_de_read(display, VLV_EMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
209
old_val = intel_de_read(display, GEN8_DE_PORT_IMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2652
snapshot->derrmr = intel_de_read(display, DERRMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2655
snapshot->err_int = intel_de_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_display_irq.c
274
u32 sdeimr = intel_de_read(display, SDEIMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
483
intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
491
intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
492
intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
493
intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
494
intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
495
intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));
drivers/gpu/drm/i915/display/intel_display_irq.c
504
res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
509
res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
514
intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
515
intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
516
intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
53
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_irq.c
580
pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
707
intel_de_read(display, FDI_RX_IIR(pipe)));
drivers/gpu/drm/i915/display/intel_display_irq.c
759
u32 err_int = intel_de_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_display_irq.c
795
u32 serr_int = intel_de_read(display, SERR_INT);
drivers/gpu/drm/i915/display/intel_display_irq.c
838
intel_de_read(display, FDI_RX_IIR(pipe)));
drivers/gpu/drm/i915/display/intel_display_irq.c
876
gtt_fault = intel_de_read(display, ILK_GTT_FAULT);
drivers/gpu/drm/i915/display/intel_display_irq.c
931
u32 pch_iir = intel_de_read(display, SDEIIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
986
u32 pch_iir = intel_de_read(display, SDEIIR);
drivers/gpu/drm/i915/display/intel_display_power.c
1080
state = intel_de_read(display, reg) & DBUF_POWER_STATE;
drivers/gpu/drm/i915/display/intel_display_power.c
1184
u32 val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1211
INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),
drivers/gpu/drm/i915/display/intel_display_power.c
1214
intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1217
intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1220
intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1223
intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
drivers/gpu/drm/i915/display/intel_display_power.c
1226
intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1230
intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1233
intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1236
(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
drivers/gpu/drm/i915/display/intel_display_power.c
1239
intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1257
return intel_de_read(display, D_COMP_BDW);
drivers/gpu/drm/i915/display/intel_display_power.c
1287
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1298
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1334
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1357
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1801
u32 status = intel_de_read(display, DPLL(display, PIPE_A));
drivers/gpu/drm/i915/display/intel_display_power.c
1832
u32 status = intel_de_read(display, DPIO_PHY_STATUS);
drivers/gpu/drm/i915/display/intel_display_power.c
1869
intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1042
return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
1043
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1148
if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1150
if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1164
return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
1165
intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1301
u32 val = intel_de_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_display_power_well.c
1457
(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1957
return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
1991
return intel_de_read(display, XE2LPD_PICA_PW_CTL) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
236
intel_de_read(display, CLKGATE_DIS_DSSDSC));
drivers/gpu/drm/i915/display/intel_display_power_well.c
375
ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
376
ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
378
ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
379
ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
671
val = intel_de_read(display, regs->driver);
drivers/gpu/drm/i915/display/intel_display_power_well.c
681
val |= intel_de_read(display, regs->bios);
drivers/gpu/drm/i915/display/intel_display_power_well.c
689
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),
drivers/gpu/drm/i915/display/intel_display_power_well.c
692
intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
696
intel_de_read(display, HSW_PWR_WELL_CTL2) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
716
intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
744
v = intel_de_read(display, DC_STATE_EN);
drivers/gpu/drm/i915/display/intel_display_power_well.c
795
val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
843
val = intel_de_read(display, DC_STATE_EN);
drivers/gpu/drm/i915/display/intel_display_power_well.c
901
(intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
929
(intel_de_read(display, UTIL_PIN_CTL) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
934
(intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
988
u32 bios_req = intel_de_read(display, regs->bios);
drivers/gpu/drm/i915/display/intel_display_power_well.c
992
u32 drv_req = intel_de_read(display, regs->driver);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
54
val = intel_de_read(display, DKL_REG_MMIO(reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1588
dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
drivers/gpu/drm/i915/display/intel_dmc.c
1662
intel_de_read(display, dc3co_reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1670
seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1677
intel_de_read(display, dc6_reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1680
intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
drivers/gpu/drm/i915/display/intel_dmc.c
1684
intel_de_read(display, DMC_SSP_BASE));
drivers/gpu/drm/i915/display/intel_dmc.c
1685
seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));
drivers/gpu/drm/i915/display/intel_dmc.c
1706
tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
drivers/gpu/drm/i915/display/intel_dmc.c
1737
int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;
drivers/gpu/drm/i915/display/intel_dmc.c
691
found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));
drivers/gpu/drm/i915/display/intel_dmc.c
701
found = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_dp.c
5410
u32 val = intel_de_read(display, reg) & ~dip_enable;
drivers/gpu/drm/i915/display/intel_dp.c
7397
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/intel_dp_aux.c
336
const u32 status = intel_de_read(display, ch_ctl);
drivers/gpu/drm/i915/display/intel_dp_aux.c
449
intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]),
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
812
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
834
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
288
old = intel_de_read(display, reg_single);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
336
val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
362
if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
drivers/gpu/drm/i915/display/intel_dpio_phy.c
365
if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &
drivers/gpu/drm/i915/display/intel_dpio_phy.c
373
if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
drivers/gpu/drm/i915/display/intel_dpio_phy.c
385
u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
522
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
649
u32 val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll.c
2170
(intel_de_read(display, DPLL(display, PIPE_B)) &
drivers/gpu/drm/i915/display/intel_dpll.c
2300
cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
drivers/gpu/drm/i915/display/intel_dpll.c
404
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll.c
410
hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
413
hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
414
hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
483
u32 lvds = intel_de_read(display, LVDS);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1265
if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1462
val = intel_de_read(display, regs[id].ctl);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1466
val = intel_de_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1471
hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1472
hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1501
val = intel_de_read(display, regs[id].ctl);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1505
val = intel_de_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2110
temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2124
temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2131
temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2148
temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2157
temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2207
val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2211
hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2214
hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2217
hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2220
hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2223
hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2226
hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2229
hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2234
hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2237
hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2240
hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2249
hw_state->pcsdw12 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2251
if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2255
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3613
val = intel_de_read(display, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3617
hw_state->mg_refclkin_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3622
intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3627
intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3634
hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3635
hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3636
hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3637
hw_state->mg_pll_frac_lock = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3639
hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3641
hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3643
intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3678
val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3750
val = intel_de_read(display, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3755
hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3756
hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3758
hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3759
hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3761
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3763
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3766
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3768
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3771
hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3777
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3779
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3782
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3784
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4005
val = intel_de_read(display, TRANS_CMTG_CHICKEN);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
559
val = intel_de_read(display, PCH_DPLL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
561
hw_state->fp0 = intel_de_read(display, PCH_FP0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
562
hw_state->fp1 = intel_de_read(display, PCH_FP1(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
574
val = intel_de_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
780
val = intel_de_read(display, WRPLL_CTL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
801
val = intel_de_read(display, SPLL_CTL);
drivers/gpu/drm/i915/display/intel_dram.c
761
u32 val = intel_de_read(display, MTL_MEM_SS_INFO_GLOBAL);
drivers/gpu/drm/i915/display/intel_dvo.c
139
tmp = intel_de_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
154
tmp = intel_de_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
170
tmp = intel_de_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
285
dvo_val = intel_de_read(display, DVO(port)) &
drivers/gpu/drm/i915/display/intel_fbc.c
2246
val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
drivers/gpu/drm/i915/display/intel_fbc.c
331
fbc_ctl = intel_de_read(display, FBC_CONTROL);
drivers/gpu/drm/i915/display/intel_fbc.c
369
return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;
drivers/gpu/drm/i915/display/intel_fbc.c
374
return intel_de_read(fbc->display, FBC_STATUS) &
drivers/gpu/drm/i915/display/intel_fbc.c
489
dpfc_ctl = intel_de_read(display, DPFC_CONTROL);
drivers/gpu/drm/i915/display/intel_fbc.c
498
return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;
drivers/gpu/drm/i915/display/intel_fbc.c
503
return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
drivers/gpu/drm/i915/display/intel_fbc.c
558
dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
drivers/gpu/drm/i915/display/intel_fbc.c
567
return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
drivers/gpu/drm/i915/display/intel_fbc.c
572
return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
drivers/gpu/drm/i915/display/intel_fbc.c
709
return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
drivers/gpu/drm/i915/display/intel_fdi.c
1004
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1007
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
drivers/gpu/drm/i915/display/intel_fdi.c
1020
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
105
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
1060
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1062
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
drivers/gpu/drm/i915/display/intel_fdi.c
1078
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1088
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
drivers/gpu/drm/i915/display/intel_fdi.c
274
fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
drivers/gpu/drm/i915/display/intel_fdi.c
392
temp = intel_de_read(display, SOUTH_CHICKEN1);
drivers/gpu/drm/i915/display/intel_fdi.c
397
intel_de_read(display, FDI_RX_CTL(PIPE_B)) &
drivers/gpu/drm/i915/display/intel_fdi.c
400
intel_de_read(display, FDI_RX_CTL(PIPE_C)) &
drivers/gpu/drm/i915/display/intel_fdi.c
42
cur_state = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_fdi.c
446
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
45
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
457
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
490
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
drivers/gpu/drm/i915/display/intel_fdi.c
498
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
502
intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
507
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
515
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
531
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
553
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
591
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
drivers/gpu/drm/i915/display/intel_fdi.c
596
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
606
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
620
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
641
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
660
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
67
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
671
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
692
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
728
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
drivers/gpu/drm/i915/display/intel_fdi.c
733
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
742
intel_de_read(display, FDI_RX_IIR(pipe)));
drivers/gpu/drm/i915/display/intel_fdi.c
748
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
754
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
762
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
775
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
785
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
789
(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {
drivers/gpu/drm/i915/display/intel_fdi.c
817
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
821
(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {
drivers/gpu/drm/i915/display/intel_fdi.c
929
temp = intel_de_read(display, DP_TP_STATUS(PORT_E));
drivers/gpu/drm/i915/display/intel_fdi.c
95
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
109
u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
126
u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
197
if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
223
if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
245
u32 err_int = intel_de_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
275
intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
309
u32 serr_int = intel_de_read(display, SERR_INT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
340
if (old && intel_de_read(display, SERR_INT) &
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
87
u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
drivers/gpu/drm/i915/display/intel_flipq.c
179
return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));
drivers/gpu/drm/i915/display/intel_flipq.c
222
intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));
drivers/gpu/drm/i915/display/intel_flipq.c
230
intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),
drivers/gpu/drm/i915/display/intel_flipq.c
231
intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));
drivers/gpu/drm/i915/display/intel_flipq.c
241
intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));
drivers/gpu/drm/i915/display/intel_flipq.c
243
tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));
drivers/gpu/drm/i915/display/intel_flipq.c
434
pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));
drivers/gpu/drm/i915/display/intel_hdcp.c
1153
intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)));
drivers/gpu/drm/i915/display/intel_hdcp.c
1891
if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1932
intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1945
if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1970
!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
2178
intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)));
drivers/gpu/drm/i915/display/intel_hdcp.c
318
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
326
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
388
val = intel_de_read(display, HDCP_KEY_STATUS);
drivers/gpu/drm/i915/display/intel_hdcp.c
397
if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
drivers/gpu/drm/i915/display/intel_hdcp.c
722
if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
873
an.reg[0] = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
875
an.reg[1] = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
914
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
drivers/gpu/drm/i915/display/intel_hdcp.c
949
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
drivers/gpu/drm/i915/display/intel_hdmi.c
102
intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
drivers/gpu/drm/i915/display/intel_hdmi.c
1038
crtc_state->infoframes.gcp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1073
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1131
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1180
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1236
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1261
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1521
scanline = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
1604
intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,
drivers/gpu/drm/i915/display/intel_hdmi.c
232
u32 val = intel_de_read(display, VIDEO_DIP_CTL);
drivers/gpu/drm/i915/display/intel_hdmi.c
274
*data++ = intel_de_read(display, VIDEO_DIP_DATA);
drivers/gpu/drm/i915/display/intel_hdmi.c
281
u32 val = intel_de_read(display, VIDEO_DIP_CTL);
drivers/gpu/drm/i915/display/intel_hdmi.c
302
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
346
*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
355
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
377
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
424
*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
432
u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
451
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
496
*data++ = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
505
u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
529
u32 val = intel_de_read(display, ctl_reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
572
*data++ = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
580
u32 val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
888
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
93
intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
442
u32 tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
455
intel_de_read(display, PORT_HOTPLUG_STAT(display)));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
496
dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
532
val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));
drivers/gpu/drm/i915/display/intel_hti.c
21
display->hti.state = intel_de_read(display, HDPORT_STATE);
drivers/gpu/drm/i915/display/intel_initial_plane.c
37
start_ts = intel_de_read(display, PIPE_FRMTMSTMP(crtc->pipe));
drivers/gpu/drm/i915/display/intel_initial_plane.c
39
ret = poll_timeout_us(end_ts = intel_de_read(display, PIPE_FRMTMSTMP(crtc->pipe)),
drivers/gpu/drm/i915/display/intel_lpe_audio.c
341
audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port));
drivers/gpu/drm/i915/display/intel_lspcon.c
661
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2216
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_lvds.c
131
tmp = intel_de_read(display, lvds_encoder->reg);
drivers/gpu/drm/i915/display/intel_lvds.c
149
tmp = intel_de_read(display, PFIT_CONTROL(display));
drivers/gpu/drm/i915/display/intel_lvds.c
162
pps->powerdown_on_reset = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_lvds.c
165
val = intel_de_read(display, PP_ON_DELAYS(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
170
val = intel_de_read(display, PP_OFF_DELAYS(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
174
val = intel_de_read(display, PP_DIVISOR(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
216
val = intel_de_read(display, PP_CONTROL(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
819
val = intel_de_read(display, lvds_encoder->reg);
drivers/gpu/drm/i915/display/intel_lvds.c
870
lvds = intel_de_read(display, lvds_reg);
drivers/gpu/drm/i915/display/intel_lvds.c
92
val = intel_de_read(display, lvds_reg);
drivers/gpu/drm/i915/display/intel_mchbar.c
70
return intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_overlay.c
558
tmp = intel_de_read(display, DOVSTA);
drivers/gpu/drm/i915/display/intel_overlay.c
623
u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
drivers/gpu/drm/i915/display/intel_overlay.c
630
if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)
drivers/gpu/drm/i915/display/intel_overlay.c
631
tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));
drivers/gpu/drm/i915/display/intel_overlay.c
633
tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
drivers/gpu/drm/i915/display/intel_overlay.c
969
attrs->gamma0 = intel_de_read(display, OGAMC0);
drivers/gpu/drm/i915/display/intel_overlay.c
970
attrs->gamma1 = intel_de_read(display, OGAMC1);
drivers/gpu/drm/i915/display/intel_overlay.c
971
attrs->gamma2 = intel_de_read(display, OGAMC2);
drivers/gpu/drm/i915/display/intel_overlay.c
972
attrs->gamma3 = intel_de_read(display, OGAMC3);
drivers/gpu/drm/i915/display/intel_overlay.c
973
attrs->gamma4 = intel_de_read(display, OGAMC4);
drivers/gpu/drm/i915/display/intel_overlay.c
974
attrs->gamma5 = intel_de_read(display, OGAMC5);
drivers/gpu/drm/i915/display/intel_pch.c
251
val = intel_de_read(display, TRANS_CHICKEN2(pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
110
val = intel_de_read(display, PCH_TRANSCONF(pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
120
u32 val = intel_de_read(display, hdmi_reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
139
u32 val = intel_de_read(display, dp_reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
229
intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
231
intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
233
intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
236
intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
238
intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
240
intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
242
intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
262
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
275
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
276
pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
381
temp = intel_de_read(display, PCH_DPLL_SEL);
drivers/gpu/drm/i915/display/intel_pch_display.c
418
u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
drivers/gpu/drm/i915/display/intel_pch_display.c
423
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
505
if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_pch_display.c
510
tmp = intel_de_read(display, FDI_RX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
524
tmp = intel_de_read(display, PCH_DPLL_SEL);
drivers/gpu/drm/i915/display/intel_pch_display.c
556
val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));
drivers/gpu/drm/i915/display/intel_pch_display.c
565
pipeconf_val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_pch_display.c
624
if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_pch_display.c
629
tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));
drivers/gpu/drm/i915/display/intel_pch_refclk.c
241
if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
404
u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
405
u32 ctl = intel_de_read(display, SPLL_CTL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
423
u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
424
u32 ctl = intel_de_read(display, WRPLL_CTL(id));
drivers/gpu/drm/i915/display/intel_pch_refclk.c
540
temp = intel_de_read(display, PCH_DPLL(pll->info->id));
drivers/gpu/drm/i915/display/intel_pch_refclk.c
561
val = intel_de_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_pfit.c
648
ctl = intel_de_read(display, PF_CTL(crtc->pipe));
drivers/gpu/drm/i915/display/intel_pfit.c
659
pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));
drivers/gpu/drm/i915/display/intel_pfit.c
660
size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));
drivers/gpu/drm/i915/display/intel_pfit.c
689
intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);
drivers/gpu/drm/i915/display/intel_pfit.c
714
intel_de_read(display, PFIT_CONTROL(display)));
drivers/gpu/drm/i915/display/intel_pfit.c
737
tmp = intel_de_read(display, PFIT_CONTROL(display));
drivers/gpu/drm/i915/display/intel_pfit.c
752
intel_de_read(display, PFIT_PGM_RATIOS(display));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
174
u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
236
u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
drivers/gpu/drm/i915/display/intel_pmdemand.c
418
reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
drivers/gpu/drm/i915/display/intel_pmdemand.c
420
reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
drivers/gpu/drm/i915/display/intel_pmdemand.c
455
return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
drivers/gpu/drm/i915/display/intel_pmdemand.c
587
reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
drivers/gpu/drm/i915/display/intel_pmdemand.c
590
reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
drivers/gpu/drm/i915/display/intel_pps.c
105
intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,
drivers/gpu/drm/i915/display/intel_pps.c
119
DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
drivers/gpu/drm/i915/display/intel_pps.c
129
pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
drivers/gpu/drm/i915/display/intel_pps.c
1382
pp_on = intel_de_read(display, regs.pp_on);
drivers/gpu/drm/i915/display/intel_pps.c
1383
pp_off = intel_de_read(display, regs.pp_off);
drivers/gpu/drm/i915/display/intel_pps.c
1394
pp_div = intel_de_read(display, regs.pp_div);
drivers/gpu/drm/i915/display/intel_pps.c
1663
intel_de_read(display, regs.pp_on),
drivers/gpu/drm/i915/display/intel_pps.c
1664
intel_de_read(display, regs.pp_off),
drivers/gpu/drm/i915/display/intel_pps.c
1666
intel_de_read(display, regs.pp_div) :
drivers/gpu/drm/i915/display/intel_pps.c
1667
(intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
drivers/gpu/drm/i915/display/intel_pps.c
1829
port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
drivers/gpu/drm/i915/display/intel_pps.c
1857
port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
drivers/gpu/drm/i915/display/intel_pps.c
1865
val = intel_de_read(display, pp_reg);
drivers/gpu/drm/i915/display/intel_pps.c
282
return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;
drivers/gpu/drm/i915/display/intel_pps.c
287
return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;
drivers/gpu/drm/i915/display/intel_pps.c
302
u32 port_sel = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_pps.c
381
return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
drivers/gpu/drm/i915/display/intel_pps.c
556
return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
drivers/gpu/drm/i915/display/intel_pps.c
569
return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
drivers/gpu/drm/i915/display/intel_pps.c
589
intel_de_read(display, _pp_stat_reg(intel_dp)),
drivers/gpu/drm/i915/display/intel_pps.c
590
intel_de_read(display, _pp_ctrl_reg(intel_dp)));
drivers/gpu/drm/i915/display/intel_pps.c
626
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
627
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
629
ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
637
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
638
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
728
control = intel_de_read(display, _pp_ctrl_reg(intel_dp));
drivers/gpu/drm/i915/display/intel_pps.c
784
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
785
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
856
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
857
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_psr.c
1170
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2006
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2015
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2030
intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);
drivers/gpu/drm/i915/display/intel_psr.c
2033
intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);
drivers/gpu/drm/i915/display/intel_psr.c
2225
val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
2318
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2323
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4235
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4251
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4342
val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
4345
psr2_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4351
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4355
val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
4370
val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
4394
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_rom.c
37
return intel_de_read(rom->display, PRIMARY_SPI_TRIGGER);
drivers/gpu/drm/i915/display/intel_rom.c
56
static_region = intel_de_read(rom->display, SPI_STATIC_REGIONS);
drivers/gpu/drm/i915/display/intel_rom.c
60
rom->offset = intel_de_read(rom->display, OROM_OFFSET) & OROM_OFFSET_MASK;
drivers/gpu/drm/i915/display/intel_sdvo.c
1627
sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1673
val = intel_de_read(display, sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1715
sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1850
temp = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1911
temp = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
235
cval = intel_de_read(display, GEN3_SDVOC);
drivers/gpu/drm/i915/display/intel_sdvo.c
237
bval = intel_de_read(display, GEN3_SDVOB);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1955
pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1956
pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1957
pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1958
pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1959
pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1960
pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1961
pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1969
pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &
drivers/gpu/drm/i915/display/intel_sprite.c
1225
error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
1226
error->surf = intel_de_read(display, DVSSURF(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
1227
error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
1244
ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;
drivers/gpu/drm/i915/display/intel_sprite.c
453
error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/intel_sprite.c
454
error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/intel_sprite.c
455
error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/intel_sprite.c
473
ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
drivers/gpu/drm/i915/display/intel_sprite.c
885
error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
886
error->surf = intel_de_read(display, SPRSURF(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
887
error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
904
ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
drivers/gpu/drm/i915/display/intel_tc.c
1017
pica_isr = intel_de_read(display, PICAINTERRUPT_ISR);
drivers/gpu/drm/i915/display/intel_tc.c
1018
pch_isr = intel_de_read(display, SDEISR);
drivers/gpu/drm/i915/display/intel_tc.c
1041
return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;
drivers/gpu/drm/i915/display/intel_tc.c
1105
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_tc.c
1149
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_tc.c
1165
return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;
drivers/gpu/drm/i915/display/intel_tc.c
1568
return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &
drivers/gpu/drm/i915/display/intel_tc.c
274
lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
313
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_tc.c
437
val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
532
fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
533
pch_isr = intel_de_read(display, SDEISR);
drivers/gpu/drm/i915/display/intel_tc.c
569
val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
588
val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
613
val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
776
val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));
drivers/gpu/drm/i915/display/intel_tc.c
822
cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR);
drivers/gpu/drm/i915/display/intel_tc.c
823
pch_isr = intel_de_read(display, SDEISR);
drivers/gpu/drm/i915/display/intel_tc.c
852
val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));
drivers/gpu/drm/i915/display/intel_tc.c
885
val = intel_de_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_tv.c
1106
tv_ctl = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1107
hctl1 = intel_de_read(display, TV_H_CTL_1);
drivers/gpu/drm/i915/display/intel_tv.c
1108
hctl3 = intel_de_read(display, TV_H_CTL_3);
drivers/gpu/drm/i915/display/intel_tv.c
1109
vctl1 = intel_de_read(display, TV_V_CTL_1);
drivers/gpu/drm/i915/display/intel_tv.c
1110
vctl2 = intel_de_read(display, TV_V_CTL_2);
drivers/gpu/drm/i915/display/intel_tv.c
1145
tmp = intel_de_read(display, TV_WIN_POS);
drivers/gpu/drm/i915/display/intel_tv.c
1149
tmp = intel_de_read(display, TV_WIN_SIZE);
drivers/gpu/drm/i915/display/intel_tv.c
1452
tv_ctl = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1578
intel_de_read(display, TV_DAC) & TV_DAC_SAVE);
drivers/gpu/drm/i915/display/intel_tv.c
1601
save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1602
save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1635
tv_dac = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1938
if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
drivers/gpu/drm/i915/display/intel_tv.c
1950
save_tv_dac = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1953
tv_dac_on = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1956
tv_dac_off = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
919
u32 tmp = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_vblank.c
135
return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
drivers/gpu/drm/i915/display/intel_vblank.c
488
line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
drivers/gpu/drm/i915/display/intel_vblank.c
490
line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
drivers/gpu/drm/i915/display/intel_vdsc.c
1090
dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vdsc.c
1091
dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vdsc.c
945
val = intel_de_read(display, dsc_reg[0]);
drivers/gpu/drm/i915/display/intel_vdsc.c
948
if (intel_de_read(display, dsc_reg[i]) != val) {
drivers/gpu/drm/i915/display/intel_vga.c
200
tmp = intel_de_read(display, vga_reg);
drivers/gpu/drm/i915/display/intel_vrr.c
1035
reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1038
reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1042
intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1044
intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1046
intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1048
intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1050
intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1060
trans_vrr_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1088
crtc_state->vrr.flipline = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1090
crtc_state->vrr.vmax = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1092
crtc_state->vrr.vmin = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1116
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1190
tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1204
tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1218
tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1229
tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
624
!(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));
drivers/gpu/drm/i915/display/intel_vrr.c
785
return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
drivers/gpu/drm/i915/display/intel_vrr.c
837
u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
888
u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/skl_scaler.c
847
ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, scaler_id));
drivers/gpu/drm/i915/display/skl_scaler.c
982
pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, scaler_id));
drivers/gpu/drm/i915/display/skl_scaler.c
983
size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, scaler_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
1702
error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
1703
error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
1704
error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
2842
plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3093
val = intel_de_read(display, PLANE_CTL(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3103
color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3189
base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
drivers/gpu/drm/i915/display/skl_universal_plane.c
3192
offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3195
val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3199
val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
949
ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
drivers/gpu/drm/i915/display/skl_watermark.c
111
val = intel_de_read(display, MTL_LATENCY_SAGV);
drivers/gpu/drm/i915/display/skl_watermark.c
2987
val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));
drivers/gpu/drm/i915/display/skl_watermark.c
2989
val = intel_de_read(display, CUR_WM(pipe, level));
drivers/gpu/drm/i915/display/skl_watermark.c
2995
val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
2997
val = intel_de_read(display, CUR_WM_TRANS(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
3003
val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
3005
val = intel_de_read(display, CUR_WM_SAGV(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
3010
val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
3012
val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
3029
dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
drivers/gpu/drm/i915/display/skl_watermark.c
3261
val = intel_de_read(display, MTL_LATENCY_LP0_LP1);
drivers/gpu/drm/i915/display/skl_watermark.c
3265
val = intel_de_read(display, MTL_LATENCY_LP2_LP3);
drivers/gpu/drm/i915/display/skl_watermark.c
3269
val = intel_de_read(display, MTL_LATENCY_LP4_LP5);
drivers/gpu/drm/i915/display/skl_watermark.c
687
val = intel_de_read(display, CUR_BUF_CFG(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
692
val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
696
val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
705
val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
83
if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
drivers/gpu/drm/i915/display/vlv_dsi.c
1034
if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
drivers/gpu/drm/i915/display/vlv_dsi.c
1038
fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;
drivers/gpu/drm/i915/display/vlv_dsi.c
1050
intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1053
intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1056
intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1060
hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1066
hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1067
hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1084
vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1085
vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1086
vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
124
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/vlv_dsi.c
1330
tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
drivers/gpu/drm/i915/display/vlv_dsi.c
1336
tmp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
241
if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))
drivers/gpu/drm/i915/display/vlv_dsi.c
346
u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
362
!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);
drivers/gpu/drm/i915/display/vlv_dsi.c
386
if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {
drivers/gpu/drm/i915/display/vlv_dsi.c
447
val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
637
temp = intel_de_read(display, port_ctrl);
drivers/gpu/drm/i915/display/vlv_dsi.c
961
bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
drivers/gpu/drm/i915/display/vlv_dsi.c
970
enabled = intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
975
u32 tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
983
if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))
drivers/gpu/drm/i915/display/vlv_dsi.c
987
u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
278
val = intel_de_read(display, BXT_DSI_PLL_ENABLE);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
292
val = intel_de_read(display, BXT_DSI_PLL_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
366
config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
382
temp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
447
tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
588
tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
