drivers/acpi/acpica/acutils.h

347

acpi_ut_debug_dump_buffer(u8 *buffer, u32 count, u32 display, u32 component_id);

drivers/acpi/acpica/acutils.h

349

void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 offset);

drivers/acpi/acpica/acutils.h

355

u32 count, u32 display, u32 base_offset);

drivers/acpi/acpica/dbdisply.c

146

u32 display = DB_BYTE_DISPLAY;

drivers/acpi/acpica/dbdisply.c

161

display = DB_WORD_DISPLAY;

drivers/acpi/acpica/dbdisply.c

163

display = DB_DWORD_DISPLAY;

drivers/acpi/acpica/dbdisply.c

165

display = DB_QWORD_DISPLAY;

drivers/acpi/acpica/dbdisply.c

216

display, ACPI_UINT32_MAX);

drivers/acpi/acpica/dbdisply.c

235

display, ACPI_UINT32_MAX);

drivers/acpi/acpica/dbdisply.c

255

acpi_ut_debug_dump_buffer(obj_ptr, size, display,

drivers/acpi/acpica/dbdisply.c

289

sizeof(struct acpi_namespace_node), display,

drivers/acpi/acpica/dbdisply.c

325

display, ACPI_UINT32_MAX);

drivers/acpi/acpica/dbdisply.c

331

display, ACPI_UINT32_MAX);

drivers/acpi/acpica/utbuffer.c

109

j += display;

drivers/acpi/acpica/utbuffer.c

170

acpi_ut_debug_dump_buffer(u8 *buffer, u32 count, u32 display, u32 component_id)

drivers/acpi/acpica/utbuffer.c

180

acpi_ut_dump_buffer(buffer, count, display, 0);

drivers/acpi/acpica/utbuffer.c

206

u8 *buffer, u32 count, u32 display, u32 base_offset)

drivers/acpi/acpica/utbuffer.c

219

display = DB_BYTE_DISPLAY;

drivers/acpi/acpica/utbuffer.c

237

fprintf(file, "%*s", ((display * 2) + 1), " ");

drivers/acpi/acpica/utbuffer.c

238

j += display;

drivers/acpi/acpica/utbuffer.c

242

switch (display) {

drivers/acpi/acpica/utbuffer.c

277

j += display;

drivers/acpi/acpica/utbuffer.c

34

void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset)

drivers/acpi/acpica/utbuffer.c

40

u32 display_data_only = display & DB_DISPLAY_DATA_ONLY;

drivers/acpi/acpica/utbuffer.c

42

display &= ~DB_DISPLAY_DATA_ONLY;

drivers/acpi/acpica/utbuffer.c

49

display = DB_BYTE_DISPLAY;

drivers/acpi/acpica/utbuffer.c

69

acpi_os_printf("%*s", ((display * 2) + 1), " ");

drivers/acpi/acpica/utbuffer.c

70

j += display;

drivers/acpi/acpica/utbuffer.c

74

switch (display) {

drivers/auxdisplay/charlcd.c

213

lcd->ops->display(lcd, CHARLCD_ON);

drivers/auxdisplay/charlcd.c

220

lcd->ops->display(lcd, CHARLCD_OFF);

drivers/auxdisplay/charlcd.h

89

int (*display)(struct charlcd *lcd, enum charlcd_onoff on);

drivers/auxdisplay/hd44780.c

136

.display = hd44780_common_display,

drivers/auxdisplay/hd44780.c

192

.display = hd44780_common_display,

drivers/auxdisplay/lcd2s.c

292

.display = lcd2s_display,

drivers/auxdisplay/panel.c

820

.display = hd44780_common_display,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

538

struct mod_hdcp_display *display = &hdcp_work[link_index].display;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

550

memset(display, 0, sizeof(*display));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

553

display->index = aconnector->base.index;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

554

display->state = MOD_HDCP_DISPLAY_ACTIVE;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

564

display->controller = CONTROLLER_ID_D0 + config->otg_inst;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

565

display->dig_fe = config->dig_fe;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

568

display->stream_enc_idx = config->stream_enc_idx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

581

display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

587

hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

597

mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

52

struct mod_hdcp_display display;

drivers/gpu/drm/amd/display/dc/dm_services.h

247

(struct dc_context *ctx, enum dm_acpi_display_type display,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

256

struct mod_hdcp_display *display,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

263

display->adjust.disable == true &&

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

265

display->adjust.disable = false;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

272

display->adjust.disable = true;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

276

memcmp(adj, &display->adjust,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

321

struct mod_hdcp_link *link, struct mod_hdcp_display *display,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

327

HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

331

if (display->state != MOD_HDCP_DISPLAY_ACTIVE) {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

337

if (get_active_display_at_index(hdcp, display->index)) {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

362

*display_container = *display;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

383

struct mod_hdcp_display *display = NULL;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

389

display = get_active_display_at_index(hdcp, index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

390

if (!display) {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

410

memset(display, 0, sizeof(struct mod_hdcp_display));

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

429

struct mod_hdcp_display *display = NULL;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

435

display = get_active_display_at_index(hdcp, index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

436

if (!display) {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

444

memcmp(display_adjust, &display->adjust,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

452

memcmp(display_adjust, &display->adjust,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

454

status = update_display_adjustments(hdcp, display, display_adjust);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

472

display->adjust = *display_adjust;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

489

struct mod_hdcp_display *display = NULL;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

492

display = get_active_display_at_index(hdcp, index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

493

if (!display) {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

500

query->display = display;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

504

if (is_display_encryption_enabled(display)) {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

516

static inline uint8_t is_display_active(struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

518

return display->state >= MOD_HDCP_DISPLAY_ACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

521

static inline uint8_t is_display_encryption_enabled(struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

523

return display->state >= MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

541

struct mod_hdcp_display *display = NULL;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

545

display = &hdcp->displays[i];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

548

return display;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

555

struct mod_hdcp_display *display = NULL;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

560

display = &hdcp->displays[i];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

563

return display;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

570

struct mod_hdcp_display *display = NULL;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

574

display = &hdcp->displays[i];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

577

return display;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

103

dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

113

display->state = MOD_HDCP_DISPLAY_INACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

115

display->state = MOD_HDCP_DISPLAY_ACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

116

HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

123

struct mod_hdcp *hdcp, struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

132

display->state = MOD_HDCP_DISPLAY_INACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

142

dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

144

dtm_cmd->dtm_in_message.topology_update_v2.controller = display->controller;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

147

dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

151

dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

159

display->state = MOD_HDCP_DISPLAY_INACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

162

HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

170

struct mod_hdcp *hdcp, struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

179

display->state = MOD_HDCP_DISPLAY_INACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

189

dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

191

dtm_cmd->dtm_in_message.topology_update_v3.controller = display->controller;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

194

dtm_cmd->dtm_in_message.topology_update_v3.stream_enc = display->stream_enc_idx;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

198

dtm_cmd->dtm_in_message.topology_update_v3.dp_mst_vcid = display->vc_id;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

214

status = add_display_to_topology_v2(hdcp, display);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

216

display->state = MOD_HDCP_DISPLAY_INACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

218

HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

238

struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

243

status = add_display_to_topology_v3(hdcp, display);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

245

status = add_display_to_topology_v2(hdcp, display);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

254

struct mod_hdcp_display *display = get_first_active_display(hdcp);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

263

if (!display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

271

hdcp_cmd->in_msg.hdcp1_create_session.display_handle = display->index;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

371

struct mod_hdcp_display *display = get_first_active_display(hdcp);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

374

if (!display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

389

display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

390

HDCP_HDCP1_ENABLED_TRACE(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

505

struct mod_hdcp_display *display = get_first_active_display(hdcp);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

514

if (!display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

522

hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

53

struct mod_hdcp_display *display =

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

59

if (!display || !is_display_active(display))

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

67

dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

76

display->state = MOD_HDCP_DISPLAY_ACTIVE;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

77

HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

836

struct mod_hdcp_display *display = get_first_active_display(hdcp);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

839

if (!display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

855

display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

856

HDCP_HDCP2_ENABLED_TRACE(hdcp, display->index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

89

struct mod_hdcp_display *display =

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

95

if (!display || !is_display_active(display))

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

316

const struct mod_hdcp_display *display;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

341

struct mod_hdcp_link *link, struct mod_hdcp_display *display,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

704

ps->display.disableFrameModulation = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

714

ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

715

ps->display.explicitRefreshrate = look_up[rrr_index];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

716

ps->display.limitRefreshrate = true;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

718

if (ps->display.explicitRefreshrate == 0)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

719

ps->display.limitRefreshrate = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

721

ps->display.limitRefreshrate = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

726

ps->display.enableVariBright = (0 != tmp);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

109

uint32_t display : 1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3629

power_state->display.disableFrameModulation = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3630

power_state->display.limitRefreshrate = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3631

power_state->display.enableVariBright =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

132

uint32_t display : 1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3176

power_state->display.disableFrameModulation = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3177

power_state->display.limitRefreshrate = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3178

power_state->display.enableVariBright =

drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h

159

struct PP_StateDisplayBlock display;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

201

struct smu_state_display_block display;

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c

55

const struct drm_display_info *display,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1381

const struct drm_display_info *display)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1392

if (!display->hdmi.scdc.supported ||

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1393

!display->hdmi.scdc.scrambling.supported)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1400

if (!display->hdmi.scdc.scrambling.low_rates &&

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1401

display->max_tmds_clock <= 340000)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1421

const struct drm_display_info *display)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1426

if (dw_hdmi_support_scdc(hdmi, display)) {

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1638

const struct drm_display_info *display)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1648

dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1679

const struct drm_display_info *display,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1689

ret = hdmi_phy_configure(hdmi, display);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1995

const struct drm_display_info *display,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1999

const struct drm_hdmi_info *hdmi_info = &display->hdmi;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2032

(dw_hdmi_support_scdc(hdmi, display) &&

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2100

if (dw_hdmi_support_scdc(hdmi, display)) {

drivers/gpu/drm/drm_modes.c

2711

bool drm_mode_is_420_only(const struct drm_display_info *display,

drivers/gpu/drm/drm_modes.c

2716

return test_bit(vic, display->hdmi.y420_vdb_modes);

drivers/gpu/drm/drm_modes.c

2731

bool drm_mode_is_420_also(const struct drm_display_info *display,

drivers/gpu/drm/drm_modes.c

2736

return test_bit(vic, display->hdmi.y420_cmdb_modes);

drivers/gpu/drm/drm_modes.c

2750

bool drm_mode_is_420(const struct drm_display_info *display,

drivers/gpu/drm/drm_modes.c

2753

return drm_mode_is_420_only(display, mode) ||

drivers/gpu/drm/drm_modes.c

2754

drm_mode_is_420_also(display, mode);

drivers/gpu/drm/i915/display/g4x_dp.c

1034

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1041

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

drivers/gpu/drm/i915/display/g4x_dp.c

1047

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1048

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1082

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1089

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

drivers/gpu/drm/i915/display/g4x_dp.c

1095

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1096

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1134

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1141

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

drivers/gpu/drm/i915/display/g4x_dp.c

1147

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1148

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1189

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1190

u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];

drivers/gpu/drm/i915/display/g4x_dp.c

1192

return intel_de_read(display, SDEISR) & bit;

drivers/gpu/drm/i915/display/g4x_dp.c

1197

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1215

return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;

drivers/gpu/drm/i915/display/g4x_dp.c

1220

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1221

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

drivers/gpu/drm/i915/display/g4x_dp.c

1223

return intel_de_read(display, DEISR) & bit;

drivers/gpu/drm/i915/display/g4x_dp.c

1230

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1233

if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A)

drivers/gpu/drm/i915/display/g4x_dp.c

125

intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/g4x_dp.c

1264

struct intel_display *display = to_intel_display(encoder->dev);

drivers/gpu/drm/i915/display/g4x_dp.c

1267

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1272

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

1283

bool g4x_dp_init(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_dp.c

1292

if (!assert_port_valid(display, port))

drivers/gpu/drm/i915/display/g4x_dp.c

1295

devdata = intel_bios_encoder_data_lookup(display, port);

drivers/gpu/drm/i915/display/g4x_dp.c

1299

drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",

drivers/gpu/drm/i915/display/g4x_dp.c

1315

if (drm_encoder_init(display->drm, &intel_encoder->base,

drivers/gpu/drm/i915/display/g4x_dp.c

133

if (display->platform.ivybridge && port == PORT_A) {

drivers/gpu/drm/i915/display/g4x_dp.c

1332

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/g4x_dp.c

1339

} else if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/g4x_dp.c

1354

if ((display->platform.ivybridge && port == PORT_A) ||

drivers/gpu/drm/i915/display/g4x_dp.c

1355

(HAS_PCH_CPT(display) && port != PORT_A)) {

drivers/gpu/drm/i915/display/g4x_dp.c

1363

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

1365

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/g4x_dp.c

1367

else if (display->platform.ivybridge && port == PORT_A)

drivers/gpu/drm/i915/display/g4x_dp.c

1369

else if (display->platform.sandybridge && port == PORT_A)

drivers/gpu/drm/i915/display/g4x_dp.c

1374

if (display->platform.valleyview || display->platform.cherryview ||

drivers/gpu/drm/i915/display/g4x_dp.c

1375

(HAS_PCH_SPLIT(display) && port != PORT_A)) {

drivers/gpu/drm/i915/display/g4x_dp.c

1386

intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

drivers/gpu/drm/i915/display/g4x_dp.c

1387

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/g4x_dp.c

1401

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/g4x_dp.c

144

} else if (HAS_PCH_CPT(display) && port != PORT_A) {

drivers/gpu/drm/i915/display/g4x_dp.c

147

intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),

drivers/gpu/drm/i915/display/g4x_dp.c

152

if (display->platform.g4x && pipe_config->limited_color_range)

drivers/gpu/drm/i915/display/g4x_dp.c

164

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

173

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

175

bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

177

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/g4x_dp.c

184

static void assert_edp_pll(struct intel_display *display, bool state)

drivers/gpu/drm/i915/display/g4x_dp.c

186

bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

188

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/g4x_dp.c

198

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

201

assert_transcoder_disabled(display, pipe_config->cpu_transcoder);

drivers/gpu/drm/i915/display/g4x_dp.c

203

assert_edp_pll_disabled(display);

drivers/gpu/drm/i915/display/g4x_dp.c

205

drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",

drivers/gpu/drm/i915/display/g4x_dp.c

215

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

216

intel_de_posting_read(display, DP_A);

drivers/gpu/drm/i915/display/g4x_dp.c

225

if (display->platform.ironlake)

drivers/gpu/drm/i915/display/g4x_dp.c

226

intel_wait_for_vblank_if_active(display, !crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

230

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

231

intel_de_posting_read(display, DP_A);

drivers/gpu/drm/i915/display/g4x_dp.c

238

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

240

assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/g4x_dp.c

242

assert_edp_pll_enabled(display);

drivers/gpu/drm/i915/display/g4x_dp.c

244

drm_dbg_kms(display->drm, "disabling eDP PLL\n");

drivers/gpu/drm/i915/display/g4x_dp.c

248

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

249

intel_de_posting_read(display, DP_A);

drivers/gpu/drm/i915/display/g4x_dp.c

253

static bool cpt_dp_port_selected(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_dp.c

258

for_each_pipe(display, p) {

drivers/gpu/drm/i915/display/g4x_dp.c

259

u32 val = intel_de_read(display, TRANS_DP_CTL(p));

drivers/gpu/drm/i915/display/g4x_dp.c

267

drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",

drivers/gpu/drm/i915/display/g4x_dp.c

276

bool g4x_dp_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_dp.c

283

val = intel_de_read(display, dp_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

288

if (display->platform.ivybridge && port == PORT_A)

drivers/gpu/drm/i915/display/g4x_dp.c

290

else if (HAS_PCH_CPT(display) && port != PORT_A)

drivers/gpu/drm/i915/display/g4x_dp.c

291

ret &= cpt_dp_port_selected(display, port, pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

292

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

303

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

308

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/g4x_dp.c

313

ret = g4x_dp_port_enabled(display, intel_dp->output_reg,

drivers/gpu/drm/i915/display/g4x_dp.c

316

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/g4x_dp.c

339

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

350

tmp = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

354

if (HAS_PCH_CPT(display) && port != PORT_A) {

drivers/gpu/drm/i915/display/g4x_dp.c

355

u32 trans_dp = intel_de_read(display,

drivers/gpu/drm/i915/display/g4x_dp.c

387

if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)

drivers/gpu/drm/i915/display/g4x_dp.c

395

if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)

drivers/gpu/drm/i915/display/g4x_dp.c

415

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

420

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/g4x_dp.c

421

(intel_de_read(display, intel_dp->output_reg) &

drivers/gpu/drm/i915/display/g4x_dp.c

425

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/g4x_dp.c

428

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

429

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

436

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {

drivers/gpu/drm/i915/display/g4x_dp.c

441

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_dp.c

442

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_dp.c

448

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

449

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

452

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

453

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

455

intel_wait_for_vblank_if_active(display, PIPE_A);

drivers/gpu/drm/i915/display/g4x_dp.c

456

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_dp.c

457

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_dp.c

462

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

470

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

478

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

487

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

497

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

56

const struct dpll *vlv_get_dpll(struct intel_display *display)

drivers/gpu/drm/i915/display/g4x_dp.c

58

return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];

drivers/gpu/drm/i915/display/g4x_dp.c

580

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

599

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

600

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

607

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

612

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

613

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

621

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

64

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

640

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

641

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

648

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

653

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

654

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

660

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

675

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

676

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

68

if (display->platform.g4x) {

drivers/gpu/drm/i915/display/g4x_dp.c

684

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/g4x_dp.c

686

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

688

if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))

drivers/gpu/drm/i915/display/g4x_dp.c

692

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

702

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/g4x_dp.c

705

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_dp.c

71

} else if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/g4x_dp.c

74

} else if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/g4x_dp.c

77

} else if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/g4x_dp.c

96

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_dp.h

21

const struct dpll *vlv_get_dpll(struct intel_display *display);

drivers/gpu/drm/i915/display/g4x_dp.h

22

bool g4x_dp_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_dp.h

25

bool g4x_dp_init(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_dp.h

28

static inline const struct dpll *vlv_get_dpll(struct intel_display *display)

drivers/gpu/drm/i915/display/g4x_dp.h

32

static inline bool g4x_dp_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_dp.h

38

static inline bool g4x_dp_init(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_hdmi.c

134

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

138

if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/g4x_hdmi.c

141

if (display->platform.g4x)

drivers/gpu/drm/i915/display/g4x_hdmi.c

153

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

160

tmp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

184

if (!HAS_PCH_SPLIT(display) &&

drivers/gpu/drm/i915/display/g4x_hdmi.c

220

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

224

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

228

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

229

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

236

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

242

drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);

drivers/gpu/drm/i915/display/g4x_hdmi.c

245

intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);

drivers/gpu/drm/i915/display/g4x_hdmi.c

254

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

263

intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);

drivers/gpu/drm/i915/display/g4x_hdmi.c

279

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

283

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

291

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

292

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

293

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

294

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

305

intel_de_write(display, intel_hdmi->hdmi_reg,

drivers/gpu/drm/i915/display/g4x_hdmi.c

307

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

31

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

313

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

314

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

315

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

316

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

325

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

331

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

346

intel_de_rmw(display, TRANS_CHICKEN1(pipe),

drivers/gpu/drm/i915/display/g4x_hdmi.c

353

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

354

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

360

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

361

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

363

intel_de_rmw(display, TRANS_CHICKEN1(pipe),

drivers/gpu/drm/i915/display/g4x_hdmi.c

380

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

387

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

390

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

391

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

398

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

40

if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range)

drivers/gpu/drm/i915/display/g4x_hdmi.c

403

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_hdmi.c

404

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/g4x_hdmi.c

412

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

413

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

414

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

415

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

418

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

drivers/gpu/drm/i915/display/g4x_hdmi.c

419

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

421

intel_wait_for_vblank_if_active(display, PIPE_A);

drivers/gpu/drm/i915/display/g4x_hdmi.c

422

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_hdmi.c

423

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/g4x_hdmi.c

55

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/g4x_hdmi.c

57

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/g4x_hdmi.c

598

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/g4x_hdmi.c

607

if (!display->platform.g4x)

drivers/gpu/drm/i915/display/g4x_hdmi.c

62

intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);

drivers/gpu/drm/i915/display/g4x_hdmi.c

621

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/g4x_hdmi.c

63

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

630

drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/g4x_hdmi.c

655

static bool is_hdmi_port_valid(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/g4x_hdmi.c

657

if (display->platform.g4x || display->platform.valleyview)

drivers/gpu/drm/i915/display/g4x_hdmi.c

663

static bool assert_hdmi_port_valid(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/g4x_hdmi.c

665

return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port),

drivers/gpu/drm/i915/display/g4x_hdmi.c

669

bool g4x_hdmi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_hdmi.c

677

if (!assert_port_valid(display, port))

drivers/gpu/drm/i915/display/g4x_hdmi.c

680

if (!assert_hdmi_port_valid(display, port))

drivers/gpu/drm/i915/display/g4x_hdmi.c

683

devdata = intel_bios_encoder_data_lookup(display, port);

drivers/gpu/drm/i915/display/g4x_hdmi.c

687

drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",

drivers/gpu/drm/i915/display/g4x_hdmi.c

69

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/g4x_hdmi.c

702

if (drm_encoder_init(display->drm, &intel_encoder->base,

drivers/gpu/drm/i915/display/g4x_hdmi.c

709

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

717

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

723

} else if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

730

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/g4x_hdmi.c

732

else if (HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/g4x_hdmi.c

74

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/g4x_hdmi.c

742

intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

drivers/gpu/drm/i915/display/g4x_hdmi.c

744

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

759

if (display->platform.g4x)

drivers/gpu/drm/i915/display/g4x_hdmi.c

79

ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);

drivers/gpu/drm/i915/display/g4x_hdmi.c

81

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/g4x_hdmi.h

19

bool g4x_hdmi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/g4x_hdmi.h

24

static inline bool g4x_hdmi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/hsw_ips.c

116

if (display->platform.haswell &&

drivers/gpu/drm/i915/display/hsw_ips.c

139

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/hsw_ips.c

157

if (display->platform.haswell &&

drivers/gpu/drm/i915/display/hsw_ips.c

187

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/hsw_ips.c

189

return HAS_IPS(display) && crtc->pipe == PIPE_A;

drivers/gpu/drm/i915/display/hsw_ips.c

207

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

209

if (display->platform.broadwell)

drivers/gpu/drm/i915/display/hsw_ips.c

21

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

218

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

230

if (min_cdclk > display->cdclk.max_cdclk_freq)

drivers/gpu/drm/i915/display/hsw_ips.c

239

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/hsw_ips.c

248

if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq)

drivers/gpu/drm/i915/display/hsw_ips.c

251

if (!display->params.enable_ips)

drivers/gpu/drm/i915/display/hsw_ips.c

274

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

280

if (display->platform.haswell) {

drivers/gpu/drm/i915/display/hsw_ips.c

281

crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;

drivers/gpu/drm/i915/display/hsw_ips.c

295

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/hsw_ips.c

297

*val = display->ips.false_color;

drivers/gpu/drm/i915/display/hsw_ips.c

305

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/hsw_ips.c

313

display->ips.false_color = val;

drivers/gpu/drm/i915/display/hsw_ips.c

32

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/hsw_ips.c

340

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/hsw_ips.c

343

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/hsw_ips.c

346

str_yes_no(display->params.enable_ips));

drivers/gpu/drm/i915/display/hsw_ips.c

348

if (DISPLAY_VER(display) >= 8) {

drivers/gpu/drm/i915/display/hsw_ips.c

351

if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)

drivers/gpu/drm/i915/display/hsw_ips.c

357

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/hsw_ips.c

37

if (display->ips.false_color)

drivers/gpu/drm/i915/display/hsw_ips.c

40

if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/hsw_ips.c

41

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/hsw_ips.c

42

intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,

drivers/gpu/drm/i915/display/hsw_ips.c

51

intel_de_write(display, IPS_CTL, val);

drivers/gpu/drm/i915/display/hsw_ips.c

59

if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))

drivers/gpu/drm/i915/display/hsw_ips.c

60

drm_err(display->drm,

drivers/gpu/drm/i915/display/hsw_ips.c

67

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

73

if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/hsw_ips.c

74

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/hsw_ips.c

75

intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));

drivers/gpu/drm/i915/display/hsw_ips.c

81

if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))

drivers/gpu/drm/i915/display/hsw_ips.c

82

drm_err(display->drm,

drivers/gpu/drm/i915/display/hsw_ips.c

85

intel_de_write(display, IPS_CTL, 0);

drivers/gpu/drm/i915/display/hsw_ips.c

86

intel_de_posting_read(display, IPS_CTL);

drivers/gpu/drm/i915/display/hsw_ips.c

98

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

15

static void i9xx_display_save_swf(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

20

if (DISPLAY_VER(display) == 2 && display->platform.mobile) {

drivers/gpu/drm/i915/display/i9xx_display_sr.c

22

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

23

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

26

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

27

} else if (DISPLAY_VER(display) == 2) {

drivers/gpu/drm/i915/display/i9xx_display_sr.c

29

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

30

} else if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/i9xx_display_sr.c

32

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

33

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

36

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

40

static void i9xx_display_restore_swf(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

45

if (DISPLAY_VER(display) == 2 && display->platform.mobile) {

drivers/gpu/drm/i915/display/i9xx_display_sr.c

47

intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

48

intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

51

intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

52

} else if (DISPLAY_VER(display) == 2) {

drivers/gpu/drm/i915/display/i9xx_display_sr.c

54

intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

55

} else if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/i9xx_display_sr.c

57

intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

58

intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

61

intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

65

void i9xx_display_sr_save(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

67

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

69

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/i9xx_display_sr.c

73

if (DISPLAY_VER(display) <= 4)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

74

display->restore.saveDSPARB = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

76

if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

77

pci_read_config_word(pdev, GCDGMBUS, &display->restore.saveGCDGMBUS);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

79

i9xx_display_save_swf(display);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

82

void i9xx_display_sr_restore(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

84

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

86

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/i9xx_display_sr.c

89

i9xx_display_restore_swf(display);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

91

if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

92

pci_write_config_word(pdev, GCDGMBUS, display->restore.saveGCDGMBUS);

drivers/gpu/drm/i915/display/i9xx_display_sr.c

95

if (DISPLAY_VER(display) <= 4)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

96

intel_de_write(display, DSPARB(display), display->restore.saveDSPARB);

drivers/gpu/drm/i915/display/i9xx_display_sr.h

11

void i9xx_display_sr_save(struct intel_display *display);

drivers/gpu/drm/i915/display/i9xx_display_sr.h

12

void i9xx_display_sr_restore(struct intel_display *display);

drivers/gpu/drm/i915/display/i9xx_plane.c

1000

else if (DISPLAY_VER(display) == 3)

drivers/gpu/drm/i915/display/i9xx_plane.c

1005

if (display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/i9xx_plane.c

1011

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/i9xx_plane.c

1013

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/i9xx_plane.c

1015

else if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

1021

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/i9xx_plane.c

1024

if (display->platform.i830 || display->platform.i845g) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1034

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

1039

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/i9xx_plane.c

1041

else if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

1046

if (HAS_ASYNC_FLIPS(display)) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1047

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1052

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1058

} else if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1063

} else if (DISPLAY_VER(display) >= 5) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1073

modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);

drivers/gpu/drm/i915/display/i9xx_plane.c

1075

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/i9xx_plane.c

1076

ret = drm_universal_plane_init(display->drm, &plane->base,

drivers/gpu/drm/i915/display/i9xx_plane.c

1083

ret = drm_universal_plane_init(display->drm, &plane->base,

drivers/gpu/drm/i915/display/i9xx_plane.c

1096

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1100

} else if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1107

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

115

static bool i9xx_plane_has_fbc(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1162

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_plane.c

1175

drm_WARN_ON(display->drm, pipe != crtc->pipe);

drivers/gpu/drm/i915/display/i9xx_plane.c

1179

drm_dbg_kms(display->drm, "failed to alloc fb\n");

drivers/gpu/drm/i915/display/i9xx_plane.c

118

if (!HAS_FBC(display))

drivers/gpu/drm/i915/display/i9xx_plane.c

1185

fb->dev = display->drm;

drivers/gpu/drm/i915/display/i9xx_plane.c

1187

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1189

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1197

if (display->platform.cherryview &&

drivers/gpu/drm/i915/display/i9xx_plane.c

1204

fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier);

drivers/gpu/drm/i915/display/i9xx_plane.c

1206

if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1207

offset = intel_de_read(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1208

DSPOFFSET(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1209

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

drivers/gpu/drm/i915/display/i9xx_plane.c

121

if (display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/i9xx_plane.c

1210

} else if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1212

offset = intel_de_read(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1213

DSPTILEOFF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1215

offset = intel_de_read(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1216

DSPLINOFF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1217

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

drivers/gpu/drm/i915/display/i9xx_plane.c

1220

base = intel_de_read(display, DSPADDR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1224

drm_WARN_ON(display->drm, offset != 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

1226

val = intel_de_read(display, PIPESRC(display, pipe));

drivers/gpu/drm/i915/display/i9xx_plane.c

123

else if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/i9xx_plane.c

1230

val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1237

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_plane.c

1250

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_plane.c

126

else if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

1266

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

1267

intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

1269

intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

132

static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_plane.c

135

if (i9xx_plane_has_fbc(display, i9xx_plane))

drivers/gpu/drm/i915/display/i9xx_plane.c

136

return display->fbc.instances[INTEL_FBC_A];

drivers/gpu/drm/i915/display/i9xx_plane.c

143

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

146

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/i9xx_plane.c

148

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/i9xx_plane.c

150

else if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

159

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

166

if (display->platform.g4x || display->platform.ironlake ||

drivers/gpu/drm/i915/display/i9xx_plane.c

167

display->platform.sandybridge || display->platform.ivybridge)

drivers/gpu/drm/i915/display/i9xx_plane.c

215

if (DISPLAY_VER(display) >= 4 &&

drivers/gpu/drm/i915/display/i9xx_plane.c

230

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

249

if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) {

drivers/gpu/drm/i915/display/i9xx_plane.c

250

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_plane.c

258

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

275

if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {

drivers/gpu/drm/i915/display/i9xx_plane.c

281

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_plane.c

300

if (!display->platform.haswell && !display->platform.broadwell) {

drivers/gpu/drm/i915/display/i9xx_plane.c

313

if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/i9xx_plane.c

314

drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095);

drivers/gpu/drm/i915/display/i9xx_plane.c

315

} else if (DISPLAY_VER(display) >= 4 &&

drivers/gpu/drm/i915/display/i9xx_plane.c

317

drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095);

drivers/gpu/drm/i915/display/i9xx_plane.c

376

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

386

if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/i9xx_plane.c

444

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

447

intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

450

if (DISPLAY_VER(display) < 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

461

intel_de_write_fw(display, DSPPOS(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

463

intel_de_write_fw(display, DSPSIZE(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

473

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

486

if (display->platform.cherryview && i9xx_plane == PLANE_B) {

drivers/gpu/drm/i915/display/i9xx_plane.c

492

intel_de_write_fw(display, PRIMPOS(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

494

intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

496

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

497

PRIMCNSTALPHA(display, i9xx_plane), 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

500

if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/i9xx_plane.c

501

intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

503

} else if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

504

intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

506

intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane),

drivers/gpu/drm/i915/display/i9xx_plane.c

515

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

drivers/gpu/drm/i915/display/i9xx_plane.c

517

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

518

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

520

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

542

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

558

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

drivers/gpu/drm/i915/display/i9xx_plane.c

560

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

561

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

563

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

570

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

573

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

574

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

575

error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

582

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

585

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

586

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

593

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

596

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

597

error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

607

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

614

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

drivers/gpu/drm/i915/display/i9xx_plane.c

615

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

625

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

628

intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

634

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

637

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

638

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

drivers/gpu/drm/i915/display/i9xx_plane.c

639

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

645

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

648

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

649

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

drivers/gpu/drm/i915/display/i9xx_plane.c

650

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

656

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

658

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

659

ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

660

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

666

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

668

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

669

ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

670

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

676

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

678

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

679

ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

680

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

686

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

688

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

689

ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

690

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

696

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

699

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

700

i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

drivers/gpu/drm/i915/display/i9xx_plane.c

701

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

707

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

710

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

711

i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

drivers/gpu/drm/i915/display/i9xx_plane.c

712

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/i9xx_plane.c

723

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

736

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/i9xx_plane.c

740

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

744

if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/i9xx_plane.c

749

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/i9xx_plane.c

819

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

825

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/i9xx_plane.c

843

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

848

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/i9xx_plane.c

905

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

910

dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

912

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

drivers/gpu/drm/i915/display/i9xx_plane.c

914

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

915

reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

916

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg);

drivers/gpu/drm/i915/display/i9xx_plane.c

919

reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

920

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg);

drivers/gpu/drm/i915/display/i9xx_plane.c

925

intel_primary_plane_create(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/i9xx_plane.c

944

if (HAS_FBC(display) && DISPLAY_VER(display) < 4 &&

drivers/gpu/drm/i915/display/i9xx_plane.c

945

INTEL_NUM_PIPES(display) == 2)

drivers/gpu/drm/i915/display/i9xx_plane.c

952

intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

954

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_plane.c

957

} else if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/i9xx_plane.c

971

if (display->platform.ivybridge) {

drivers/gpu/drm/i915/display/i9xx_plane.c

983

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.c

988

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/i9xx_plane.c

990

else if (display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/i9xx_plane.c

992

else if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/i9xx_plane.c

997

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/i9xx_plane.c

998

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/i9xx_plane.h

31

intel_primary_plane_create(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/i9xx_plane.h

49

intel_primary_plane_create(struct intel_display *display, int pipe)

drivers/gpu/drm/i915/display/i9xx_wm.c

1027

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1030

for (; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1043

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1049

for (; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1066

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1079

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

108

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1119

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1127

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1147

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1149

if (level >= display->wm.num_levels)

drivers/gpu/drm/i915/display/i9xx_wm.c

116

static void chv_set_memory_dvfs(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/i9xx_wm.c

121

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

123

val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

drivers/gpu/drm/i915/display/i9xx_wm.c

1291

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/i9xx_wm.c

130

vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

132

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),

drivers/gpu/drm/i915/display/i9xx_wm.c

1321

drm_WARN_ON(display->drm, intermediate->wm.plane[plane_id] >

drivers/gpu/drm/i915/display/i9xx_wm.c

1339

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1345

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1352

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1355

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

136

drm_err(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

1386

static void g4x_merge_wm(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

139

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

1396

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1418

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

142

static void chv_set_memory_pm5(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/i9xx_wm.c

1430

static void g4x_program_watermarks(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

1432

struct g4x_wm_values *old_wm = &display->wm.g4x;

drivers/gpu/drm/i915/display/i9xx_wm.c

1435

g4x_merge_wm(display, &new_wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

1441

_intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

1443

g4x_write_wm_values(display, &new_wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

1446

_intel_set_memory_cxsr(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

1454

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1458

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

146

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

1460

g4x_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

1461

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

1467

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1474

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

1476

g4x_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

1477

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

148

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/i9xx_wm.c

1496

static void vlv_setup_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

1499

display->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;

drivers/gpu/drm/i915/display/i9xx_wm.c

1501

display->wm.num_levels = VLV_WM_LEVEL_PM2 + 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

1503

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1504

display->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;

drivers/gpu/drm/i915/display/i9xx_wm.c

1505

display->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;

drivers/gpu/drm/i915/display/i9xx_wm.c

1507

display->wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

1515

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1521

if (display->wm.pri_latency[level] == 0)

drivers/gpu/drm/i915/display/i9xx_wm.c

153

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

1542

display->wm.pri_latency[level] * 10);

drivers/gpu/drm/i915/display/i9xx_wm.c

155

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

1556

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

161

static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/i9xx_wm.c

1626

drm_WARN_ON(display->drm, active_planes != 0 && fifo_left != 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1630

drm_WARN_ON(display->drm, fifo_left != fifo_size);

drivers/gpu/drm/i915/display/i9xx_wm.c

1641

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1643

for (; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

166

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1669

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

167

was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

drivers/gpu/drm/i915/display/i9xx_wm.c

1672

for (; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

168

intel_de_write(display, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1685

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

169

intel_de_posting_read(display, FW_BLC_SELF_VLV);

drivers/gpu/drm/i915/display/i9xx_wm.c

1696

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

170

} else if (display->platform.g4x || display->platform.i965gm) {

drivers/gpu/drm/i915/display/i9xx_wm.c

171

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

1713

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

172

intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

173

intel_de_posting_read(display, FW_BLC_SELF);

drivers/gpu/drm/i915/display/i9xx_wm.c

174

} else if (display->platform.pineview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1744

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

175

val = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

1755

wm_state->num_levels = display->wm.num_levels;

drivers/gpu/drm/i915/display/i9xx_wm.c

1765

const int sr_fifo_size = INTEL_NUM_PIPES(display) * 512 - 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

181

intel_de_write(display, DSPFW3(display), val);

drivers/gpu/drm/i915/display/i9xx_wm.c

182

intel_de_posting_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

183

} else if (display->platform.i945g || display->platform.i945gm) {

drivers/gpu/drm/i915/display/i9xx_wm.c

184

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

1865

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1866

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

187

intel_de_write(display, FW_BLC_SELF, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

188

intel_de_posting_read(display, FW_BLC_SELF);

drivers/gpu/drm/i915/display/i9xx_wm.c

1881

drm_WARN_ON(display->drm, fifo_state->plane[PLANE_CURSOR] != 63);

drivers/gpu/drm/i915/display/i9xx_wm.c

1882

drm_WARN_ON(display->drm, fifo_size != 511);

drivers/gpu/drm/i915/display/i9xx_wm.c

189

} else if (display->platform.i915gm) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1899

dsparb = intel_de_read_fw(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

1900

dsparb2 = intel_de_read_fw(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

1912

intel_de_write_fw(display, DSPARB(display), dsparb);

drivers/gpu/drm/i915/display/i9xx_wm.c

1913

intel_de_write_fw(display, DSPARB2, dsparb2);

drivers/gpu/drm/i915/display/i9xx_wm.c

1916

dsparb = intel_de_read_fw(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

1917

dsparb2 = intel_de_read_fw(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

1929

intel_de_write_fw(display, DSPARB(display), dsparb);

drivers/gpu/drm/i915/display/i9xx_wm.c

1930

intel_de_write_fw(display, DSPARB2, dsparb2);

drivers/gpu/drm/i915/display/i9xx_wm.c

1933

dsparb3 = intel_de_read_fw(display, DSPARB3);

drivers/gpu/drm/i915/display/i9xx_wm.c

1934

dsparb2 = intel_de_read_fw(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

1946

intel_de_write_fw(display, DSPARB3, dsparb3);

drivers/gpu/drm/i915/display/i9xx_wm.c

1947

intel_de_write_fw(display, DSPARB2, dsparb2);

drivers/gpu/drm/i915/display/i9xx_wm.c

195

was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

1953

intel_de_read_fw(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

198

intel_de_write(display, INSTPM, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

199

intel_de_posting_read(display, INSTPM);

drivers/gpu/drm/i915/display/i9xx_wm.c

2028

static void vlv_merge_wm(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2034

wm->level = display->wm.num_levels - 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

2037

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

204

trace_intel_memory_cxsr(display, was_enabled, enable);

drivers/gpu/drm/i915/display/i9xx_wm.c

2056

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

206

drm_dbg_kms(display->drm, "memory self-refresh is %s (was %s)\n",

drivers/gpu/drm/i915/display/i9xx_wm.c

2071

static void vlv_program_watermarks(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2073

struct vlv_wm_values *old_wm = &display->wm.vlv;

drivers/gpu/drm/i915/display/i9xx_wm.c

2076

vlv_merge_wm(display, &new_wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

2082

chv_set_memory_dvfs(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2085

chv_set_memory_pm5(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2088

_intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2090

vlv_write_wm_values(display, &new_wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

2093

_intel_set_memory_cxsr(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2096

chv_set_memory_pm5(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2099

chv_set_memory_dvfs(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2107

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

2111

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

2113

vlv_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2114

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

2120

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

2127

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

2129

vlv_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2130

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

2133

static void i965_update_wm(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2141

crtc = single_enabled_crtc(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2162

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2177

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2185

intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2188

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2193

intel_de_write(display, DSPFW1(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

2198

intel_de_write(display, DSPFW2(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

2202

intel_de_write(display, DSPFW3(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

2206

intel_set_memory_cxsr(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2211

static struct intel_crtc *intel_crtc_for_plane(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2216

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2219

return intel_crtc_for_pipe(display, plane->pipe);

drivers/gpu/drm/i915/display/i9xx_wm.c

2225

static void i9xx_update_wm(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2235

if (display->platform.i945gm)

drivers/gpu/drm/i915/display/i9xx_wm.c

2237

else if (DISPLAY_VER(display) != 2)

drivers/gpu/drm/i915/display/i9xx_wm.c

2242

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/i9xx_wm.c

2243

fifo_size = i830_get_fifo_size(display, PLANE_A);

drivers/gpu/drm/i915/display/i9xx_wm.c

2245

fifo_size = i9xx_get_fifo_size(display, PLANE_A);

drivers/gpu/drm/i915/display/i9xx_wm.c

2246

crtc = intel_crtc_for_plane(display, PLANE_A);

drivers/gpu/drm/i915/display/i9xx_wm.c

2252

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/i9xx_wm.c

2257

planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2266

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/i9xx_wm.c

2269

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/i9xx_wm.c

2270

fifo_size = i830_get_fifo_size(display, PLANE_B);

drivers/gpu/drm/i915/display/i9xx_wm.c

2272

fifo_size = i9xx_get_fifo_size(display, PLANE_B);

drivers/gpu/drm/i915/display/i9xx_wm.c

2273

crtc = intel_crtc_for_plane(display, PLANE_B);

drivers/gpu/drm/i915/display/i9xx_wm.c

2279

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/i9xx_wm.c

2284

planeb_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2293

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2296

crtc = single_enabled_crtc(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2297

if (display->platform.i915gm && crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2312

intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2315

if (HAS_FW_BLC(display) && crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2328

if (display->platform.i915gm || display->platform.i945gm)

drivers/gpu/drm/i915/display/i9xx_wm.c

2336

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2342

if (display->platform.i945g || display->platform.i945gm)

drivers/gpu/drm/i915/display/i9xx_wm.c

2343

intel_de_write(display, FW_BLC_SELF,

drivers/gpu/drm/i915/display/i9xx_wm.c

2346

intel_de_write(display, FW_BLC_SELF, srwm & 0x3f);

drivers/gpu/drm/i915/display/i9xx_wm.c

2349

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2360

intel_de_write(display, FW_BLC, fwater_lo);

drivers/gpu/drm/i915/display/i9xx_wm.c

2361

intel_de_write(display, FW_BLC2, fwater_hi);

drivers/gpu/drm/i915/display/i9xx_wm.c

2364

intel_set_memory_cxsr(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2367

static void i845_update_wm(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2373

crtc = single_enabled_crtc(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2377

planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2379

i845_get_fifo_size(display, PLANE_A),

drivers/gpu/drm/i915/display/i9xx_wm.c

2381

fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;

drivers/gpu/drm/i915/display/i9xx_wm.c

2384

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2387

intel_de_write(display, FW_BLC, fwater_lo);

drivers/gpu/drm/i915/display/i9xx_wm.c

250

bool intel_set_memory_cxsr(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/i9xx_wm.c

254

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

2542

ilk_display_fifo_size(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2544

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/i9xx_wm.c

2546

else if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/i9xx_wm.c

255

ret = _intel_set_memory_cxsr(display, enable);

drivers/gpu/drm/i915/display/i9xx_wm.c

2553

ilk_plane_wm_reg_max(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2556

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/i9xx_wm.c

2559

else if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/i9xx_wm.c

256

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/i9xx_wm.c

257

display->wm.vlv.cxsr = enable;

drivers/gpu/drm/i915/display/i9xx_wm.c

2571

ilk_cursor_wm_reg_max(struct intel_display *display, int level)

drivers/gpu/drm/i915/display/i9xx_wm.c

2573

if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/i9xx_wm.c

2579

static unsigned int ilk_fbc_wm_reg_max(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

258

else if (display->platform.g4x)

drivers/gpu/drm/i915/display/i9xx_wm.c

2581

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/i9xx_wm.c

2588

static unsigned int ilk_plane_wm_max(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

259

display->wm.g4x.cxsr = enable;

drivers/gpu/drm/i915/display/i9xx_wm.c

2594

unsigned int fifo_size = ilk_display_fifo_size(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

260

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

2602

fifo_size /= INTEL_NUM_PIPES(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2609

if (DISPLAY_VER(display) < 7)

drivers/gpu/drm/i915/display/i9xx_wm.c

2625

return min(fifo_size, ilk_plane_wm_reg_max(display, level, is_sprite));

drivers/gpu/drm/i915/display/i9xx_wm.c

2629

static unsigned int ilk_cursor_wm_max(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2638

return ilk_cursor_wm_reg_max(display, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

2641

static void ilk_compute_wm_maximums(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2647

max->pri = ilk_plane_wm_max(display, level, config, ddb_partitioning, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2648

max->spr = ilk_plane_wm_max(display, level, config, ddb_partitioning, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2649

max->cur = ilk_cursor_wm_max(display, level, config);

drivers/gpu/drm/i915/display/i9xx_wm.c

2650

max->fbc = ilk_fbc_wm_reg_max(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2653

static void ilk_compute_wm_reg_maximums(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2657

max->pri = ilk_plane_wm_reg_max(display, level, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

2658

max->spr = ilk_plane_wm_reg_max(display, level, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

2659

max->cur = ilk_cursor_wm_reg_max(display, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

2660

max->fbc = ilk_fbc_wm_reg_max(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2663

static bool ilk_validate_wm_level(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2687

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2691

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2695

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2708

static void ilk_compute_wm_level(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2717

u16 pri_latency = display->wm.pri_latency[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

2718

u16 spr_latency = display->wm.spr_latency[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

2719

u16 cur_latency = display->wm.cur_latency[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

2743

static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])

drivers/gpu/drm/i915/display/i9xx_wm.c

2745

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

2748

display->wm.num_levels = 5;

drivers/gpu/drm/i915/display/i9xx_wm.c

2761

static void snb_read_wm_latency(struct intel_display *display, u16 wm[])

drivers/gpu/drm/i915/display/i9xx_wm.c

2763

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

2766

display->wm.num_levels = 4;

drivers/gpu/drm/i915/display/i9xx_wm.c

2776

static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])

drivers/gpu/drm/i915/display/i9xx_wm.c

2778

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

2781

display->wm.num_levels = 3;

drivers/gpu/drm/i915/display/i9xx_wm.c

2791

static void intel_fixup_spr_wm_latency(struct intel_display *display, u16 wm[5])

drivers/gpu/drm/i915/display/i9xx_wm.c

2794

if (DISPLAY_VER(display) == 5)

drivers/gpu/drm/i915/display/i9xx_wm.c

2798

static void intel_fixup_cur_wm_latency(struct intel_display *display, u16 wm[5])

drivers/gpu/drm/i915/display/i9xx_wm.c

2801

if (DISPLAY_VER(display) == 5)

drivers/gpu/drm/i915/display/i9xx_wm.c

2805

static bool ilk_increase_wm_latency(struct intel_display *display, u16 wm[5], u16 min)

drivers/gpu/drm/i915/display/i9xx_wm.c

2813

for (level = 1; level < display->wm.num_levels; level++)

drivers/gpu/drm/i915/display/i9xx_wm.c

2819

static void snb_wm_latency_quirk(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2827

changed = ilk_increase_wm_latency(display, display->wm.pri_latency, 12);

drivers/gpu/drm/i915/display/i9xx_wm.c

2828

changed |= ilk_increase_wm_latency(display, display->wm.spr_latency, 12);

drivers/gpu/drm/i915/display/i9xx_wm.c

2829

changed |= ilk_increase_wm_latency(display, display->wm.cur_latency, 12);

drivers/gpu/drm/i915/display/i9xx_wm.c

2834

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2836

intel_print_wm_latency(display, "Primary", display->wm.pri_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2837

intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2838

intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2841

static void snb_wm_lp3_irq_quirk(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2854

if (display->wm.pri_latency[3] == 0 &&

drivers/gpu/drm/i915/display/i9xx_wm.c

2855

display->wm.spr_latency[3] == 0 &&

drivers/gpu/drm/i915/display/i9xx_wm.c

2856

display->wm.cur_latency[3] == 0)

drivers/gpu/drm/i915/display/i9xx_wm.c

2859

display->wm.pri_latency[3] = 0;

drivers/gpu/drm/i915/display/i9xx_wm.c

286

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

2860

display->wm.spr_latency[3] = 0;

drivers/gpu/drm/i915/display/i9xx_wm.c

2861

display->wm.cur_latency[3] = 0;

drivers/gpu/drm/i915/display/i9xx_wm.c

2863

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

2865

intel_print_wm_latency(display, "Primary", display->wm.pri_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2866

intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2867

intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2870

static void ilk_setup_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

2872

if (display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/i9xx_wm.c

2873

hsw_read_wm_latency(display, display->wm.pri_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2874

else if (DISPLAY_VER(display) >= 6)

drivers/gpu/drm/i915/display/i9xx_wm.c

2875

snb_read_wm_latency(display, display->wm.pri_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2877

ilk_read_wm_latency(display, display->wm.pri_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2879

memcpy(display->wm.spr_latency, display->wm.pri_latency,

drivers/gpu/drm/i915/display/i9xx_wm.c

2880

sizeof(display->wm.pri_latency));

drivers/gpu/drm/i915/display/i9xx_wm.c

2881

memcpy(display->wm.cur_latency, display->wm.pri_latency,

drivers/gpu/drm/i915/display/i9xx_wm.c

2882

sizeof(display->wm.pri_latency));

drivers/gpu/drm/i915/display/i9xx_wm.c

2884

intel_fixup_spr_wm_latency(display, display->wm.spr_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2885

intel_fixup_cur_wm_latency(display, display->wm.cur_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2887

intel_print_wm_latency(display, "Primary", display->wm.pri_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2888

intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2889

intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2891

if (DISPLAY_VER(display) == 6) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2892

snb_wm_latency_quirk(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2893

snb_wm_lp3_irq_quirk(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

2897

static bool ilk_validate_pipe_wm(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

2909

ilk_compute_wm_maximums(display, 0, &config, INTEL_DDB_PART_1_2, &max);

drivers/gpu/drm/i915/display/i9xx_wm.c

2912

if (!ilk_validate_wm_level(display, 0, &max, &pipe_wm->wm[0])) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2913

drm_dbg_kms(display->drm, "LP0 watermark invalid\n");

drivers/gpu/drm/i915/display/i9xx_wm.c

2924

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/i9xx_wm.c

295

dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

2951

usable_level = display->wm.num_levels - 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

2954

if (DISPLAY_VER(display) < 7 && pipe_wm->sprites_enabled)

drivers/gpu/drm/i915/display/i9xx_wm.c

296

dsparb2 = intel_de_read(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

2962

ilk_compute_wm_level(display, crtc, 0, crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2965

if (!ilk_validate_pipe_wm(display, pipe_wm))

drivers/gpu/drm/i915/display/i9xx_wm.c

2968

ilk_compute_wm_reg_maximums(display, 1, &max);

drivers/gpu/drm/i915/display/i9xx_wm.c

2973

ilk_compute_wm_level(display, crtc, level, crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2981

if (!ilk_validate_wm_level(display, level, &max, wm)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2998

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

301

dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

302

dsparb2 = intel_de_read(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

3023

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3044

if (!ilk_validate_pipe_wm(display, intermediate))

drivers/gpu/drm/i915/display/i9xx_wm.c

307

dsparb2 = intel_de_read(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

3076

static void ilk_merge_wm_level(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

308

dsparb3 = intel_de_read(display, DSPARB3);

drivers/gpu/drm/i915/display/i9xx_wm.c

3084

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3109

static void ilk_wm_merge(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3114

int level, num_levels = display->wm.num_levels;

drivers/gpu/drm/i915/display/i9xx_wm.c

3118

if ((DISPLAY_VER(display) < 7 || display->platform.ivybridge) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

3123

merged->fbc_wm_enabled = DISPLAY_VER(display) >= 6;

drivers/gpu/drm/i915/display/i9xx_wm.c

3129

ilk_merge_wm_level(display, level, wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

3133

else if (!ilk_validate_wm_level(display, level, max, wm))

drivers/gpu/drm/i915/display/i9xx_wm.c

3149

if (DISPLAY_VER(display) == 5 && HAS_FBC(display) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

3150

display->params.enable_fbc && !merged->fbc_wm_enabled) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3166

static unsigned int ilk_wm_lp_latency(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3169

if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/i9xx_wm.c

3172

return display->wm.pri_latency[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

3175

static void ilk_compute_wm_results(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3199

WM_LP_LATENCY(ilk_wm_lp_latency(display, level)) |

drivers/gpu/drm/i915/display/i9xx_wm.c

3206

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/i9xx_wm.c

3217

if (DISPLAY_VER(display) < 7 && r->spr_val) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3218

drm_WARN_ON(display->drm, wm_lp != 1);

drivers/gpu/drm/i915/display/i9xx_wm.c

3224

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3229

if (drm_WARN_ON(display->drm, !r->enable))

drivers/gpu/drm/i915/display/i9xx_wm.c

323

static int i9xx_get_fifo_size(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3244

ilk_find_best_result(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3250

for (level = 1; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

326

u32 dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3276

static unsigned int ilk_compute_wm_dirty(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3284

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3322

static bool _ilk_disable_lp_wm(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3325

struct ilk_wm_values *previous = &display->wm.hw;

drivers/gpu/drm/i915/display/i9xx_wm.c

333

drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",

drivers/gpu/drm/i915/display/i9xx_wm.c

3330

intel_de_write(display, WM3_LP_ILK, previous->wm_lp[2]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3335

intel_de_write(display, WM2_LP_ILK, previous->wm_lp[1]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3340

intel_de_write(display, WM1_LP_ILK, previous->wm_lp[0]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3356

static void ilk_write_wm_values(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3359

struct ilk_wm_values *previous = &display->wm.hw;

drivers/gpu/drm/i915/display/i9xx_wm.c

3362

dirty = ilk_compute_wm_dirty(display, previous, results);

drivers/gpu/drm/i915/display/i9xx_wm.c

3366

_ilk_disable_lp_wm(display, dirty);

drivers/gpu/drm/i915/display/i9xx_wm.c

3369

intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3371

intel_de_write(display, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3373

intel_de_write(display, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3376

if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/i9xx_wm.c

3377

intel_de_rmw(display, WM_MISC, WM_MISC_DATA_PARTITION_5_6,

drivers/gpu/drm/i915/display/i9xx_wm.c

3381

intel_de_rmw(display, DISP_ARB_CTL2, DISP_DATA_PARTITION_5_6,

drivers/gpu/drm/i915/display/i9xx_wm.c

3387

intel_de_rmw(display, DISP_ARB_CTL, DISP_FBC_WM_DIS,

drivers/gpu/drm/i915/display/i9xx_wm.c

339

static int i830_get_fifo_size(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3392

intel_de_write(display, WM1S_LP_ILK, results->wm_lp_spr[0]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3394

if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3396

intel_de_write(display, WM2S_LP_IVB, results->wm_lp_spr[1]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3398

intel_de_write(display, WM3S_LP_IVB, results->wm_lp_spr[2]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3402

intel_de_write(display, WM1_LP_ILK, results->wm_lp[0]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3404

intel_de_write(display, WM2_LP_ILK, results->wm_lp[1]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3406

intel_de_write(display, WM3_LP_ILK, results->wm_lp[2]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3408

display->wm.hw = *results;

drivers/gpu/drm/i915/display/i9xx_wm.c

3411

bool ilk_disable_cxsr(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

3413

return _ilk_disable_lp_wm(display, WM_DIRTY_LP_ALL);

drivers/gpu/drm/i915/display/i9xx_wm.c

3416

static void ilk_compute_wm_config(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

342

u32 dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3422

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3434

static void ilk_program_watermarks(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

3442

ilk_compute_wm_config(display, &config);

drivers/gpu/drm/i915/display/i9xx_wm.c

3444

ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_1_2, &max);

drivers/gpu/drm/i915/display/i9xx_wm.c

3445

ilk_wm_merge(display, &config, &max, &lp_wm_1_2);

drivers/gpu/drm/i915/display/i9xx_wm.c

3448

if (DISPLAY_VER(display) >= 7 &&

drivers/gpu/drm/i915/display/i9xx_wm.c

3450

ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_5_6, &max);

drivers/gpu/drm/i915/display/i9xx_wm.c

3451

ilk_wm_merge(display, &config, &max, &lp_wm_5_6);

drivers/gpu/drm/i915/display/i9xx_wm.c

3453

best_lp_wm = ilk_find_best_result(display, &lp_wm_1_2, &lp_wm_5_6);

drivers/gpu/drm/i915/display/i9xx_wm.c

3461

ilk_compute_wm_results(display, best_lp_wm, partitioning, &results);

drivers/gpu/drm/i915/display/i9xx_wm.c

3463

ilk_write_wm_values(display, &results);

drivers/gpu/drm/i915/display/i9xx_wm.c

3469

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

3473

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

3475

ilk_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

3476

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

3482

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

3489

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

3491

ilk_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

3492

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

3497

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

3498

struct ilk_wm_values *hw = &display->wm.hw;

drivers/gpu/drm/i915/display/i9xx_wm.c

350

drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",

drivers/gpu/drm/i915/display/i9xx_wm.c

3503

hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));

drivers/gpu/drm/i915/display/i9xx_wm.c

3530

for (level = 0; level < display->wm.num_levels; level++)

drivers/gpu/drm/i915/display/i9xx_wm.c

356

static int i845_get_fifo_size(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3579

void ilk_wm_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

359

u32 dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3590

if (!display->funcs.wm->optimize_watermarks)

drivers/gpu/drm/i915/display/i9xx_wm.c

3593

if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))

drivers/gpu/drm/i915/display/i9xx_wm.c

3596

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

3597

if (drm_WARN_ON(display->drm, !state))

drivers/gpu/drm/i915/display/i9xx_wm.c

3613

if (!HAS_GMCH(display))

drivers/gpu/drm/i915/display/i9xx_wm.c

3620

ret = intel_atomic_check(display->drm, state);

drivers/gpu/drm/i915/display/i9xx_wm.c

365

drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",

drivers/gpu/drm/i915/display/i9xx_wm.c

3650

drm_WARN(display->drm, ret,

drivers/gpu/drm/i915/display/i9xx_wm.c

3664

static void g4x_read_wm_values(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3669

tmp = intel_de_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3675

tmp = intel_de_read(display, DSPFW2(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3683

tmp = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3690

static void vlv_read_wm_values(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

3696

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3697

tmp = intel_de_read(display, VLV_DDL(pipe));

drivers/gpu/drm/i915/display/i9xx_wm.c

3709

tmp = intel_de_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3715

tmp = intel_de_read(display, DSPFW2(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3720

tmp = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3723

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3724

tmp = intel_de_read(display, DSPFW7_CHV);

drivers/gpu/drm/i915/display/i9xx_wm.c

3728

tmp = intel_de_read(display, DSPFW8_CHV);

drivers/gpu/drm/i915/display/i9xx_wm.c

3732

tmp = intel_de_read(display, DSPFW9_CHV);

drivers/gpu/drm/i915/display/i9xx_wm.c

3736

tmp = intel_de_read(display, DSPHOWM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3748

tmp = intel_de_read(display, DSPFW7);

drivers/gpu/drm/i915/display/i9xx_wm.c

3752

tmp = intel_de_read(display, DSPHOWM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3766

static void g4x_wm_get_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

3768

struct g4x_wm_values *wm = &display->wm.g4x;

drivers/gpu/drm/i915/display/i9xx_wm.c

3771

g4x_read_wm_values(display, wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

3773

wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

3775

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3840

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

3848

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

3851

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

3854

drm_dbg_kms(display->drm, "Initial SR=%s HPLL=%s FBC=%s\n",

drivers/gpu/drm/i915/display/i9xx_wm.c

3859

static void g4x_wm_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

3864

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

3866

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3868

intel_crtc_for_pipe(display, plane->pipe);

drivers/gpu/drm/i915/display/i9xx_wm.c

3879

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3890

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3896

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/i9xx_wm.c

3903

g4x_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

3905

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

3908

static void vlv_wm_get_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

3910

struct vlv_wm_values *wm = &display->wm.vlv;

drivers/gpu/drm/i915/display/i9xx_wm.c

3915

vlv_read_wm_values(display, wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

3917

wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

drivers/gpu/drm/i915/display/i9xx_wm.c

3920

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3921

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

3923

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3936

val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

drivers/gpu/drm/i915/display/i9xx_wm.c

3938

vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

3940

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),

drivers/gpu/drm/i915/display/i9xx_wm.c

3944

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

3947

display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

3949

val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

drivers/gpu/drm/i915/display/i9xx_wm.c

3954

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/i9xx_wm.c

3957

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3997

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

4006

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

4011

static void vlv_wm_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

4016

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

4018

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4020

intel_crtc_for_pipe(display, plane->pipe);

drivers/gpu/drm/i915/display/i9xx_wm.c

4031

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4039

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4045

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/i9xx_wm.c

4052

vlv_program_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

4054

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/i9xx_wm.c

4061

static void ilk_init_lp_watermarks(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

4063

intel_de_rmw(display, WM3_LP_ILK, WM_LP_ENABLE, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

4064

intel_de_rmw(display, WM2_LP_ILK, WM_LP_ENABLE, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

4065

intel_de_rmw(display, WM1_LP_ILK, WM_LP_ENABLE, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

4073

static void ilk_wm_get_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

4075

struct ilk_wm_values *hw = &display->wm.hw;

drivers/gpu/drm/i915/display/i9xx_wm.c

4078

ilk_init_lp_watermarks(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

4080

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/i9xx_wm.c

4083

hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4084

hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4085

hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4087

hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4088

if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4089

hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);

drivers/gpu/drm/i915/display/i9xx_wm.c

4090

hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);

drivers/gpu/drm/i915/display/i9xx_wm.c

4093

if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/i9xx_wm.c

4094

hw->partitioning = (intel_de_read(display, WM_MISC) &

drivers/gpu/drm/i915/display/i9xx_wm.c

4097

else if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/i9xx_wm.c

4098

hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &

drivers/gpu/drm/i915/display/i9xx_wm.c

4103

!(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);

drivers/gpu/drm/i915/display/i9xx_wm.c

4153

void i9xx_wm_init(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

4156

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4157

ilk_setup_wm_latency(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

4158

display->funcs.wm = &ilk_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4159

} else if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4160

vlv_setup_wm_latency(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

4161

display->funcs.wm = &vlv_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4162

} else if (display->platform.g4x) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4163

g4x_setup_wm_latency(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

4164

display->funcs.wm = &g4x_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4165

} else if (display->platform.pineview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4166

if (!pnv_get_cxsr_latency(display)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4167

drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");

drivers/gpu/drm/i915/display/i9xx_wm.c

4169

intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

4170

display->funcs.wm = &nop_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4172

display->funcs.wm = &pnv_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4174

} else if (DISPLAY_VER(display) == 4) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4175

display->funcs.wm = &i965_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4176

} else if (DISPLAY_VER(display) == 3) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4177

display->funcs.wm = &i9xx_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4178

} else if (DISPLAY_VER(display) == 2) {

drivers/gpu/drm/i915/display/i9xx_wm.c

4179

if (INTEL_NUM_PIPES(display) == 1)

drivers/gpu/drm/i915/display/i9xx_wm.c

4180

display->funcs.wm = &i845_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4182

display->funcs.wm = &i9xx_wm_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

4184

drm_err(display->drm,

drivers/gpu/drm/i915/display/i9xx_wm.c

4186

display->funcs.wm = &nop_funcs;

drivers/gpu/drm/i915/display/i9xx_wm.c

568

static unsigned int intel_calculate_wm(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

586

drm_dbg_kms(display->drm, "FIFO entries required for mode: %d\n", entries);

drivers/gpu/drm/i915/display/i9xx_wm.c

589

drm_dbg_kms(display->drm, "FIFO watermark level: %d\n", wm_size);

drivers/gpu/drm/i915/display/i9xx_wm.c

639

static struct intel_crtc *single_enabled_crtc(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

643

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/i9xx_wm.c

654

static void pnv_update_wm(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

661

latency = pnv_get_cxsr_latency(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

663

drm_dbg_kms(display->drm, "Unknown FSB/MEM, disabling CxSR\n");

drivers/gpu/drm/i915/display/i9xx_wm.c

664

intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

668

crtc = single_enabled_crtc(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

676

wm = intel_calculate_wm(display, pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

680

reg = intel_de_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

683

intel_de_write(display, DSPFW1(display), reg);

drivers/gpu/drm/i915/display/i9xx_wm.c

684

drm_dbg_kms(display->drm, "DSPFW1 register is %x\n", reg);

drivers/gpu/drm/i915/display/i9xx_wm.c

687

wm = intel_calculate_wm(display, pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

691

intel_de_rmw(display, DSPFW3(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

695

wm = intel_calculate_wm(display, pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

699

intel_de_rmw(display, DSPFW3(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

703

wm = intel_calculate_wm(display, pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

707

reg = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

710

intel_de_write(display, DSPFW3(display), reg);

drivers/gpu/drm/i915/display/i9xx_wm.c

711

drm_dbg_kms(display->drm, "DSPFW3 register is %x\n", reg);

drivers/gpu/drm/i915/display/i9xx_wm.c

713

intel_set_memory_cxsr(display, true);

drivers/gpu/drm/i915/display/i9xx_wm.c

715

intel_set_memory_cxsr(display, false);

drivers/gpu/drm/i915/display/i9xx_wm.c

806

static void g4x_write_wm_values(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

811

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/i9xx_wm.c

812

trace_g4x_wm(intel_crtc_for_pipe(display, pipe), wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

814

intel_de_write(display, DSPFW1(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

819

intel_de_write(display, DSPFW2(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

826

intel_de_write(display, DSPFW3(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

832

intel_de_posting_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

838

static void vlv_write_wm_values(struct intel_display *display,

drivers/gpu/drm/i915/display/i9xx_wm.c

843

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/i9xx_wm.c

844

trace_vlv_wm(intel_crtc_for_pipe(display, pipe), wm);

drivers/gpu/drm/i915/display/i9xx_wm.c

846

intel_de_write(display, VLV_DDL(pipe),

drivers/gpu/drm/i915/display/i9xx_wm.c

858

intel_de_write(display, DSPHOWM, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

859

intel_de_write(display, DSPHOWM1, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

860

intel_de_write(display, DSPFW4, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

861

intel_de_write(display, DSPFW5, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

862

intel_de_write(display, DSPFW6, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

864

intel_de_write(display, DSPFW1(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

869

intel_de_write(display, DSPFW2(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

873

intel_de_write(display, DSPFW3(display),

drivers/gpu/drm/i915/display/i9xx_wm.c

876

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/i9xx_wm.c

877

intel_de_write(display, DSPFW7_CHV,

drivers/gpu/drm/i915/display/i9xx_wm.c

880

intel_de_write(display, DSPFW8_CHV,

drivers/gpu/drm/i915/display/i9xx_wm.c

883

intel_de_write(display, DSPFW9_CHV,

drivers/gpu/drm/i915/display/i9xx_wm.c

886

intel_de_write(display, DSPHOWM,

drivers/gpu/drm/i915/display/i9xx_wm.c

898

intel_de_write(display, DSPFW7,

drivers/gpu/drm/i915/display/i9xx_wm.c

901

intel_de_write(display, DSPHOWM,

drivers/gpu/drm/i915/display/i9xx_wm.c

91

static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

911

intel_de_posting_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

916

static void g4x_setup_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.c

919

display->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;

drivers/gpu/drm/i915/display/i9xx_wm.c

920

display->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;

drivers/gpu/drm/i915/display/i9xx_wm.c

921

display->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;

drivers/gpu/drm/i915/display/i9xx_wm.c

923

display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

93

const struct dram_info *dram_info = intel_dram_info(display);

drivers/gpu/drm/i915/display/i9xx_wm.c

972

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

976

unsigned int latency = display->wm.pri_latency[level] * 10;

drivers/gpu/drm/i915/display/i9xx_wm.c

99

bool is_desktop = !display->platform.mobile;

drivers/gpu/drm/i915/display/i9xx_wm.h

16

bool ilk_disable_cxsr(struct intel_display *display);

drivers/gpu/drm/i915/display/i9xx_wm.h

17

void ilk_wm_sanitize(struct intel_display *display);

drivers/gpu/drm/i915/display/i9xx_wm.h

18

bool intel_set_memory_cxsr(struct intel_display *display, bool enable);

drivers/gpu/drm/i915/display/i9xx_wm.h

19

void i9xx_wm_init(struct intel_display *display);

drivers/gpu/drm/i915/display/i9xx_wm.h

21

static inline bool ilk_disable_cxsr(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.h

25

static inline void ilk_wm_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/i9xx_wm.h

28

static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/i9xx_wm.h

32

static inline void i9xx_wm_init(struct intel_display *display)

drivers/gpu/drm/i915/display/icl_dsi.c

1000

intel_de_write(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1001

TRANS_VSYNC(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1015

intel_de_write(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1016

TRANS_VSYNCSHIFT(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1027

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/icl_dsi.c

1030

intel_de_write(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1031

TRANS_VBLANK(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1039

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1046

intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,

drivers/gpu/drm/i915/display/icl_dsi.c

1050

if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1052

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1060

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1084

intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1091

intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1098

intel_de_rmw(display, DSI_TA_TO(dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1107

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1119

tmp = intel_de_read(display, UTIL_PIN_CTL);

drivers/gpu/drm/i915/display/icl_dsi.c

1127

intel_de_write(display, UTIL_PIN_CTL, tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

116

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1165

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1181

tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1188

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1248

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1250

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)

drivers/gpu/drm/i915/display/icl_dsi.c

1251

intel_de_rmw(display, CHICKEN_PAR1_1,

drivers/gpu/drm/i915/display/icl_dsi.c

126

wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);

drivers/gpu/drm/i915/display/icl_dsi.c

1264

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1268

if (DISPLAY_VER(display) == 13) {

drivers/gpu/drm/i915/display/icl_dsi.c

127

wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);

drivers/gpu/drm/i915/display/icl_dsi.c

1270

intel_de_rmw(display, TGL_DSI_CHKN_REG(port),

drivers/gpu/drm/i915/display/icl_dsi.c

1306

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1315

intel_de_rmw(display, TRANSCONF(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1319

if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1321

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1338

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1348

intel_de_rmw(display, DSI_CMD_FRMCTL(port),

drivers/gpu/drm/i915/display/icl_dsi.c

1355

tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1358

intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

1360

ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1363

drm_err(display->drm, "DSI link not in ULPS\n");

drivers/gpu/drm/i915/display/icl_dsi.c

1369

intel_de_rmw(display,

drivers/gpu/drm/i915/display/icl_dsi.c

137

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1370

TRANS_DDI_FUNC_CTL(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1378

intel_de_rmw(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1379

TRANS_DDI_FUNC_CTL2(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

1387

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1394

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);

drivers/gpu/drm/i915/display/icl_dsi.c

1396

ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),

drivers/gpu/drm/i915/display/icl_dsi.c

1400

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1409

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1417

intel_display_power_put(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1426

intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),

drivers/gpu/drm/i915/display/icl_dsi.c

144

wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);

drivers/gpu/drm/i915/display/icl_dsi.c

1488

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/icl_dsi.c

1491

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/icl_dsi.c

151

ret = intel_de_wait_for_clear_us(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1540

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/icl_dsi.c

1549

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

155

drm_err(display->drm, "LPTX bit not cleared\n");

drivers/gpu/drm/i915/display/icl_dsi.c

1592

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1603

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&

drivers/gpu/drm/i915/display/icl_dsi.c

1604

!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))

drivers/gpu/drm/i915/display/icl_dsi.c

1605

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1614

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1616

int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;

drivers/gpu/drm/i915/display/icl_dsi.c

163

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/icl_dsi.c

1643

drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);

drivers/gpu/drm/i915/display/icl_dsi.c

1644

drm_WARN_ON(display->drm, vdsc_cfg->simple_422);

drivers/gpu/drm/i915/display/icl_dsi.c

1645

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1647

drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);

drivers/gpu/drm/i915/display/icl_dsi.c

1648

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

1664

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1698

drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");

drivers/gpu/drm/i915/display/icl_dsi.c

171

drm_err(display->drm, "payload size exceeds max queue limit\n");

drivers/gpu/drm/i915/display/icl_dsi.c

1722

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

1730

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1737

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1738

TRANS_DDI_FUNC_CTL(display, dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1753

drm_err(display->drm, "Invalid PIPE input\n");

drivers/gpu/drm/i915/display/icl_dsi.c

1757

tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1761

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/icl_dsi.c

178

if (!wait_for_payload_credits(display, dsi_trans, 1))

drivers/gpu/drm/i915/display/icl_dsi.c

184

intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

1924

void icl_dsi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/icl_dsi.c

195

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/icl_dsi.c

1954

drm_encoder_init(display->drm, &encoder->base,

drivers/gpu/drm/i915/display/icl_dsi.c

1980

drm_connector_init(display->drm, connector,

drivers/gpu/drm/i915/display/icl_dsi.c

199

if (!wait_for_header_credits(display, dsi_trans, 1))

drivers/gpu/drm/i915/display/icl_dsi.c

1992

intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);

drivers/gpu/drm/i915/display/icl_dsi.c

1994

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/icl_dsi.c

1996

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/icl_dsi.c

1999

drm_err(display->drm, "DSI fixed mode info missing\n");

drivers/gpu/drm/i915/display/icl_dsi.c

2012

if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))

drivers/gpu/drm/i915/display/icl_dsi.c

2015

if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))

drivers/gpu/drm/i915/display/icl_dsi.c

202

tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

2029

drm_dbg_kms(display->drm, "no device found\n");

drivers/gpu/drm/i915/display/icl_dsi.c

221

intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

228

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

246

intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,

drivers/gpu/drm/i915/display/icl_dsi.c

252

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

266

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

269

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

270

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);

drivers/gpu/drm/i915/display/icl_dsi.c

276

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

279

intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

280

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);

drivers/gpu/drm/i915/display/icl_dsi.c

286

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);

drivers/gpu/drm/i915/display/icl_dsi.c

290

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),

drivers/gpu/drm/i915/display/icl_dsi.c

298

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

304

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/icl_dsi.c

314

dss_ctl1 = intel_de_read(display, dss_ctl1_reg);

drivers/gpu/drm/i915/display/icl_dsi.c

329

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

334

intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,

drivers/gpu/drm/i915/display/icl_dsi.c

341

intel_de_write(display, dss_ctl1_reg, dss_ctl1);

drivers/gpu/drm/i915/display/icl_dsi.c

362

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

371

if (display->platform.alderlake_s || display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/icl_dsi.c

381

intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),

drivers/gpu/drm/i915/display/icl_dsi.c

383

intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));

drivers/gpu/drm/i915/display/icl_dsi.c

387

intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),

drivers/gpu/drm/i915/display/icl_dsi.c

389

intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));

drivers/gpu/drm/i915/display/icl_dsi.c

392

if (display->platform.alderlake_s || display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/icl_dsi.c

394

intel_de_write(display, ADL_MIPIO_DW(port, 8),

drivers/gpu/drm/i915/display/icl_dsi.c

396

intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));

drivers/gpu/drm/i915/display/icl_dsi.c

403

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/icl_dsi.c

407

drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);

drivers/gpu/drm/i915/display/icl_dsi.c

409

intel_display_power_get(display,

drivers/gpu/drm/i915/display/icl_dsi.c

418

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

423

intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),

drivers/gpu/drm/i915/display/icl_dsi.c

431

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

436

intel_combo_phy_power_up_lanes(display, phy, true,

drivers/gpu/drm/i915/display/icl_dsi.c

442

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

450

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),

drivers/gpu/drm/i915/display/icl_dsi.c

453

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),

drivers/gpu/drm/i915/display/icl_dsi.c

459

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),

drivers/gpu/drm/i915/display/icl_dsi.c

461

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

464

intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

467

if (display->platform.jasperlake || display->platform.elkhartlake ||

drivers/gpu/drm/i915/display/icl_dsi.c

468

(DISPLAY_VER(display) >= 12)) {

drivers/gpu/drm/i915/display/icl_dsi.c

469

intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),

drivers/gpu/drm/i915/display/icl_dsi.c

472

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/icl_dsi.c

476

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),

drivers/gpu/drm/i915/display/icl_dsi.c

485

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

492

tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

494

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

495

intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);

drivers/gpu/drm/i915/display/icl_dsi.c

504

intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,

drivers/gpu/drm/i915/display/icl_dsi.c

509

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

511

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

512

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);

drivers/gpu/drm/i915/display/icl_dsi.c

520

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

522

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

523

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);

drivers/gpu/drm/i915/display/icl_dsi.c

529

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

535

intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);

drivers/gpu/drm/i915/display/icl_dsi.c

537

ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),

drivers/gpu/drm/i915/display/icl_dsi.c

540

drm_err(display->drm, "DDI port:%c buffer idle\n",

drivers/gpu/drm/i915/display/icl_dsi.c

549

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

556

intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),

drivers/gpu/drm/i915/display/icl_dsi.c

561

intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),

drivers/gpu/drm/i915/display/icl_dsi.c

570

if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/icl_dsi.c

573

intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),

drivers/gpu/drm/i915/display/icl_dsi.c

579

if (display->platform.jasperlake || display->platform.elkhartlake) {

drivers/gpu/drm/i915/display/icl_dsi.c

581

intel_de_rmw(display, ICL_DPHY_CHKN(phy),

drivers/gpu/drm/i915/display/icl_dsi.c

590

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

596

intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),

drivers/gpu/drm/i915/display/icl_dsi.c

60

static int header_credits_available(struct intel_display *display,

drivers/gpu/drm/i915/display/icl_dsi.c

601

intel_de_write(display, DSI_CLK_TIMING_PARAM(port),

drivers/gpu/drm/i915/display/icl_dsi.c

606

intel_de_write(display, DSI_DATA_TIMING_PARAM(port),

drivers/gpu/drm/i915/display/icl_dsi.c

610

if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/icl_dsi.c

613

intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),

drivers/gpu/drm/i915/display/icl_dsi.c

623

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

628

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

629

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

63

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)

drivers/gpu/drm/i915/display/icl_dsi.c

633

intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

634

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

639

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

644

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

645

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

649

intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

650

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

655

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

661

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

67

static int payload_credits_available(struct intel_display *display,

drivers/gpu/drm/i915/display/icl_dsi.c

674

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

680

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

682

val = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

687

intel_de_write(display, ICL_DPCLKA_CFGCR0, val);

drivers/gpu/drm/i915/display/icl_dsi.c

692

intel_de_write(display, ICL_DPCLKA_CFGCR0, val);

drivers/gpu/drm/i915/display/icl_dsi.c

694

intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

696

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

70

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)

drivers/gpu/drm/i915/display/icl_dsi.c

703

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

713

tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

74

static bool wait_for_header_credits(struct intel_display *display,

drivers/gpu/drm/i915/display/icl_dsi.c

769

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/icl_dsi.c

79

ret = poll_timeout_us(available = header_credits_available(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

802

intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

809

intel_de_rmw(display,

drivers/gpu/drm/i915/display/icl_dsi.c

810

TRANS_DDI_FUNC_CTL2(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

822

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/icl_dsi.c

823

TRANS_DDI_FUNC_CTL(display, dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

83

drm_err(display->drm, "DSI header credits not released\n");

drivers/gpu/drm/i915/display/icl_dsi.c

849

intel_de_write(display,

drivers/gpu/drm/i915/display/icl_dsi.c

850

TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);

drivers/gpu/drm/i915/display/icl_dsi.c

859

ret = intel_de_wait_for_set_us(display,

drivers/gpu/drm/i915/display/icl_dsi.c

863

drm_err(display->drm, "DSI link not ready\n");

drivers/gpu/drm/i915/display/icl_dsi.c

871

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/icl_dsi.c

90

static bool wait_for_payload_credits(struct intel_display *display,

drivers/gpu/drm/i915/display/icl_dsi.c

938

drm_err(display->drm, "hactive is less then 256 pixels\n");

drivers/gpu/drm/i915/display/icl_dsi.c

942

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

948

intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

95

ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

957

drm_err(display->drm,

drivers/gpu/drm/i915/display/icl_dsi.c

962

drm_err(display->drm, "hback porch < 16 pixels\n");

drivers/gpu/drm/i915/display/icl_dsi.c

971

intel_de_write(display,

drivers/gpu/drm/i915/display/icl_dsi.c

972

TRANS_HSYNC(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

986

intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),

drivers/gpu/drm/i915/display/icl_dsi.c

99

drm_err(display->drm, "DSI payload credits not released\n");

drivers/gpu/drm/i915/display/icl_dsi.c

991

drm_err(display->drm, "Invalid vsync_end value\n");

drivers/gpu/drm/i915/display/icl_dsi.c

994

drm_err(display->drm, "vsync_start less than vactive\n");

drivers/gpu/drm/i915/display/icl_dsi.h

13

void icl_dsi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_acpi.c

190

void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_acpi.c

192

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_acpi.c

270

void intel_acpi_device_id_update(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_acpi.c

277

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_acpi.c

294

void intel_acpi_assign_connector_fwnodes(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_acpi.c

296

struct drm_device *drm_dev = display->drm;

drivers/gpu/drm/i915/display/intel_acpi.c

339

void intel_acpi_video_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_acpi.c

353

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_acpi.h

14

void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_acpi.h

15

void intel_acpi_device_id_update(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_acpi.h

16

void intel_acpi_assign_connector_fwnodes(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_acpi.h

17

void intel_acpi_video_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_acpi.h

22

void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; }

drivers/gpu/drm/i915/display/intel_acpi.h

24

void intel_acpi_device_id_update(struct intel_display *display) { return; }

drivers/gpu/drm/i915/display/intel_acpi.h

26

void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; }

drivers/gpu/drm/i915/display/intel_acpi.h

28

void intel_acpi_video_register(struct intel_display *display) { return; }

drivers/gpu/drm/i915/display/intel_alpm.c

121

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

138

if (display->params.psr_safest_params)

drivers/gpu/drm/i915/display/intel_alpm.c

151

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

154

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_alpm.c

167

if (display->params.psr_safest_params)

drivers/gpu/drm/i915/display/intel_alpm.c

192

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

194

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_alpm.c

203

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

216

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_alpm.c

218

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_alpm.c

235

if (display->params.psr_safest_params)

drivers/gpu/drm/i915/display/intel_alpm.c

249

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

255

drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");

drivers/gpu/drm/i915/display/intel_alpm.c

265

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_alpm.c

301

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

305

if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_alpm.c

328

intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_alpm.c

339

drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n");

drivers/gpu/drm/i915/display/intel_alpm.c

344

intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);

drivers/gpu/drm/i915/display/intel_alpm.c

358

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

362

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_alpm.c

380

intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);

drivers/gpu/drm/i915/display/intel_alpm.c

382

intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);

drivers/gpu/drm/i915/display/intel_alpm.c

388

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_alpm.c

396

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_alpm.c

402

for_each_intel_encoder_mask(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_alpm.c

416

intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_alpm.c

417

drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");

drivers/gpu/drm/i915/display/intel_alpm.c

443

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_alpm.c

454

for_each_intel_encoder_mask(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_alpm.c

473

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_alpm.c

480

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_alpm.c

492

alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_alpm.c

499

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_alpm.c

534

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_alpm.c

537

if (DISPLAY_VER(display) < 20 ||

drivers/gpu/drm/i915/display/intel_alpm.c

550

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

553

if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)

drivers/gpu/drm/i915/display/intel_alpm.c

558

intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_alpm.c

561

drm_dbg_kms(display->drm, "Disabling ALPM\n");

drivers/gpu/drm/i915/display/intel_alpm.c

567

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

574

drm_err(display->drm, "Error reading ALPM status\n");

drivers/gpu/drm/i915/display/intel_alpm.c

579

drm_dbg_kms(display->drm, "ALPM lock timeout error\n");

drivers/gpu/drm/i915/display/intel_atomic.c

104

if (property == display->properties.broadcast_rgb) {

drivers/gpu/drm/i915/display/intel_atomic.c

109

drm_dbg_atomic(display->drm, "Unknown property [PROP:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_atomic.c

63

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_atomic.c

67

if (property == display->properties.force_audio)

drivers/gpu/drm/i915/display/intel_atomic.c

69

else if (property == display->properties.broadcast_rgb)

drivers/gpu/drm/i915/display/intel_atomic.c

72

drm_dbg_atomic(display->drm,

drivers/gpu/drm/i915/display/intel_atomic.c

95

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_atomic.c

99

if (property == display->properties.force_audio) {

drivers/gpu/drm/i915/display/intel_audio.c

1012

if (DISPLAY_VER(display) == 10) {

drivers/gpu/drm/i915/display/intel_audio.c

1015

} else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_audio.c

1025

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_audio.c

1035

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_audio.c

1044

struct intel_display *display = to_intel_display(kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1050

wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK);

drivers/gpu/drm/i915/display/intel_audio.c

1052

if (display->audio.power_refcount++ == 0) {

drivers/gpu/drm/i915/display/intel_audio.c

1053

if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_audio.c

1054

intel_de_write(display, AUD_FREQ_CNTRL,

drivers/gpu/drm/i915/display/intel_audio.c

1055

display->audio.freq_cntrl);

drivers/gpu/drm/i915/display/intel_audio.c

1056

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

1058

display->audio.freq_cntrl);

drivers/gpu/drm/i915/display/intel_audio.c

1062

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_audio.c

1063

glk_force_audio_cdclk(display, true);

drivers/gpu/drm/i915/display/intel_audio.c

1065

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_audio.c

1066

intel_de_rmw(display, AUD_PIN_BUF_CTL,

drivers/gpu/drm/i915/display/intel_audio.c

1076

struct intel_display *display = to_intel_display(kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1080

if (--display->audio.power_refcount == 0)

drivers/gpu/drm/i915/display/intel_audio.c

1081

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_audio.c

1082

glk_force_audio_cdclk(display, false);

drivers/gpu/drm/i915/display/intel_audio.c

1084

intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref);

drivers/gpu/drm/i915/display/intel_audio.c

1090

struct intel_display *display = to_intel_display(kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1093

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_audio.c

1102

intel_de_rmw(display, HSW_AUD_CHICKENBIT,

drivers/gpu/drm/i915/display/intel_audio.c

1107

intel_de_rmw(display, HSW_AUD_CHICKENBIT,

drivers/gpu/drm/i915/display/intel_audio.c

1118

struct intel_display *display = to_intel_display(kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1120

if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display)))

drivers/gpu/drm/i915/display/intel_audio.c

1123

return display->cdclk.hw.cdclk;

drivers/gpu/drm/i915/display/intel_audio.c

1135

static struct intel_audio_state *find_audio_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_audio.c

1143

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

1144

cpu_transcoder >= ARRAY_SIZE(display->audio.state)))

drivers/gpu/drm/i915/display/intel_audio.c

1147

audio_state = &display->audio.state[cpu_transcoder];

drivers/gpu/drm/i915/display/intel_audio.c

1159

for_each_cpu_transcoder(display, cpu_transcoder) {

drivers/gpu/drm/i915/display/intel_audio.c

1163

audio_state = &display->audio.state[cpu_transcoder];

drivers/gpu/drm/i915/display/intel_audio.c

1177

struct intel_display *display = to_intel_display(kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1178

struct i915_audio_component *acomp = display->audio.component;

drivers/gpu/drm/i915/display/intel_audio.c

1185

if (!HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_audio.c

1189

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

1191

audio_state = find_audio_state(display, port, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_audio.c

1193

drm_dbg_kms(display->drm, "Not valid for port %c\n",

drivers/gpu/drm/i915/display/intel_audio.c

1211

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

1220

struct intel_display *display = to_intel_display(kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1224

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

1226

audio_state = find_audio_state(display, port, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_audio.c

1228

drm_dbg_kms(display->drm, "Not valid for port %c\n",

drivers/gpu/drm/i915/display/intel_audio.c

1230

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

1242

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

1259

struct intel_display *display = to_intel_display(drv_kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1263

if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev))

drivers/gpu/drm/i915/display/intel_audio.c

1266

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

1271

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_audio.c

1277

display->audio.component = acomp;

drivers/gpu/drm/i915/display/intel_audio.c

1278

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_audio.c

1286

struct intel_display *display = to_intel_display(drv_kdev);

drivers/gpu/drm/i915/display/intel_audio.c

1289

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_audio.c

1292

display->audio.component = NULL;

drivers/gpu/drm/i915/display/intel_audio.c

1293

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_audio.c

1297

if (display->audio.power_refcount)

drivers/gpu/drm/i915/display/intel_audio.c

1298

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

1300

display->audio.power_refcount);

drivers/gpu/drm/i915/display/intel_audio.c

1333

static void intel_audio_component_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

1337

if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_audio.c

1338

aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);

drivers/gpu/drm/i915/display/intel_audio.c

1340

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_audio.c

1346

if ((display->platform.tigerlake || display->platform.rocketlake) &&

drivers/gpu/drm/i915/display/intel_audio.c

1350

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

1354

display->audio.freq_cntrl = aud_freq;

drivers/gpu/drm/i915/display/intel_audio.c

1358

intel_audio_cdclk_change_post(display);

drivers/gpu/drm/i915/display/intel_audio.c

1361

static void intel_audio_component_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

1365

ret = component_add_typed(display->drm->dev,

drivers/gpu/drm/i915/display/intel_audio.c

1369

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

1375

display->audio.component_registered = true;

drivers/gpu/drm/i915/display/intel_audio.c

1385

static void intel_audio_component_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

1387

if (!display->audio.component_registered)

drivers/gpu/drm/i915/display/intel_audio.c

1390

component_del(display->drm->dev, &intel_audio_component_bind_ops);

drivers/gpu/drm/i915/display/intel_audio.c

1391

display->audio.component_registered = false;

drivers/gpu/drm/i915/display/intel_audio.c

1400

void intel_audio_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

1402

if (intel_lpe_audio_init(display) < 0)

drivers/gpu/drm/i915/display/intel_audio.c

1403

intel_audio_component_init(display);

drivers/gpu/drm/i915/display/intel_audio.c

1406

void intel_audio_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

1408

if (!display->audio.lpe.platdev)

drivers/gpu/drm/i915/display/intel_audio.c

1409

intel_audio_component_register(display);

drivers/gpu/drm/i915/display/intel_audio.c

1416

void intel_audio_deinit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

1418

if (display->audio.lpe.platdev)

drivers/gpu/drm/i915/display/intel_audio.c

1419

intel_lpe_audio_teardown(display);

drivers/gpu/drm/i915/display/intel_audio.c

1421

intel_audio_component_cleanup(display);

drivers/gpu/drm/i915/display/intel_audio.c

191

static bool needs_wa_14020863754(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

193

return DISPLAY_VERx100(display) == 3000 ||

drivers/gpu/drm/i915/display/intel_audio.c

194

DISPLAY_VERx100(display) == 2000 ||

drivers/gpu/drm/i915/display/intel_audio.c

195

DISPLAY_VERx100(display) == 1401;

drivers/gpu/drm/i915/display/intel_audio.c

201

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

211

if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500)

drivers/gpu/drm/i915/display/intel_audio.c

215

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

221

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

256

static int g4x_eld_buffer_size(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

260

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

drivers/gpu/drm/i915/display/intel_audio.c

268

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

273

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

drivers/gpu/drm/i915/display/intel_audio.c

277

intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);

drivers/gpu/drm/i915/display/intel_audio.c

279

eld_buffer_size = g4x_eld_buffer_size(display);

drivers/gpu/drm/i915/display/intel_audio.c

283

eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);

drivers/gpu/drm/i915/display/intel_audio.c

290

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

294

intel_de_rmw(display, G4X_AUD_CNTL_ST,

drivers/gpu/drm/i915/display/intel_audio.c

305

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

312

intel_de_rmw(display, G4X_AUD_CNTL_ST,

drivers/gpu/drm/i915/display/intel_audio.c

315

eld_buffer_size = g4x_eld_buffer_size(display);

drivers/gpu/drm/i915/display/intel_audio.c

319

intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]);

drivers/gpu/drm/i915/display/intel_audio.c

321

intel_de_write(display, G4X_HDMIW_HDMIEDID, 0);

drivers/gpu/drm/i915/display/intel_audio.c

323

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

324

(intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);

drivers/gpu/drm/i915/display/intel_audio.c

326

intel_de_rmw(display, G4X_AUD_CNTL_ST,

drivers/gpu/drm/i915/display/intel_audio.c

334

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

338

intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_audio.c

352

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

353

struct i915_audio_component *acomp = display->audio.component;

drivers/gpu/drm/i915/display/intel_audio.c

361

tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_audio.c

369

drm_dbg_kms(display->drm, "using N %d\n", n);

drivers/gpu/drm/i915/display/intel_audio.c

375

drm_dbg_kms(display->drm, "using automatic N\n");

drivers/gpu/drm/i915/display/intel_audio.c

378

intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp);

drivers/gpu/drm/i915/display/intel_audio.c

384

tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_audio.c

387

intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);

drivers/gpu/drm/i915/display/intel_audio.c

403

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

406

if (!HAS_DP20(display))

drivers/gpu/drm/i915/display/intel_audio.c

409

intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,

drivers/gpu/drm/i915/display/intel_audio.c

417

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

421

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

424

intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_audio.c

433

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

drivers/gpu/drm/i915/display/intel_audio.c

440

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

drivers/gpu/drm/i915/display/intel_audio.c

443

if (needs_wa_14020863754(display))

drivers/gpu/drm/i915/display/intel_audio.c

444

intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0);

drivers/gpu/drm/i915/display/intel_audio.c

448

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

454

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

466

cdclk = display->cdclk.hw.cdclk;

drivers/gpu/drm/i915/display/intel_audio.c

472

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

517

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

522

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_audio.c

525

val = intel_de_read(display, AUD_CONFIG_BE);

drivers/gpu/drm/i915/display/intel_audio.c

527

if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_audio.c

529

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_audio.c

556

intel_de_write(display, AUD_CONFIG_BE, val);

drivers/gpu/drm/i915/display/intel_audio.c

563

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

567

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

575

if (needs_wa_14020863754(display))

drivers/gpu/drm/i915/display/intel_audio.c

576

intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX);

drivers/gpu/drm/i915/display/intel_audio.c

579

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

drivers/gpu/drm/i915/display/intel_audio.c

585

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

drivers/gpu/drm/i915/display/intel_audio.c

596

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

603

static void ibx_audio_regs_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_audio.c

607

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_audio.c

612

} else if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_audio.c

617

} else if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_audio.c

629

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

635

if (drm_WARN_ON(display->drm, port == PORT_A))

drivers/gpu/drm/i915/display/intel_audio.c

638

ibx_audio_regs_init(display, pipe, &regs);

drivers/gpu/drm/i915/display/intel_audio.c

640

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

643

intel_de_rmw(display, regs.aud_config,

drivers/gpu/drm/i915/display/intel_audio.c

652

intel_de_rmw(display, regs.aud_cntrl_st2,

drivers/gpu/drm/i915/display/intel_audio.c

655

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

665

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

671

if (drm_WARN_ON(display->drm, port == PORT_A))

drivers/gpu/drm/i915/display/intel_audio.c

676

ibx_audio_regs_init(display, pipe, &regs);

drivers/gpu/drm/i915/display/intel_audio.c

678

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

681

intel_de_rmw(display, regs.aud_cntrl_st2,

drivers/gpu/drm/i915/display/intel_audio.c

690

intel_de_rmw(display, regs.aud_config,

drivers/gpu/drm/i915/display/intel_audio.c

698

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

705

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

712

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

741

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

742

struct i915_audio_component *acomp = display->audio.component;

drivers/gpu/drm/i915/display/intel_audio.c

752

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

759

if (display->funcs.audio)

drivers/gpu/drm/i915/display/intel_audio.c

760

display->funcs.audio->audio_codec_enable(encoder,

drivers/gpu/drm/i915/display/intel_audio.c

764

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

766

audio_state = &display->audio.state[cpu_transcoder];

drivers/gpu/drm/i915/display/intel_audio.c

772

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

783

intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,

drivers/gpu/drm/i915/display/intel_audio.c

801

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

802

struct i915_audio_component *acomp = display->audio.component;

drivers/gpu/drm/i915/display/intel_audio.c

812

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_audio.c

818

if (display->funcs.audio)

drivers/gpu/drm/i915/display/intel_audio.c

819

display->funcs.audio->audio_codec_disable(encoder,

drivers/gpu/drm/i915/display/intel_audio.c

823

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

825

audio_state = &display->audio.state[cpu_transcoder];

drivers/gpu/drm/i915/display/intel_audio.c

830

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

841

intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false);

drivers/gpu/drm/i915/display/intel_audio.c

847

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

851

mutex_lock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

853

audio_state = &display->audio.state[cpu_transcoder];

drivers/gpu/drm/i915/display/intel_audio.c

858

mutex_unlock(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_audio.c

864

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_audio.c

869

if (display->funcs.audio)

drivers/gpu/drm/i915/display/intel_audio.c

870

display->funcs.audio->audio_codec_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

895

void intel_audio_hooks_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

897

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_audio.c

898

display->funcs.audio = &g4x_audio_funcs;

drivers/gpu/drm/i915/display/intel_audio.c

899

else if (display->platform.valleyview || display->platform.cherryview ||

drivers/gpu/drm/i915/display/intel_audio.c

900

HAS_PCH_CPT(display) || HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/intel_audio.c

901

display->funcs.audio = &ibx_audio_funcs;

drivers/gpu/drm/i915/display/intel_audio.c

902

else if (display->platform.haswell || DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_audio.c

903

display->funcs.audio = &hsw_audio_funcs;

drivers/gpu/drm/i915/display/intel_audio.c

911

void intel_audio_cdclk_change_pre(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

913

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_audio.c

914

intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);

drivers/gpu/drm/i915/display/intel_audio.c

923

void intel_audio_cdclk_change_post(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_audio.c

927

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_audio.c

928

get_aud_ts_cdclk_m_n(display->cdclk.hw.ref,

drivers/gpu/drm/i915/display/intel_audio.c

929

display->cdclk.hw.cdclk, &aud_ts);

drivers/gpu/drm/i915/display/intel_audio.c

931

intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n);

drivers/gpu/drm/i915/display/intel_audio.c

932

intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);

drivers/gpu/drm/i915/display/intel_audio.c

933

drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n",

drivers/gpu/drm/i915/display/intel_audio.c

959

static void glk_force_audio_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_audio.c

967

crtc = intel_first_crtc(display);

drivers/gpu/drm/i915/display/intel_audio.c

972

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_audio.c

973

if (drm_WARN_ON(display->drm, !state))

drivers/gpu/drm/i915/display/intel_audio.c

988

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/intel_audio.c

998

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.h

16

void intel_audio_hooks_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_audio.h

28

void intel_audio_cdclk_change_pre(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_audio.h

29

void intel_audio_cdclk_change_post(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_audio.h

31

void intel_audio_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_audio.h

32

void intel_audio_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_audio.h

33

void intel_audio_deinit(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_backlight.c

100

if (display->params.invert_brightness > 0 ||

drivers/gpu/drm/i915/display/intel_backlight.c

1004

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

101

intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)) {

drivers/gpu/drm/i915/display/intel_backlight.c

1031

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1033

return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq),

drivers/gpu/drm/i915/display/intel_backlight.c

1070

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1079

if (HAS_PCH_LPT_H(display))

drivers/gpu/drm/i915/display/intel_backlight.c

1093

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1095

return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq),

drivers/gpu/drm/i915/display/intel_backlight.c

1109

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

111

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1112

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_backlight.c

1113

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

drivers/gpu/drm/i915/display/intel_backlight.c

1115

clock = KHz(display->cdclk.hw.cdclk);

drivers/gpu/drm/i915/display/intel_backlight.c

1127

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1130

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_backlight.c

1131

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

drivers/gpu/drm/i915/display/intel_backlight.c

1133

clock = KHz(display->cdclk.hw.cdclk);

drivers/gpu/drm/i915/display/intel_backlight.c

114

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n",

drivers/gpu/drm/i915/display/intel_backlight.c

1145

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1148

if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {

drivers/gpu/drm/i915/display/intel_backlight.c

1149

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_backlight.c

1155

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

drivers/gpu/drm/i915/display/intel_backlight.c

1164

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1168

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1173

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1183

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1189

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1196

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1209

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

121

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1213

drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);

drivers/gpu/drm/i915/display/intel_backlight.c

1224

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1235

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

124

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1240

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_backlight.c

1241

alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;

drivers/gpu/drm/i915/display/intel_backlight.c

1243

alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;

drivers/gpu/drm/i915/display/intel_backlight.c

1246

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

1249

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1252

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1264

cpu_mode = panel->backlight.pwm_enabled && HAS_PCH_LPT(display) &&

drivers/gpu/drm/i915/display/intel_backlight.c

1271

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1276

intel_de_write(display, BLC_PWM_PCH_CTL1,

drivers/gpu/drm/i915/display/intel_backlight.c

1279

intel_de_write(display, BLC_PWM_CPU_CTL2,

drivers/gpu/drm/i915/display/intel_backlight.c

1283

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1292

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1296

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

1299

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1310

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1314

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1323

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1327

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1329

if (DISPLAY_VER(display) == 2 || display->platform.i915gm || display->platform.i945gm)

drivers/gpu/drm/i915/display/intel_backlight.c

1332

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_backlight.c

135

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1356

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1365

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1369

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1373

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

138

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1389

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1398

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1402

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_backlight.c

1405

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

1408

ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

141

if (display->params.invert_brightness > 0 ||

drivers/gpu/drm/i915/display/intel_backlight.c

142

(display->params.invert_brightness == 0 &&

drivers/gpu/drm/i915/display/intel_backlight.c

1421

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

143

intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)))

drivers/gpu/drm/i915/display/intel_backlight.c

1431

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1437

pwm_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_backlight.c

1442

val = intel_de_read(display, UTIL_PIN_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1449

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

1461

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1469

static int cnp_num_backlight_controllers(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_backlight.c

1471

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

drivers/gpu/drm/i915/display/intel_backlight.c

1474

if (INTEL_PCH_TYPE(display) >= PCH_DG1)

drivers/gpu/drm/i915/display/intel_backlight.c

1477

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_backlight.c

1483

static bool cnp_backlight_controller_is_valid(struct intel_display *display, int controller)

drivers/gpu/drm/i915/display/intel_backlight.c

1485

if (controller < 0 || controller >= cnp_num_backlight_controllers(display))

drivers/gpu/drm/i915/display/intel_backlight.c

1489

INTEL_PCH_TYPE(display) >= PCH_ICP &&

drivers/gpu/drm/i915/display/intel_backlight.c

1490

INTEL_PCH_TYPE(display) <= PCH_ADP)

drivers/gpu/drm/i915/display/intel_backlight.c

1491

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

drivers/gpu/drm/i915/display/intel_backlight.c

1499

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1508

if (!cnp_backlight_controller_is_valid(display, panel->backlight.controller)) {

drivers/gpu/drm/i915/display/intel_backlight.c

1509

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1516

pwm_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_backlight.c

152

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1521

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

1533

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

154

return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

1544

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1551

panel->backlight.pwm = pwm_get(display->drm->dev,

drivers/gpu/drm/i915/display/intel_backlight.c

1555

panel->backlight.pwm = pwm_get(display->drm->dev,

drivers/gpu/drm/i915/display/intel_backlight.c

1561

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1580

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

159

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1591

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

161

return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

1657

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

166

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1663

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

1667

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

1672

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1677

if (intel_has_quirk(display, QUIRK_BACKLIGHT_PRESENT)) {

drivers/gpu/drm/i915/display/intel_backlight.c

1678

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1682

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

1690

if (drm_WARN_ON(display->drm, !panel->backlight.funcs))

drivers/gpu/drm/i915/display/intel_backlight.c

1694

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

1696

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

1699

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

170

val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

1707

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

171

if (DISPLAY_VER(display) < 4)

drivers/gpu/drm/i915/display/intel_backlight.c

175

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_backlight.c

1818

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

1824

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_backlight.c

1826

} else if (INTEL_PCH_TYPE(display) >= PCH_CNP) {

drivers/gpu/drm/i915/display/intel_backlight.c

1828

} else if (INTEL_PCH_TYPE(display) >= PCH_LPT_H) {

drivers/gpu/drm/i915/display/intel_backlight.c

1829

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_backlight.c

1833

} else if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_backlight.c

1835

} else if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_backlight.c

1841

} else if (DISPLAY_VER(display) == 4) {

drivers/gpu/drm/i915/display/intel_backlight.c

1851

if (!intel_has_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))

drivers/gpu/drm/i915/display/intel_backlight.c

187

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

189

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_backlight.c

192

return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

197

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

200

return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

215

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

218

val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

219

intel_de_write(display, BLC_PWM_PCH_CTL2, val | level);

drivers/gpu/drm/i915/display/intel_backlight.c

225

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

228

tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

229

intel_de_write(display, BLC_PWM_CPU_CTL, tmp | level);

drivers/gpu/drm/i915/display/intel_backlight.c

235

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

239

if (drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0))

drivers/gpu/drm/i915/display/intel_backlight.c

243

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_backlight.c

251

if (DISPLAY_VER(display) == 4) {

drivers/gpu/drm/i915/display/intel_backlight.c

258

tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;

drivers/gpu/drm/i915/display/intel_backlight.c

259

intel_de_write(display, BLC_PWM_CTL, tmp | level);

drivers/gpu/drm/i915/display/intel_backlight.c

265

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

269

tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

270

intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level);

drivers/gpu/drm/i915/display/intel_backlight.c

276

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

279

intel_de_write(display, BXT_BLC_PWM_DUTY(panel->backlight.controller), level);

drivers/gpu/drm/i915/display/intel_backlight.c

294

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

297

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight level = %d\n",

drivers/gpu/drm/i915/display/intel_backlight.c

310

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

323

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

325

drm_WARN_ON(display->drm, panel->backlight.max == 0);

drivers/gpu/drm/i915/display/intel_backlight.c

339

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

345

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

358

tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

360

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] CPU backlight was enabled, disabling\n",

drivers/gpu/drm/i915/display/intel_backlight.c

362

intel_de_write(display, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

365

intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

371

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

375

intel_de_rmw(display, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

377

intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

388

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

392

intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

398

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

403

intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

409

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

414

intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

418

intel_de_rmw(display, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

424

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

429

intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

447

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

459

if (display->drm->switch_power_state == DRM_SWITCH_POWER_CHANGING) {

drivers/gpu/drm/i915/display/intel_backlight.c

460

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Skipping backlight disable on vga switch\n",

drivers/gpu/drm/i915/display/intel_backlight.c

465

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

472

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

479

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

483

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

485

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

489

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

drivers/gpu/drm/i915/display/intel_backlight.c

492

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_backlight.c

493

intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY,

drivers/gpu/drm/i915/display/intel_backlight.c

497

intel_de_rmw(display, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY,

drivers/gpu/drm/i915/display/intel_backlight.c

502

intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

509

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_backlight.c

512

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

drivers/gpu/drm/i915/display/intel_backlight.c

513

intel_de_posting_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

514

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

524

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

529

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

531

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

535

intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

538

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

540

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

544

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

drivers/gpu/drm/i915/display/intel_backlight.c

551

intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

552

intel_de_posting_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

553

intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

559

intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

565

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

drivers/gpu/drm/i915/display/intel_backlight.c

566

intel_de_posting_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

567

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

574

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

578

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

580

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

583

intel_de_write(display, BLC_PWM_CTL, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

593

if (display->platform.pineview && panel->backlight.active_low_pwm)

drivers/gpu/drm/i915/display/intel_backlight.c

596

intel_de_write(display, BLC_PWM_CTL, ctl);

drivers/gpu/drm/i915/display/intel_backlight.c

597

intel_de_posting_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

607

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_backlight.c

608

intel_de_write(display, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

615

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

620

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

622

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

626

intel_de_write(display, BLC_PWM_CTL2, ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

634

intel_de_write(display, BLC_PWM_CTL, ctl);

drivers/gpu/drm/i915/display/intel_backlight.c

641

intel_de_write(display, BLC_PWM_CTL2, ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

642

intel_de_posting_read(display, BLC_PWM_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

643

intel_de_write(display, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

652

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

657

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

659

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

663

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

667

intel_de_write(display, VLV_BLC_PWM_CTL(pipe), ctl);

drivers/gpu/drm/i915/display/intel_backlight.c

675

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);

drivers/gpu/drm/i915/display/intel_backlight.c

676

intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

677

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);

drivers/gpu/drm/i915/display/intel_backlight.c

684

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

691

val = intel_de_read(display, UTIL_PIN_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

693

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

697

intel_de_write(display, UTIL_PIN_CTL, val);

drivers/gpu/drm/i915/display/intel_backlight.c

703

intel_de_write(display, UTIL_PIN_CTL,

drivers/gpu/drm/i915/display/intel_backlight.c

707

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

709

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

713

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

717

intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

726

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);

drivers/gpu/drm/i915/display/intel_backlight.c

727

intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

728

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

736

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

740

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

742

drm_dbg_kms(display->drm, "backlight already enabled\n");

drivers/gpu/drm/i915/display/intel_backlight.c

744

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

748

intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

757

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);

drivers/gpu/drm/i915/display/intel_backlight.c

758

intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

759

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

drivers/gpu/drm/i915/display/intel_backlight.c

801

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

808

drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

810

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

814

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

820

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

824

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

829

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

831

drm_dbg_kms(display->drm, "get backlight PWM = %d\n", val);

drivers/gpu/drm/i915/display/intel_backlight.c

850

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

857

mutex_lock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

859

drm_WARN_ON(display->drm, panel->backlight.max == 0);

drivers/gpu/drm/i915/display/intel_backlight.c

867

mutex_unlock(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_backlight.c

873

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

876

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

drivers/gpu/drm/i915/display/intel_backlight.c

878

drm_dbg_kms(display->drm, "updating intel_backlight, brightness=%d/%d\n",

drivers/gpu/drm/i915/display/intel_backlight.c

899

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_backlight.c

907

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

910

with_intel_display_rpm(display) {

drivers/gpu/drm/i915/display/intel_backlight.c

913

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

drivers/gpu/drm/i915/display/intel_backlight.c

919

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_backlight.c

92

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

932

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_backlight.c

948

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_backlight.c

95

drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);

drivers/gpu/drm/i915/display/intel_backlight.c

97

if (display->params.invert_brightness < 0)

drivers/gpu/drm/i915/display/intel_backlight.c

986

display->drm->primary->index,

drivers/gpu/drm/i915/display/intel_backlight.c

995

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1007

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1015

parse_lfp_backlight(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1023

backlight_data = bdb_find_section(display, BDB_LFP_BACKLIGHT);

drivers/gpu/drm/i915/display/intel_bios.c

1028

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1038

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1046

if (display->vbt.version >= 191) {

drivers/gpu/drm/i915/display/intel_bios.c

1057

if (display->vbt.version >= 234) {

drivers/gpu/drm/i915/display/intel_bios.c

1064

if (display->vbt.version >= 236)

drivers/gpu/drm/i915/display/intel_bios.c

1073

drm_warn(display->drm, "Brightness min level > 255\n");

drivers/gpu/drm/i915/display/intel_bios.c

1085

if (display->vbt.version >= 239)

drivers/gpu/drm/i915/display/intel_bios.c

1091

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1102

parse_sdvo_lvds_data(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1109

index = display->params.vbt_sdvo_panel_type;

drivers/gpu/drm/i915/display/intel_bios.c

1111

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1119

sdvo_lvds_options = bdb_find_section(display, BDB_SDVO_LVDS_OPTIONS);

drivers/gpu/drm/i915/display/intel_bios.c

1126

dtd = bdb_find_section(display, BDB_SDVO_LVDS_DTD);

drivers/gpu/drm/i915/display/intel_bios.c

1137

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1147

fill_detail_timing_data(display, panel_fixed_mode, &dtd->dtd[index]);

drivers/gpu/drm/i915/display/intel_bios.c

1151

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1156

static int intel_bios_ssc_frequency(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1159

switch (DISPLAY_VER(display)) {

drivers/gpu/drm/i915/display/intel_bios.c

1171

parse_general_features(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

1175

general = bdb_find_section(display, BDB_GENERAL_FEATURES);

drivers/gpu/drm/i915/display/intel_bios.c

1179

display->vbt.int_tv_support = general->int_tv_support;

drivers/gpu/drm/i915/display/intel_bios.c

1181

if (display->vbt.version >= 155 &&

drivers/gpu/drm/i915/display/intel_bios.c

1182

(HAS_DDI(display) || display->platform.valleyview))

drivers/gpu/drm/i915/display/intel_bios.c

1183

display->vbt.int_crt_support = general->int_crt_support;

drivers/gpu/drm/i915/display/intel_bios.c

1184

display->vbt.lvds_use_ssc = general->enable_ssc;

drivers/gpu/drm/i915/display/intel_bios.c

1185

display->vbt.lvds_ssc_freq =

drivers/gpu/drm/i915/display/intel_bios.c

1186

intel_bios_ssc_frequency(display, general->ssc_freq);

drivers/gpu/drm/i915/display/intel_bios.c

1187

display->vbt.display_clock_mode = general->display_clock_mode;

drivers/gpu/drm/i915/display/intel_bios.c

1188

display->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;

drivers/gpu/drm/i915/display/intel_bios.c

1189

if (display->vbt.version >= 181) {

drivers/gpu/drm/i915/display/intel_bios.c

1190

display->vbt.orientation = general->rotate_180 ?

drivers/gpu/drm/i915/display/intel_bios.c

1194

display->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;

drivers/gpu/drm/i915/display/intel_bios.c

1197

if (display->vbt.version >= 249 && general->afc_startup_config) {

drivers/gpu/drm/i915/display/intel_bios.c

1198

display->vbt.override_afc_startup = true;

drivers/gpu/drm/i915/display/intel_bios.c

1199

display->vbt.override_afc_startup_val = general->afc_startup_config == 1 ? 0 : 7;

drivers/gpu/drm/i915/display/intel_bios.c

1202

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1204

display->vbt.int_tv_support,

drivers/gpu/drm/i915/display/intel_bios.c

1205

display->vbt.int_crt_support,

drivers/gpu/drm/i915/display/intel_bios.c

1206

display->vbt.lvds_use_ssc,

drivers/gpu/drm/i915/display/intel_bios.c

1207

display->vbt.lvds_ssc_freq,

drivers/gpu/drm/i915/display/intel_bios.c

1208

display->vbt.display_clock_mode,

drivers/gpu/drm/i915/display/intel_bios.c

1209

display->vbt.fdi_rx_polarity_inverted);

drivers/gpu/drm/i915/display/intel_bios.c

1219

parse_sdvo_device_mapping(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

1228

if (!IS_DISPLAY_VER(display, 3, 7)) {

drivers/gpu/drm/i915/display/intel_bios.c

1229

drm_dbg_kms(display->drm, "Skipping SDVO device mapping\n");

drivers/gpu/drm/i915/display/intel_bios.c

1233

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

1248

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1252

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1258

mapping = &display->vbt.sdvo_mappings[child->dvo_port - 1];

drivers/gpu/drm/i915/display/intel_bios.c

1266

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1272

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1279

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1288

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1294

parse_driver_features(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

1298

driver = bdb_find_section(display, BDB_DRIVER_FEATURES);

drivers/gpu/drm/i915/display/intel_bios.c

1302

if (DISPLAY_VER(display) >= 5) {

drivers/gpu/drm/i915/display/intel_bios.c

1309

display->vbt.int_lvds_support = 0;

drivers/gpu/drm/i915/display/intel_bios.c

1322

if (display->vbt.version >= 134 &&

drivers/gpu/drm/i915/display/intel_bios.c

1325

display->vbt.int_lvds_support = 0;

drivers/gpu/drm/i915/display/intel_bios.c

1330

parse_panel_driver_features(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1335

driver = bdb_find_section(display, BDB_DRIVER_FEATURES);

drivers/gpu/drm/i915/display/intel_bios.c

1339

if (display->vbt.version < 228) {

drivers/gpu/drm/i915/display/intel_bios.c

1340

drm_dbg_kms(display->drm, "DRRS State Enabled:%d\n",

drivers/gpu/drm/i915/display/intel_bios.c

1364

parse_power_conservation_features(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1372

if (display->vbt.version < 228)

drivers/gpu/drm/i915/display/intel_bios.c

1375

power = bdb_find_section(display, BDB_LFP_POWER);

drivers/gpu/drm/i915/display/intel_bios.c

1398

if (display->vbt.version >= 232)

drivers/gpu/drm/i915/display/intel_bios.c

1401

if (display->vbt.version >= 233)

drivers/gpu/drm/i915/display/intel_bios.c

1417

parse_edp(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1424

edp = bdb_find_section(display, BDB_EDP);

drivers/gpu/drm/i915/display/intel_bios.c

1446

if (display->vbt.version >= 224) {

drivers/gpu/drm/i915/display/intel_bios.c

1461

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1479

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1499

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

151

bdb_find_section(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1519

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1525

if (display->vbt.version >= 173) {

drivers/gpu/drm/i915/display/intel_bios.c

1529

if (display->params.edp_vswing) {

drivers/gpu/drm/i915/display/intel_bios.c

1531

display->params.edp_vswing == 1;

drivers/gpu/drm/i915/display/intel_bios.c

1541

if (display->vbt.version >= 244)

drivers/gpu/drm/i915/display/intel_bios.c

1545

if (display->vbt.version >= 251)

drivers/gpu/drm/i915/display/intel_bios.c

1551

parse_psr(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1558

psr = bdb_find_section(display, BDB_PSR);

drivers/gpu/drm/i915/display/intel_bios.c

156

list_for_each_entry(entry, &display->vbt.bdb_blocks, node) {

drivers/gpu/drm/i915/display/intel_bios.c

1560

drm_dbg_kms(display->drm, "No PSR BDB found.\n");

drivers/gpu/drm/i915/display/intel_bios.c

1574

if (display->vbt.version >= 205 &&

drivers/gpu/drm/i915/display/intel_bios.c

1575

(DISPLAY_VER(display) >= 9 && !display->platform.broxton)) {

drivers/gpu/drm/i915/display/intel_bios.c

1587

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1607

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1620

if (display->vbt.version >= 226) {

drivers/gpu/drm/i915/display/intel_bios.c

1646

static void parse_dsi_backlight_ports(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1650

enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C;

drivers/gpu/drm/i915/display/intel_bios.c

1652

if (!panel->vbt.dsi.config->dual_link || display->vbt.version < 197) {

drivers/gpu/drm/i915/display/intel_bios.c

1692

parse_mipi_config(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1702

if (!intel_bios_is_dsi_present(display, &port))

drivers/gpu/drm/i915/display/intel_bios.c

1708

start = bdb_find_section(display, BDB_MIPI_CONFIG);

drivers/gpu/drm/i915/display/intel_bios.c

1710

drm_dbg_kms(display->drm, "No MIPI config BDB found");

drivers/gpu/drm/i915/display/intel_bios.c

1714

drm_dbg_kms(display->drm, "Found MIPI Config block, panel index = %d\n",

drivers/gpu/drm/i915/display/intel_bios.c

1735

parse_dsi_backlight_ports(display, panel, port);

drivers/gpu/drm/i915/display/intel_bios.c

1767

find_panel_sequence_block(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1785

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1799

drm_err(display->drm, "Invalid sequence block\n");

drivers/gpu/drm/i915/display/intel_bios.c

1811

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1817

static int goto_next_sequence(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1848

drm_err(display->drm, "Unknown operation byte\n");

drivers/gpu/drm/i915/display/intel_bios.c

1856

static int goto_next_sequence_v3(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1868

drm_err(display->drm, "Too small sequence size\n");

drivers/gpu/drm/i915/display/intel_bios.c

1885

drm_err(display->drm, "Invalid sequence size\n");

drivers/gpu/drm/i915/display/intel_bios.c

1895

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1918

drm_err(display->drm, "Unknown operation byte %u\n",

drivers/gpu/drm/i915/display/intel_bios.c

1931

static int get_init_otp_deassert_fragment_len(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1937

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

1966

static void vlv_fixup_mipi_sequences(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

1984

len = get_init_otp_deassert_fragment_len(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

1988

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2021

static void icl_fixup_mipi_sequences(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

2026

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2034

static void fixup_mipi_sequences(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

2037

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_bios.c

2038

icl_fixup_mipi_sequences(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

2039

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_bios.c

2040

vlv_fixup_mipi_sequences(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

2044

parse_mipi_sequence(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

2058

sequence = bdb_find_section(display, BDB_MIPI_SEQUENCE);

drivers/gpu/drm/i915/display/intel_bios.c

206

static size_t lfp_data_min_size(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2060

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2067

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2073

drm_dbg_kms(display->drm, "Found MIPI sequence block v%u\n",

drivers/gpu/drm/i915/display/intel_bios.c

2076

seq_data = find_panel_sequence_block(display, sequence, panel_type, &seq_size);

drivers/gpu/drm/i915/display/intel_bios.c

2091

drm_err(display->drm, "Unknown sequence %u\n",

drivers/gpu/drm/i915/display/intel_bios.c

2098

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2104

index = goto_next_sequence_v3(display, data, index, seq_size);

drivers/gpu/drm/i915/display/intel_bios.c

2106

index = goto_next_sequence(display, data, index, seq_size);

drivers/gpu/drm/i915/display/intel_bios.c

2108

drm_err(display->drm, "Invalid sequence %u\n",

drivers/gpu/drm/i915/display/intel_bios.c

211

ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);

drivers/gpu/drm/i915/display/intel_bios.c

2118

fixup_mipi_sequences(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

2120

drm_dbg_kms(display->drm, "MIPI related VBT parsing complete\n");

drivers/gpu/drm/i915/display/intel_bios.c

2129

parse_compression_parameters(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2136

if (display->vbt.version < 198)

drivers/gpu/drm/i915/display/intel_bios.c

2139

params = bdb_find_section(display, BDB_COMPRESSION_PARAMETERS);

drivers/gpu/drm/i915/display/intel_bios.c

2143

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2150

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2156

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

2163

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2169

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2181

static u8 translate_iboost(struct intel_display *display, u8 val)

drivers/gpu/drm/i915/display/intel_bios.c

2186

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2243

static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin)

drivers/gpu/drm/i915/display/intel_bios.c

2248

if (INTEL_PCH_TYPE(display) >= PCH_MTL || display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/intel_bios.c

2251

} else if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_bios.c

2254

} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {

drivers/gpu/drm/i915/display/intel_bios.c

2256

} else if (display->platform.rocketlake && INTEL_PCH_TYPE(display) == PCH_TGP) {

drivers/gpu/drm/i915/display/intel_bios.c

2259

} else if (HAS_PCH_TGP(display) && DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_bios.c

2262

} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {

drivers/gpu/drm/i915/display/intel_bios.c

2265

} else if (HAS_PCH_CNP(display)) {

drivers/gpu/drm/i915/display/intel_bios.c

2278

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2336

static enum port dvo_port_to_port(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

2390

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_bios.c

2395

else if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_bios.c

2400

else if (display->platform.dg1 || display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_bios.c

2413

dsi_dvo_port_to_port(struct intel_display *display, u8 dvo_port)

drivers/gpu/drm/i915/display/intel_bios.c

2419

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_bios.c

2430

struct intel_display *display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

2434

port = dvo_port_to_port(display, child->dvo_port);

drivers/gpu/drm/i915/display/intel_bios.c

2435

if (port == PORT_NONE && DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_bios.c

2436

port = dsi_dvo_port_to_port(display, child->dvo_port);

drivers/gpu/drm/i915/display/intel_bios.c

2500

if (!devdata || devdata->display->vbt.version < 216)

drivers/gpu/drm/i915/display/intel_bios.c

2503

if (devdata->display->vbt.version >= 230)

drivers/gpu/drm/i915/display/intel_bios.c

2511

if (!devdata || devdata->display->vbt.version < 244)

drivers/gpu/drm/i915/display/intel_bios.c

2521

if (!devdata || devdata->display->vbt.version < 263)

drivers/gpu/drm/i915/display/intel_bios.c

2533

struct intel_display *display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

2549

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2560

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2571

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2581

struct intel_display *display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

2584

if (port != PORT_A || DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_bios.c

2592

drm_dbg_kms(display->drm, "VBT claims port A supports DVI%s, ignoring\n",

drivers/gpu/drm/i915/display/intel_bios.c

2602

struct intel_display *display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

2612

if (display->platform.broadwell && devdata->child.hdmi_level_shifter_value > 9) {

drivers/gpu/drm/i915/display/intel_bios.c

2613

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2662

return devdata && HAS_LSPCON(devdata->display) && devdata->child.lspcon;

drivers/gpu/drm/i915/display/intel_bios.c

2668

if (!devdata || devdata->display->vbt.version < 158 ||

drivers/gpu/drm/i915/display/intel_bios.c

2669

DISPLAY_VER(devdata->display) >= 14)

drivers/gpu/drm/i915/display/intel_bios.c

2677

if (!devdata || devdata->display->vbt.version < 204)

drivers/gpu/drm/i915/display/intel_bios.c

2699

static bool is_port_valid(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_bios.c

2706

if (port == PORT_F && display->platform.icelake)

drivers/gpu/drm/i915/display/intel_bios.c

2707

return display->platform.icelake_port_f;

drivers/gpu/drm/i915/display/intel_bios.c

2714

struct intel_display *display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

2734

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2743

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2748

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2754

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2761

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2768

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2774

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2780

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2788

drm_WARN(display->drm, child->use_vbt_vswing,

drivers/gpu/drm/i915/display/intel_bios.c

2795

struct intel_display *display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

2802

if (!is_port_valid(display, port)) {

drivers/gpu/drm/i915/display/intel_bios.c

2803

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2814

static bool has_ddi_port_info(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2816

return DISPLAY_VER(display) >= 5 || display->platform.g4x;

drivers/gpu/drm/i915/display/intel_bios.c

2819

static void parse_ddi_ports(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2823

if (!has_ddi_port_info(display))

drivers/gpu/drm/i915/display/intel_bios.c

2826

list_for_each_entry(devdata, &display->vbt.display_devices, node)

drivers/gpu/drm/i915/display/intel_bios.c

2829

list_for_each_entry(devdata, &display->vbt.display_devices, node)

drivers/gpu/drm/i915/display/intel_bios.c

2857

static bool child_device_size_valid(struct intel_display *display, int size)

drivers/gpu/drm/i915/display/intel_bios.c

2861

expected_size = child_device_expected_size(display->vbt.version);

drivers/gpu/drm/i915/display/intel_bios.c

2864

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2866

display->vbt.version, expected_size);

drivers/gpu/drm/i915/display/intel_bios.c

2871

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2873

size, expected_size, display->vbt.version);

drivers/gpu/drm/i915/display/intel_bios.c

2877

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2887

parse_general_definitions(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2896

defs = bdb_find_section(display, BDB_GENERAL_DEFINITIONS);

drivers/gpu/drm/i915/display/intel_bios.c

2898

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2905

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2912

drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);

drivers/gpu/drm/i915/display/intel_bios.c

2913

if (intel_gmbus_is_valid_pin(display, bus_pin))

drivers/gpu/drm/i915/display/intel_bios.c

2914

display->vbt.crt_ddc_pin = bus_pin;

drivers/gpu/drm/i915/display/intel_bios.c

2916

if (!child_device_size_valid(display, defs->child_dev_size))

drivers/gpu/drm/i915/display/intel_bios.c

2927

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2935

devdata->display = display;

drivers/gpu/drm/i915/display/intel_bios.c

2945

list_add_tail(&devdata->node, &display->vbt.display_devices);

drivers/gpu/drm/i915/display/intel_bios.c

2948

if (list_empty(&display->vbt.display_devices))

drivers/gpu/drm/i915/display/intel_bios.c

2949

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

2955

init_vbt_defaults(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2957

display->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;

drivers/gpu/drm/i915/display/intel_bios.c

2960

display->vbt.int_tv_support = 1;

drivers/gpu/drm/i915/display/intel_bios.c

2961

display->vbt.int_crt_support = 1;

drivers/gpu/drm/i915/display/intel_bios.c

2964

display->vbt.int_lvds_support = 1;

drivers/gpu/drm/i915/display/intel_bios.c

2967

display->vbt.lvds_use_ssc = 1;

drivers/gpu/drm/i915/display/intel_bios.c

2972

display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display,

drivers/gpu/drm/i915/display/intel_bios.c

2973

!HAS_PCH_SPLIT(display));

drivers/gpu/drm/i915/display/intel_bios.c

2974

drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n",

drivers/gpu/drm/i915/display/intel_bios.c

2975

display->vbt.lvds_ssc_freq);

drivers/gpu/drm/i915/display/intel_bios.c

2991

init_vbt_missing_defaults(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

2993

unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask;

drivers/gpu/drm/i915/display/intel_bios.c

2996

if (!HAS_DDI(display) && !display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_bios.c

3002

enum phy phy = intel_port_to_phy(display, port);

drivers/gpu/drm/i915/display/intel_bios.c

3008

if (intel_phy_is_tc(display, phy))

drivers/gpu/drm/i915/display/intel_bios.c

3016

devdata->display = display;

drivers/gpu/drm/i915/display/intel_bios.c

3035

list_add_tail(&devdata->node, &display->vbt.display_devices);

drivers/gpu/drm/i915/display/intel_bios.c

3037

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3043

display->vbt.version = 155;

drivers/gpu/drm/i915/display/intel_bios.c

3064

bool intel_bios_is_valid_vbt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3074

drm_dbg_kms(display->drm, "VBT header incomplete\n");

drivers/gpu/drm/i915/display/intel_bios.c

3079

drm_dbg_kms(display->drm, "VBT invalid signature\n");

drivers/gpu/drm/i915/display/intel_bios.c

3084

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3095

drm_dbg_kms(display->drm, "BDB header incomplete\n");

drivers/gpu/drm/i915/display/intel_bios.c

3101

drm_dbg_kms(display->drm, "BDB incomplete\n");

drivers/gpu/drm/i915/display/intel_bios.c

3108

static struct vbt_header *firmware_get_vbt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3113

const char *name = display->params.vbt_firmware;

drivers/gpu/drm/i915/display/intel_bios.c

3119

ret = request_firmware(&fw, name, display->drm->dev);

drivers/gpu/drm/i915/display/intel_bios.c

3121

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3127

if (intel_bios_is_valid_vbt(display, fw->data, fw->size)) {

drivers/gpu/drm/i915/display/intel_bios.c

3130

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3136

drm_dbg_kms(display->drm, "Invalid VBT firmware \"%s\"\n",

drivers/gpu/drm/i915/display/intel_bios.c

3145

static struct vbt_header *oprom_get_vbt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3164

drm_dbg_kms(display->drm, "VBT header incomplete\n");

drivers/gpu/drm/i915/display/intel_bios.c

3172

drm_dbg_kms(display->drm, "VBT incomplete (vbt_size overflows)\n");

drivers/gpu/drm/i915/display/intel_bios.c

3182

if (!intel_bios_is_valid_vbt(display, vbt, vbt_size))

drivers/gpu/drm/i915/display/intel_bios.c

3185

drm_dbg_kms(display->drm, "Found valid VBT in %s\n", type);

drivers/gpu/drm/i915/display/intel_bios.c

3201

static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3206

vbt = firmware_get_vbt(display, sizep);

drivers/gpu/drm/i915/display/intel_bios.c

3209

vbt = intel_opregion_get_vbt(display, sizep);

drivers/gpu/drm/i915/display/intel_bios.c

3215

if (!vbt && display->platform.dgfx)

drivers/gpu/drm/i915/display/intel_bios.c

3216

with_intel_display_rpm(display)

drivers/gpu/drm/i915/display/intel_bios.c

3217

vbt = oprom_get_vbt(display, intel_rom_spi(display->drm), sizep, "SPI flash");

drivers/gpu/drm/i915/display/intel_bios.c

3220

with_intel_display_rpm(display)

drivers/gpu/drm/i915/display/intel_bios.c

3221

vbt = oprom_get_vbt(display, intel_rom_pci(display->drm), sizep, "PCI ROM");

drivers/gpu/drm/i915/display/intel_bios.c

3234

void intel_bios_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

3239

INIT_LIST_HEAD(&display->vbt.display_devices);

drivers/gpu/drm/i915/display/intel_bios.c

3240

INIT_LIST_HEAD(&display->vbt.bdb_blocks);

drivers/gpu/drm/i915/display/intel_bios.c

3242

if (!HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_bios.c

3243

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3248

init_vbt_defaults(display);

drivers/gpu/drm/i915/display/intel_bios.c

3250

vbt = intel_bios_get_vbt(display, NULL);

drivers/gpu/drm/i915/display/intel_bios.c

3256

display->vbt.version = bdb->version;

drivers/gpu/drm/i915/display/intel_bios.c

3258

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3261

display->vbt.version);

drivers/gpu/drm/i915/display/intel_bios.c

3263

init_bdb_blocks(display, bdb);

drivers/gpu/drm/i915/display/intel_bios.c

3266

parse_general_features(display);

drivers/gpu/drm/i915/display/intel_bios.c

3267

parse_general_definitions(display);

drivers/gpu/drm/i915/display/intel_bios.c

3268

parse_driver_features(display);

drivers/gpu/drm/i915/display/intel_bios.c

3271

parse_compression_parameters(display);

drivers/gpu/drm/i915/display/intel_bios.c

3275

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3277

init_vbt_missing_defaults(display);

drivers/gpu/drm/i915/display/intel_bios.c

3281

parse_sdvo_device_mapping(display);

drivers/gpu/drm/i915/display/intel_bios.c

3282

parse_ddi_ports(display);

drivers/gpu/drm/i915/display/intel_bios.c

3287

static void intel_bios_init_panel(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3295

drm_WARN_ON(display->drm, !use_fallback);

drivers/gpu/drm/i915/display/intel_bios.c

3299

panel->vbt.panel_type = get_panel_type(display, devdata,

drivers/gpu/drm/i915/display/intel_bios.c

3302

drm_WARN_ON(display->drm, use_fallback);

drivers/gpu/drm/i915/display/intel_bios.c

3308

parse_panel_options(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3309

parse_generic_dtd(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3310

parse_lfp_data(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3311

parse_lfp_backlight(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3312

parse_sdvo_lvds_data(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3313

parse_panel_driver_features(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3314

parse_power_conservation_features(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3315

parse_edp(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3316

parse_psr(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3317

parse_mipi_config(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3318

parse_mipi_sequence(display, panel);

drivers/gpu/drm/i915/display/intel_bios.c

3321

void intel_bios_init_panel_early(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3325

intel_bios_init_panel(display, panel, devdata, NULL, false);

drivers/gpu/drm/i915/display/intel_bios.c

3328

void intel_bios_init_panel_late(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3333

intel_bios_init_panel(display, panel, devdata, drm_edid, true);

drivers/gpu/drm/i915/display/intel_bios.c

3340

void intel_bios_driver_remove(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

3345

list_for_each_entry_safe(devdata, nd, &display->vbt.display_devices,

drivers/gpu/drm/i915/display/intel_bios.c

3352

list_for_each_entry_safe(entry, ne, &display->vbt.bdb_blocks, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3381

bool intel_bios_is_tv_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

3385

if (!display->vbt.int_tv_support)

drivers/gpu/drm/i915/display/intel_bios.c

3388

if (list_empty(&display->vbt.display_devices))

drivers/gpu/drm/i915/display/intel_bios.c

3391

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3423

bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)

drivers/gpu/drm/i915/display/intel_bios.c

3427

if (list_empty(&display->vbt.display_devices))

drivers/gpu/drm/i915/display/intel_bios.c

3430

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3441

if (intel_gmbus_is_valid_pin(display, child->i2c_pin))

drivers/gpu/drm/i915/display/intel_bios.c

3457

return intel_opregion_vbt_present(display);

drivers/gpu/drm/i915/display/intel_bios.c

3470

bool intel_bios_is_port_present(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_bios.c

3474

if (WARN_ON(!has_ddi_port_info(display)))

drivers/gpu/drm/i915/display/intel_bios.c

3477

if (!is_port_valid(display, port))

drivers/gpu/drm/i915/display/intel_bios.c

3480

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3483

if (dvo_port_to_port(display, child->dvo_port) == port)

drivers/gpu/drm/i915/display/intel_bios.c

3519

bool intel_bios_is_dsi_present(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3524

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3531

if (dsi_dvo_port_to_port(display, dvo_port) == PORT_NONE) {

drivers/gpu/drm/i915/display/intel_bios.c

3532

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3539

*port = dsi_dvo_port_to_port(display, dvo_port);

drivers/gpu/drm/i915/display/intel_bios.c

3550

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_bios.c

3564

drm_dbg_kms(display->drm, "VBT: Unsupported BPC %d for DCS\n",

drivers/gpu/drm/i915/display/intel_bios.c

3585

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3593

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3618

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_bios.c

3621

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3627

if (dsi_dvo_port_to_port(display, child->dvo_port) == encoder->port) {

drivers/gpu/drm/i915/display/intel_bios.c

366

static void *generate_lfp_data_ptrs(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3687

static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel)

drivers/gpu/drm/i915/display/intel_bios.c

3692

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_bios.c

3695

} else if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_bios.c

3698

} else if (display->platform.dg1 || display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_bios.c

3711

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

3723

return map_aux_ch(devdata->display, devdata->child.aux_channel);

drivers/gpu/drm/i915/display/intel_bios.c

3728

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_bios.c

3735

display = devdata->display;

drivers/gpu/drm/i915/display/intel_bios.c

3738

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3749

if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)

drivers/gpu/drm/i915/display/intel_bios.c

3752

return translate_iboost(devdata->display, devdata->child.dp_iboost_level);

drivers/gpu/drm/i915/display/intel_bios.c

3757

if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)

drivers/gpu/drm/i915/display/intel_bios.c

3760

return translate_iboost(devdata->display, devdata->child.hdmi_iboost_level);

drivers/gpu/drm/i915/display/intel_bios.c

3768

return map_ddc_pin(devdata->display, devdata->child.ddc_pin);

drivers/gpu/drm/i915/display/intel_bios.c

3773

return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;

drivers/gpu/drm/i915/display/intel_bios.c

3778

return devdata->display->vbt.version >= 209 && devdata->child.tbt;

drivers/gpu/drm/i915/display/intel_bios.c

3783

return devdata->display->vbt.version >= 264 &&

drivers/gpu/drm/i915/display/intel_bios.c

3789

return devdata->display->vbt.version >= 264 &&

drivers/gpu/drm/i915/display/intel_bios.c

380

if (display->vbt.version < 155)

drivers/gpu/drm/i915/display/intel_bios.c

3804

intel_bios_encoder_data_lookup(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_bios.c

3808

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

drivers/gpu/drm/i915/display/intel_bios.c

3816

void intel_bios_for_each_encoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3817

void (*func)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

3822

list_for_each_entry(devdata, &display->vbt.display_devices, node)

drivers/gpu/drm/i915/display/intel_bios.c

3823

func(display, devdata);

drivers/gpu/drm/i915/display/intel_bios.c

3828

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_bios.c

3832

vbt = intel_bios_get_vbt(display, &vbt_size);

drivers/gpu/drm/i915/display/intel_bios.c

3844

void intel_bios_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bios.c

3846

debugfs_create_file("i915_vbt", 0444, display->drm->debugfs_root,

drivers/gpu/drm/i915/display/intel_bios.c

3847

display, &intel_bios_vbt_fops);

drivers/gpu/drm/i915/display/intel_bios.c

389

drm_dbg_kms(display->drm, "Generating LFP data table pointers\n");

drivers/gpu/drm/i915/display/intel_bios.c

457

init_bdb_block(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

470

temp_block = generate_lfp_data_ptrs(display, bdb);

drivers/gpu/drm/i915/display/intel_bios.c

477

drm_WARN(display->drm, min_size == 0,

drivers/gpu/drm/i915/display/intel_bios.c

500

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

506

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

512

list_add_tail(&entry->node, &display->vbt.bdb_blocks);

drivers/gpu/drm/i915/display/intel_bios.c

515

static void init_bdb_blocks(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

525

min_size = lfp_data_min_size(display);

drivers/gpu/drm/i915/display/intel_bios.c

527

init_bdb_block(display, bdb, section_id, min_size);

drivers/gpu/drm/i915/display/intel_bios.c

532

fill_detail_timing_data(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

575

drm_dbg_kms(display->drm, "reducing hsync_end %d->%d\n",

drivers/gpu/drm/i915/display/intel_bios.c

580

drm_dbg_kms(display->drm, "reducing vsync_end %d->%d\n",

drivers/gpu/drm/i915/display/intel_bios.c

625

static int opregion_get_panel_type(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

629

return intel_opregion_get_panel_type(display);

drivers/gpu/drm/i915/display/intel_bios.c

632

static int vbt_get_panel_type(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

638

lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);

drivers/gpu/drm/i915/display/intel_bios.c

644

drm_dbg_kms(display->drm, "Invalid VBT panel type 0x%x\n",

drivers/gpu/drm/i915/display/intel_bios.c

652

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

658

static int pnpid_get_panel_type(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

677

p = drm_dbg_printer(display->drm, DRM_UT_KMS, "EDID");

drivers/gpu/drm/i915/display/intel_bios.c

680

ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);

drivers/gpu/drm/i915/display/intel_bios.c

684

data = bdb_find_section(display, BDB_LFP_DATA);

drivers/gpu/drm/i915/display/intel_bios.c

708

static int fallback_get_panel_type(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

72

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_bios.c

722

static int get_panel_type(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

728

int (*get_panel_type)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

753

panel_types[i].panel_type = panel_types[i].get_panel_type(display, devdata,

drivers/gpu/drm/i915/display/intel_bios.c

756

drm_WARN_ON(display->drm, panel_types[i].panel_type > 0xf &&

drivers/gpu/drm/i915/display/intel_bios.c

760

drm_dbg_kms(display->drm, "Panel type (%s): %d\n",

drivers/gpu/drm/i915/display/intel_bios.c

775

drm_dbg_kms(display->drm, "Selected panel type (%s): %d\n",

drivers/gpu/drm/i915/display/intel_bios.c

793

parse_panel_options(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

800

lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);

drivers/gpu/drm/i915/display/intel_bios.c

824

drm_dbg_kms(display->drm, "DRRS supported mode is static\n");

drivers/gpu/drm/i915/display/intel_bios.c

828

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

833

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

840

parse_lfp_panel_dtd(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

858

fill_detail_timing_data(display, panel_fixed_mode, panel_dvo_timing);

drivers/gpu/drm/i915/display/intel_bios.c

862

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

874

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

881

parse_lfp_data(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

891

ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);

drivers/gpu/drm/i915/display/intel_bios.c

895

data = bdb_find_section(display, BDB_LFP_DATA);

drivers/gpu/drm/i915/display/intel_bios.c

900

parse_lfp_panel_dtd(display, panel, data, ptrs);

drivers/gpu/drm/i915/display/intel_bios.c

904

p = drm_dbg_printer(display->drm, DRM_UT_KMS, "Panel");

drivers/gpu/drm/i915/display/intel_bios.c

911

drm_dbg_kms(display->drm, "Panel name: %.*s\n",

drivers/gpu/drm/i915/display/intel_bios.c

915

if (display->vbt.version >= 188) {

drivers/gpu/drm/i915/display/intel_bios.c

918

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bios.c

925

parse_generic_dtd(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.c

941

if (display->vbt.version < 229)

drivers/gpu/drm/i915/display/intel_bios.c

944

generic_dtd = bdb_find_section(display, BDB_GENERIC_DTD);

drivers/gpu/drm/i915/display/intel_bios.c

949

drm_err(display->drm, "GDTD size %u is too small.\n",

drivers/gpu/drm/i915/display/intel_bios.c

954

drm_err(display->drm, "Unexpected GDTD size %u\n",

drivers/gpu/drm/i915/display/intel_bios.c

962

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bios.h

102

void intel_bios_for_each_encoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.h

103

void (*func)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.h

106

void intel_bios_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bios.h

53

void intel_bios_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bios.h

54

void intel_bios_init_panel_early(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.h

57

void intel_bios_init_panel_late(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.h

62

void intel_bios_driver_remove(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bios.h

63

bool intel_bios_is_valid_vbt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bios.h

65

bool intel_bios_is_tv_present(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bios.h

66

bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);

drivers/gpu/drm/i915/display/intel_bios.h

67

bool intel_bios_is_port_present(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_bios.h

68

bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port);

drivers/gpu/drm/i915/display/intel_bios.h

74

intel_bios_encoder_data_lookup(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_bw.c

1001

drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",

drivers/gpu/drm/i915/display/intel_bw.c

1010

icl_pcode_restrict_qgv_points(display, new_mask);

drivers/gpu/drm/i915/display/intel_bw.c

1015

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

1033

drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",

drivers/gpu/drm/i915/display/intel_bw.c

1042

icl_pcode_restrict_qgv_points(display, new_mask);

drivers/gpu/drm/i915/display/intel_bw.c

1045

static int mtl_find_qgv_points(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

1051

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

drivers/gpu/drm/i915/display/intel_bw.c

1065

if (!intel_bw_can_enable_sagv(display, new_bw_state)) {

drivers/gpu/drm/i915/display/intel_bw.c

1067

drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");

drivers/gpu/drm/i915/display/intel_bw.c

1077

tgl_max_bw_index(display, num_active_planes, i);

drivers/gpu/drm/i915/display/intel_bw.c

1080

if (bw_index >= ARRAY_SIZE(display->bw.max))

drivers/gpu/drm/i915/display/intel_bw.c

1083

max_data_rate = display->bw.max[bw_index].deratedbw[i];

drivers/gpu/drm/i915/display/intel_bw.c

109

static int icl_pcode_read_qgv_point_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

1090

qgv_peak_bw = display->bw.max[bw_index].peakbw[i];

drivers/gpu/drm/i915/display/intel_bw.c

1093

drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",

drivers/gpu/drm/i915/display/intel_bw.c

1097

drm_dbg_kms(display->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",

drivers/gpu/drm/i915/display/intel_bw.c

1105

drm_dbg_kms(display->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",

drivers/gpu/drm/i915/display/intel_bw.c

1116

static int icl_find_qgv_points(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

1122

unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

drivers/gpu/drm/i915/display/intel_bw.c

1123

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

drivers/gpu/drm/i915/display/intel_bw.c

1134

unsigned int max_data_rate = icl_qgv_bw(display,

drivers/gpu/drm/i915/display/intel_bw.c

1139

drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d\n",

drivers/gpu/drm/i915/display/intel_bw.c

1144

unsigned int max_data_rate = adl_psf_bw(display, i);

drivers/gpu/drm/i915/display/intel_bw.c

1149

drm_dbg_kms(display->drm, "PSF GV point %d: max bw %d"

drivers/gpu/drm/i915/display/intel_bw.c

1160

drm_dbg_kms(display->drm, "No QGV points provide sufficient memory"

drivers/gpu/drm/i915/display/intel_bw.c

1167

drm_dbg_kms(display->drm, "No PSF GV points provide sufficient memory"

drivers/gpu/drm/i915/display/intel_bw.c

117

ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

drivers/gpu/drm/i915/display/intel_bw.c

1178

if (!intel_bw_can_enable_sagv(display, new_bw_state)) {

drivers/gpu/drm/i915/display/intel_bw.c

1179

qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);

drivers/gpu/drm/i915/display/intel_bw.c

1180

drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",

drivers/gpu/drm/i915/display/intel_bw.c

1188

new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display,

drivers/gpu/drm/i915/display/intel_bw.c

1204

static int intel_bw_check_qgv_points(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

1208

unsigned int data_rate = intel_bw_data_rate(display, new_bw_state);

drivers/gpu/drm/i915/display/intel_bw.c

1210

intel_bw_num_active_planes(display, new_bw_state);

drivers/gpu/drm/i915/display/intel_bw.c

1214

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_bw.c

1215

return mtl_find_qgv_points(display, data_rate, num_active_planes,

drivers/gpu/drm/i915/display/intel_bw.c

1218

return icl_find_qgv_points(display, data_rate, num_active_planes,

drivers/gpu/drm/i915/display/intel_bw.c

1224

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

124

sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0),

drivers/gpu/drm/i915/display/intel_bw.c

1258

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

1295

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

1324

if (intel_bw_can_enable_sagv(display, new_bw_state) !=

drivers/gpu/drm/i915/display/intel_bw.c

1325

intel_bw_can_enable_sagv(display, old_bw_state)) {

drivers/gpu/drm/i915/display/intel_bw.c

1340

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

1346

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_bw.c

1358

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_bw.c

1369

intel_bw_can_enable_sagv(display, old_bw_state) !=

drivers/gpu/drm/i915/display/intel_bw.c

137

static int adls_pcode_read_psf_gv_point_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

1370

intel_bw_can_enable_sagv(display, new_bw_state))

drivers/gpu/drm/i915/display/intel_bw.c

1380

ret = intel_bw_check_qgv_points(display, old_bw_state, new_bw_state);

drivers/gpu/drm/i915/display/intel_bw.c

1390

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_bw.c

1398

drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n",

drivers/gpu/drm/i915/display/intel_bw.c

1404

void intel_bw_update_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bw.c

1407

to_intel_bw_state(display->bw.obj.state);

drivers/gpu/drm/i915/display/intel_bw.c

1410

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_bw.c

1416

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_bw.c

1424

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_bw.c

1434

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_bw.c

1436

to_intel_bw_state(display->bw.obj.state);

drivers/gpu/drm/i915/display/intel_bw.c

1439

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_bw.c

144

ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

drivers/gpu/drm/i915/display/intel_bw.c

1469

int intel_bw_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bw.c

1477

intel_atomic_global_obj_init(display, &display->bw.obj,

drivers/gpu/drm/i915/display/intel_bw.c

1484

if (intel_has_sagv(display) && IS_DISPLAY_VER(display, 11, 13))

drivers/gpu/drm/i915/display/intel_bw.c

1485

icl_force_disable_sagv(display, state);

drivers/gpu/drm/i915/display/intel_bw.c

1504

bool intel_bw_can_enable_sagv(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

1507

if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/intel_bw.c

157

static u16 icl_qgv_points_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bw.c

159

unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

drivers/gpu/drm/i915/display/intel_bw.c

160

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

drivers/gpu/drm/i915/display/intel_bw.c

177

static bool is_sagv_enabled(struct intel_display *display, u16 points_mask)

drivers/gpu/drm/i915/display/intel_bw.c

179

return !is_power_of_2(~points_mask & icl_qgv_points_mask(display) &

drivers/gpu/drm/i915/display/intel_bw.c

183

static int icl_pcode_restrict_qgv_points(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

188

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_bw.c

192

ret = intel_pcode_request(display->drm, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,

drivers/gpu/drm/i915/display/intel_bw.c

199

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

205

display->sagv.status = is_sagv_enabled(display, points_mask) ?

drivers/gpu/drm/i915/display/intel_bw.c

211

static int mtl_read_qgv_point_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

214

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_bw.c

234

intel_read_qgv_point_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

238

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_bw.c

239

return mtl_read_qgv_point_info(display, sp, point);

drivers/gpu/drm/i915/display/intel_bw.c

240

else if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_bw.c

241

return dg1_mchbar_read_qgv_point_info(display, sp, point);

drivers/gpu/drm/i915/display/intel_bw.c

243

return icl_pcode_read_qgv_point_info(display, sp, point);

drivers/gpu/drm/i915/display/intel_bw.c

246

static int icl_get_qgv_points(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

256

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_bw.c

285

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_bw.c

300

if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_bw.c

319

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/intel_bw.c

324

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

331

ret = intel_read_qgv_point_info(display, sp, i);

drivers/gpu/drm/i915/display/intel_bw.c

333

drm_dbg_kms(display->drm, "Could not read QGV %d info\n", i);

drivers/gpu/drm/i915/display/intel_bw.c

337

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

344

ret = adls_pcode_read_psf_gv_point_info(display, qi->psf_points);

drivers/gpu/drm/i915/display/intel_bw.c

346

drm_err(display->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");

drivers/gpu/drm/i915/display/intel_bw.c

351

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

453

static int icl_get_bw_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

463

int num_groups = ARRAY_SIZE(display->bw.max);

drivers/gpu/drm/i915/display/intel_bw.c

466

ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);

drivers/gpu/drm/i915/display/intel_bw.c

468

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

479

struct intel_bw_info *bi = &display->bw.max[i];

drivers/gpu/drm/i915/display/intel_bw.c

506

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

517

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/intel_bw.c

519

display->sagv.status = I915_SAGV_ENABLED;

drivers/gpu/drm/i915/display/intel_bw.c

524

static int tgl_get_bw_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

535

int num_groups = ARRAY_SIZE(display->bw.max);

drivers/gpu/drm/i915/display/intel_bw.c

538

ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);

drivers/gpu/drm/i915/display/intel_bw.c

540

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

545

if (DISPLAY_VER(display) < 14 &&

drivers/gpu/drm/i915/display/intel_bw.c

551

if (num_channels < qi.max_numchannels && DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_bw.c

554

if (DISPLAY_VER(display) >= 12 && num_channels > qi.max_numchannels)

drivers/gpu/drm/i915/display/intel_bw.c

555

drm_warn(display->drm, "Number of channels exceeds max number of channels.");

drivers/gpu/drm/i915/display/intel_bw.c

572

struct intel_bw_info *bi = &display->bw.max[i];

drivers/gpu/drm/i915/display/intel_bw.c

580

bi_next = &display->bw.max[i + 1];

drivers/gpu/drm/i915/display/intel_bw.c

612

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

623

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

635

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/intel_bw.c

637

display->sagv.status = I915_SAGV_ENABLED;

drivers/gpu/drm/i915/display/intel_bw.c

642

static void dg2_get_bw_info(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bw.c

644

unsigned int deratedbw = display->platform.dg2_g11 ? 38000 : 50000;

drivers/gpu/drm/i915/display/intel_bw.c

645

int num_groups = ARRAY_SIZE(display->bw.max);

drivers/gpu/drm/i915/display/intel_bw.c

656

struct intel_bw_info *bi = &display->bw.max[i];

drivers/gpu/drm/i915/display/intel_bw.c

664

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/intel_bw.c

667

static int xe2_hpd_get_bw_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

676

ret = icl_get_qgv_points(display, dram_info, &qi, true);

drivers/gpu/drm/i915/display/intel_bw.c

678

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_bw.c

690

display->bw.max[0].deratedbw[i] =

drivers/gpu/drm/i915/display/intel_bw.c

692

display->bw.max[0].peakbw[i] = bw;

drivers/gpu/drm/i915/display/intel_bw.c

694

drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",

drivers/gpu/drm/i915/display/intel_bw.c

695

i, display->bw.max[0].deratedbw[i],

drivers/gpu/drm/i915/display/intel_bw.c

696

display->bw.max[0].peakbw[i]);

drivers/gpu/drm/i915/display/intel_bw.c

700

display->bw.max[0].num_planes = 1;

drivers/gpu/drm/i915/display/intel_bw.c

701

display->bw.max[0].num_qgv_points = qi.num_points;

drivers/gpu/drm/i915/display/intel_bw.c

702

for (i = 1; i < ARRAY_SIZE(display->bw.max); i++)

drivers/gpu/drm/i915/display/intel_bw.c

703

memcpy(&display->bw.max[i], &display->bw.max[0],

drivers/gpu/drm/i915/display/intel_bw.c

704

sizeof(display->bw.max[0]));

drivers/gpu/drm/i915/display/intel_bw.c

710

drm_WARN_ON(display->drm, qi.num_points != 2);

drivers/gpu/drm/i915/display/intel_bw.c

711

display->sagv.status = I915_SAGV_ENABLED;

drivers/gpu/drm/i915/display/intel_bw.c

716

static unsigned int icl_max_bw_index(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

726

for (i = 0; i < ARRAY_SIZE(display->bw.max); i++) {

drivers/gpu/drm/i915/display/intel_bw.c

728

&display->bw.max[i];

drivers/gpu/drm/i915/display/intel_bw.c

73

static int dg1_mchbar_read_qgv_point_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

744

static unsigned int tgl_max_bw_index(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

754

for (i = ARRAY_SIZE(display->bw.max) - 1; i >= 0; i--) {

drivers/gpu/drm/i915/display/intel_bw.c

756

&display->bw.max[i];

drivers/gpu/drm/i915/display/intel_bw.c

77

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_bw.c

772

static unsigned int adl_psf_bw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

776

&display->bw.max[0];

drivers/gpu/drm/i915/display/intel_bw.c

781

static unsigned int icl_qgv_bw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

786

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_bw.c

787

idx = tgl_max_bw_index(display, num_active_planes, qgv_point);

drivers/gpu/drm/i915/display/intel_bw.c

789

idx = icl_max_bw_index(display, num_active_planes, qgv_point);

drivers/gpu/drm/i915/display/intel_bw.c

791

if (idx >= ARRAY_SIZE(display->bw.max))

drivers/gpu/drm/i915/display/intel_bw.c

794

return display->bw.max[idx].deratedbw[qgv_point];

drivers/gpu/drm/i915/display/intel_bw.c

797

void intel_bw_init_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bw.c

799

const struct dram_info *dram_info = intel_dram_info(display);

drivers/gpu/drm/i915/display/intel_bw.c

801

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_bw.c

810

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/intel_bw.c

811

drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);

drivers/gpu/drm/i915/display/intel_bw.c

813

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_bw.c

814

if (DISPLAY_VERx100(display) == 3002)

drivers/gpu/drm/i915/display/intel_bw.c

815

tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

817

tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

818

} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {

drivers/gpu/drm/i915/display/intel_bw.c

820

xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

822

xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

823

} else if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_bw.c

824

tgl_get_bw_info(display, dram_info, &mtl_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

825

} else if (display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_bw.c

826

dg2_get_bw_info(display);

drivers/gpu/drm/i915/display/intel_bw.c

827

} else if (display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/intel_bw.c

828

tgl_get_bw_info(display, dram_info, &adlp_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

829

} else if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_bw.c

830

tgl_get_bw_info(display, dram_info, &adls_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

831

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_bw.c

832

tgl_get_bw_info(display, dram_info, &rkl_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

833

} else if (DISPLAY_VER(display) == 12) {

drivers/gpu/drm/i915/display/intel_bw.c

834

tgl_get_bw_info(display, dram_info, &tgl_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

835

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/intel_bw.c

836

icl_get_bw_info(display, dram_info, &icl_sa_info);

drivers/gpu/drm/i915/display/intel_bw.c

840

static unsigned int intel_bw_num_active_planes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

846

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_bw.c

852

static unsigned int intel_bw_data_rate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

858

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_bw.c

861

if (DISPLAY_VER(display) >= 13 && intel_display_vtd_active(display))

drivers/gpu/drm/i915/display/intel_bw.c

875

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

878

bw_state = intel_atomic_get_old_global_obj_state(state, &display->bw.obj);

drivers/gpu/drm/i915/display/intel_bw.c

886

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

889

bw_state = intel_atomic_get_new_global_obj_state(state, &display->bw.obj);

drivers/gpu/drm/i915/display/intel_bw.c

897

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.c

900

bw_state = intel_atomic_get_global_obj_state(state, &display->bw.obj);

drivers/gpu/drm/i915/display/intel_bw.c

907

static unsigned int icl_max_bw_qgv_point_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

910

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

drivers/gpu/drm/i915/display/intel_bw.c

917

icl_qgv_bw(display, num_active_planes, i);

drivers/gpu/drm/i915/display/intel_bw.c

936

static u16 icl_prepare_qgv_points_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

941

ADLS_PCODE_REQ_PSF_PT(psf_points)) & icl_qgv_points_mask(display);

drivers/gpu/drm/i915/display/intel_bw.c

944

static unsigned int icl_max_bw_psf_gv_point_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_bw.c

946

unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

drivers/gpu/drm/i915/display/intel_bw.c

952

unsigned int max_data_rate = adl_psf_bw(display, i);

drivers/gpu/drm/i915/display/intel_bw.c

965

static void icl_force_disable_sagv(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_bw.c

968

unsigned int qgv_points = icl_max_bw_qgv_point_mask(display, 0);

drivers/gpu/drm/i915/display/intel_bw.c

969

unsigned int psf_points = icl_max_bw_psf_gv_point_mask(display);

drivers/gpu/drm/i915/display/intel_bw.c

971

bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display,

drivers/gpu/drm/i915/display/intel_bw.c

975

drm_dbg_kms(display->drm, "Forcing SAGV disable: mask 0x%x\n",

drivers/gpu/drm/i915/display/intel_bw.c

978

icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask);

drivers/gpu/drm/i915/display/intel_bw.c

983

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_bw.h

29

void intel_bw_init_hw(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bw.h

30

int intel_bw_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bw.h

32

void intel_bw_update_hw_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_bw.h

36

bool intel_bw_can_enable_sagv(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_casf.c

108

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

110

if (!HAS_CASF(display))

drivers/gpu/drm/i915/display/intel_casf.c

141

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

145

sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));

drivers/gpu/drm/i915/display/intel_casf.c

147

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_casf.c

192

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

198

drm_WARN(display->drm, 0, "Second scaler not enabled\n");

drivers/gpu/drm/i915/display/intel_casf.c

202

intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),

drivers/gpu/drm/i915/display/intel_casf.c

215

intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0),

drivers/gpu/drm/i915/display/intel_casf.c

264

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

276

intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl);

drivers/gpu/drm/i915/display/intel_casf.c

283

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

286

intel_de_write(display, SKL_PS_CTRL(crtc->pipe, 1), 0);

drivers/gpu/drm/i915/display/intel_casf.c

287

intel_de_write(display, SKL_PS_WIN_POS(crtc->pipe, 1), 0);

drivers/gpu/drm/i915/display/intel_casf.c

288

intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_casf.c

289

intel_de_write(display, SKL_PS_WIN_SZ(crtc->pipe, 1), 0);

drivers/gpu/drm/i915/display/intel_casf.c

68

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

71

intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),

drivers/gpu/drm/i915/display/intel_casf.c

75

intel_de_write(display, SHRPLUT_DATA(crtc->pipe),

drivers/gpu/drm/i915/display/intel_casf.c

81

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

85

intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,

drivers/gpu/drm/i915/display/intel_casf.c

88

win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));

drivers/gpu/drm/i915/display/intel_casf.c

90

intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);

drivers/gpu/drm/i915/display/intel_cdclk.c

1006

static void skl_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1011

skl_dpll0_update(display, cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.c

1018

cdctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1073

static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1075

bool changed = display->cdclk.skl_preferred_vco_freq != vco;

drivers/gpu/drm/i915/display/intel_cdclk.c

1077

display->cdclk.skl_preferred_vco_freq = vco;

drivers/gpu/drm/i915/display/intel_cdclk.c

1080

intel_update_max_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

1083

static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1085

drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);

drivers/gpu/drm/i915/display/intel_cdclk.c

1102

static void skl_dpll0_enable(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1104

intel_de_rmw(display, DPLL_CTRL1,

drivers/gpu/drm/i915/display/intel_cdclk.c

1109

skl_dpll0_link_rate(display, vco));

drivers/gpu/drm/i915/display/intel_cdclk.c

1110

intel_de_posting_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_cdclk.c

1112

intel_de_rmw(display, LCPLL1_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

1115

if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))

drivers/gpu/drm/i915/display/intel_cdclk.c

1116

drm_err(display->drm, "DPLL0 not locked\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1118

display->cdclk.hw.vco = vco;

drivers/gpu/drm/i915/display/intel_cdclk.c

1121

skl_set_preferred_cdclk_vco(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

1124

static void skl_dpll0_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

1126

intel_de_rmw(display, LCPLL1_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

1129

if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))

drivers/gpu/drm/i915/display/intel_cdclk.c

1130

drm_err(display->drm, "Couldn't disable DPLL0\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1132

display->cdclk.hw.vco = 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

1135

static u32 skl_cdclk_freq_sel(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1140

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

1141

cdclk != display->cdclk.hw.bypass);

drivers/gpu/drm/i915/display/intel_cdclk.c

1142

drm_WARN_ON(display->drm, vco != 0);

drivers/gpu/drm/i915/display/intel_cdclk.c

1158

static void skl_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1175

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

1176

display->platform.skylake && vco == 8640000);

drivers/gpu/drm/i915/display/intel_cdclk.c

1178

ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

1183

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

1188

freq_select = skl_cdclk_freq_sel(display, cdclk, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

1190

if (display->cdclk.hw.vco != 0 &&

drivers/gpu/drm/i915/display/intel_cdclk.c

1191

display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1192

skl_dpll0_disable(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

1194

cdclk_ctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1196

if (display->cdclk.hw.vco != vco) {

drivers/gpu/drm/i915/display/intel_cdclk.c

1200

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

drivers/gpu/drm/i915/display/intel_cdclk.c

1205

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

drivers/gpu/drm/i915/display/intel_cdclk.c

1206

intel_de_posting_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1208

if (display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1209

skl_dpll0_enable(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

1213

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

drivers/gpu/drm/i915/display/intel_cdclk.c

1216

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

drivers/gpu/drm/i915/display/intel_cdclk.c

1220

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

drivers/gpu/drm/i915/display/intel_cdclk.c

1221

intel_de_posting_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1224

intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

1227

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

1230

static void skl_sanitize_cdclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

1239

if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)

drivers/gpu/drm/i915/display/intel_cdclk.c

1242

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

1243

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

drivers/gpu/drm/i915/display/intel_cdclk.c

1246

if (display->cdclk.hw.vco == 0 ||

drivers/gpu/drm/i915/display/intel_cdclk.c

1247

display->cdclk.hw.cdclk == display->cdclk.hw.bypass)

drivers/gpu/drm/i915/display/intel_cdclk.c

1256

cdctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1258

skl_cdclk_decimal(display->cdclk.hw.cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

1264

drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1267

display->cdclk.hw.cdclk = 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

1269

display->cdclk.hw.vco = ~0;

drivers/gpu/drm/i915/display/intel_cdclk.c

1272

static void skl_cdclk_init_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

1276

skl_sanitize_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

1278

if (display->cdclk.hw.cdclk != 0 &&

drivers/gpu/drm/i915/display/intel_cdclk.c

1279

display->cdclk.hw.vco != 0) {

drivers/gpu/drm/i915/display/intel_cdclk.c

1284

if (display->cdclk.skl_preferred_vco_freq == 0)

drivers/gpu/drm/i915/display/intel_cdclk.c

1285

skl_set_preferred_cdclk_vco(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1286

display->cdclk.hw.vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

1290

cdclk_config = display->cdclk.hw;

drivers/gpu/drm/i915/display/intel_cdclk.c

1292

cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

1298

skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

1301

static void skl_cdclk_uninit_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

1303

struct intel_cdclk_config cdclk_config = display->cdclk.hw;

drivers/gpu/drm/i915/display/intel_cdclk.c

1309

skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

1585

static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

1587

const struct intel_cdclk_vals *table = display->cdclk.table;

drivers/gpu/drm/i915/display/intel_cdclk.c

1591

if (table[i].refclk == display->cdclk.hw.ref &&

drivers/gpu/drm/i915/display/intel_cdclk.c

1595

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_cdclk.c

1597

min_cdclk, display->cdclk.hw.ref);

drivers/gpu/drm/i915/display/intel_cdclk.c

1598

return display->cdclk.max_cdclk_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

1601

static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

1603

const struct intel_cdclk_vals *table = display->cdclk.table;

drivers/gpu/drm/i915/display/intel_cdclk.c

1606

if (cdclk == display->cdclk.hw.bypass)

drivers/gpu/drm/i915/display/intel_cdclk.c

161

void (*get_cdclk)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1610

if (table[i].refclk == display->cdclk.hw.ref &&

drivers/gpu/drm/i915/display/intel_cdclk.c

1612

return display->cdclk.hw.ref * table[i].ratio;

drivers/gpu/drm/i915/display/intel_cdclk.c

1614

drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",

drivers/gpu/drm/i915/display/intel_cdclk.c

1615

cdclk, display->cdclk.hw.ref);

drivers/gpu/drm/i915/display/intel_cdclk.c

163

void (*set_cdclk)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

170

void intel_cdclk_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1707

static void icl_readout_refclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1710

u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

1728

static void bxt_de_pll_readout(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

173

display->funcs.cdclk->get_cdclk(display, cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.c

1733

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_cdclk.c

1735

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_cdclk.c

1736

icl_readout_refclk(display, cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.c

1740

val = intel_de_read(display, BXT_DE_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_cdclk.c

1755

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_cdclk.c

1758

ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

176

static void intel_cdclk_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1763

static void bxt_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1770

bxt_de_pll_readout(display, cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.c

1772

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_cdclk.c

1774

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_cdclk.c

1784

divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

180

display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

1804

if (HAS_CDCLK_SQUASH(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

1805

squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1821

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_cdclk.c

1822

cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

drivers/gpu/drm/i915/display/intel_cdclk.c

1828

intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

1831

static void bxt_de_pll_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

1833

intel_de_write(display, BXT_DE_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_cdclk.c

1836

if (intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1838

drm_err(display->drm, "timeout waiting for DE PLL unlock\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1840

display->cdclk.hw.vco = 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

1843

static void bxt_de_pll_enable(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1845

int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);

drivers/gpu/drm/i915/display/intel_cdclk.c

1847

intel_de_rmw(display, BXT_DE_PLL_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

185

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

1850

intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_cdclk.c

1853

if (intel_de_wait_for_set_ms(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1855

drm_err(display->drm, "timeout waiting for DE PLL lock\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1857

display->cdclk.hw.vco = vco;

drivers/gpu/drm/i915/display/intel_cdclk.c

1860

static void icl_cdclk_pll_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

187

return display->funcs.cdclk->modeset_calc_cdclk(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

1873

if (intel_display_wa(display, 13012396614))

drivers/gpu/drm/i915/display/intel_cdclk.c

1874

intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK);

drivers/gpu/drm/i915/display/intel_cdclk.c

1876

intel_de_rmw(display, BXT_DE_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_cdclk.c

1880

if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

drivers/gpu/drm/i915/display/intel_cdclk.c

1881

drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1883

display->cdclk.hw.vco = 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

1886

static void icl_cdclk_pll_enable(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1888

int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);

drivers/gpu/drm/i915/display/intel_cdclk.c

1892

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

1895

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

1898

if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

drivers/gpu/drm/i915/display/intel_cdclk.c

1899

drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

190

static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1901

display->cdclk.hw.vco = vco;

drivers/gpu/drm/i915/display/intel_cdclk.c

1904

static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

1906

int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);

drivers/gpu/drm/i915/display/intel_cdclk.c

1911

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

1915

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

1918

if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_cdclk.c

1920

drm_err(display->drm, "timeout waiting for FREQ change request ack\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

1923

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

1925

display->cdclk.hw.vco = vco;

drivers/gpu/drm/i915/display/intel_cdclk.c

1928

static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_cdclk.c

193

return display->funcs.cdclk->calc_voltage_level(cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

1930

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_cdclk.c

1935

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_cdclk.c

1948

static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1956

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

1957

cdclk != display->cdclk.hw.bypass);

drivers/gpu/drm/i915/display/intel_cdclk.c

1958

drm_WARN_ON(display->drm, vco != 0);

drivers/gpu/drm/i915/display/intel_cdclk.c

196

static void fixed_133mhz_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1978

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_cdclk.c

1979

drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1);

drivers/gpu/drm/i915/display/intel_cdclk.c

1984

static u16 cdclk_squash_waveform(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

1987

const struct intel_cdclk_vals *table = display->cdclk.table;

drivers/gpu/drm/i915/display/intel_cdclk.c

1990

if (cdclk == display->cdclk.hw.bypass)

drivers/gpu/drm/i915/display/intel_cdclk.c

1994

if (table[i].refclk == display->cdclk.hw.ref &&

drivers/gpu/drm/i915/display/intel_cdclk.c

1998

drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",

drivers/gpu/drm/i915/display/intel_cdclk.c

1999

cdclk, display->cdclk.hw.ref);

drivers/gpu/drm/i915/display/intel_cdclk.c

2004

static void icl_cdclk_pll_update(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2006

if (display->cdclk.hw.vco != 0 &&

drivers/gpu/drm/i915/display/intel_cdclk.c

2007

display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2008

icl_cdclk_pll_disable(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2010

if (display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2011

icl_cdclk_pll_enable(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

2014

static void bxt_cdclk_pll_update(struct intel_display *display, int vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2016

if (display->cdclk.hw.vco != 0 &&

drivers/gpu/drm/i915/display/intel_cdclk.c

2017

display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2018

bxt_de_pll_disable(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

202

static void fixed_200mhz_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2020

if (display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2021

bxt_de_pll_enable(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

2024

static void dg2_cdclk_squash_program(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2033

intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);

drivers/gpu/drm/i915/display/intel_cdclk.c

2046

static bool mdclk_source_is_cdclk_pll(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2048

return DISPLAY_VER(display) >= 20;

drivers/gpu/drm/i915/display/intel_cdclk.c

2051

static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2053

if (mdclk_source_is_cdclk_pll(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2059

int intel_mdclk_cdclk_ratio(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2062

if (mdclk_source_is_cdclk_pll(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2069

static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2072

intel_dbuf_mdclk_cdclk_ratio_update(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2073

intel_mdclk_cdclk_ratio(display, cdclk_config),

drivers/gpu/drm/i915/display/intel_cdclk.c

2077

static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

208

static void fixed_266mhz_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2090

if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2093

old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2094

new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2111

if (drm_WARN_ON(display->drm, old_div != new_div))

drivers/gpu/drm/i915/display/intel_cdclk.c

214

static void fixed_333mhz_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2140

drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <

drivers/gpu/drm/i915/display/intel_cdclk.c

2142

drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >

drivers/gpu/drm/i915/display/intel_cdclk.c

2143

display->cdclk.max_cdclk_freq);

drivers/gpu/drm/i915/display/intel_cdclk.c

2144

drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=

drivers/gpu/drm/i915/display/intel_cdclk.c

2150

static bool pll_enable_wa_needed(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2152

return (DISPLAY_VERx100(display) == 2000 ||

drivers/gpu/drm/i915/display/intel_cdclk.c

2153

DISPLAY_VERx100(display) == 1400 ||

drivers/gpu/drm/i915/display/intel_cdclk.c

2154

display->platform.dg2) &&

drivers/gpu/drm/i915/display/intel_cdclk.c

2155

display->cdclk.hw.vco > 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

2158

static u32 bxt_cdclk_ctl(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2167

waveform = cdclk_squash_waveform(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2169

val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform);

drivers/gpu/drm/i915/display/intel_cdclk.c

2171

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/intel_cdclk.c

2172

val |= bxt_cdclk_cd2x_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

2178

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/intel_cdclk.c

2182

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2189

if (intel_display_wa(display, 13012396614) && vco == 0)

drivers/gpu/drm/i915/display/intel_cdclk.c

2192

val |= xe2lpd_mdclk_source_sel(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

220

static void fixed_400mhz_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2200

static void _bxt_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2207

if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&

drivers/gpu/drm/i915/display/intel_cdclk.c

2208

!cdclk_pll_is_unknown(display->cdclk.hw.vco)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2209

if (display->cdclk.hw.vco != vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2210

adlp_cdclk_pll_crawl(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

2211

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2213

if (pll_enable_wa_needed(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2214

dg2_cdclk_squash_program(display, 0);

drivers/gpu/drm/i915/display/intel_cdclk.c

2216

icl_cdclk_pll_update(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

2218

bxt_cdclk_pll_update(display, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

2221

if (HAS_CDCLK_SQUASH(display)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2222

u16 waveform = cdclk_squash_waveform(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2224

dg2_cdclk_squash_program(display, waveform);

drivers/gpu/drm/i915/display/intel_cdclk.c

2227

intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));

drivers/gpu/drm/i915/display/intel_cdclk.c

2230

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));

drivers/gpu/drm/i915/display/intel_cdclk.c

2233

static void bxt_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2247

if (DISPLAY_VER(display) >= 14 || display->platform.dg2)

drivers/gpu/drm/i915/display/intel_cdclk.c

2249

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_cdclk.c

2250

ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

2259

ret = intel_pcode_write_timeout(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

226

static void fixed_450mhz_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2264

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

2270

if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

2271

xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.c

2273

if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,

drivers/gpu/drm/i915/display/intel_cdclk.c

2275

_bxt_set_cdclk(display, &mid_cdclk_config, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

2276

_bxt_set_cdclk(display, cdclk_config, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

2278

_bxt_set_cdclk(display, cdclk_config, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

2281

if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

2282

xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.c

2284

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_cdclk.c

2289

else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)

drivers/gpu/drm/i915/display/intel_cdclk.c

2290

ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

2292

if (DISPLAY_VER(display) < 11) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2299

ret = intel_pcode_write_timeout(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

2304

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

2310

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2312

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_cdclk.c

2317

display->cdclk.hw.voltage_level = cdclk_config->voltage_level;

drivers/gpu/drm/i915/display/intel_cdclk.c

232

static void i85x_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2320

static void bxt_sanitize_cdclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2325

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2326

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

drivers/gpu/drm/i915/display/intel_cdclk.c

2328

if (display->cdclk.hw.vco == 0 ||

drivers/gpu/drm/i915/display/intel_cdclk.c

2329

display->cdclk.hw.cdclk == display->cdclk.hw.bypass)

drivers/gpu/drm/i915/display/intel_cdclk.c

2333

cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2334

if (cdclk != display->cdclk.hw.cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

2338

vco = bxt_calc_cdclk_pll_vco(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2339

if (vco != display->cdclk.hw.vco)

drivers/gpu/drm/i915/display/intel_cdclk.c

2347

cdctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

2348

expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

235

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

2355

cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

2356

expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

2363

drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

2366

display->cdclk.hw.cdclk = 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

2369

display->cdclk.hw.vco = ~0;

drivers/gpu/drm/i915/display/intel_cdclk.c

2372

static void bxt_cdclk_init_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2376

bxt_sanitize_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2378

if (display->cdclk.hw.cdclk != 0 &&

drivers/gpu/drm/i915/display/intel_cdclk.c

2379

display->cdclk.hw.vco != 0)

drivers/gpu/drm/i915/display/intel_cdclk.c

2382

cdclk_config = display->cdclk.hw;

drivers/gpu/drm/i915/display/intel_cdclk.c

2389

cdclk_config.cdclk = bxt_calc_cdclk(display, 0);

drivers/gpu/drm/i915/display/intel_cdclk.c

2390

cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2392

intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2394

bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

2397

static void bxt_cdclk_uninit_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2399

struct intel_cdclk_config cdclk_config = display->cdclk.hw;

drivers/gpu/drm/i915/display/intel_cdclk.c

2404

intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2406

bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_cdclk.c

2418

void intel_cdclk_init_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2420

if (DISPLAY_VER(display) >= 10 || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_cdclk.c

2421

bxt_cdclk_init_hw(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2422

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_cdclk.c

2423

skl_cdclk_init_hw(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2433

void intel_cdclk_uninit_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2435

if (DISPLAY_VER(display) >= 10 || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_cdclk.c

2436

bxt_cdclk_uninit_hw(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2437

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_cdclk.c

2438

skl_cdclk_uninit_hw(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2441

static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2448

drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));

drivers/gpu/drm/i915/display/intel_cdclk.c

2453

if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2456

old_waveform = cdclk_squash_waveform(display, a->cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2457

new_waveform = cdclk_squash_waveform(display, b->cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

2463

static bool intel_cdclk_can_crawl(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2469

if (!HAS_CDCLK_CRAWL(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2485

static bool intel_cdclk_can_squash(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2495

if (!HAS_CDCLK_SQUASH(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2532

static bool intel_cdclk_can_cd2x_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2537

if (DISPLAY_VER(display) < 10 && !display->platform.broxton)

drivers/gpu/drm/i915/display/intel_cdclk.c

2546

if (HAS_CDCLK_SQUASH(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

2570

void intel_cdclk_dump_config(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2574

drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",

drivers/gpu/drm/i915/display/intel_cdclk.c

2580

static void intel_pcode_notify(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2590

if (!display->platform.dg2)

drivers/gpu/drm/i915/display/intel_cdclk.c

2601

ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

2607

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

2612

static void intel_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2618

if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))

drivers/gpu/drm/i915/display/intel_cdclk.c

2621

if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))

drivers/gpu/drm/i915/display/intel_cdclk.c

2624

intel_cdclk_dump_config(display, cdclk_config, context);

drivers/gpu/drm/i915/display/intel_cdclk.c

2626

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2632

intel_audio_cdclk_change_pre(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2639

mutex_lock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_cdclk.c

2640

for_each_intel_dp(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2644

&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_cdclk.c

2647

intel_cdclk_set_cdclk(display, cdclk_config, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

2649

for_each_intel_dp(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2654

mutex_unlock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_cdclk.c

2656

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_cdclk.c

2662

intel_audio_cdclk_change_post(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2664

if (drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

2665

intel_cdclk_changed(&display->cdclk.hw, cdclk_config),

drivers/gpu/drm/i915/display/intel_cdclk.c

2667

intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");

drivers/gpu/drm/i915/display/intel_cdclk.c

2668

intel_cdclk_dump_config(display, cdclk_config, "[sw state]");

drivers/gpu/drm/i915/display/intel_cdclk.c

2672

static bool dg2_power_well_count(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2675

return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

2680

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2690

dg2_power_well_count(display, old_cdclk_state) ==

drivers/gpu/drm/i915/display/intel_cdclk.c

2691

dg2_power_well_count(display, new_cdclk_state))

drivers/gpu/drm/i915/display/intel_cdclk.c

2698

update_pipe_count = dg2_power_well_count(display, new_cdclk_state) >

drivers/gpu/drm/i915/display/intel_cdclk.c

2699

dg2_power_well_count(display, old_cdclk_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2717

num_active_pipes = dg2_power_well_count(display, new_cdclk_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2719

intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,

drivers/gpu/drm/i915/display/intel_cdclk.c

2725

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2737

update_pipe_count = dg2_power_well_count(display, new_cdclk_state) <

drivers/gpu/drm/i915/display/intel_cdclk.c

2738

dg2_power_well_count(display, old_cdclk_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

274

static void i915gm_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2754

num_active_pipes = dg2_power_well_count(display, new_cdclk_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2756

intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,

drivers/gpu/drm/i915/display/intel_cdclk.c

277

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

2781

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2796

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_cdclk.c

2821

drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);

drivers/gpu/drm/i915/display/intel_cdclk.c

2823

intel_set_cdclk(display, &cdclk_config, pipe,

drivers/gpu/drm/i915/display/intel_cdclk.c

2837

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2851

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_cdclk.c

2860

drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);

drivers/gpu/drm/i915/display/intel_cdclk.c

2862

intel_set_cdclk(display, &new_cdclk_state->actual, pipe,

drivers/gpu/drm/i915/display/intel_cdclk.c

2867

static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)

drivers/gpu/drm/i915/display/intel_cdclk.c

2869

return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;

drivers/gpu/drm/i915/display/intel_cdclk.c

2873

static int intel_cdclk_guardband(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

2875

if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_cdclk.c

2876

display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_cdclk.c

2878

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_cdclk.c

2886

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2887

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

drivers/gpu/drm/i915/display/intel_cdclk.c

2888

int guardband = intel_cdclk_guardband(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

2901

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_cdclk.c

2905

for_each_intel_plane_on_crtc(display->drm, crtc, plane)

drivers/gpu/drm/i915/display/intel_cdclk.c

2935

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2966

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

298

static void i945gm_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

2980

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

301

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

3013

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3025

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3056

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3063

static bool glk_cdclk_audio_wa_needed(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

3066

return display->platform.geminilake &&

drivers/gpu/drm/i915/display/intel_cdclk.c

3073

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3081

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_cdclk.c

3092

if (glk_cdclk_audio_wa_needed(display, cdclk_state))

drivers/gpu/drm/i915/display/intel_cdclk.c

3095

if (min_cdclk > display->cdclk.max_cdclk_freq) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3096

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3098

min_cdclk, display->cdclk.max_cdclk_freq);

drivers/gpu/drm/i915/display/intel_cdclk.c

3120

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3148

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_cdclk.c

3157

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3166

cdclk = vlv_calc_cdclk(display, min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3170

vlv_calc_voltage_level(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3173

cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3177

vlv_calc_voltage_level(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3216

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

322

static unsigned int intel_hpll_vco(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3225

vco = display->cdclk.skl_preferred_vco_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

3287

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3300

cdclk = bxt_calc_cdclk(display, min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3301

vco = bxt_calc_cdclk_pll_vco(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3307

intel_cdclk_calc_voltage_level(display, cdclk));

drivers/gpu/drm/i915/display/intel_cdclk.c

3310

cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3311

vco = bxt_calc_cdclk_pll_vco(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3316

intel_cdclk_calc_voltage_level(display, cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3368

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3371

cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);

drivers/gpu/drm/i915/display/intel_cdclk.c

3381

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3409

if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) !=

drivers/gpu/drm/i915/display/intel_cdclk.c

3410

glk_cdclk_audio_wa_needed(display, new_cdclk_state))

drivers/gpu/drm/i915/display/intel_cdclk.c

3413

if (dg2_power_well_count(display, old_cdclk_state) !=

drivers/gpu/drm/i915/display/intel_cdclk.c

3414

dg2_power_well_count(display, new_cdclk_state))

drivers/gpu/drm/i915/display/intel_cdclk.c

3462

int intel_cdclk_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3470

intel_atomic_global_obj_init(display, &display->cdclk.obj,

drivers/gpu/drm/i915/display/intel_cdclk.c

3476

static bool intel_cdclk_need_serialize(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

3486

dg2_power_well_count(display, old_cdclk_state) !=

drivers/gpu/drm/i915/display/intel_cdclk.c

3487

dg2_power_well_count(display, new_cdclk_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3492

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3508

if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3526

intel_cdclk_can_cd2x_update(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

3533

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_cdclk.c

3543

if (intel_cdclk_can_crawl_and_squash(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

3546

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3548

} else if (intel_cdclk_can_squash(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

3551

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3553

} else if (intel_cdclk_can_crawl(display,

drivers/gpu/drm/i915/display/intel_cdclk.c

3556

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3561

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3573

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3577

if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=

drivers/gpu/drm/i915/display/intel_cdclk.c

3578

intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3579

int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);

drivers/gpu/drm/i915/display/intel_cdclk.c

3586

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3590

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

3638

void intel_cdclk_update_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3641

to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3643

to_intel_cdclk_state(display->cdclk.obj.state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3649

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_cdclk.c

366

if (display->platform.gm45)

drivers/gpu/drm/i915/display/intel_cdclk.c

3663

cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3668

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_cdclk.c

3670

intel_cdclk_update_hw_state(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

3673

static int intel_compute_max_dotclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3675

int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));

drivers/gpu/drm/i915/display/intel_cdclk.c

3676

int guardband = intel_cdclk_guardband(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

3677

int max_cdclk_freq = display->cdclk.max_cdclk_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

368

else if (display->platform.g45)

drivers/gpu/drm/i915/display/intel_cdclk.c

3690

void intel_update_max_cdclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3692

if (DISPLAY_VER(display) >= 35) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3693

display->cdclk.max_cdclk_freq = 787200;

drivers/gpu/drm/i915/display/intel_cdclk.c

3694

} else if (DISPLAY_VERx100(display) >= 3002) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3695

display->cdclk.max_cdclk_freq = 480000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3696

} else if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3697

display->cdclk.max_cdclk_freq = 691200;

drivers/gpu/drm/i915/display/intel_cdclk.c

3698

} else if (display->platform.jasperlake || display->platform.elkhartlake) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3699

if (display->cdclk.hw.ref == 24000)

drivers/gpu/drm/i915/display/intel_cdclk.c

370

else if (display->platform.i965gm)

drivers/gpu/drm/i915/display/intel_cdclk.c

3700

display->cdclk.max_cdclk_freq = 552000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3702

display->cdclk.max_cdclk_freq = 556800;

drivers/gpu/drm/i915/display/intel_cdclk.c

3703

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3704

if (display->cdclk.hw.ref == 24000)

drivers/gpu/drm/i915/display/intel_cdclk.c

3705

display->cdclk.max_cdclk_freq = 648000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3707

display->cdclk.max_cdclk_freq = 652800;

drivers/gpu/drm/i915/display/intel_cdclk.c

3708

} else if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3709

display->cdclk.max_cdclk_freq = 316800;

drivers/gpu/drm/i915/display/intel_cdclk.c

3710

} else if (display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3711

display->cdclk.max_cdclk_freq = 624000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3712

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3713

u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

3716

vco = display->cdclk.skl_preferred_vco_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

3717

drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);

drivers/gpu/drm/i915/display/intel_cdclk.c

372

else if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_cdclk.c

3733

display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

3734

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_cdclk.c

374

else if (display->platform.g33)

drivers/gpu/drm/i915/display/intel_cdclk.c

3741

if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

drivers/gpu/drm/i915/display/intel_cdclk.c

3742

display->cdclk.max_cdclk_freq = 450000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3743

else if (display->platform.broadwell_ulx)

drivers/gpu/drm/i915/display/intel_cdclk.c

3744

display->cdclk.max_cdclk_freq = 450000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3745

else if (display->platform.broadwell_ult)

drivers/gpu/drm/i915/display/intel_cdclk.c

3746

display->cdclk.max_cdclk_freq = 540000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3748

display->cdclk.max_cdclk_freq = 675000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3749

} else if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3750

display->cdclk.max_cdclk_freq = 320000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3751

} else if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3752

display->cdclk.max_cdclk_freq = 400000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3755

display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;

drivers/gpu/drm/i915/display/intel_cdclk.c

3758

display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

3760

drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",

drivers/gpu/drm/i915/display/intel_cdclk.c

3761

display->cdclk.max_cdclk_freq);

drivers/gpu/drm/i915/display/intel_cdclk.c

3763

drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",

drivers/gpu/drm/i915/display/intel_cdclk.c

3764

display->cdclk.max_dotclk_freq);

drivers/gpu/drm/i915/display/intel_cdclk.c

3773

void intel_update_cdclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3775

intel_cdclk_get_cdclk(display, &display->cdclk.hw);

drivers/gpu/drm/i915/display/intel_cdclk.c

3783

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_cdclk.c

3784

intel_de_write(display, GMBUSFREQ_VLV,

drivers/gpu/drm/i915/display/intel_cdclk.c

3785

DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));

drivers/gpu/drm/i915/display/intel_cdclk.c

3788

static int dg1_rawclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

379

tmp = intel_de_read(display, display->platform.pineview ||

drivers/gpu/drm/i915/display/intel_cdclk.c

3794

intel_de_write(display, PCH_RAWCLK_FREQ,

drivers/gpu/drm/i915/display/intel_cdclk.c

380

display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);

drivers/gpu/drm/i915/display/intel_cdclk.c

3800

static int cnp_rawclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3805

if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3821

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_cdclk.c

3825

intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3829

static int pch_rawclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3831

return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;

drivers/gpu/drm/i915/display/intel_cdclk.c

3834

static int i9xx_hrawclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3837

return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4);

drivers/gpu/drm/i915/display/intel_cdclk.c

384

drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",

drivers/gpu/drm/i915/display/intel_cdclk.c

3847

u32 intel_read_rawclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3851

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

drivers/gpu/drm/i915/display/intel_cdclk.c

3858

else if (INTEL_PCH_TYPE(display) >= PCH_DG1)

drivers/gpu/drm/i915/display/intel_cdclk.c

3859

freq = dg1_rawclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

3860

else if (INTEL_PCH_TYPE(display) >= PCH_CNP)

drivers/gpu/drm/i915/display/intel_cdclk.c

3861

freq = cnp_rawclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

3862

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_cdclk.c

3863

freq = pch_rawclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

3864

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_cdclk.c

3865

freq = vlv_clock_get_hrawclk(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

3866

else if (DISPLAY_VER(display) >= 3)

drivers/gpu/drm/i915/display/intel_cdclk.c

3867

freq = i9xx_hrawclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

387

drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);

drivers/gpu/drm/i915/display/intel_cdclk.c

3877

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_cdclk.c

3879

seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

3880

seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);

drivers/gpu/drm/i915/display/intel_cdclk.c

3881

seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);

drivers/gpu/drm/i915/display/intel_cdclk.c

3888

void intel_cdclk_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

3890

debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,

drivers/gpu/drm/i915/display/intel_cdclk.c

3891

display, &i915_cdclk_info_fops);

drivers/gpu/drm/i915/display/intel_cdclk.c

392

static void g33_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

395

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

404

cdclk_config->vco = intel_hpll_vco(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

4041

void intel_init_cdclk_hooks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

4043

if (DISPLAY_VER(display) >= 35) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4044

display->funcs.cdclk = &xe3lpd_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4045

display->cdclk.table = xe3p_lpd_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4046

} else if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4047

display->funcs.cdclk = &xe3lpd_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4048

display->cdclk.table = xe3lpd_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4049

} else if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4050

display->funcs.cdclk = &rplu_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4051

display->cdclk.table = xe2lpd_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4052

} else if (DISPLAY_VERx100(display) >= 1401) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4053

display->funcs.cdclk = &rplu_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4054

display->cdclk.table = xe2hpd_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4055

} else if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4056

display->funcs.cdclk = &rplu_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4057

display->cdclk.table = mtl_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4058

} else if (display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4059

display->funcs.cdclk = &tgl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4060

display->cdclk.table = dg2_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4061

} else if (display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4063

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4064

display->cdclk.table = adlp_a_step_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4065

display->funcs.cdclk = &tgl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4066

} else if (display->platform.alderlake_p_raptorlake_u) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4067

display->cdclk.table = rplu_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4068

display->funcs.cdclk = &rplu_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4070

display->cdclk.table = adlp_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4071

display->funcs.cdclk = &tgl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4073

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4074

display->funcs.cdclk = &tgl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4075

display->cdclk.table = rkl_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4076

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4077

display->funcs.cdclk = &tgl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4078

display->cdclk.table = icl_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4079

} else if (display->platform.jasperlake || display->platform.elkhartlake) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4080

display->funcs.cdclk = &ehl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4081

display->cdclk.table = icl_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4082

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4083

display->funcs.cdclk = &icl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4084

display->cdclk.table = icl_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4085

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4086

display->funcs.cdclk = &bxt_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4087

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_cdclk.c

4088

display->cdclk.table = glk_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4090

display->cdclk.table = bxt_cdclk_table;

drivers/gpu/drm/i915/display/intel_cdclk.c

4091

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4092

display->funcs.cdclk = &skl_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4093

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4094

display->funcs.cdclk = &bdw_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4095

} else if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4096

display->funcs.cdclk = &hsw_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4097

} else if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4098

display->funcs.cdclk = &chv_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4099

} else if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4100

display->funcs.cdclk = &vlv_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4101

} else if (display->platform.sandybridge || display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4102

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4103

} else if (display->platform.ironlake) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4104

display->funcs.cdclk = &ilk_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4105

} else if (display->platform.gm45) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4106

display->funcs.cdclk = &gm45_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4107

} else if (display->platform.g45) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4108

display->funcs.cdclk = &g33_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4109

} else if (display->platform.i965gm) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4110

display->funcs.cdclk = &i965gm_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4111

} else if (display->platform.i965g) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4112

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4113

} else if (display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4114

display->funcs.cdclk = &pnv_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4115

} else if (display->platform.g33) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4116

display->funcs.cdclk = &g33_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4117

} else if (display->platform.i945gm) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4118

display->funcs.cdclk = &i945gm_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4119

} else if (display->platform.i945g) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4120

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4121

} else if (display->platform.i915gm) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4122

display->funcs.cdclk = &i915gm_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4123

} else if (display->platform.i915g) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4124

display->funcs.cdclk = &i915g_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4125

} else if (display->platform.i865g) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4126

display->funcs.cdclk = &i865g_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4127

} else if (display->platform.i85x) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4128

display->funcs.cdclk = &i85x_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4129

} else if (display->platform.i845g) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4130

display->funcs.cdclk = &i845g_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4131

} else if (display->platform.i830) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4132

display->funcs.cdclk = &i830_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4135

if (drm_WARN(display->drm, !display->funcs.cdclk,

drivers/gpu/drm/i915/display/intel_cdclk.c

4137

display->funcs.cdclk = &i830_cdclk_funcs;

drivers/gpu/drm/i915/display/intel_cdclk.c

4180

void intel_cdclk_read_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

4184

cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4186

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

4187

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

drivers/gpu/drm/i915/display/intel_cdclk.c

4188

cdclk_state->actual = display->cdclk.hw;

drivers/gpu/drm/i915/display/intel_cdclk.c

4189

cdclk_state->logical = display->cdclk.hw;

drivers/gpu/drm/i915/display/intel_cdclk.c

4194

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4196

if (DISPLAY_VER(display) >= 10 || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4197

return bxt_calc_cdclk(display, min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

4198

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4201

vco = display->cdclk.skl_preferred_vco_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

4206

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4208

} else if (display->platform.cherryview || display->platform.valleyview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

4209

return vlv_calc_cdclk(display, min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

4211

return display->cdclk.max_cdclk_freq;

drivers/gpu/drm/i915/display/intel_cdclk.c

4218

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4219

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

drivers/gpu/drm/i915/display/intel_cdclk.c

4256

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4258

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

drivers/gpu/drm/i915/display/intel_cdclk.c

435

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

441

static void pnv_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

444

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

463

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

475

static void i965gm_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

478

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

486

cdclk_config->vco = intel_hpll_vco(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

514

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

520

static void gm45_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

523

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_cdclk.c

527

cdclk_config->vco = intel_hpll_vco(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

543

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

551

static void hsw_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

554

u32 lcpll = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

559

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

drivers/gpu/drm/i915/display/intel_cdclk.c

563

else if (display->platform.haswell_ult)

drivers/gpu/drm/i915/display/intel_cdclk.c

569

static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

571

int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ?

drivers/gpu/drm/i915/display/intel_cdclk.c

579

if (display->platform.valleyview && min_cdclk > freq_320)

drivers/gpu/drm/i915/display/intel_cdclk.c

589

static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

591

if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/intel_cdclk.c

604

return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1;

drivers/gpu/drm/i915/display/intel_cdclk.c

608

static void vlv_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

613

cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

614

cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

616

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

617

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_cdclk.c

618

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

620

if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_cdclk.c

628

static void vlv_program_pfi_credits(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cdclk.c

632

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_cdclk.c

637

if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

639

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_cdclk.c

651

intel_de_write(display, GCI_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

654

intel_de_write(display, GCI_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

661

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

662

intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);

drivers/gpu/drm/i915/display/intel_cdclk.c

665

static void vlv_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

692

wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);

drivers/gpu/drm/i915/display/intel_cdclk.c

694

vlv_iosf_sb_get(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

699

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_cdclk.c

702

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

704

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),

drivers/gpu/drm/i915/display/intel_cdclk.c

708

drm_err(display->drm, "timed out waiting for CDCLK change\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

713

divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1,

drivers/gpu/drm/i915/display/intel_cdclk.c

717

val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL);

drivers/gpu/drm/i915/display/intel_cdclk.c

720

vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

722

ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),

drivers/gpu/drm/i915/display/intel_cdclk.c

726

drm_err(display->drm, "timed out waiting for CDCLK change\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

730

val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC);

drivers/gpu/drm/i915/display/intel_cdclk.c

741

vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

743

vlv_iosf_sb_put(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

748

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

750

vlv_program_pfi_credits(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

752

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_cdclk.c

755

static void chv_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

781

wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);

drivers/gpu/drm/i915/display/intel_cdclk.c

783

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

784

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_cdclk.c

787

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

789

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),

drivers/gpu/drm/i915/display/intel_cdclk.c

793

drm_err(display->drm, "timed out waiting for CDCLK change\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

795

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_cdclk.c

797

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

799

vlv_program_pfi_credits(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

801

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_cdclk.c

831

static void bdw_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

834

u32 lcpll = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

839

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

drivers/gpu/drm/i915/display/intel_cdclk.c

875

static void bdw_set_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

882

if (drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

883

(intel_de_read(display, LCPLL_CTL) &

drivers/gpu/drm/i915/display/intel_cdclk.c

891

ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

drivers/gpu/drm/i915/display/intel_cdclk.c

893

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.c

898

intel_de_rmw(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

905

ret = intel_de_wait_for_set_us(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

908

drm_err(display->drm, "Switching to FCLK failed\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

910

intel_de_rmw(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

913

intel_de_rmw(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

916

ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_cdclk.c

919

drm_err(display->drm, "Switching back to LCPLL failed\n");

drivers/gpu/drm/i915/display/intel_cdclk.c

921

intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,

drivers/gpu/drm/i915/display/intel_cdclk.c

924

intel_de_write(display, CDCLK_FREQ,

drivers/gpu/drm/i915/display/intel_cdclk.c

927

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_cdclk.c

965

static void skl_dpll0_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

973

val = intel_de_read(display, LCPLL1_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

977

if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))

drivers/gpu/drm/i915/display/intel_cdclk.c

980

val = intel_de_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_cdclk.c

982

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_cdclk.h

25

void intel_cdclk_init_hw(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

26

void intel_cdclk_uninit_hw(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

27

void intel_init_cdclk_hooks(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

28

void intel_update_max_cdclk(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

29

void intel_update_cdclk(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

30

u32 intel_read_rawclk(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

33

int intel_mdclk_cdclk_ratio(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.h

38

void intel_cdclk_dump_config(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.h

41

void intel_cdclk_get_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.h

47

void intel_cdclk_update_hw_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

61

int intel_cdclk_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

62

void intel_cdclk_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cdclk.h

70

void intel_cdclk_read_hw(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cmtg.c

101

static void intel_cmtg_get_config(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cmtg.c

106

val = intel_de_read(display, TRANS_CMTG_CTL_A);

drivers/gpu/drm/i915/display/intel_cmtg.c

109

if (intel_cmtg_has_cmtg_b(display)) {

drivers/gpu/drm/i915/display/intel_cmtg.c

110

val = intel_de_read(display, TRANS_CMTG_CTL_B);

drivers/gpu/drm/i915/display/intel_cmtg.c

114

cmtg_config->trans_a_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_A);

drivers/gpu/drm/i915/display/intel_cmtg.c

115

cmtg_config->trans_b_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_B);

drivers/gpu/drm/i915/display/intel_cmtg.c

118

static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cmtg.c

121

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_cmtg.c

127

static void intel_cmtg_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cmtg.c

134

intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A),

drivers/gpu/drm/i915/display/intel_cmtg.c

138

intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B),

drivers/gpu/drm/i915/display/intel_cmtg.c

142

drm_dbg_kms(display->drm, "Disabling CMTG A\n");

drivers/gpu/drm/i915/display/intel_cmtg.c

143

intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_cmtg.c

149

drm_dbg_kms(display->drm, "Disabling CMTG B\n");

drivers/gpu/drm/i915/display/intel_cmtg.c

150

intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_cmtg.c

155

if (intel_cmtg_has_clock_sel(display) && clk_sel_clr)

drivers/gpu/drm/i915/display/intel_cmtg.c

156

intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);

drivers/gpu/drm/i915/display/intel_cmtg.c

167

void intel_cmtg_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cmtg.c

171

if (!HAS_CMTG(display))

drivers/gpu/drm/i915/display/intel_cmtg.c

174

intel_cmtg_get_config(display, &cmtg_config);

drivers/gpu/drm/i915/display/intel_cmtg.c

175

intel_cmtg_dump_config(display, &cmtg_config);

drivers/gpu/drm/i915/display/intel_cmtg.c

183

if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))

drivers/gpu/drm/i915/display/intel_cmtg.c

186

intel_cmtg_disable(display, &cmtg_config);

drivers/gpu/drm/i915/display/intel_cmtg.c

63

static bool intel_cmtg_has_cmtg_b(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cmtg.c

65

return DISPLAY_VER(display) >= 20;

drivers/gpu/drm/i915/display/intel_cmtg.c

68

static bool intel_cmtg_has_clock_sel(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cmtg.c

70

return DISPLAY_VER(display) >= 14;

drivers/gpu/drm/i915/display/intel_cmtg.c

73

static void intel_cmtg_dump_config(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cmtg.c

76

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cmtg.c

79

intel_cmtg_has_cmtg_b(display) ? str_enabled_disabled(cmtg_config->cmtg_b_enable) : "n/a",

drivers/gpu/drm/i915/display/intel_cmtg.c

84

static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cmtg.c

90

if (!HAS_TRANSCODER(display, trans))

drivers/gpu/drm/i915/display/intel_cmtg.c

95

with_intel_display_power_if_enabled(display, power_domain)

drivers/gpu/drm/i915/display/intel_cmtg.c

96

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));

drivers/gpu/drm/i915/display/intel_cmtg.h

11

void intel_cmtg_sanitize(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_color.c

1038

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1043

intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),

drivers/gpu/drm/i915/display/intel_color.c

1051

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1053

intel_de_write(display, GAMMA_MODE(crtc->pipe),

drivers/gpu/drm/i915/display/intel_color.c

1056

intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),

drivers/gpu/drm/i915/display/intel_color.c

1062

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1064

return intel_de_read(display, GAMMA_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

1069

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1071

return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

1076

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1082

tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/intel_color.c

1087

if (!HAS_GMCH(display) && tmp & DISP_PIPE_CSC_ENABLE)

drivers/gpu/drm/i915/display/intel_color.c

1103

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1109

if (DISPLAY_VER(display) < 35) {

drivers/gpu/drm/i915/display/intel_color.c

1110

u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

1123

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1140

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), val);

drivers/gpu/drm/i915/display/intel_color.c

1142

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1144

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

drivers/gpu/drm/i915/display/intel_color.c

1150

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1158

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), 0);

drivers/gpu/drm/i915/display/intel_color.c

1160

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1162

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

drivers/gpu/drm/i915/display/intel_color.c

1167

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1184

intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

1188

create_linear_lut(struct intel_display *display, int lut_size)

drivers/gpu/drm/i915/display/intel_color.c

1194

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

1222

create_resized_lut(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_color.c

1231

blob_out = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

1259

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1270

intel_de_write_fw(display, PALETTE(display, pipe, i),

drivers/gpu/drm/i915/display/intel_color.c

1277

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1283

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

1284

PALETTE(display, pipe, 2 * i + 0),

drivers/gpu/drm/i915/display/intel_color.c

1286

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

1287

PALETTE(display, pipe, 2 * i + 1),

drivers/gpu/drm/i915/display/intel_color.c

1313

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1319

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

1320

PALETTE(display, pipe, 2 * i + 0),

drivers/gpu/drm/i915/display/intel_color.c

1322

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

1323

PALETTE(display, pipe, 2 * i + 1),

drivers/gpu/drm/i915/display/intel_color.c

1327

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 0), lut[i].red);

drivers/gpu/drm/i915/display/intel_color.c

1328

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 1), lut[i].green);

drivers/gpu/drm/i915/display/intel_color.c

1329

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 2), lut[i].blue);

drivers/gpu/drm/i915/display/intel_color.c

1353

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1358

intel_de_write_fw(display, reg, val);

drivers/gpu/drm/i915/display/intel_color.c

1364

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1369

intel_de_write_fw(display, reg, val);

drivers/gpu/drm/i915/display/intel_color.c

1586

static int glk_degamma_lut_size(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_color.c

1588

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_color.c

1620

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1652

DISPLAY_VER(display) >= 14 ?

drivers/gpu/drm/i915/display/intel_color.c

1657

while (i++ < glk_degamma_lut_size(display))

drivers/gpu/drm/i915/display/intel_color.c

1659

DISPLAY_VER(display) >= 14 ?

drivers/gpu/drm/i915/display/intel_color.c

1860

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1866

intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0),

drivers/gpu/drm/i915/display/intel_color.c

1868

intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1),

drivers/gpu/drm/i915/display/intel_color.c

1894

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1900

intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 0),

drivers/gpu/drm/i915/display/intel_color.c

1902

intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 1),

drivers/gpu/drm/i915/display/intel_color.c

1909

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1925

intel_de_write_fw(display, CGM_PIPE_MODE(crtc->pipe),

drivers/gpu/drm/i915/display/intel_color.c

1931

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1936

display->funcs.color->load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1942

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1944

if (display->funcs.color->color_commit_noarm)

drivers/gpu/drm/i915/display/intel_color.c

1945

display->funcs.color->color_commit_noarm(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1951

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1953

display->funcs.color->color_commit_arm(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1958

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1960

if (display->funcs.color->color_post_update)

drivers/gpu/drm/i915/display/intel_color.c

1961

display->funcs.color->color_post_update(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1966

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1972

if (DISPLAY_VER(display) < 9) {

drivers/gpu/drm/i915/display/intel_color.c

1988

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1990

return crtc_state->dsb_color && !HAS_DOUBLE_BUFFERED_LUT(display);

drivers/gpu/drm/i915/display/intel_color.c

1995

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1997

return crtc_state->dsb_color && HAS_DOUBLE_BUFFERED_LUT(display);

drivers/gpu/drm/i915/display/intel_color.c

2003

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

2017

if (HAS_DOUBLE_BUFFERED_LUT(display))

drivers/gpu/drm/i915/display/intel_color.c

2025

display->funcs.color->load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2057

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

2061

if (HAS_DOUBLE_BUFFERED_LUT(display))

drivers/gpu/drm/i915/display/intel_color.c

2100

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

2116

return display->funcs.color->color_check(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2121

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2123

display->funcs.color->get_config(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2125

display->funcs.color->read_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2127

if (display->funcs.color->read_csc)

drivers/gpu/drm/i915/display/intel_color.c

2128

display->funcs.color->read_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2136

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2145

return display->funcs.color->lut_equal(crtc_state, blob1, blob2,

drivers/gpu/drm/i915/display/intel_color.c

2152

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_color.c

2160

(DISPLAY_VER(display) < 9 && plane->id == PLANE_PRIMARY);

drivers/gpu/drm/i915/display/intel_color.c

2167

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

2182

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_color.c

2197

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_color.c

2206

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2212

return DISPLAY_INFO(display)->color.gamma_lut_tests;

drivers/gpu/drm/i915/display/intel_color.c

2217

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2219

return DISPLAY_INFO(display)->color.degamma_lut_tests;

drivers/gpu/drm/i915/display/intel_color.c

2224

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2230

return DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

2235

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2237

return DISPLAY_INFO(display)->color.degamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

2243

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

2251

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2263

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2271

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

228

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_color.c

231

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_HI(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2316

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

2325

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

233

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_ME(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2336

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2339

if (DISPLAY_VER(display) >= 11 || HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/intel_color.c

2340

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2342

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2344

} else if (DISPLAY_VER(display) == 10) {

drivers/gpu/drm/i915/display/intel_color.c

2345

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2348

crtc_state->pre_csc_lut != display->color.glk_linear_degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2349

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

235

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_LO(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2354

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2357

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2375

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

238

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RY_GY(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2390

if (DISPLAY_VER(display) < 4 &&

drivers/gpu/drm/i915/display/intel_color.c

240

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BY(pipe),

drivers/gpu/drm/i915/display/intel_color.c

243

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RU_GU(pipe),

drivers/gpu/drm/i915/display/intel_color.c

245

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BU(pipe),

drivers/gpu/drm/i915/display/intel_color.c

248

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RV_GV(pipe),

drivers/gpu/drm/i915/display/intel_color.c

250

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BV(pipe),

drivers/gpu/drm/i915/display/intel_color.c

253

if (DISPLAY_VER(display) < 7)

drivers/gpu/drm/i915/display/intel_color.c

2559

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

256

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_HI(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2564

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_color.c

258

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_ME(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2598

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

260

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_LO(pipe),

drivers/gpu/drm/i915/display/intel_color.c

2608

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2616

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

267

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

2671

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2677

drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);

drivers/gpu/drm/i915/display/intel_color.c

2678

drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);

drivers/gpu/drm/i915/display/intel_color.c

2680

degamma_lut = create_resized_lut(display, crtc_state->hw.degamma_lut, 512,

drivers/gpu/drm/i915/display/intel_color.c

2685

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut, 512,

drivers/gpu/drm/i915/display/intel_color.c

2704

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

271

csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2714

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

272

csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_PREOFF_ME(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2722

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

273

csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_PREOFF_LO(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2730

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

275

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2777

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

278

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2782

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_color.c

2783

DISPLAY_INFO(display)->color.degamma_lut_size,

drivers/gpu/drm/i915/display/intel_color.c

2799

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_color.c

281

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2822

display->color.glk_linear_degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

284

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2841

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_color.c

2852

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

2860

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

287

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2899

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

290

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));

drivers/gpu/drm/i915/display/intel_color.c

2917

else if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_color.c

293

if (DISPLAY_VER(display) < 7)

drivers/gpu/drm/i915/display/intel_color.c

296

csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_HI(pipe));

drivers/gpu/drm/i915/display/intel_color.c

297

csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_ME(pipe));

drivers/gpu/drm/i915/display/intel_color.c

298

csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_LO(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3298

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3304

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

3313

u32 val = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

3314

PALETTE(display, pipe, i));

drivers/gpu/drm/i915/display/intel_color.c

3324

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3325

u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3332

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

334

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_color.c

3340

ldw = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

3341

PALETTE(display, pipe, 2 * i + 0));

drivers/gpu/drm/i915/display/intel_color.c

3342

udw = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

3343

PALETTE(display, pipe, 2 * i + 1));

drivers/gpu/drm/i915/display/intel_color.c

337

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_HI(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3375

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3376

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3381

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

339

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_ME(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3390

u32 ldw = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

3391

PALETTE(display, pipe, 2 * i + 0));

drivers/gpu/drm/i915/display/intel_color.c

3392

u32 udw = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_color.c

3393

PALETTE(display, pipe, 2 * i + 1));

drivers/gpu/drm/i915/display/intel_color.c

3398

lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 0)));

drivers/gpu/drm/i915/display/intel_color.c

3399

lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 1)));

drivers/gpu/drm/i915/display/intel_color.c

3400

lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 2)));

drivers/gpu/drm/i915/display/intel_color.c

341

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_LO(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3427

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3428

int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3433

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

344

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3442

u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));

drivers/gpu/drm/i915/display/intel_color.c

3443

u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));

drivers/gpu/drm/i915/display/intel_color.c

3453

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3454

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3459

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

346

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BY(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3468

u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));

drivers/gpu/drm/i915/display/intel_color.c

3469

u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));

drivers/gpu/drm/i915/display/intel_color.c

3479

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3482

crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

349

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3502

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3508

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

351

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BU(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3517

u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));

drivers/gpu/drm/i915/display/intel_color.c

3527

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3528

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3533

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

354

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3542

u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));

drivers/gpu/drm/i915/display/intel_color.c

356

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BV(pipe),

drivers/gpu/drm/i915/display/intel_color.c

359

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3590

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3596

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

3607

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3609

val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

drivers/gpu/drm/i915/display/intel_color.c

361

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3614

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

363

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3655

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3661

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

3669

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3671

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3676

u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3681

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

370

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3720

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3721

int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3726

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

3739

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

374

csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3741

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3746

u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3748

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_color.c

375

csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3754

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

376

csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));

drivers/gpu/drm/i915/display/intel_color.c

378

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3786

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3787

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

3792

blob = drm_property_create_blob(display->drm,

drivers/gpu/drm/i915/display/intel_color.c

3800

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3802

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

3807

u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3808

u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

drivers/gpu/drm/i915/display/intel_color.c

381

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3813

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

384

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3855

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3865

if (!icl_is_hdr_plane(display, plane) || !blob)

drivers/gpu/drm/i915/display/intel_color.c

387

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));

drivers/gpu/drm/i915/display/intel_color.c

390

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3913

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),

drivers/gpu/drm/i915/display/intel_color.c

3915

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),

drivers/gpu/drm/i915/display/intel_color.c

3918

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),

drivers/gpu/drm/i915/display/intel_color.c

3920

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),

drivers/gpu/drm/i915/display/intel_color.c

3923

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),

drivers/gpu/drm/i915/display/intel_color.c

3925

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),

drivers/gpu/drm/i915/display/intel_color.c

3928

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0), 0);

drivers/gpu/drm/i915/display/intel_color.c

3929

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1), 0);

drivers/gpu/drm/i915/display/intel_color.c

393

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3930

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2), 0);

drivers/gpu/drm/i915/display/intel_color.c

3935

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

3938

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

3941

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

3950

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3957

if (icl_is_hdr_plane(display, plane)) {

drivers/gpu/drm/i915/display/intel_color.c

396

csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3960

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

3968

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

397

csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3976

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

398

csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));

drivers/gpu/drm/i915/display/intel_color.c

3984

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

3989

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

3995

intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);

drivers/gpu/drm/i915/display/intel_color.c

4003

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4010

if (icl_is_hdr_plane(display, plane)) {

drivers/gpu/drm/i915/display/intel_color.c

4011

intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),

drivers/gpu/drm/i915/display/intel_color.c

4014

intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),

drivers/gpu/drm/i915/display/intel_color.c

4021

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

4028

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

4038

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

4043

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

4049

intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);

drivers/gpu/drm/i915/display/intel_color.c

4050

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_color.c

4076

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_color.c

4081

if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {

drivers/gpu/drm/i915/display/intel_color.c

4082

drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",

drivers/gpu/drm/i915/display/intel_color.c

4087

intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), LUT_3D_AUTO_INCREMENT);

drivers/gpu/drm/i915/display/intel_color.c

4089

intel_de_write_dsb(display, dsb, LUT_3D_DATA(pipe), glk_3dlut_10(&lut[i]));

drivers/gpu/drm/i915/display/intel_color.c

4090

intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0);

drivers/gpu/drm/i915/display/intel_color.c

4095

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

4099

if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {

drivers/gpu/drm/i915/display/intel_color.c

4100

drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not committing change\n",

drivers/gpu/drm/i915/display/intel_color.c

4108

intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val);

drivers/gpu/drm/i915/display/intel_color.c

419

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

422

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_color.c

4243

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4246

if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))

drivers/gpu/drm/i915/display/intel_color.c

4254

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4256

if (display->funcs.color->load_plane_csc_matrix)

drivers/gpu/drm/i915/display/intel_color.c

4257

display->funcs.color->load_plane_csc_matrix(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

426

if (DISPLAY_VER(display) < 7 || display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_color.c

4264

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4266

if (display->funcs.color->load_plane_luts)

drivers/gpu/drm/i915/display/intel_color.c

4267

display->funcs.color->load_plane_luts(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4271

intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_color.c

4273

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_color.c

4283

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4286

if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))

drivers/gpu/drm/i915/display/intel_color.c

4303

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

4309

gamma_lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

4310

degamma_lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;

drivers/gpu/drm/i915/display/intel_color.c

4311

has_ctm = DISPLAY_VER(display) >= 5;

drivers/gpu/drm/i915/display/intel_color.c

4321

if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)

drivers/gpu/drm/i915/display/intel_color.c

4328

int intel_color_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_color.c

4332

if (DISPLAY_VER(display) != 10)

drivers/gpu/drm/i915/display/intel_color.c

4335

blob = create_linear_lut(display,

drivers/gpu/drm/i915/display/intel_color.c

4336

DISPLAY_INFO(display)->color.degamma_lut_size);

drivers/gpu/drm/i915/display/intel_color.c

434

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

4340

display->color.glk_linear_degamma_lut = blob;

drivers/gpu/drm/i915/display/intel_color.c

4345

void intel_color_init_hooks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_color.c

4347

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/intel_color.c

4348

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_color.c

4349

display->funcs.color = &chv_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4350

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_color.c

4351

display->funcs.color = &vlv_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4352

else if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_color.c

4353

display->funcs.color = &i965_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4355

display->funcs.color = &i9xx_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4357

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_color.c

4358

display->funcs.color = &tgl_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4359

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_color.c

4360

display->funcs.color = &icl_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4361

else if (DISPLAY_VER(display) == 10)

drivers/gpu/drm/i915/display/intel_color.c

4362

display->funcs.color = &glk_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4363

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_color.c

4364

display->funcs.color = &skl_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4365

else if (DISPLAY_VER(display) == 8)

drivers/gpu/drm/i915/display/intel_color.c

4366

display->funcs.color = &bdw_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4367

else if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_color.c

4368

display->funcs.color = &hsw_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4369

else if (DISPLAY_VER(display) == 7)

drivers/gpu/drm/i915/display/intel_color.c

4370

display->funcs.color = &ivb_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

4372

display->funcs.color = &ilk_color_funcs;

drivers/gpu/drm/i915/display/intel_color.c

442

if (DISPLAY_VER(display) == 10)

drivers/gpu/drm/i915/display/intel_color.c

457

static void ilk_csc_copy(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_color.c

463

if (DISPLAY_VER(display) < 7)

drivers/gpu/drm/i915/display/intel_color.c

471

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

479

ilk_csc_copy(display, csc, &ilk_csc_matrix_limited_range);

drivers/gpu/drm/i915/display/intel_color.c

481

ilk_csc_copy(display, csc, &ilk_csc_matrix_identity);

drivers/gpu/drm/i915/display/intel_color.c

529

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

533

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

drivers/gpu/drm/i915/display/intel_color.c

537

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

drivers/gpu/drm/i915/display/intel_color.c

539

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);

drivers/gpu/drm/i915/display/intel_color.c

541

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

drivers/gpu/drm/i915/display/intel_color.c

543

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_limited_range);

drivers/gpu/drm/i915/display/intel_color.c

551

drm_WARN_ON(display->drm, !display->platform.geminilake);

drivers/gpu/drm/i915/display/intel_color.c

553

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);

drivers/gpu/drm/i915/display/intel_color.c

570

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

573

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);

drivers/gpu/drm/i915/display/intel_color.c

577

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);

drivers/gpu/drm/i915/display/intel_color.c

583

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);

drivers/gpu/drm/i915/display/intel_color.c

585

ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);

drivers/gpu/drm/i915/display/intel_color.c

587

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);

drivers/gpu/drm/i915/display/intel_color.c

589

ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);

drivers/gpu/drm/i915/display/intel_color.c

591

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);

drivers/gpu/drm/i915/display/intel_color.c

651

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

654

intel_de_write_fw(display, PIPE_WGC_C01_C00(display, pipe),

drivers/gpu/drm/i915/display/intel_color.c

656

intel_de_write_fw(display, PIPE_WGC_C02(display, pipe),

drivers/gpu/drm/i915/display/intel_color.c

659

intel_de_write_fw(display, PIPE_WGC_C11_C10(display, pipe),

drivers/gpu/drm/i915/display/intel_color.c

661

intel_de_write_fw(display, PIPE_WGC_C12(display, pipe),

drivers/gpu/drm/i915/display/intel_color.c

664

intel_de_write_fw(display, PIPE_WGC_C21_C20(display, pipe),

drivers/gpu/drm/i915/display/intel_color.c

666

intel_de_write_fw(display, PIPE_WGC_C22(display, pipe),

drivers/gpu/drm/i915/display/intel_color.c

673

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

677

tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));

drivers/gpu/drm/i915/display/intel_color.c

681

tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));

drivers/gpu/drm/i915/display/intel_color.c

684

tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));

drivers/gpu/drm/i915/display/intel_color.c

688

tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));

drivers/gpu/drm/i915/display/intel_color.c

691

tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));

drivers/gpu/drm/i915/display/intel_color.c

695

tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));

drivers/gpu/drm/i915/display/intel_color.c

709

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

712

drm_WARN_ON(display->drm, !crtc_state->wgc_enable);

drivers/gpu/drm/i915/display/intel_color.c

716

drm_WARN_ON(display->drm, crtc_state->wgc_enable);

drivers/gpu/drm/i915/display/intel_color.c

753

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

756

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF01(pipe),

drivers/gpu/drm/i915/display/intel_color.c

758

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF23(pipe),

drivers/gpu/drm/i915/display/intel_color.c

760

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF45(pipe),

drivers/gpu/drm/i915/display/intel_color.c

762

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF67(pipe),

drivers/gpu/drm/i915/display/intel_color.c

764

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF8(pipe),

drivers/gpu/drm/i915/display/intel_color.c

771

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_color.c

775

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));

drivers/gpu/drm/i915/display/intel_color.c

779

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));

drivers/gpu/drm/i915/display/intel_color.c

783

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));

drivers/gpu/drm/i915/display/intel_color.c

787

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));

drivers/gpu/drm/i915/display/intel_color.c

791

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));

drivers/gpu/drm/i915/display/intel_color.c

805

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

807

drm_WARN_ON(display->drm, crtc_state->wgc_enable);

drivers/gpu/drm/i915/display/intel_color.c

810

drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);

drivers/gpu/drm/i915/display/intel_color.c

814

drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);

drivers/gpu/drm/i915/display/intel_color.h

20

void intel_color_init_hooks(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_color.h

21

int intel_color_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_color.h

49

bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_color_pipeline.c

21

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_color_pipeline.c

50

if (DISPLAY_VER(display) >= 35 &&

drivers/gpu/drm/i915/display/intel_color_pipeline.c

51

intel_color_crtc_has_3dlut(display, pipe) &&

drivers/gpu/drm/i915/display/intel_color_pipeline.c

84

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_color_pipeline.c

91

if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))

drivers/gpu/drm/i915/display/intel_combo_phy.c

101

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_combo_phy.c

112

static bool icl_verify_procmon_ref_values(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_combo_phy.c

118

procmon = icl_get_procmon_ref_values(display, phy);

drivers/gpu/drm/i915/display/intel_combo_phy.c

120

ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

122

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

124

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

130

static bool has_phy_misc(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_combo_phy.c

141

if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_combo_phy.c

143

else if ((display->platform.jasperlake || display->platform.elkhartlake) ||

drivers/gpu/drm/i915/display/intel_combo_phy.c

144

display->platform.rocketlake ||

drivers/gpu/drm/i915/display/intel_combo_phy.c

145

display->platform.dg1)

drivers/gpu/drm/i915/display/intel_combo_phy.c

151

static bool icl_combo_phy_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_combo_phy.c

155

if (!has_phy_misc(display, phy))

drivers/gpu/drm/i915/display/intel_combo_phy.c

156

return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;

drivers/gpu/drm/i915/display/intel_combo_phy.c

158

return !(intel_de_read(display, ICL_PHY_MISC(phy)) &

drivers/gpu/drm/i915/display/intel_combo_phy.c

160

(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);

drivers/gpu/drm/i915/display/intel_combo_phy.c

163

static bool ehl_vbt_ddi_d_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_combo_phy.c

165

bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);

drivers/gpu/drm/i915/display/intel_combo_phy.c

166

bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);

drivers/gpu/drm/i915/display/intel_combo_phy.c

167

bool dsi_present = intel_bios_is_dsi_present(display, NULL);

drivers/gpu/drm/i915/display/intel_combo_phy.c

184

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_combo_phy.c

190

static bool phy_is_master(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_combo_phy.c

210

else if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_combo_phy.c

212

else if (display->platform.dg1 || display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_combo_phy.c

218

static bool icl_combo_phy_verify_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_combo_phy.c

224

if (!icl_combo_phy_enabled(display, phy))

drivers/gpu/drm/i915/display/intel_combo_phy.c

227

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

228

ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

234

ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

238

ret &= icl_verify_procmon_ref_values(display, phy);

drivers/gpu/drm/i915/display/intel_combo_phy.c

240

if (phy_is_master(display, phy)) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

241

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

244

if (display->platform.jasperlake || display->platform.elkhartlake) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

245

if (ehl_vbt_ddi_d_present(display))

drivers/gpu/drm/i915/display/intel_combo_phy.c

248

ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

254

ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

260

void intel_combo_phy_power_up_lanes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_combo_phy.c

267

drm_WARN_ON(display->drm, lane_reversal);

drivers/gpu/drm/i915/display/intel_combo_phy.c

305

intel_de_rmw(display, ICL_PORT_CL_DW10(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

309

static void icl_combo_phys_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_combo_phy.c

313

for_each_combo_phy(display, phy) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

317

if (icl_combo_phy_verify_state(display, phy))

drivers/gpu/drm/i915/display/intel_combo_phy.c

320

procmon = icl_get_procmon_ref_values(display, phy);

drivers/gpu/drm/i915/display/intel_combo_phy.c

322

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_combo_phy.c

326

if (!has_phy_misc(display, phy))

drivers/gpu/drm/i915/display/intel_combo_phy.c

337

val = intel_de_read(display, ICL_PHY_MISC(phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

338

if ((display->platform.jasperlake || display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_combo_phy.c

342

if (ehl_vbt_ddi_d_present(display))

drivers/gpu/drm/i915/display/intel_combo_phy.c

347

intel_de_write(display, ICL_PHY_MISC(phy), val);

drivers/gpu/drm/i915/display/intel_combo_phy.c

350

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

351

val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

355

intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);

drivers/gpu/drm/i915/display/intel_combo_phy.c

357

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

360

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);

drivers/gpu/drm/i915/display/intel_combo_phy.c

363

icl_set_procmon_ref_values(display, phy);

drivers/gpu/drm/i915/display/intel_combo_phy.c

365

if (phy_is_master(display, phy))

drivers/gpu/drm/i915/display/intel_combo_phy.c

366

intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

369

intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);

drivers/gpu/drm/i915/display/intel_combo_phy.c

370

intel_de_rmw(display, ICL_PORT_CL_DW5(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

375

static void icl_combo_phys_uninit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_combo_phy.c

379

for_each_combo_phy_reverse(display, phy) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

381

!icl_combo_phy_verify_state(display, phy)) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

382

if (display->platform.tigerlake || display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

388

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_combo_phy.c

392

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_combo_phy.c

398

if (!has_phy_misc(display, phy))

drivers/gpu/drm/i915/display/intel_combo_phy.c

401

intel_de_rmw(display, ICL_PHY_MISC(phy), 0,

drivers/gpu/drm/i915/display/intel_combo_phy.c

405

intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);

drivers/gpu/drm/i915/display/intel_combo_phy.c

409

void intel_combo_phy_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_combo_phy.c

411

icl_combo_phys_init(display);

drivers/gpu/drm/i915/display/intel_combo_phy.c

414

void intel_combo_phy_uninit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_combo_phy.c

416

icl_combo_phys_uninit(display);

drivers/gpu/drm/i915/display/intel_combo_phy.c

58

icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_combo_phy.c

62

val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

80

static void icl_set_procmon_ref_values(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_combo_phy.c

85

procmon = icl_get_procmon_ref_values(display, phy);

drivers/gpu/drm/i915/display/intel_combo_phy.c

87

intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),

drivers/gpu/drm/i915/display/intel_combo_phy.c

90

intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);

drivers/gpu/drm/i915/display/intel_combo_phy.c

91

intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);

drivers/gpu/drm/i915/display/intel_combo_phy.c

94

static bool check_phy_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_combo_phy.c

98

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_combo_phy.h

14

void intel_combo_phy_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_combo_phy.h

15

void intel_combo_phy_uninit(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_combo_phy.h

16

void intel_combo_phy_power_up_lanes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_connector.c

198

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_connector.c

200

drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_connector.c

257

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_connector.c

260

prop = display->properties.force_audio;

drivers/gpu/drm/i915/display/intel_connector.c

262

prop = drm_property_create_enum(display->drm, 0,

drivers/gpu/drm/i915/display/intel_connector.c

269

display->properties.force_audio = prop;

drivers/gpu/drm/i915/display/intel_connector.c

283

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_connector.c

286

prop = display->properties.broadcast_rgb;

drivers/gpu/drm/i915/display/intel_connector.c

288

prop = drm_property_create_enum(display->drm, DRM_MODE_PROP_ENUM,

drivers/gpu/drm/i915/display/intel_connector.c

295

display->properties.broadcast_rgb = prop;

drivers/gpu/drm/i915/display/intel_connector.c

327

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_connector.c

334

if (!HAS_GMCH(display) || connector->connector_type == DRM_MODE_CONNECTOR_LVDS)

drivers/gpu/drm/i915/display/intel_connector.c

45

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_connector.c

47

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id,

drivers/gpu/drm/i915/display/intel_connector.c

51

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_connector.c

57

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_connector.c

66

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_connector.c

69

if (!queue_work(display->wq.unordered, &connector->modeset_retry_work))

drivers/gpu/drm/i915/display/intel_crt.c

1006

void intel_crt_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_crt.c

1014

if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_crt.c

1016

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_crt.c

1021

adpa = intel_de_read(display, adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

1031

intel_de_write(display, adpa_reg,

drivers/gpu/drm/i915/display/intel_crt.c

1035

if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_crt.c

1037

intel_de_write(display, adpa_reg, adpa);

drivers/gpu/drm/i915/display/intel_crt.c

1050

ddc_pin = display->vbt.crt_ddc_pin;

drivers/gpu/drm/i915/display/intel_crt.c

1052

drm_connector_init_with_ddc(display->drm, &connector->base,

drivers/gpu/drm/i915/display/intel_crt.c

1055

intel_gmbus_get_adapter(display, ddc_pin));

drivers/gpu/drm/i915/display/intel_crt.c

1057

drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,

drivers/gpu/drm/i915/display/intel_crt.c

1064

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_crt.c

1069

if (DISPLAY_VER(display) != 2)

drivers/gpu/drm/i915/display/intel_crt.c

1076

if (HAS_HOTPLUG(display) &&

drivers/gpu/drm/i915/display/intel_crt.c

1086

if (HAS_DDI(display)) {

drivers/gpu/drm/i915/display/intel_crt.c

1087

assert_port_valid(display, PORT_E);

drivers/gpu/drm/i915/display/intel_crt.c

110

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

1104

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_crt.c

1126

if (HAS_PCH_LPT(display)) {

drivers/gpu/drm/i915/display/intel_crt.c

1130

display->fdi.rx_config = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

115

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_crt.c

120

ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);

drivers/gpu/drm/i915/display/intel_crt.c

122

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_crt.c

129

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

133

tmp = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

178

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

184

if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_crt.c

195

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_crt.c

197

else if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_crt.c

202

if (!HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_crt.c

203

intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_crt.c

220

intel_de_write(display, crt->adpa_reg, adpa);

drivers/gpu/drm/i915/display/intel_crt.c

251

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

253

drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

255

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_crt.c

263

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

282

drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

284

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_crt.c

292

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

294

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

296

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_crt.c

304

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

308

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

310

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_crt.c

322

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

326

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

340

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_crt.c

341

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_crt.c

356

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

357

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_crt.c

361

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_crt.c

368

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_crt.c

370

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_crt.c

376

else if (IS_DISPLAY_VER(display, 3, 4))

drivers/gpu/drm/i915/display/intel_crt.c

387

if (HAS_PCH_LPT(display) &&

drivers/gpu/drm/i915/display/intel_crt.c

437

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

456

if (HAS_PCH_LPT(display)) {

drivers/gpu/drm/i915/display/intel_crt.c

459

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

479

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

486

bool turn_off_dac = HAS_PCH_SPLIT(display);

drivers/gpu/drm/i915/display/intel_crt.c

491

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

492

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

499

intel_de_write(display, crt->adpa_reg, adpa);

drivers/gpu/drm/i915/display/intel_crt.c

501

if (intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_crt.c

505

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

509

intel_de_write(display, crt->adpa_reg, save_adpa);

drivers/gpu/drm/i915/display/intel_crt.c

510

intel_de_posting_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

515

adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

520

drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",

drivers/gpu/drm/i915/display/intel_crt.c

528

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

548

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

549

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

554

intel_de_write(display, crt->adpa_reg, adpa);

drivers/gpu/drm/i915/display/intel_crt.c

556

if (intel_de_wait_for_clear_ms(display, crt->adpa_reg,

drivers/gpu/drm/i915/display/intel_crt.c

558

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

560

intel_de_write(display, crt->adpa_reg, save_adpa);

drivers/gpu/drm/i915/display/intel_crt.c

564

adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

570

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

580

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

585

if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_crt.c

588

if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_crt.c

596

if (display->platform.g45)

drivers/gpu/drm/i915/display/intel_crt.c

603

i915_hotplug_interrupt_update(display,

drivers/gpu/drm/i915/display/intel_crt.c

607

if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display),

drivers/gpu/drm/i915/display/intel_crt.c

609

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

613

stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));

drivers/gpu/drm/i915/display/intel_crt.c

618

intel_de_write(display, PORT_HOTPLUG_STAT(display),

drivers/gpu/drm/i915/display/intel_crt.c

621

i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0);

drivers/gpu/drm/i915/display/intel_crt.c

664

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

677

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

680

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

685

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

697

struct intel_display *display = to_intel_display(&crt->base);

drivers/gpu/drm/i915/display/intel_crt.c

708

drm_dbg_kms(display->drm, "starting load-detect on CRT\n");

drivers/gpu/drm/i915/display/intel_crt.c

710

save_bclrpat = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

711

BCLRPAT(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_crt.c

712

save_vtotal = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

713

TRANS_VTOTAL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_crt.c

714

vblank = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

715

TRANS_VBLANK(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_crt.c

724

intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);

drivers/gpu/drm/i915/display/intel_crt.c

726

if (DISPLAY_VER(display) != 2) {

drivers/gpu/drm/i915/display/intel_crt.c

727

u32 transconf = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

728

TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_crt.c

730

intel_de_write(display, TRANSCONF(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_crt.c

732

intel_de_posting_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

733

TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_crt.c

738

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));

drivers/gpu/drm/i915/display/intel_crt.c

739

st00 = intel_de_read8(display, _VGA_MSR_WRITE);

drivers/gpu/drm/i915/display/intel_crt.c

744

intel_de_write(display, TRANSCONF(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_crt.c

755

u32 vsync = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

756

TRANS_VSYNC(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_crt.c

760

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_crt.c

761

TRANS_VBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_crt.c

775

while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)

drivers/gpu/drm/i915/display/intel_crt.c

777

while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)

drivers/gpu/drm/i915/display/intel_crt.c

787

st00 = intel_de_read8(display, _VGA_MSR_WRITE);

drivers/gpu/drm/i915/display/intel_crt.c

790

} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

drivers/gpu/drm/i915/display/intel_crt.c

794

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_crt.c

795

TRANS_VBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_crt.c

809

intel_de_write(display, BCLRPAT(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_crt.c

846

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

853

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",

drivers/gpu/drm/i915/display/intel_crt.c

857

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_crt.c

860

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_crt.c

863

if (display->params.load_detect_test) {

drivers/gpu/drm/i915/display/intel_crt.c

864

wakeref = intel_display_power_get(display, encoder->power_domain);

drivers/gpu/drm/i915/display/intel_crt.c

872

wakeref = intel_display_power_get(display, encoder->power_domain);

drivers/gpu/drm/i915/display/intel_crt.c

874

if (HAS_HOTPLUG(display)) {

drivers/gpu/drm/i915/display/intel_crt.c

880

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

885

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_crt.c

898

if (HAS_HOTPLUG(display)) {

drivers/gpu/drm/i915/display/intel_crt.c

91

bool intel_crt_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crt.c

918

else if (DISPLAY_VER(display) < 4)

drivers/gpu/drm/i915/display/intel_crt.c

921

else if (display->params.load_detect_test)

drivers/gpu/drm/i915/display/intel_crt.c

929

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_crt.c

936

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_crt.c

943

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_crt.c

946

wakeref = intel_display_power_get(display, encoder->power_domain);

drivers/gpu/drm/i915/display/intel_crt.c

949

if (ret || !display->platform.g4x)

drivers/gpu/drm/i915/display/intel_crt.c

953

ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);

drivers/gpu/drm/i915/display/intel_crt.c

957

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_crt.c

96

val = intel_de_read(display, adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

964

struct intel_display *display = to_intel_display(encoder->dev);

drivers/gpu/drm/i915/display/intel_crt.c

967

if (DISPLAY_VER(display) >= 5) {

drivers/gpu/drm/i915/display/intel_crt.c

970

adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

973

intel_de_write(display, crt->adpa_reg, adpa);

drivers/gpu/drm/i915/display/intel_crt.c

974

intel_de_posting_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

976

drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);

drivers/gpu/drm/i915/display/intel_crt.c

99

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_crt.h

16

bool intel_crt_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crt.h

18

void intel_crt_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_crt.h

21

static inline bool intel_crt_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crt.h

26

static inline void intel_crt_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_crtc.c

100

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

116

if (display->platform.i965gm &&

drivers/gpu/drm/i915/display/intel_crtc.c

120

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_crtc.c

122

else if (DISPLAY_VER(display) >= 3)

drivers/gpu/drm/i915/display/intel_crtc.c

149

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

164

flush_work(&display->irq.vblank_notify_work);

drivers/gpu/drm/i915/display/intel_crtc.c

311

static int __intel_crtc_init(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_crtc.c

323

crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe];

drivers/gpu/drm/i915/display/intel_crtc.c

325

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_crtc.c

326

primary = skl_universal_plane_create(display, pipe, PLANE_1);

drivers/gpu/drm/i915/display/intel_crtc.c

328

primary = intel_primary_plane_create(display, pipe);

drivers/gpu/drm/i915/display/intel_crtc.c

335

intel_init_fifo_underrun_reporting(display, crtc, false);

drivers/gpu/drm/i915/display/intel_crtc.c

337

for_each_sprite(display, pipe, sprite) {

drivers/gpu/drm/i915/display/intel_crtc.c

340

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_crtc.c

341

plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite);

drivers/gpu/drm/i915/display/intel_crtc.c

343

plane = intel_sprite_plane_create(display, pipe, sprite);

drivers/gpu/drm/i915/display/intel_crtc.c

351

cursor = intel_cursor_plane_create(display, pipe);

drivers/gpu/drm/i915/display/intel_crtc.c

358

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/intel_crtc.c

359

if (display->platform.cherryview ||

drivers/gpu/drm/i915/display/intel_crtc.c

360

display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_crtc.c

361

display->platform.g4x)

drivers/gpu/drm/i915/display/intel_crtc.c

363

else if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/intel_crtc.c

365

else if (display->platform.i945gm ||

drivers/gpu/drm/i915/display/intel_crtc.c

366

display->platform.i915gm)

drivers/gpu/drm/i915/display/intel_crtc.c

368

else if (DISPLAY_VER(display) == 3)

drivers/gpu/drm/i915/display/intel_crtc.c

373

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_crtc.c

379

ret = drm_crtc_init_with_planes(display->drm, &crtc->base,

drivers/gpu/drm/i915/display/intel_crtc.c

385

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_crtc.c

396

drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);

drivers/gpu/drm/i915/display/intel_crtc.c

398

if (HAS_CASF(display) && crtc->num_scalers >= 2)

drivers/gpu/drm/i915/display/intel_crtc.c

40

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_crtc.c

409

int intel_crtc_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_crtc.c

414

drm_dbg_kms(display->drm, "%d display pipe%s available.\n",

drivers/gpu/drm/i915/display/intel_crtc.c

415

INTEL_NUM_PIPES(display), str_plural(INTEL_NUM_PIPES(display)));

drivers/gpu/drm/i915/display/intel_crtc.c

417

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_crtc.c

418

ret = __intel_crtc_init(display, pipe);

drivers/gpu/drm/i915/display/intel_crtc.c

42

if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0,

drivers/gpu/drm/i915/display/intel_crtc.c

445

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

451

!HAS_DOUBLE_BUFFERED_LUT(display)) &&

drivers/gpu/drm/i915/display/intel_crtc.c

48

struct intel_crtc *intel_first_crtc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_crtc.c

50

return to_intel_crtc(drm_crtc_from_index(display->drm, 0));

drivers/gpu/drm/i915/display/intel_crtc.c

53

struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crtc.c

544

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_crtc.c

552

drm_WARN_ON(display->drm, new_crtc_state->use_dsb);

drivers/gpu/drm/i915/display/intel_crtc.c

58

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_crtc.c

580

if (drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base)))

drivers/gpu/drm/i915/display/intel_crtc.c

683

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_crtc.c

691

drm_WARN_ON(display->drm, new_crtc_state->use_dsb);

drivers/gpu/drm/i915/display/intel_crtc.c

702

if (DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/intel_crtc.c

71

void intel_wait_for_vblank_if_active(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crtc.c

74

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_crtc.c

755

if (intel_parent_vgpu_active(display))

drivers/gpu/drm/i915/display/intel_crtc.c

760

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_crtc.c

829

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

844

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_crtc.c

854

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

856

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_crtc.h

40

int intel_crtc_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_crtc.h

54

struct intel_crtc *intel_first_crtc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_crtc.h

55

struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crtc.h

57

void intel_wait_for_vblank_if_active(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

140

ilk_dump_csc(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

156

if (DISPLAY_VER(display) < 7)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

180

struct intel_display *display = to_intel_display(pipe_config);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

191

p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

265

intel_dump_infoframe(display, &pipe_config->infoframes.avi);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

268

intel_dump_infoframe(display, &pipe_config->infoframes.spd);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

271

intel_dump_infoframe(display, &pipe_config->infoframes.hdmi);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

274

intel_dump_infoframe(display, &pipe_config->infoframes.drm);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

277

intel_dump_infoframe(display, &pipe_config->infoframes.drm);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

330

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

337

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

352

intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

354

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

365

display->color.glk_linear_degamma_lut ? "(linear) " : "",

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

371

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

372

ilk_dump_csc(display, &p, "output csc", &pipe_config->output_csc);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

374

if (!HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

375

ilk_dump_csc(display, &p, "pipe csc", &pipe_config->csc);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

376

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

378

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

46

intel_dump_infoframe(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

52

hdmi_infoframe_log(KERN_DEBUG, display->drm->dev, frame);

drivers/gpu/drm/i915/display/intel_cursor.c

1003

intel_cursor_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cursor.c

1019

if (display->platform.i845g || display->platform.i865g) {

drivers/gpu/drm/i915/display/intel_cursor.c

1029

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_cursor.c

1031

else if (display->platform.i85x)

drivers/gpu/drm/i915/display/intel_cursor.c

1036

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_cursor.c

1047

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_cursor.c

1055

if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display))

drivers/gpu/drm/i915/display/intel_cursor.c

1058

modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE);

drivers/gpu/drm/i915/display/intel_cursor.c

1060

ret = drm_universal_plane_init(display->drm, &cursor->base,

drivers/gpu/drm/i915/display/intel_cursor.c

1073

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_cursor.c

108

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cursor.c

1081

zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1;

drivers/gpu/drm/i915/display/intel_cursor.c

1084

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_cursor.c

1097

void intel_cursor_mode_config_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cursor.c

1099

struct drm_mode_config *mode_config = &display->drm->mode_config;

drivers/gpu/drm/i915/display/intel_cursor.c

1101

if (display->platform.i845g) {

drivers/gpu/drm/i915/display/intel_cursor.c

1104

} else if (display->platform.i865g) {

drivers/gpu/drm/i915/display/intel_cursor.c

1107

} else if (display->platform.i830 || display->platform.i85x ||

drivers/gpu/drm/i915/display/intel_cursor.c

1108

display->platform.i915g || display->platform.i915gm) {

drivers/gpu/drm/i915/display/intel_cursor.c

122

if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) {

drivers/gpu/drm/i915/display/intel_cursor.c

140

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

148

drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n",

drivers/gpu/drm/i915/display/intel_cursor.c

229

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

244

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cursor.c

252

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_cursor.c

262

drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n",

drivers/gpu/drm/i915/display/intel_cursor.c

279

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

301

intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);

drivers/gpu/drm/i915/display/intel_cursor.c

302

intel_de_write_fw(display, CURBASE(display, PIPE_A), base);

drivers/gpu/drm/i915/display/intel_cursor.c

303

intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);

drivers/gpu/drm/i915/display/intel_cursor.c

304

intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);

drivers/gpu/drm/i915/display/intel_cursor.c

305

intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);

drivers/gpu/drm/i915/display/intel_cursor.c

311

intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);

drivers/gpu/drm/i915/display/intel_cursor.c

325

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

331

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_cursor.c

335

ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;

drivers/gpu/drm/i915/display/intel_cursor.c

339

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_cursor.c

371

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

373

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_cursor.c

381

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

385

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_cursor.c

394

if (DISPLAY_VER(display) < 5 && !display->platform.g4x)

drivers/gpu/drm/i915/display/intel_cursor.c

402

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

405

if (display->platform.sandybridge || display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_cursor.c

427

if (DISPLAY_VER(display) == 13)

drivers/gpu/drm/i915/display/intel_cursor.c

435

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

458

if (HAS_CUR_FBC(display) &&

drivers/gpu/drm/i915/display/intel_cursor.c

473

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

489

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cursor.c

497

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_cursor.c

502

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cursor.c

519

if (display->platform.cherryview && pipe == PIPE_C &&

drivers/gpu/drm/i915/display/intel_cursor.c

521

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cursor.c

536

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

542

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);

drivers/gpu/drm/i915/display/intel_cursor.c

550

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

558

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);

drivers/gpu/drm/i915/display/intel_cursor.c

560

intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe),

drivers/gpu/drm/i915/display/intel_cursor.c

569

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

580

intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);

drivers/gpu/drm/i915/display/intel_cursor.c

583

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);

drivers/gpu/drm/i915/display/intel_cursor.c

620

struct intel_display *display = to_intel_display(plane->base.dev);

drivers/gpu/drm/i915/display/intel_cursor.c

628

for (level = 0; level < display->wm.num_levels; level++)

drivers/gpu/drm/i915/display/intel_cursor.c

629

intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),

drivers/gpu/drm/i915/display/intel_cursor.c

632

intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),

drivers/gpu/drm/i915/display/intel_cursor.c

635

if (HAS_HW_SAGV_WM(display)) {

drivers/gpu/drm/i915/display/intel_cursor.c

638

intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),

drivers/gpu/drm/i915/display/intel_cursor.c

640

intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),

drivers/gpu/drm/i915/display/intel_cursor.c

644

intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),

drivers/gpu/drm/i915/display/intel_cursor.c

654

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

665

if (DISPLAY_VER(display) < 14 && width != height)

drivers/gpu/drm/i915/display/intel_cursor.c

692

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_cursor.c

703

if (HAS_CUR_FBC(display))

drivers/gpu/drm/i915/display/intel_cursor.c

704

intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl);

drivers/gpu/drm/i915/display/intel_cursor.c

705

intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl);

drivers/gpu/drm/i915/display/intel_cursor.c

706

intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);

drivers/gpu/drm/i915/display/intel_cursor.c

707

intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);

drivers/gpu/drm/i915/display/intel_cursor.c

713

intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);

drivers/gpu/drm/i915/display/intel_cursor.c

714

intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);

drivers/gpu/drm/i915/display/intel_cursor.c

728

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

740

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_cursor.c

744

val = intel_de_read(display, CURCNTR(display, plane->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

748

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_cursor.c

753

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_cursor.c

762

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

764

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

765

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

766

error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

773

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

775

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

776

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

811

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

86

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

915

if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {

drivers/gpu/drm/i915/display/intel_cursor.c

982

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_cursor.c

983

const struct drm_mode_config *config = &display->drm->mode_config;

drivers/gpu/drm/i915/display/intel_cursor.c

991

if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints)))

drivers/gpu/drm/i915/display/intel_cursor.h

15

intel_cursor_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cursor.h

20

void intel_cursor_mode_config_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

110

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

115

wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

123

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

127

intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

133

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

135

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

136

XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

142

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

146

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

149

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

152

drm_err_once(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

164

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

168

if (intel_de_wait_ms(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

172

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

176

if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

178

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

187

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

196

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2051

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2054

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2074

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2080

drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <

drivers/gpu/drm/i915/display/intel_cx0_phy.c

210

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2115

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2127

drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2140

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

216

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2164

drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&hw_state->cx0pll.c10));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

219

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2198

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2204

lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2221

max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2224

if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2242

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2244

return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

225

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2252

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2283

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2290

static void intel_c10_pll_program(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2369

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2374

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2377

} else if (display->platform.battlemage) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2379

} else if (display->platform.meteorlake_u ||

drivers/gpu/drm/i915/display/intel_cx0_phy.c

241

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2464

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2468

if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2470

if (DISPLAY_VERx100(display) == 1401)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2474

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2476

else if (DISPLAY_VERx100(display) == 1401)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

250

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

254

assert_dc_off(display);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2607

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2609

drm_WARN_ON(display->drm, vdr->custom_width & ~PHY_C20_CUSTOM_WIDTH_MASK);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2614

drm_WARN_ON(display->drm, vdr->serdes_rate & ~PHY_C20_SERDES_RATE_MASK);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2622

drm_WARN_ON(display->drm, vdr->hdmi_rate & ~PHY_C20_HDMI_RATE_MASK);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

264

drm_err_once(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2667

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2692

drm_WARN_ON(display->drm, is_dp != c20pll_state_is_dp(&hw_state->cx0pll.c20));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2762

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2781

PHY_C20_B_TX_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2785

PHY_C20_A_TX_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2793

PHY_C20_B_CMN_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2797

PHY_C20_A_CMN_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2806

PHY_C20_B_MPLLB_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

281

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2810

PHY_C20_A_MPLLB_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2818

PHY_C20_B_MPLLA_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2822

PHY_C20_A_MPLLA_CNTX_CFG(display, i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

287

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2886

static void intel_c20_pll_program(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

290

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2914

PHY_C20_A_TX_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2918

PHY_C20_B_TX_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2926

PHY_C20_A_CMN_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2930

PHY_C20_B_CMN_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2939

PHY_C20_A_MPLLB_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2943

PHY_C20_B_MPLLB_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2950

PHY_C20_A_MPLLA_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2954

PHY_C20_B_MPLLA_CNTX_CFG(display, i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

296

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2979

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2983

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2993

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2995

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3004

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3006

XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

303

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3035

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3038

i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3041

intel_de_rmw(display, buf_ctl2_reg,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3047

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3050

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3056

intel_de_rmw(display, buf_ctl2_reg,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

306

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3061

if (intel_de_wait_for_clear_ms(display, buf_ctl2_reg,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3064

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3071

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3074

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3077

intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3109

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3122

if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL1(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3125

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3129

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3132

if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3135

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3139

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3143

if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3147

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3155

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3157

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

316

} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3160

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

318

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3227

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3240

drm_WARN_ON(display->drm, lane_reversal && intel_tc_port_in_dp_alt_mode(dig_port));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3266

intel_c10_pll_program(display, encoder, &pll_state->c10);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3268

intel_c20_pll_program(display, encoder, &pll_state->c20);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3285

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3291

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3296

if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3300

drm_warn(display->drm, "Port %c PLL not locked\n",

drivers/gpu/drm/i915/display/intel_cx0_phy.c

331

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3333

bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3346

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3349

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3351

clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3353

drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3354

drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3355

drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3376

static int intel_mtl_tbt_clock_select(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3389

if (DISPLAY_VER(display) < 30) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3390

drm_WARN_ON(display->drm, "UHBR10 not supported for the platform\n");

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3395

if (DISPLAY_VER(display) < 30) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3396

drm_WARN_ON(display->drm, "UHBR20 not supported for the platform\n");

drivers/gpu/drm/i915/display/intel_cx0_phy.c

340

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3408

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3418

mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3419

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3420

intel_mtl_tbt_clock_select(display, port_clock));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3425

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3429

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

344

assert_dc_off(display);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3440

intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3443

if (intel_de_wait_for_set_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3445

drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3457

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3485

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3490

if (DISPLAY_VER(display) < 20 ||

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3517

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3522

if ((display->platform.battlemage && encoder->port == PORT_A) ||

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3523

(DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3531

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

354

drm_err_once(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3548

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3553

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3558

if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3562

drm_warn(display->drm, "Port %c PLL not unlocked\n",

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3571

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3572

XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3573

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3581

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3585

return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3591

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3602

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3606

if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3608

drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3619

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3620

XELPDP_DDI_CLOCK_SELECT_MASK(display) |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3624

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3644

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3651

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3652

clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

370

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

372

assert_dc_off(display);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3751

void intel_cx0_pll_power_save_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3755

if (DISPLAY_VER(display) != 30)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3758

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3776

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3781

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

38

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

384

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

387

assert_dc_off(display);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

41

if (display->platform.pantherlake) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

42

if (display->platform.pantherlake_wildcatlake)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

476

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

48

if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

491

if (drm_WARN_ON_ONCE(display->drm, !trans)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

79

assert_dc_off(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

83

enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

84

drm_WARN_ON(display->drm, !enabled);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

89

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

93

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

94

XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),

drivers/gpu/drm/i915/display/intel_cx0_phy.h

75

bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cx0_phy.h

80

void intel_cx0_pll_power_save_wa(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

201

#define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

203

#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

206

#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

103

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

104

unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

111

for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

120

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

141

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

149

int intel_dbuf_bw_min_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

155

for_each_dbuf_slice(display, slice) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

164

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

181

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

189

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

199

if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

214

if (intel_dbuf_bw_state_changed(display, old_dbuf_bw_state, new_dbuf_bw_state)) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

221

intel_dbuf_bw_min_cdclk(display, old_dbuf_bw_state),

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

222

intel_dbuf_bw_min_cdclk(display, new_dbuf_bw_state),

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

230

void intel_dbuf_bw_update_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

233

to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

236

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

239

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

249

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

251

to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

254

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

283

int intel_dbuf_bw_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

291

intel_atomic_global_obj_init(display, &display->dbuf_bw.obj,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

31

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

34

dbuf_bw_state = intel_atomic_get_old_global_obj_state(state, &display->dbuf_bw.obj);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

42

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

45

dbuf_bw_state = intel_atomic_get_new_global_obj_state(state, &display->dbuf_bw.obj);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

53

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

56

dbuf_bw_state = intel_atomic_get_global_obj_state(state, &display->dbuf_bw.obj);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

63

static bool intel_dbuf_bw_changed(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

69

for_each_dbuf_slice(display, slice) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

78

static bool intel_dbuf_bw_state_changed(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

84

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

90

if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))

drivers/gpu/drm/i915/display/intel_dbuf_bw.h

29

int intel_dbuf_bw_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dbuf_bw.h

32

int intel_dbuf_bw_min_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dbuf_bw.h

34

void intel_dbuf_bw_update_hw_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_ddi.c

1002

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_ddi.c

1011

intel_display_power_put(display, domain, wf);

drivers/gpu/drm/i915/display/intel_ddi.c

1017

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1025

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

1032

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

1033

dig_port->ddi_io_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_ddi.c

1043

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1051

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_ddi.c

1053

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

1058

intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_ddi.c

1063

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1070

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

1075

intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_ddi.c

1078

static void _skl_ddi_set_iboost(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi.c

1083

tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);

drivers/gpu/drm/i915/display/intel_ddi.c

1089

intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp);

drivers/gpu/drm/i915/display/intel_ddi.c

1096

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1110

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1118

drm_err(display->drm, "Invalid I_boost value %u\n", iboost);

drivers/gpu/drm/i915/display/intel_ddi.c

1122

_skl_ddi_set_iboost(display, encoder->port, iboost);

drivers/gpu/drm/i915/display/intel_ddi.c

1125

_skl_ddi_set_iboost(display, PORT_E, iboost);

drivers/gpu/drm/i915/display/intel_ddi.c

1131

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

1137

if (drm_WARN_ON(display->drm, n_entries < 1))

drivers/gpu/drm/i915/display/intel_ddi.c

1139

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

1172

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1179

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1187

intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val,

drivers/gpu/drm/i915/display/intel_ddi.c

119

static bool has_buf_trans_select(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_ddi.c

1192

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1199

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

drivers/gpu/drm/i915/display/intel_ddi.c

1205

intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),

drivers/gpu/drm/i915/display/intel_ddi.c

121

return DISPLAY_VER(display) < 10 && !display->platform.broxton;

drivers/gpu/drm/i915/display/intel_ddi.c

1217

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1228

intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1237

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

124

static bool has_iboost(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_ddi.c

1247

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1252

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);

drivers/gpu/drm/i915/display/intel_ddi.c

126

return DISPLAY_VER(display) == 9 && !display->platform.broxton;

drivers/gpu/drm/i915/display/intel_ddi.c

1262

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1268

intel_de_rmw(display, ICL_PORT_CL_DW5(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1272

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1274

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

drivers/gpu/drm/i915/display/intel_ddi.c

1280

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1282

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

drivers/gpu/drm/i915/display/intel_ddi.c

1288

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1297

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1301

intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1303

intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1313

intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1319

intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1330

intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1339

intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1355

intel_de_rmw(display, MG_CLKHUB(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1362

intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1369

intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

137

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1379

intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1381

intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),

drivers/gpu/drm/i915/display/intel_ddi.c

1389

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1398

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1405

if (display->platform.alderlake_p &&

drivers/gpu/drm/i915/display/intel_ddi.c

1406

IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {

drivers/gpu/drm/i915/display/intel_ddi.c

1411

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1414

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1419

intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1423

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1433

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

144

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1441

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1444

if (display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/intel_ddi.c

1460

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

1471

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

148

if (has_iboost(display) &&

drivers/gpu/drm/i915/display/intel_ddi.c

1484

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_ddi.c

1511

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1516

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1525

if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))

drivers/gpu/drm/i915/display/intel_ddi.c

153

intel_de_write(display, DDI_BUF_TRANS_LO(port, i),

drivers/gpu/drm/i915/display/intel_ddi.c

1535

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1541

if (has_iboost(display))

drivers/gpu/drm/i915/display/intel_ddi.c

155

intel_de_write(display, DDI_BUF_TRANS_HI(port, i),

drivers/gpu/drm/i915/display/intel_ddi.c

1550

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

drivers/gpu/drm/i915/display/intel_ddi.c

1556

intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

1557

intel_de_posting_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

1560

static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_ddi.c

1563

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1565

intel_de_rmw(display, reg, clk_sel_mask, clk_sel);

drivers/gpu/drm/i915/display/intel_ddi.c

1571

intel_de_rmw(display, reg, clk_off, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1573

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1576

static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_ddi.c

1579

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1581

intel_de_rmw(display, reg, 0, clk_off);

drivers/gpu/drm/i915/display/intel_ddi.c

1583

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1586

static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_ddi.c

1589

return !(intel_de_read(display, reg) & clk_off);

drivers/gpu/drm/i915/display/intel_ddi.c

1593

_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_ddi.c

1598

id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;

drivers/gpu/drm/i915/display/intel_ddi.c

1600

return intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_ddi.c

1606

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1610

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1613

_icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1621

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1624

_icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1630

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1633

return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1639

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1642

return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1650

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1654

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1657

_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1665

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1668

_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1674

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1677

return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

168

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1683

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1686

return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1694

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1698

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1705

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

1710

_icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1718

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1721

_icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1727

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1730

return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),

drivers/gpu/drm/i915/display/intel_ddi.c

1736

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1741

val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1754

return intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_ddi.c

176

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_ddi.c

1760

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1764

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1767

_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1775

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1778

_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1784

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1787

return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1793

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1796

return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

180

if (has_iboost(display) &&

drivers/gpu/drm/i915/display/intel_ddi.c

1804

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1808

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1815

intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);

drivers/gpu/drm/i915/display/intel_ddi.c

1822

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1827

intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);

drivers/gpu/drm/i915/display/intel_ddi.c

1832

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1836

tmp = intel_de_read(display, DDI_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

1847

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

185

intel_de_write(display, DDI_BUF_TRANS_LO(port, 9),

drivers/gpu/drm/i915/display/intel_ddi.c

1852

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1855

intel_de_write(display, DDI_CLK_SEL(port),

drivers/gpu/drm/i915/display/intel_ddi.c

1858

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1860

intel_de_rmw(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1863

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1868

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

187

intel_de_write(display, DDI_BUF_TRANS_HI(port, 9),

drivers/gpu/drm/i915/display/intel_ddi.c

1872

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1874

intel_de_rmw(display, ICL_DPCLKA_CFGCR0,

drivers/gpu/drm/i915/display/intel_ddi.c

1877

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1879

intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);

drivers/gpu/drm/i915/display/intel_ddi.c

1884

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1889

tmp = intel_de_read(display, DDI_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

1894

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/intel_ddi.c

1901

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1907

tmp = intel_de_read(display, DDI_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

191

static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

1926

return intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_ddi.c

193

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

1931

struct intel_display *display = to_intel_display(encoder->base.dev);

drivers/gpu/drm/i915/display/intel_ddi.c

194

return XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

1949

return intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_ddi.c

1955

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1959

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

1962

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1964

intel_de_rmw(display, DPLL_CTRL2,

drivers/gpu/drm/i915/display/intel_ddi.c

1970

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1975

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1978

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1980

intel_de_rmw(display, DPLL_CTRL2,

drivers/gpu/drm/i915/display/intel_ddi.c

1983

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1988

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

199

void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

1995

return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));

drivers/gpu/drm/i915/display/intel_ddi.c

2000

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2005

tmp = intel_de_read(display, DPLL_CTRL2);

drivers/gpu/drm/i915/display/intel_ddi.c

2017

return intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_ddi.c

2023

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2027

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

2030

intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));

drivers/gpu/drm/i915/display/intel_ddi.c

2035

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2038

intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);

drivers/gpu/drm/i915/display/intel_ddi.c

2043

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2046

return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;

drivers/gpu/drm/i915/display/intel_ddi.c

2051

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2056

tmp = intel_de_read(display, PORT_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

2084

return intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_ddi.c

209

if (display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_ddi.c

2102

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2122

if (drm_WARN_ON(display->drm, is_mst))

drivers/gpu/drm/i915/display/intel_ddi.c

2137

for_each_intel_encoder(display->drm, other_encoder) {

drivers/gpu/drm/i915/display/intel_ddi.c

2141

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

215

if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port),

drivers/gpu/drm/i915/display/intel_ddi.c

2156

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

2164

tgl_dkl_phy_check_and_rewrite(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi.c

2167

if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))

drivers/gpu/drm/i915/display/intel_ddi.c

2168

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);

drivers/gpu/drm/i915/display/intel_ddi.c

2169

if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))

drivers/gpu/drm/i915/display/intel_ddi.c

217

drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",

drivers/gpu/drm/i915/display/intel_ddi.c

2170

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2177

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2183

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

2190

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

2191

ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));

drivers/gpu/drm/i915/display/intel_ddi.c

2192

ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));

drivers/gpu/drm/i915/display/intel_ddi.c

2194

ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

2195

ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

2207

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

223

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2252

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

2253

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);

drivers/gpu/drm/i915/display/intel_ddi.c

2254

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2256

if (IS_DISPLAY_VER(display, 12, 13))

drivers/gpu/drm/i915/display/intel_ddi.c

2257

tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2260

intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);

drivers/gpu/drm/i915/display/intel_ddi.c

2261

intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);

drivers/gpu/drm/i915/display/intel_ddi.c

2277

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2279

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

2280

return TGL_DP_TP_CTL(display,

drivers/gpu/drm/i915/display/intel_ddi.c

2289

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2291

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

2292

return TGL_DP_TP_STATUS(display,

drivers/gpu/drm/i915/display/intel_ddi.c

2301

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2303

intel_de_write(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2310

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2312

if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2314

drm_err(display->drm, "Timed out waiting for ACT sent\n");

drivers/gpu/drm/i915/display/intel_ddi.c

2321

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2328

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

2337

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

234

if (DISPLAY_VER(display) < 10) {

drivers/gpu/drm/i915/display/intel_ddi.c

2344

drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",

drivers/gpu/drm/i915/display/intel_ddi.c

2350

drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");

drivers/gpu/drm/i915/display/intel_ddi.c

2355

struct intel_display *display = to_intel_display(aux->drm_dev);

drivers/gpu/drm/i915/display/intel_ddi.c

2367

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

2380

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2388

ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2391

ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2395

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

240

if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port),

drivers/gpu/drm/i915/display/intel_ddi.c

2416

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

242

drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",

drivers/gpu/drm/i915/display/intel_ddi.c

2423

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2426

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/intel_ddi.c

2434

drm_dbg_kms(display->drm, "Retry FEC enabling\n");

drivers/gpu/drm/i915/display/intel_ddi.c

2436

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2443

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2451

drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n");

drivers/gpu/drm/i915/display/intel_ddi.c

2457

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2462

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2464

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

2470

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2476

intel_combo_phy_power_up_lanes(display, phy, false,

drivers/gpu/drm/i915/display/intel_ddi.c

2486

static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_ddi.c

2488

if (DISPLAY_VER(display) > 20)

drivers/gpu/drm/i915/display/intel_ddi.c

2490

else if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_ddi.c

2499

struct intel_display *display = to_intel_display(pipe_config);

drivers/gpu/drm/i915/display/intel_ddi.c

2504

if (!HAS_MSO(display))

drivers/gpu/drm/i915/display/intel_ddi.c

2507

dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_ddi.c

2513

if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {

drivers/gpu/drm/i915/display/intel_ddi.c

2520

drm_WARN(display->drm, true,

drivers/gpu/drm/i915/display/intel_ddi.c

2536

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2541

if (!HAS_MSO(display))

drivers/gpu/drm/i915/display/intel_ddi.c

2553

intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),

drivers/gpu/drm/i915/display/intel_ddi.c

2561

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2567

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_ddi.c

2570

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_ddi.c

2575

reg = XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

2580

intel_de_rmw(display, reg, 0, set_bits);

drivers/gpu/drm/i915/display/intel_ddi.c

2582

ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100);

drivers/gpu/drm/i915/display/intel_ddi.c

2584

drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",

drivers/gpu/drm/i915/display/intel_ddi.c

2592

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2607

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),

drivers/gpu/drm/i915/display/intel_ddi.c

2614

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2620

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

drivers/gpu/drm/i915/display/intel_ddi.c

2747

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2792

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

2793

dig_port->ddi_io_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_ddi.c

2894

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2900

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_ddi.c

2901

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

2904

drm_WARN_ON(display->drm, is_mst && port == PORT_A);

drivers/gpu/drm/i915/display/intel_ddi.c

2921

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

2922

dig_port->ddi_io_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_ddi.c

2928

if (has_buf_trans_select(display))

drivers/gpu/drm/i915/display/intel_ddi.c

2944

if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&

drivers/gpu/drm/i915/display/intel_ddi.c

2961

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2963

if (HAS_DP20(display))

drivers/gpu/drm/i915/display/intel_ddi.c

2970

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

2972

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

2989

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2996

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

2997

dig_port->ddi_io_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3032

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_ddi.c

3036

drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3038

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_ddi.c

3061

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3067

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_ddi.c

3070

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_ddi.c

3075

reg = XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

3080

intel_de_rmw(display, reg, clr_bits, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

3082

ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100);

drivers/gpu/drm/i915/display/intel_ddi.c

3084

drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",

drivers/gpu/drm/i915/display/intel_ddi.c

3090

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3093

intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);

drivers/gpu/drm/i915/display/intel_ddi.c

3094

intel_de_posting_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

3102

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3105

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

3107

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

3108

intel_wait_ddi_buf_idle(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

3113

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

3119

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_ddi.c

3120

intel_wait_ddi_buf_idle(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

3130

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3147

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

3151

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3152

TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

3172

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

3181

intel_display_power_put(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3188

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

3189

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

drivers/gpu/drm/i915/display/intel_ddi.c

3198

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3206

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_ddi.c

3211

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

3216

intel_display_power_put(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3230

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3236

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_ddi.c

3252

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

3263

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_ddi.c

3269

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_ddi.c

3371

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3376

if (port == PORT_A && DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_ddi.c

3391

gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

3401

drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);

drivers/gpu/drm/i915/display/intel_ddi.c

3403

if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))

drivers/gpu/drm/i915/display/intel_ddi.c

3406

return CHICKEN_TRANS(display, trans[port]);

drivers/gpu/drm/i915/display/intel_ddi.c

3414

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3423

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

3427

if (has_buf_trans_select(display))

drivers/gpu/drm/i915/display/intel_ddi.c

3436

if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_ddi.c

3443

i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

3446

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_ddi.c

3455

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_ddi.c

3456

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_ddi.c

3467

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_ddi.c

3488

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_ddi.c

3496

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),

drivers/gpu/drm/i915/display/intel_ddi.c

3501

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_ddi.c

3503

} else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3504

drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port));

drivers/gpu/drm/i915/display/intel_ddi.c

3516

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3527

intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

3529

intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

3543

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,

drivers/gpu/drm/i915/display/intel_ddi.c

3554

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) {

drivers/gpu/drm/i915/display/intel_ddi.c

356

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3598

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3603

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

3667

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3673

if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)

drivers/gpu/drm/i915/display/intel_ddi.c

3676

for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

drivers/gpu/drm/i915/display/intel_ddi.c

369

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_ddi.c

3692

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3711

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_ddi.c

3718

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3723

intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),

drivers/gpu/drm/i915/display/intel_ddi.c

3730

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3739

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3741

drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);

drivers/gpu/drm/i915/display/intel_ddi.c

3753

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

3754

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

376

if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3766

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_ddi.c

3788

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3793

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3795

drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);

drivers/gpu/drm/i915/display/intel_ddi.c

3806

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

3807

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3809

if (display->platform.alderlake_p &&

drivers/gpu/drm/i915/display/intel_ddi.c

382

if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3821

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3825

temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3846

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);

drivers/gpu/drm/i915/display/intel_ddi.c

3852

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3856

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

3866

if (port == PORT_A && DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_ddi.c

3869

if (intel_de_wait_for_set_ms(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3872

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

3876

static bool intel_ddi_is_audio_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi.c

3882

if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO))

drivers/gpu/drm/i915/display/intel_ddi.c

3885

return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &

drivers/gpu/drm/i915/display/intel_ddi.c

389

static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

391

u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

drivers/gpu/drm/i915/display/intel_ddi.c

3915

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3917

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

3919

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

3921

else if (display->platform.jasperlake || display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_ddi.c

3923

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_ddi.c

3927

static enum transcoder bdw_transcoder_master_readout(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi.c

3932

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_ddi.c

3933

u32 ctl2 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3934

TRANS_DDI_FUNC_CTL2(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

3941

u32 ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3942

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

3958

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3964

bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3966

for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) {

drivers/gpu/drm/i915/display/intel_ddi.c

3971

trans_wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3977

if (bdw_transcoder_master_readout(display, cpu_transcoder) ==

drivers/gpu/drm/i915/display/intel_ddi.c

3981

intel_display_power_put(display, power_domain, trans_wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

3984

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

3993

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3996

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

4027

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4031

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

drivers/gpu/drm/i915/display/intel_ddi.c

4039

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4051

if (DISPLAY_VER(display) >= 12 &&

drivers/gpu/drm/i915/display/intel_ddi.c

4060

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

drivers/gpu/drm/i915/display/intel_ddi.c

4063

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_ddi.c

4065

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

4080

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4088

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

4094

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_ddi.c

4096

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

4106

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4110

ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4145

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {

drivers/gpu/drm/i915/display/intel_ddi.c

4151

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {

drivers/gpu/drm/i915/display/intel_ddi.c

4173

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4177

if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)))

drivers/gpu/drm/i915/display/intel_ddi.c

4185

intel_ddi_is_audio_enabled(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4192

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_ddi.c

4213

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_ddi.c

4229

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

423

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4234

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

4238

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4239

drm_WARN_ON(display->drm, !pll_active);

drivers/gpu/drm/i915/display/intel_ddi.c

4243

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_ddi.c

4270

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4276

pll = intel_get_dpll_by_id(display, pll_id);

drivers/gpu/drm/i915/display/intel_ddi.c

4278

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

4282

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4283

drm_WARN_ON(display->drm, !pll_active);

drivers/gpu/drm/i915/display/intel_ddi.c

4290

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_ddi.c

430

drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4305

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4308

mtl_port_to_pll_id(display, encoder->port));

drivers/gpu/drm/i915/display/intel_ddi.c

4314

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4321

mtl_port_to_pll_id(display, encoder->port));

drivers/gpu/drm/i915/display/intel_ddi.c

4365

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4368

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

4391

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4396

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_ddi.c

4407

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4408

drm_WARN_ON(display->drm, !pll_active);

drivers/gpu/drm/i915/display/intel_ddi.c

4413

crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);

drivers/gpu/drm/i915/display/intel_ddi.c

4415

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_ddi.c

4462

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4466

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",

drivers/gpu/drm/i915/display/intel_ddi.c

4501

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4506

if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)

drivers/gpu/drm/i915/display/intel_ddi.c

4521

if (display->platform.haswell && crtc->pipe == PIPE_A &&

drivers/gpu/drm/i915/display/intel_ddi.c

4527

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_ddi.c

453

drm_WARN_ON(display->drm, crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_ddi.c

4578

struct intel_display *display = to_intel_display(ref_crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4590

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_ddi.c

4622

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4633

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_ddi.c

4661

struct intel_display *display = to_intel_display(encoder->dev);

drivers/gpu/drm/i915/display/intel_ddi.c

4667

intel_display_power_flush_work(display);

drivers/gpu/drm/i915/display/intel_ddi.c

4705

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_ddi.c

4714

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

4732

privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL);

drivers/gpu/drm/i915/display/intel_ddi.c

4737

drm_warn(display->drm, "Error getting privacy-screen\n");

drivers/gpu/drm/i915/display/intel_ddi.c

4747

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

476

intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

4760

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

drivers/gpu/drm/i915/display/intel_ddi.c

4777

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

4793

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",

drivers/gpu/drm/i915/display/intel_ddi.c

4813

return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);

drivers/gpu/drm/i915/display/intel_ddi.c

4818

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4822

drm_WARN_ON(display->drm, !dig_port->dp.attached_connector);

drivers/gpu/drm/i915/display/intel_ddi.c

4885

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4886

u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];

drivers/gpu/drm/i915/display/intel_ddi.c

4888

return intel_de_read(display, SDEISR) & bit;

drivers/gpu/drm/i915/display/intel_ddi.c

4893

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4894

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

drivers/gpu/drm/i915/display/intel_ddi.c

4896

return intel_de_read(display, DEISR) & bit;

drivers/gpu/drm/i915/display/intel_ddi.c

4901

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4902

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

drivers/gpu/drm/i915/display/intel_ddi.c

4904

return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;

drivers/gpu/drm/i915/display/intel_ddi.c

492

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4933

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_ddi.c

4944

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_ddi.c

4953

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_ddi.c

4957

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_ddi.c

496

if (!HAS_DP20(display))

drivers/gpu/drm/i915/display/intel_ddi.c

4961

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

drivers/gpu/drm/i915/display/intel_ddi.c

4974

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

4983

static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

4993

static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5001

static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5009

static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5011

if (HAS_PCH_TGP(display))

drivers/gpu/drm/i915/display/intel_ddi.c

5012

return tgl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

502

intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_ddi.c

5020

static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5028

static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5033

if (HAS_PCH_TGP(display))

drivers/gpu/drm/i915/display/intel_ddi.c

5034

return icl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5039

static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5041

if (HAS_PCH_TGP(display))

drivers/gpu/drm/i915/display/intel_ddi.c

5042

return icl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5047

static bool intel_ddi_is_tc(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5049

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

5051

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_ddi.c

5094

static bool port_strap_detected(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5097

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_ddi.c

5102

return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5104

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5106

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5108

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5122

static bool assert_has_icl_dsi(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_ddi.c

5124

return !drm_WARN(display->drm, !display->platform.alderlake_p &&

drivers/gpu/drm/i915/display/intel_ddi.c

5125

!display->platform.tigerlake && DISPLAY_VER(display) != 11,

drivers/gpu/drm/i915/display/intel_ddi.c

5129

static bool port_in_use(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_ddi.c

5133

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_ddi.c

5142

static const char *intel_ddi_encoder_name(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi.c

5146

if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) {

drivers/gpu/drm/i915/display/intel_ddi.c

515

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

5150

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

5151

enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5158

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_ddi.c

5159

enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5170

drm_WARN_ON(display->drm, seq_buf_has_overflowed(s));

drivers/gpu/drm/i915/display/intel_ddi.c

5175

void intel_ddi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi.c

5190

if (!port_strap_detected(display, port)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5191

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

5196

if (!assert_port_valid(display, port))

drivers/gpu/drm/i915/display/intel_ddi.c

5199

if (port_in_use(display, port)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5200

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

5207

if (!assert_has_icl_dsi(display))

drivers/gpu/drm/i915/display/intel_ddi.c

5210

icl_dsi_init(display, devdata);

drivers/gpu/drm/i915/display/intel_ddi.c

5214

phy = intel_port_to_phy(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5222

if (intel_hti_uses_phy(display, phy)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5223

drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n",

drivers/gpu/drm/i915/display/intel_ddi.c

524

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

5240

drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n",

drivers/gpu/drm/i915/display/intel_ddi.c

5245

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

5251

if (intel_phy_is_snps(display, phy) &&

drivers/gpu/drm/i915/display/intel_ddi.c

5252

display->snps.phy_failed_calibration & BIT(phy)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5253

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

5265

drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs,

drivers/gpu/drm/i915/display/intel_ddi.c

5267

intel_ddi_encoder_name(display, port, phy, &encoder_name));

drivers/gpu/drm/i915/display/intel_ddi.c

5292

encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5297

if (HAS_LT_PHY(display)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5302

} else if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_ddi.c

5310

} else if (display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_ddi.c

5314

} else if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_ddi.c

5319

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_ddi.c

5324

} else if (display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_ddi.c

5329

} else if (display->platform.jasperlake || display->platform.elkhartlake) {

drivers/gpu/drm/i915/display/intel_ddi.c

5330

if (intel_ddi_is_tc(display, port)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5342

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_ddi.c

5343

if (intel_ddi_is_tc(display, port)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5355

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_ddi.c

5358

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_ddi.c

5363

} else if (display->platform.broadwell || display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_ddi.c

5370

if (HAS_LT_PHY(display)) {

drivers/gpu/drm/i915/display/intel_ddi.c

5372

} else if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_ddi.c

5374

} else if (display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_ddi.c

5376

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

5381

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_ddi.c

5386

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_ddi.c

5394

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_ddi.c

5395

encoder->hpd_pin = xelpd_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5396

else if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_ddi.c

5397

encoder->hpd_pin = dg1_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5398

else if (display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_ddi.c

5399

encoder->hpd_pin = rkl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5400

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_ddi.c

5401

encoder->hpd_pin = tgl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5402

else if (display->platform.jasperlake || display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_ddi.c

5403

encoder->hpd_pin = ehl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5404

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_ddi.c

5405

encoder->hpd_pin = icl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5406

else if (DISPLAY_VER(display) == 9 && !display->platform.broxton)

drivers/gpu/drm/i915/display/intel_ddi.c

5407

encoder->hpd_pin = skl_hpd_pin(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5411

ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

5416

dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;

drivers/gpu/drm/i915/display/intel_ddi.c

5445

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

5462

drm_WARN_ON(display->drm, port > PORT_I);

drivers/gpu/drm/i915/display/intel_ddi.c

5463

dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);

drivers/gpu/drm/i915/display/intel_ddi.c

5465

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_ddi.c

5470

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_ddi.c

5472

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_ddi.c

5474

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_ddi.c

5479

} else if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_ddi.c

5495

encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display);

drivers/gpu/drm/i915/display/intel_ddi.c

586

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_ddi.c

599

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

603

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

613

if (IS_DISPLAY_VER(display, 8, 10) &&

drivers/gpu/drm/i915/display/intel_ddi.c

628

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

631

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_ddi.c

643

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_ddi.c

644

TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

648

intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

662

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

670

intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

682

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

687

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_ddi.c

688

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_ddi.c

689

TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

692

ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

693

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

699

if (IS_DISPLAY_VER(display, 8, 10))

drivers/gpu/drm/i915/display/intel_ddi.c

703

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

712

intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

718

if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&

drivers/gpu/drm/i915/display/intel_ddi.c

720

drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");

drivers/gpu/drm/i915/display/intel_ddi.c

730

struct intel_display *display = to_intel_display(intel_encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

734

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_ddi.c

736

if (drm_WARN_ON(display->drm, !wakeref))

drivers/gpu/drm/i915/display/intel_ddi.c

739

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

741

intel_display_power_put(display, intel_encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

747

struct intel_display *display = to_intel_display(intel_connector);

drivers/gpu/drm/i915/display/intel_ddi.c

757

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_ddi.c

768

if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)

drivers/gpu/drm/i915/display/intel_ddi.c

773

ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

drivers/gpu/drm/i915/display/intel_ddi.c

779

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {

drivers/gpu/drm/i915/display/intel_ddi.c

784

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {

drivers/gpu/drm/i915/display/intel_ddi.c

790

} else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {

drivers/gpu/drm/i915/display/intel_ddi.c

798

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

806

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

816

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_ddi.c

821

tmp = intel_de_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

825

if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {

drivers/gpu/drm/i915/display/intel_ddi.c

826

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

827

TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/display/intel_ddi.c

848

for_each_pipe(display, p) {

drivers/gpu/drm/i915/display/intel_ddi.c

853

trans_wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_ddi.c

858

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi.c

866

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

867

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

868

intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_ddi.c

878

else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))

drivers/gpu/drm/i915/display/intel_ddi.c

885

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

908

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

916

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

924

if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) {

drivers/gpu/drm/i915/display/intel_ddi.c

925

tmp = intel_de_read(display, BXT_PHY_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

929

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_ddi.c

934

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

957

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_ddi.c

973

return intel_display_power_aux_io_domain(display, dig_port->aux_ch);

drivers/gpu/drm/i915/display/intel_ddi.c

974

else if (DISPLAY_VER(display) < 14 &&

drivers/gpu/drm/i915/display/intel_ddi.c

986

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_ddi.c

990

drm_WARN_ON(display->drm, dig_port->aux_wakeref);

drivers/gpu/drm/i915/display/intel_ddi.c

995

dig_port->aux_wakeref = intel_display_power_get(display, domain);

drivers/gpu/drm/i915/display/intel_ddi.h

56

void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_ddi.h

57

void intel_ddi_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1474

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1477

if (display->platform.tigerlake_uy) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1789

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1791

if (HAS_LT_PHY(display)) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1793

} else if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1798

} else if (display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1800

} else if (display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1805

} else if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1807

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1809

} else if (display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1811

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1816

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1817

if (display->platform.jasperlake)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1819

else if (display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1825

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1827

} else if (display->platform.cometlake_ulx ||

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1828

display->platform.coffeelake_ulx ||

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1829

display->platform.kabylake_ulx) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1831

} else if (display->platform.cometlake_ult ||

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1832

display->platform.coffeelake_ult ||

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1833

display->platform.kabylake_ult) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1835

} else if (display->platform.cometlake ||

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1836

display->platform.coffeelake ||

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1837

display->platform.kabylake) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1839

} else if (display->platform.skylake_ulx) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1841

} else if (display->platform.skylake_ult) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1843

} else if (display->platform.skylake) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1845

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1847

} else if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1850

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_de.h

101

intel_de_wait_us(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

107

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

109

ret = __intel_wait_for_register(__to_uncore(display), reg, mask,

drivers/gpu/drm/i915/display/intel_de.h

112

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

118

intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

124

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

126

ret = __intel_wait_for_register(__to_uncore(display), reg, mask,

drivers/gpu/drm/i915/display/intel_de.h

129

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

135

intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

139

return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,

drivers/gpu/drm/i915/display/intel_de.h

144

intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

148

return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,

drivers/gpu/drm/i915/display/intel_de.h

15

static inline struct intel_uncore *__to_uncore(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_de.h

153

intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

156

return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);

drivers/gpu/drm/i915/display/intel_de.h

160

intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

163

return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);

drivers/gpu/drm/i915/display/intel_de.h

167

intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

17

return to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_de.h

170

return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);

drivers/gpu/drm/i915/display/intel_de.h

174

intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,

drivers/gpu/drm/i915/display/intel_de.h

177

return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);

drivers/gpu/drm/i915/display/intel_de.h

189

intel_de_read_fw(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_de.h

193

val = intel_uncore_read_fw(__to_uncore(display), reg);

drivers/gpu/drm/i915/display/intel_de.h

200

intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)

drivers/gpu/drm/i915/display/intel_de.h

203

intel_uncore_write_fw(__to_uncore(display), reg, val);

drivers/gpu/drm/i915/display/intel_de.h

207

intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)

drivers/gpu/drm/i915/display/intel_de.h

21

intel_de_read(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_de.h

211

old = intel_de_read_fw(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

213

intel_de_write_fw(display, reg, val);

drivers/gpu/drm/i915/display/intel_de.h

219

intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_de.h

221

return intel_uncore_read_notrace(__to_uncore(display), reg);

drivers/gpu/drm/i915/display/intel_de.h

225

intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)

drivers/gpu/drm/i915/display/intel_de.h

227

intel_uncore_write_notrace(__to_uncore(display), reg, val);

drivers/gpu/drm/i915/display/intel_de.h

231

intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,

drivers/gpu/drm/i915/display/intel_de.h

237

intel_de_write_fw(display, reg, val);

drivers/gpu/drm/i915/display/intel_de.h

25

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

27

val = intel_uncore_read(__to_uncore(display), reg);

drivers/gpu/drm/i915/display/intel_de.h

29

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

35

intel_de_read8(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_de.h

39

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

41

val = intel_uncore_read8(__to_uncore(display), reg);

drivers/gpu/drm/i915/display/intel_de.h

43

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

49

intel_de_read64_2x32(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_de.h

54

intel_dmc_wl_get(display, lower_reg);

drivers/gpu/drm/i915/display/intel_de.h

55

intel_dmc_wl_get(display, upper_reg);

drivers/gpu/drm/i915/display/intel_de.h

57

val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,

drivers/gpu/drm/i915/display/intel_de.h

60

intel_dmc_wl_put(display, upper_reg);

drivers/gpu/drm/i915/display/intel_de.h

61

intel_dmc_wl_put(display, lower_reg);

drivers/gpu/drm/i915/display/intel_de.h

67

intel_de_posting_read(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_de.h

69

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

71

intel_uncore_posting_read(__to_uncore(display), reg);

drivers/gpu/drm/i915/display/intel_de.h

73

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

77

intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)

drivers/gpu/drm/i915/display/intel_de.h

79

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

81

intel_uncore_write(__to_uncore(display), reg, val);

drivers/gpu/drm/i915/display/intel_de.h

83

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

87

intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)

drivers/gpu/drm/i915/display/intel_de.h

91

intel_dmc_wl_get(display, reg);

drivers/gpu/drm/i915/display/intel_de.h

93

val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);

drivers/gpu/drm/i915/display/intel_de.h

95

intel_dmc_wl_put(display, reg);

drivers/gpu/drm/i915/display/intel_display.c

1017

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

1024

intel_frontbuffer_flip(display, new_crtc_state->fb_bits);

drivers/gpu/drm/i915/display/intel_display.c

1027

intel_update_watermarks(display);

drivers/gpu/drm/i915/display/intel_display.c

1033

intel_async_flip_vtd_wa(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1037

skl_wa_827(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1041

icl_wa_scalerclkgating(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1045

icl_wa_cursorclkgating(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1053

if (intel_display_wa(display, 14011503117)) {

drivers/gpu/drm/i915/display/intel_display.c

1148

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

1180

intel_async_flip_vtd_wa(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1185

skl_wa_827(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1190

icl_wa_scalerclkgating(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1195

icl_wa_cursorclkgating(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1206

if (HAS_GMCH(display) && old_crtc_state->hw.active &&

drivers/gpu/drm/i915/display/intel_display.c

1207

new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))

drivers/gpu/drm/i915/display/intel_display.c

1217

if (!HAS_GMCH(display) && old_crtc_state->hw.active &&

drivers/gpu/drm/i915/display/intel_display.c

1218

new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))

drivers/gpu/drm/i915/display/intel_display.c

1242

intel_update_watermarks(display);

drivers/gpu/drm/i915/display/intel_display.c

1253

if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

1254

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1267

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

1289

intel_frontbuffer_flip(display, fb_bits);

drivers/gpu/drm/i915/display/intel_display.c

1294

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

1303

if (display->dpll.mgr) {

drivers/gpu/drm/i915/display/intel_display.c

1493

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

1498

if (drm_WARN_ON(display->drm, crtc->active))

drivers/gpu/drm/i915/display/intel_display.c

1511

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1512

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

152

skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)

drivers/gpu/drm/i915/display/intel_display.c

1525

assert_fdi_tx_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

1526

assert_fdi_rx_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

154

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

drivers/gpu/drm/i915/display/intel_display.c

1547

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_display.c

1560

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1561

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1567

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1569

return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;

drivers/gpu/drm/i915/display/intel_display.c

1574

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

1577

intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),

drivers/gpu/drm/i915/display/intel_display.c

1583

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1586

intel_de_write(display, WM_LINETIME(crtc->pipe),

drivers/gpu/drm/i915/display/intel_display.c

1593

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1595

intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

1602

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

161

icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_display.c

1619

intel_de_write(display, TRANS_MULT(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

1630

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

1637

if (drm_WARN_ON(display->drm, crtc->active))

drivers/gpu/drm/i915/display/intel_display.c

1639

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

164

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

drivers/gpu/drm/i915/display/intel_display.c

1653

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

1659

if (HAS_UNCOMPRESSED_JOINER(display))

drivers/gpu/drm/i915/display/intel_display.c

1664

if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_display.c

1671

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

1680

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display.c

1693

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display.c

1701

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

171

icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_display.c

1716

if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {

drivers/gpu/drm/i915/display/intel_display.c

1718

intel_crtc_for_pipe(display, hsw_workaround_pipe);

drivers/gpu/drm/i915/display/intel_display.c

1729

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

1739

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

174

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

drivers/gpu/drm/i915/display/intel_display.c

1740

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

1758

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1759

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

1765

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

1782

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

1791

bool intel_phy_is_combo(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_display.c

1795

else if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_display.c

1797

else if (display->platform.dg1 || display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_display.c

1799

else if (display->platform.jasperlake || display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_display.c

1801

else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))

drivers/gpu/drm/i915/display/intel_display.c

1823

bool intel_phy_is_tc(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_display.c

1829

if (display->platform.dgfx)

drivers/gpu/drm/i915/display/intel_display.c

1832

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_display.c

1834

else if (display->platform.tigerlake)

drivers/gpu/drm/i915/display/intel_display.c

1836

else if (display->platform.icelake)

drivers/gpu/drm/i915/display/intel_display.c

1843

bool intel_phy_is_snps(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_display.c

1849

return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;

drivers/gpu/drm/i915/display/intel_display.c

1853

enum phy intel_port_to_phy(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display.c

1855

if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)

drivers/gpu/drm/i915/display/intel_display.c

1857

else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)

drivers/gpu/drm/i915/display/intel_display.c

1859

else if (display->platform.alderlake_s && port >= PORT_TC1)

drivers/gpu/drm/i915/display/intel_display.c

1861

else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)

drivers/gpu/drm/i915/display/intel_display.c

1863

else if ((display->platform.jasperlake || display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_display.c

1876

enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display.c

1878

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display.c

1889

enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display.c

1891

if (!intel_phy_is_tc(display, intel_port_to_phy(display, port)))

drivers/gpu/drm/i915/display/intel_display.c

1894

return intel_port_to_tc(display, port);

drivers/gpu/drm/i915/display/intel_display.c

1899

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

1901

return intel_port_to_phy(display, encoder->port);

drivers/gpu/drm/i915/display/intel_display.c

1906

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

1908

return intel_phy_is_combo(display, intel_encoder_to_phy(encoder));

drivers/gpu/drm/i915/display/intel_display.c

1913

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

1915

return intel_phy_is_snps(display, intel_encoder_to_phy(encoder));

drivers/gpu/drm/i915/display/intel_display.c

1920

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

1926

return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));

drivers/gpu/drm/i915/display/intel_display.c

1931

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

1933

return intel_tc_phy_port_to_tc(display, encoder->port);

drivers/gpu/drm/i915/display/intel_display.c

1939

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_display.c

1942

return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);

drivers/gpu/drm/i915/display/intel_display.c

1944

return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

drivers/gpu/drm/i915/display/intel_display.c

1950

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1967

drm_for_each_encoder_mask(encoder, display->drm,

drivers/gpu/drm/i915/display/intel_display.c

1974

if (HAS_DDI(display) && crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_display.c

1987

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2004

intel_display_power_get_in_set(display,

drivers/gpu/drm/i915/display/intel_display.c

2012

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2014

intel_display_power_put_mask_in_set(display,

drivers/gpu/drm/i915/display/intel_display.c

2039

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2044

if (drm_WARN_ON(display->drm, crtc->active))

drivers/gpu/drm/i915/display/intel_display.c

2051

intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0);

drivers/gpu/drm/i915/display/intel_display.c

2053

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_display.c

2054

intel_de_write(display, CHV_BLEND(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

2056

intel_de_write(display, CHV_CANVAS(display, pipe), 0);

drivers/gpu/drm/i915/display/intel_display.c

2061

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

2065

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

2087

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2092

if (drm_WARN_ON(display->drm, crtc->active))

drivers/gpu/drm/i915/display/intel_display.c

2101

if (DISPLAY_VER(display) != 2)

drivers/gpu/drm/i915/display/intel_display.c

2102

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

2113

intel_update_watermarks(display);

drivers/gpu/drm/i915/display/intel_display.c

2121

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_display.c

2128

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

2137

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_display.c

2151

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

2152

chv_disable_pll(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

2153

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_display.c

2154

vlv_disable_pll(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

2161

if (DISPLAY_VER(display) != 2)

drivers/gpu/drm/i915/display/intel_display.c

2162

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

2164

if (!display->funcs.wm->initial_watermarks)

drivers/gpu/drm/i915/display/intel_display.c

2165

intel_update_watermarks(display);

drivers/gpu/drm/i915/display/intel_display.c

2168

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_display.c

2169

i830_enable_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

2182

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2185

return HAS_DOUBLE_WIDE(display) &&

drivers/gpu/drm/i915/display/intel_display.c

2186

(crtc->pipe == PIPE_A || display->platform.i915g);

drivers/gpu/drm/i915/display/intel_display.c

2233

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2235

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display.c

2346

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2359

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

2366

intel_is_dual_link_lvds(display)) {

drivers/gpu/drm/i915/display/intel_display.c

2367

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

2379

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2383

int clock_limit = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_display.c

2398

if (DISPLAY_VER(display) < 4) {

drivers/gpu/drm/i915/display/intel_display.c

2399

clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;

drivers/gpu/drm/i915/display/intel_display.c

2407

clock_limit = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_display.c

2413

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

2426

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2429

if (!HAS_DSB(display))

drivers/gpu/drm/i915/display/intel_display.c

2441

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

2453

drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n",

drivers/gpu/drm/i915/display/intel_display.c

2549

void intel_panel_sanitize_ssc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

2557

if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_display.c

2558

bool bios_lvds_use_ssc = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2562

if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {

drivers/gpu/drm/i915/display/intel_display.c

2563

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

2566

str_enabled_disabled(display->vbt.lvds_use_ssc));

drivers/gpu/drm/i915/display/intel_display.c

2567

display->vbt.lvds_use_ssc = bios_lvds_use_ssc;

drivers/gpu/drm/i915/display/intel_display.c

2579

void intel_set_m_n(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

2584

intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);

drivers/gpu/drm/i915/display/intel_display.c

2585

intel_de_write(display, data_n_reg, m_n->data_n);

drivers/gpu/drm/i915/display/intel_display.c

2586

intel_de_write(display, link_m_reg, m_n->link_m);

drivers/gpu/drm/i915/display/intel_display.c

2591

intel_de_write(display, link_n_reg, m_n->link_n);

drivers/gpu/drm/i915/display/intel_display.c

2594

bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

2597

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display.c

2600

return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;

drivers/gpu/drm/i915/display/intel_display.c

2607

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2610

if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_display.c

2611

intel_set_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_display.c

2612

PIPE_DATA_M1(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2613

PIPE_DATA_N1(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2614

PIPE_LINK_M1(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2615

PIPE_LINK_N1(display, transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2617

intel_set_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_display.c

2626

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2628

if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))

drivers/gpu/drm/i915/display/intel_display.c

2631

intel_set_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_display.c

2632

PIPE_DATA_M2(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2633

PIPE_DATA_N2(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2634

PIPE_LINK_M2(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2635

PIPE_LINK_N2(display, transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2641

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2644

return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);

drivers/gpu/drm/i915/display/intel_display.c

2649

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2657

drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2684

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_display.c

2685

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_display.c

2686

TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2694

} else if (DISPLAY_VER(display) == 12) {

drivers/gpu/drm/i915/display/intel_display.c

2699

if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)

drivers/gpu/drm/i915/display/intel_display.c

2700

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_display.c

2701

TRANS_VSYNCSHIFT(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2704

intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2707

intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2710

intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2720

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_display.c

2723

intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2726

intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2729

intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2737

if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&

drivers/gpu/drm/i915/display/intel_display.c

2739

intel_de_write(display, TRANS_VTOTAL(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

2743

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_display.c

2752

intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2759

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2764

drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2777

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_display.c

2778

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_display.c

2779

TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2787

} else if (DISPLAY_VER(display) == 12) {

drivers/gpu/drm/i915/display/intel_display.c

2796

intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2805

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_display.c

2812

intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

2822

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2831

intel_de_write(display, PIPESRC(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

2837

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2840

if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/intel_display.c

2843

if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_display.c

2844

display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display.c

2845

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2846

TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;

drivers/gpu/drm/i915/display/intel_display.c

2848

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2849

TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;

drivers/gpu/drm/i915/display/intel_display.c

2855

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2860

tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2865

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2866

TRANS_HBLANK(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2871

tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2875

tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2881

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2882

TRANS_VBLANK(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2886

tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2896

if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {

drivers/gpu/drm/i915/display/intel_display.c

2898

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2899

TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2903

} else if (DISPLAY_VER(display) == 12) {

drivers/gpu/drm/i915/display/intel_display.c

2915

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_display.c

2916

pipe_config->min_hblank = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2940

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

2943

tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

2954

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2963

if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2970

if (display->platform.g4x || display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_display.c

2971

display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_display.c

2995

if (DISPLAY_VER(display) < 4 ||

drivers/gpu/drm/i915/display/intel_display.c

3004

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_display.c

3015

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_display.c

3016

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3022

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3025

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

3033

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/intel_display.c

3034

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3048

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3056

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_display.c

3060

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3069

if (display->platform.g4x || display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_display.c

3070

display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_display.c

3087

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_display.c

3095

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_display.c

3101

if (HAS_DOUBLE_WIDE(display))

drivers/gpu/drm/i915/display/intel_display.c

3111

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_display.c

3116

} else if (display->platform.i945g || display->platform.i945gm ||

drivers/gpu/drm/i915/display/intel_display.c

3117

display->platform.g33 || display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_display.c

3129

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

3131

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_display.c

3147

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_display.c

3154

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3196

drm_WARN_ON(display->drm, crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_display.c

3211

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_display.c

3212

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3217

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3228

if (display->platform.haswell && crtc_state->dither)

drivers/gpu/drm/i915/display/intel_display.c

3231

if (DISPLAY_VER(display) < 35) {

drivers/gpu/drm/i915/display/intel_display.c

3238

if (display->platform.haswell &&

drivers/gpu/drm/i915/display/intel_display.c

3242

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_display.c

3243

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3249

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3265

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_display.c

3281

val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :

drivers/gpu/drm/i915/display/intel_display.c

3284

if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

3287

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display.c

3291

if (display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_display.c

3294

intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);

drivers/gpu/drm/i915/display/intel_display.c

3299

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3302

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

3322

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_display.c

3342

void intel_get_m_n(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

3347

m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3348

m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3349

m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3350

m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3351

m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;

drivers/gpu/drm/i915/display/intel_display.c

3358

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3361

if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_display.c

3362

intel_get_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_display.c

3363

PIPE_DATA_M1(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3364

PIPE_DATA_N1(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3365

PIPE_LINK_M1(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3366

PIPE_LINK_N1(display, transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3368

intel_get_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_display.c

3377

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3379

if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))

drivers/gpu/drm/i915/display/intel_display.c

3382

intel_get_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_display.c

3383

PIPE_DATA_M2(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3384

PIPE_DATA_N2(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3385

PIPE_LINK_M2(display, transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3386

PIPE_LINK_N2(display, transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3392

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3400

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_display.c

3404

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

343

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

346

return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

3462

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_display.c

3467

static u8 joiner_pipes(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

3471

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display.c

3473

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display.c

3478

return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;

drivers/gpu/drm/i915/display/intel_display.c

3481

static bool transcoder_ddi_func_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

3489

with_intel_display_power_if_enabled(display, power_domain)

drivers/gpu/drm/i915/display/intel_display.c

3490

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3491

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3496

static void enabled_uncompressed_joiner_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

3504

if (!HAS_UNCOMPRESSED_JOINER(display))

drivers/gpu/drm/i915/display/intel_display.c

3507

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

drivers/gpu/drm/i915/display/intel_display.c

3508

joiner_pipes(display)) {

drivers/gpu/drm/i915/display/intel_display.c

3513

with_intel_display_power_if_enabled(display, power_domain) {

drivers/gpu/drm/i915/display/intel_display.c

3514

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_display.c

3524

static void enabled_bigjoiner_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

3532

if (!HAS_BIGJOINER(display))

drivers/gpu/drm/i915/display/intel_display.c

3535

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

drivers/gpu/drm/i915/display/intel_display.c

3536

joiner_pipes(display)) {

drivers/gpu/drm/i915/display/intel_display.c

354

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3541

with_intel_display_power_if_enabled(display, power_domain) {

drivers/gpu/drm/i915/display/intel_display.c

3542

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_display.c

357

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_display.c

3593

static void enabled_ultrajoiner_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

3601

if (!HAS_ULTRAJOINER(display))

drivers/gpu/drm/i915/display/intel_display.c

3604

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

drivers/gpu/drm/i915/display/intel_display.c

3605

joiner_pipes(display)) {

drivers/gpu/drm/i915/display/intel_display.c

361

if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

3610

with_intel_display_power_if_enabled(display, power_domain) {

drivers/gpu/drm/i915/display/intel_display.c

3611

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_display.c

3624

static void enabled_joiner_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

363

drm_WARN(display->drm, 1, "pipe_off wait timed out\n");

drivers/gpu/drm/i915/display/intel_display.c

3635

enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes,

drivers/gpu/drm/i915/display/intel_display.c

3642

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3649

drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);

drivers/gpu/drm/i915/display/intel_display.c

3651

enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes,

drivers/gpu/drm/i915/display/intel_display.c

3654

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3657

enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes,

drivers/gpu/drm/i915/display/intel_display.c

3660

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3668

drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,

drivers/gpu/drm/i915/display/intel_display.c

3672

drm_WARN(display->drm, secondary_ultrajoiner_pipes !=

drivers/gpu/drm/i915/display/intel_display.c

3678

drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,

drivers/gpu/drm/i915/display/intel_display.c

3682

drm_WARN(display->drm, secondary_bigjoiner_pipes !=

drivers/gpu/drm/i915/display/intel_display.c

3688

drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=

drivers/gpu/drm/i915/display/intel_display.c

369

void assert_transcoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

3702

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3717

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3732

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3743

static u8 hsw_panel_transcoders(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

3747

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display.c

3755

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3756

u8 panel_transcoder_mask = hsw_panel_transcoders(display);

drivers/gpu/drm/i915/display/intel_display.c

3765

for_each_cpu_transcoder_masked(display, cpu_transcoder,

drivers/gpu/drm/i915/display/intel_display.c

377

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_display.c

3772

with_intel_display_power_if_enabled(display, power_domain)

drivers/gpu/drm/i915/display/intel_display.c

3773

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3774

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3781

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_display.c

3806

if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))

drivers/gpu/drm/i915/display/intel_display.c

381

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_display.c

3810

enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);

drivers/gpu/drm/i915/display/intel_display.c

3813

if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))

drivers/gpu/drm/i915/display/intel_display.c

383

u32 val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3838

static void assert_enabled_transcoders(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

384

TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3842

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3848

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

3857

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3865

assert_enabled_transcoders(display, enabled_transcoders);

drivers/gpu/drm/i915/display/intel_display.c

387

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_display.c

3874

if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,

drivers/gpu/drm/i915/display/intel_display.c

3878

if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {

drivers/gpu/drm/i915/display/intel_display.c

3879

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3880

TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3886

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3887

TRANSCONF(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3896

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3907

if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,

drivers/gpu/drm/i915/display/intel_display.c

3918

if (!bxt_dsi_pll_is_enabled(display))

drivers/gpu/drm/i915/display/intel_display.c

392

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_display.c

3922

tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));

drivers/gpu/drm/i915/display/intel_display.c

3926

tmp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/intel_display.c

3939

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3944

enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes);

drivers/gpu/drm/i915/display/intel_display.c

3955

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

3959

if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,

drivers/gpu/drm/i915/display/intel_display.c

3965

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/intel_display.c

3967

drm_WARN_ON(display->drm, active);

drivers/gpu/drm/i915/display/intel_display.c

3979

tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3992

DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display.c

400

struct intel_display *display = to_intel_display(plane->base.dev);

drivers/gpu/drm/i915/display/intel_display.c

4000

if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display.c

4001

u32 tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

4002

TRANSCONF(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

4017

tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

4019

if (display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display.c

4023

if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,

drivers/gpu/drm/i915/display/intel_display.c

4025

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display.c

4036

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

4037

TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;

drivers/gpu/drm/i915/display/intel_display.c

4043

intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);

drivers/gpu/drm/i915/display/intel_display.c

4050

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4053

if (!display->funcs.display->get_pipe_config(crtc, crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

406

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_display.c

4113

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

4122

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

417

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

420

for_each_intel_plane_on_crtc(display->drm, crtc, plane)

drivers/gpu/drm/i915/display/intel_display.c

4212

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4224

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/intel_display.c

4225

skl_watermark_ipc_enabled(display))

drivers/gpu/drm/i915/display/intel_display.c

4234

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

4239

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display.c

426

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4260

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

4265

if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&

drivers/gpu/drm/i915/display/intel_display.c

4282

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

4292

if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_display.c

4306

if (HAS_IPS(display)) {

drivers/gpu/drm/i915/display/intel_display.c

4312

if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_display.c

4313

display->platform.broadwell || display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display.c

432

drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));

drivers/gpu/drm/i915/display/intel_display.c

4331

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4355

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

4374

int intel_display_max_pipe_bpp(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

4376

if (display->platform.g4x || display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_display.c

4377

display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

4379

else if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_display.c

4389

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

4396

crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);

drivers/gpu/drm/i915/display/intel_display.c

441

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/intel_display.c

4415

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

4426

drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display.c

443

assert_dsi_pll_enabled(display);

drivers/gpu/drm/i915/display/intel_display.c

4433

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_display.c

4449

drm_WARN_ON(display->drm, !connector_state->crtc);

drivers/gpu/drm/i915/display/intel_display.c

445

assert_pll_enabled(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

4453

if (drm_WARN_ON(display->drm, !HAS_DDI(display)))

drivers/gpu/drm/i915/display/intel_display.c

449

assert_fdi_rx_pll_enabled(display,

drivers/gpu/drm/i915/display/intel_display.c

451

assert_fdi_tx_pll_enabled(display,

drivers/gpu/drm/i915/display/intel_display.c

458

if (DISPLAY_VER(display) == 13)

drivers/gpu/drm/i915/display/intel_display.c

459

intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

4601

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

462

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_display.c

4634

if (display->platform.g4x ||

drivers/gpu/drm/i915/display/intel_display.c

4635

display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

4651

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

466

if (DISPLAY_VER(display) == 14)

drivers/gpu/drm/i915/display/intel_display.c

4684

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

469

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

4714

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

473

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

4756

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",

drivers/gpu/drm/i915/display/intel_display.c

476

drm_WARN_ON(display->drm, !display->platform.i830);

drivers/gpu/drm/i915/display/intel_display.c

4772

drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",

drivers/gpu/drm/i915/display/intel_display.c

4783

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

481

if (DISPLAY_VER(display) >= 13 &&

drivers/gpu/drm/i915/display/intel_display.c

488

intel_de_write(display, TRANSCONF(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

490

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

4913

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

4928

hdmi_infoframe_log(loglevel, display->drm->dev, a);

drivers/gpu/drm/i915/display/intel_display.c

4930

hdmi_infoframe_log(loglevel, display->drm->dev, b);

drivers/gpu/drm/i915/display/intel_display.c

4999

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

5004

intel_dpll_dump_hw_state(display, p, a);

drivers/gpu/drm/i915/display/intel_display.c

5006

intel_dpll_dump_hw_state(display, p, b);

drivers/gpu/drm/i915/display/intel_display.c

5011

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5023

return HAS_LRR(display) &&

drivers/gpu/drm/i915/display/intel_display.c

5024

(old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&

drivers/gpu/drm/i915/display/intel_display.c

5035

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

5041

intel_lt_phy_dump_hw_state(display, a);

drivers/gpu/drm/i915/display/intel_display.c

5043

intel_lt_phy_dump_hw_state(display, b);

drivers/gpu/drm/i915/display/intel_display.c

505

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5051

struct intel_display *display = to_intel_display(current_config);

drivers/gpu/drm/i915/display/intel_display.c

5058

p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);

drivers/gpu/drm/i915/display/intel_display.c

5060

p = drm_err_printer(display->drm, NULL);

drivers/gpu/drm/i915/display/intel_display.c

511

drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));

drivers/gpu/drm/i915/display/intel_display.c

5151

if (!intel_dpll_compare_hw_state(display, &current_config->name, \

drivers/gpu/drm/i915/display/intel_display.c

519

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

5295

if (HAS_DOUBLE_BUFFERED_M_N(display)) {

drivers/gpu/drm/i915/display/intel_display.c

531

if (!display->platform.i830)

drivers/gpu/drm/i915/display/intel_display.c

5329

if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||

drivers/gpu/drm/i915/display/intel_display.c

5330

display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

5346

if (DISPLAY_VER(display) < 4)

drivers/gpu/drm/i915/display/intel_display.c

535

if (DISPLAY_VER(display) >= 13 &&

drivers/gpu/drm/i915/display/intel_display.c

5369

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display.c

5389

if (display->dpll.mgr)

drivers/gpu/drm/i915/display/intel_display.c

539

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_display.c

5393

if (display->dpll.mgr || HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display.c

5397

if (HAS_LT_PHY(display))

drivers/gpu/drm/i915/display/intel_display.c

5403

if (display->platform.g4x || DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_display.c

541

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display.c

542

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

549

u32 intel_plane_fb_max_stride(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

5493

if (!fastset || intel_vrr_always_use_vrr_tg(display)) {

drivers/gpu/drm/i915/display/intel_display.c

5531

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5535

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",

drivers/gpu/drm/i915/display/intel_display.c

5575

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5578

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {

drivers/gpu/drm/i915/display/intel_display.c

561

crtc = intel_first_crtc(display);

drivers/gpu/drm/i915/display/intel_display.c

5622

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5625

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_display.c

5651

int intel_modeset_commit_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

5659

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_display.c

5666

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

drivers/gpu/drm/i915/display/intel_display.c

574

struct intel_display *display = to_intel_display(drm);

drivers/gpu/drm/i915/display/intel_display.c

576

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display.c

5782

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5786

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display.c

579

return intel_plane_fb_max_stride(display,

drivers/gpu/drm/i915/display/intel_display.c

5807

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5815

drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",

drivers/gpu/drm/i915/display/intel_display.c

5838

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5848

drm_dbg_atomic(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

5895

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5904

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

5908

if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {

drivers/gpu/drm/i915/display/intel_display.c

5909

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

5913

primary_crtc_state->joiner_pipes, joiner_pipes(display));

drivers/gpu/drm/i915/display/intel_display.c

5917

for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,

drivers/gpu/drm/i915/display/intel_display.c

5928

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

5947

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

5966

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

5971

for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,

drivers/gpu/drm/i915/display/intel_display.c

600

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

6005

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6017

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6024

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6035

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6054

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6061

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6073

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6086

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6093

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6100

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

611

drm_for_each_plane_mask(plane, display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6116

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6133

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6150

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6158

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6166

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6174

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6182

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6190

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6197

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6205

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

621

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

6212

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6219

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6227

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6239

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

627

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

6270

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {

drivers/gpu/drm/i915/display/intel_display.c

6276

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {

drivers/gpu/drm/i915/display/intel_display.c

6306

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6331

if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))

drivers/gpu/drm/i915/display/intel_display.c

6350

if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))

drivers/gpu/drm/i915/display/intel_display.c

6414

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_display.c

6420

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_display.c

6461

drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);

drivers/gpu/drm/i915/display/intel_display.c

653

if (HAS_GMCH(display) &&

drivers/gpu/drm/i915/display/intel_display.c

6530

drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n");

drivers/gpu/drm/i915/display/intel_display.c

654

intel_set_memory_cxsr(display, false))

drivers/gpu/drm/i915/display/intel_display.c

6581

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

661

if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)

drivers/gpu/drm/i915/display/intel_display.c

662

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);

drivers/gpu/drm/i915/display/intel_display.c

6625

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display.c

6627

if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)

drivers/gpu/drm/i915/display/intel_display.c

6628

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

6634

intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);

drivers/gpu/drm/i915/display/intel_display.c

6641

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

6655

if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_display.c

6658

} else if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_display.c

6673

if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_display.c

6674

display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display.c

6688

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6695

drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);

drivers/gpu/drm/i915/display/intel_display.c

6705

if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_display.c

6720

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6725

drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);

drivers/gpu/drm/i915/display/intel_display.c

6732

if (DISPLAY_VER(display) >= 9 && !modeset)

drivers/gpu/drm/i915/display/intel_display.c

6738

HAS_DOUBLE_BUFFERED_LUT(display))

drivers/gpu/drm/i915/display/intel_display.c

6748

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6756

for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,

drivers/gpu/drm/i915/display/intel_display.c

6767

display->funcs.display->crtc_enable(state, crtc);

drivers/gpu/drm/i915/display/intel_display.c

6776

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6785

if (HAS_DPT(display))

drivers/gpu/drm/i915/display/intel_display.c

6799

if (DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/intel_display.c

681

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

6815

drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));

drivers/gpu/drm/i915/display/intel_display.c

686

tmp = intel_de_read(display, PIPE_CHICKEN(pipe));

drivers/gpu/drm/i915/display/intel_display.c

6888

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6897

for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

drivers/gpu/drm/i915/display/intel_display.c

6903

display->funcs.display->crtc_disable(state, crtc);

drivers/gpu/drm/i915/display/intel_display.c

6905

for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

drivers/gpu/drm/i915/display/intel_display.c

6920

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

6987

drm_WARN_ON(display->drm, disable_pipes);

drivers/gpu/drm/i915/display/intel_display.c

7014

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

706

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_display.c

708

else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))

drivers/gpu/drm/i915/display/intel_display.c

712

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_display.c

715

intel_de_write(display, PIPE_CHICKEN(pipe), tmp);

drivers/gpu/drm/i915/display/intel_display.c

7156

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

7166

drm_WARN_ON(display->drm, modeset_pipes);

drivers/gpu/drm/i915/display/intel_display.c

7167

drm_WARN_ON(display->drm, update_pipes);

drivers/gpu/drm/i915/display/intel_display.c

718

bool intel_has_pending_fb_unpin(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

7212

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

7220

drm_atomic_helper_cleanup_planes(display->drm, &state->base);

drivers/gpu/drm/i915/display/intel_display.c

7227

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

723

drm_for_each_crtc(crtc, display->drm) {

drivers/gpu/drm/i915/display/intel_display.c

7264

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/intel_display.c

7271

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

7283

intel_flipq_supported(display) &&

drivers/gpu/drm/i915/display/intel_display.c

7294

(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&

drivers/gpu/drm/i915/display/intel_display.c

7304

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

7381

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display.c

7416

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_display.c

7417

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_display.c

7429

intel_td_flush(display);

drivers/gpu/drm/i915/display/intel_display.c

7470

wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);

drivers/gpu/drm/i915/display/intel_display.c

7496

drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);

drivers/gpu/drm/i915/display/intel_display.c

7511

spin_lock_irq(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_display.c

7514

spin_unlock_irq(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_display.c

7530

display->funcs.display->commit_modeset_enables(state);

drivers/gpu/drm/i915/display/intel_display.c

7546

drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);

drivers/gpu/drm/i915/display/intel_display.c

7578

if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

7579

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

drivers/gpu/drm/i915/display/intel_display.c

7607

intel_check_cpu_fifo_underruns(display);

drivers/gpu/drm/i915/display/intel_display.c

7608

intel_check_pch_fifo_underruns(display);

drivers/gpu/drm/i915/display/intel_display.c

7633

intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);

drivers/gpu/drm/i915/display/intel_display.c

7634

intel_display_rpm_put(display, state->wakeref);

drivers/gpu/drm/i915/display/intel_display.c

7645

queue_work(display->wq.cleanup, &state->cleanup_work);

drivers/gpu/drm/i915/display/intel_display.c

7704

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_display.c

7708

state->wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_display.c

7727

if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {

drivers/gpu/drm/i915/display/intel_display.c

7740

drm_dbg_atomic(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

7742

intel_display_rpm_put(display, state->wakeref);

drivers/gpu/drm/i915/display/intel_display.c

7752

intel_display_rpm_put(display, state->wakeref);

drivers/gpu/drm/i915/display/intel_display.c

7760

queue_work(display->wq.modeset, &state->base.commit_work);

drivers/gpu/drm/i915/display/intel_display.c

7762

queue_work(display->wq.flip, &state->base.commit_work);

drivers/gpu/drm/i915/display/intel_display.c

7765

flush_workqueue(display->wq.modeset);

drivers/gpu/drm/i915/display/intel_display.c

7774

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

7778

for_each_intel_encoder(display->drm, source_encoder) {

drivers/gpu/drm/i915/display/intel_display.c

7788

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display.c

7792

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)

drivers/gpu/drm/i915/display/intel_display.c

7798

static bool ilk_has_edp_a(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

7800

if (!display->platform.mobile)

drivers/gpu/drm/i915/display/intel_display.c

7803

if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)

drivers/gpu/drm/i915/display/intel_display.c

7806

if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))

drivers/gpu/drm/i915/display/intel_display.c

7812

static bool intel_ddi_crt_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

7814

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display.c

7817

if (display->platform.haswell_ult || display->platform.broadwell_ult)

drivers/gpu/drm/i915/display/intel_display.c

7820

if (HAS_PCH_LPT_H(display) &&

drivers/gpu/drm/i915/display/intel_display.c

7821

intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)

drivers/gpu/drm/i915/display/intel_display.c

7825

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

drivers/gpu/drm/i915/display/intel_display.c

7828

if (!display->vbt.int_crt_support)

drivers/gpu/drm/i915/display/intel_display.c

7834

bool assert_port_valid(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display.c

7836

return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),

drivers/gpu/drm/i915/display/intel_display.c

7840

void intel_setup_outputs(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

7845

intel_pps_unlock_regs_wa(display);

drivers/gpu/drm/i915/display/intel_display.c

7847

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display.c

7850

if (HAS_DDI(display)) {

drivers/gpu/drm/i915/display/intel_display.c

7851

if (intel_ddi_crt_present(display))

drivers/gpu/drm/i915/display/intel_display.c

7852

intel_crt_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7854

intel_bios_for_each_encoder(display, intel_ddi_init);

drivers/gpu/drm/i915/display/intel_display.c

7856

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display.c

7857

vlv_dsi_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7858

} else if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_display.c

7866

intel_lvds_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7867

intel_crt_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7869

dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

787

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

7871

if (ilk_has_edp_a(display))

drivers/gpu/drm/i915/display/intel_display.c

7872

g4x_dp_init(display, DP_A, PORT_A);

drivers/gpu/drm/i915/display/intel_display.c

7874

if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {

drivers/gpu/drm/i915/display/intel_display.c

7876

found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7878

g4x_hdmi_init(display, PCH_HDMIB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7879

if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))

drivers/gpu/drm/i915/display/intel_display.c

7880

g4x_dp_init(display, PCH_DP_B, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7883

if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7884

g4x_hdmi_init(display, PCH_HDMIC, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7886

if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7887

g4x_hdmi_init(display, PCH_HDMID, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

7889

if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7890

g4x_dp_init(display, PCH_DP_C, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7892

if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7893

g4x_dp_init(display, PCH_DP_D, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

7894

} else if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_display.c

7897

if (display->platform.valleyview && display->vbt.int_crt_support)

drivers/gpu/drm/i915/display/intel_display.c

7898

intel_crt_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7915

has_edp = intel_dp_is_port_edp(display, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7916

has_port = intel_bios_is_port_present(display, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7917

if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7918

has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7919

if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)

drivers/gpu/drm/i915/display/intel_display.c

7920

g4x_hdmi_init(display, VLV_HDMIB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7922

has_edp = intel_dp_is_port_edp(display, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7923

has_port = intel_bios_is_port_present(display, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7924

if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7925

has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7926

if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)

drivers/gpu/drm/i915/display/intel_display.c

7927

g4x_hdmi_init(display, VLV_HDMIC, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7929

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_display.c

793

if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_display.c

7934

has_port = intel_bios_is_port_present(display, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

7935

if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7936

g4x_dp_init(display, CHV_DP_D, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

7937

if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7938

g4x_hdmi_init(display, CHV_HDMID, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

7941

vlv_dsi_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7942

} else if (display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_display.c

7943

intel_lvds_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7944

intel_crt_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7945

} else if (IS_DISPLAY_VER(display, 3, 4)) {

drivers/gpu/drm/i915/display/intel_display.c

7948

if (display->platform.mobile)

drivers/gpu/drm/i915/display/intel_display.c

7949

intel_lvds_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7951

intel_crt_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7953

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

drivers/gpu/drm/i915/display/intel_display.c

7954

drm_dbg_kms(display->drm, "probing SDVOB\n");

drivers/gpu/drm/i915/display/intel_display.c

7955

found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7956

if (!found && display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_display.c

7957

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

7959

g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7962

if (!found && display->platform.g4x)

drivers/gpu/drm/i915/display/intel_display.c

7963

g4x_dp_init(display, DP_B, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7968

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

drivers/gpu/drm/i915/display/intel_display.c

7969

drm_dbg_kms(display->drm, "probing SDVOC\n");

drivers/gpu/drm/i915/display/intel_display.c

7970

found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7973

if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {

drivers/gpu/drm/i915/display/intel_display.c

7975

if (display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_display.c

7976

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

7978

g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7980

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_display.c

7981

g4x_dp_init(display, DP_C, PORT_C);

drivers/gpu/drm/i915/display/intel_display.c

7984

if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))

drivers/gpu/drm/i915/display/intel_display.c

7985

g4x_dp_init(display, DP_D, PORT_D);

drivers/gpu/drm/i915/display/intel_display.c

7987

if (SUPPORTS_TV(display))

drivers/gpu/drm/i915/display/intel_display.c

7988

intel_tv_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7989

} else if (DISPLAY_VER(display) == 2) {

drivers/gpu/drm/i915/display/intel_display.c

7990

if (display->platform.i85x)

drivers/gpu/drm/i915/display/intel_display.c

7991

intel_lvds_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7993

intel_crt_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7994

intel_dvo_init(display);

drivers/gpu/drm/i915/display/intel_display.c

7997

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_display.c

8004

intel_init_pch_refclk(display);

drivers/gpu/drm/i915/display/intel_display.c

8006

drm_helper_move_panel_connectors_to_head(display->drm);

drivers/gpu/drm/i915/display/intel_display.c

8009

static int max_dotclock(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

801

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

8011

int max_dotclock = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_display.c

8013

if (HAS_ULTRAJOINER(display))

drivers/gpu/drm/i915/display/intel_display.c

8015

else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))

drivers/gpu/drm/i915/display/intel_display.c

8024

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_display.c

804

if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display.c

8061

if (mode->clock > max_dotclock(display))

drivers/gpu/drm/i915/display/intel_display.c

8065

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display.c

8070

} else if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_display.c

8071

display->platform.broadwell || display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display.c

8076

} else if (DISPLAY_VER(display) >= 3) {

drivers/gpu/drm/i915/display/intel_display.c

8111

enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

8118

if (DISPLAY_VER(display) >= 5) {

drivers/gpu/drm/i915/display/intel_display.c

812

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

8137

if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&

drivers/gpu/drm/i915/display/intel_display.c

8145

intel_mode_valid_max_plane_size(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

8155

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_display.c

8163

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_display.c

8166

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display.c

817

DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display.c

823

static void intel_async_flip_vtd_wa(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.c

8232

void intel_init_display_hooks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

8234

if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_display.c

8235

display->funcs.display = &skl_display_funcs;

drivers/gpu/drm/i915/display/intel_display.c

8236

} else if (HAS_DDI(display)) {

drivers/gpu/drm/i915/display/intel_display.c

8237

display->funcs.display = &ddi_display_funcs;

drivers/gpu/drm/i915/display/intel_display.c

8238

} else if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_display.c

8239

display->funcs.display = &pch_split_display_funcs;

drivers/gpu/drm/i915/display/intel_display.c

8240

} else if (display->platform.cherryview ||

drivers/gpu/drm/i915/display/intel_display.c

8241

display->platform.valleyview) {

drivers/gpu/drm/i915/display/intel_display.c

8242

display->funcs.display = &vlv_display_funcs;

drivers/gpu/drm/i915/display/intel_display.c

8244

display->funcs.display = &i9xx_display_funcs;

drivers/gpu/drm/i915/display/intel_display.c

8248

int intel_initial_commit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

8255

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_display.c

826

if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_display.c

8265

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_display.c

8292

for_each_intel_encoder_mask(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_display.c

831

intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),

drivers/gpu/drm/i915/display/intel_display.c

8322

void i830_enable_pipe(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_display.c

8324

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

8337

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8340

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8352

intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

8354

intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

8356

intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

8358

intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

836

intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),

drivers/gpu/drm/i915/display/intel_display.c

8360

intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

8362

intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

8364

intel_de_write(display, PIPESRC(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

8367

intel_de_write(display, FP0(pipe), fp);

drivers/gpu/drm/i915/display/intel_display.c

8368

intel_de_write(display, FP1(pipe), fp);

drivers/gpu/drm/i915/display/intel_display.c

8375

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_display.c

8377

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8380

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8388

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8392

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8393

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8397

intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8398

intel_de_posting_read(display, TRANSCONF(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8403

void i830_disable_pipe(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_display.c

8405

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display.c

8407

drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",

drivers/gpu/drm/i915/display/intel_display.c

8410

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8411

intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8412

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8413

intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8414

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8415

intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8416

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8417

intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);

drivers/gpu/drm/i915/display/intel_display.c

8418

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display.c

8419

intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);

drivers/gpu/drm/i915/display/intel_display.c

8421

intel_de_write(display, TRANSCONF(display, pipe), 0);

drivers/gpu/drm/i915/display/intel_display.c

8422

intel_de_posting_read(display, TRANSCONF(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8426

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_display.c

8427

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display.c

8430

bool intel_scanout_needs_vtd_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display.c

8432

return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display);

drivers/gpu/drm/i915/display/intel_display.c

844

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

846

return crtc_state->uapi.async_flip && intel_display_vtd_active(display) &&

drivers/gpu/drm/i915/display/intel_display.c

847

(DISPLAY_VER(display) == 9 || display->platform.broadwell ||

drivers/gpu/drm/i915/display/intel_display.c

848

display->platform.haswell);

drivers/gpu/drm/i915/display/intel_display.h

373

#define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \

drivers/gpu/drm/i915/display/intel_display.h

375

(i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \

drivers/gpu/drm/i915/display/intel_display.h

379

#define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \

drivers/gpu/drm/i915/display/intel_display.h

381

(i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \

drivers/gpu/drm/i915/display/intel_display.h

385

#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \

drivers/gpu/drm/i915/display/intel_display.h

386

for_each_crtc_in_masks(display, crtc, \

drivers/gpu/drm/i915/display/intel_display.h

391

#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \

drivers/gpu/drm/i915/display/intel_display.h

392

for_each_crtc_in_masks_reverse(display, crtc, \

drivers/gpu/drm/i915/display/intel_display.h

406

u32 intel_plane_fb_max_stride(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

412

intel_mode_valid_max_plane_size(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

416

intel_cpu_transcoder_mode_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

418

enum phy intel_port_to_phy(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.h

442

void i830_enable_pipe(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_display.h

443

void i830_disable_pipe(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_display.h

444

bool intel_has_pending_fb_unpin(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display.h

450

bool intel_phy_is_combo(struct intel_display *display, enum phy phy);

drivers/gpu/drm/i915/display/intel_display.h

451

bool intel_phy_is_tc(struct intel_display *display, enum phy phy);

drivers/gpu/drm/i915/display/intel_display.h

452

bool intel_phy_is_snps(struct intel_display *display, enum phy phy);

drivers/gpu/drm/i915/display/intel_display.h

453

enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.h

454

enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.h

467

void intel_set_m_n(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

471

void intel_get_m_n(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

475

bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

513

int intel_display_max_pipe_bpp(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display.h

520

int intel_modeset_commit_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

529

void intel_init_display_hooks(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display.h

530

void intel_setup_outputs(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display.h

531

int intel_initial_commit(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display.h

532

void intel_panel_sanitize_ssc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display.h

539

void assert_transcoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display.h

544

bool assert_port_valid(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.h

561

bool intel_scanout_needs_vtd_wa(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_conversion.c

20

return d->display;

drivers/gpu/drm/i915/display/intel_display_core.h

300

const struct intel_display_funcs *display;

drivers/gpu/drm/i915/display/intel_display_core.h

83

void (*update_wm)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_core.h

93

void (*get_hw_state)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_core.h

94

void (*sanitize)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

100

sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1009

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

101

else if (display->platform.i915gm)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1018

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

102

sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

103

else if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1031

out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

104

sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

105

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

106

sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1075

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

108

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1084

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1098

out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1142

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1151

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1166

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

117

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1177

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1186

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1193

drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",

drivers/gpu/drm/i915/display/intel_display_debugfs.c

121

fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1266

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1284

if (HAS_ULTRAJOINER(display)) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1322

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1338

if (DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/intel_display_debugfs.c

134

mutex_lock(&display->drm->mode_config.fb_lock);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

135

drm_for_each_fb(drm_fb, display->drm) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

150

mutex_unlock(&display->drm->mode_config.fb_lock);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

157

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

159

intel_display_power_debug(display, m);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

179

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

186

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

398

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

401

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

544

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

580

for_each_intel_encoder_mask(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

595

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

60

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

601

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

603

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

607

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

613

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

618

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

620

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

627

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

63

drm_printf(&p, "PCH type: %d\n", INTEL_PCH_TYPE(display));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

632

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

635

display->dpll.ref_clks.nssc,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

636

display->dpll.ref_clks.ssc);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

638

for_each_dpll(display, pll, i) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

645

intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

647

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

65

intel_display_device_info_print(DISPLAY_INFO(display),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

654

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

658

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

66

DISPLAY_RUNTIME_INFO(display), &p);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

661

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

665

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

67

intel_display_params_dump(&display->params, display->drm->driver->name, &p);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

685

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

691

intel_lpsp_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

696

with_intel_display_rpm(display)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

697

is_enabled = intel_display_power_well_is_enabled(display,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

705

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

708

if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

709

lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

710

} else if (IS_DISPLAY_VER(display, 11, 12)) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

711

lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

712

} else if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

713

lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

726

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

732

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

74

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

76

spin_lock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

760

struct intel_display *display = filp->private_data;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

772

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

789

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

79

display->fb_tracking.busy_bits);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

802

intel_fbc_reset_underrun(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

81

spin_unlock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

827

void intel_display_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

829

struct dentry *debugfs_root = display->drm->debugfs_root;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

832

display, &i915_fifo_underrun_reset_ops);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

836

debugfs_root, display->drm->primary);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

838

intel_bios_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

839

intel_cdclk_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

840

intel_dmc_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

841

intel_dp_test_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

842

intel_fbc_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

843

intel_hpd_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

844

intel_opregion_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

845

intel_psr_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

846

intel_wm_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

847

intel_display_debugfs_params(display);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

853

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

864

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

866

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

873

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

876

else if (IS_DISPLAY_VER(display, 9, 10))

drivers/gpu/drm/i915/display/intel_display_debugfs.c

88

struct intel_display *display = node_to_intel_display(m->private);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

881

else if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

893

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

905

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

92

wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

94

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

96

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_display_debugfs.c

966

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

97

sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

975

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

98

else if (display->platform.i965gm || display->platform.g4x ||

drivers/gpu/drm/i915/display/intel_display_debugfs.c

982

drm_dbg(display->drm, "Got %s for DSC Enable\n",

drivers/gpu/drm/i915/display/intel_display_debugfs.c

99

display->platform.i945g || display->platform.i945gm)

drivers/gpu/drm/i915/display/intel_display_debugfs.h

14

void intel_display_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_debugfs.h

18

static inline void intel_display_debugfs_register(struct intel_display *display) {}

drivers/gpu/drm/i915/display/intel_display_debugfs_params.c

154

void intel_display_debugfs_params(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_debugfs_params.c

156

struct dentry *debugfs_root = display->drm->debugfs_root;

drivers/gpu/drm/i915/display/intel_display_debugfs_params.c

160

snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);

drivers/gpu/drm/i915/display/intel_display_debugfs_params.c

174

dir, #x, mode, &display->params.x);

drivers/gpu/drm/i915/display/intel_display_debugfs_params.h

11

void intel_display_debugfs_params(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_device.c

1508

const struct intel_display_device_info *display;

drivers/gpu/drm/i915/display/intel_display_device.c

1519

probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *ip_ver)

drivers/gpu/drm/i915/display/intel_display_device.c

1521

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_display_device.c

1529

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_device.c

1538

drm_dbg_kms(display->drm, "Device doesn't have display\n");

drivers/gpu/drm/i915/display/intel_display_device.c

1550

return gmdid_display_map[i].display;

drivers/gpu/drm/i915/display/intel_display_device.c

1554

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_device.c

1586

static enum intel_step get_pre_gmdid_step(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_device.c

1590

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_display_device.c

1609

drm_warn(display->drm, "Unknown revision 0x%02x\n", revision);

drivers/gpu/drm/i915/display/intel_display_device.c

1623

drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n",

drivers/gpu/drm/i915/display/intel_display_device.c

1627

drm_dbg_kms(display->drm, "Using future display stepping\n");

drivers/gpu/drm/i915/display/intel_display_device.c

1632

drm_WARN_ON(display->drm, step == STEP_NONE);

drivers/gpu/drm/i915/display/intel_display_device.c

1659

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_display_device.c

1666

display = kzalloc_obj(*display);

drivers/gpu/drm/i915/display/intel_display_device.c

1667

if (!display)

drivers/gpu/drm/i915/display/intel_display_device.c

1671

display->drm = pci_get_drvdata(pdev);

drivers/gpu/drm/i915/display/intel_display_device.c

1673

display->parent = parent;

drivers/gpu/drm/i915/display/intel_display_device.c

1675

intel_display_params_copy(&display->params);

drivers/gpu/drm/i915/display/intel_display_device.c

1678

drm_dbg_kms(display->drm, "Device doesn't have display\n");

drivers/gpu/drm/i915/display/intel_display_device.c

1684

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_device.c

1692

info = probe_gmdid_display(display, &ip_ver);

drivers/gpu/drm/i915/display/intel_display_device.c

1696

DISPLAY_INFO(display) = info;

drivers/gpu/drm/i915/display/intel_display_device.c

1698

memcpy(DISPLAY_RUNTIME_INFO(display),

drivers/gpu/drm/i915/display/intel_display_device.c

1699

&DISPLAY_INFO(display)->__runtime_defaults,

drivers/gpu/drm/i915/display/intel_display_device.c

1700

sizeof(*DISPLAY_RUNTIME_INFO(display)));

drivers/gpu/drm/i915/display/intel_display_device.c

1702

drm_WARN_ON(display->drm, !desc->name ||

drivers/gpu/drm/i915/display/intel_display_device.c

1705

display->platform = desc->platforms;

drivers/gpu/drm/i915/display/intel_display_device.c

1709

drm_WARN_ON(display->drm, !subdesc->name ||

drivers/gpu/drm/i915/display/intel_display_device.c

1712

display_platforms_or(&display->platform, &subdesc->platforms);

drivers/gpu/drm/i915/display/intel_display_device.c

1715

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_device.c

1716

display_platforms_weight(&display->platform) !=

drivers/gpu/drm/i915/display/intel_display_device.c

1722

DISPLAY_RUNTIME_INFO(display)->ip = ip_ver;

drivers/gpu/drm/i915/display/intel_display_device.c

1725

drm_dbg_kms(display->drm, "Using future display stepping\n");

drivers/gpu/drm/i915/display/intel_display_device.c

1729

step = get_pre_gmdid_step(display, &desc->step_info,

drivers/gpu/drm/i915/display/intel_display_device.c

1733

DISPLAY_RUNTIME_INFO(display)->step = step;

drivers/gpu/drm/i915/display/intel_display_device.c

1735

drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n",

drivers/gpu/drm/i915/display/intel_display_device.c

1737

pdev->device, display->platform.dgfx ? "discrete" : "integrated",

drivers/gpu/drm/i915/display/intel_display_device.c

1738

DISPLAY_RUNTIME_INFO(display)->ip.ver,

drivers/gpu/drm/i915/display/intel_display_device.c

1739

DISPLAY_RUNTIME_INFO(display)->ip.rel,

drivers/gpu/drm/i915/display/intel_display_device.c

1742

return display;

drivers/gpu/drm/i915/display/intel_display_device.c

1745

DISPLAY_INFO(display) = &no_display;

drivers/gpu/drm/i915/display/intel_display_device.c

1747

return display;

drivers/gpu/drm/i915/display/intel_display_device.c

1750

void intel_display_device_remove(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_device.c

1752

if (!display)

drivers/gpu/drm/i915/display/intel_display_device.c

1755

intel_display_params_free(&display->params);

drivers/gpu/drm/i915/display/intel_display_device.c

1756

kfree(display);

drivers/gpu/drm/i915/display/intel_display_device.c

1759

static void __intel_display_device_info_runtime_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_device.c

1761

struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);

drivers/gpu/drm/i915/display/intel_display_device.c

1769

if (display->platform.haswell_ult || display->platform.broadwell_ult)

drivers/gpu/drm/i915/display/intel_display_device.c

1772

if (display->platform.icelake_port_f)

drivers/gpu/drm/i915/display/intel_display_device.c

1776

if (display->platform.alderlake_s && IS_DISPLAY_STEP(display, STEP_A0, STEP_A2))

drivers/gpu/drm/i915/display/intel_display_device.c

1777

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1779

else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_device.c

1780

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1782

} else if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_display_device.c

1788

if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))

drivers/gpu/drm/i915/display/intel_display_device.c

1789

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1791

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display_device.c

1792

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1794

else if (DISPLAY_VER(display) == 10)

drivers/gpu/drm/i915/display/intel_display_device.c

1795

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1797

else if (display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_device.c

1810

} else if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_display_device.c

1811

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1813

} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_display_device.c

1814

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1818

if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) &&

drivers/gpu/drm/i915/display/intel_display_device.c

1819

!(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) {

drivers/gpu/drm/i915/display/intel_display_device.c

1820

drm_info(display->drm, "Display not present, disabling\n");

drivers/gpu/drm/i915/display/intel_display_device.c

1824

if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_display_device.c

1825

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

drivers/gpu/drm/i915/display/intel_display_device.c

1826

u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);

drivers/gpu/drm/i915/display/intel_display_device.c

1839

(HAS_PCH_CPT(display) &&

drivers/gpu/drm/i915/display/intel_display_device.c

1841

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_display_device.c

1845

drm_info(display->drm, "PipeC fused off\n");

drivers/gpu/drm/i915/display/intel_display_device.c

1849

} else if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_display_device.c

1850

u32 dfsm = intel_de_read(display, SKL_DFSM);

drivers/gpu/drm/i915/display/intel_display_device.c

1868

if (DISPLAY_VER(display) >= 12 &&

drivers/gpu/drm/i915/display/intel_display_device.c

1881

if (display->platform.dg2 || DISPLAY_VER(display) < 13) {

drivers/gpu/drm/i915/display/intel_display_device.c

1886

if (DISPLAY_VER(display) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))

drivers/gpu/drm/i915/display/intel_display_device.c

1889

if (IS_DISPLAY_VER(display, 10, 12) &&

drivers/gpu/drm/i915/display/intel_display_device.c

1893

if (DISPLAY_VER(display) >= 20 &&

drivers/gpu/drm/i915/display/intel_display_device.c

1898

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_display_device.c

1899

u32 cap = intel_de_read(display, XE2LPD_DE_CAP);

drivers/gpu/drm/i915/display/intel_display_device.c

1907

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_device.c

1913

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_display_device.c

1915

intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;

drivers/gpu/drm/i915/display/intel_display_device.c

1917

display_runtime->rawclk_freq = intel_read_rawclk(display);

drivers/gpu/drm/i915/display/intel_display_device.c

1918

drm_dbg_kms(display->drm, "rawclk rate: %d kHz\n",

drivers/gpu/drm/i915/display/intel_display_device.c

1927

void intel_display_device_info_runtime_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_device.c

1929

if (HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_device.c

1930

__intel_display_device_info_runtime_init(display);

drivers/gpu/drm/i915/display/intel_display_device.c

1933

if (!HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_display_device.c

1934

display->drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);

drivers/gpu/drm/i915/display/intel_display_device.c

1935

display->info.__device_info = &no_display;

drivers/gpu/drm/i915/display/intel_display_device.c

1939

if (!display->params.nuclear_pageflip &&

drivers/gpu/drm/i915/display/intel_display_device.c

1940

DISPLAY_VER(display) < 5 && !display->platform.g4x)

drivers/gpu/drm/i915/display/intel_display_device.c

1941

display->drm->driver_features &= ~DRIVER_ATOMIC;

drivers/gpu/drm/i915/display/intel_display_device.c

1969

bool intel_display_device_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_device.c

1971

return display && HAS_DISPLAY(display);

drivers/gpu/drm/i915/display/intel_display_device.c

1983

bool intel_display_device_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_device.c

1986

drm_WARN_ON(display->drm, !HAS_DISPLAY(display));

drivers/gpu/drm/i915/display/intel_display_device.c

1988

return !display->params.disable_display &&

drivers/gpu/drm/i915/display/intel_display_device.c

1989

!intel_opregion_headless_sku(display);

drivers/gpu/drm/i915/display/intel_display_device.h

265

#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe) \

drivers/gpu/drm/i915/display/intel_display_device.h

266

(DISPLAY_INFO((display))->pipe_offsets[(pipe)] - \

drivers/gpu/drm/i915/display/intel_display_device.h

267

DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \

drivers/gpu/drm/i915/display/intel_display_device.h

268

DISPLAY_MMIO_BASE((display)))

drivers/gpu/drm/i915/display/intel_display_device.h

270

#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \

drivers/gpu/drm/i915/display/intel_display_device.h

271

(DISPLAY_INFO((display))->trans_offsets[(trans)] - \

drivers/gpu/drm/i915/display/intel_display_device.h

272

DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \

drivers/gpu/drm/i915/display/intel_display_device.h

273

DISPLAY_MMIO_BASE((display)))

drivers/gpu/drm/i915/display/intel_display_device.h

275

#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \

drivers/gpu/drm/i915/display/intel_display_device.h

276

(DISPLAY_INFO((display))->cursor_offsets[(pipe)] - \

drivers/gpu/drm/i915/display/intel_display_device.h

277

DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \

drivers/gpu/drm/i915/display/intel_display_device.h

278

DISPLAY_MMIO_BASE((display)))

drivers/gpu/drm/i915/display/intel_display_device.h

280

#define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset)

drivers/gpu/drm/i915/display/intel_display_device.h

339

bool intel_display_device_present(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_device.h

340

bool intel_display_device_enabled(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_device.h

343

void intel_display_device_remove(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_device.h

344

void intel_display_device_info_runtime_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.c

114

static void intel_mode_config_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

116

struct drm_mode_config *mode_config = &display->drm->mode_config;

drivers/gpu/drm/i915/display/intel_display_driver.c

118

drm_mode_config_init(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

119

INIT_LIST_HEAD(&display->global.obj_list);

drivers/gpu/drm/i915/display/intel_display_driver.c

130

mode_config->async_page_flip = HAS_ASYNC_FLIPS(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

136

if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/intel_display_driver.c

139

} else if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_display_driver.c

142

} else if (DISPLAY_VER(display) == 3) {

drivers/gpu/drm/i915/display/intel_display_driver.c

150

intel_cursor_mode_config_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

153

static void intel_mode_config_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

155

intel_atomic_global_obj_cleanup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

156

drm_mode_config_cleanup(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

159

static void intel_plane_possible_crtcs_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

163

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/intel_display_driver.c

164

struct intel_crtc *crtc = intel_crtc_for_pipe(display,

drivers/gpu/drm/i915/display/intel_display_driver.c

171

void intel_display_driver_early_probe(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

174

intel_pch_detect(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

176

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

179

spin_lock_init(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_display_driver.c

180

mutex_init(&display->backlight.lock);

drivers/gpu/drm/i915/display/intel_display_driver.c

181

mutex_init(&display->audio.mutex);

drivers/gpu/drm/i915/display/intel_display_driver.c

182

mutex_init(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/intel_display_driver.c

183

mutex_init(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_display_driver.c

184

mutex_init(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_display_driver.c

186

intel_display_irq_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

187

intel_dkl_phy_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

188

intel_color_init_hooks(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

189

intel_init_cdclk_hooks(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

190

intel_audio_hooks_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

191

intel_dpll_init_clock_hook(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

192

intel_init_display_hooks(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

193

intel_fdi_init_hook(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

194

intel_dmc_wl_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

198

int intel_display_driver_probe_noirq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

202

if (HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_display_driver.c

203

ret = drm_vblank_init(display->drm,

drivers/gpu/drm/i915/display/intel_display_driver.c

204

INTEL_NUM_PIPES(display));

drivers/gpu/drm/i915/display/intel_display_driver.c

209

intel_bios_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

211

ret = intel_vga_register(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

215

intel_psr_dc5_dc6_wa_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

218

ret = intel_power_domains_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

222

intel_pmdemand_init_early(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

224

intel_power_domains_init_hw(display, false);

drivers/gpu/drm/i915/display/intel_display_driver.c

226

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

229

display->hotplug.dp_wq = alloc_ordered_workqueue("intel-dp", 0);

drivers/gpu/drm/i915/display/intel_display_driver.c

230

if (!display->hotplug.dp_wq) {

drivers/gpu/drm/i915/display/intel_display_driver.c

235

display->wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);

drivers/gpu/drm/i915/display/intel_display_driver.c

236

if (!display->wq.modeset) {

drivers/gpu/drm/i915/display/intel_display_driver.c

241

display->wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |

drivers/gpu/drm/i915/display/intel_display_driver.c

243

if (!display->wq.flip) {

drivers/gpu/drm/i915/display/intel_display_driver.c

248

display->wq.cleanup = alloc_workqueue("i915_cleanup", WQ_HIGHPRI, 0);

drivers/gpu/drm/i915/display/intel_display_driver.c

249

if (!display->wq.cleanup) {

drivers/gpu/drm/i915/display/intel_display_driver.c

254

display->wq.unordered = alloc_workqueue("display_unordered", 0, 0);

drivers/gpu/drm/i915/display/intel_display_driver.c

255

if (!display->wq.unordered) {

drivers/gpu/drm/i915/display/intel_display_driver.c

260

intel_dmc_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

262

intel_mode_config_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

264

ret = intel_cdclk_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

268

ret = intel_color_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

272

ret = intel_dbuf_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

276

ret = intel_dbuf_bw_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

280

ret = intel_bw_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

284

ret = intel_pmdemand_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

288

intel_init_quirks(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

290

intel_fbc_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

295

destroy_workqueue(display->wq.unordered);

drivers/gpu/drm/i915/display/intel_display_driver.c

297

destroy_workqueue(display->wq.cleanup);

drivers/gpu/drm/i915/display/intel_display_driver.c

299

destroy_workqueue(display->wq.flip);

drivers/gpu/drm/i915/display/intel_display_driver.c

301

destroy_workqueue(display->wq.modeset);

drivers/gpu/drm/i915/display/intel_display_driver.c

303

destroy_workqueue(display->hotplug.dp_wq);

drivers/gpu/drm/i915/display/intel_display_driver.c

305

intel_dmc_fini(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

306

intel_power_domains_driver_remove(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

308

intel_vga_unregister(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

310

intel_bios_driver_remove(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

316

static void set_display_access(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_driver.c

324

err = drm_modeset_lock_all_ctx(display->drm, &ctx);

drivers/gpu/drm/i915/display/intel_display_driver.c

328

display->access.any_task_allowed = any_task_allowed;

drivers/gpu/drm/i915/display/intel_display_driver.c

329

display->access.allowed_task = allowed_task;

drivers/gpu/drm/i915/display/intel_display_driver.c

332

drm_WARN_ON(display->drm, err);

drivers/gpu/drm/i915/display/intel_display_driver.c

345

void intel_display_driver_enable_user_access(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

347

set_display_access(display, true, NULL);

drivers/gpu/drm/i915/display/intel_display_driver.c

349

intel_hpd_enable_detection_work(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

369

void intel_display_driver_disable_user_access(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

371

intel_hpd_disable_detection_work(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

373

set_display_access(display, false, current);

drivers/gpu/drm/i915/display/intel_display_driver.c

388

void intel_display_driver_suspend_access(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

390

set_display_access(display, false, NULL);

drivers/gpu/drm/i915/display/intel_display_driver.c

407

void intel_display_driver_resume_access(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

409

set_display_access(display, false, current);

drivers/gpu/drm/i915/display/intel_display_driver.c

423

bool intel_display_driver_check_access(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

428

if (display->access.any_task_allowed ||

drivers/gpu/drm/i915/display/intel_display_driver.c

429

display->access.allowed_task == current)

drivers/gpu/drm/i915/display/intel_display_driver.c

435

if (display->access.allowed_task)

drivers/gpu/drm/i915/display/intel_display_driver.c

437

display->access.allowed_task->comm,

drivers/gpu/drm/i915/display/intel_display_driver.c

438

task_pid_vnr(display->access.allowed_task));

drivers/gpu/drm/i915/display/intel_display_driver.c

440

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_driver.c

448

int intel_display_driver_probe_nogem(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

452

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

455

intel_wm_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

457

intel_panel_sanitize_ssc(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

459

intel_pps_setup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

461

intel_gmbus_setup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

463

ret = intel_crtc_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

467

intel_plane_possible_crtcs_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

468

intel_dpll_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

469

intel_fdi_pll_freq_update(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

471

intel_display_driver_init_hw(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

472

intel_dpll_update_ref_clks(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

474

if (display->cdclk.max_cdclk_freq == 0)

drivers/gpu/drm/i915/display/intel_display_driver.c

475

intel_update_max_cdclk(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

477

intel_hti_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

479

intel_setup_outputs(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

481

ret = intel_dp_tunnel_mgr_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

485

intel_display_driver_disable_user_access(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

487

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

488

intel_modeset_setup_hw_state(display, display->drm->mode_config.acquire_ctx);

drivers/gpu/drm/i915/display/intel_display_driver.c

489

intel_acpi_assign_connector_fwnodes(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

490

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

492

intel_initial_plane_config(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

499

if (!HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

500

ilk_wm_sanitize(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

505

intel_hdcp_component_fini(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

507

intel_mode_config_cleanup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

513

int intel_display_driver_probe(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

517

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

525

intel_hdcp_component_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

527

intel_flipq_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

535

ret = intel_initial_commit(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

537

drm_dbg_kms(display->drm, "Initial modeset failed, %d\n", ret);

drivers/gpu/drm/i915/display/intel_display_driver.c

539

intel_overlay_setup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

542

intel_hpd_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

544

skl_watermark_ipc_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

549

void intel_display_driver_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

551

struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,

drivers/gpu/drm/i915/display/intel_display_driver.c

554

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

558

intel_opregion_register(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

559

intel_acpi_video_register(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

561

intel_audio_init(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

563

intel_display_driver_enable_user_access(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

565

intel_audio_register(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

567

intel_display_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

574

drm_kms_helper_poll_init(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

575

intel_hpd_poll_disable(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

577

intel_fbdev_setup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

579

intel_display_device_info_print(DISPLAY_INFO(display),

drivers/gpu/drm/i915/display/intel_display_driver.c

580

DISPLAY_RUNTIME_INFO(display), &p);

drivers/gpu/drm/i915/display/intel_display_driver.c

586

void intel_display_driver_remove(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

588

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

591

flush_workqueue(display->wq.flip);

drivers/gpu/drm/i915/display/intel_display_driver.c

592

flush_workqueue(display->wq.modeset);

drivers/gpu/drm/i915/display/intel_display_driver.c

593

flush_workqueue(display->wq.cleanup);

drivers/gpu/drm/i915/display/intel_display_driver.c

594

flush_workqueue(display->wq.unordered);

drivers/gpu/drm/i915/display/intel_display_driver.c

601

intel_dp_mst_suspend(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

605

void intel_display_driver_remove_noirq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

607

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

610

intel_display_driver_suspend_access(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

616

intel_hpd_poll_fini(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

621

flush_workqueue(display->wq.unordered);

drivers/gpu/drm/i915/display/intel_display_driver.c

623

intel_hdcp_component_fini(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

625

intel_mode_config_cleanup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

627

intel_dp_tunnel_mgr_cleanup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

629

intel_overlay_cleanup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

631

intel_gmbus_teardown(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

633

destroy_workqueue(display->hotplug.dp_wq);

drivers/gpu/drm/i915/display/intel_display_driver.c

634

destroy_workqueue(display->wq.flip);

drivers/gpu/drm/i915/display/intel_display_driver.c

635

destroy_workqueue(display->wq.modeset);

drivers/gpu/drm/i915/display/intel_display_driver.c

636

destroy_workqueue(display->wq.cleanup);

drivers/gpu/drm/i915/display/intel_display_driver.c

637

destroy_workqueue(display->wq.unordered);

drivers/gpu/drm/i915/display/intel_display_driver.c

639

intel_fbc_cleanup(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

643

void intel_display_driver_remove_nogem(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

645

intel_dmc_fini(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

647

intel_power_domains_driver_remove(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

649

intel_vga_unregister(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

651

intel_bios_driver_remove(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

654

void intel_display_driver_unregister(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

656

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

661

drm_client_dev_unregister(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

668

drm_kms_helper_poll_fini(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

670

intel_display_driver_disable_user_access(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

672

intel_audio_deinit(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

674

drm_atomic_helper_shutdown(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

677

intel_opregion_unregister(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

684

int intel_display_driver_suspend(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

689

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

692

state = drm_atomic_helper_suspend(display->drm);

drivers/gpu/drm/i915/display/intel_display_driver.c

695

drm_err(display->drm, "Suspending crtc's failed with %i\n",

drivers/gpu/drm/i915/display/intel_display_driver.c

698

display->restore.modeset_state = state;

drivers/gpu/drm/i915/display/intel_display_driver.c

701

flush_workqueue(display->wq.cleanup);

drivers/gpu/drm/i915/display/intel_display_driver.c

703

intel_dp_mst_suspend(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

709

__intel_display_driver_resume(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_driver.c

717

intel_modeset_setup_hw_state(display, ctx);

drivers/gpu/drm/i915/display/intel_display_driver.c

737

if (!HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

742

drm_WARN_ON(display->drm, ret == -EDEADLK);

drivers/gpu/drm/i915/display/intel_display_driver.c

747

void intel_display_driver_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

749

struct drm_atomic_state *state = display->restore.modeset_state;

drivers/gpu/drm/i915/display/intel_display_driver.c

753

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

757

intel_dp_mst_resume(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

759

display->restore.modeset_state = NULL;

drivers/gpu/drm/i915/display/intel_display_driver.c

766

ret = drm_modeset_lock_all_ctx(display->drm, &ctx);

drivers/gpu/drm/i915/display/intel_display_driver.c

774

ret = __intel_display_driver_resume(display, state, &ctx);

drivers/gpu/drm/i915/display/intel_display_driver.c

776

skl_watermark_ipc_update(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

781

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_driver.c

89

void intel_display_driver_init_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_driver.c

91

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_driver.c

94

intel_cdclk_read_hw(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

96

intel_display_wa_apply(display);

drivers/gpu/drm/i915/display/intel_display_driver.h

17

void intel_display_driver_init_hw(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

18

void intel_display_driver_early_probe(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

19

int intel_display_driver_probe_noirq(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

20

int intel_display_driver_probe_nogem(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

21

int intel_display_driver_probe(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

22

void intel_display_driver_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

23

void intel_display_driver_remove(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

24

void intel_display_driver_remove_noirq(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

25

void intel_display_driver_remove_nogem(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

26

void intel_display_driver_unregister(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

27

int intel_display_driver_suspend(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

28

void intel_display_driver_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

31

int __intel_display_driver_resume(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_driver.h

35

void intel_display_driver_enable_user_access(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

36

void intel_display_driver_disable_user_access(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

37

void intel_display_driver_suspend_access(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

38

void intel_display_driver_resume_access(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_driver.h

39

bool intel_display_driver_check_access(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1007

if (!HAS_PCH_NOP(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1008

*sde_ier = intel_de_read_fw(display, SDEIER);

drivers/gpu/drm/i915/display/intel_display_irq.c

1009

intel_de_write_fw(display, SDEIER, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1015

void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier)

drivers/gpu/drm/i915/display/intel_display_irq.c

1017

intel_de_write_fw(display, DEIER, de_ier);

drivers/gpu/drm/i915/display/intel_display_irq.c

1020

intel_de_write_fw(display, SDEIER, sde_ier);

drivers/gpu/drm/i915/display/intel_display_irq.c

1023

bool ilk_display_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1028

de_iir = intel_de_read_fw(display, DEIIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1030

intel_de_write_fw(display, DEIIR, de_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1031

if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/intel_display_irq.c

1032

_ivb_display_irq_handler(display, de_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1034

_ilk_display_irq_handler(display, de_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1041

static u32 gen8_de_port_aux_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1045

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_display_irq.c

1047

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_irq.c

1050

else if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_display_irq.c

1060

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_irq.c

107

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

1072

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display_irq.c

1077

if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1085

static u32 gen8_de_pipe_fault_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1087

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_display_irq.c

1095

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_irq.c

1105

else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

1113

else if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/intel_display_irq.c

1123

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display_irq.c

1132

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display_irq.c

1146

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

1148

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1157

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

1159

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1168

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

117

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1170

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1232

gen8_pipe_fault_handlers(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1234

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_irq.c

1236

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_irq.c

1238

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display_irq.c

1240

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display_irq.c

1246

static void intel_pmdemand_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1248

wake_up_all(&display->pmdemand.waitqueue);

drivers/gpu/drm/i915/display/intel_display_irq.c

1252

gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

1256

if (HAS_DBUF_OVERLAP_DETECTION(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1258

drm_warn(display->drm, "DBuf overlap detected\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

126

static void intel_pipe_fault_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1263

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1267

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1270

intel_pmdemand_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1275

u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);

drivers/gpu/drm/i915/display/intel_display_irq.c

1276

drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val);

drivers/gpu/drm/i915/display/intel_display_irq.c

1280

intel_opregion_asle_intr(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1289

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1292

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_irq.c

1293

iir_reg = TRANS_PSR_IIR(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1298

psr_iir = intel_de_rmw(display, iir_reg, 0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

130

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1306

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_display_irq.c

1312

drm_err(display->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1315

static void gen11_dsi_te_interrupt_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1327

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));

drivers/gpu/drm/i915/display/intel_display_irq.c

1339

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

drivers/gpu/drm/i915/display/intel_display_irq.c

1343

drm_err(display->drm, "DSI trancoder not configured in command mode\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

1348

val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));

drivers/gpu/drm/i915/display/intel_display_irq.c

1360

drm_err(display->drm, "Invalid PIPE\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

1364

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1368

intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1371

static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1373

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display_irq.c

1379

static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

1384

*pch_iir = intel_de_read(display, SDEIIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1394

drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL);

drivers/gpu/drm/i915/display/intel_display_irq.c

1396

pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1397

*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1398

intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1401

intel_de_write(display, SDEIIR, *pch_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1404

intel_de_write(display, PICAINTERRUPT_IER, pica_ier);

drivers/gpu/drm/i915/display/intel_display_irq.c

1407

void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)

drivers/gpu/drm/i915/display/intel_display_irq.c

1412

drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display));

drivers/gpu/drm/i915/display/intel_display_irq.c

1415

iir = intel_de_read(display, GEN8_DE_MISC_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1417

intel_de_write(display, GEN8_DE_MISC_IIR, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1418

gen8_de_misc_irq_handler(display, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1420

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1425

if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1426

iir = intel_de_read(display, GEN11_DE_HPD_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1428

intel_de_write(display, GEN11_DE_HPD_IIR, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1429

gen11_hpd_irq_handler(display, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1431

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1437

iir = intel_de_read(display, GEN8_DE_PORT_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1441

intel_de_write(display, GEN8_DE_PORT_IIR, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1443

if (iir & gen8_de_port_aux_mask(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1444

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1448

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1452

bxt_hpd_irq_handler(display, hotplug_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

1455

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1459

ilk_hpd_irq_handler(display, hotplug_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

146

intel_handle_vblank(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

1464

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/intel_display_irq.c

1466

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1470

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1474

gen11_dsi_te_interrupt_handler(display, te_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

148

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1480

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1483

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1488

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1494

iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

1496

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1502

intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1505

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1507

if (iir & gen8_de_pipe_flip_done_mask(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

1508

flip_done_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1510

if (HAS_DSB(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1512

intel_dsb_irq_handler(display, pipe, INTEL_DSB_0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1515

intel_dsb_irq_handler(display, pipe, INTEL_DSB_1);

drivers/gpu/drm/i915/display/intel_display_irq.c

1518

intel_dsb_irq_handler(display, pipe, INTEL_DSB_2);

drivers/gpu/drm/i915/display/intel_display_irq.c

1521

if (HAS_PIPEDMC(display) && iir & GEN12_PIPEDMC_INTERRUPT)

drivers/gpu/drm/i915/display/intel_display_irq.c

1522

intel_pipedmc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1525

hsw_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1528

intel_cpu_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

1530

fault_errors = iir & gen8_de_pipe_fault_mask(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1532

intel_pipe_fault_irq_handler(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1533

gen8_pipe_fault_handlers(display),

drivers/gpu/drm/i915/display/intel_display_irq.c

1537

if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) &&

drivers/gpu/drm/i915/display/intel_display_irq.c

1546

gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1549

xelpdp_pica_irq_handler(display, pica_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1551

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_display_irq.c

1552

icp_irq_handler(display, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1553

else if (INTEL_PCH_TYPE(display) >= PCH_SPT)

drivers/gpu/drm/i915/display/intel_display_irq.c

1554

spt_irq_handler(display, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1556

cpt_irq_handler(display, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1562

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

1568

u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)

drivers/gpu/drm/i915/display/intel_display_irq.c

1575

intel_display_rpm_assert_block(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1577

iir = intel_de_read(display, GEN11_GU_MISC_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1579

intel_de_write(display, GEN11_GU_MISC_IIR, iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1581

intel_display_rpm_assert_unblock(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1586

void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

1589

intel_opregion_asle_intr(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

159

void ilk_update_display_irq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1592

void gen11_display_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1596

intel_display_rpm_assert_block(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1601

disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);

drivers/gpu/drm/i915/display/intel_display_irq.c

1603

intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1604

gen8_de_irq_handler(display, disp_ctl);

drivers/gpu/drm/i915/display/intel_display_irq.c

1605

intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

drivers/gpu/drm/i915/display/intel_display_irq.c

1607

intel_display_rpm_assert_unblock(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1610

static void i915gm_irq_cstate_wa_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1612

lockdep_assert_held(&display->drm->vblank_time_lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1620

if (display->irq.vblank_enabled++ == 0)

drivers/gpu/drm/i915/display/intel_display_irq.c

1621

intel_de_write(display, SCPD0,

drivers/gpu/drm/i915/display/intel_display_irq.c

1625

static void i915gm_irq_cstate_wa_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1627

lockdep_assert_held(&display->drm->vblank_time_lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1629

if (--display->irq.vblank_enabled == 0)

drivers/gpu/drm/i915/display/intel_display_irq.c

1630

intel_de_write(display, SCPD0,

drivers/gpu/drm/i915/display/intel_display_irq.c

1634

void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/intel_display_irq.c

1636

spin_lock_irq(&display->drm->vblank_time_lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1639

i915gm_irq_cstate_wa_enable(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

164

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1641

i915gm_irq_cstate_wa_disable(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1643

spin_unlock_irq(&display->drm->vblank_time_lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1648

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

165

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

1652

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1653

i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1654

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1661

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

1665

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1666

i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1667

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

167

new_val = display->irq.ilk_de_imr_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

1672

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

1674

i915gm_irq_cstate_wa_enable(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1681

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

1685

i915gm_irq_cstate_wa_disable(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1690

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

1694

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1695

i915_enable_pipestat(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

1697

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1704

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

1708

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1709

i915_disable_pipestat(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

171

if (new_val != display->irq.ilk_de_imr_mask &&

drivers/gpu/drm/i915/display/intel_display_irq.c

1711

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1716

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

1719

u32 bit = DISPLAY_VER(display) >= 7 ?

drivers/gpu/drm/i915/display/intel_display_irq.c

172

!drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1722

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1723

ilk_enable_display_irq(display, bit);

drivers/gpu/drm/i915/display/intel_display_irq.c

1724

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1729

if (HAS_PSR(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

173

display->irq.ilk_de_imr_mask = new_val;

drivers/gpu/drm/i915/display/intel_display_irq.c

1737

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_irq.c

174

intel_de_write(display, DEIMR, display->irq.ilk_de_imr_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

1740

u32 bit = DISPLAY_VER(display) >= 7 ?

drivers/gpu/drm/i915/display/intel_display_irq.c

1743

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1744

ilk_disable_display_irq(display, bit);

drivers/gpu/drm/i915/display/intel_display_irq.c

1745

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

175

intel_de_posting_read(display, DEIMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1751

struct intel_display *display = to_intel_display(intel_crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

1764

intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT);

drivers/gpu/drm/i915/display/intel_display_irq.c

1766

intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1773

struct intel_display *display =

drivers/gpu/drm/i915/display/intel_display_irq.c

1774

container_of(work, typeof(*display), irq.vblank_notify_work);

drivers/gpu/drm/i915/display/intel_display_irq.c

1775

int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count);

drivers/gpu/drm/i915/display/intel_display_irq.c

1777

intel_psr_notify_vblank_enable_disable(display, vblank_enable_count);

drivers/gpu/drm/i915/display/intel_display_irq.c

1783

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

179

void ilk_enable_display_irq(struct intel_display *display, u32 bits)

drivers/gpu/drm/i915/display/intel_display_irq.c

1790

if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0)

drivers/gpu/drm/i915/display/intel_display_irq.c

1791

schedule_work(&display->irq.vblank_notify_work);

drivers/gpu/drm/i915/display/intel_display_irq.c

1793

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1794

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);

drivers/gpu/drm/i915/display/intel_display_irq.c

1795

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1800

if (HAS_PSR(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

1809

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_irq.c

181

ilk_update_display_irq(display, bits, bits);

drivers/gpu/drm/i915/display/intel_display_irq.c

1816

spin_lock_irqsave(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1817

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);

drivers/gpu/drm/i915/display/intel_display_irq.c

1818

spin_unlock_irqrestore(&display->irq.lock, irqflags);

drivers/gpu/drm/i915/display/intel_display_irq.c

1820

if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0)

drivers/gpu/drm/i915/display/intel_display_irq.c

1821

schedule_work(&display->irq.vblank_notify_work);

drivers/gpu/drm/i915/display/intel_display_irq.c

184

void ilk_disable_display_irq(struct intel_display *display, u32 bits)

drivers/gpu/drm/i915/display/intel_display_irq.c

186

ilk_update_display_irq(display, bits, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1863

static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt)

drivers/gpu/drm/i915/display/intel_display_irq.c

1867

tmp = intel_de_read(display, DPINVGTT);

drivers/gpu/drm/i915/display/intel_display_irq.c

1883

intel_de_write(display, DPINVGTT, status);

drivers/gpu/drm/i915/display/intel_display_irq.c

1884

intel_de_write(display, DPINVGTT, enable << 16);

drivers/gpu/drm/i915/display/intel_display_irq.c

1887

static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt)

drivers/gpu/drm/i915/display/intel_display_irq.c

1891

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1896

intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers,

drivers/gpu/drm/i915/display/intel_display_irq.c

1901

void vlv_display_error_irq_ack(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1906

*eir = intel_de_read(display, VLV_EIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1909

vlv_page_table_error_irq_ack(display, dpinvgtt);

drivers/gpu/drm/i915/display/intel_display_irq.c

1911

intel_de_write(display, VLV_EIR, *eir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1918

emr = intel_de_read(display, VLV_EMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1919

intel_de_write(display, VLV_EMR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

1920

intel_de_write(display, VLV_EMR, emr);

drivers/gpu/drm/i915/display/intel_display_irq.c

1923

void vlv_display_error_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1926

drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);

drivers/gpu/drm/i915/display/intel_display_irq.c

1929

vlv_page_table_error_irq_handler(display, dpinvgtt);

drivers/gpu/drm/i915/display/intel_display_irq.c

1932

static void _vlv_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1934

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display_irq.c

1935

intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

drivers/gpu/drm/i915/display/intel_display_irq.c

1937

intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);

drivers/gpu/drm/i915/display/intel_display_irq.c

1939

error_reset(display, VLV_ERROR_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1941

i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1942

intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1944

i9xx_pipestat_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1946

irq_reset(display, VLV_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1947

display->irq.vlv_imr_mask = ~0u;

drivers/gpu/drm/i915/display/intel_display_irq.c

195

void bdw_update_port_irq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

1950

void vlv_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1952

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1953

if (display->irq.vlv_display_irqs_enabled)

drivers/gpu/drm/i915/display/intel_display_irq.c

1954

_vlv_display_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1955

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1958

void i9xx_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1960

if (HAS_HOTPLUG(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

1961

i915_hotplug_interrupt_update(display, 0xffffffff, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1962

intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

1965

i9xx_pipestat_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1968

u32 i9xx_display_irq_enable_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1975

if (DISPLAY_VER(display) >= 3)

drivers/gpu/drm/i915/display/intel_display_irq.c

1978

if (HAS_HOTPLUG(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

1984

void i915_display_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

1990

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1991

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1992

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1993

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

1995

i915_enable_asle_pipestat(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

1998

void i965_display_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2004

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2005

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2006

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2007

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2008

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

201

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2010

i915_enable_asle_pipestat(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2019

static void _vlv_display_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2025

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display_irq.c

2026

intel_de_write(display, DPINVGTT,

drivers/gpu/drm/i915/display/intel_display_irq.c

203

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

2030

intel_de_write(display, DPINVGTT,

drivers/gpu/drm/i915/display/intel_display_irq.c

2034

error_init(display, VLV_ERROR_REGS, ~vlv_error_mask());

drivers/gpu/drm/i915/display/intel_display_irq.c

2038

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2039

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

2040

i915_enable_pipestat(display, pipe, pipestat_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

2049

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display_irq.c

205

if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)))

drivers/gpu/drm/i915/display/intel_display_irq.c

2053

drm_WARN_ON(display->drm, display->irq.vlv_imr_mask != ~0u);

drivers/gpu/drm/i915/display/intel_display_irq.c

2055

display->irq.vlv_imr_mask = ~enable_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

2057

irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

2060

void vlv_display_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2062

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2063

if (display->irq.vlv_display_irqs_enabled)

drivers/gpu/drm/i915/display/intel_display_irq.c

2064

_vlv_display_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2065

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2068

static void ibx_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2070

if (HAS_PCH_NOP(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2073

irq_reset(display, SDE_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2075

if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2076

intel_de_write(display, SERR_INT, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2079

void ilk_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

208

old_val = intel_de_read(display, GEN8_DE_PORT_IMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

2081

irq_reset(display, DE_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2082

display->irq.ilk_de_imr_mask = ~0u;

drivers/gpu/drm/i915/display/intel_display_irq.c

2084

if (DISPLAY_VER(display) == 7)

drivers/gpu/drm/i915/display/intel_display_irq.c

2085

intel_de_write(display, GEN7_ERR_INT, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2087

if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2088

intel_de_write(display, EDP_PSR_IMR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2089

intel_de_write(display, EDP_PSR_IIR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2092

ibx_display_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2095

void gen8_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2099

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2102

intel_de_write(display, EDP_PSR_IMR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2103

intel_de_write(display, EDP_PSR_IIR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2105

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

2106

if (intel_display_power_is_enabled(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2108

irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

2110

irq_reset(display, GEN8_DE_PORT_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2111

irq_reset(display, GEN8_DE_MISC_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2113

if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2114

ibx_display_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2117

void gen11_display_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2123

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2126

intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

2128

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2131

for_each_cpu_transcoder_masked(display, trans, trans_mask) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2135

if (!intel_display_power_is_enabled(display, domain))

drivers/gpu/drm/i915/display/intel_display_irq.c

2138

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2139

TRANS_PSR_IMR(display, trans),

drivers/gpu/drm/i915/display/intel_display_irq.c

2141

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2142

TRANS_PSR_IIR(display, trans),

drivers/gpu/drm/i915/display/intel_display_irq.c

2146

intel_de_write(display, EDP_PSR_IMR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2147

intel_de_write(display, EDP_PSR_IIR, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

215

intel_de_write(display, GEN8_DE_PORT_IMR, new_val);

drivers/gpu/drm/i915/display/intel_display_irq.c

2150

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

2151

if (intel_display_power_is_enabled(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2153

irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

2155

irq_reset(display, GEN8_DE_PORT_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2156

irq_reset(display, GEN8_DE_MISC_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2158

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_irq.c

2159

irq_reset(display, PICAINTERRUPT_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

216

intel_de_posting_read(display, GEN8_DE_PORT_IMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

2161

irq_reset(display, GEN11_DE_HPD_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2163

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_display_irq.c

2164

irq_reset(display, SDE_IRQ_REGS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2167

void gen8_irq_power_well_post_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2171

gen8_de_pipe_flip_done_mask(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2174

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2176

if (!intel_parent_irq_enabled(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2177

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2181

for_each_pipe_masked(display, pipe, pipe_mask)

drivers/gpu/drm/i915/display/intel_display_irq.c

2182

irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

drivers/gpu/drm/i915/display/intel_display_irq.c

2183

display->irq.de_pipe_imr_mask[pipe],

drivers/gpu/drm/i915/display/intel_display_irq.c

2184

~display->irq.de_pipe_imr_mask[pipe] | extra_ier);

drivers/gpu/drm/i915/display/intel_display_irq.c

2186

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2189

void gen8_irq_power_well_pre_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2194

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2196

if (!intel_parent_irq_enabled(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2197

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2201

for_each_pipe_masked(display, pipe, pipe_mask)

drivers/gpu/drm/i915/display/intel_display_irq.c

2202

irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

2204

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2207

intel_parent_irq_synchronize(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2221

static void ibx_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2225

if (HAS_PCH_NOP(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2228

if (HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2230

else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2235

irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2238

void valleyview_enable_display_irqs(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2240

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2242

if (display->irq.vlv_display_irqs_enabled)

drivers/gpu/drm/i915/display/intel_display_irq.c

2245

display->irq.vlv_display_irqs_enabled = true;

drivers/gpu/drm/i915/display/intel_display_irq.c

2247

if (intel_parent_irq_enabled(display)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2248

_vlv_display_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2249

_vlv_display_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2253

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2256

void valleyview_disable_display_irqs(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2258

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2260

if (!display->irq.vlv_display_irqs_enabled)

drivers/gpu/drm/i915/display/intel_display_irq.c

2263

display->irq.vlv_display_irqs_enabled = false;

drivers/gpu/drm/i915/display/intel_display_irq.c

2265

if (intel_parent_irq_enabled(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2266

_vlv_display_irq_reset(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2268

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

227

static void bdw_update_pipe_irq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2271

void ilk_de_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2275

if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2296

if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2297

assert_iir_is_zero(display, EDP_PSR_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

2301

if (display->platform.ironlake && display->platform.mobile)

drivers/gpu/drm/i915/display/intel_display_irq.c

2304

display->irq.ilk_de_imr_mask = ~display_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

2306

ibx_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2308

irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask,

drivers/gpu/drm/i915/display/intel_display_irq.c

2312

static void mtp_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2313

static void icp_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2315

void gen8_de_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2317

u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |

drivers/gpu/drm/i915/display/intel_display_irq.c

2320

u32 de_port_masked = gen8_de_port_aux_mask(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2327

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

233

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2330

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_irq.c

2331

mtp_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2332

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_display_irq.c

2333

icp_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2334

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2335

ibx_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2337

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_display_irq.c

2340

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_irq.c

2343

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2346

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2349

if (intel_bios_is_dsi_present(display, &port))

drivers/gpu/drm/i915/display/intel_display_irq.c

235

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

2353

if (HAS_DBUF_OVERLAP_DETECTION(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2356

if (HAS_DSB(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2362

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_display_irq.c

2367

gen8_de_pipe_flip_done_mask(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

237

if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)))

drivers/gpu/drm/i915/display/intel_display_irq.c

2370

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_irq.c

2372

else if (display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_display_irq.c

2375

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2378

for_each_cpu_transcoder_masked(display, trans, trans_mask) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2382

if (!intel_display_power_is_enabled(display, domain))

drivers/gpu/drm/i915/display/intel_display_irq.c

2385

assert_iir_is_zero(display, TRANS_PSR_IIR(display, trans));

drivers/gpu/drm/i915/display/intel_display_irq.c

2388

assert_iir_is_zero(display, EDP_PSR_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

2391

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2392

display->irq.de_pipe_imr_mask[pipe] = ~de_pipe_masked;

drivers/gpu/drm/i915/display/intel_display_irq.c

2394

if (intel_display_power_is_enabled(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

2396

irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

drivers/gpu/drm/i915/display/intel_display_irq.c

2397

display->irq.de_pipe_imr_mask[pipe],

drivers/gpu/drm/i915/display/intel_display_irq.c

240

new_val = display->irq.de_pipe_imr_mask[pipe];

drivers/gpu/drm/i915/display/intel_display_irq.c

2401

irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);

drivers/gpu/drm/i915/display/intel_display_irq.c

2402

irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);

drivers/gpu/drm/i915/display/intel_display_irq.c

2404

if (IS_DISPLAY_VER(display, 11, 13)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2409

irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables);

drivers/gpu/drm/i915/display/intel_display_irq.c

2413

u32 xelpdp_pica_aux_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2417

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_display_irq.c

2423

static void mtp_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2426

u32 de_hpd_mask = xelpdp_pica_aux_mask(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2430

irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables);

drivers/gpu/drm/i915/display/intel_display_irq.c

2432

irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

2435

static void icp_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2439

irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

244

if (new_val != display->irq.de_pipe_imr_mask[pipe]) {

drivers/gpu/drm/i915/display/intel_display_irq.c

2442

void gen11_de_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2444

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2447

gen8_de_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2449

intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

drivers/gpu/drm/i915/display/intel_display_irq.c

245

display->irq.de_pipe_imr_mask[pipe] = new_val;

drivers/gpu/drm/i915/display/intel_display_irq.c

2452

void dg1_de_irq_postinstall(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2454

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2457

gen8_de_irq_postinstall(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2458

intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

drivers/gpu/drm/i915/display/intel_display_irq.c

246

intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_pipe_imr_mask[pipe]);

drivers/gpu/drm/i915/display/intel_display_irq.c

2461

void intel_display_irq_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2463

spin_lock_init(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

2465

display->drm->vblank_disable_immediate = true;

drivers/gpu/drm/i915/display/intel_display_irq.c

2467

intel_hotplug_irq_init(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

2469

INIT_WORK(&display->irq.vblank_notify_work,

drivers/gpu/drm/i915/display/intel_display_irq.c

247

intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

2478

intel_display_irq_snapshot_capture(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

2486

if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

2487

snapshot->derrmr = intel_de_read(display, DERRMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

251

void bdw_enable_pipe_irq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

254

bdw_update_pipe_irq(display, pipe, bits, bits);

drivers/gpu/drm/i915/display/intel_display_irq.c

257

void bdw_disable_pipe_irq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

260

bdw_update_pipe_irq(display, pipe, bits, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

269

void ibx_display_interrupt_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

273

u32 sdeimr = intel_de_read(display, SDEIMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

278

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

280

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

282

if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)))

drivers/gpu/drm/i915/display/intel_display_irq.c

285

intel_de_write(display, SDEIMR, sdeimr);

drivers/gpu/drm/i915/display/intel_display_irq.c

286

intel_de_posting_read(display, SDEIMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

289

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)

drivers/gpu/drm/i915/display/intel_display_irq.c

291

ibx_display_interrupt_update(display, bits, bits);

drivers/gpu/drm/i915/display/intel_display_irq.c

294

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)

drivers/gpu/drm/i915/display/intel_display_irq.c

296

ibx_display_interrupt_update(display, bits, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

299

u32 i915_pipestat_enable_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

302

u32 status_mask = display->irq.pipestat_irq_mask[pipe];

drivers/gpu/drm/i915/display/intel_display_irq.c

305

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

307

if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_display_irq.c

314

if (drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

321

if (drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

33

static void irq_reset(struct intel_display *display, struct i915_irq_regs regs)

drivers/gpu/drm/i915/display/intel_display_irq.c

334

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

343

void i915_enable_pipestat(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

346

i915_reg_t reg = PIPESTAT(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

349

drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,

drivers/gpu/drm/i915/display/intel_display_irq.c

35

intel_de_write(display, regs.imr, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

353

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

354

drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display));

drivers/gpu/drm/i915/display/intel_display_irq.c

356

if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)

drivers/gpu/drm/i915/display/intel_display_irq.c

359

display->irq.pipestat_irq_mask[pipe] |= status_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

36

intel_de_posting_read(display, regs.imr);

drivers/gpu/drm/i915/display/intel_display_irq.c

360

enable_mask = i915_pipestat_enable_mask(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

362

intel_de_write(display, reg, enable_mask | status_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

363

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_irq.c

366

void i915_disable_pipestat(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

369

i915_reg_t reg = PIPESTAT(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

372

drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,

drivers/gpu/drm/i915/display/intel_display_irq.c

376

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

377

drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display));

drivers/gpu/drm/i915/display/intel_display_irq.c

379

if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0)

drivers/gpu/drm/i915/display/intel_display_irq.c

38

intel_de_write(display, regs.ier, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

382

display->irq.pipestat_irq_mask[pipe] &= ~status_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

383

enable_mask = i915_pipestat_enable_mask(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

385

intel_de_write(display, reg, enable_mask | status_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

386

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_irq.c

389

static bool i915_has_legacy_blc_interrupt(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

391

if (display->platform.i85x)

drivers/gpu/drm/i915/display/intel_display_irq.c

394

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_display_irq.c

397

return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile;

drivers/gpu/drm/i915/display/intel_display_irq.c

401

static void i915_enable_asle_pipestat(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

403

if (!intel_opregion_asle_present(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

406

if (!i915_has_legacy_blc_interrupt(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

409

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

41

intel_de_write(display, regs.iir, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

411

i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

412

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_display_irq.c

413

i915_enable_pipestat(display, PIPE_A,

drivers/gpu/drm/i915/display/intel_display_irq.c

416

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

42

intel_de_posting_read(display, regs.iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

420

static void display_pipe_crc_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

426

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

43

intel_de_write(display, regs.iir, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

44

intel_de_posting_read(display, regs.iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

442

(DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

455

display_pipe_crc_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

462

static void flip_done_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

465

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

467

spin_lock(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

475

spin_unlock(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

478

static void hsw_pipe_crc_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

481

display_pipe_crc_irq_handler(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

482

intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

486

static void ivb_pipe_crc_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

489

display_pipe_crc_irq_handler(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

490

intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

491

intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

492

intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

493

intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

494

intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));

drivers/gpu/drm/i915/display/intel_display_irq.c

497

static void i9xx_pipe_crc_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

50

static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_display_irq.c

502

if (DISPLAY_VER(display) >= 3)

drivers/gpu/drm/i915/display/intel_display_irq.c

503

res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

507

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_display_irq.c

508

res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

512

display_pipe_crc_irq_handler(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

513

intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

514

intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

515

intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

519

static void i9xx_pipestat_irq_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

52

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_irq.c

523

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

524

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_display_irq.c

525

PIPESTAT(display, pipe),

drivers/gpu/drm/i915/display/intel_display_irq.c

528

display->irq.pipestat_irq_mask[pipe] = 0;

drivers/gpu/drm/i915/display/intel_display_irq.c

532

void i9xx_pipestat_irq_ack(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

537

spin_lock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

539

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_display_irq.c

540

!display->irq.vlv_display_irqs_enabled) {

drivers/gpu/drm/i915/display/intel_display_irq.c

541

spin_unlock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

545

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

57

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_display_irq.c

573

status_mask |= display->irq.pipestat_irq_mask[pipe];

drivers/gpu/drm/i915/display/intel_display_irq.c

578

reg = PIPESTAT(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

579

pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

580

enable_mask = i915_pipestat_enable_mask(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

592

intel_de_write(display, reg, pipe_stats[pipe]);

drivers/gpu/drm/i915/display/intel_display_irq.c

593

intel_de_write(display, reg, enable_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

596

spin_unlock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_irq.c

599

void i915_pipestat_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

60

intel_de_write(display, reg, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

605

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

607

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

61

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_irq.c

613

i9xx_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

616

intel_cpu_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

62

intel_de_write(display, reg, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

620

intel_opregion_asle_intr(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

623

void i965_pipestat_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

629

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

63

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_irq.c

631

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

637

i9xx_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

640

intel_cpu_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

644

intel_opregion_asle_intr(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

647

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

650

void valleyview_pipestat_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.c

655

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

657

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

66

static void irq_init(struct intel_display *display, struct i915_irq_regs regs,

drivers/gpu/drm/i915/display/intel_display_irq.c

660

flip_done_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

663

i9xx_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

666

intel_cpu_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

670

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

673

static void ibx_irq_handler(struct intel_display *display, u32 pch_iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

678

ibx_hpd_irq_handler(display, hotplug_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

683

drm_dbg(display->drm, "PCH audio power change on port %d\n",

drivers/gpu/drm/i915/display/intel_display_irq.c

688

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

69

assert_iir_is_zero(display, regs.iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

691

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

694

drm_dbg(display->drm, "PCH HDCP audio interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

697

drm_dbg(display->drm, "PCH transcoder audio interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

700

drm_err(display->drm, "PCH poison interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

703

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

704

drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",

drivers/gpu/drm/i915/display/intel_display_irq.c

706

intel_de_read(display, FDI_RX_IIR(pipe)));

drivers/gpu/drm/i915/display/intel_display_irq.c

71

intel_de_write(display, regs.ier, ier_val);

drivers/gpu/drm/i915/display/intel_display_irq.c

710

drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

713

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_display_irq.c

717

intel_pch_fifo_underrun_irq_handler(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_irq.c

72

intel_de_write(display, regs.imr, imr_val);

drivers/gpu/drm/i915/display/intel_display_irq.c

720

intel_pch_fifo_underrun_irq_handler(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_irq.c

73

intel_de_posting_read(display, regs.imr);

drivers/gpu/drm/i915/display/intel_display_irq.c

756

static void ivb_err_int_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

758

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

drivers/gpu/drm/i915/display/intel_display_irq.c

76

static void error_reset(struct intel_display *display, struct i915_error_regs regs)

drivers/gpu/drm/i915/display/intel_display_irq.c

762

drm_err(display->drm, "Poison interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

765

drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

768

drm_err_ratelimited(display->drm, "Invalid PTE data\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

770

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

774

intel_cpu_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

777

if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_display_irq.c

778

ivb_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

78

intel_de_write(display, regs.emr, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

780

hsw_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

785

intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers,

drivers/gpu/drm/i915/display/intel_display_irq.c

789

intel_de_write(display, GEN7_ERR_INT, err_int);

drivers/gpu/drm/i915/display/intel_display_irq.c

79

intel_de_posting_read(display, regs.emr);

drivers/gpu/drm/i915/display/intel_display_irq.c

792

static void cpt_serr_int_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

794

u32 serr_int = intel_de_read(display, SERR_INT);

drivers/gpu/drm/i915/display/intel_display_irq.c

798

drm_err(display->drm, "PCH poison interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

800

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

802

intel_pch_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

804

intel_de_write(display, SERR_INT, serr_int);

drivers/gpu/drm/i915/display/intel_display_irq.c

807

static void cpt_irq_handler(struct intel_display *display, u32 pch_iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

81

intel_de_write(display, regs.eir, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

812

ibx_hpd_irq_handler(display, hotplug_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

817

drm_dbg(display->drm, "PCH audio power change on port %c\n",

drivers/gpu/drm/i915/display/intel_display_irq.c

82

intel_de_posting_read(display, regs.eir);

drivers/gpu/drm/i915/display/intel_display_irq.c

822

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

825

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

828

drm_dbg(display->drm, "Audio CP request interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

83

intel_de_write(display, regs.eir, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

831

drm_dbg(display->drm, "Audio CP change interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

834

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_irq.c

835

drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",

drivers/gpu/drm/i915/display/intel_display_irq.c

837

intel_de_read(display, FDI_RX_IIR(pipe)));

drivers/gpu/drm/i915/display/intel_display_irq.c

84

intel_de_posting_read(display, regs.eir);

drivers/gpu/drm/i915/display/intel_display_irq.c

841

cpt_serr_int_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

87

static void error_init(struct intel_display *display, struct i915_error_regs regs,

drivers/gpu/drm/i915/display/intel_display_irq.c

870

static void ilk_gtt_fault_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_irq.c

875

gtt_fault = intel_de_read(display, ILK_GTT_FAULT);

drivers/gpu/drm/i915/display/intel_display_irq.c

876

intel_de_write(display, ILK_GTT_FAULT, gtt_fault);

drivers/gpu/drm/i915/display/intel_display_irq.c

879

drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

882

drm_err_ratelimited(display->drm, "Invalid PTE data\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

884

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

889

intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers,

drivers/gpu/drm/i915/display/intel_display_irq.c

894

static void _ilk_display_irq_handler(struct intel_display *display, u32 de_iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

90

intel_de_write(display, regs.eir, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

900

ilk_hpd_irq_handler(display, hotplug_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

903

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

906

intel_opregion_asle_intr(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

909

drm_err(display->drm, "Poison interrupt\n");

drivers/gpu/drm/i915/display/intel_display_irq.c

91

intel_de_posting_read(display, regs.eir);

drivers/gpu/drm/i915/display/intel_display_irq.c

912

ilk_gtt_fault_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

914

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

916

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

919

flip_done_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

92

intel_de_write(display, regs.eir, 0xffffffff);

drivers/gpu/drm/i915/display/intel_display_irq.c

922

intel_cpu_fifo_underrun_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

925

i9xx_pipe_crc_irq_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

93

intel_de_posting_read(display, regs.eir);

drivers/gpu/drm/i915/display/intel_display_irq.c

930

u32 pch_iir = intel_de_read(display, SDEIIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

932

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_display_irq.c

933

cpt_irq_handler(display, pch_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

935

ibx_irq_handler(display, pch_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

938

intel_de_write(display, SDEIIR, pch_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

941

if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT)

drivers/gpu/drm/i915/display/intel_display_irq.c

942

ilk_display_rps_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

945

static void _ivb_display_irq_handler(struct intel_display *display, u32 de_iir)

drivers/gpu/drm/i915/display/intel_display_irq.c

95

intel_de_write(display, regs.emr, emr_val);

drivers/gpu/drm/i915/display/intel_display_irq.c

951

ilk_hpd_irq_handler(display, hotplug_trigger);

drivers/gpu/drm/i915/display/intel_display_irq.c

954

ivb_err_int_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

959

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_display_irq.c

96

intel_de_posting_read(display, regs.emr);

drivers/gpu/drm/i915/display/intel_display_irq.c

963

psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0);

drivers/gpu/drm/i915/display/intel_display_irq.c

970

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

973

intel_opregion_asle_intr(display);

drivers/gpu/drm/i915/display/intel_display_irq.c

975

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_irq.c

977

intel_handle_vblank(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

980

flip_done_handler(display, pipe);

drivers/gpu/drm/i915/display/intel_display_irq.c

984

if (!HAS_PCH_NOP(display) && (de_iir & DE_PCH_EVENT_IVB)) {

drivers/gpu/drm/i915/display/intel_display_irq.c

985

u32 pch_iir = intel_de_read(display, SDEIIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

987

cpt_irq_handler(display, pch_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

990

intel_de_write(display, SDEIIR, pch_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

994

void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier)

drivers/gpu/drm/i915/display/intel_display_irq.c

997

*de_ier = intel_de_read_fw(display, DEIER);

drivers/gpu/drm/i915/display/intel_display_irq.c

998

intel_de_write_fw(display, DEIER, *de_ier & ~DE_MASTER_IRQ_CONTROL);

drivers/gpu/drm/i915/display/intel_display_irq.h

19

u32 xelpdp_pica_aux_mask(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

21

void valleyview_enable_display_irqs(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

22

void valleyview_disable_display_irqs(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

24

void ilk_update_display_irq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.h

26

void ilk_enable_display_irq(struct intel_display *display, u32 bits);

drivers/gpu/drm/i915/display/intel_display_irq.h

27

void ilk_disable_display_irq(struct intel_display *display, u32 bits);

drivers/gpu/drm/i915/display/intel_display_irq.h

29

void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);

drivers/gpu/drm/i915/display/intel_display_irq.h

30

void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

drivers/gpu/drm/i915/display/intel_display_irq.h

31

void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

drivers/gpu/drm/i915/display/intel_display_irq.h

33

void ibx_display_interrupt_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_irq.h

35

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);

drivers/gpu/drm/i915/display/intel_display_irq.h

36

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);

drivers/gpu/drm/i915/display/intel_display_irq.h

38

void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask);

drivers/gpu/drm/i915/display/intel_display_irq.h

39

void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask);

drivers/gpu/drm/i915/display/intel_display_irq.h

52

void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);

drivers/gpu/drm/i915/display/intel_display_irq.h

53

void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);

drivers/gpu/drm/i915/display/intel_display_irq.h

54

bool ilk_display_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

55

void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);

drivers/gpu/drm/i915/display/intel_display_irq.h

56

void gen11_display_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

58

u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);

drivers/gpu/drm/i915/display/intel_display_irq.h

59

void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);

drivers/gpu/drm/i915/display/intel_display_irq.h

61

void i9xx_display_irq_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

62

void ilk_display_irq_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

63

void vlv_display_irq_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

64

void gen8_display_irq_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

65

void gen11_display_irq_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

67

u32 i9xx_display_irq_enable_mask(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

68

void i915_display_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

69

void i965_display_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

70

void vlv_display_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

71

void ilk_de_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

72

void gen8_de_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

73

void gen11_de_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

74

void dg1_de_irq_postinstall(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

76

u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_display_irq.h

77

void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

drivers/gpu/drm/i915/display/intel_display_irq.h

78

void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

drivers/gpu/drm/i915/display/intel_display_irq.h

80

void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

drivers/gpu/drm/i915/display/intel_display_irq.h

82

void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

drivers/gpu/drm/i915/display/intel_display_irq.h

83

void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

drivers/gpu/drm/i915/display/intel_display_irq.h

84

void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);

drivers/gpu/drm/i915/display/intel_display_irq.h

86

void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);

drivers/gpu/drm/i915/display/intel_display_irq.h

87

void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);

drivers/gpu/drm/i915/display/intel_display_irq.h

89

void intel_display_irq_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_irq.h

91

void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);

drivers/gpu/drm/i915/display/intel_display_irq.h

93

struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.c

1015

drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);

drivers/gpu/drm/i915/display/intel_display_power.c

1027

int intel_power_domains_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1029

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1031

display->params.disable_power_well =

drivers/gpu/drm/i915/display/intel_display_power.c

1032

sanitize_disable_power_well_option(display->params.disable_power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

1034

get_allowed_dc_mask(display, display->params.enable_dc);

drivers/gpu/drm/i915/display/intel_display_power.c

1037

sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);

drivers/gpu/drm/i915/display/intel_display_power.c

1053

void intel_power_domains_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1055

intel_display_power_map_cleanup(&display->power.domains);

drivers/gpu/drm/i915/display/intel_display_power.c

1058

static void intel_power_domains_sync_hw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1060

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1064

for_each_power_well(display, power_well)

drivers/gpu/drm/i915/display/intel_display_power.c

1065

intel_power_well_sync_hw(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

1069

static void gen9_dbuf_slice_set(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

1075

intel_de_rmw(display, reg, DBUF_POWER_REQUEST,

drivers/gpu/drm/i915/display/intel_display_power.c

1077

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_power.c

1080

state = intel_de_read(display, reg) & DBUF_POWER_STATE;

drivers/gpu/drm/i915/display/intel_display_power.c

1081

drm_WARN(display->drm, enable != state,

drivers/gpu/drm/i915/display/intel_display_power.c

1086

void gen9_dbuf_slices_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

1089

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1090

u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;

drivers/gpu/drm/i915/display/intel_display_power.c

1093

drm_WARN(display->drm, req_slices & ~slice_mask,

drivers/gpu/drm/i915/display/intel_display_power.c

1097

drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n",

drivers/gpu/drm/i915/display/intel_display_power.c

1109

for_each_dbuf_slice(display, slice)

drivers/gpu/drm/i915/display/intel_display_power.c

1110

gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));

drivers/gpu/drm/i915/display/intel_display_power.c

1112

display->dbuf.enabled_slices = req_slices;

drivers/gpu/drm/i915/display/intel_display_power.c

1117

static void gen9_dbuf_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1121

display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1123

slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;

drivers/gpu/drm/i915/display/intel_display_power.c

1125

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_power.c

1126

intel_pmdemand_program_dbuf(display, slices_mask);

drivers/gpu/drm/i915/display/intel_display_power.c

1132

gen9_dbuf_slices_update(display, slices_mask);

drivers/gpu/drm/i915/display/intel_display_power.c

1135

static void gen9_dbuf_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1137

gen9_dbuf_slices_update(display, 0);

drivers/gpu/drm/i915/display/intel_display_power.c

1139

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_power.c

1140

intel_pmdemand_program_dbuf(display, 0);

drivers/gpu/drm/i915/display/intel_display_power.c

1143

static void gen12_dbuf_slices_config(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1147

for_each_dbuf_slice(display, slice)

drivers/gpu/drm/i915/display/intel_display_power.c

1148

intel_de_rmw(display, DBUF_CTL_S(slice),

drivers/gpu/drm/i915/display/intel_display_power.c

1153

static void icl_mbus_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1155

unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;

drivers/gpu/drm/i915/display/intel_display_power.c

1158

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_power.c

1175

if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/intel_display_power.c

1179

intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1182

static void hsw_assert_cdclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1184

u32 val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1193

drm_err(display->drm, "CDCLK source is not LCPLL\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1196

drm_err(display->drm, "LCPLL is disabled\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1199

drm_err(display->drm, "LCPLL not using non-SSC reference\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1202

static void assert_can_disable_lcpll(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1206

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/intel_display_power.c

1207

INTEL_DISPLAY_STATE_WARN(display, crtc->active,

drivers/gpu/drm/i915/display/intel_display_power.c

1211

INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),

drivers/gpu/drm/i915/display/intel_display_power.c

1213

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1214

intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1216

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1217

intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1219

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1220

intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1222

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1223

intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,

drivers/gpu/drm/i915/display/intel_display_power.c

1225

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1226

intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1228

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display_power.c

1229

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1230

intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1232

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1233

intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1235

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1236

(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),

drivers/gpu/drm/i915/display/intel_display_power.c

1238

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1239

intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1248

INTEL_DISPLAY_STATE_WARN(display, intel_parent_irq_enabled(display),

drivers/gpu/drm/i915/display/intel_display_power.c

1252

static u32 hsw_read_dcomp(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1254

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display_power.c

1255

return intel_de_read(display, D_COMP_HSW);

drivers/gpu/drm/i915/display/intel_display_power.c

1257

return intel_de_read(display, D_COMP_BDW);

drivers/gpu/drm/i915/display/intel_display_power.c

1260

static void hsw_write_dcomp(struct intel_display *display, u32 val)

drivers/gpu/drm/i915/display/intel_display_power.c

1262

if (display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display_power.c

1263

if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val))

drivers/gpu/drm/i915/display/intel_display_power.c

1264

drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1266

intel_de_write(display, D_COMP_BDW, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1267

intel_de_posting_read(display, D_COMP_BDW);

drivers/gpu/drm/i915/display/intel_display_power.c

1279

static void hsw_disable_lcpll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

1285

assert_can_disable_lcpll(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1287

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1291

intel_de_write(display, LCPLL_CTL, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1293

ret = intel_de_wait_for_set_us(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_display_power.c

1296

drm_err(display->drm, "Switching to FCLK failed\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1298

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1302

intel_de_write(display, LCPLL_CTL, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1303

intel_de_posting_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1305

if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))

drivers/gpu/drm/i915/display/intel_display_power.c

1306

drm_err(display->drm, "LCPLL still locked\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1308

val = hsw_read_dcomp(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1310

hsw_write_dcomp(display, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1313

ret = poll_timeout_us(val = hsw_read_dcomp(display),

drivers/gpu/drm/i915/display/intel_display_power.c

1317

drm_err(display->drm, "D_COMP RCOMP still in progress\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1320

intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);

drivers/gpu/drm/i915/display/intel_display_power.c

1321

intel_de_posting_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1329

static void hsw_restore_lcpll(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1334

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1344

intel_parent_pc8_block(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1348

intel_de_write(display, LCPLL_CTL, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1349

intel_de_posting_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1352

val = hsw_read_dcomp(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1355

hsw_write_dcomp(display, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1357

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1359

intel_de_write(display, LCPLL_CTL, val);

drivers/gpu/drm/i915/display/intel_display_power.c

1361

if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))

drivers/gpu/drm/i915/display/intel_display_power.c

1362

drm_err(display->drm, "LCPLL not locked yet\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1365

intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);

drivers/gpu/drm/i915/display/intel_display_power.c

1367

ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,

drivers/gpu/drm/i915/display/intel_display_power.c

1370

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

1374

intel_parent_pc8_unblock(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1376

intel_update_cdclk(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1377

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

drivers/gpu/drm/i915/display/intel_display_power.c

1403

static void hsw_enable_pc8(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1405

drm_dbg_kms(display->drm, "Enabling package C8+\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1407

if (HAS_PCH_LPT_LP(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1408

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_display_power.c

1411

lpt_disable_clkout_dp(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1412

hsw_disable_lcpll(display, true, true);

drivers/gpu/drm/i915/display/intel_display_power.c

1415

static void hsw_disable_pc8(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1417

drm_dbg_kms(display->drm, "Disabling package C8+\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1419

hsw_restore_lcpll(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1420

intel_init_pch_refclk(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1424

intel_clock_gating_init(display->drm);

drivers/gpu/drm/i915/display/intel_display_power.c

1428

static void intel_pch_reset_handshake(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

1434

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/intel_display_power.c

1437

if (display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_display_power.c

1445

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_power.c

1448

intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);

drivers/gpu/drm/i915/display/intel_display_power.c

1451

static void skl_display_core_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

1454

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1457

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power.c

1460

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

drivers/gpu/drm/i915/display/intel_display_power.c

1462

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1468

well = lookup_power_well(display, SKL_DISP_PW_1);

drivers/gpu/drm/i915/display/intel_display_power.c

1469

intel_power_well_enable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1471

well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);

drivers/gpu/drm/i915/display/intel_display_power.c

1472

intel_power_well_enable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1476

intel_cdclk_init_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1478

gen9_dbuf_enable(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1481

intel_dmc_load_program(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1484

static void skl_display_core_uninit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1486

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1489

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1492

gen9_disable_dc_states(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1495

gen9_dbuf_disable(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1497

intel_cdclk_uninit_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1510

well = lookup_power_well(display, SKL_DISP_PW_1);

drivers/gpu/drm/i915/display/intel_display_power.c

1511

intel_power_well_disable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1518

static void bxt_display_core_init(struct intel_display *display, bool resume)

drivers/gpu/drm/i915/display/intel_display_power.c

1520

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1523

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power.c

1531

intel_pch_reset_handshake(display, false);

drivers/gpu/drm/i915/display/intel_display_power.c

1533

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1539

well = lookup_power_well(display, SKL_DISP_PW_1);

drivers/gpu/drm/i915/display/intel_display_power.c

1540

intel_power_well_enable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1544

intel_cdclk_init_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1546

gen9_dbuf_enable(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1549

intel_dmc_load_program(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1552

static void bxt_display_core_uninit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1554

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1557

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1560

gen9_disable_dc_states(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1563

gen9_dbuf_disable(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1565

intel_cdclk_uninit_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1576

well = lookup_power_well(display, SKL_DISP_PW_1);

drivers/gpu/drm/i915/display/intel_display_power.c

1577

intel_power_well_disable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1614

static void tgl_bw_buddy_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1616

const struct dram_info *dram_info = intel_dram_info(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1618

unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;

drivers/gpu/drm/i915/display/intel_display_power.c

1622

if (display->platform.dgfx && !display->platform.dg1)

drivers/gpu/drm/i915/display/intel_display_power.c

1625

if (display->platform.alderlake_s ||

drivers/gpu/drm/i915/display/intel_display_power.c

1626

(display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)))

drivers/gpu/drm/i915/display/intel_display_power.c

1638

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

1641

intel_de_write(display, BW_BUDDY_CTL(i),

drivers/gpu/drm/i915/display/intel_display_power.c

1645

intel_de_write(display, BW_BUDDY_PAGE_MASK(i),

drivers/gpu/drm/i915/display/intel_display_power.c

1649

if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/intel_display_power.c

1650

intel_de_rmw(display, BW_BUDDY_CTL(i),

drivers/gpu/drm/i915/display/intel_display_power.c

1657

static void icl_display_core_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

1660

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1663

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power.c

1666

if (INTEL_PCH_TYPE(display) >= PCH_TGP &&

drivers/gpu/drm/i915/display/intel_display_power.c

1667

INTEL_PCH_TYPE(display) < PCH_DG1)

drivers/gpu/drm/i915/display/intel_display_power.c

1668

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,

drivers/gpu/drm/i915/display/intel_display_power.c

1672

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

drivers/gpu/drm/i915/display/intel_display_power.c

1674

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1678

intel_combo_phy_init(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1685

well = lookup_power_well(display, SKL_DISP_PW_1);

drivers/gpu/drm/i915/display/intel_display_power.c

1686

intel_power_well_enable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1689

if (DISPLAY_VER(display) == 14)

drivers/gpu/drm/i915/display/intel_display_power.c

1690

intel_de_rmw(display, DC_STATE_EN,

drivers/gpu/drm/i915/display/intel_display_power.c

1694

intel_cdclk_init_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1696

if (DISPLAY_VER(display) == 12 || display->platform.dg2)

drivers/gpu/drm/i915/display/intel_display_power.c

1697

gen12_dbuf_slices_config(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1700

gen9_dbuf_enable(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1703

icl_mbus_init(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1706

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_power.c

1707

tgl_bw_buddy_init(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1710

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_display_power.c

1711

intel_snps_phy_wait_for_calibration(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1714

if (DISPLAY_VERx100(display) == 1401)

drivers/gpu/drm/i915/display/intel_display_power.c

1715

intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);

drivers/gpu/drm/i915/display/intel_display_power.c

1718

intel_dmc_load_program(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1721

if (IS_DISPLAY_VERx100(display, 1200, 1300))

drivers/gpu/drm/i915/display/intel_display_power.c

1722

intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0,

drivers/gpu/drm/i915/display/intel_display_power.c

1727

if (DISPLAY_VER(display) == 13)

drivers/gpu/drm/i915/display/intel_display_power.c

1728

intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);

drivers/gpu/drm/i915/display/intel_display_power.c

1731

if (DISPLAY_VER(display) == 20) {

drivers/gpu/drm/i915/display/intel_display_power.c

1732

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_display_power.c

1734

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_display_power.c

1739

static void icl_display_core_uninit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1741

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1744

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

1747

gen9_disable_dc_states(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1748

intel_dmc_disable_program(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1753

gen9_dbuf_disable(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1756

intel_cdclk_uninit_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1758

if (DISPLAY_VER(display) == 14)

drivers/gpu/drm/i915/display/intel_display_power.c

1759

intel_de_rmw(display, DC_STATE_EN, 0,

drivers/gpu/drm/i915/display/intel_display_power.c

1768

well = lookup_power_well(display, SKL_DISP_PW_1);

drivers/gpu/drm/i915/display/intel_display_power.c

1769

intel_power_well_disable(display, well);

drivers/gpu/drm/i915/display/intel_display_power.c

1773

intel_combo_phy_uninit(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1776

static void chv_phy_control_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1779

lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

drivers/gpu/drm/i915/display/intel_display_power.c

1781

lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);

drivers/gpu/drm/i915/display/intel_display_power.c

1790

display->power.chv_phy_control =

drivers/gpu/drm/i915/display/intel_display_power.c

1804

if (intel_power_well_is_enabled(display, cmn_bc)) {

drivers/gpu/drm/i915/display/intel_display_power.c

1805

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

drivers/gpu/drm/i915/display/intel_display_power.c

1812

display->power.chv_phy_control |=

drivers/gpu/drm/i915/display/intel_display_power.c

1815

display->power.chv_phy_control |=

drivers/gpu/drm/i915/display/intel_display_power.c

1822

display->power.chv_phy_control |=

drivers/gpu/drm/i915/display/intel_display_power.c

1825

display->power.chv_phy_control |=

drivers/gpu/drm/i915/display/intel_display_power.c

1828

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);

drivers/gpu/drm/i915/display/intel_display_power.c

1830

display->power.chv_phy_assert[DPIO_PHY0] = false;

drivers/gpu/drm/i915/display/intel_display_power.c

1832

display->power.chv_phy_assert[DPIO_PHY0] = true;

drivers/gpu/drm/i915/display/intel_display_power.c

1835

if (intel_power_well_is_enabled(display, cmn_d)) {

drivers/gpu/drm/i915/display/intel_display_power.c

1836

u32 status = intel_de_read(display, DPIO_PHY_STATUS);

drivers/gpu/drm/i915/display/intel_display_power.c

1844

display->power.chv_phy_control |=

drivers/gpu/drm/i915/display/intel_display_power.c

1847

display->power.chv_phy_control |=

drivers/gpu/drm/i915/display/intel_display_power.c

1850

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);

drivers/gpu/drm/i915/display/intel_display_power.c

1852

display->power.chv_phy_assert[DPIO_PHY1] = false;

drivers/gpu/drm/i915/display/intel_display_power.c

1854

display->power.chv_phy_assert[DPIO_PHY1] = true;

drivers/gpu/drm/i915/display/intel_display_power.c

1857

drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n",

drivers/gpu/drm/i915/display/intel_display_power.c

1858

display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power.c

1863

static void vlv_cmnlane_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1866

lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

drivers/gpu/drm/i915/display/intel_display_power.c

1868

lookup_power_well(display, VLV_DISP_PW_DISP2D);

drivers/gpu/drm/i915/display/intel_display_power.c

1871

if (intel_power_well_is_enabled(display, cmn) &&

drivers/gpu/drm/i915/display/intel_display_power.c

1872

intel_power_well_is_enabled(display, disp2d) &&

drivers/gpu/drm/i915/display/intel_display_power.c

1873

intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)

drivers/gpu/drm/i915/display/intel_display_power.c

1876

drm_dbg_kms(display->drm, "toggling display PHY side reset\n");

drivers/gpu/drm/i915/display/intel_display_power.c

1879

intel_power_well_enable(display, disp2d);

drivers/gpu/drm/i915/display/intel_display_power.c

1888

intel_power_well_disable(display, cmn);

drivers/gpu/drm/i915/display/intel_display_power.c

1891

static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)

drivers/gpu/drm/i915/display/intel_display_power.c

1895

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power.c

1896

ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;

drivers/gpu/drm/i915/display/intel_display_power.c

1897

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power.c

1902

static void assert_ved_power_gated(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1904

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

1905

!vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0),

drivers/gpu/drm/i915/display/intel_display_power.c

1909

static void assert_isp_power_gated(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

1917

drm_WARN(display->drm, !pci_dev_present(isp_ids) &&

drivers/gpu/drm/i915/display/intel_display_power.c

1918

!vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0),

drivers/gpu/drm/i915/display/intel_display_power.c

1922

static void intel_power_domains_verify_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.c

1940

void intel_power_domains_init_hw(struct intel_display *display, bool resume)

drivers/gpu/drm/i915/display/intel_display_power.c

1942

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

1946

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_power.c

1947

icl_display_core_init(display, resume);

drivers/gpu/drm/i915/display/intel_display_power.c

1948

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_power.c

1949

bxt_display_core_init(display, resume);

drivers/gpu/drm/i915/display/intel_display_power.c

1950

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_display_power.c

1951

skl_display_core_init(display, resume);

drivers/gpu/drm/i915/display/intel_display_power.c

1952

} else if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_display_power.c

1954

chv_phy_control_init(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1956

assert_isp_power_gated(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1957

} else if (display->platform.valleyview) {

drivers/gpu/drm/i915/display/intel_display_power.c

1959

vlv_cmnlane_wa(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1961

assert_ved_power_gated(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1962

assert_isp_power_gated(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1963

} else if (display->platform.broadwell || display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_display_power.c

1964

hsw_assert_cdclk(display);

drivers/gpu/drm/i915/display/intel_display_power.c

1965

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

drivers/gpu/drm/i915/display/intel_display_power.c

1966

} else if (display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_display_power.c

1967

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

drivers/gpu/drm/i915/display/intel_display_power.c

1976

drm_WARN_ON(display->drm, power_domains->init_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

1978

intel_display_power_get(display, POWER_DOMAIN_INIT);

drivers/gpu/drm/i915/display/intel_display_power.c

1981

if (!display->params.disable_power_well) {

drivers/gpu/drm/i915/display/intel_display_power.c

1982

drm_WARN_ON(display->drm, power_domains->disable_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

1983

display->power.domains.disable_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_display_power.c

1986

intel_power_domains_sync_hw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2002

void intel_power_domains_driver_remove(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2005

fetch_and_zero(&display->power.domains.init_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2008

if (!display->params.disable_power_well)

drivers/gpu/drm/i915/display/intel_display_power.c

2009

intel_display_power_put(display, POWER_DOMAIN_INIT,

drivers/gpu/drm/i915/display/intel_display_power.c

2010

fetch_and_zero(&display->power.domains.disable_wakeref));

drivers/gpu/drm/i915/display/intel_display_power.c

2012

intel_display_power_flush_work_sync(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2014

intel_power_domains_verify_state(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2017

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2030

void intel_power_domains_sanitize_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2032

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2037

for_each_power_well_reverse(display, power_well) {

drivers/gpu/drm/i915/display/intel_display_power.c

2039

!intel_power_well_is_enabled(display, power_well))

drivers/gpu/drm/i915/display/intel_display_power.c

2042

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

2045

intel_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

2063

void intel_power_domains_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2066

fetch_and_zero(&display->power.domains.init_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2068

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2069

intel_power_domains_verify_state(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2079

void intel_power_domains_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

208

static bool __intel_display_power_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

2081

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2083

drm_WARN_ON(display->drm, power_domains->init_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2085

intel_display_power_get(display, POWER_DOMAIN_INIT);

drivers/gpu/drm/i915/display/intel_display_power.c

2087

intel_power_domains_verify_state(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2101

void intel_power_domains_suspend(struct intel_display *display, bool s2idle)

drivers/gpu/drm/i915/display/intel_display_power.c

2103

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2107

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2117

intel_dmc_has_payload(display)) {

drivers/gpu/drm/i915/display/intel_display_power.c

2118

intel_display_power_flush_work(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2119

intel_power_domains_verify_state(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2127

if (!display->params.disable_power_well)

drivers/gpu/drm/i915/display/intel_display_power.c

2128

intel_display_power_put(display, POWER_DOMAIN_INIT,

drivers/gpu/drm/i915/display/intel_display_power.c

2129

fetch_and_zero(&display->power.domains.disable_wakeref));

drivers/gpu/drm/i915/display/intel_display_power.c

2131

intel_display_power_flush_work(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2132

intel_power_domains_verify_state(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2134

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display_power.c

2135

icl_display_core_uninit(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2136

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power.c

2137

bxt_display_core_uninit(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2138

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_display_power.c

2139

skl_display_core_uninit(display);

drivers/gpu/drm/i915/display/intel_display_power.c

214

if (intel_display_rpm_suspended(display))

drivers/gpu/drm/i915/display/intel_display_power.c

2154

void intel_power_domains_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2156

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2159

intel_power_domains_init_hw(display, true);

drivers/gpu/drm/i915/display/intel_display_power.c

2162

drm_WARN_ON(display->drm, power_domains->init_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

2164

intel_display_power_get(display, POWER_DOMAIN_INIT);

drivers/gpu/drm/i915/display/intel_display_power.c

2170

static void intel_power_domains_dump_info(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2172

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2175

for_each_power_well(display, power_well) {

drivers/gpu/drm/i915/display/intel_display_power.c

2178

drm_dbg_kms(display->drm, "%-25s %d\n",

drivers/gpu/drm/i915/display/intel_display_power.c

2182

drm_dbg_kms(display->drm, " %-23s %d\n",

drivers/gpu/drm/i915/display/intel_display_power.c

219

for_each_power_domain_well_reverse(display, power_well, domain) {

drivers/gpu/drm/i915/display/intel_display_power.c

2198

static void intel_power_domains_verify_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2200

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2209

for_each_power_well(display, power_well) {

drivers/gpu/drm/i915/display/intel_display_power.c

2214

enabled = intel_power_well_is_enabled(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

2218

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

2228

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

2242

intel_power_domains_dump_info(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2252

static void intel_power_domains_verify_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2258

void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)

drivers/gpu/drm/i915/display/intel_display_power.c

2260

intel_power_domains_suspend(display, s2idle);

drivers/gpu/drm/i915/display/intel_display_power.c

2262

if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||

drivers/gpu/drm/i915/display/intel_display_power.c

2263

display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_power.c

2264

bxt_enable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2265

} else if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_display_power.c

2266

hsw_enable_pc8(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2270

if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1)

drivers/gpu/drm/i915/display/intel_display_power.c

2271

intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);

drivers/gpu/drm/i915/display/intel_display_power.c

2274

void intel_display_power_resume_early(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2276

if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||

drivers/gpu/drm/i915/display/intel_display_power.c

2277

display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_power.c

2278

gen9_sanitize_dc_state(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2279

bxt_disable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2280

} else if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_display_power.c

2281

hsw_disable_pc8(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2285

if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1)

drivers/gpu/drm/i915/display/intel_display_power.c

2286

intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);

drivers/gpu/drm/i915/display/intel_display_power.c

2288

intel_power_domains_resume(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2291

void intel_display_power_suspend(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2293

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_power.c

2294

icl_display_core_uninit(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2295

bxt_enable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2296

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_power.c

2297

bxt_display_core_uninit(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2298

bxt_enable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2299

} else if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_display_power.c

2300

hsw_enable_pc8(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2304

void intel_display_power_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

2306

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2308

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_power.c

2309

bxt_disable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2310

icl_display_core_init(display, true);

drivers/gpu/drm/i915/display/intel_display_power.c

2311

if (intel_dmc_has_payload(display)) {

drivers/gpu/drm/i915/display/intel_display_power.c

2313

skl_enable_dc6(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2315

gen9_enable_dc5(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2317

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_display_power.c

2318

bxt_disable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2319

bxt_display_core_init(display, true);

drivers/gpu/drm/i915/display/intel_display_power.c

2320

if (intel_dmc_has_payload(display) &&

drivers/gpu/drm/i915/display/intel_display_power.c

2322

gen9_enable_dc5(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2323

} else if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_display_power.c

2324

hsw_disable_pc8(display);

drivers/gpu/drm/i915/display/intel_display_power.c

2328

void intel_display_power_debug(struct intel_display *display, struct seq_file *m)

drivers/gpu/drm/i915/display/intel_display_power.c

2330

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2478

intel_port_domains_for_platform(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

2482

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_display_power.c

2485

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_display_power.c

2488

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_display_power.c

249

bool intel_display_power_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

2498

intel_port_domains_for_port(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display_power.c

2504

intel_port_domains_for_platform(display, &domains, &domains_size);

drivers/gpu/drm/i915/display/intel_display_power.c

2513

intel_display_power_ddi_io_domain(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display_power.c

2515

const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);

drivers/gpu/drm/i915/display/intel_display_power.c

2517

if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))

drivers/gpu/drm/i915/display/intel_display_power.c

252

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

2524

intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_display_power.c

2526

const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);

drivers/gpu/drm/i915/display/intel_display_power.c

2528

if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))

drivers/gpu/drm/i915/display/intel_display_power.c

2535

intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch)

drivers/gpu/drm/i915/display/intel_display_power.c

2541

intel_port_domains_for_platform(display, &domains, &domains_size);

drivers/gpu/drm/i915/display/intel_display_power.c

2550

intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch)

drivers/gpu/drm/i915/display/intel_display_power.c

2552

const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);

drivers/gpu/drm/i915/display/intel_display_power.c

2554

if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))

drivers/gpu/drm/i915/display/intel_display_power.c

256

ret = __intel_display_power_is_enabled(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

2561

intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch)

drivers/gpu/drm/i915/display/intel_display_power.c

2563

const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);

drivers/gpu/drm/i915/display/intel_display_power.c

2565

if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))

drivers/gpu/drm/i915/display/intel_display_power.c

2572

intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch)

drivers/gpu/drm/i915/display/intel_display_power.c

2574

const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);

drivers/gpu/drm/i915/display/intel_display_power.c

2576

if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))

drivers/gpu/drm/i915/display/intel_display_power.c

263

sanitize_target_dc_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

266

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

297

void intel_display_power_set_target_dc_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

302

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

305

power_well = lookup_power_well(display, SKL_DISP_DC_OFF);

drivers/gpu/drm/i915/display/intel_display_power.c

307

if (drm_WARN_ON(display->drm, !power_well))

drivers/gpu/drm/i915/display/intel_display_power.c

310

state = sanitize_target_dc_state(display, state);

drivers/gpu/drm/i915/display/intel_display_power.c

315

dc_off_enabled = intel_power_well_is_enabled(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

321

intel_power_well_enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

326

intel_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

340

u32 intel_display_power_get_current_dc_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

343

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

347

power_well = lookup_power_well(display, SKL_DISP_DC_OFF);

drivers/gpu/drm/i915/display/intel_display_power.c

349

if (drm_WARN_ON(display->drm, !power_well))

drivers/gpu/drm/i915/display/intel_display_power.c

352

current_dc_state = intel_power_well_is_enabled(display, power_well) ?

drivers/gpu/drm/i915/display/intel_display_power.c

375

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power.c

379

return !drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

388

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power.c

397

err |= drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

402

err |= drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

411

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power.c

416

drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));

drivers/gpu/drm/i915/display/intel_display_power.c

418

drm_dbg_kms(display->drm, "%s use_count %d\n",

drivers/gpu/drm/i915/display/intel_display_power.c

426

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power.c

430

drm_dbg_kms(display->drm, "async_put_wakeref: %s\n",

drivers/gpu/drm/i915/display/intel_display_power.c

491

intel_display_power_grab_async_put_ref(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

494

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

511

intel_display_rpm_put_raw(display,

drivers/gpu/drm/i915/display/intel_display_power.c

520

__intel_display_power_get_domain(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

523

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

526

if (intel_display_power_grab_async_put_ref(display, domain))

drivers/gpu/drm/i915/display/intel_display_power.c

529

for_each_power_domain_well(display, power_well, domain)

drivers/gpu/drm/i915/display/intel_display_power.c

530

intel_power_well_get(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

547

struct ref_tracker *intel_display_power_get(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

550

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

553

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_display_power.c

556

__intel_display_power_get_domain(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

575

intel_display_power_get_if_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

578

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

582

wakeref = intel_display_rpm_get_if_in_use(display);

drivers/gpu/drm/i915/display/intel_display_power.c

588

if (__intel_display_power_is_enabled(display, domain)) {

drivers/gpu/drm/i915/display/intel_display_power.c

589

__intel_display_power_get_domain(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

598

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

606

__intel_display_power_put_domain(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

609

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

614

drm_WARN(display->drm, !power_domains->domain_use_count[domain],

drivers/gpu/drm/i915/display/intel_display_power.c

618

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

625

for_each_power_domain_well_reverse(display, power_well, domain)

drivers/gpu/drm/i915/display/intel_display_power.c

626

intel_power_well_put(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power.c

629

static void __intel_display_power_put(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

632

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

635

__intel_display_power_put_domain(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

644

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power.c

647

drm_WARN_ON(display->drm, power_domains->async_put_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

649

drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq,

drivers/gpu/drm/i915/display/intel_display_power.c

658

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power.c

664

wakeref = intel_display_rpm_get_noresume(display);

drivers/gpu/drm/i915/display/intel_display_power.c

669

__intel_display_power_put_domain(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

672

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

678

struct intel_display *display = container_of(work, struct intel_display,

drivers/gpu/drm/i915/display/intel_display_power.c

680

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

683

new_work_wakeref = intel_display_rpm_get_raw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

723

intel_display_rpm_put_raw(display, old_work_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

725

intel_display_rpm_put_raw(display, new_work_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

741

void __intel_display_power_put_async(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

746

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

749

work_wakeref = intel_display_rpm_get_raw(display);

drivers/gpu/drm/i915/display/intel_display_power.c

756

__intel_display_power_put_domain(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

761

drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1);

drivers/gpu/drm/i915/display/intel_display_power.c

781

intel_display_rpm_put_raw(display, work_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

783

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

798

void intel_display_power_flush_work(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

800

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

820

intel_display_rpm_put_raw(display, work_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

831

intel_display_power_flush_work_sync(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power.c

833

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power.c

835

intel_display_power_flush_work(display);

drivers/gpu/drm/i915/display/intel_display_power.c

840

drm_WARN_ON(display->drm, power_domains->async_put_wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

854

void intel_display_power_put(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

858

__intel_display_power_put(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

859

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_display_power.c

875

void intel_display_power_put_unchecked(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

878

__intel_display_power_put(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

879

intel_display_rpm_put_unchecked(display);

drivers/gpu/drm/i915/display/intel_display_power.c

884

intel_display_power_get_in_set(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

890

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

drivers/gpu/drm/i915/display/intel_display_power.c

892

wf = intel_display_power_get(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

900

intel_display_power_get_in_set_if_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

906

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

drivers/gpu/drm/i915/display/intel_display_power.c

908

wf = intel_display_power_get_if_enabled(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.c

921

intel_display_power_put_mask_in_set(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.c

927

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

936

intel_display_power_put(display, domain, wf);

drivers/gpu/drm/i915/display/intel_display_power.c

950

static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)

drivers/gpu/drm/i915/display/intel_display_power.c

956

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power.c

959

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_display_power.c

961

else if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_display_power.c

963

else if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_display_power.c

965

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_power.c

967

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power.c

969

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_display_power.c

979

mask = display->platform.geminilake || display->platform.broxton ||

drivers/gpu/drm/i915/display/intel_display_power.c

980

DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0;

drivers/gpu/drm/i915/display/intel_display_power.c

982

if (!display->params.disable_power_well)

drivers/gpu/drm/i915/display/intel_display_power.c

990

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.c

995

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power.h

172

int intel_power_domains_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

173

void intel_power_domains_cleanup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

174

void intel_power_domains_init_hw(struct intel_display *display, bool resume);

drivers/gpu/drm/i915/display/intel_display_power.h

175

void intel_power_domains_driver_remove(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

176

void intel_power_domains_enable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

177

void intel_power_domains_disable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

178

void intel_power_domains_suspend(struct intel_display *display, bool s2idle);

drivers/gpu/drm/i915/display/intel_display_power.h

179

void intel_power_domains_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

180

void intel_power_domains_sanitize_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

182

void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);

drivers/gpu/drm/i915/display/intel_display_power.h

183

void intel_display_power_resume_early(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

184

void intel_display_power_suspend(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

185

void intel_display_power_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

186

void intel_display_power_set_target_dc_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

188

u32 intel_display_power_get_current_dc_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

190

bool intel_display_power_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

192

struct ref_tracker *intel_display_power_get(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

195

intel_display_power_get_if_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

197

void __intel_display_power_put_async(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

201

void intel_display_power_flush_work(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power.h

203

void intel_display_power_put(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

207

intel_display_power_put_async(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

211

__intel_display_power_put_async(display, domain, wakeref, -1);

drivers/gpu/drm/i915/display/intel_display_power.h

215

intel_display_power_put_async_delay(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

220

__intel_display_power_put_async(display, domain, wakeref, delay_ms);

drivers/gpu/drm/i915/display/intel_display_power.h

223

void intel_display_power_put_unchecked(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

227

intel_display_power_put(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

231

intel_display_power_put_unchecked(display, domain);

drivers/gpu/drm/i915/display/intel_display_power.h

235

intel_display_power_put_async(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

239

__intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1);

drivers/gpu/drm/i915/display/intel_display_power.h

243

intel_display_power_put_async_delay(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

248

__intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms);

drivers/gpu/drm/i915/display/intel_display_power.h

253

intel_display_power_get_in_set(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

258

intel_display_power_get_in_set_if_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

263

intel_display_power_put_mask_in_set(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

268

intel_display_power_put_all_in_set(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

271

intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask);

drivers/gpu/drm/i915/display/intel_display_power.h

274

void intel_display_power_debug(struct intel_display *display, struct seq_file *m);

drivers/gpu/drm/i915/display/intel_display_power.h

277

intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display_power.h

279

intel_display_power_ddi_io_domain(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display_power.h

281

intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch);

drivers/gpu/drm/i915/display/intel_display_power.h

283

intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch);

drivers/gpu/drm/i915/display/intel_display_power.h

285

intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch);

drivers/gpu/drm/i915/display/intel_display_power.h

299

void gen9_dbuf_slices_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power.h

302

#define __with_intel_display_power(display, domain, wf) \

drivers/gpu/drm/i915/display/intel_display_power.h

303

for (struct ref_tracker *(wf) = intel_display_power_get((display), (domain)); (wf); \

drivers/gpu/drm/i915/display/intel_display_power.h

304

intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL)

drivers/gpu/drm/i915/display/intel_display_power.h

306

#define with_intel_display_power(display, domain) \

drivers/gpu/drm/i915/display/intel_display_power.h

307

__with_intel_display_power(display, domain, __UNIQUE_ID(wakeref))

drivers/gpu/drm/i915/display/intel_display_power.h

309

#define __with_intel_display_power_if_enabled(display, domain, wf) \

drivers/gpu/drm/i915/display/intel_display_power.h

310

for (struct ref_tracker *(wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \

drivers/gpu/drm/i915/display/intel_display_power.h

311

intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL)

drivers/gpu/drm/i915/display/intel_display_power.h

313

#define with_intel_display_power_if_enabled(display, domain) \

drivers/gpu/drm/i915/display/intel_display_power.h

314

__with_intel_display_power_if_enabled(display, domain, __UNIQUE_ID(wakeref))

drivers/gpu/drm/i915/display/intel_display_power_map.c

1811

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power_map.c

1836

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_map.c

1847

drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8);

drivers/gpu/drm/i915/display/intel_display_power_map.c

1848

drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id));

drivers/gpu/drm/i915/display/intel_display_power_map.c

1869

struct intel_display *display = container_of(power_domains,

drivers/gpu/drm/i915/display/intel_display_power_map.c

1876

if (!HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_display_power_map.c

1881

if (DISPLAY_VERx100(display) == 3002)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1883

else if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1885

else if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1887

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1889

else if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1891

else if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1893

else if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1895

else if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1897

else if (display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1899

else if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1901

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1903

else if (display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1905

else if (display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1907

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1909

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1911

else if (display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1913

else if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1915

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_display_power_map.c

1917

else if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1001

static void gen9_assert_dbuf_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1003

u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1004

u8 enabled_dbuf_slices = display->dbuf.enabled_slices;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1006

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1013

void gen9_disable_dc_states(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1015

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1020

tgl_disable_dc3co(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1024

if (HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

1025

intel_dmc_wl_get_noreg(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1026

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1027

intel_dmc_wl_put_noreg(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1029

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1035

intel_dmc_wl_disable(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1037

intel_cdclk_get_cdclk(display, &cdclk_config);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1039

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1040

intel_cdclk_clock_changed(&display->cdclk.hw,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1043

gen9_assert_dbuf_enabled(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1045

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1046

bxt_verify_dpio_phy_power_wells(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1048

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1054

intel_combo_phy_init(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1057

static void gen9_dc_off_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1060

gen9_disable_dc_states(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1063

static void gen9_dc_off_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1066

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1068

if (!intel_dmc_has_payload(display))

drivers/gpu/drm/i915/display/intel_display_power_well.c

1073

tgl_enable_dc3co(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1076

skl_enable_dc6(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1079

gen9_enable_dc5(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1084

static void i9xx_power_well_sync_hw_noop(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1089

static void i9xx_always_on_power_well_noop(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1094

static bool i9xx_always_on_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

110

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1100

static void i830_pipes_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1103

if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1104

i830_enable_pipe(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1105

if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1106

i830_enable_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1109

static void i830_pipes_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1112

i830_disable_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1113

i830_disable_pipe(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1116

static bool i830_pipes_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1119

return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

1120

intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1123

static void i830_pipes_power_well_sync_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1127

i830_pipes_power_well_enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1129

i830_pipes_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

113

return &display->power.domains.power_wells[0];

drivers/gpu/drm/i915/display/intel_display_power_well.c

1132

static void vlv_set_power_well(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1146

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1148

val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1152

ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1155

vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1157

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),

drivers/gpu/drm/i915/display/intel_display_power_well.c

116

void intel_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1161

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1164

vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1167

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1170

static void vlv_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1173

vlv_set_power_well(display, power_well, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1176

static void vlv_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1179

vlv_set_power_well(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1182

static bool vlv_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

119

drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1194

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1196

state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask;

drivers/gpu/drm/i915/display/intel_display_power_well.c

120

power_well->desc->ops->enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1201

drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

1210

ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1211

drm_WARN_ON(display->drm, ctrl != state);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1213

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1218

static void vlv_init_display_clock_gating(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1226

intel_de_rmw(display, VLV_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1232

intel_de_write(display, MI_ARB_VLV,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1234

intel_de_write(display, CBR1_VLV, 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1236

drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1237

intel_de_write(display, RAWCLK_FREQ_VLV,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1238

DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq,

drivers/gpu/drm/i915/display/intel_display_power_well.c

124

void intel_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1242

static void vlv_display_power_well_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1255

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

1256

u32 val = intel_de_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1262

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1265

vlv_init_display_clock_gating(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1267

valleyview_enable_display_irqs(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

127

drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1273

if (display->power.domains.initializing)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1276

intel_hpd_init(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1277

intel_hpd_poll_disable(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1280

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

1285

intel_vga_disable(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1287

intel_pps_unlock_regs_wa(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

129

power_well->desc->ops->disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1290

static void vlv_display_power_well_deinit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1292

valleyview_disable_display_irqs(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1295

intel_parent_irq_synchronize(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1297

vlv_pps_reset_all(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1300

if (!display->drm->dev->power.is_suspended)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1301

intel_hpd_poll_enable(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1304

static void vlv_display_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1307

vlv_set_power_well(display, power_well, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1309

vlv_display_power_well_init(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1312

static void vlv_display_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1315

vlv_display_power_well_deinit(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1317

vlv_set_power_well(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

132

void intel_power_well_sync_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1320

static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1326

vlv_set_power_well(display, power_well, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1339

intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1342

static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1347

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1348

assert_pll_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_display_power_well.c

135

power_well->desc->ops->sync_hw(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1351

intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1353

vlv_set_power_well(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1358

static void assert_chv_phy_status(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

136

power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1361

lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1363

lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1364

u32 phy_control = display->power.chv_phy_control;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1376

if (!display->power.chv_phy_assert[DPIO_PHY0])

drivers/gpu/drm/i915/display/intel_display_power_well.c

1384

if (!display->power.chv_phy_assert[DPIO_PHY1])

drivers/gpu/drm/i915/display/intel_display_power_well.c

1389

if (intel_power_well_is_enabled(display, cmn_bc)) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

139

void intel_power_well_get(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1412

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

143

intel_power_well_enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1430

if (intel_power_well_is_enabled(display, cmn_d)) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

1455

if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1457

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1459

val & phy_status_mask, phy_status, display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

146

void intel_power_well_put(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1464

static void chv_dpio_cmn_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1471

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1482

vlv_set_power_well(display, power_well, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1485

if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1487

drm_err(display->drm, "Display PHY %d is not power up\n",

drivers/gpu/drm/i915/display/intel_display_power_well.c

149

drm_WARN(display->drm, !power_well->count,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1490

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1493

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1496

vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1499

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1501

vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1508

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1510

vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1513

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1515

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1516

intel_de_write(display, DISPLAY_PHY_CONTROL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1517

display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1519

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1521

phy, display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1523

assert_chv_phy_status(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1526

static void chv_dpio_cmn_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1532

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1538

assert_pll_disabled(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1539

assert_pll_disabled(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_power_well.c

154

intel_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1542

assert_pll_disabled(display, PIPE_C);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1545

display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1546

intel_de_write(display, DISPLAY_PHY_CONTROL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1547

display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1549

vlv_set_power_well(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1551

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1553

phy, display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1556

display->power.chv_phy_assert[phy] = true;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1558

assert_chv_phy_status(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1561

static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy,

drivers/gpu/drm/i915/display/intel_display_power_well.c

157

bool intel_power_well_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1573

if (!display->power.chv_phy_assert[phy])

drivers/gpu/drm/i915/display/intel_display_power_well.c

1581

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1582

val = vlv_dpio_read(display->drm, phy, reg);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1583

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

160

return power_well->desc->ops->is_enabled(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1616

drm_WARN(display->drm, actual != expected,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1625

bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1628

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1633

was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1639

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1641

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1643

intel_de_write(display, DISPLAY_PHY_CONTROL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1644

display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1646

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1648

phy, ch, display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1650

assert_chv_phy_status(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1661

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1662

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1668

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1669

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1672

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1674

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1676

intel_de_write(display, DISPLAY_PHY_CONTROL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1677

display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1679

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

168

bool intel_display_power_well_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1681

phy, ch, mask, display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1683

assert_chv_phy_status(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1685

assert_chv_phy_powergate(display, phy, ch, override, mask);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1690

static bool chv_pipe_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1697

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1699

state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1704

drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

1712

ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1713

drm_WARN_ON(display->drm, ctrl << 16 != state);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1715

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1720

static void chv_set_pipe_power_well(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

173

power_well = lookup_power_well(display, power_well_id);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1731

vlv_punit_get(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1733

ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1739

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1741

ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1745

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1748

vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM));

drivers/gpu/drm/i915/display/intel_display_power_well.c

175

return intel_power_well_is_enabled(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1753

vlv_punit_put(display->drm);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1756

static void chv_pipe_power_well_sync_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1759

intel_de_write(display, DISPLAY_PHY_CONTROL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1760

display->power.chv_phy_control);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1763

static void chv_pipe_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1766

chv_set_pipe_power_well(display, power_well, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1768

vlv_display_power_well_init(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1771

static void chv_pipe_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1774

vlv_display_power_well_deinit(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1776

chv_set_pipe_power_well(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1780

tgl_tc_cold_request(struct intel_display *display, bool block)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1798

ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1814

drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un");

drivers/gpu/drm/i915/display/intel_display_power_well.c

1816

drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n",

drivers/gpu/drm/i915/display/intel_display_power_well.c

1821

tgl_tc_cold_off_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1824

tgl_tc_cold_request(display, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1828

tgl_tc_cold_off_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1831

tgl_tc_cold_request(display, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1835

tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1839

tgl_tc_cold_off_power_well_enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1841

tgl_tc_cold_off_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1845

tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1855

static void xelpdp_aux_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1859

enum phy phy = icl_aux_pw_to_phy(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1861

if (icl_aux_pw_is_tc_phy(display, power_well))

drivers/gpu/drm/i915/display/intel_display_power_well.c

1862

icl_tc_port_assert_ref_held(display, power_well,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1863

aux_ch_to_digital_port(display, aux_ch));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1865

intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1869

if (HAS_LT_PHY(display)) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

1870

if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1872

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1886

static void xelpdp_aux_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1890

enum phy phy = icl_aux_pw_to_phy(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1892

intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1896

if (HAS_LT_PHY(display)) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

1897

if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1899

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1907

static bool xelpdp_aux_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1912

return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

1916

static void xe2lpd_pica_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1919

intel_de_write(display, XE2LPD_PICA_PW_CTL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1922

if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1924

drm_dbg_kms(display->drm, "pica power well enable timeout\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

1926

drm_WARN(display->drm, 1, "Power well PICA timeout when enabled");

drivers/gpu/drm/i915/display/intel_display_power_well.c

1930

static void xe2lpd_pica_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1933

intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1935

if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1937

drm_dbg_kms(display->drm, "pica power well disable timeout\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

1939

drm_WARN(display->drm, 1, "Power well PICA timeout when disabled");

drivers/gpu/drm/i915/display/intel_display_power_well.c

1943

static bool xe2lpd_pica_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

1946

return intel_de_read(display, XE2LPD_PICA_PW_CTL) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

204

static void hsw_power_well_post_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

208

intel_vga_reset_io_mem(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

211

gen8_irq_power_well_post_enable(display, irq_pipe_mask);

drivers/gpu/drm/i915/display/intel_display_power_well.c

214

static void hsw_power_well_pre_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

218

gen8_irq_power_well_pre_disable(display, irq_pipe_mask);

drivers/gpu/drm/i915/display/intel_display_power_well.c

239

aux_ch_to_digital_port(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

244

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

261

icl_aux_pw_to_encoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

265

struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

277

static enum phy icl_aux_pw_to_phy(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

280

struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

285

static bool icl_aux_pw_is_tc_phy(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

288

struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

293

static void hsw_wait_for_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

306

if (display->platform.dg2 && power_well->desc->fixed_enable_delay) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

312

if (intel_de_wait_for_set_ms(display, regs->driver,

drivers/gpu/drm/i915/display/intel_display_power_well.c

314

drm_dbg_kms(display->drm, "%s power well enable timeout\n",

drivers/gpu/drm/i915/display/intel_display_power_well.c

317

drm_WARN_ON(display->drm, !timeout_expected);

drivers/gpu/drm/i915/display/intel_display_power_well.c

322

static u32 hsw_power_well_requesters(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

329

ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

330

ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

332

ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

333

ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

338

static void hsw_wait_for_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

355

reqs = hsw_power_well_requesters(display, regs, pw_idx);

drivers/gpu/drm/i915/display/intel_display_power_well.c

357

ret = intel_de_wait_for_clear_ms(display, regs->driver,

drivers/gpu/drm/i915/display/intel_display_power_well.c

365

reqs = hsw_power_well_requesters(display, regs, pw_idx);

drivers/gpu/drm/i915/display/intel_display_power_well.c

367

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

373

static void gen9_wait_for_power_well_fuses(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

377

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

378

intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS,

drivers/gpu/drm/i915/display/intel_display_power_well.c

382

static void hsw_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

391

pg = pw_idx_to_pg(display, pw_idx);

drivers/gpu/drm/i915/display/intel_display_power_well.c

394

if (display->platform.alderlake_p && pg == SKL_PG1)

drivers/gpu/drm/i915/display/intel_display_power_well.c

395

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);

drivers/gpu/drm/i915/display/intel_display_power_well.c

405

gen9_wait_for_power_well_fuses(display, SKL_PG0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

408

intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));

drivers/gpu/drm/i915/display/intel_display_power_well.c

410

hsw_wait_for_power_well_enable(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

415

pg = pw_idx_to_pg(display, pw_idx);

drivers/gpu/drm/i915/display/intel_display_power_well.c

417

gen9_wait_for_power_well_fuses(display, pg);

drivers/gpu/drm/i915/display/intel_display_power_well.c

420

hsw_power_well_post_enable(display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

425

static void hsw_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

431

hsw_power_well_pre_disable(display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

434

intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

435

hsw_wait_for_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

438

static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch)

drivers/gpu/drm/i915/display/intel_display_power_well.c

440

struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

446

icl_combo_phy_aux_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

45

static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx)

drivers/gpu/drm/i915/display/intel_display_power_well.c

452

drm_WARN_ON(display->drm, !display->platform.icelake);

drivers/gpu/drm/i915/display/intel_display_power_well.c

454

intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));

drivers/gpu/drm/i915/display/intel_display_power_well.c

460

intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),

drivers/gpu/drm/i915/display/intel_display_power_well.c

463

hsw_wait_for_power_well_enable(display, power_well, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

467

!intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx)))

drivers/gpu/drm/i915/display/intel_display_power_well.c

468

intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),

drivers/gpu/drm/i915/display/intel_display_power_well.c

47

int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1;

drivers/gpu/drm/i915/display/intel_display_power_well.c

473

icl_combo_phy_aux_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

479

drm_WARN_ON(display->drm, !display->platform.icelake);

drivers/gpu/drm/i915/display/intel_display_power_well.c

485

intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),

drivers/gpu/drm/i915/display/intel_display_power_well.c

488

intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

490

hsw_wait_for_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

495

static void icl_tc_port_assert_ref_held(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

499

if (drm_WARN_ON(display->drm, !dig_port))

drivers/gpu/drm/i915/display/intel_display_power_well.c

502

if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))

drivers/gpu/drm/i915/display/intel_display_power_well.c

505

drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));

drivers/gpu/drm/i915/display/intel_display_power_well.c

510

static void icl_tc_port_assert_ref_held(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

520

static void icl_tc_cold_exit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

525

ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

536

drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" :

drivers/gpu/drm/i915/display/intel_display_power_well.c

541

icl_tc_phy_aux_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

545

struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);

drivers/gpu/drm/i915/display/intel_display_power_well.c

552

icl_tc_port_assert_ref_held(display, power_well, dig_port);

drivers/gpu/drm/i915/display/intel_display_power_well.c

554

intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),

drivers/gpu/drm/i915/display/intel_display_power_well.c

557

intel_de_rmw(display, regs->driver,

drivers/gpu/drm/i915/display/intel_display_power_well.c

567

if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))

drivers/gpu/drm/i915/display/intel_display_power_well.c

568

icl_tc_cold_exit(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

570

hsw_wait_for_power_well_enable(display, power_well, timeout_expected);

drivers/gpu/drm/i915/display/intel_display_power_well.c

572

if (DISPLAY_VER(display) >= 12 && !is_tbt) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

577

ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),

drivers/gpu/drm/i915/display/intel_display_power_well.c

581

drm_warn(display->drm, "Timeout waiting TC uC health\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

586

icl_aux_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

589

if (icl_aux_pw_is_tc_phy(display, power_well))

drivers/gpu/drm/i915/display/intel_display_power_well.c

590

return icl_tc_phy_aux_power_well_enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

591

else if (display->platform.icelake)

drivers/gpu/drm/i915/display/intel_display_power_well.c

592

return icl_combo_phy_aux_power_well_enable(display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

595

return hsw_power_well_enable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

599

icl_aux_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

602

if (icl_aux_pw_is_tc_phy(display, power_well))

drivers/gpu/drm/i915/display/intel_display_power_well.c

603

return hsw_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

604

else if (display->platform.icelake)

drivers/gpu/drm/i915/display/intel_display_power_well.c

605

return icl_combo_phy_aux_power_well_disable(display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

608

return hsw_power_well_disable(display, power_well);

drivers/gpu/drm/i915/display/intel_display_power_well.c

616

static bool hsw_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

626

val = intel_de_read(display, regs->driver);

drivers/gpu/drm/i915/display/intel_display_power_well.c

634

if (DISPLAY_VER(display) == 9 && !display->platform.broxton &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

636

val |= intel_de_read(display, regs->bios);

drivers/gpu/drm/i915/display/intel_display_power_well.c

641

static void assert_can_enable_dc9(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

643

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

644

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),

drivers/gpu/drm/i915/display/intel_display_power_well.c

646

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

647

intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

650

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

651

intel_de_read(display, HSW_PWR_WELL_CTL2) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

654

drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display),

drivers/gpu/drm/i915/display/intel_display_power_well.c

666

static void assert_can_disable_dc9(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

668

drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display),

drivers/gpu/drm/i915/display/intel_display_power_well.c

67

void (*sync_hw)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

670

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

671

intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

684

static void gen9_write_dc_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

691

intel_de_write(display, DC_STATE_EN, state);

drivers/gpu/drm/i915/display/intel_display_power_well.c

699

v = intel_de_read(display, DC_STATE_EN);

drivers/gpu/drm/i915/display/intel_display_power_well.c

702

intel_de_write(display, DC_STATE_EN, state);

drivers/gpu/drm/i915/display/intel_display_power_well.c

712

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

718

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

723

static u32 gen9_dc_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

729

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_display_power_well.c

732

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display_power_well.c

734

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power_well.c

74

void (*enable)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

742

void gen9_sanitize_dc_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

744

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power_well.c

747

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power_well.c

750

val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

752

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

781

void gen9_set_dc_state(struct intel_display *display, u32 state)

drivers/gpu/drm/i915/display/intel_display_power_well.c

783

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_display_power_well.c

788

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_power_well.c

791

if (drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

796

intel_psr_notify_dc5_dc6(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

798

val = intel_de_read(display, DC_STATE_EN);

drivers/gpu/drm/i915/display/intel_display_power_well.c

799

mask = gen9_dc_mask(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

80

void (*disable)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

800

drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n",

drivers/gpu/drm/i915/display/intel_display_power_well.c

805

drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",

drivers/gpu/drm/i915/display/intel_display_power_well.c

811

intel_dmc_update_dc6_allowed_count(display, true);

drivers/gpu/drm/i915/display/intel_display_power_well.c

816

gen9_write_dc_state(display, val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

819

intel_dmc_update_dc6_allowed_count(display, false);

drivers/gpu/drm/i915/display/intel_display_power_well.c

824

static void tgl_enable_dc3co(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

826

drm_dbg_kms(display->drm, "Enabling DC3CO\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

827

gen9_set_dc_state(display, DC_STATE_EN_DC3CO);

drivers/gpu/drm/i915/display/intel_display_power_well.c

83

bool (*is_enabled)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

830

static void tgl_disable_dc3co(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

832

drm_dbg_kms(display->drm, "Disabling DC3CO\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

833

intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);

drivers/gpu/drm/i915/display/intel_display_power_well.c

834

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power_well.c

841

static void assert_can_enable_dc5(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

846

if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/intel_display_power_well.c

851

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

852

intel_display_power_well_is_enabled(display, high_pg),

drivers/gpu/drm/i915/display/intel_display_power_well.c

855

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

856

(intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

860

assert_display_rpm_held(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

862

assert_main_dmc_loaded(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

865

void gen9_enable_dc5(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

867

assert_can_enable_dc5(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

869

drm_dbg_kms(display->drm, "Enabling DC5\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

872

if (DISPLAY_VER(display) == 9 && !display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power_well.c

873

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

drivers/gpu/drm/i915/display/intel_display_power_well.c

876

intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5);

drivers/gpu/drm/i915/display/intel_display_power_well.c

878

gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5);

drivers/gpu/drm/i915/display/intel_display_power_well.c

881

static void assert_can_enable_dc6(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

883

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

884

(intel_de_read(display, UTIL_PIN_CTL) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

888

drm_WARN_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_display_power_well.c

889

(intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

893

assert_main_dmc_loaded(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

896

void skl_enable_dc6(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

898

assert_can_enable_dc6(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

900

drm_dbg_kms(display->drm, "Enabling DC6\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

903

if (DISPLAY_VER(display) == 9 && !display->platform.broxton)

drivers/gpu/drm/i915/display/intel_display_power_well.c

904

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

drivers/gpu/drm/i915/display/intel_display_power_well.c

907

intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);

drivers/gpu/drm/i915/display/intel_display_power_well.c

909

gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);

drivers/gpu/drm/i915/display/intel_display_power_well.c

912

void bxt_enable_dc9(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

914

assert_can_enable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

916

drm_dbg_kms(display->drm, "Enabling DC9\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

921

if (display->platform.broxton || display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_display_power_well.c

922

bxt_pps_reset_all(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

923

gen9_set_dc_state(display, DC_STATE_EN_DC9);

drivers/gpu/drm/i915/display/intel_display_power_well.c

926

void bxt_disable_dc9(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

928

assert_can_disable_dc9(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

930

drm_dbg_kms(display->drm, "Disabling DC9\n");

drivers/gpu/drm/i915/display/intel_display_power_well.c

932

gen9_set_dc_state(display, DC_STATE_DISABLE);

drivers/gpu/drm/i915/display/intel_display_power_well.c

934

intel_pps_unlock_regs_wa(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

937

static void hsw_power_well_sync_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

94

lookup_power_well(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

943

u32 bios_req = intel_de_read(display, regs->bios);

drivers/gpu/drm/i915/display/intel_display_power_well.c

947

u32 drv_req = intel_de_read(display, regs->driver);

drivers/gpu/drm/i915/display/intel_display_power_well.c

950

intel_de_write(display, regs->driver, drv_req | mask);

drivers/gpu/drm/i915/display/intel_display_power_well.c

951

intel_de_write(display, regs->bios, bios_req & ~mask);

drivers/gpu/drm/i915/display/intel_display_power_well.c

955

static void bxt_dpio_cmn_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

958

bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

961

static void bxt_dpio_cmn_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

964

bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

967

static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

970

return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

973

static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_power_well.c

977

power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A);

drivers/gpu/drm/i915/display/intel_display_power_well.c

979

bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

981

power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

drivers/gpu/drm/i915/display/intel_display_power_well.c

983

bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);

drivers/gpu/drm/i915/display/intel_display_power_well.c

985

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

986

power_well = lookup_power_well(display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

989

bxt_dpio_phy_verify_state(display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

99

for_each_power_well(display, power_well)

drivers/gpu/drm/i915/display/intel_display_power_well.c

994

static bool gen9_dc_off_power_well_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.c

997

return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

998

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);

drivers/gpu/drm/i915/display/intel_display_power_well.h

129

struct i915_power_well *lookup_power_well(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

132

void intel_power_well_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

134

void intel_power_well_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

136

void intel_power_well_sync_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

138

void intel_power_well_get(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

140

void intel_power_well_put(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

142

bool intel_power_well_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

145

bool intel_display_power_well_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_power_well.h

154

bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,

drivers/gpu/drm/i915/display/intel_display_power_well.h

157

void gen9_enable_dc5(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power_well.h

158

void skl_enable_dc6(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power_well.h

159

void gen9_sanitize_dc_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power_well.h

160

void gen9_set_dc_state(struct intel_display *display, u32 state);

drivers/gpu/drm/i915/display/intel_display_power_well.h

161

void gen9_disable_dc_states(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power_well.h

162

void bxt_enable_dc9(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_power_well.h

163

void bxt_disable_dc9(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

38

#define _MMIO_PIPE2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_PIPE_OFFSET((display), (pipe)) + (reg))

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

39

#define _MMIO_TRANS2(display, trans, reg) _MMIO(INTEL_DISPLAY_DEVICE_TRANS_OFFSET((display), (trans)) + (reg))

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

40

#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_CURSOR_OFFSET((display), (pipe)) + (reg))

drivers/gpu/drm/i915/display/intel_display_regs.h

1485

#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))

drivers/gpu/drm/i915/display/intel_display_reset.c

107

intel_pps_unlock_regs_wa(display);

drivers/gpu/drm/i915/display/intel_display_reset.c

108

intel_display_driver_init_hw(display);

drivers/gpu/drm/i915/display/intel_display_reset.c

109

intel_clock_gating_init(display->drm);

drivers/gpu/drm/i915/display/intel_display_reset.c

110

intel_cx0_pll_power_save_wa(display);

drivers/gpu/drm/i915/display/intel_display_reset.c

111

intel_hpd_init(display);

drivers/gpu/drm/i915/display/intel_display_reset.c

113

ret = __intel_display_driver_resume(display, state, ctx);

drivers/gpu/drm/i915/display/intel_display_reset.c

115

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_reset.c

118

intel_hpd_poll_disable(display);

drivers/gpu/drm/i915/display/intel_display_reset.c

125

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_display_reset.c

19

bool intel_display_reset_test(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_reset.c

21

return display->params.force_reset_modeset_test;

drivers/gpu/drm/i915/display/intel_display_reset.c

25

bool intel_display_reset_prepare(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_reset.c

28

struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;

drivers/gpu/drm/i915/display/intel_display_reset.c

32

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_reset.c

35

if (atomic_read(&display->restore.pending_fb_pin)) {

drivers/gpu/drm/i915/display/intel_display_reset.c

36

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_display_reset.c

45

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_display_reset.c

48

ret = drm_modeset_lock_all_ctx(display->drm, ctx);

drivers/gpu/drm/i915/display/intel_display_reset.c

58

state = drm_atomic_helper_duplicate_state(display->drm, ctx);

drivers/gpu/drm/i915/display/intel_display_reset.c

61

drm_err(display->drm, "Duplicating state failed with %i\n",

drivers/gpu/drm/i915/display/intel_display_reset.c

66

ret = drm_atomic_helper_disable_all(display->drm, ctx);

drivers/gpu/drm/i915/display/intel_display_reset.c

68

drm_err(display->drm, "Suspending crtc's failed with %i\n",

drivers/gpu/drm/i915/display/intel_display_reset.c

74

display->restore.modeset_state = state;

drivers/gpu/drm/i915/display/intel_display_reset.c

80

void intel_display_reset_finish(struct intel_display *display, bool test_only)

drivers/gpu/drm/i915/display/intel_display_reset.c

82

struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;

drivers/gpu/drm/i915/display/intel_display_reset.c

86

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_display_reset.c

89

state = fetch_and_zero(&display->restore.modeset_state);

drivers/gpu/drm/i915/display/intel_display_reset.c

98

drm_WARN_ON(display->drm, ret == -EDEADLK);

drivers/gpu/drm/i915/display/intel_display_reset.c

99

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_display_reset.h

15

bool intel_display_reset_test(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_reset.h

16

bool intel_display_reset_prepare(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_reset.h

18

void intel_display_reset_finish(struct intel_display *display, bool test_only);

drivers/gpu/drm/i915/display/intel_display_rpm.c

11

return display->parent->rpm->get_raw(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

14

void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref)

drivers/gpu/drm/i915/display/intel_display_rpm.c

16

display->parent->rpm->put_raw(display->drm, wakeref);

drivers/gpu/drm/i915/display/intel_display_rpm.c

19

struct ref_tracker *intel_display_rpm_get(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

21

return display->parent->rpm->get(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

24

struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

26

return display->parent->rpm->get_if_in_use(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

29

struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

31

return display->parent->rpm->get_noresume(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

34

void intel_display_rpm_put(struct intel_display *display, struct ref_tracker *wakeref)

drivers/gpu/drm/i915/display/intel_display_rpm.c

36

display->parent->rpm->put(display->drm, wakeref);

drivers/gpu/drm/i915/display/intel_display_rpm.c

39

void intel_display_rpm_put_unchecked(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

41

display->parent->rpm->put_unchecked(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

44

bool intel_display_rpm_suspended(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

46

return display->parent->rpm->suspended(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

49

void assert_display_rpm_held(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

51

display->parent->rpm->assert_held(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

54

void intel_display_rpm_assert_block(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

56

display->parent->rpm->assert_block(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

59

void intel_display_rpm_assert_unblock(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.c

61

display->parent->rpm->assert_unblock(display->drm);

drivers/gpu/drm/i915/display/intel_display_rpm.c

9

struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rpm.h

12

struct ref_tracker *intel_display_rpm_get(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

13

void intel_display_rpm_put(struct intel_display *display, struct ref_tracker *wakeref);

drivers/gpu/drm/i915/display/intel_display_rpm.h

23

bool intel_display_rpm_suspended(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

25

void assert_display_rpm_held(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

26

void intel_display_rpm_assert_block(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

27

void intel_display_rpm_assert_unblock(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

30

struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

31

void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref);

drivers/gpu/drm/i915/display/intel_display_rpm.h

33

struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

34

struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rpm.h

35

void intel_display_rpm_put_unchecked(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rps.c

101

spin_lock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_rps.c

102

ilk_disable_display_irq(display, DE_PCU_EVENT);

drivers/gpu/drm/i915/display/intel_display_rps.c

103

spin_unlock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_rps.c

106

void ilk_display_rps_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rps.c

108

intel_parent_rps_ilk_irq_handler(display);

drivers/gpu/drm/i915/display/intel_display_rps.c

29

struct intel_display *display = to_intel_display(wait->crtc->dev);

drivers/gpu/drm/i915/display/intel_display_rps.c

36

intel_parent_rps_boost_if_not_started(display, wait->fence);

drivers/gpu/drm/i915/display/intel_display_rps.c

50

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_display_rps.c

53

if (!intel_parent_rps_available(display))

drivers/gpu/drm/i915/display/intel_display_rps.c

56

if (DISPLAY_VER(display) < 6)

drivers/gpu/drm/i915/display/intel_display_rps.c

77

void intel_display_rps_mark_interactive(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_rps.c

81

if (!intel_parent_rps_available(display))

drivers/gpu/drm/i915/display/intel_display_rps.c

87

intel_parent_rps_mark_interactive(display, interactive);

drivers/gpu/drm/i915/display/intel_display_rps.c

92

void ilk_display_rps_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rps.c

94

spin_lock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_rps.c

95

ilk_enable_display_irq(display, DE_PCU_EVENT);

drivers/gpu/drm/i915/display/intel_display_rps.c

96

spin_unlock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_display_rps.c

99

void ilk_display_rps_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_rps.h

18

void intel_display_rps_mark_interactive(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_rps.h

21

void ilk_display_rps_enable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rps.h

22

void ilk_display_rps_disable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_rps.h

23

void ilk_display_rps_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_snapshot.c

17

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_display_snapshot.c

27

struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_snapshot.c

35

snapshot->display = display;

drivers/gpu/drm/i915/display/intel_display_snapshot.c

37

memcpy(&snapshot->info, DISPLAY_INFO(display), sizeof(snapshot->info));

drivers/gpu/drm/i915/display/intel_display_snapshot.c

38

memcpy(&snapshot->runtime_info, DISPLAY_RUNTIME_INFO(display),

drivers/gpu/drm/i915/display/intel_display_snapshot.c

43

snapshot->irq = intel_display_irq_snapshot_capture(display);

drivers/gpu/drm/i915/display/intel_display_snapshot.c

44

snapshot->overlay = intel_overlay_snapshot_capture(display);

drivers/gpu/drm/i915/display/intel_display_snapshot.c

45

snapshot->dmc = intel_dmc_snapshot_capture(display);

drivers/gpu/drm/i915/display/intel_display_snapshot.c

53

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_display_snapshot.c

58

display = snapshot->display;

drivers/gpu/drm/i915/display/intel_display_snapshot.c

61

intel_display_params_dump(&snapshot->params, display->drm->driver->name, p);

drivers/gpu/drm/i915/display/intel_display_snapshot.h

11

struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_trace.h

110

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_trace.h

117

for_each_intel_crtc(display->drm, it__) {

drivers/gpu/drm/i915/display/intel_display_trace.h

180

TP_PROTO(struct intel_display *display, enum pipe pipe),

drivers/gpu/drm/i915/display/intel_display_trace.h

181

TP_ARGS(display, pipe),

drivers/gpu/drm/i915/display/intel_display_trace.h

184

__string(dev, __dev_name_display(display))

drivers/gpu/drm/i915/display/intel_display_trace.h

191

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display_trace.h

204

TP_PROTO(struct intel_display *display, enum pipe pch_transcoder),

drivers/gpu/drm/i915/display/intel_display_trace.h

205

TP_ARGS(display, pch_transcoder),

drivers/gpu/drm/i915/display/intel_display_trace.h

208

__string(dev, __dev_name_display(display))

drivers/gpu/drm/i915/display/intel_display_trace.h

216

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_display_trace.h

229

TP_PROTO(struct intel_display *display, bool old, bool new),

drivers/gpu/drm/i915/display/intel_display_trace.h

230

TP_ARGS(display, old, new),

drivers/gpu/drm/i915/display/intel_display_trace.h

233

__string(dev, __dev_name_display(display))

drivers/gpu/drm/i915/display/intel_display_trace.h

247

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_display_trace.h

27

#define __dev_name_display(display) dev_name((display)->drm->dev)

drivers/gpu/drm/i915/display/intel_display_trace.h

520

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_display_trace.h

521

struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);

drivers/gpu/drm/i915/display/intel_display_trace.h

613

struct intel_display *display = to_intel_display(plane->base.dev);

drivers/gpu/drm/i915/display/intel_display_trace.h

614

struct intel_crtc *crtc = intel_crtc_for_pipe(display,

drivers/gpu/drm/i915/display/intel_display_trace.h

641

struct intel_display *display = to_intel_display(plane->base.dev);

drivers/gpu/drm/i915/display/intel_display_trace.h

642

struct intel_crtc *crtc = intel_crtc_for_pipe(display,

drivers/gpu/drm/i915/display/intel_display_trace.h

669

struct intel_display *display = to_intel_display(plane->base.dev);

drivers/gpu/drm/i915/display/intel_display_trace.h

670

struct intel_crtc *crtc = intel_crtc_for_pipe(display,

drivers/gpu/drm/i915/display/intel_display_trace.h

80

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_display_trace.h

810

TP_PROTO(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_trace.h

812

TP_ARGS(display, frontbuffer_bits, origin),

drivers/gpu/drm/i915/display/intel_display_trace.h

815

__string(dev, __dev_name_display(display))

drivers/gpu/drm/i915/display/intel_display_trace.h

831

TP_PROTO(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_display_trace.h

833

TP_ARGS(display, frontbuffer_bits, origin),

drivers/gpu/drm/i915/display/intel_display_trace.h

836

__string(dev, __dev_name_display(display))

drivers/gpu/drm/i915/display/intel_display_trace.h

856

#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/display

drivers/gpu/drm/i915/display/intel_display_trace.h

87

for_each_intel_crtc(display->drm, it__) {

drivers/gpu/drm/i915/display/intel_display_utils.c

15

bool intel_display_run_as_guest(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_utils.c

25

bool intel_display_vtd_active(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_utils.c

27

if (device_iommu_mapped(display->drm->dev))

drivers/gpu/drm/i915/display/intel_display_utils.c

31

return intel_display_run_as_guest(display);

drivers/gpu/drm/i915/display/intel_display_utils.h

24

bool intel_display_run_as_guest(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_utils.h

25

bool intel_display_vtd_active(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_wa.c

14

static void gen11_display_wa_apply(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_wa.c

17

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);

drivers/gpu/drm/i915/display/intel_display_wa.c

20

static void xe_d_display_wa_apply(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_wa.c

23

intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);

drivers/gpu/drm/i915/display/intel_display_wa.c

26

static void adlp_display_wa_apply(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_wa.c

29

intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);

drivers/gpu/drm/i915/display/intel_display_wa.c

32

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);

drivers/gpu/drm/i915/display/intel_display_wa.c

35

void intel_display_wa_apply(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_wa.c

37

if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_display_wa.c

38

adlp_display_wa_apply(display);

drivers/gpu/drm/i915/display/intel_display_wa.c

39

else if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/intel_display_wa.c

40

xe_d_display_wa_apply(display);

drivers/gpu/drm/i915/display/intel_display_wa.c

41

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display_wa.c

42

gen11_display_wa_apply(display);

drivers/gpu/drm/i915/display/intel_display_wa.c

50

static bool intel_display_needs_wa_16025573575(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_wa.c

52

return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||

drivers/gpu/drm/i915/display/intel_display_wa.c

53

DISPLAY_VERx100(display) == 3500;

drivers/gpu/drm/i915/display/intel_display_wa.c

62

bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)

drivers/gpu/drm/i915/display/intel_display_wa.c

66

return DISPLAY_VERx100(display) == 3000;

drivers/gpu/drm/i915/display/intel_display_wa.c

68

return DISPLAY_VER(display) == 13;

drivers/gpu/drm/i915/display/intel_display_wa.c

70

return DISPLAY_VER(display) == 35;

drivers/gpu/drm/i915/display/intel_display_wa.c

72

return display->platform.battlemage;

drivers/gpu/drm/i915/display/intel_display_wa.c

74

return intel_display_needs_wa_16023588340(display);

drivers/gpu/drm/i915/display/intel_display_wa.c

76

return intel_display_needs_wa_16025573575(display);

drivers/gpu/drm/i915/display/intel_display_wa.c

78

return IS_DISPLAY_VERx100(display, 1100, 1400);

drivers/gpu/drm/i915/display/intel_display_wa.c

80

drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);

drivers/gpu/drm/i915/display/intel_display_wa.h

13

void intel_display_wa_apply(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_wa.h

16

static inline bool intel_display_needs_wa_16023588340(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_display_wa.h

21

bool intel_display_needs_wa_16023588340(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_display_wa.h

39

bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

109

intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)

drivers/gpu/drm/i915/display/intel_dkl_phy.c

111

spin_lock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

113

dkl_phy_set_hip_idx(display, reg);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

114

intel_de_posting_read(display, DKL_REG_MMIO(reg));

drivers/gpu/drm/i915/display/intel_dkl_phy.c

116

spin_unlock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

18

void intel_dkl_phy_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dkl_phy.c

20

spin_lock_init(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

24

dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)

drivers/gpu/drm/i915/display/intel_dkl_phy.c

28

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dkl_phy.c

32

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_dkl_phy.c

47

intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)

drivers/gpu/drm/i915/display/intel_dkl_phy.c

51

spin_lock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

53

dkl_phy_set_hip_idx(display, reg);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

54

val = intel_de_read(display, DKL_REG_MMIO(reg));

drivers/gpu/drm/i915/display/intel_dkl_phy.c

56

spin_unlock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

70

intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)

drivers/gpu/drm/i915/display/intel_dkl_phy.c

72

spin_lock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

74

dkl_phy_set_hip_idx(display, reg);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

75

intel_de_write(display, DKL_REG_MMIO(reg), val);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

77

spin_unlock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

91

intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)

drivers/gpu/drm/i915/display/intel_dkl_phy.c

93

spin_lock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

95

dkl_phy_set_hip_idx(display, reg);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

96

intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

98

spin_unlock(&display->dkl.phy_lock);

drivers/gpu/drm/i915/display/intel_dkl_phy.h

15

void intel_dkl_phy_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dkl_phy.h

17

intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);

drivers/gpu/drm/i915/display/intel_dkl_phy.h

19

intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);

drivers/gpu/drm/i915/display/intel_dkl_phy.h

21

intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);

drivers/gpu/drm/i915/display/intel_dkl_phy.h

23

intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);

drivers/gpu/drm/i915/display/intel_dmc.c

1001

drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

101

const char *p = dmc_firmware_param(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1023

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.c

1033

} else if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_dmc.c

1036

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dmc.c

1040

drm_warn(display->drm, "Unknown mmio range for sanity check");

drivers/gpu/drm/i915/display/intel_dmc.c

1056

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.c

1104

drm_err(display->drm, "Unknown DMC fw header version: %u\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1110

drm_err(display->drm, "DMC firmware has wrong dmc header length "

drivers/gpu/drm/i915/display/intel_dmc.c

1117

drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);

drivers/gpu/drm/i915/display/intel_dmc.c

1123

drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1127

drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

1139

if (!fixup_dmc_evt(display, dmc_id,

drivers/gpu/drm/i915/display/intel_dmc.c

1144

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dmc.c

1148

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dmc.c

1155

drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1157

is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :

drivers/gpu/drm/i915/display/intel_dmc.c

1158

is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",

drivers/gpu/drm/i915/display/intel_dmc.c

1159

disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],

drivers/gpu/drm/i915/display/intel_dmc.c

1173

drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);

drivers/gpu/drm/i915/display/intel_dmc.c

1188

drm_err(display->drm, "Truncated DMC firmware, refusing.\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1198

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.c

1211

drm_err(display->drm, "DMC firmware has unknown header version %u\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1225

drm_err(display->drm, "DMC firmware has wrong package header length "

drivers/gpu/drm/i915/display/intel_dmc.c

1243

drm_err(display->drm, "Truncated DMC firmware, refusing.\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1252

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.c

1255

drm_err(display->drm, "Truncated DMC firmware, refusing.\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1261

drm_err(display->drm, "DMC firmware has wrong CSS header length "

drivers/gpu/drm/i915/display/intel_dmc.c

1274

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.c

1279

const struct stepping_info *si = intel_get_stepping_info(display, &display_info);

drivers/gpu/drm/i915/display/intel_dmc.c

1309

drm_err(display->drm, "Reading beyond the fw_size\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1317

if (!intel_dmc_has_payload(display)) {

drivers/gpu/drm/i915/display/intel_dmc.c

1318

drm_err(display->drm, "DMC firmware main program not found\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1325

static void intel_dmc_runtime_pm_get(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1327

drm_WARN_ON(display->drm, display->dmc.wakeref);

drivers/gpu/drm/i915/display/intel_dmc.c

1328

display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

drivers/gpu/drm/i915/display/intel_dmc.c

1331

static void intel_dmc_runtime_pm_put(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1334

fetch_and_zero(&display->dmc.wakeref);

drivers/gpu/drm/i915/display/intel_dmc.c

1336

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

drivers/gpu/drm/i915/display/intel_dmc.c

1339

static const char *dmc_fallback_path(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1341

if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_dmc.c

1350

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.c

1355

err = request_firmware(&fw, dmc->fw_path, display->drm->dev);

drivers/gpu/drm/i915/display/intel_dmc.c

1357

if (err == -ENOENT && !dmc_firmware_param(display)) {

drivers/gpu/drm/i915/display/intel_dmc.c

1358

fallback_path = dmc_fallback_path(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1360

drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1362

err = request_firmware(&fw, fallback_path, display->drm->dev);

drivers/gpu/drm/i915/display/intel_dmc.c

1369

drm_notice(display->drm,

drivers/gpu/drm/i915/display/intel_dmc.c

1372

drm_notice(display->drm, "DMC firmware homepage: %s",

drivers/gpu/drm/i915/display/intel_dmc.c

1379

drm_notice(display->drm,

drivers/gpu/drm/i915/display/intel_dmc.c

1385

intel_dmc_load_program(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1386

intel_dmc_runtime_pm_put(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1388

drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1403

void intel_dmc_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1407

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1418

intel_dmc_runtime_pm_get(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1424

dmc->display = display;

drivers/gpu/drm/i915/display/intel_dmc.c

1428

dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);

drivers/gpu/drm/i915/display/intel_dmc.c

1430

if (dmc_firmware_param_disabled(display)) {

drivers/gpu/drm/i915/display/intel_dmc.c

1431

drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");

drivers/gpu/drm/i915/display/intel_dmc.c

1435

if (dmc_firmware_param(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1436

dmc->fw_path = dmc_firmware_param(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1439

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dmc.c

1444

display->dmc.dmc = dmc;

drivers/gpu/drm/i915/display/intel_dmc.c

1446

drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);

drivers/gpu/drm/i915/display/intel_dmc.c

1447

queue_work(display->wq.unordered, &dmc->work);

drivers/gpu/drm/i915/display/intel_dmc.c

1463

void intel_dmc_suspend(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1465

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1467

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1474

if (!intel_dmc_has_payload(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1475

intel_dmc_runtime_pm_put(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1478

void intel_dmc_wait_fw_load(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1480

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1482

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1496

void intel_dmc_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1498

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1505

if (!intel_dmc_has_payload(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1506

intel_dmc_runtime_pm_get(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1516

void intel_dmc_fini(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1518

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1521

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1524

intel_dmc_suspend(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1525

drm_WARN_ON(display->drm, display->dmc.wakeref);

drivers/gpu/drm/i915/display/intel_dmc.c

1532

display->dmc.dmc = NULL;

drivers/gpu/drm/i915/display/intel_dmc.c

1542

struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1544

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1547

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1555

snapshot->loaded = intel_dmc_has_payload(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1575

void intel_dmc_update_dc6_allowed_count(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

1578

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1581

if (DISPLAY_VER(dmc->display) < 14)

drivers/gpu/drm/i915/display/intel_dmc.c

1584

dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);

drivers/gpu/drm/i915/display/intel_dmc.c

1592

static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)

drivers/gpu/drm/i915/display/intel_dmc.c

1594

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_dmc.c

1595

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1598

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_dmc.c

1604

intel_dmc_update_dc6_allowed_count(display, false);

drivers/gpu/drm/i915/display/intel_dmc.c

1614

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_dmc.c

1615

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1620

if (!HAS_DMC(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1623

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1627

str_yes_no(intel_dmc_has_payload(display)));

drivers/gpu/drm/i915/display/intel_dmc.c

1630

str_yes_no(DISPLAY_VER(display) >= 12));

drivers/gpu/drm/i915/display/intel_dmc.c

1632

str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));

drivers/gpu/drm/i915/display/intel_dmc.c

1634

str_yes_no(display->platform.alderlake_p ||

drivers/gpu/drm/i915/display/intel_dmc.c

1635

DISPLAY_VER(display) >= 14));

drivers/gpu/drm/i915/display/intel_dmc.c

1637

str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));

drivers/gpu/drm/i915/display/intel_dmc.c

1639

if (!intel_dmc_has_payload(display))

drivers/gpu/drm/i915/display/intel_dmc.c

1645

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dmc.c

1648

if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_dmc.c

1658

intel_de_read(display, dc3co_reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1660

dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT :

drivers/gpu/drm/i915/display/intel_dmc.c

1662

if (!display->platform.geminilake && !display->platform.broxton)

drivers/gpu/drm/i915/display/intel_dmc.c

1666

seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1668

if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))

drivers/gpu/drm/i915/display/intel_dmc.c

1673

intel_de_read(display, dc6_reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1676

intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

drivers/gpu/drm/i915/display/intel_dmc.c

1680

intel_de_read(display, DMC_SSP_BASE));

drivers/gpu/drm/i915/display/intel_dmc.c

1681

seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));

drivers/gpu/drm/i915/display/intel_dmc.c

1683

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_dmc.c

1690

void intel_dmc_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

1692

debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root,

drivers/gpu/drm/i915/display/intel_dmc.c

1693

display, &intel_dmc_debugfs_status_fops);

drivers/gpu/drm/i915/display/intel_dmc.c

1696

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dmc.c

1698

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_dmc.c

1701

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_dmc.c

1702

tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));

drivers/gpu/drm/i915/display/intel_dmc.c

1703

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);

drivers/gpu/drm/i915/display/intel_dmc.c

1706

spin_lock(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_dmc.c

1719

spin_unlock(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_dmc.c

1723

drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1726

drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1729

drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1733

int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;

drivers/gpu/drm/i915/display/intel_dmc.c

1735

drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n",

drivers/gpu/drm/i915/display/intel_dmc.c

1742

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dmc.c

1745

dmc_configure_event(display, dmc_id, event, true);

drivers/gpu/drm/i915/display/intel_dmc.c

1751

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dmc.c

1754

dmc_configure_event(display, dmc_id, event, false);

drivers/gpu/drm/i915/display/intel_dmc.c

1759

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dmc.c

1760

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

1768

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dmc.c

1771

intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),

drivers/gpu/drm/i915/display/intel_dmc.c

1777

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dmc.c

1780

intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);

drivers/gpu/drm/i915/display/intel_dmc.c

188

static const char *dmc_firmware_default(struct intel_display *display, u32 *size)

drivers/gpu/drm/i915/display/intel_dmc.c

193

if (DISPLAY_VERx100(display) == 3500) {

drivers/gpu/drm/i915/display/intel_dmc.c

196

} else if (DISPLAY_VERx100(display) == 3002) {

drivers/gpu/drm/i915/display/intel_dmc.c

199

} else if (DISPLAY_VERx100(display) == 3000) {

drivers/gpu/drm/i915/display/intel_dmc.c

202

} else if (DISPLAY_VERx100(display) == 2000) {

drivers/gpu/drm/i915/display/intel_dmc.c

205

} else if (DISPLAY_VERx100(display) == 1401) {

drivers/gpu/drm/i915/display/intel_dmc.c

208

} else if (DISPLAY_VERx100(display) == 1400) {

drivers/gpu/drm/i915/display/intel_dmc.c

211

} else if (display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_dmc.c

214

} else if (display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/intel_dmc.c

217

} else if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_dmc.c

220

} else if (display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_dmc.c

223

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_dmc.c

226

} else if (display->platform.tigerlake) {

drivers/gpu/drm/i915/display/intel_dmc.c

229

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/intel_dmc.c

232

} else if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_dmc.c

235

} else if (display->platform.kabylake ||

drivers/gpu/drm/i915/display/intel_dmc.c

236

display->platform.coffeelake ||

drivers/gpu/drm/i915/display/intel_dmc.c

237

display->platform.cometlake) {

drivers/gpu/drm/i915/display/intel_dmc.c

240

} else if (display->platform.skylake) {

drivers/gpu/drm/i915/display/intel_dmc.c

243

} else if (display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_dmc.c

410

static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)

drivers/gpu/drm/i915/display/intel_dmc.c

412

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

417

bool intel_dmc_has_payload(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

419

return has_dmc_id_fw(display, DMC_FW_MAIN);

drivers/gpu/drm/i915/display/intel_dmc.c

423

intel_get_stepping_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

426

const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));

drivers/gpu/drm/i915/display/intel_dmc.c

433

static void gen9_set_dc_state_debugmask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

436

intel_de_rmw(display, DC_STATE_DEBUG, 0,

drivers/gpu/drm/i915/display/intel_dmc.c

438

intel_de_posting_read(display, DC_STATE_DEBUG);

drivers/gpu/drm/i915/display/intel_dmc.c

441

static void disable_event_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

444

intel_de_write(display, ctl_reg,

drivers/gpu/drm/i915/display/intel_dmc.c

449

intel_de_write(display, htp_reg, 0);

drivers/gpu/drm/i915/display/intel_dmc.c

452

static void disable_all_event_handlers(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

458

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_dmc.c

461

if (!has_dmc_id_fw(display, dmc_id))

drivers/gpu/drm/i915/display/intel_dmc.c

465

disable_event_handler(display,

drivers/gpu/drm/i915/display/intel_dmc.c

466

DMC_EVT_CTL(display, dmc_id, handler),

drivers/gpu/drm/i915/display/intel_dmc.c

467

DMC_EVT_HTP(display, dmc_id, handler));

drivers/gpu/drm/i915/display/intel_dmc.c

470

static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/intel_dmc.c

483

intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),

drivers/gpu/drm/i915/display/intel_dmc.c

487

intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),

drivers/gpu/drm/i915/display/intel_dmc.c

491

static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

498

intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,

drivers/gpu/drm/i915/display/intel_dmc.c

503

static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/intel_dmc.c

505

if (display->platform.meteorlake && enable)

drivers/gpu/drm/i915/display/intel_dmc.c

506

mtl_pipedmc_clock_gating_wa(display);

drivers/gpu/drm/i915/display/intel_dmc.c

507

else if (DISPLAY_VER(display) == 13)

drivers/gpu/drm/i915/display/intel_dmc.c

508

adlp_pipedmc_clock_gating_wa(display, enable);

drivers/gpu/drm/i915/display/intel_dmc.c

511

static u32 pipedmc_interrupt_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

537

static bool is_dmc_evt_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

541

u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));

drivers/gpu/drm/i915/display/intel_dmc.c

542

u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

drivers/gpu/drm/i915/display/intel_dmc.c

547

static bool is_dmc_evt_htp_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

551

u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));

drivers/gpu/drm/i915/display/intel_dmc.c

552

u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

drivers/gpu/drm/i915/display/intel_dmc.c

557

static bool is_event_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

562

return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&

drivers/gpu/drm/i915/display/intel_dmc.c

566

static bool fixup_dmc_evt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

571

if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))

drivers/gpu/drm/i915/display/intel_dmc.c

574

if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp))

drivers/gpu/drm/i915/display/intel_dmc.c

578

if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=

drivers/gpu/drm/i915/display/intel_dmc.c

579

i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))

drivers/gpu/drm/i915/display/intel_dmc.c

586

if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN &&

drivers/gpu/drm/i915/display/intel_dmc.c

587

is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {

drivers/gpu/drm/i915/display/intel_dmc.c

600

if ((display->platform.tigerlake || display->platform.alderlake_s) &&

drivers/gpu/drm/i915/display/intel_dmc.c

601

is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {

drivers/gpu/drm/i915/display/intel_dmc.c

611

static bool disable_dmc_evt(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

615

if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))

drivers/gpu/drm/i915/display/intel_dmc.c

623

if (display->platform.tigerlake &&

drivers/gpu/drm/i915/display/intel_dmc.c

624

is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))

drivers/gpu/drm/i915/display/intel_dmc.c

628

if ((display->platform.tigerlake || display->platform.alderlake_s) &&

drivers/gpu/drm/i915/display/intel_dmc.c

629

is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data))

drivers/gpu/drm/i915/display/intel_dmc.c

635

static u32 dmc_mmiodata(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

639

if (disable_dmc_evt(display, dmc_id,

drivers/gpu/drm/i915/display/intel_dmc.c

647

static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id)

drivers/gpu/drm/i915/display/intel_dmc.c

649

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

65

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_dmc.c

653

intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],

drivers/gpu/drm/i915/display/intel_dmc.c

654

dmc_mmiodata(display, dmc, dmc_id, i));

drivers/gpu/drm/i915/display/intel_dmc.c

658

static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id)

drivers/gpu/drm/i915/display/intel_dmc.c

660

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

663

disable_all_event_handlers(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

668

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/intel_dmc.c

675

dmc_load_mmio(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

678

static void assert_dmc_loaded(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

681

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

685

if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))

drivers/gpu/drm/i915/display/intel_dmc.c

688

found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));

drivers/gpu/drm/i915/display/intel_dmc.c

691

drm_WARN(display->drm, found != expected,

drivers/gpu/drm/i915/display/intel_dmc.c

698

found = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_dmc.c

699

expected = dmc_mmiodata(display, dmc, dmc_id, i);

drivers/gpu/drm/i915/display/intel_dmc.c

701

drm_WARN(display->drm, found != expected,

drivers/gpu/drm/i915/display/intel_dmc.c

707

void assert_main_dmc_loaded(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

709

assert_dmc_loaded(display, DMC_FW_MAIN);

drivers/gpu/drm/i915/display/intel_dmc.c

712

static bool need_pipedmc_load_program(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

715

return DISPLAY_VER(display) == 12;

drivers/gpu/drm/i915/display/intel_dmc.c

718

static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dmc.c

725

if (IS_DISPLAY_VER(display, 30, 35))

drivers/gpu/drm/i915/display/intel_dmc.c

734

if (DISPLAY_VER(display) == 20)

drivers/gpu/drm/i915/display/intel_dmc.c

741

if (display->platform.battlemage)

drivers/gpu/drm/i915/display/intel_dmc.c

750

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_dmc.c

758

if (IS_DISPLAY_VER(display, 13, 14))

drivers/gpu/drm/i915/display/intel_dmc.c

766

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

773

if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_dmc.c

781

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

786

if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))

drivers/gpu/drm/i915/display/intel_dmc.c

794

if (need_pipedmc_load_program(display))

drivers/gpu/drm/i915/display/intel_dmc.c

795

dmc_load_program(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

796

else if (need_pipedmc_load_mmio(display, pipe))

drivers/gpu/drm/i915/display/intel_dmc.c

797

dmc_load_mmio(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

799

assert_dmc_loaded(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

801

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_dmc.c

802

intel_flipq_reset(display, pipe);

drivers/gpu/drm/i915/display/intel_dmc.c

804

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));

drivers/gpu/drm/i915/display/intel_dmc.c

805

intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));

drivers/gpu/drm/i915/display/intel_dmc.c

808

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dmc.c

809

intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));

drivers/gpu/drm/i915/display/intel_dmc.c

811

intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);

drivers/gpu/drm/i915/display/intel_dmc.c

816

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

821

if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))

drivers/gpu/drm/i915/display/intel_dmc.c

824

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dmc.c

825

intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);

drivers/gpu/drm/i915/display/intel_dmc.c

827

intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dmc.c

829

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_dmc.c

830

intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);

drivers/gpu/drm/i915/display/intel_dmc.c

831

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));

drivers/gpu/drm/i915/display/intel_dmc.c

833

intel_flipq_reset(display, pipe);

drivers/gpu/drm/i915/display/intel_dmc.c

837

static void dmc_configure_event(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

842

struct intel_dmc *dmc = display_to_dmc(display);

drivers/gpu/drm/i915/display/intel_dmc.c

850

if (!is_event_handler(display, dmc_id, event_id, reg, data))

drivers/gpu/drm/i915/display/intel_dmc.c

853

intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data));

drivers/gpu/drm/i915/display/intel_dmc.c

857

drm_WARN_ONCE(display->drm, num_handlers != 1,

drivers/gpu/drm/i915/display/intel_dmc.c

862

void intel_dmc_configure_dc_balance_event(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

867

dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);

drivers/gpu/drm/i915/display/intel_dmc.c

87

static struct intel_dmc *display_to_dmc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

879

void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_dmc.c

882

intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe),

drivers/gpu/drm/i915/display/intel_dmc.c

89

return display->dmc.dmc;

drivers/gpu/drm/i915/display/intel_dmc.c

897

void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.c

902

dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable);

drivers/gpu/drm/i915/display/intel_dmc.c

913

void intel_dmc_load_program(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

915

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_dmc.c

918

if (!intel_dmc_has_payload(display))

drivers/gpu/drm/i915/display/intel_dmc.c

92

static const char *dmc_firmware_param(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

921

assert_display_rpm_held(display);

drivers/gpu/drm/i915/display/intel_dmc.c

923

pipedmc_clock_gating_wa(display, true);

drivers/gpu/drm/i915/display/intel_dmc.c

926

dmc_load_program(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

927

assert_dmc_loaded(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

930

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_dmc.c

931

intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,

drivers/gpu/drm/i915/display/intel_dmc.c

939

gen9_set_dc_state_debugmask(display);

drivers/gpu/drm/i915/display/intel_dmc.c

94

const char *p = display->params.dmc_firmware_path;

drivers/gpu/drm/i915/display/intel_dmc.c

941

pipedmc_clock_gating_wa(display, false);

drivers/gpu/drm/i915/display/intel_dmc.c

951

void intel_dmc_disable_program(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

955

if (!intel_dmc_has_payload(display))

drivers/gpu/drm/i915/display/intel_dmc.c

958

pipedmc_clock_gating_wa(display, true);

drivers/gpu/drm/i915/display/intel_dmc.c

961

disable_all_event_handlers(display, dmc_id);

drivers/gpu/drm/i915/display/intel_dmc.c

963

pipedmc_clock_gating_wa(display, false);

drivers/gpu/drm/i915/display/intel_dmc.c

99

static bool dmc_firmware_param_disabled(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc.c

993

struct intel_display *display = dmc->display;

drivers/gpu/drm/i915/display/intel_dmc.h

20

void intel_dmc_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

21

void intel_dmc_load_program(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

22

void intel_dmc_wait_fw_load(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

23

void intel_dmc_disable_program(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

26

void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_dmc.h

28

void intel_dmc_configure_dc_balance_event(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.h

30

void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc.h

32

void intel_dmc_fini(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

33

void intel_dmc_suspend(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

34

void intel_dmc_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

35

bool intel_dmc_has_payload(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

36

void intel_dmc_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

38

struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

40

void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);

drivers/gpu/drm/i915/display/intel_dmc.h

42

void assert_main_dmc_loaded(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc.h

44

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dmc.h

54

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

155

static void __intel_dmc_wl_release(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

157

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

161

queue_delayed_work(display->wq.unordered, &wl->work,

drivers/gpu/drm/i915/display/intel_dmc_wl.c

169

struct intel_display *display =

drivers/gpu/drm/i915/display/intel_dmc_wl.c

182

intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

184

if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,

drivers/gpu/drm/i915/display/intel_dmc_wl.c

197

static void __intel_dmc_wl_take(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

199

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

210

intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, 0, DMC_WAKELOCK_CTL_REQ);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

216

if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,

drivers/gpu/drm/i915/display/intel_dmc_wl.c

242

static bool intel_dmc_wl_check_range(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dmc_wl.c

248

if (display->params.enable_dmc_wl == ENABLE_DMC_WL_ANY_REGISTER)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

280

static bool __intel_dmc_wl_supported(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

282

return display->params.enable_dmc_wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

285

static void intel_dmc_wl_sanitize_param(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

289

if (!HAS_DMC_WAKELOCK(display)) {

drivers/gpu/drm/i915/display/intel_dmc_wl.c

290

display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

291

} else if (display->params.enable_dmc_wl < 0) {

drivers/gpu/drm/i915/display/intel_dmc_wl.c

292

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

293

display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

295

display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

296

} else if (display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX) {

drivers/gpu/drm/i915/display/intel_dmc_wl.c

297

display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

300

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dmc_wl.c

301

display->params.enable_dmc_wl < 0 ||

drivers/gpu/drm/i915/display/intel_dmc_wl.c

302

display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

304

switch (display->params.enable_dmc_wl) {

drivers/gpu/drm/i915/display/intel_dmc_wl.c

322

drm_dbg_kms(display->drm, "Sanitized enable_dmc_wl value: %d (%s)\n",

drivers/gpu/drm/i915/display/intel_dmc_wl.c

323

display->params.enable_dmc_wl, desc);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

326

void intel_dmc_wl_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

328

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

330

intel_dmc_wl_sanitize_param(display);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

332

if (!display->params.enable_dmc_wl)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

338

display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

342

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

344

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

347

if (!__intel_dmc_wl_supported(display))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

354

if (drm_WARN_ON(display->drm, wl->enabled))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

362

intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

381

__intel_dmc_wl_take(display);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

388

void intel_dmc_wl_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

390

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

393

if (!__intel_dmc_wl_supported(display))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

396

intel_dmc_wl_flush_release_work(display);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

400

if (drm_WARN_ON(display->drm, !wl->enabled))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

404

intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

416

intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

424

void intel_dmc_wl_flush_release_work(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

426

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

428

if (!__intel_dmc_wl_supported(display))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

434

void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

436

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

439

if (!__intel_dmc_wl_supported(display))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

445

!intel_dmc_wl_check_range(display, reg, wl->dc_state))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

461

__intel_dmc_wl_take(display);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

467

void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

469

struct intel_dmc_wl *wl = &display->wl;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

472

if (!__intel_dmc_wl_supported(display))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

478

!intel_dmc_wl_check_range(display, reg, wl->dc_state))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

489

__intel_dmc_wl_release(display);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

498

void intel_dmc_wl_get_noreg(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

500

intel_dmc_wl_get(display, INVALID_MMIO_REG);

drivers/gpu/drm/i915/display/intel_dmc_wl.c

503

void intel_dmc_wl_put_noreg(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

505

intel_dmc_wl_put(display, INVALID_MMIO_REG);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

32

void intel_dmc_wl_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

33

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

34

void intel_dmc_wl_disable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

35

void intel_dmc_wl_flush_release_work(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

36

void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

37

void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

38

void intel_dmc_wl_get_noreg(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dmc_wl.h

39

void intel_dmc_wl_put_noreg(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp.c

1013

if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))

drivers/gpu/drm/i915/display/intel_dp.c

1018

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

1037

(!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4))

drivers/gpu/drm/i915/display/intel_dp.c

1061

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

1073

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1085

return !HAS_GMCH(display) && !display->platform.ironlake;

drivers/gpu/drm/i915/display/intel_dp.c

1089

return DISPLAY_VER(display) >= 11;

drivers/gpu/drm/i915/display/intel_dp.c

1149

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1161

drm_dbg_kms(display->drm, "Cannot force DSC output format\n");

drivers/gpu/drm/i915/display/intel_dp.c

1175

drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));

drivers/gpu/drm/i915/display/intel_dp.c

1227

static bool intel_dp_hdisplay_bad(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.c

1243

return hdisplay == 4096 && !HAS_DDI(display);

drivers/gpu/drm/i915/display/intel_dp.c

1344

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1352

hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;

drivers/gpu/drm/i915/display/intel_dp.c

1354

return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||

drivers/gpu/drm/i915/display/intel_dp.c

1362

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1367

if (HAS_ULTRAJOINER(display) &&

drivers/gpu/drm/i915/display/intel_dp.c

1371

if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) &&

drivers/gpu/drm/i915/display/intel_dp.c

1380

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1382

if (!HAS_DSC(display))

drivers/gpu/drm/i915/display/intel_dp.c

1385

if (connector->mst.dp && !HAS_DSC_MST(display))

drivers/gpu/drm/i915/display/intel_dp.c

1402

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_dp.c

1409

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_dp.c

1417

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_dp.c

1443

status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);

drivers/gpu/drm/i915/display/intel_dp.c

1450

if (intel_dp_hdisplay_bad(display, mode->hdisplay))

drivers/gpu/drm/i915/display/intel_dp.c

1498

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)

drivers/gpu/drm/i915/display/intel_dp.c

1508

return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);

drivers/gpu/drm/i915/display/intel_dp.c

1511

bool intel_dp_source_supports_tps3(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

1513

return DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_dp.c

1514

display->platform.broadwell || display->platform.haswell;

drivers/gpu/drm/i915/display/intel_dp.c

1517

bool intel_dp_source_supports_tps4(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

1519

return DISPLAY_VER(display) >= 10;

drivers/gpu/drm/i915/display/intel_dp.c

1532

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1539

drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));

drivers/gpu/drm/i915/display/intel_dp.c

1543

drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));

drivers/gpu/drm/i915/display/intel_dp.c

1547

drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));

drivers/gpu/drm/i915/display/intel_dp.c

1584

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1588

if (drm_WARN_ON(display->drm, i < 0))

drivers/gpu/drm/i915/display/intel_dp.c

1597

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1600

if (display->platform.g4x && port_clock == 268800)

drivers/gpu/drm/i915/display/intel_dp.c

1624

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1627

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dp.c

1630

if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&

drivers/gpu/drm/i915/display/intel_dp.c

1695

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1721

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

1733

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1739

return HAS_DOUBLE_BUFFERED_M_N(display) &&

drivers/gpu/drm/i915/display/intel_dp.c

174

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1806

int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

1809

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dp.c

1811

if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_dp.c

1854

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1857

dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);

drivers/gpu/drm/i915/display/intel_dp.c

1867

static int intel_dp_source_dsc_version_minor(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

1869

return DISPLAY_VER(display) >= 14 ? 2 : 1;

drivers/gpu/drm/i915/display/intel_dp.c

188

if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))

drivers/gpu/drm/i915/display/intel_dp.c

1903

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1926

min(intel_dp_source_dsc_version_minor(display),

drivers/gpu/drm/i915/display/intel_dp.c

1936

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

1951

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1962

if (min(intel_dp_source_dsc_version_minor(display),

drivers/gpu/drm/i915/display/intel_dp.c

2113

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2128

if (DISPLAY_VER(display) < 13)

drivers/gpu/drm/i915/display/intel_dp.c

2139

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2142

if (DISPLAY_VER(display) < 14 || !incr)

drivers/gpu/drm/i915/display/intel_dp.c

2159

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2161

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_dp.c

2176

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2178

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_dp.c

2181

drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));

drivers/gpu/drm/i915/display/intel_dp.c

2193

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2199

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_dp.c

2200

drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));

drivers/gpu/drm/i915/display/intel_dp.c

2218

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2252

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2280

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2289

drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",

drivers/gpu/drm/i915/display/intel_dp.c

2294

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2353

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2379

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2391

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2405

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2429

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2439

drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "

drivers/gpu/drm/i915/display/intel_dp.c

2502

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2509

joiner_max_bpp = get_max_compressed_bpp_with_joiner(display,

drivers/gpu/drm/i915/display/intel_dp.c

2526

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2580

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2614

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2637

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2640

int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);

drivers/gpu/drm/i915/display/intel_dp.c

2650

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2671

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2705

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2753

bool intel_dp_joiner_needs_dsc(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.c

2762

return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||

drivers/gpu/drm/i915/display/intel_dp.c

2772

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

2794

joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);

drivers/gpu/drm/i915/display/intel_dp.c

281

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2821

drm_dbg_kms(display->drm, "DSC required but not available\n");

drivers/gpu/drm/i915/display/intel_dp.c

2826

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2843

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2890

static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_dp.c

2892

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_dp.c

2894

if (DISPLAY_VER(display) < 12 && port == PORT_A)

drivers/gpu/drm/i915/display/intel_dp.c

2904

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

291

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

2981

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

306

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3082

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3092

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3105

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

3123

if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder))

drivers/gpu/drm/i915/display/intel_dp.c

3135

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

3148

if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))

drivers/gpu/drm/i915/display/intel_dp.c

3153

if (display->platform.ironlake || display->platform.sandybridge ||

drivers/gpu/drm/i915/display/intel_dp.c

3154

display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_dp.c

3176

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3182

if (!intel_dp_port_has_audio(display, encoder->port))

drivers/gpu/drm/i915/display/intel_dp.c

3197

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

320

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3208

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3281

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3299

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/intel_dp.c

3312

drm_dbg(display->drm, "failed to calculate dsc slice count\n");

drivers/gpu/drm/i915/display/intel_dp.c

3353

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3372

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3397

if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))

drivers/gpu/drm/i915/display/intel_dp.c

3442

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3510

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3516

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/intel_dp.c

3526

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

353

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3531

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/intel_dp.c

355

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3574

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

3578

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3587

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

3596

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3605

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp.c

3630

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3677

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp.c

3682

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3708

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp.c

3713

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3728

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3742

drm_dbg_kms(display->drm, "Failed to read source OUI\n");

drivers/gpu/drm/i915/display/intel_dp.c

3751

drm_dbg_kms(display->drm, "Failed to write source OUI\n");

drivers/gpu/drm/i915/display/intel_dp.c

3765

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3768

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3780

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3817

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3861

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3871

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3886

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3894

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

3906

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3918

drm_err(display->drm, "Failed to read DPCD register 0x%x\n",

drivers/gpu/drm/i915/display/intel_dp.c

3921

drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp.c

3993

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4001

drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);

drivers/gpu/drm/i915/display/intel_dp.c

4004

drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",

drivers/gpu/drm/i915/display/intel_dp.c

4013

drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);

drivers/gpu/drm/i915/display/intel_dp.c

4050

drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);

drivers/gpu/drm/i915/display/intel_dp.c

4053

drm_dbg(display->drm, "FRL trained with : %d Gbps\n",

drivers/gpu/drm/i915/display/intel_dp.c

4093

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4108

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4114

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4117

drm_dbg(display->drm, "FRL training Completed\n");

drivers/gpu/drm/i915/display/intel_dp.c

4167

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4217

drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");

drivers/gpu/drm/i915/display/intel_dp.c

4223

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4238

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4274

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4281

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4343

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

4365

drm_err(display->drm, "Failed to read FEC DPCD register\n");

drivers/gpu/drm/i915/display/intel_dp.c

4369

drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",

drivers/gpu/drm/i915/display/intel_dp.c

4400

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4403

if (!HAS_DSC(display))

drivers/gpu/drm/i915/display/intel_dp.c

4418

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

4434

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4442

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

4460

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4469

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4478

drm_err(display->drm, "Failed to read MSO cap\n");

drivers/gpu/drm/i915/display/intel_dp.c

4485

drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);

drivers/gpu/drm/i915/display/intel_dp.c

4490

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4494

if (!HAS_MSO(display)) {

drivers/gpu/drm/i915/display/intel_dp.c

4495

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4525

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4556

intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))

drivers/gpu/drm/i915/display/intel_dp.c

4579

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4583

drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);

drivers/gpu/drm/i915/display/intel_dp.c

4607

drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp.c

4724

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4726

if (!display->params.enable_dp_mst)

drivers/gpu/drm/i915/display/intel_dp.c

4742

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4751

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4756

str_yes_no(display->params.enable_dp_mst),

drivers/gpu/drm/i915/display/intel_dp.c

4782

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4787

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4797

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4805

if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) {

drivers/gpu/drm/i915/display/intel_dp.c

4886

intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.c

4903

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

4909

drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");

drivers/gpu/drm/i915/display/intel_dp.c

4967

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

4981

len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,

drivers/gpu/drm/i915/display/intel_dp.c

4994

if (drm_WARN_ON(display->drm, len < 0))

drivers/gpu/drm/i915/display/intel_dp.c

5005

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

5006

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp.c

5011

if (HAS_AS_SDP(display))

drivers/gpu/drm/i915/display/intel_dp.c

5014

u32 val = intel_de_read(display, reg) & ~dip_enable;

drivers/gpu/drm/i915/display/intel_dp.c

5017

if (!enable && HAS_DSC(display))

drivers/gpu/drm/i915/display/intel_dp.c

5027

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_dp.c

5028

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_dp.c

508

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5149

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

516

return DISPLAY_VER(display) >= 12 ||

drivers/gpu/drm/i915/display/intel_dp.c

5164

drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");

drivers/gpu/drm/i915/display/intel_dp.c

517

(DISPLAY_VER(display) == 11 &&

drivers/gpu/drm/i915/display/intel_dp.c

5217

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

5232

drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");

drivers/gpu/drm/i915/display/intel_dp.c

5239

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

5256

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5286

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5301

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5324

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5331

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5357

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5368

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5375

drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);

drivers/gpu/drm/i915/display/intel_dp.c

5387

if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,

drivers/gpu/drm/i915/display/intel_dp.c

5397

drm_dbg_kms(display->drm, "Failed to ack ESI\n");

drivers/gpu/drm/i915/display/intel_dp.c

546

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5485

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5498

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_dp.c

550

display->platform.pantherlake_wildcatlake)

drivers/gpu/drm/i915/display/intel_dp.c

5510

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

5512

drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp.c

5517

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5526

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

553

if (DISPLAY_VERx100(display) == 1401)

drivers/gpu/drm/i915/display/intel_dp.c

5533

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp.c

5553

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5584

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

5592

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

drivers/gpu/drm/i915/display/intel_dp.c

5610

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5615

ret = intel_modeset_commit_pipes(display, pipe_mask, ctx);

drivers/gpu/drm/i915/display/intel_dp.c

5622

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5655

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5674

drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");

drivers/gpu/drm/i915/display/intel_dp.c

5679

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5691

drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,

drivers/gpu/drm/i915/display/intel_dp.c

5765

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5770

if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))

drivers/gpu/drm/i915/display/intel_dp.c

5813

drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");

drivers/gpu/drm/i915/display/intel_dp.c

5855

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

5860

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) {

drivers/gpu/drm/i915/display/intel_dp.c

5902

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5926

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5959

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5977

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

5988

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6001

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",

drivers/gpu/drm/i915/display/intel_dp.c

6038

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6040

intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&

drivers/gpu/drm/i915/display/intel_dp.c

607

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6071

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_dp.c

6079

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_dp.c

6081

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6082

!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));

drivers/gpu/drm/i915/display/intel_dp.c

6084

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_dp.c

6087

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_dp.c

612

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

615

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_dp.c

616

if (display->platform.battlemage) {

drivers/gpu/drm/i915/display/intel_dp.c

6222

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6225

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_dp.c

6228

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_dp.c

624

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_dp.c

6243

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_dp.c

6261

mode = drm_dp_downstream_mode(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

627

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_dp.c

6277

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6286

drm_dbg_kms(display->drm, "registering %s bus for %s\n",

drivers/gpu/drm/i915/display/intel_dp.c

629

else if (display->platform.alderlake_p || display->platform.alderlake_s ||

drivers/gpu/drm/i915/display/intel_dp.c

630

display->platform.dg1 || display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_dp.c

632

else if (display->platform.jasperlake || display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_dp.c

6323

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6326

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

636

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_dp.c

6376

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp.c

6381

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp.c

639

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_dp.c

6417

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp.c

642

} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||

drivers/gpu/drm/i915/display/intel_dp.c

6423

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_dp.c

643

display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_dp.c

6450

drm_WARN_ON(display->drm, transcoders != 0);

drivers/gpu/drm/i915/display/intel_dp.c

6486

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6516

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_dp.c

6532

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6538

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_dp.c

6539

if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {

drivers/gpu/drm/i915/display/intel_dp.c

6540

display->hotplug.event_bits |= BIT(hpd_pin);

drivers/gpu/drm/i915/display/intel_dp.c

6543

&display->hotplug.oob_hotplug_last_state,

drivers/gpu/drm/i915/display/intel_dp.c

6547

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_dp.c

6550

intel_hpd_schedule_detection(display);

drivers/gpu/drm/i915/display/intel_dp.c

6576

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp.c

6582

intel_display_rpm_suspended(display) ||

drivers/gpu/drm/i915/display/intel_dp.c

6590

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6598

drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",

drivers/gpu/drm/i915/display/intel_dp.c

6632

static bool _intel_dp_is_port_edp(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.c

6640

if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_dp.c

6643

if (DISPLAY_VER(display) < 9 && port == PORT_A)

drivers/gpu/drm/i915/display/intel_dp.c

6649

bool intel_dp_is_port_edp(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_dp.c

6652

intel_bios_encoder_data_lookup(display, port);

drivers/gpu/drm/i915/display/intel_dp.c

6654

return _intel_dp_is_port_edp(display, devdata, port);

drivers/gpu/drm/i915/display/intel_dp.c

6660

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6666

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_dp.c

6672

if (display->platform.haswell || display->platform.broadwell ||

drivers/gpu/drm/i915/display/intel_dp.c

6673

DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_dp.c

6683

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6689

if (!display->platform.g4x && port != PORT_A)

drivers/gpu/drm/i915/display/intel_dp.c

6693

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_dp.c

6695

else if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_dp.c

6709

if (HAS_VRR(display))

drivers/gpu/drm/i915/display/intel_dp.c

6716

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6724

display->vbt.orientation,

drivers/gpu/drm/i915/display/intel_dp.c

6732

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6735

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dp.c

6744

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6759

if (intel_get_lvds_encoder(display)) {

drivers/gpu/drm/i915/display/intel_dp.c

6760

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6761

!(HAS_PCH_IBX(display) || HAS_PCH_CPT(display)));

drivers/gpu/drm/i915/display/intel_dp.c

6762

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6768

intel_bios_init_panel_early(display, &connector->panel,

drivers/gpu/drm/i915/display/intel_dp.c

6772

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6799

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6822

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6834

if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

6837

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6844

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_dp.c

6850

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6865

intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,

drivers/gpu/drm/i915/display/intel_dp.c

6881

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_dp.c

6884

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6911

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp.c

6927

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_dp.c

6930

if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {

drivers/gpu/drm/i915/display/intel_dp.c

6936

DISPLAY_VER(display) < 30);

drivers/gpu/drm/i915/display/intel_dp.c

6941

if (drm_WARN_ON(dev, (display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_dp.c

6942

display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_dp.c

6952

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dp.c

6958

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

6967

if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_dp.c

6976

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_dp.c

6996

if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

6999

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

7011

intel_display_power_flush_work(display);

drivers/gpu/drm/i915/display/intel_dp.c

7017

void intel_dp_mst_suspend(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

7021

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_dp.c

7024

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_dp.c

7040

void intel_dp_mst_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

7044

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_dp.c

7047

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_dp.c

7070

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7075

drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",

drivers/gpu/drm/i915/display/intel_dp.c

7122

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7137

if ((assume_all_enabled && HAS_AS_SDP(display)) ||

drivers/gpu/drm/i915/display/intel_dp.c

734

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

740

if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))

drivers/gpu/drm/i915/display/intel_dp.c

745

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >

drivers/gpu/drm/i915/display/intel_dp.c

769

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

772

if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))

drivers/gpu/drm/i915/display/intel_dp.c

801

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

803

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp.c

813

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {

drivers/gpu/drm/i915/display/intel_dp.c

861

small_joiner_ram_size_bits(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

863

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_dp.c

865

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_dp.c

899

static int bigjoiner_interface_bits(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp.c

901

return DISPLAY_VER(display) >= 14 ? 36 : 24;

drivers/gpu/drm/i915/display/intel_dp.c

904

static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,

drivers/gpu/drm/i915/display/intel_dp.c

912

max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /

drivers/gpu/drm/i915/display/intel_dp.c

921

static u32 small_joiner_ram_max_bpp(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.c

928

max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;

drivers/gpu/drm/i915/display/intel_dp.c

947

u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.c

951

u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);

drivers/gpu/drm/i915/display/intel_dp.c

954

max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,

drivers/gpu/drm/i915/display/intel_dp.c

966

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp.h

100

void intel_dp_mst_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp.h

117

bool intel_dp_source_supports_tps3(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp.h

118

bool intel_dp_source_supports_tps4(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp.h

129

bool intel_dp_joiner_needs_dsc(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp.h

214

int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp.h

92

bool intel_dp_is_port_edp(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_dp.h

99

void intel_dp_mst_suspend(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp_aux.c

108

freq = display->cdclk.hw.cdclk;

drivers/gpu/drm/i915/display/intel_dp_aux.c

110

freq = DISPLAY_RUNTIME_INFO(display)->rawclk_freq;

drivers/gpu/drm/i915/display/intel_dp_aux.c

116

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

119

if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(display)) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

182

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

186

if (display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_dp_aux.c

206

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

22

static const char *aux_ch_name(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp_aux.c

232

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dp_aux.c

244

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

25

if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD)

drivers/gpu/drm/i915/display/intel_dp_aux.c

27

else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1)

drivers/gpu/drm/i915/display/intel_dp_aux.c

275

aux_wakeref = intel_display_power_get(display, aux_domain);

drivers/gpu/drm/i915/display/intel_dp_aux.c

288

display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dp_aux.c

315

status = intel_de_read_notrace(display, ch_ctl);

drivers/gpu/drm/i915/display/intel_dp_aux.c

324

const u32 status = intel_de_read(display, ch_ctl);

drivers/gpu/drm/i915/display/intel_dp_aux.c

327

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_dp_aux.c

338

if (drm_WARN_ON(display->drm, send_bytes > 20 || recv_size > 20)) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

354

intel_de_write(display, ch_data[i >> 2],

drivers/gpu/drm/i915/display/intel_dp_aux.c

359

intel_de_write(display, ch_ctl, send_ctl);

drivers/gpu/drm/i915/display/intel_dp_aux.c

364

intel_de_write(display, ch_ctl,

drivers/gpu/drm/i915/display/intel_dp_aux.c

388

drm_err(display->drm, "%s: not done (status 0x%08x)\n",

drivers/gpu/drm/i915/display/intel_dp_aux.c

400

drm_err(display->drm, "%s: receive error (status 0x%08x)\n",

drivers/gpu/drm/i915/display/intel_dp_aux.c

411

drm_dbg_kms(display->drm, "%s: timeout (status 0x%08x)\n",

drivers/gpu/drm/i915/display/intel_dp_aux.c

426

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux.c

437

intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]),

drivers/gpu/drm/i915/display/intel_dp_aux.c

450

intel_display_power_put_async(display, aux_domain, aux_wakeref);

drivers/gpu/drm/i915/display/intel_dp_aux.c

488

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

503

if (drm_WARN_ON(display->drm, txsize > 20))

drivers/gpu/drm/i915/display/intel_dp_aux.c

506

drm_WARN_ON(display->drm, !msg->buffer != !msg->size);

drivers/gpu/drm/i915/display/intel_dp_aux.c

531

if (drm_WARN_ON(display->drm, rxsize > 20))

drivers/gpu/drm/i915/display/intel_dp_aux.c

60

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

66

#define C (((status = intel_de_read_notrace(display, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)

drivers/gpu/drm/i915/display/intel_dp_aux.c

67

done = wait_event_timeout(display->gmbus.wait_queue, C,

drivers/gpu/drm/i915/display/intel_dp_aux.c

71

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux.c

741

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

752

return XELPDP_DP_AUX_CH_CTL(display, aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

755

return XELPDP_DP_AUX_CH_CTL(display, AUX_CH_A);

drivers/gpu/drm/i915/display/intel_dp_aux.c

761

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

772

return XELPDP_DP_AUX_CH_DATA(display, aux_ch, index);

drivers/gpu/drm/i915/display/intel_dp_aux.c

775

return XELPDP_DP_AUX_CH_DATA(display, AUX_CH_A, index);

drivers/gpu/drm/i915/display/intel_dp_aux.c

789

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

795

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

798

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

801

} else if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

804

} else if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

807

} else if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

81

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

815

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_dp_aux.c

817

else if (display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_dp_aux.c

819

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_dp_aux.c

824

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_dp_aux.c

829

intel_dp->aux.drm_dev = display->drm;

drivers/gpu/drm/i915/display/intel_dp_aux.c

834

aux_ch_name(display, buf, sizeof(buf), aux_ch),

drivers/gpu/drm/i915/display/intel_dp_aux.c

845

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_aux.c

848

if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E)

drivers/gpu/drm/i915/display/intel_dp_aux.c

858

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_aux.c

861

for_each_intel_encoder(display->drm, other) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

877

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_aux.c

898

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux.c

90

return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 2000);

drivers/gpu/drm/i915/display/intel_dp_aux.c

901

aux_ch_name(display, buf, sizeof(buf), aux_ch),

drivers/gpu/drm/i915/display/intel_dp_aux.c

906

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux.c

909

aux_ch_name(display, buf, sizeof(buf), aux_ch), source);

drivers/gpu/drm/i915/display/intel_dp_aux.c

914

void intel_dp_aux_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp_aux.c

916

wake_up_all(&display->gmbus.wait_queue);

drivers/gpu/drm/i915/display/intel_dp_aux.c

95

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

21

void intel_dp_aux_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

114

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

127

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

147

if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

150

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

176

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

183

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

202

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

248

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

265

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

275

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

286

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

306

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

318

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

342

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

374

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

389

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

397

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

403

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

411

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

428

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

520

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

537

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

541

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

550

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

567

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

593

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

603

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

609

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

617

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

643

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

652

switch (display->params.enable_dpcd_backlight) {

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

102

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

112

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

123

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

132

struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

140

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

152

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

156

ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

168

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

174

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

186

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

193

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

205

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

217

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

230

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

240

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

260

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

267

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

279

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

283

ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

346

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

355

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

401

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

434

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

518

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

572

drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

585

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

61

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

69

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

701

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

714

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

717

ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

750

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

759

drm_err(display->drm, "%s HDCP stream select failed (%d)\n",

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

768

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

785

if (intel_de_wait_ms(display, HDCP_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

788

drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

800

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

811

if (DISPLAY_VER(display) < 30) {

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

812

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

813

HDCP2_AUTH_STREAM(display, cpu_transcoder, port));

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

815

drm_WARN_ON(display->drm, enable &&

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

824

if (intel_de_wait_ms(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

828

drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

833

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

834

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

835

HDCP2_STREAM_STATUS(display, cpu_transcoder, port));

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

837

drm_WARN_ON(display->drm, enable &&

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

85

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

892

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

897

if (!is_hdcp_supported(display, port))

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

96

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1138

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1157

if (!display->hotplug.ignore_long_hpd &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1644

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1692

if (display->hotplug.ignore_long_hpd) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1734

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1741

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1749

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1805

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1814

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1821

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1832

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1839

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1847

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1907

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1916

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1923

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1934

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1938

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1944

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1953

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1957

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1963

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1972

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1976

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1982

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1990

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1997

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2003

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2014

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2018

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2024

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2032

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2036

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2042

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2055

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2059

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2065

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

224

if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

255

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

263

(DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

326

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

329

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

339

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

351

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

361

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

373

drm_WARN_ON_ONCE(display->drm,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

383

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

386

DISPLAY_VER(display) >= 10 || display->platform.broxton;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

780

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

793

source_tps4 = intel_dp_source_supports_tps4(display);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

811

source_tps3 = intel_dp_source_supports_tps3(display);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1002

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1022

drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

1025

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1038

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1039

TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_dp_mst.c

1052

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1058

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1083

if (DISPLAY_VER(display) < 12 || !last_mst_stream)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1159

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1177

drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && first_mst_stream &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

120

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1206

if (DISPLAY_VER(display) < 12 || !first_mst_stream)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1209

if (DISPLAY_VER(display) >= 13 && !first_mst_stream)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1218

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

122

drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

1222

if (!display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1225

if (!IS_DISPLAY_STEP(display, STEP_D0, STEP_FOREVER))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1233

if (IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1246

intel_de_rmw(display, CHICKEN_MISC_3, clear, set);

drivers/gpu/drm/i915/display/intel_dp_mst.c

125

if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1254

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1265

drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1272

intel_de_write(display, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_dp_mst.c

1274

intel_de_write(display, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_dp_mst.c

1286

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1301

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1302

intel_de_rmw(display, CHICKEN_TRANS(display, trans),

drivers/gpu/drm/i915/display/intel_dp_mst.c

1308

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config, i) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

133

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1347

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

135

drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

1355

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1418

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1423

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1437

*status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_dp_mst.c

145

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

149

if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1505

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1515

*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1537

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1540

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1546

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1591

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1595

display->drm->mode_config.path_property, 0);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1597

display->drm->mode_config.tile_property, 0);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1638

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1676

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1689

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1705

ret = drm_connector_dynamic_init(display->drm, &connector->base, &mst_connector_funcs,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1717

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

1732

drm_dbg_kms(display->drm, "[%s:%d] HDCP MST init failed, skipping.\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

1763

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1777

drm_encoder_init(display->drm, &encoder->base, &mst_stream_encoder_funcs,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1817

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1821

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1829

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1834

if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1837

if (DISPLAY_VER(display) < 12 && port == PORT_A)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1840

if (DISPLAY_VER(display) < 11 && port == PORT_E)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1847

ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst.mgr, display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1849

INTEL_NUM_PIPES(display), conn_base_id);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2081

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2095

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

252

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

265

drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) ||

drivers/gpu/drm/i915/display/intel_dp_mst.c

271

drm_WARN_ON(display->drm, min_bpp_x16 != max_bpp_x16);

drivers/gpu/drm/i915/display/intel_dp_mst.c

305

drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (" FXP_Q4_FMT " -> " FXP_Q4_FMT ")\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

310

drm_dbg_kms(display->drm, "Looking for slots in range min bpp " FXP_Q4_FMT " max bpp " FXP_Q4_FMT "\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

316

drm_dbg_kms(display->drm, "Can't get valid DSC slice count\n");

drivers/gpu/drm/i915/display/intel_dp_mst.c

322

drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16);

drivers/gpu/drm/i915/display/intel_dp_mst.c

328

drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16));

drivers/gpu/drm/i915/display/intel_dp_mst.c

332

drm_WARN_ON(display->drm, !is_mst);

drivers/gpu/drm/i915/display/intel_dp_mst.c

393

drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_dp_mst.c

418

drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_dp_mst.c

425

drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

435

drm_dbg_kms(display->drm, "Got %d slots for pipe bpp " FXP_Q4_FMT " dsc %d\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

464

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

469

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

523

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

532

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

539

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

552

drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate);

drivers/gpu/drm/i915/display/intel_dp_mst.c

562

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

602

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

632

joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);

drivers/gpu/drm/i915/display/intel_dp_mst.c

650

drm_dbg_kms(display->drm, "DSC required but not available\n");

drivers/gpu/drm/i915/display/intel_dp_mst.c

656

drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",

drivers/gpu/drm/i915/display/intel_dp_mst.c

670

drm_WARN(display->drm, intel_dp->force_dsc_bpc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

676

drm_dbg_kms(display->drm, "Trying to find VCPI slots in DSC mode\n");

drivers/gpu/drm/i915/display/intel_dp_mst.c

694

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_dp_mst.c

722

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

728

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_dp_mst.c

782

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

790

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mst_pipe_mask) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

795

if (drm_WARN_ON(display->drm, !crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

905

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

913

drm_connector_list_iter_begin(display->drm, &connector_list_iter);

drivers/gpu/drm/i915/display/intel_dp_test.c

115

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

125

drm_dbg_kms(display->drm, "Test pattern read failed\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

134

drm_dbg_kms(display->drm, "H Width read failed\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

141

drm_dbg_kms(display->drm, "V Height read failed\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

148

drm_dbg_kms(display->drm, "TEST MISC read failed\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

177

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

193

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

207

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

223

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

233

drm_dbg_kms(display->drm, "Disable Phy Test Pattern\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

234

intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);

drivers/gpu/drm/i915/display/intel_dp_test.c

235

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_dp_test.c

236

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_test.c

241

drm_dbg_kms(display->drm, "Set D10.2 Phy Test Pattern\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

242

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

drivers/gpu/drm/i915/display/intel_dp_test.c

246

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

248

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

drivers/gpu/drm/i915/display/intel_dp_test.c

253

drm_dbg_kms(display->drm, "Set PRBS7 Phy Test Pattern\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

254

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

drivers/gpu/drm/i915/display/intel_dp_test.c

263

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

266

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val);

drivers/gpu/drm/i915/display/intel_dp_test.c

268

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val);

drivers/gpu/drm/i915/display/intel_dp_test.c

270

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val);

drivers/gpu/drm/i915/display/intel_dp_test.c

271

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

drivers/gpu/drm/i915/display/intel_dp_test.c

281

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

284

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

drivers/gpu/drm/i915/display/intel_dp_test.c

289

if (DISPLAY_VER(display) < 10) {

drivers/gpu/drm/i915/display/intel_dp_test.c

290

drm_warn(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

294

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

296

intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);

drivers/gpu/drm/i915/display/intel_dp_test.c

297

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_test.c

302

drm_warn(display->drm, "Invalid Phy Test Pattern\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

309

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

316

drm_dbg_kms(display->drm, "failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

337

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

342

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

35

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

355

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

362

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

369

drm_dbg_kms(display->drm, "LINK_TRAINING test requested\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

373

drm_dbg_kms(display->drm, "TEST_PATTERN test requested\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

377

drm_dbg_kms(display->drm, "EDID test requested\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

381

drm_dbg_kms(display->drm, "PHY_PATTERN test requested\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

385

drm_dbg_kms(display->drm, "Invalid test request '%02x'\n",

drivers/gpu/drm/i915/display/intel_dp_test.c

396

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

406

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

413

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp_test.c

433

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

45

drm_dbg_kms(display->drm, "Setting pipe_bpp to %d\n", bpp);

drivers/gpu/drm/i915/display/intel_dp_test.c

453

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

459

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

drivers/gpu/drm/i915/display/intel_dp_test.c

471

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] PHY test\n",

drivers/gpu/drm/i915/display/intel_dp_test.c

474

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

drivers/gpu/drm/i915/display/intel_dp_test.c

479

if (DISPLAY_VER(display) >= 12 &&

drivers/gpu/drm/i915/display/intel_dp_test.c

525

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

530

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

533

drm_kms_helper_hotplug_event(display->drm);

drivers/gpu/drm/i915/display/intel_dp_test.c

536

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_test.c

555

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_dp_test.c

570

drm_dbg_kms(display->drm, "Copied %d bytes from user\n", (unsigned int)len);

drivers/gpu/drm/i915/display/intel_dp_test.c

572

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp_test.c

589

drm_dbg_kms(display->drm, "Got %d for test active\n", val);

drivers/gpu/drm/i915/display/intel_dp_test.c

610

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_dp_test.c

615

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp_test.c

660

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_dp_test.c

665

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp_test.c

714

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_dp_test.c

719

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_dp_test.c

753

void intel_dp_test_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp_test.c

760

display->drm->debugfs_root,

drivers/gpu/drm/i915/display/intel_dp_test.c

761

display,

drivers/gpu/drm/i915/display/intel_dp_test.c

77

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

89

drm_dbg_kms(display->drm, "Lane count read failed\n");

drivers/gpu/drm/i915/display/intel_dp_test.c

97

drm_dbg_kms(display->drm, "Link Rate read failed\n");

drivers/gpu/drm/i915/display/intel_dp_test.h

21

void intel_dp_test_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

106

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

124

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

130

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

137

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

148

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

175

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

180

tunnel = drm_dp_tunnel_detect(display->dp_tunnel_mgr,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

192

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

269

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

276

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

299

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

311

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

352

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

374

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

379

drm_WARN_ON(display->drm, old_tunnel != tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

398

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

426

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

445

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

451

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

462

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

471

drm_WARN_ON(display->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1));

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

509

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

517

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

588

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

597

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

72

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

721

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

729

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

786

int intel_dp_tunnel_mgr_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

793

drm_connector_list_iter_begin(display->drm, &connector_list_iter);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

802

tunnel_mgr = drm_dp_tunnel_mgr_create(display->drm, dp_connectors);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

806

display->dp_tunnel_mgr = tunnel_mgr;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

817

void intel_dp_tunnel_mgr_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

819

drm_dp_tunnel_mgr_destroy(display->dp_tunnel_mgr);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

820

display->dp_tunnel_mgr = NULL;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

84

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

127

intel_dp_tunnel_mgr_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

132

static inline void intel_dp_tunnel_mgr_cleanup(struct intel_display *display) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

56

int intel_dp_tunnel_mgr_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

57

void intel_dp_tunnel_mgr_cleanup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1001

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1004

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1012

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1023

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1028

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1032

chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1040

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1045

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1049

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1051

vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1053

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1055

vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1058

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1077

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1082

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1084

vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1085

vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1086

vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1088

vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1091

vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1093

vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1094

vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1095

vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1097

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1103

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1109

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1111

vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1114

vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1121

vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1122

vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1123

vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1125

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1131

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1140

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1147

vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1150

vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1151

vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1153

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1159

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1164

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1165

vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1166

vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1167

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1173

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1184

dpll_reg = DPLL(display, 0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1188

dpll_reg = DPLL(display, 0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1197

if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask, 1000, &val))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1198

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

225

bxt_get_phy_list(struct intel_display *display, int *count)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

227

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

237

bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

241

bxt_get_phy_list(display, &count);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

246

void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

252

phys = bxt_get_phy_list(display, &count);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

271

drm_WARN(display->drm, 1, "PHY not found for PORT %c",

drivers/gpu/drm/i915/display/intel_dpio_phy.c

281

static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

288

old = intel_de_read(display, reg_single);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

290

intel_de_write(display, reg_group, val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

298

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

305

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

308

bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

314

bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

321

intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

331

intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

336

val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

338

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

345

intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

350

bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

355

bool bxt_dpio_phy_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

360

phy_info = bxt_get_phy_info(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

362

if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

365

if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &

drivers/gpu/drm/i915/display/intel_dpio_phy.c

367

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

373

if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

374

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

383

static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

385

u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

390

static void bxt_phy_wait_grc_done(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

393

if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

394

drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

397

static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

402

phy_info = bxt_get_phy_info(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

404

if (bxt_dpio_phy_is_enabled(display, phy)) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

407

display->state.bxt_phy_grc = bxt_get_grc(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

409

if (bxt_dpio_phy_verify_state(display, phy)) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

410

drm_dbg(display->drm, "DDI PHY %d already enabled, "

drivers/gpu/drm/i915/display/intel_dpio_phy.c

415

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

420

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

430

if (intel_de_wait_ms(display, BXT_PORT_CL1CM_DW0(phy),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

432

drm_err(display->drm, "timeout during PHY%d power on\n",

drivers/gpu/drm/i915/display/intel_dpio_phy.c

436

intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

439

intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

443

intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

447

intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

453

bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

460

val = bxt_get_grc(display, phy_info->rcomp_phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

461

display->state.bxt_phy_grc = val;

drivers/gpu/drm/i915/display/intel_dpio_phy.c

466

intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

467

intel_de_rmw(display, BXT_PORT_REF_DW8(phy),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

474

intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

477

void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

481

phy_info = bxt_get_phy_info(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

483

intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

485

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

488

void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

490

const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

494

lockdep_assert_held(&display->power.domains.lock);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

498

was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

505

_bxt_dpio_phy_init(display, rcomp_phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

507

_bxt_dpio_phy_init(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

510

bxt_dpio_phy_uninit(display, rcomp_phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

514

__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

522

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

530

drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "

drivers/gpu/drm/i915/display/intel_dpio_phy.c

540

bool bxt_dpio_phy_verify_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

547

phy_info = bxt_get_phy_info(display, phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

550

__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \

drivers/gpu/drm/i915/display/intel_dpio_phy.c

553

if (!bxt_dpio_phy_is_enabled(display, phy))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

577

u32 grc_code = display->state.bxt_phy_grc;

drivers/gpu/drm/i915/display/intel_dpio_phy.c

616

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

622

bxt_port_to_phy_channel(display, port, &phy, &ch);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

629

intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),

drivers/gpu/drm/i915/display/intel_dpio_phy.c

638

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

645

bxt_port_to_phy_channel(display, port, &phy, &ch);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

649

u32 val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

720

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

727

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

730

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

734

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

737

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

741

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

744

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

747

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

750

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

753

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

758

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

761

vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

766

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

779

vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

789

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

794

vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

798

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

800

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

803

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

805

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

808

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

815

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

821

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

826

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

829

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

834

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

837

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

843

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

846

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

852

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

860

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

862

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

864

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

870

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

886

!chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

890

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

897

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

903

vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

905

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

911

vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

915

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

921

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

924

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

930

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

938

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

943

vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

945

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

951

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

959

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

962

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

964

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

967

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

969

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

979

vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

994

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

996

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

999

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));

drivers/gpu/drm/i915/display/intel_dpio_phy.h

30

void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

34

void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

35

void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

36

bool bxt_dpio_phy_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

38

bool bxt_dpio_phy_verify_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

78

static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

86

static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.h

89

static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)

drivers/gpu/drm/i915/display/intel_dpio_phy.h

92

static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

97

static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll.c

1007

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1017

if (display->platform.i945g || display->platform.i945gm ||

drivers/gpu/drm/i915/display/intel_dpll.c

1018

display->platform.g33 || display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_dpll.c

1031

if (display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_dpll.c

1034

} else if (display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_dpll.c

1058

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_dpll.c

1064

intel_panel_use_ssc(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1076

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1079

if (display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_dpll.c

1089

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_dpll.c

1097

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1127

if (display->platform.i830 ||

drivers/gpu/drm/i915/display/intel_dpll.c

1132

intel_panel_use_ssc(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1155

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1162

if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/intel_dpll.c

1184

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1190

if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/intel_dpll.c

1239

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1242

((intel_panel_use_ssc(display) && display->vbt.lvds_ssc_freq == 100000) ||

drivers/gpu/drm/i915/display/intel_dpll.c

1243

(HAS_PCH_IBX(display) && intel_is_dual_link_lvds(display))))

drivers/gpu/drm/i915/display/intel_dpll.c

1272

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1306

if (INTEL_NUM_PIPES(display) == 3 &&

drivers/gpu/drm/i915/display/intel_dpll.c

1332

intel_panel_use_ssc(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1356

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1368

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1369

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

1371

display->vbt.lvds_ssc_freq);

drivers/gpu/drm/i915/display/intel_dpll.c

1372

refclk = display->vbt.lvds_ssc_freq;

drivers/gpu/drm/i915/display/intel_dpll.c

1375

if (intel_is_dual_link_lvds(display)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1532

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1539

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1540

refclk = display->vbt.lvds_ssc_freq;

drivers/gpu/drm/i915/display/intel_dpll.c

1541

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

1546

if (intel_is_dual_link_lvds(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1581

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1588

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1589

refclk = display->vbt.lvds_ssc_freq;

drivers/gpu/drm/i915/display/intel_dpll.c

1590

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

1619

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1626

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1627

refclk = display->vbt.lvds_ssc_freq;

drivers/gpu/drm/i915/display/intel_dpll.c

1628

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

1659

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1666

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1667

refclk = display->vbt.lvds_ssc_freq;

drivers/gpu/drm/i915/display/intel_dpll.c

1668

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

1746

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1751

drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));

drivers/gpu/drm/i915/display/intel_dpll.c

1759

ret = display->funcs.dpll->crtc_compute_clock(state, crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1761

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",

drivers/gpu/drm/i915/display/intel_dpll.c

1772

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll.c

1777

drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));

drivers/gpu/drm/i915/display/intel_dpll.c

1778

drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1783

if (!display->funcs.dpll->crtc_get_dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

1786

ret = display->funcs.dpll->crtc_get_dpll(state, crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1788

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",

drivers/gpu/drm/i915/display/intel_dpll.c

1797

intel_dpll_init_clock_hook(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll.c

1799

if (HAS_LT_PHY(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1800

display->funcs.dpll = &xe3plpd_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1801

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dpll.c

1802

display->funcs.dpll = &mtl_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1803

else if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_dpll.c

1804

display->funcs.dpll = &dg2_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1805

else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1806

display->funcs.dpll = &hsw_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1807

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1808

display->funcs.dpll = &ilk_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1809

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dpll.c

1810

display->funcs.dpll = &chv_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1811

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_dpll.c

1812

display->funcs.dpll = &vlv_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1813

else if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_dpll.c

1814

display->funcs.dpll = &g4x_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1815

else if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_dpll.c

1816

display->funcs.dpll = &pnv_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1817

else if (DISPLAY_VER(display) != 2)

drivers/gpu/drm/i915/display/intel_dpll.c

1818

display->funcs.dpll = &i9xx_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1820

display->funcs.dpll = &i8xx_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1823

static bool i9xx_has_pps(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll.c

1825

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_dpll.c

1828

return display->platform.pineview || display->platform.mobile;

drivers/gpu/drm/i915/display/intel_dpll.c

1833

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1839

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

1842

if (i9xx_has_pps(display))

drivers/gpu/drm/i915/display/intel_dpll.c

1843

assert_pps_unlocked(display, pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

1845

intel_de_write(display, FP0(pipe), hw_state->fp0);

drivers/gpu/drm/i915/display/intel_dpll.c

1846

intel_de_write(display, FP1(pipe), hw_state->fp1);

drivers/gpu/drm/i915/display/intel_dpll.c

1853

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

1855

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1858

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1861

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_dpll.c

1862

intel_de_write(display, DPLL_MD(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

1870

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1875

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1876

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

1881

static void vlv_pllb_recal_opamp(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll.c

1890

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

1893

vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1895

tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);

drivers/gpu/drm/i915/display/intel_dpll.c

1898

vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1900

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

1902

vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1904

tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);

drivers/gpu/drm/i915/display/intel_dpll.c

1907

vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1912

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1920

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

1926

vlv_pllb_recal_opamp(display, phy, ch);

drivers/gpu/drm/i915/display/intel_dpll.c

1929

vlv_dpio_write(display->drm, phy, VLV_PCS_DW17_BCAST, 0x0100000f);

drivers/gpu/drm/i915/display/intel_dpll.c

1932

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW16(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

1934

vlv_dpio_write(display->drm, phy, VLV_PLL_DW16(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1937

vlv_dpio_write(display->drm, phy, VLV_CMN_DW0, 0x610);

drivers/gpu/drm/i915/display/intel_dpll.c

1953

vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1956

vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

1962

vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x009f0003);

drivers/gpu/drm/i915/display/intel_dpll.c

1964

vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x00d0000f);

drivers/gpu/drm/i915/display/intel_dpll.c

1969

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000);

drivers/gpu/drm/i915/display/intel_dpll.c

1971

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000);

drivers/gpu/drm/i915/display/intel_dpll.c

1975

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000);

drivers/gpu/drm/i915/display/intel_dpll.c

1977

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000);

drivers/gpu/drm/i915/display/intel_dpll.c

1980

coreclk = vlv_dpio_read(display->drm, phy, VLV_PLL_DW7(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

1984

vlv_dpio_write(display->drm, phy, VLV_PLL_DW7(ch), coreclk);

drivers/gpu/drm/i915/display/intel_dpll.c

1986

vlv_dpio_write(display->drm, phy, VLV_PLL_DW19(ch), 0x87871000);

drivers/gpu/drm/i915/display/intel_dpll.c

1988

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

1993

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1998

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1999

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2002

if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

drivers/gpu/drm/i915/display/intel_dpll.c

2003

drm_err(display->drm, "DPLL %d failed to lock\n", pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2008

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2013

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

2016

assert_pps_unlocked(display, pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2019

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2027

intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md);

drivers/gpu/drm/i915/display/intel_dpll.c

2028

intel_de_posting_read(display, DPLL_MD(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2033

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2043

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

2046

vlv_dpio_write(display->drm, phy, CHV_CMN_DW13(ch),

drivers/gpu/drm/i915/display/intel_dpll.c

2053

vlv_dpio_write(display->drm, phy, CHV_PLL_DW0(ch),

drivers/gpu/drm/i915/display/intel_dpll.c

2057

vlv_dpio_write(display->drm, phy, CHV_PLL_DW1(ch),

drivers/gpu/drm/i915/display/intel_dpll.c

2062

vlv_dpio_write(display->drm, phy, CHV_PLL_DW2(ch),

drivers/gpu/drm/i915/display/intel_dpll.c

2066

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

2071

vlv_dpio_write(display->drm, phy, CHV_PLL_DW3(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

2074

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW9(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

2080

vlv_dpio_write(display->drm, phy, CHV_PLL_DW9(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

2105

vlv_dpio_write(display->drm, phy, CHV_PLL_DW6(ch), loopfilter);

drivers/gpu/drm/i915/display/intel_dpll.c

2107

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW8(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

2110

vlv_dpio_write(display->drm, phy, CHV_PLL_DW8(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

2113

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch),

drivers/gpu/drm/i915/display/intel_dpll.c

2114

vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)) |

drivers/gpu/drm/i915/display/intel_dpll.c

2117

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

2122

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2130

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

2133

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

2135

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

2137

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

2145

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

2148

if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

drivers/gpu/drm/i915/display/intel_dpll.c

2149

drm_err(display->drm, "PLL %d failed to lock\n", pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2154

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2159

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

2162

assert_pps_unlocked(display, pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2165

intel_de_write(display, DPLL(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2180

intel_de_write(display, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2181

intel_de_write(display, DPLL_MD(display, PIPE_B),

drivers/gpu/drm/i915/display/intel_dpll.c

2183

intel_de_write(display, CBR4_VLV, 0);

drivers/gpu/drm/i915/display/intel_dpll.c

2184

display->state.chv_dpll_md[pipe] = hw_state->dpll_md;

drivers/gpu/drm/i915/display/intel_dpll.c

2190

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

2191

(intel_de_read(display, DPLL(display, PIPE_B)) &

drivers/gpu/drm/i915/display/intel_dpll.c

2194

intel_de_write(display, DPLL_MD(display, pipe),

drivers/gpu/drm/i915/display/intel_dpll.c

2196

intel_de_posting_read(display, DPLL_MD(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2210

int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_dpll.c

2213

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2225

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_dpll.c

2238

void vlv_disable_pll(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dpll.c

2243

assert_transcoder_disabled(display, (enum transcoder)pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2250

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2251

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2254

void chv_disable_pll(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dpll.c

2261

assert_transcoder_disabled(display, (enum transcoder)pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2268

intel_de_write(display, DPLL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2269

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2271

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

2274

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

2276

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), val);

drivers/gpu/drm/i915/display/intel_dpll.c

2278

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

2283

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2288

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_dpll.c

2292

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

2294

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_dpll.c

2295

intel_de_posting_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

2307

void vlv_force_pll_off(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dpll.c

2309

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dpll.c

2310

chv_disable_pll(display, pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2312

vlv_disable_pll(display, pipe);

drivers/gpu/drm/i915/display/intel_dpll.c

2316

static void assert_pll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll.c

2321

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_dpll.c

2322

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_dpll.c

2327

void assert_pll_enabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dpll.c

2329

assert_pll(display, pipe, true);

drivers/gpu/drm/i915/display/intel_dpll.c

2332

void assert_pll_disabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_dpll.c

2334

assert_pll(display, pipe, false);

drivers/gpu/drm/i915/display/intel_dpll.c

378

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

382

return display->vbt.lvds_ssc_freq;

drivers/gpu/drm/i915/display/intel_dpll.c

383

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_dpll.c

385

else if (DISPLAY_VER(display) != 2)

drivers/gpu/drm/i915/display/intel_dpll.c

394

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

397

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_dpll.c

401

if (display->platform.cherryview && crtc->pipe != PIPE_A)

drivers/gpu/drm/i915/display/intel_dpll.c

402

tmp = display->state.chv_dpll_md[crtc->pipe];

drivers/gpu/drm/i915/display/intel_dpll.c

404

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll.c

405

DPLL_MD(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

410

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

412

if (!display->platform.valleyview && !display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_dpll.c

413

hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

414

hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

426

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

441

if (display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_dpll.c

449

if (DISPLAY_VER(display) != 2) {

drivers/gpu/drm/i915/display/intel_dpll.c

450

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_dpll.c

467

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll.c

473

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_dpll.c

480

if (display->platform.i85x &&

drivers/gpu/drm/i915/display/intel_dpll.c

481

intel_lvds_port_enabled(display, LVDS, &lvds_pipe) &&

drivers/gpu/drm/i915/display/intel_dpll.c

483

u32 lvds = intel_de_read(display, LVDS);

drivers/gpu/drm/i915/display/intel_dpll.c

518

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

531

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

532

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW3(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

533

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

546

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

559

vlv_dpio_get(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

560

cmn_dw13 = vlv_dpio_read(display->drm, phy, CHV_CMN_DW13(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

561

pll_dw0 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW0(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

562

pll_dw1 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW1(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

563

pll_dw2 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW2(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

564

pll_dw3 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));

drivers/gpu/drm/i915/display/intel_dpll.c

565

vlv_dpio_put(display->drm);

drivers/gpu/drm/i915/display/intel_dpll.c

582

static bool intel_pll_is_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll.c

595

if (!display->platform.pineview &&

drivers/gpu/drm/i915/display/intel_dpll.c

596

!display->platform.valleyview && !display->platform.cherryview &&

drivers/gpu/drm/i915/display/intel_dpll.c

597

!display->platform.broxton && !display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_dpll.c

601

if (!display->platform.valleyview && !display->platform.cherryview &&

drivers/gpu/drm/i915/display/intel_dpll.c

602

!display->platform.broxton && !display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_dpll.c

625

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

633

if (intel_is_dual_link_lvds(display))

drivers/gpu/drm/i915/display/intel_dpll.c

661

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

682

if (!intel_pll_is_valid(display,

drivers/gpu/drm/i915/display/intel_dpll.c

719

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

738

if (!intel_pll_is_valid(display,

drivers/gpu/drm/i915/display/intel_dpll.c

775

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

799

if (!intel_pll_is_valid(display,

drivers/gpu/drm/i915/display/intel_dpll.c

822

static bool vlv_PLL_is_optimal(struct intel_display *display, int target_freq,

drivers/gpu/drm/i915/display/intel_dpll.c

832

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_dpll.c

838

if (drm_WARN_ON_ONCE(display->drm, !target_freq))

drivers/gpu/drm/i915/display/intel_dpll.c

869

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

893

if (!intel_pll_is_valid(display,

drivers/gpu/drm/i915/display/intel_dpll.c

898

if (!vlv_PLL_is_optimal(display, target,

drivers/gpu/drm/i915/display/intel_dpll.c

926

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

961

if (!intel_pll_is_valid(display, limit, &clock))

drivers/gpu/drm/i915/display/intel_dpll.c

964

if (!vlv_PLL_is_optimal(display, target, &clock, best_clock,

drivers/gpu/drm/i915/display/intel_dpll.h

19

void intel_dpll_init_clock_hook(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpll.h

31

int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_dpll.h

33

void vlv_force_pll_off(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dpll.h

36

void chv_disable_pll(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dpll.h

38

void vlv_disable_pll(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dpll.h

49

void assert_pll_enabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dpll.h

50

void assert_pll_disabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1014

static int hsw_ddi_wrpll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1026

if (display->platform.haswell && !display->platform.haswell_ult) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1027

refclk = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1037

refclk = display->dpll.ref_clks.ssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1059

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1072

crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1094

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1103

drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1112

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1132

pll = intel_get_dpll_by_id(display, pll_id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1140

static int hsw_ddi_lcpll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1157

drm_WARN(display->drm, 1, "bad port clock sel\n");

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

116

void (*update_ref_clks)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1192

static int hsw_ddi_spll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1210

drm_WARN(display->drm, 1, "bad spll freq\n");

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

124

intel_atomic_duplicate_dpll_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1260

static void hsw_update_dpll_ref_clks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1262

display->dpll.ref_clks.ssc = 135000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1264

if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1265

display->dpll.ref_clks.nssc = 24000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1267

display->dpll.ref_clks.nssc = 135000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1303

static void hsw_ddi_lcpll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1309

static void hsw_ddi_lcpll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

131

for_each_dpll(display, pll, i)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1314

static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1382

static void skl_ddi_pll_write_ctrl1(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1388

intel_de_rmw(display, DPLL_CTRL1,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

139

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1393

intel_de_posting_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1396

static void skl_ddi_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1404

skl_ddi_pll_write_ctrl1(display, pll, hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1406

intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1407

intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1408

intel_de_posting_read(display, regs[id].cfgcr1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1409

intel_de_posting_read(display, regs[id].cfgcr2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1412

intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1414

if (intel_de_wait_for_set_ms(display, DPLL_STATUS, DPLL_LOCK(id), 5))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1415

drm_err(display->drm, "DPLL %d not locked\n", id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1418

static void skl_ddi_dpll0_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1424

skl_ddi_pll_write_ctrl1(display, pll, hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1427

static void skl_ddi_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1434

intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1435

intel_de_posting_read(display, regs[id].ctl);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1438

static void skl_ddi_dpll0_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1443

static bool skl_ddi_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1454

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

146

intel_atomic_duplicate_dpll_state(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1461

val = intel_de_read(display, regs[id].ctl);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1465

val = intel_de_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1470

hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1471

hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1476

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1481

static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1492

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1500

val = intel_de_read(display, regs[id].ctl);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1501

if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE)))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1504

val = intel_de_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1510

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

162

intel_get_dpll_by_id(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

168

for_each_dpll(display, pll, i) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1754

static int skl_ddi_wrpll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1759

int ref_clock = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

178

void assert_dpll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1786

drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1820

if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1828

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1834

display->dpll.ref_clks.nssc, &wrpll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

185

if (drm_WARN(display->drm, !pll,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1858

crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

189

cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

190

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1902

static int skl_ddi_lcpll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1930

drm_WARN(display->drm, 1, "Unsupported link rate\n");

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1981

static int skl_ddi_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1992

return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1994

return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1997

static void skl_update_dpll_ref_clks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2000

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2056

static void bxt_ddi_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

206

enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2067

bxt_port_to_phy_channel(display, port, &phy, &ch);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2070

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2072

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2073

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2076

ret = intel_de_wait_for_set_us(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2080

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2085

intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2089

intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

209

return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2093

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2097

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2101

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2105

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2109

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2114

intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2117

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2120

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2123

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2127

intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2130

temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2132

intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2135

intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2138

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2139

intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2141

ret = intel_de_wait_for_set_us(display, BXT_PORT_PLL_ENABLE(port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2144

drm_err(display->drm, "PLL %d not locked\n", port);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2146

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2147

temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2149

intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2156

temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2160

intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2163

static void bxt_ddi_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2169

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2170

intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2172

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2173

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2176

ret = intel_de_wait_for_clear_us(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2180

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2185

static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2197

bxt_port_to_phy_channel(display, port, &phy, &ch);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2199

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2206

val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2210

hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2213

hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2216

hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2219

hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2222

hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2225

hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2228

hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

223

intel_combo_pll_enable_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2233

hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2236

hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2239

hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2248

hw_state->pcsdw12 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2250

if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2251

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2254

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

226

if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2261

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

228

else if ((display->platform.jasperlake || display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2282

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2292

drm_WARN_ON(display->drm, clk_div->m1 != 2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2300

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2311

chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2313

drm_WARN_ON(display->drm, clk_div->vco == 0 ||

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2320

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2344

drm_err(display->drm, "Invalid VCO\n");

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

236

intel_tc_pll_enable_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2385

static int bxt_ddi_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2401

return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2417

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

242

if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2427

crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2452

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2460

pll = intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2462

drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2473

static void bxt_update_dpll_ref_clks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2475

display->dpll.ref_clks.ssc = 100000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2476

display->dpll.ref_clks.nssc = 100000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

248

static void _intel_enable_shared_dpll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

252

pll->wakeref = intel_display_power_get(display, pll->info->power_domain);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

254

pll->info->funcs->enable(display, pll, &pll->state.hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

258

static void _intel_disable_shared_dpll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

261

pll->info->funcs->disable(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2628

ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2630

return ((display->platform.elkhartlake &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2631

IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2632

DISPLAY_VER(display) >= 12) &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2633

display->dpll.ref_clks.nssc == 38400;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

265

intel_display_power_put(display, pll->info->power_domain, pll->wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2725

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2727

display->dpll.ref_clks.nssc == 24000 ?

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2747

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2749

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2750

switch (display->dpll.ref_clks.nssc) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2752

MISSING_CASE(display->dpll.ref_clks.nssc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

276

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2763

switch (display->dpll.ref_clks.nssc) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2765

MISSING_CASE(display->dpll.ref_clks.nssc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2780

static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2788

drm_WARN_ON(display->drm, 1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2793

static int icl_wrpll_ref_clock(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2795

int ref_clock = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2811

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2812

int ref_clock = icl_wrpll_ref_clock(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

282

if (drm_WARN_ON(display->drm, !pll))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

285

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2851

static int icl_ddi_combo_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2856

int ref_clock = icl_wrpll_ref_clock(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

288

if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

289

drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2902

if (ehl_combo_pll_div_frac_wa_needed(display))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2907

if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2913

static void icl_calc_dpll_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2920

if (ehl_combo_pll_div_frac_wa_needed(display))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2931

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2936

if (display->vbt.override_afc_startup)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2937

hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

294

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

300

drm_WARN_ON(display->drm, !pll->on);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

301

assert_dpll_enabled(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3023

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3025

int refclk_khz = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3035

bool is_dkl = DISPLAY_VER(display) >= 12;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

304

drm_WARN_ON(display->drm, pll->on);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

306

drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

308

_intel_enable_shared_dpll(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

311

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3133

if (display->vbt.override_afc_startup) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3134

u8 val = display->vbt.override_afc_startup_val;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

322

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3224

static int icl_ddi_mg_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3232

ref_clock = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3234

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

328

if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3339

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

334

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

335

if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3356

icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3361

crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3371

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3379

if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3385

} else if (display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3395

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

340

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3400

} else if ((display->platform.jasperlake ||

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3401

display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3412

dpll_mask &= ~intel_hti_dpll_mask(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3431

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3446

icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

345

assert_dpll_enabled(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

346

drm_WARN_ON(display->drm, !pll->on);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3460

crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3519

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

352

drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3524

enum intel_dpll_id pll_id = mtl_port_to_pll_id(display, encoder->port);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

354

_intel_disable_shared_dpll(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

357

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3594

static bool mg_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3605

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3607

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

361

intel_dpll_mask_all(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3612

val = intel_de_read(display, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3616

hw_state->mg_refclkin_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3621

intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3626

intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3633

hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3634

hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3635

hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3636

hw_state->mg_pll_frac_lock = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3638

hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3640

hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3642

intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3644

if (display->dpll.ref_clks.nssc == 38400) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3657

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3661

static bool dkl_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

367

for_each_dpll(display, pll, i) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3672

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3677

val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

368

drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3685

hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3690

intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3698

intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3702

hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3704

if (display->vbt.override_afc_startup)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3708

hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3712

hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3718

hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3723

intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3729

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3733

static bool icl_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3744

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3749

val = intel_de_read(display, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3753

if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3754

hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3755

hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3756

} else if (display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3757

hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3758

hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3759

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3760

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3762

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3764

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3765

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3767

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3769

if (display->vbt.override_afc_startup) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3770

hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3774

if ((display->platform.jasperlake || display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3776

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3778

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3781

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3783

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3790

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3794

static bool combo_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3798

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3800

return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3803

static bool icl_tbt_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3807

return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3810

static void icl_dpll_write(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3817

if (display->platform.alderlake_s) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

382

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3820

} else if (display->platform.dg1) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3823

} else if (display->platform.rocketlake) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3826

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

383

unsigned long dpll_mask_all = intel_dpll_mask_all(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3831

if ((display->platform.jasperlake || display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3841

intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3842

intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3843

drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3845

if (display->vbt.override_afc_startup &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3847

intel_de_rmw(display, div0_reg,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3849

intel_de_posting_read(display, cfgcr1_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3852

static void icl_mg_pll_write(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3864

intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3867

intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3871

intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3878

intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3879

intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3880

intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3881

intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3883

intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3885

intel_de_rmw(display, MG_PLL_BIAS(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3888

intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3892

intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3895

static void dkl_pll_write(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

390

drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3907

val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3910

intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3912

val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3915

intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3917

val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3923

intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3926

if (display->vbt.override_afc_startup)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3928

intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3931

val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3935

intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3937

val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3943

intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3945

val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3949

intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

395

pll = intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3951

val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3955

intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3957

intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3960

static void icl_pll_power_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3964

intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3970

if (intel_de_wait_for_set_ms(display, enable_reg, PLL_POWER_STATE, 1))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3971

drm_err(display->drm, "PLL %d Power not enabled\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3975

static void icl_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3979

intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3982

if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3983

drm_err(display->drm, "PLL %d not locked\n", pll->info->id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3986

static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3990

if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4004

val = intel_de_read(display, TRANS_CMTG_CHICKEN);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4005

val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4006

if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4007

drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4010

static void combo_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4015

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4017

icl_pll_power_enable(display, pll, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4019

icl_dpll_write(display, pll, hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4027

icl_pll_enable(display, pll, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4029

adlp_cmtg_clock_gating_wa(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4034

static void icl_tbt_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4040

icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4042

icl_dpll_write(display, pll, hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4050

icl_pll_enable(display, pll, TBT_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4055

static void mg_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4060

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4062

icl_pll_power_enable(display, pll, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4064

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4065

dkl_pll_write(display, pll, hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4067

icl_mg_pll_write(display, pll, hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4075

icl_pll_enable(display, pll, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4080

static void icl_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

409

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4092

intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4095

if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4096

drm_err(display->drm, "PLL %d locked\n", pll->info->id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4100

intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4106

if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_POWER_STATE, 1))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4107

drm_err(display->drm, "PLL %d Power not disabled\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4111

static void combo_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4114

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4116

icl_pll_disable(display, pll, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4119

static void icl_tbt_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4122

icl_pll_disable(display, pll, TBT_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4125

static void mg_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4128

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4130

icl_pll_disable(display, pll, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4133

static void icl_update_dpll_ref_clks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4136

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

421

drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4355

static struct intel_encoder *get_intel_encoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4361

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4362

mtl_id = mtl_port_to_pll_id(display, encoder->port);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4371

static bool mtl_pll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4375

struct intel_encoder *encoder = get_intel_encoder(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4383

static int mtl_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4387

struct intel_encoder *encoder = get_intel_encoder(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4389

if (drm_WARN_ON(display->drm, !encoder))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4395

static void mtl_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4399

struct intel_encoder *encoder = get_intel_encoder(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4401

if (drm_WARN_ON(display->drm, !encoder))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4407

static void mtl_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4410

struct intel_encoder *encoder = get_intel_encoder(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4412

if (drm_WARN_ON(display->drm, !encoder))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4425

static void mtl_tbt_pll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

443

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4431

static void mtl_tbt_pll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4436

static int mtl_tbt_pll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4444

drm_WARN_ON(display->drm, 1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

445

drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

449

drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4579

void intel_dpll_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4585

mutex_init(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4587

if (DISPLAY_VER(display) >= 35 || display->platform.dg2)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4590

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4592

else if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4594

else if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4596

else if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4598

else if (display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4600

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4602

else if (display->platform.jasperlake || display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4604

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4606

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4608

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4610

else if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4612

else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4621

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4622

i >= ARRAY_SIZE(display->dpll.dplls)))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4626

if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4629

display->dpll.dplls[i].info = &dpll_info[i];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4630

display->dpll.dplls[i].index = i;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4633

display->dpll.mgr = dpll_mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4634

display->dpll.num_dpll = i;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4655

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4656

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4658

if (drm_WARN_ON(display->drm, !dpll_mgr))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4688

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4689

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4691

if (drm_WARN_ON(display->drm, !dpll_mgr))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4711

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4712

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4740

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4741

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4743

if (drm_WARN_ON(display->drm, !dpll_mgr))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4757

int intel_dpll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4761

if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4764

return pll->info->funcs->get_freq(display, pll, dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4775

bool intel_dpll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4779

return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4782

static void readout_dpll_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4787

pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4790

pll->wakeref = intel_display_power_get(display, pll->info->power_domain);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4793

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4802

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4807

void intel_dpll_update_ref_clks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4809

if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4810

display->dpll.mgr->update_ref_clks(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4813

void intel_dpll_readout_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4818

for_each_dpll(display, pll, i)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4819

readout_dpll_hw_state(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

482

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4822

static void sanitize_dpll_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4828

adlp_cmtg_clock_gating_wa(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4833

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4837

_intel_disable_shared_dpll(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

484

drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4840

void intel_dpll_sanitize_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4845

intel_cx0_pll_power_save_wa(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4847

for_each_dpll(display, pll, i)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4848

sanitize_dpll_state(display, pll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4859

void intel_dpll_dump_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4863

if (display->dpll.mgr) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4864

display->dpll.mgr->dump_hw_state(p, dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

488

drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4883

bool intel_dpll_compare_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4887

if (display->dpll.mgr) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4888

return display->dpll.mgr->compare_hw_state(a, b);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4898

verify_single_dpll_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4907

active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4910

INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4913

INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4916

INTEL_DISPLAY_STATE_WARN(display, pll->on != active,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4922

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4933

INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4937

INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4941

INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4945

if (INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4950

struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4953

intel_dpll_dump_hw_state(display, &p, &dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4955

intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4969

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4976

verify_single_dpll_state(display, new_crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4984

INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4989

INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4999

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5003

for_each_dpll(display, pll, i)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5004

verify_single_dpll_state(display, pll, NULL, NULL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

532

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

540

for_each_dpll(display, pll, i)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

544

static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

553

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

558

val = intel_de_read(display, PCH_DPLL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

560

hw_state->fp0 = intel_de_read(display, PCH_FP0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

561

hw_state->fp1 = intel_de_read(display, PCH_FP1(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

563

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

568

static void ibx_assert_pch_refclk_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

573

val = intel_de_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

576

INTEL_DISPLAY_STATE_WARN(display, !enabled,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

580

static void ibx_pch_dpll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

588

ibx_assert_pch_refclk_enabled(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

590

intel_de_write(display, PCH_FP0(id), hw_state->fp0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

591

intel_de_write(display, PCH_FP1(id), hw_state->fp1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

593

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

596

intel_de_posting_read(display, PCH_DPLL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

604

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

605

intel_de_posting_read(display, PCH_DPLL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

609

static void ibx_pch_dpll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

614

intel_de_write(display, PCH_DPLL(id), 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

615

intel_de_posting_read(display, PCH_DPLL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

630

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

636

if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

639

pll = intel_get_dpll_by_id(display, id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

641

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

710

static void hsw_ddi_wrpll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

717

intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

718

intel_de_posting_read(display, WRPLL_CTL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

72

void (*enable)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

722

static void hsw_ddi_spll_enable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

728

intel_de_write(display, SPLL_CTL, hw_state->spll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

729

intel_de_posting_read(display, SPLL_CTL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

733

static void hsw_ddi_wrpll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

738

intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

739

intel_de_posting_read(display, WRPLL_CTL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

745

if (display->dpll.pch_ssc_use & BIT(id))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

746

intel_init_pch_refclk(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

749

static void hsw_ddi_spll_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

754

intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

755

intel_de_posting_read(display, SPLL_CTL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

761

if (display->dpll.pch_ssc_use & BIT(id))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

762

intel_init_pch_refclk(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

765

static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

774

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

779

val = intel_de_read(display, WRPLL_CTL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

782

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

787

static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

795

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

800

val = intel_de_read(display, SPLL_CTL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

803

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

81

void (*disable)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

89

bool (*get_hw_state)(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

409

intel_get_dpll_by_id(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

411

void assert_dpll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

432

int intel_dpll_get_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

435

bool intel_dpll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

441

void intel_dpll_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

442

void intel_dpll_update_ref_clks(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

443

void intel_dpll_readout_hw_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

444

void intel_dpll_sanitize_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

446

void intel_dpll_dump_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

449

bool intel_dpll_compare_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

453

enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_dpt.c

130

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/display/intel_dpt.c

142

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_dpt.c

143

atomic_inc(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_dpt.c

173

atomic_dec(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_dpt.c

174

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_dpt.c

199

void intel_dpt_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpt.c

203

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_dpt.c

206

mutex_lock(&display->drm->mode_config.fb_lock);

drivers/gpu/drm/i915/display/intel_dpt.c

207

drm_for_each_fb(drm_fb, display->drm) {

drivers/gpu/drm/i915/display/intel_dpt.c

213

mutex_unlock(&display->drm->mode_config.fb_lock);

drivers/gpu/drm/i915/display/intel_dpt.c

226

void intel_dpt_suspend(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dpt.c

230

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_dpt.c

233

mutex_lock(&display->drm->mode_config.fb_lock);

drivers/gpu/drm/i915/display/intel_dpt.c

235

drm_for_each_fb(drm_fb, display->drm) {

drivers/gpu/drm/i915/display/intel_dpt.c

242

mutex_unlock(&display->drm->mode_config.fb_lock);

drivers/gpu/drm/i915/display/intel_dpt.h

20

void intel_dpt_suspend(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpt.h

21

void intel_dpt_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dpt_common.c

14

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_dpt_common.c

16

if (DISPLAY_VER(display) == 14) {

drivers/gpu/drm/i915/display/intel_dpt_common.c

24

intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_dpt_common.c

26

display->params.enable_dpt ? 0 :

drivers/gpu/drm/i915/display/intel_dpt_common.c

29

} else if (DISPLAY_VER(display) == 13) {

drivers/gpu/drm/i915/display/intel_dpt_common.c

30

intel_de_rmw(display, CHICKEN_MISC_2,

drivers/gpu/drm/i915/display/intel_dpt_common.c

32

display->params.enable_dpt ? 0 :

drivers/gpu/drm/i915/display/intel_dram.c

101

drm_dbg_kms(display->drm, "unknown memory frequency 0x%02x\n",

drivers/gpu/drm/i915/display/intel_dram.c

107

static unsigned int chv_mem_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

111

vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK));

drivers/gpu/drm/i915/display/intel_dram.c

112

val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG);

drivers/gpu/drm/i915/display/intel_dram.c

113

vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK));

drivers/gpu/drm/i915/display/intel_dram.c

123

static unsigned int vlv_mem_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

127

vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_PUNIT));

drivers/gpu/drm/i915/display/intel_dram.c

128

val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);

drivers/gpu/drm/i915/display/intel_dram.c

129

vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_PUNIT));

drivers/gpu/drm/i915/display/intel_dram.c

144

unsigned int intel_mem_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

146

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_dram.c

147

return pnv_mem_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

148

else if (DISPLAY_VER(display) == 5)

drivers/gpu/drm/i915/display/intel_dram.c

149

return ilk_mem_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

150

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dram.c

151

return chv_mem_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

152

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_dram.c

153

return vlv_mem_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

158

static unsigned int i9xx_fsb_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

160

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

173

if (display->platform.pineview || display->platform.mobile) {

drivers/gpu/drm/i915/display/intel_dram.c

214

static unsigned int ilk_fsb_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

216

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

237

drm_dbg_kms(display->drm, "unknown fsb frequency 0x%04x\n", fsb);

drivers/gpu/drm/i915/display/intel_dram.c

242

unsigned int intel_fsb_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

244

if (DISPLAY_VER(display) == 5)

drivers/gpu/drm/i915/display/intel_dram.c

245

return ilk_fsb_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

246

else if (IS_DISPLAY_VER(display, 3, 4))

drivers/gpu/drm/i915/display/intel_dram.c

247

return i9xx_fsb_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

252

static int i915_get_dram_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

254

dram_info->fsb_freq = intel_fsb_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

256

drm_dbg_kms(display->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq);

drivers/gpu/drm/i915/display/intel_dram.c

258

dram_info->mem_freq = intel_mem_freq(display);

drivers/gpu/drm/i915/display/intel_dram.c

260

drm_dbg_kms(display->drm, "DDR speed: %d kHz\n", dram_info->mem_freq);

drivers/gpu/drm/i915/display/intel_dram.c

262

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_dram.c

263

dram_info->type = pnv_dram_type(display);

drivers/gpu/drm/i915/display/intel_dram.c

399

skl_dram_print_dimm_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dram.c

403

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dram.c

410

skl_dram_get_dimm_l_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dram.c

414

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_dram.c

424

skl_dram_print_dimm_info(display, dimm, channel, 'L');

drivers/gpu/drm/i915/display/intel_dram.c

428

skl_dram_get_dimm_s_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dram.c

432

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_dram.c

442

skl_dram_print_dimm_info(display, dimm, channel, 'S');

drivers/gpu/drm/i915/display/intel_dram.c

446

skl_dram_get_channel_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dram.c

450

skl_dram_get_dimm_l_info(display, &ch->dimm_l, channel, val);

drivers/gpu/drm/i915/display/intel_dram.c

451

skl_dram_get_dimm_s_info(display, &ch->dimm_s, channel, val);

drivers/gpu/drm/i915/display/intel_dram.c

454

drm_dbg_kms(display->drm, "CH%u not populated\n", channel);

drivers/gpu/drm/i915/display/intel_dram.c

468

drm_dbg_kms(display->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n",

drivers/gpu/drm/i915/display/intel_dram.c

484

skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

486

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

495

ret = skl_dram_get_channel_info(display, &ch0, 0, val);

drivers/gpu/drm/i915/display/intel_dram.c

500

ret = skl_dram_get_channel_info(display, &ch1, 1, val);

drivers/gpu/drm/i915/display/intel_dram.c

505

drm_info(display->drm, "Number of memory channels is zero\n");

drivers/gpu/drm/i915/display/intel_dram.c

510

drm_info(display->drm, "couldn't get memory rank information\n");

drivers/gpu/drm/i915/display/intel_dram.c

518

drm_dbg_kms(display->drm, "Memory configuration is symmetric? %s\n",

drivers/gpu/drm/i915/display/intel_dram.c

521

drm_dbg_kms(display->drm, "16Gb+ DIMMs: %s\n",

drivers/gpu/drm/i915/display/intel_dram.c

528

skl_get_dram_type(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

530

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

551

skl_get_dram_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

555

dram_info->type = skl_get_dram_type(display);

drivers/gpu/drm/i915/display/intel_dram.c

557

ret = skl_dram_get_channels_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

58

static enum intel_dram_type pnv_dram_type(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

60

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

642

static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

644

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

66

static unsigned int pnv_mem_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

665

drm_WARN_ON(display->drm, type != INTEL_DRAM_UNKNOWN &&

drivers/gpu/drm/i915/display/intel_dram.c

669

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dram.c

68

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

682

drm_info(display->drm, "couldn't get memory information\n");

drivers/gpu/drm/i915/display/intel_dram.c

689

static int icl_pcode_read_mem_global_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dram.c

695

ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

drivers/gpu/drm/i915/display/intel_dram.c

700

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_dram.c

751

static int gen11_get_dram_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

755

ret = skl_dram_get_channels_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

759

return icl_pcode_read_mem_global_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

762

static int gen12_get_dram_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

764

return icl_pcode_read_mem_global_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

767

static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info)

drivers/gpu/drm/i915/display/intel_dram.c

769

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.c

792

drm_WARN_ON(display->drm, !display->platform.dgfx);

drivers/gpu/drm/i915/display/intel_dram.c

796

drm_WARN_ON(display->drm, !display->platform.dgfx);

drivers/gpu/drm/i915/display/intel_dram.c

808

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/intel_dram.c

814

int intel_dram_detect(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

819

if (display->platform.dg2 || !HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_dram.c

822

dram_info = drmm_kzalloc(display->drm, sizeof(*dram_info), GFP_KERNEL);

drivers/gpu/drm/i915/display/intel_dram.c

826

display->dram.info = dram_info;

drivers/gpu/drm/i915/display/intel_dram.c

828

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dram.c

829

ret = xelpdp_get_dram_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

830

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_dram.c

831

ret = gen12_get_dram_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

832

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_dram.c

833

ret = gen11_get_dram_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

834

else if (display->platform.broxton || display->platform.geminilake)

drivers/gpu/drm/i915/display/intel_dram.c

835

ret = bxt_get_dram_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

836

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_dram.c

837

ret = skl_get_dram_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

839

ret = i915_get_dram_info(display, dram_info);

drivers/gpu/drm/i915/display/intel_dram.c

841

drm_dbg_kms(display->drm, "DRAM type: %s\n",

drivers/gpu/drm/i915/display/intel_dram.c

844

drm_dbg_kms(display->drm, "DRAM channels: %u\n", dram_info->num_channels);

drivers/gpu/drm/i915/display/intel_dram.c

846

drm_dbg_kms(display->drm, "Num QGV points %u\n", dram_info->num_qgv_points);

drivers/gpu/drm/i915/display/intel_dram.c

847

drm_dbg_kms(display->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points);

drivers/gpu/drm/i915/display/intel_dram.c

85

static unsigned int ilk_mem_freq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

861

const struct dram_info *intel_dram_info(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dram.c

863

return display->dram.info;

drivers/gpu/drm/i915/display/intel_dram.c

87

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_dram.h

37

int intel_dram_detect(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dram.h

38

unsigned int intel_fsb_freq(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dram.h

39

unsigned int intel_mem_freq(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dram.h

40

const struct dram_info *intel_dram_info(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_drrs.c

112

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

117

if (intel_cpu_transcoder_has_m2_n2(display, crtc->drrs.cpu_transcoder))

drivers/gpu/drm/i915/display/intel_drrs.c

127

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

129

mod_delayed_work(display->wq.unordered, &crtc->drrs.work, msecs_to_jiffies(1000));

drivers/gpu/drm/i915/display/intel_drrs.c

134

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.c

140

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

drivers/gpu/drm/i915/display/intel_drrs.c

224

static void intel_drrs_frontbuffer_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_drrs.c

230

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_drrs.c

272

void intel_drrs_invalidate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_drrs.c

275

intel_drrs_frontbuffer_update(display, frontbuffer_bits, true);

drivers/gpu/drm/i915/display/intel_drrs.c

290

void intel_drrs_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_drrs.c

293

intel_drrs_frontbuffer_update(display, frontbuffer_bits, false);

drivers/gpu/drm/i915/display/intel_drrs.c

314

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

327

str_yes_no(intel_cpu_transcoder_has_drrs(display,

drivers/gpu/drm/i915/display/intel_drrs.c

355

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

377

drm_dbg_kms(display->drm, "Manually %sactivating DRRS\n", val ? "" : "de");

drivers/gpu/drm/i915/display/intel_drrs.c

69

bool intel_cpu_transcoder_has_drrs(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_drrs.c

72

if (HAS_DOUBLE_BUFFERED_M_N(display))

drivers/gpu/drm/i915/display/intel_drrs.c

75

return intel_cpu_transcoder_has_m2_n2(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_drrs.c

82

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

86

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_drrs.c

91

intel_de_rmw(display, TRANSCONF(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_drrs.h

19

bool intel_cpu_transcoder_has_drrs(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_drrs.h

25

void intel_drrs_invalidate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_drrs.h

27

void intel_drrs_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dsb.c

1005

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_dsb.c

1008

drm_info_once(display->drm,

drivers/gpu/drm/i915/display/intel_dsb.c

1028

void intel_dsb_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dsb.c

1031

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_dsb.c

1034

tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));

drivers/gpu/drm/i915/display/intel_dsb.c

1035

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp);

drivers/gpu/drm/i915/display/intel_dsb.c

1038

spin_lock(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_dsb.c

1051

spin_unlock(&display->drm->event_lock);

drivers/gpu/drm/i915/display/intel_dsb.c

1054

errors = tmp & dsb_error_int_status(display);

drivers/gpu/drm/i915/display/intel_dsb.c

1056

drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n",

drivers/gpu/drm/i915/display/intel_dsb.c

1059

drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n",

drivers/gpu/drm/i915/display/intel_dsb.c

1062

drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n",

drivers/gpu/drm/i915/display/intel_dsb.c

1065

drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n",

drivers/gpu/drm/i915/display/intel_dsb.c

1068

drm_err(display->drm, "[CRTC:%d:%s] DSB %d GOSUB programming error\n",

drivers/gpu/drm/i915/display/intel_dsb.c

133

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dsb.c

136

unsigned int latency = skl_watermark_max_latency(display, 0);

drivers/gpu/drm/i915/display/intel_dsb.c

186

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

189

return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2,

drivers/gpu/drm/i915/display/intel_dsb.c

197

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

199

return !drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dsb.c

206

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

209

drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n",

drivers/gpu/drm/i915/display/intel_dsb.c

212

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dsb.c

218

drm_dbg_kms(display->drm, "}\n");

drivers/gpu/drm/i915/display/intel_dsb.c

221

static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_dsb.c

224

return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;

drivers/gpu/drm/i915/display/intel_dsb.c

554

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

558

if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id))

drivers/gpu/drm/i915/display/intel_dsb.c

619

static u32 dsb_error_int_status(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dsb.c

633

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dsb.c

636

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_dsb.c

642

static u32 dsb_error_int_en(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dsb.c

650

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_dsb.c

657

if (0 && DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_dsb.c

760

struct intel_display *display = to_intel_display(state->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

764

if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))

drivers/gpu/drm/i915/display/intel_dsb.c

777

dsb_error_int_status(display) | DSB_PROG_INT_STATUS |

drivers/gpu/drm/i915/display/intel_dsb.c

778

dsb_error_int_en(display) | DSB_PROG_INT_EN);

drivers/gpu/drm/i915/display/intel_dsb.c

877

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

883

if (is_dsb_busy(display, pipe, dsb->id)) {

drivers/gpu/drm/i915/display/intel_dsb.c

884

drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",

drivers/gpu/drm/i915/display/intel_dsb.c

889

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

892

intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

895

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

896

dsb_error_int_status(display) | DSB_PROG_INT_STATUS |

drivers/gpu/drm/i915/display/intel_dsb.c

897

dsb_error_int_en(display) | DSB_PROG_INT_EN);

drivers/gpu/drm/i915/display/intel_dsb.c

899

intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), 0);

drivers/gpu/drm/i915/display/intel_dsb.c

901

intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

904

intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

911

struct intel_display *display = to_intel_display(crtc->base.dev);

drivers/gpu/drm/i915/display/intel_dsb.c

916

ret = poll_timeout_us(is_busy = is_dsb_busy(display, pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

922

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

925

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsb.c

928

intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,

drivers/gpu/drm/i915/display/intel_dsb.c

929

intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset,

drivers/gpu/drm/i915/display/intel_dsb.c

930

intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset);

drivers/gpu/drm/i915/display/intel_dsb.c

941

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0);

drivers/gpu/drm/i915/display/intel_dsb.c

943

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),

drivers/gpu/drm/i915/display/intel_dsb.c

944

dsb_error_int_status(display) | DSB_PROG_INT_STATUS);

drivers/gpu/drm/i915/display/intel_dsb.c

965

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_dsb.c

971

if (!HAS_DSB(display))

drivers/gpu/drm/i915/display/intel_dsb.c

974

if (!display->params.enable_dsb)

drivers/gpu/drm/i915/display/intel_dsb.c

981

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_dsb.c

986

dsb_buf = intel_dsb_buffer_create(display->drm, size);

drivers/gpu/drm/i915/display/intel_dsb.c

992

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_dsb.h

74

void intel_dsb_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dsi.c

120

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dsi.c

127

orientation = display->vbt.orientation;

drivers/gpu/drm/i915/display/intel_dsi.c

64

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_dsi.c

68

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_dsi.c

71

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/intel_dsi.c

80

return intel_mode_valid_max_plane_size(display, mode, 1);

drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c

166

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c

176

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

104

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

122

if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port]))

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

127

drm_dbg_kms(display->drm, "no dsi device for port %c\n",

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

140

drm_dbg_kms(display->drm, "DSI packet: Port %c (seq %u), Flags 0x%02x, VC %u, %s, Type 0x%02x, Length %u, Data %*ph\n",

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

180

drm_err(display->drm, "DSI send packet failed with %pe\n", ERR_PTR(ret));

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

182

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

193

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

196

drm_dbg_kms(display->drm, "%d usecs\n", delay);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

207

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

215

gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

218

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

253

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

258

drm_dbg_kms(display->drm, "SC gpio not supported\n");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

262

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

275

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

295

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

301

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

331

static void icl_native_gpio_set_value(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

336

if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2))

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

353

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

354

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

358

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

364

intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

371

intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

378

intel_de_rmw(display, GPIO(display, index),

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

387

intel_de_rmw(display, GPIO(display, index),

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

399

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

404

bool native = DISPLAY_VER(display) >= 11;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

425

drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

429

icl_native_gpio_set_value(display, gpio_number, value);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

430

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

432

else if (display->platform.valleyview)

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

434

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

472

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

473

struct acpi_device *adev = ACPI_COMPANION(display->drm->dev);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

493

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

503

drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n",

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

513

drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

531

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

544

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

546

drm_dbg_kms(display->drm, "Skipping SPI element execution\n");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

553

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

569

drm_err(display->drm, "%s failed, error: %d\n", __func__, ret);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

571

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

621

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

626

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

634

drm_WARN_ON(display->drm, *data != seq_id);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

636

drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n",

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

666

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

672

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

678

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

704

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

705

struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

763

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

771

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

817

drm_err(display->drm, "Burst mode target is not set\n");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

834

drm_err(display->drm, "Burst mode freq is less than computed\n");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

898

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

908

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

914

if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) {

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

923

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

926

pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0");

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

928

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

936

intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

938

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

946

devm_gpiod_get(display->drm->dev, "backlight", flags);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

948

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_dvo.c

133

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_dvo.c

139

tmp = intel_de_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

150

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dvo.c

154

tmp = intel_de_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

164

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dvo.c

170

tmp = intel_de_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

190

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dvo.c

196

intel_de_rmw(display, DVO(port), DVO_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_dvo.c

197

intel_de_posting_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

205

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dvo.c

213

intel_de_rmw(display, DVO(port), 0, DVO_ENABLE);

drivers/gpu/drm/i915/display/intel_dvo.c

214

intel_de_posting_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

223

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_dvo.c

228

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_dvo.c

232

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_dvo.c

292

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_dvo.c

300

dvo_val = intel_de_read(display, DVO(port)) &

drivers/gpu/drm/i915/display/intel_dvo.c

313

intel_de_write(display, DVO_SRCDIM(port),

drivers/gpu/drm/i915/display/intel_dvo.c

316

intel_de_write(display, DVO(port), dvo_val);

drivers/gpu/drm/i915/display/intel_dvo.c

322

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_dvo.c

326

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_dvo.c

329

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_dvo.c

332

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_dvo.c

340

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_dvo.c

344

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_dvo.c

417

static bool intel_dvo_init_dev(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dvo.c

432

if (intel_gmbus_is_valid_pin(display, dvo->gpio))

drivers/gpu/drm/i915/display/intel_dvo.c

444

i2c = intel_gmbus_get_adapter(display, gpio);

drivers/gpu/drm/i915/display/intel_dvo.c

460

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/intel_dvo.c

461

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

drivers/gpu/drm/i915/display/intel_dvo.c

467

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_dvo.c

468

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

drivers/gpu/drm/i915/display/intel_dvo.c

476

static bool intel_dvo_probe(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dvo.c

483

if (intel_dvo_init_dev(display, intel_dvo,

drivers/gpu/drm/i915/display/intel_dvo.c

491

void intel_dvo_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_dvo.c

519

if (!intel_dvo_probe(display, intel_dvo)) {

drivers/gpu/drm/i915/display/intel_dvo.c

525

assert_port_valid(display, intel_dvo->dev.port);

drivers/gpu/drm/i915/display/intel_dvo.c

536

drm_encoder_init(display->drm, &encoder->base,

drivers/gpu/drm/i915/display/intel_dvo.c

541

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] detected %s\n",

drivers/gpu/drm/i915/display/intel_dvo.c

550

drm_connector_init_with_ddc(display->drm, &connector->base,

drivers/gpu/drm/i915/display/intel_dvo.c

553

intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));

drivers/gpu/drm/i915/display/intel_dvo.h

12

void intel_dvo_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_dvo.h

14

static inline void intel_dvo_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_encoder.c

100

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_encoder.c

102

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_encoder.c

35

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_encoder.c

37

mod_delayed_work(display->wq.unordered,

drivers/gpu/drm/i915/display/intel_encoder.c

41

void intel_encoder_unblock_all_hpds(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_encoder.c

45

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_encoder.c

48

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_encoder.c

52

void intel_encoder_block_all_hpds(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_encoder.c

56

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_encoder.c

59

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_encoder.c

63

void intel_encoder_suspend_all(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_encoder.c

67

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_encoder.c

74

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_encoder.c

75

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_encoder.c

78

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_encoder.c

80

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_encoder.c

85

void intel_encoder_shutdown_all(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_encoder.c

89

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_encoder.c

96

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_encoder.c

97

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_encoder.h

18

void intel_encoder_suspend_all(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_encoder.h

19

void intel_encoder_shutdown_all(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_encoder.h

21

void intel_encoder_block_all_hpds(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_encoder.h

22

void intel_encoder_unblock_all_hpds(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fb.c

1018

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

1021

drm_WARN_ON(display->drm, new_offset > old_offset);

drivers/gpu/drm/i915/display/intel_fb.c

1027

tile_size = intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

1077

static u32 intel_compute_aligned_offset(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fb.c

1092

tile_size = intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

1136

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1143

return intel_compute_aligned_offset(display, x, y, fb, color_plane,

drivers/gpu/drm/i915/display/intel_fb.c

1152

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

1156

alignment = intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

1161

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1173

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1193

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

1227

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1241

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1256

if (DISPLAY_VER(display) < 4)

drivers/gpu/drm/i915/display/intel_fb.c

1268

unsigned int alignment = intel_tile_size(display) - 1;

drivers/gpu/drm/i915/display/intel_fb.c

1281

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1283

return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&

drivers/gpu/drm/i915/display/intel_fb.c

1289

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1292

return DISPLAY_VER(display) < 4 ||

drivers/gpu/drm/i915/display/intel_fb.c

1338

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1344

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1365

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1376

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1377

unsigned int tile_size = intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

1380

offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane,

drivers/gpu/drm/i915/display/intel_fb.c

1431

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1434

if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&

drivers/gpu/drm/i915/display/intel_fb.c

1464

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1470

return DIV_ROUND_UP(size, intel_tile_size(display));

drivers/gpu/drm/i915/display/intel_fb.c

1473

#define assign_chk_ovf(display, var, val) ({ \

drivers/gpu/drm/i915/display/intel_fb.c

1474

drm_WARN_ON((display)->drm, overflows_type(val, var)); \

drivers/gpu/drm/i915/display/intel_fb.c

1478

#define assign_bfld_chk_ovf(display, var, val) ({ \

drivers/gpu/drm/i915/display/intel_fb.c

1480

drm_WARN_ON((display)->drm, (var) != (val)); \

drivers/gpu/drm/i915/display/intel_fb.c

1489

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1494

unsigned int tile_size = intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

1498

assign_bfld_chk_ovf(display, remap_info->offset, obj_offset);

drivers/gpu/drm/i915/display/intel_fb.c

1503

assign_chk_ovf(display, remap_info->size,

drivers/gpu/drm/i915/display/intel_fb.c

1508

assign_chk_ovf(display, remap_info->src_stride,

drivers/gpu/drm/i915/display/intel_fb.c

1510

assign_chk_ovf(display, remap_info->width,

drivers/gpu/drm/i915/display/intel_fb.c

1512

assign_chk_ovf(display, remap_info->height,

drivers/gpu/drm/i915/display/intel_fb.c

1517

drm_WARN_ON(display->drm, remap_info->linear);

drivers/gpu/drm/i915/display/intel_fb.c

1518

check_array_bounds(display, view->gtt.rotated.plane, color_plane);

drivers/gpu/drm/i915/display/intel_fb.c

1520

assign_chk_ovf(display, remap_info->dst_stride,

drivers/gpu/drm/i915/display/intel_fb.c

1541

drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);

drivers/gpu/drm/i915/display/intel_fb.c

1543

check_array_bounds(display, view->gtt.remapped.plane, color_plane);

drivers/gpu/drm/i915/display/intel_fb.c

1577

assign_chk_ovf(display, remap_info->dst_stride, dst_stride);

drivers/gpu/drm/i915/display/intel_fb.c

1635

static void intel_fb_view_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fb.c

1643

(display->platform.alderlake_p || DISPLAY_VER(display) >= 14))

drivers/gpu/drm/i915/display/intel_fb.c

1649

struct intel_display *display = to_intel_display(fb->base.dev);

drivers/gpu/drm/i915/display/intel_fb.c

1651

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_fb.c

1660

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

1664

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/intel_fb.c

1672

drm_WARN_ON(display->drm, plane_min_alignment &&

drivers/gpu/drm/i915/display/intel_fb.c

1686

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

1690

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/intel_fb.c

1700

int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb)

drivers/gpu/drm/i915/display/intel_fb.c

1707

unsigned int tile_size = intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

1709

intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL);

drivers/gpu/drm/i915/display/intel_fb.c

1711

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1716

intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED);

drivers/gpu/drm/i915/display/intel_fb.c

1718

intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);

drivers/gpu/drm/i915/display/intel_fb.c

1737

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1744

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1790

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

1835

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1844

intel_fb_view_init(display, &plane_state->view,

drivers/gpu/drm/i915/display/intel_fb.c

1853

drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier));

drivers/gpu/drm/i915/display/intel_fb.c

1974

u32 intel_fb_max_stride(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fb.c

1984

if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) ||

drivers/gpu/drm/i915/display/intel_fb.c

1985

intel_fb_modifier_uses_dpt(display, modifier))

drivers/gpu/drm/i915/display/intel_fb.c

1986

return intel_plane_fb_max_stride(display, info, modifier);

drivers/gpu/drm/i915/display/intel_fb.c

1987

else if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/intel_fb.c

1996

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

2000

unsigned int max_stride = intel_plane_fb_max_stride(display,

drivers/gpu/drm/i915/display/intel_fb.c

2010

return intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

2021

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_fb.c

2032

else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) &&

drivers/gpu/drm/i915/display/intel_fb.c

2041

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2063

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2127

struct intel_display *display = to_intel_display(obj->dev);

drivers/gpu/drm/i915/display/intel_fb.c

2130

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2213

struct intel_display *display = to_intel_display(obj->dev);

drivers/gpu/drm/i915/display/intel_fb.c

2219

intel_fb->panic = intel_parent_panic_alloc(display);

drivers/gpu/drm/i915/display/intel_fb.c

2237

if (!drm_any_plane_has_format(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2240

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2247

max_stride = intel_fb_max_stride(display, info, mode_cmd->modifier[0]);

drivers/gpu/drm/i915/display/intel_fb.c

2249

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2260

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2267

drm_helper_mode_fill_fb_struct(display->drm, fb, info, mode_cmd);

drivers/gpu/drm/i915/display/intel_fb.c

2273

drm_dbg_kms(display->drm, "bad plane %d handle\n", i);

drivers/gpu/drm/i915/display/intel_fb.c

2280

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2291

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb.c

2302

ret = intel_fill_fb_info(display, intel_fb);

drivers/gpu/drm/i915/display/intel_fb.c

2311

drm_dbg_kms(display->drm, "failed to create DPT\n");

drivers/gpu/drm/i915/display/intel_fb.c

2319

ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs);

drivers/gpu/drm/i915/display/intel_fb.c

2321

drm_err(display->drm, "framebuffer init failed %d\n", ret);

drivers/gpu/drm/i915/display/intel_fb.c

26

#define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))

drivers/gpu/drm/i915/display/intel_fb.c

546

static bool plane_has_modifier(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fb.c

550

if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until))

drivers/gpu/drm/i915/display/intel_fb.c

561

intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)

drivers/gpu/drm/i915/display/intel_fb.c

565

(DISPLAY_VER(display) < 14 || !display->platform.dgfx))

drivers/gpu/drm/i915/display/intel_fb.c

569

(DISPLAY_VER(display) < 20 || display->platform.dgfx))

drivers/gpu/drm/i915/display/intel_fb.c

584

u64 *intel_fb_plane_get_modifiers(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fb.c

592

if (plane_has_modifier(display, plane_caps, &intel_modifiers[i]))

drivers/gpu/drm/i915/display/intel_fb.c

597

if (drm_WARN_ON(display->drm, !list))

drivers/gpu/drm/i915/display/intel_fb.c

602

if (plane_has_modifier(display, plane_caps, &intel_modifiers[i]))

drivers/gpu/drm/i915/display/intel_fb.c

758

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

762

else if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/intel_fb.c

769

unsigned int intel_tile_size(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fb.c

771

return DISPLAY_VER(display) == 2 ? 2048 : 4096;

drivers/gpu/drm/i915/display/intel_fb.c

777

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

782

return intel_tile_size(display);

drivers/gpu/drm/i915/display/intel_fb.c

784

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_fb.c

814

if (HAS_128B_Y_TILING(display))

drivers/gpu/drm/i915/display/intel_fb.c

845

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

847

return intel_tile_size(display) /

drivers/gpu/drm/i915/display/intel_fb.c

899

bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier)

drivers/gpu/drm/i915/display/intel_fb.c

901

return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR;

drivers/gpu/drm/i915/display/intel_fb.c

906

struct intel_display *display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/intel_fb.c

908

return display->params.enable_dpt &&

drivers/gpu/drm/i915/display/intel_fb.c

909

intel_fb_modifier_uses_dpt(display, fb->modifier);

drivers/gpu/drm/i915/display/intel_fb.h

120

bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier);

drivers/gpu/drm/i915/display/intel_fb.h

45

u64 *intel_fb_plane_get_modifiers(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fb.h

62

unsigned int intel_tile_size(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fb.h

88

int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb);

drivers/gpu/drm/i915/display/intel_fb_bo.c

26

struct intel_display *display = to_intel_display(obj->base.dev);

drivers/gpu/drm/i915/display/intel_fb_bo.c

41

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb_bo.c

49

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb_bo.c

59

if (DISPLAY_VER(display) < 4 &&

drivers/gpu/drm/i915/display/intel_fb_bo.c

61

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb_bo.c

71

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fb_pin.c

106

atomic_dec(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_fb_pin.c

121

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_fb_pin.c

144

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_fb_pin.c

146

atomic_inc(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_fb_pin.c

157

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_fb_pin.c

198

if (ret != 0 && DISPLAY_VER(display) < 4) {

drivers/gpu/drm/i915/display/intel_fb_pin.c

222

atomic_dec(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_fb_pin.c

223

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_fb_pin.c

266

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb_pin.c

310

drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma));

drivers/gpu/drm/i915/display/intel_fb_pin.c

33

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_fb_pin.c

51

atomic_inc(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_fbc.c

1000

fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);

drivers/gpu/drm/i915/display/intel_fbc.c

1004

static int fbc_sys_cache_limit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

1006

if (DISPLAY_VER(display) == 35)

drivers/gpu/drm/i915/display/intel_fbc.c

1014

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

1015

struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;

drivers/gpu/drm/i915/display/intel_fbc.c

1019

if (!HAS_FBC_SYS_CACHE(display))

drivers/gpu/drm/i915/display/intel_fbc.c

1022

range = fbc_sys_cache_limit(display) / (64 * 1024);

drivers/gpu/drm/i915/display/intel_fbc.c

1024

offset = intel_parent_stolen_node_offset(display, fbc->compressed_fb) / (4 * 1024);

drivers/gpu/drm/i915/display/intel_fbc.c

1032

fbc_sys_cache_update_config(display, cfg, fbc->id);

drivers/gpu/drm/i915/display/intel_fbc.c

1038

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

1043

if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb))

drivers/gpu/drm/i915/display/intel_fbc.c

1044

intel_parent_stolen_remove_node(display, fbc->compressed_llb);

drivers/gpu/drm/i915/display/intel_fbc.c

1045

if (intel_parent_stolen_node_allocated(display, fbc->compressed_fb))

drivers/gpu/drm/i915/display/intel_fbc.c

1046

intel_parent_stolen_remove_node(display, fbc->compressed_fb);

drivers/gpu/drm/i915/display/intel_fbc.c

1049

void intel_fbc_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

1054

for_each_intel_fbc(display, fbc, fbc_id) {

drivers/gpu/drm/i915/display/intel_fbc.c

1059

intel_parent_stolen_node_free(display, fbc->compressed_fb);

drivers/gpu/drm/i915/display/intel_fbc.c

1060

intel_parent_stolen_node_free(display, fbc->compressed_llb);

drivers/gpu/drm/i915/display/intel_fbc.c

1065

mutex_lock(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

1066

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

1067

display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE);

drivers/gpu/drm/i915/display/intel_fbc.c

1068

mutex_unlock(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

1114

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1116

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_fbc.c

1118

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_fbc.c

1120

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

1122

else if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/intel_fbc.c

1130

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1140

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_fbc.c

1150

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1159

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

1220

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1222

if (HAS_PIXEL_NORMALIZER(display) &&

drivers/gpu/drm/i915/display/intel_fbc.c

1231

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1233

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/intel_fbc.c

1235

else if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_fbc.c

1237

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

1267

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1269

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_fbc.c

1271

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

1277

static void intel_fbc_max_surface_size(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

1280

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/intel_fbc.c

1283

} else if (DISPLAY_VER(display) >= 10) {

drivers/gpu/drm/i915/display/intel_fbc.c

1286

} else if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/intel_fbc.c

1289

} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_fbc.c

130

static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fbc.c

1306

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1309

intel_fbc_max_surface_size(display, &max_w, &max_h);

drivers/gpu/drm/i915/display/intel_fbc.c

1319

static void intel_fbc_max_plane_size(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

132

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_fbc.c

1322

if (DISPLAY_VER(display) >= 10) {

drivers/gpu/drm/i915/display/intel_fbc.c

1325

} else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_fbc.c

1328

} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_fbc.c

1339

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1342

intel_fbc_max_plane_size(display, &max_w, &max_h);

drivers/gpu/drm/i915/display/intel_fbc.c

1364

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1366

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_fbc.c

137

if (drm_WARN_ON(display->drm, !primary))

drivers/gpu/drm/i915/display/intel_fbc.c

1384

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

1386

drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0);

drivers/gpu/drm/i915/display/intel_fbc.c

1388

intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

1410

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_fbc.c

1413

if (!HAS_FBC_DIRTY_RECT(display))

drivers/gpu/drm/i915/display/intel_fbc.c

1444

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_fbc.c

1462

drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE &&

drivers/gpu/drm/i915/display/intel_fbc.c

1463

!intel_fbc_has_fences(display));

drivers/gpu/drm/i915/display/intel_fbc.c

1477

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1491

return DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_fbc.c

1498

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1504

intel_parent_stolen_node_size(display, fbc->compressed_fb);

drivers/gpu/drm/i915/display/intel_fbc.c

1544

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_fbc.c

1551

if (!HAS_FBC_DIRTY_RECT(display))

drivers/gpu/drm/i915/display/intel_fbc.c

1572

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1575

if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_fbc.c

1585

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_fbc.c

1596

if (!intel_parent_stolen_initialized(display)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1601

if (intel_parent_vgpu_active(display)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1606

if (!display->params.enable_fbc) {

drivers/gpu/drm/i915/display/intel_fbc.c

1616

if (intel_display_wa(display, 16023588340)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1626

if (intel_display_wa(display, 15018326506)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1632

if (intel_display_vtd_active(display) &&

drivers/gpu/drm/i915/display/intel_fbc.c

1633

(display->platform.skylake || display->platform.broxton)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1662

if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) {

drivers/gpu/drm/i915/display/intel_fbc.c

1668

if ((IS_DISPLAY_VER(display, 12, 13) ||

drivers/gpu/drm/i915/display/intel_fbc.c

1669

IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) &&

drivers/gpu/drm/i915/display/intel_fbc.c

1695

if (DISPLAY_VER(display) < 20 &&

drivers/gpu/drm/i915/display/intel_fbc.c

1717

if (IS_DISPLAY_VER(display, 9, 12) &&

drivers/gpu/drm/i915/display/intel_fbc.c

1724

if (IS_DISPLAY_VER(display, 9, 12) &&

drivers/gpu/drm/i915/display/intel_fbc.c

173

static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

1731

if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) {

drivers/gpu/drm/i915/display/intel_fbc.c

1743

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1757

if (min_cdclk > display->cdclk.max_cdclk_freq)

drivers/gpu/drm/i915/display/intel_fbc.c

1812

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_fbc.c

1838

if (fbc->activated && DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_fbc.c

187

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_fbc.c

1872

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

1876

drm_WARN_ON(display->drm, fbc->active);

drivers/gpu/drm/i915/display/intel_fbc.c

1878

drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_fbc.c

1888

if (display->platform.dg2 || DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_fbc.c

1956

void intel_fbc_invalidate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

1963

for_each_intel_fbc(display, fbc, fbc_id)

drivers/gpu/drm/i915/display/intel_fbc.c

1995

void intel_fbc_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

2002

for_each_intel_fbc(display, fbc, fbc_id)

drivers/gpu/drm/i915/display/intel_fbc.c

201

static unsigned int _intel_fbc_cfb_stride(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

2027

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_fbc.c

2046

drm_WARN_ON(display->drm, fbc->active);

drivers/gpu/drm/i915/display/intel_fbc.c

2068

drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_fbc.c

2074

if (HAS_FBC_DIRTY_RECT(display))

drivers/gpu/drm/i915/display/intel_fbc.c

2091

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fbc.c

2094

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/intel_fbc.c

210

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_fbc.c

211

return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width));

drivers/gpu/drm/i915/display/intel_fbc.c

2139

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

2147

drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n");

drivers/gpu/drm/i915/display/intel_fbc.c

2152

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));

drivers/gpu/drm/i915/display/intel_fbc.c

2160

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

2167

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

218

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

2183

void intel_fbc_reset_underrun(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2188

for_each_intel_fbc(display, fbc, fbc_id)

drivers/gpu/drm/i915/display/intel_fbc.c

2194

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

2207

queue_work(display->wq.unordered, &fbc->underrun_work);

drivers/gpu/drm/i915/display/intel_fbc.c

2224

void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2229

for_each_intel_fbc(display, fbc, fbc_id)

drivers/gpu/drm/i915/display/intel_fbc.c

223

return _intel_fbc_cfb_stride(display, cpp, width, stride);

drivers/gpu/drm/i915/display/intel_fbc.c

2243

void intel_fbc_read_underrun_dbg_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

2246

struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_fbc.c

2252

val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));

drivers/gpu/drm/i915/display/intel_fbc.c

2256

intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);

drivers/gpu/drm/i915/display/intel_fbc.c

2259

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

2273

static int intel_sanitize_fbc_option(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2275

if (display->params.enable_fbc >= 0)

drivers/gpu/drm/i915/display/intel_fbc.c

2276

return !!display->params.enable_fbc;

drivers/gpu/drm/i915/display/intel_fbc.c

2278

if (!HAS_FBC(display))

drivers/gpu/drm/i915/display/intel_fbc.c

2281

if (display->platform.broadwell || DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_fbc.c

2292

static struct intel_fbc *intel_fbc_create(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

2301

fbc->compressed_fb = intel_parent_stolen_node_alloc(display);

drivers/gpu/drm/i915/display/intel_fbc.c

2304

fbc->compressed_llb = intel_parent_stolen_node_alloc(display);

drivers/gpu/drm/i915/display/intel_fbc.c

2309

fbc->display = display;

drivers/gpu/drm/i915/display/intel_fbc.c

231

static unsigned int intel_fbc_max_cfb_height(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2313

if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/intel_fbc.c

2315

else if (DISPLAY_VER(display) == 6)

drivers/gpu/drm/i915/display/intel_fbc.c

2317

else if (DISPLAY_VER(display) == 5)

drivers/gpu/drm/i915/display/intel_fbc.c

2319

else if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

2321

else if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/intel_fbc.c

2329

intel_parent_stolen_node_free(display, fbc->compressed_llb);

drivers/gpu/drm/i915/display/intel_fbc.c

233

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_fbc.c

2330

intel_parent_stolen_node_free(display, fbc->compressed_fb);

drivers/gpu/drm/i915/display/intel_fbc.c

2342

void intel_fbc_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2346

display->params.enable_fbc = intel_sanitize_fbc_option(display);

drivers/gpu/drm/i915/display/intel_fbc.c

2347

drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n",

drivers/gpu/drm/i915/display/intel_fbc.c

2348

display->params.enable_fbc);

drivers/gpu/drm/i915/display/intel_fbc.c

235

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

2350

for_each_fbc_id(display, fbc_id)

drivers/gpu/drm/i915/display/intel_fbc.c

2351

display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);

drivers/gpu/drm/i915/display/intel_fbc.c

2353

mutex_init(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

2354

display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;

drivers/gpu/drm/i915/display/intel_fbc.c

2365

void intel_fbc_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2370

for_each_intel_fbc(display, fbc, fbc_id) {

drivers/gpu/drm/i915/display/intel_fbc.c

2376

mutex_lock(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

2377

fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);

drivers/gpu/drm/i915/display/intel_fbc.c

2378

mutex_unlock(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

2384

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

2388

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_fbc.c

2390

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_fbc.c

2398

mutex_lock(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

2400

str_yes_no(display->fbc.sys_cache.id == fbc->id));

drivers/gpu/drm/i915/display/intel_fbc.c

2401

mutex_unlock(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

2406

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/intel_fbc.c

241

static unsigned int _intel_fbc_cfb_size(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.c

2420

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_fbc.c

2422

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_fbc.c

244

return min(height, intel_fbc_max_cfb_height(display)) * stride;

drivers/gpu/drm/i915/display/intel_fbc.c

2479

void intel_fbc_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

2483

fbc = display->fbc.instances[INTEL_FBC_A];

drivers/gpu/drm/i915/display/intel_fbc.c

2485

intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);

drivers/gpu/drm/i915/display/intel_fbc.c

249

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

252

return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state));

drivers/gpu/drm/i915/display/intel_fbc.c

257

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

272

(DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) ||

drivers/gpu/drm/i915/display/intel_fbc.c

273

display->platform.battlemage)

drivers/gpu/drm/i915/display/intel_fbc.c

279

static bool intel_fbc_has_fences(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

281

return intel_parent_has_fenced_regions(display);

drivers/gpu/drm/i915/display/intel_fbc.c

286

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

294

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_fbc.c

303

if (display->platform.i945gm)

drivers/gpu/drm/i915/display/intel_fbc.c

328

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

332

fbc_ctl = intel_de_read(display, FBC_CONTROL);

drivers/gpu/drm/i915/display/intel_fbc.c

337

intel_de_write(display, FBC_CONTROL, fbc_ctl);

drivers/gpu/drm/i915/display/intel_fbc.c

340

if (intel_de_wait_for_clear_ms(display, FBC_STATUS,

drivers/gpu/drm/i915/display/intel_fbc.c

342

drm_dbg_kms(display->drm, "FBC idle timed out\n");

drivers/gpu/drm/i915/display/intel_fbc.c

349

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

355

intel_de_write(display, FBC_TAG(i), 0);

drivers/gpu/drm/i915/display/intel_fbc.c

357

if (DISPLAY_VER(display) == 4) {

drivers/gpu/drm/i915/display/intel_fbc.c

358

intel_de_write(display, FBC_CONTROL2,

drivers/gpu/drm/i915/display/intel_fbc.c

360

intel_de_write(display, FBC_FENCE_OFF,

drivers/gpu/drm/i915/display/intel_fbc.c

364

intel_de_write(display, FBC_CONTROL,

drivers/gpu/drm/i915/display/intel_fbc.c

370

return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;

drivers/gpu/drm/i915/display/intel_fbc.c

375

return intel_de_read(fbc->display, FBC_STATUS) &

drivers/gpu/drm/i915/display/intel_fbc.c

381

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

385

intel_de_write_fw(display, DSPADDR(display, i9xx_plane),

drivers/gpu/drm/i915/display/intel_fbc.c

386

intel_de_read_fw(display, DSPADDR(display, i9xx_plane)));

drivers/gpu/drm/i915/display/intel_fbc.c

391

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

393

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

394

range_end_overflows_t(u64, intel_parent_stolen_area_address(display),

drivers/gpu/drm/i915/display/intel_fbc.c

395

intel_parent_stolen_node_offset(display, fbc->compressed_fb),

drivers/gpu/drm/i915/display/intel_fbc.c

397

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

398

range_end_overflows_t(u64, intel_parent_stolen_area_address(display),

drivers/gpu/drm/i915/display/intel_fbc.c

399

intel_parent_stolen_node_offset(display, fbc->compressed_llb),

drivers/gpu/drm/i915/display/intel_fbc.c

401

intel_de_write(display, FBC_CFB_BASE,

drivers/gpu/drm/i915/display/intel_fbc.c

402

intel_parent_stolen_node_address(display, fbc->compressed_fb));

drivers/gpu/drm/i915/display/intel_fbc.c

403

intel_de_write(display, FBC_LL_BASE,

drivers/gpu/drm/i915/display/intel_fbc.c

404

intel_parent_stolen_node_address(display, fbc->compressed_llb));

drivers/gpu/drm/i915/display/intel_fbc.c

418

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

422

intel_de_write_fw(display, DSPSURF(display, i9xx_plane),

drivers/gpu/drm/i915/display/intel_fbc.c

423

intel_de_read_fw(display, DSPSURF(display, i9xx_plane)));

drivers/gpu/drm/i915/display/intel_fbc.c

452

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

459

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

465

if (DISPLAY_VER(display) < 6)

drivers/gpu/drm/i915/display/intel_fbc.c

474

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

477

intel_de_write(display, DPFC_FENCE_YOFF,

drivers/gpu/drm/i915/display/intel_fbc.c

480

intel_de_write(display, DPFC_CONTROL,

drivers/gpu/drm/i915/display/intel_fbc.c

486

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

490

dpfc_ctl = intel_de_read(display, DPFC_CONTROL);

drivers/gpu/drm/i915/display/intel_fbc.c

493

intel_de_write(display, DPFC_CONTROL, dpfc_ctl);

drivers/gpu/drm/i915/display/intel_fbc.c

499

return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;

drivers/gpu/drm/i915/display/intel_fbc.c

504

return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;

drivers/gpu/drm/i915/display/intel_fbc.c

509

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

511

intel_de_write(display, DPFC_CB_BASE,

drivers/gpu/drm/i915/display/intel_fbc.c

512

intel_parent_stolen_node_offset(display, fbc->compressed_fb));

drivers/gpu/drm/i915/display/intel_fbc.c

526

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

529

intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

532

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

539

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

541

if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_fbc.c

542

intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS,

drivers/gpu/drm/i915/display/intel_fbc.c

544

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_fbc.c

545

intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

552

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

555

if (HAS_FBC_DIRTY_RECT(display))

drivers/gpu/drm/i915/display/intel_fbc.c

556

intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);

drivers/gpu/drm/i915/display/intel_fbc.c

559

dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));

drivers/gpu/drm/i915/display/intel_fbc.c

562

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);

drivers/gpu/drm/i915/display/intel_fbc.c

568

return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;

drivers/gpu/drm/i915/display/intel_fbc.c

573

return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;

drivers/gpu/drm/i915/display/intel_fbc.c

578

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

580

intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

581

intel_parent_stolen_node_offset(display, fbc->compressed_fb));

drivers/gpu/drm/i915/display/intel_fbc.c

595

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

602

intel_de_write(display, SNB_DPFC_CTL_SA, ctl);

drivers/gpu/drm/i915/display/intel_fbc.c

603

intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);

drivers/gpu/drm/i915/display/intel_fbc.c

615

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

617

intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);

drivers/gpu/drm/i915/display/intel_fbc.c

618

intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id));

drivers/gpu/drm/i915/display/intel_fbc.c

632

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

640

intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val);

drivers/gpu/drm/i915/display/intel_fbc.c

645

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

654

intel_de_rmw(display, CHICKEN_MISC_4,

drivers/gpu/drm/i915/display/intel_fbc.c

661

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

667

if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_fbc.c

670

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_fbc.c

684

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

687

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_fbc.c

689

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_fbc.c

692

if (intel_fbc_has_fences(display))

drivers/gpu/drm/i915/display/intel_fbc.c

697

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_fbc.c

698

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);

drivers/gpu/drm/i915/display/intel_fbc.c

700

if (HAS_FBC_DIRTY_RECT(display))

drivers/gpu/drm/i915/display/intel_fbc.c

701

intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

704

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

710

return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;

drivers/gpu/drm/i915/display/intel_fbc.c

716

intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

761

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

764

drm_WARN_ON(display->drm, fbc->flip_pending);

drivers/gpu/drm/i915/display/intel_fbc.c

773

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

778

if (fbc->active && !intel_fbc_has_fences(display))

drivers/gpu/drm/i915/display/intel_fbc.c

784

drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));

drivers/gpu/drm/i915/display/intel_fbc.c

802

static u64 intel_fbc_cfb_base_max(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

804

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

810

static u64 intel_fbc_stolen_end(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

812

u64 end = intel_fbc_cfb_base_max(display);

drivers/gpu/drm/i915/display/intel_fbc.c

820

if (display->platform.broadwell ||

drivers/gpu/drm/i915/display/intel_fbc.c

821

(DISPLAY_VER(display) == 9 && !display->platform.broxton)) {

drivers/gpu/drm/i915/display/intel_fbc.c

822

u64 stolen_area_size = intel_parent_stolen_area_size(display);

drivers/gpu/drm/i915/display/intel_fbc.c

829

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

845

static int intel_fbc_max_limit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbc.c

848

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_fbc.c

861

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

862

u64 end = intel_fbc_stolen_end(display);

drivers/gpu/drm/i915/display/intel_fbc.c

868

ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb,

drivers/gpu/drm/i915/display/intel_fbc.c

873

for (; limit <= intel_fbc_max_limit(display); limit <<= 1) {

drivers/gpu/drm/i915/display/intel_fbc.c

874

ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb,

drivers/gpu/drm/i915/display/intel_fbc.c

886

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

889

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

890

intel_parent_stolen_node_allocated(display, fbc->compressed_fb));

drivers/gpu/drm/i915/display/intel_fbc.c

891

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

892

intel_parent_stolen_node_allocated(display, fbc->compressed_llb));

drivers/gpu/drm/i915/display/intel_fbc.c

894

if (DISPLAY_VER(display) < 5 && !display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_fbc.c

895

ret = intel_parent_stolen_insert_node(display, fbc->compressed_llb, 4096, 4096);

drivers/gpu/drm/i915/display/intel_fbc.c

904

drm_info_once(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

909

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

911

intel_parent_stolen_node_size(display, fbc->compressed_fb), fbc->limit);

drivers/gpu/drm/i915/display/intel_fbc.c

915

if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb))

drivers/gpu/drm/i915/display/intel_fbc.c

916

intel_parent_stolen_remove_node(display, fbc->compressed_llb);

drivers/gpu/drm/i915/display/intel_fbc.c

918

if (intel_parent_stolen_initialized(display))

drivers/gpu/drm/i915/display/intel_fbc.c

919

drm_info_once(display->drm,

drivers/gpu/drm/i915/display/intel_fbc.c

931

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

933

if (display->platform.skylake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_fbc.c

938

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

942

if (display->platform.skylake || display->platform.kabylake ||

drivers/gpu/drm/i915/display/intel_fbc.c

943

display->platform.coffeelake || display->platform.cometlake) {

drivers/gpu/drm/i915/display/intel_fbc.c

948

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

953

if (IS_DISPLAY_VER(display, 11, 12))

drivers/gpu/drm/i915/display/intel_fbc.c

954

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

96

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_fbc.c

961

if (intel_display_wa(display, 22014263786))

drivers/gpu/drm/i915/display/intel_fbc.c

962

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

drivers/gpu/drm/i915/display/intel_fbc.c

966

if (display->platform.dg2 || DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_fbc.c

970

static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg,

drivers/gpu/drm/i915/display/intel_fbc.c

973

if (!HAS_FBC_SYS_CACHE(display))

drivers/gpu/drm/i915/display/intel_fbc.c

976

lockdep_assert_held(&display->fbc.sys_cache.lock);

drivers/gpu/drm/i915/display/intel_fbc.c

983

if (!intel_display_wa(display, 14025769978))

drivers/gpu/drm/i915/display/intel_fbc.c

987

intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);

drivers/gpu/drm/i915/display/intel_fbc.c

989

display->fbc.sys_cache.id = id;

drivers/gpu/drm/i915/display/intel_fbc.c

994

struct intel_display *display = fbc->display;

drivers/gpu/drm/i915/display/intel_fbc.c

995

struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;

drivers/gpu/drm/i915/display/intel_fbc.h

37

void intel_fbc_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbc.h

38

void intel_fbc_cleanup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbc.h

39

void intel_fbc_sanitize(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbc.h

43

void intel_fbc_invalidate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.h

46

void intel_fbc_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.h

49

void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbc.h

50

void intel_fbc_read_underrun_dbg_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbc.h

52

void intel_fbc_reset_underrun(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbc.h

54

void intel_fbc_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbdev.c

226

__intel_fbdev_fb_alloc(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbdev.c

239

obj = intel_fbdev_fb_bo_create(display->drm, size);

drivers/gpu/drm/i915/display/intel_fbdev.c

246

drm_get_format_info(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

267

struct intel_display *display = to_intel_display(helper->dev);

drivers/gpu/drm/i915/display/intel_fbdev.c

283

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

292

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_fbdev.c

294

if (!fb || drm_WARN_ON(display->drm, !intel_fb_bo(&fb->base))) {

drivers/gpu/drm/i915/display/intel_fbdev.c

295

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

298

fb = __intel_fbdev_fb_alloc(display, sizes);

drivers/gpu/drm/i915/display/intel_fbdev.c

304

drm_dbg_kms(display->drm, "re-using BIOS fb\n");

drivers/gpu/drm/i915/display/intel_fbdev.c

331

ret = intel_fbdev_fb_fill_info(display->drm, info, obj, vma);

drivers/gpu/drm/i915/display/intel_fbdev.c

335

drm_fb_helper_fill_info(info, display->drm->fb_helper, sizes);

drivers/gpu/drm/i915/display/intel_fbdev.c

346

drm_dbg_kms(display->drm, "allocated %dx%d fb: 0x%08x\n",

drivers/gpu/drm/i915/display/intel_fbdev.c

353

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_fbdev.c

360

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_fbdev.c

374

static bool intel_fbdev_init_bios(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fbdev.c

382

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_fbdev.c

392

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

399

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

406

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

415

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

421

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_fbdev.c

429

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

435

drm_dbg_kms(display->drm, "checking [PLANE:%d:%s] for BIOS fb\n",

drivers/gpu/drm/i915/display/intel_fbdev.c

446

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

457

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

466

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

474

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

481

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fbdev.c

491

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_fbdev.c

502

drm_WARN(display->drm, !plane_state->uapi.fb,

drivers/gpu/drm/i915/display/intel_fbdev.c

508

drm_dbg_kms(display->drm, "using BIOS fb for initial console\n");

drivers/gpu/drm/i915/display/intel_fbdev.c

533

void intel_fbdev_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fbdev.c

538

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_fbdev.c

541

ifbdev = drmm_kzalloc(display->drm, sizeof(*ifbdev), GFP_KERNEL);

drivers/gpu/drm/i915/display/intel_fbdev.c

545

display->fbdev.fbdev = ifbdev;

drivers/gpu/drm/i915/display/intel_fbdev.c

546

if (intel_fbdev_init_bios(display, ifbdev))

drivers/gpu/drm/i915/display/intel_fbdev.c

551

drm_client_setup_with_color_mode(display->drm, preferred_bpp);

drivers/gpu/drm/i915/display/intel_fbdev.c

69

struct intel_display *display = to_intel_display(fb_helper->client.dev);

drivers/gpu/drm/i915/display/intel_fbdev.c

71

return display->fbdev.fbdev;

drivers/gpu/drm/i915/display/intel_fbdev.h

23

void intel_fbdev_setup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbdev.h

30

static inline void intel_fbdev_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fdi.c

100

static void assert_fdi_rx_pll(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fdi.c

1005

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1008

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

drivers/gpu/drm/i915/display/intel_fdi.c

1009

intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

1011

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1015

intel_de_rmw(display, reg, 0, FDI_PCDCLK);

drivers/gpu/drm/i915/display/intel_fdi.c

1016

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1021

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1023

intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

1025

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1032

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

1036

intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

1039

intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

1040

intel_de_posting_read(display, FDI_TX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

1044

intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

1045

intel_de_posting_read(display, FDI_RX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

105

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

1051

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

1057

intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

1058

intel_de_posting_read(display, FDI_TX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

106

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_fdi.c

1061

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1063

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

drivers/gpu/drm/i915/display/intel_fdi.c

1064

intel_de_write(display, reg, temp & ~FDI_RX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

1066

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1070

if (HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/intel_fdi.c

1071

intel_de_write(display, FDI_RX_CHICKEN(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

1075

intel_de_rmw(display, FDI_TX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

1079

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1080

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_fdi.c

1089

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

drivers/gpu/drm/i915/display/intel_fdi.c

1090

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

1092

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1109

intel_fdi_init_hook(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fdi.c

111

void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

1111

if (display->platform.ironlake) {

drivers/gpu/drm/i915/display/intel_fdi.c

1112

display->funcs.fdi = &ilk_funcs;

drivers/gpu/drm/i915/display/intel_fdi.c

1113

} else if (display->platform.sandybridge) {

drivers/gpu/drm/i915/display/intel_fdi.c

1114

display->funcs.fdi = &gen6_funcs;

drivers/gpu/drm/i915/display/intel_fdi.c

1115

} else if (display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_fdi.c

1117

display->funcs.fdi = &ivb_funcs;

drivers/gpu/drm/i915/display/intel_fdi.c

113

assert_fdi_rx_pll(display, pipe, true);

drivers/gpu/drm/i915/display/intel_fdi.c

116

void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

118

assert_fdi_rx_pll(display, pipe, false);

drivers/gpu/drm/i915/display/intel_fdi.c

124

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

126

display->funcs.fdi->fdi_link_train(crtc, crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

142

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_fdi.c

147

if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3)

drivers/gpu/drm/i915/display/intel_fdi.c

150

crtc = intel_crtc_for_pipe(display, PIPE_C);

drivers/gpu/drm/i915/display/intel_fdi.c

162

crtc = intel_crtc_for_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_fdi.c

185

static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_fdi.c

195

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

199

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

205

if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_fdi.c

207

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

216

if (INTEL_NUM_PIPES(display) == 2)

drivers/gpu/drm/i915/display/intel_fdi.c

227

other_crtc = intel_crtc_for_pipe(display, PIPE_C);

drivers/gpu/drm/i915/display/intel_fdi.c

234

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

242

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

248

other_crtc = intel_crtc_for_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_fdi.c

255

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

269

void intel_fdi_pll_freq_update(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fdi.c

271

if (display->platform.ironlake) {

drivers/gpu/drm/i915/display/intel_fdi.c

274

fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;

drivers/gpu/drm/i915/display/intel_fdi.c

276

display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000;

drivers/gpu/drm/i915/display/intel_fdi.c

277

} else if (display->platform.sandybridge || display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_fdi.c

278

display->fdi.pll_freq = 270000;

drivers/gpu/drm/i915/display/intel_fdi.c

283

drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq);

drivers/gpu/drm/i915/display/intel_fdi.c

286

int intel_fdi_link_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fdi.c

289

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_fdi.c

29

static void assert_fdi_tx(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fdi.c

292

return display->fdi.pll_freq;

drivers/gpu/drm/i915/display/intel_fdi.c

298

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

309

link_bw = intel_fdi_link_freq(display, pipe_config);

drivers/gpu/drm/i915/display/intel_fdi.c

332

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

336

ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,

drivers/gpu/drm/i915/display/intel_fdi.c

34

if (HAS_DDI(display)) {

drivers/gpu/drm/i915/display/intel_fdi.c

389

static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/intel_fdi.c

393

temp = intel_de_read(display, SOUTH_CHICKEN1);

drivers/gpu/drm/i915/display/intel_fdi.c

397

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

398

intel_de_read(display, FDI_RX_CTL(PIPE_B)) &

drivers/gpu/drm/i915/display/intel_fdi.c

400

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

401

intel_de_read(display, FDI_RX_CTL(PIPE_C)) &

drivers/gpu/drm/i915/display/intel_fdi.c

408

drm_dbg_kms(display->drm, "%sabling fdi C rx\n",

drivers/gpu/drm/i915/display/intel_fdi.c

410

intel_de_write(display, SOUTH_CHICKEN1, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

411

intel_de_posting_read(display, SOUTH_CHICKEN1);

drivers/gpu/drm/i915/display/intel_fdi.c

416

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

42

cur_state = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_fdi.c

424

cpt_set_fdi_bc_bifurcation(display, false);

drivers/gpu/drm/i915/display/intel_fdi.c

426

cpt_set_fdi_bc_bifurcation(display, true);

drivers/gpu/drm/i915/display/intel_fdi.c

43

TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

430

cpt_set_fdi_bc_bifurcation(display, true);

drivers/gpu/drm/i915/display/intel_fdi.c

440

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

447

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

448

if (display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_fdi.c

45

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

455

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

458

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

459

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_fdi.c

466

intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

469

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

47

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_fdi.c

473

if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_fdi.c

474

intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

481

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

490

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

491

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

drivers/gpu/drm/i915/display/intel_fdi.c

494

assert_transcoder_enabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_fdi.c

499

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

502

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

503

intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

508

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

513

intel_de_write(display, reg, temp | FDI_TX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

516

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

519

intel_de_write(display, reg, temp | FDI_RX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

52

void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

521

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

525

intel_de_write(display, FDI_RX_CHICKEN(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

527

intel_de_write(display, FDI_RX_CHICKEN(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

532

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

533

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

drivers/gpu/drm/i915/display/intel_fdi.c

536

drm_dbg_kms(display->drm, "FDI train 1 done.\n");

drivers/gpu/drm/i915/display/intel_fdi.c

537

intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK);

drivers/gpu/drm/i915/display/intel_fdi.c

54

assert_fdi_tx(display, pipe, true);

drivers/gpu/drm/i915/display/intel_fdi.c

542

drm_err(display->drm, "FDI train 1 fail!\n");

drivers/gpu/drm/i915/display/intel_fdi.c

545

intel_de_rmw(display, FDI_TX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

547

intel_de_rmw(display, FDI_RX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

549

intel_de_posting_read(display, FDI_RX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

554

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

555

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

drivers/gpu/drm/i915/display/intel_fdi.c

558

intel_de_write(display, reg,

drivers/gpu/drm/i915/display/intel_fdi.c

560

drm_dbg_kms(display->drm, "FDI train 2 done.\n");

drivers/gpu/drm/i915/display/intel_fdi.c

565

drm_err(display->drm, "FDI train 2 fail!\n");

drivers/gpu/drm/i915/display/intel_fdi.c

567

drm_dbg_kms(display->drm, "FDI train done\n");

drivers/gpu/drm/i915/display/intel_fdi.c

57

void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

582

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

59

assert_fdi_tx(display, pipe, false);

drivers/gpu/drm/i915/display/intel_fdi.c

591

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

592

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

drivers/gpu/drm/i915/display/intel_fdi.c

597

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

600

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

602

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

607

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

615

intel_de_write(display, reg, temp | FDI_TX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

617

intel_de_write(display, FDI_RX_MISC(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

62

static void assert_fdi_rx(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fdi.c

621

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

622

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_fdi.c

629

intel_de_write(display, reg, temp | FDI_RX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

631

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

635

intel_de_rmw(display, FDI_TX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

637

intel_de_posting_read(display, FDI_TX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

642

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

643

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

drivers/gpu/drm/i915/display/intel_fdi.c

645

intel_de_write(display, reg,

drivers/gpu/drm/i915/display/intel_fdi.c

647

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

657

drm_err(display->drm, "FDI train 1 fail!\n");

drivers/gpu/drm/i915/display/intel_fdi.c

661

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

664

if (display->platform.sandybridge) {

drivers/gpu/drm/i915/display/intel_fdi.c

669

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

67

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

672

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

673

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_fdi.c

68

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/intel_fdi.c

680

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

682

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

686

intel_de_rmw(display, FDI_TX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

688

intel_de_posting_read(display, FDI_TX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

693

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

694

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

drivers/gpu/drm/i915/display/intel_fdi.c

696

intel_de_write(display, reg,

drivers/gpu/drm/i915/display/intel_fdi.c

698

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

708

drm_err(display->drm, "FDI train 2 fail!\n");

drivers/gpu/drm/i915/display/intel_fdi.c

710

drm_dbg_kms(display->drm, "FDI train done.\n");

drivers/gpu/drm/i915/display/intel_fdi.c

717

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

728

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

729

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

drivers/gpu/drm/i915/display/intel_fdi.c

73

void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

734

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

737

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

739

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

742

drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n",

drivers/gpu/drm/i915/display/intel_fdi.c

743

intel_de_read(display, FDI_RX_IIR(pipe)));

drivers/gpu/drm/i915/display/intel_fdi.c

749

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

75

assert_fdi_rx(display, pipe, true);

drivers/gpu/drm/i915/display/intel_fdi.c

752

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

755

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

759

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_fdi.c

763

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

770

intel_de_write(display, reg, temp | FDI_TX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

772

intel_de_write(display, FDI_RX_MISC(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

776

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

779

intel_de_write(display, reg, temp | FDI_RX_ENABLE);

drivers/gpu/drm/i915/display/intel_fdi.c

78

void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

781

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

786

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

787

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

drivers/gpu/drm/i915/display/intel_fdi.c

790

(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {

drivers/gpu/drm/i915/display/intel_fdi.c

791

intel_de_write(display, reg,

drivers/gpu/drm/i915/display/intel_fdi.c

793

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

80

assert_fdi_rx(display, pipe, false);

drivers/gpu/drm/i915/display/intel_fdi.c

801

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

807

intel_de_rmw(display, FDI_TX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

810

intel_de_rmw(display, FDI_RX_CTL(pipe),

drivers/gpu/drm/i915/display/intel_fdi.c

813

intel_de_posting_read(display, FDI_RX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_fdi.c

818

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

819

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

drivers/gpu/drm/i915/display/intel_fdi.c

822

(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {

drivers/gpu/drm/i915/display/intel_fdi.c

823

intel_de_write(display, reg,

drivers/gpu/drm/i915/display/intel_fdi.c

825

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

83

void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_fdi.c

833

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

838

drm_dbg_kms(display->drm, "FDI train done.\n");

drivers/gpu/drm/i915/display/intel_fdi.c

852

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

867

intel_de_write(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

874

rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |

drivers/gpu/drm/i915/display/intel_fdi.c

877

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

878

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

88

if (display->platform.ironlake)

drivers/gpu/drm/i915/display/intel_fdi.c

883

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

886

drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);

drivers/gpu/drm/i915/display/intel_fdi.c

893

intel_de_write(display, DP_TP_CTL(PORT_E),

drivers/gpu/drm/i915/display/intel_fdi.c

903

intel_de_write(display, DDI_BUF_CTL(PORT_E),

drivers/gpu/drm/i915/display/intel_fdi.c

907

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

drivers/gpu/drm/i915/display/intel_fdi.c

912

intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));

drivers/gpu/drm/i915/display/intel_fdi.c

916

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

917

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

92

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_fdi.c

923

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

925

intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

930

temp = intel_de_read(display, DP_TP_STATUS(PORT_E));

drivers/gpu/drm/i915/display/intel_fdi.c

932

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_fdi.c

942

drm_err(display->drm, "FDI link training failed!\n");

drivers/gpu/drm/i915/display/intel_fdi.c

947

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

drivers/gpu/drm/i915/display/intel_fdi.c

948

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

95

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

950

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

951

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

drivers/gpu/drm/i915/display/intel_fdi.c

954

intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

955

intel_de_posting_read(display, DP_TP_CTL(PORT_E));

drivers/gpu/drm/i915/display/intel_fdi.c

957

intel_wait_ddi_buf_idle(display, PORT_E);

drivers/gpu/drm/i915/display/intel_fdi.c

96

INTEL_DISPLAY_STATE_WARN(display, !cur_state,

drivers/gpu/drm/i915/display/intel_fdi.c

960

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

963

intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));

drivers/gpu/drm/i915/display/intel_fdi.c

967

intel_de_write(display, DP_TP_CTL(PORT_E),

drivers/gpu/drm/i915/display/intel_fdi.c

976

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_fdi.c

984

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

985

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

986

intel_wait_ddi_buf_idle(display, PORT_E);

drivers/gpu/drm/i915/display/intel_fdi.c

988

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

drivers/gpu/drm/i915/display/intel_fdi.c

991

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

992

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_fdi.c

997

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.h

21

int intel_fdi_link_freq(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fdi.h

31

void intel_fdi_init_hook(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fdi.h

35

void intel_fdi_pll_freq_update(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fdi.h

40

void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fdi.h

41

void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fdi.h

42

void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fdi.h

43

void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fdi.h

44

void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fdi.h

45

void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fdi.h

46

void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

100

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

102

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

104

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

108

static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

110

u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

115

intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

118

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

125

static void read_underrun_dbg_pkgc(struct intel_display *display, bool log)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

127

u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

136

intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

139

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

143

static void read_underrun_dbg_info(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

147

if (!HAS_UNDERRUN_DBG_INFO(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

150

read_underrun_dbg1(display, pipe, log);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

151

read_underrun_dbg2(display, pipe, log);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

152

intel_fbc_read_underrun_dbg_info(display, pipe, log);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

153

read_underrun_dbg_pkgc(display, log);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

156

static bool ivb_can_enable_err_int(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

161

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

163

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

164

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

173

static bool cpt_can_enable_serr_int(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

178

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

180

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

181

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

192

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

193

i915_reg_t reg = PIPESTAT(display, crtc->pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

196

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

198

if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

201

enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

202

intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

203

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

205

trace_intel_cpu_fifo_underrun(display, crtc->pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

206

drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

209

static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

213

i915_reg_t reg = PIPESTAT(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

215

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

218

u32 enable_mask = i915_pipestat_enable_mask(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

220

intel_de_write(display, reg,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

222

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

224

if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

225

drm_err(display->drm, "pipe %c underrun\n",

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

230

static void ilk_set_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

237

ilk_enable_display_irq(display, bit);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

239

ilk_disable_display_irq(display, bit);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

244

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

246

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

248

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

253

intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

254

intel_de_posting_read(display, GEN7_ERR_INT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

256

trace_intel_cpu_fifo_underrun(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

257

drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

260

static void ivb_set_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

265

intel_de_write(display, GEN7_ERR_INT,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

268

if (!ivb_can_enable_err_int(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

271

ilk_enable_display_irq(display, DE_ERR_INT_IVB);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

273

ilk_disable_display_irq(display, DE_ERR_INT_IVB);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

276

intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

277

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

284

static void bdw_set_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

288

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

290

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

293

static void ibx_set_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

301

ibx_enable_display_interrupt(display, bit);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

303

ibx_disable_display_interrupt(display, bit);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

308

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

310

u32 serr_int = intel_de_read(display, SERR_INT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

312

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

317

intel_de_write(display, SERR_INT,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

319

intel_de_posting_read(display, SERR_INT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

321

trace_intel_pch_fifo_underrun(display, pch_transcoder);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

322

drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

326

static void cpt_set_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

331

intel_de_write(display, SERR_INT,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

334

if (!cpt_can_enable_serr_int(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

337

ibx_enable_display_interrupt(display, SDE_ERROR_CPT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

339

ibx_disable_display_interrupt(display, SDE_ERROR_CPT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

341

if (old && intel_de_read(display, SERR_INT) &

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

343

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

350

static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

353

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

356

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

370

read_underrun_dbg_info(display, pipe, false);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

372

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

373

i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

374

else if (display->platform.ironlake || display->platform.sandybridge)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

375

ilk_set_fifo_underrun_reporting(display, pipe, enable);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

376

else if (DISPLAY_VER(display) == 7)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

377

ivb_set_fifo_underrun_reporting(display, pipe, enable, old);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

378

else if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

379

bdw_set_fifo_underrun_reporting(display, pipe, enable);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

400

bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

406

spin_lock_irqsave(&display->irq.lock, flags);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

407

ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

408

spin_unlock_irqrestore(&display->irq.lock, flags);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

427

bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

431

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

444

spin_lock_irqsave(&display->irq.lock, flags);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

449

if (HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

450

ibx_set_fifo_underrun_reporting(display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

454

cpt_set_fifo_underrun_reporting(display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

458

spin_unlock_irqrestore(&display->irq.lock, flags);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

471

void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

474

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

481

if (HAS_GMCH(display) &&

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

485

if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

486

trace_intel_cpu_fifo_underrun(display, pipe);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

488

drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

490

read_underrun_dbg_info(display, pipe, true);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

493

intel_fbc_handle_fifo_underrun_irq(display);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

505

void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

508

if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

510

trace_intel_pch_fifo_underrun(display, pch_transcoder);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

511

drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

525

void intel_check_cpu_fifo_underruns(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

529

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

531

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

535

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

537

else if (DISPLAY_VER(display) == 7)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

541

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

552

void intel_check_pch_fifo_underruns(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

556

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

558

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

562

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

566

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

569

void intel_init_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

584

if (intel_has_pch_trancoder(display, crtc->pipe))

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

64

static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe,

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

80

drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n",

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

83

drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

86

static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

88

u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

93

intel_de_write(display, UNDERRUN_DBG1(pipe), val);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

98

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

15

void intel_init_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

17

bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

19

bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

22

void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

24

void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

26

void intel_check_cpu_fifo_underruns(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fifo_underrun.h

27

void intel_check_pch_fifo_underruns(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_flipq.c

107

drm_dbg_kms(display->drm, "[CRTC:%d:%s] FQ %d: start 0x%x\n",

drivers/gpu/drm/i915/display/intel_flipq.c

113

bool intel_flipq_supported(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

115

if (!display->params.enable_flipq)

drivers/gpu/drm/i915/display/intel_flipq.c

118

if (!display->dmc.dmc)

drivers/gpu/drm/i915/display/intel_flipq.c

121

if (DISPLAY_VER(display) == 20)

drivers/gpu/drm/i915/display/intel_flipq.c

125

return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display);

drivers/gpu/drm/i915/display/intel_flipq.c

128

void intel_flipq_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

132

intel_dmc_wait_fw_load(display);

drivers/gpu/drm/i915/display/intel_flipq.c

134

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/intel_flipq.c

138

static int cdclk_factor(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

140

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_flipq.c

146

int intel_flipq_exec_time_us(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

149

DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) +

drivers/gpu/drm/i915/display/intel_flipq.c

150

display->sagv.block_time_us;

drivers/gpu/drm/i915/display/intel_flipq.c

153

static int intel_flipq_preempt_timeout_ms(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

155

return DIV_ROUND_UP(intel_flipq_exec_time_us(display), 1000);

drivers/gpu/drm/i915/display/intel_flipq.c

160

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

162

intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),

drivers/gpu/drm/i915/display/intel_flipq.c

166

intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_flipq.c

169

intel_flipq_preempt_timeout_ms(display)))

drivers/gpu/drm/i915/display/intel_flipq.c

170

drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt timeout\n",

drivers/gpu/drm/i915/display/intel_flipq.c

176

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

178

return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));

drivers/gpu/drm/i915/display/intel_flipq.c

183

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

185

intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),

drivers/gpu/drm/i915/display/intel_flipq.c

195

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

197

intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);

drivers/gpu/drm/i915/display/intel_flipq.c

202

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

205

intel_flipq_exec_time_us(display));

drivers/gpu/drm/i915/display/intel_flipq.c

211

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

215

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_flipq.c

221

intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));

drivers/gpu/drm/i915/display/intel_flipq.c

226

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_flipq.c

229

intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),

drivers/gpu/drm/i915/display/intel_flipq.c

230

intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));

drivers/gpu/drm/i915/display/intel_flipq.c

232

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_flipq.c

237

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_flipq.c

240

intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));

drivers/gpu/drm/i915/display/intel_flipq.c

242

tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));

drivers/gpu/drm/i915/display/intel_flipq.c

244

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_flipq.c

254

void intel_flipq_reset(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_flipq.c

256

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_flipq.c

259

intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

261

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

262

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

267

intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

268

intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

273

intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

276

static enum pipedmc_event_id flipq_event_id(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

278

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_flipq.c

286

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

292

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_flipq.c

296

intel_de_write(display, PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr),

drivers/gpu/drm/i915/display/intel_flipq.c

298

intel_de_write(display, PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr),

drivers/gpu/drm/i915/display/intel_flipq.c

302

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),

drivers/gpu/drm/i915/display/intel_flipq.c

304

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),

drivers/gpu/drm/i915/display/intel_flipq.c

308

intel_pipedmc_enable_event(crtc, flipq_event_id(display));

drivers/gpu/drm/i915/display/intel_flipq.c

310

intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);

drivers/gpu/drm/i915/display/intel_flipq.c

315

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

320

intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

322

intel_pipedmc_disable_event(crtc, flipq_event_id(display));

drivers/gpu/drm/i915/display/intel_flipq.c

324

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

325

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_flipq.c

331

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

337

return !drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_flipq.c

344

static void intel_flipq_write(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_flipq.c

347

intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail *

drivers/gpu/drm/i915/display/intel_flipq.c

351

static void lnl_flipq_add(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_flipq.c

361

intel_flipq_write(display, flipq, pts, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

362

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

drivers/gpu/drm/i915/display/intel_flipq.c

363

intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT |

drivers/gpu/drm/i915/display/intel_flipq.c

366

intel_flipq_write(display, flipq, 0, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

367

intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */

drivers/gpu/drm/i915/display/intel_flipq.c

368

intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */

drivers/gpu/drm/i915/display/intel_flipq.c

373

intel_flipq_write(display, flipq, pts, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

374

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

drivers/gpu/drm/i915/display/intel_flipq.c

375

intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT |

drivers/gpu/drm/i915/display/intel_flipq.c

378

intel_flipq_write(display, flipq, 0, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

386

static void ptl_flipq_add(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_flipq.c

396

intel_flipq_write(display, flipq, pts, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

397

intel_flipq_write(display, flipq, 0, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

398

intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT |

drivers/gpu/drm/i915/display/intel_flipq.c

401

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

drivers/gpu/drm/i915/display/intel_flipq.c

402

intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */

drivers/gpu/drm/i915/display/intel_flipq.c

403

intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */

drivers/gpu/drm/i915/display/intel_flipq.c

408

intel_flipq_write(display, flipq, pts, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

409

intel_flipq_write(display, flipq, 0, i++);

drivers/gpu/drm/i915/display/intel_flipq.c

410

intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT |

drivers/gpu/drm/i915/display/intel_flipq.c

413

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

drivers/gpu/drm/i915/display/intel_flipq.c

427

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

433

pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));

drivers/gpu/drm/i915/display/intel_flipq.c

437

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_flipq.c

438

ptl_flipq_add(display, flipq, pts, dsb_id, dsb);

drivers/gpu/drm/i915/display/intel_flipq.c

440

lnl_flipq_add(display, flipq, pts, dsb_id, dsb);

drivers/gpu/drm/i915/display/intel_flipq.c

451

static bool need_dmc_halt_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_flipq.c

453

return DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_flipq.c

454

(display->platform.pantherlake &&

drivers/gpu/drm/i915/display/intel_flipq.c

455

IS_DISPLAY_STEP(display, STEP_A0, STEP_B0));

drivers/gpu/drm/i915/display/intel_flipq.c

460

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

462

if (need_dmc_halt_wa(display))

drivers/gpu/drm/i915/display/intel_flipq.c

468

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

470

if (need_dmc_halt_wa(display))

drivers/gpu/drm/i915/display/intel_flipq.c

98

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_flipq.h

19

bool intel_flipq_supported(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_flipq.h

20

void intel_flipq_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_flipq.h

21

void intel_flipq_reset(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_flipq.h

31

int intel_flipq_exec_time_us(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

100

intel_psr_flush(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

101

intel_fbc_flush(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

115

void intel_frontbuffer_flip(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_frontbuffer.c

118

spin_lock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

120

display->fb_tracking.busy_bits &= ~frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

121

spin_unlock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

123

frontbuffer_flush(display, frontbuffer_bits, ORIGIN_FLIP);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

130

struct intel_display *display = front->display;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

133

spin_lock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

134

display->fb_tracking.busy_bits |= frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

135

spin_unlock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

138

trace_intel_frontbuffer_invalidate(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

141

intel_psr_invalidate(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

142

intel_drrs_invalidate(display, frontbuffer_bits);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

143

intel_fbc_invalidate(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

150

struct intel_display *display = front->display;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

156

spin_lock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

158

frontbuffer_bits &= display->fb_tracking.busy_bits;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

159

display->fb_tracking.busy_bits &= ~frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

160

spin_unlock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

164

frontbuffer_flush(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

200

front->display = to_intel_display(drm);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

207

drm_WARN_ON(front->display->drm, atomic_read(&front->bits));

drivers/gpu/drm/i915/display/intel_frontbuffer.c

246

drm_WARN_ON(old->display->drm,

drivers/gpu/drm/i915/display/intel_frontbuffer.c

252

drm_WARN_ON(new->display->drm,

drivers/gpu/drm/i915/display/intel_frontbuffer.c

83

static void frontbuffer_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_frontbuffer.c

88

spin_lock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

89

frontbuffer_bits &= ~display->fb_tracking.busy_bits;

drivers/gpu/drm/i915/display/intel_frontbuffer.c

90

spin_unlock(&display->fb_tracking.lock);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

95

trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

98

intel_td_flush(display);

drivers/gpu/drm/i915/display/intel_frontbuffer.c

99

intel_drrs_flush(display, frontbuffer_bits);

drivers/gpu/drm/i915/display/intel_frontbuffer.h

44

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_frontbuffer.h

66

void intel_frontbuffer_flip(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_global_state.c

111

void intel_atomic_global_obj_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_global_state.c

124

list_add_tail(&obj->head, &display->global.obj_list);

drivers/gpu/drm/i915/display/intel_global_state.c

127

void intel_atomic_global_obj_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_global_state.c

131

list_for_each_entry_safe(obj, next, &display->global.obj_list, head) {

drivers/gpu/drm/i915/display/intel_global_state.c

134

drm_WARN_ON(display->drm, kref_read(&obj->state->ref) != 1);

drivers/gpu/drm/i915/display/intel_global_state.c

139

static void assert_global_state_write_locked(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_global_state.c

143

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/intel_global_state.c

162

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_global_state.c

166

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_global_state.c

171

drm_WARN(display->drm, 1, "Global state not read locked\n");

drivers/gpu/drm/i915/display/intel_global_state.c

178

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_global_state.c

220

drm_dbg_atomic(display->drm, "Added new global object %p state %p to %p\n",

drivers/gpu/drm/i915/display/intel_global_state.c

254

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_global_state.c

261

drm_WARN_ON(display->drm, obj->state != old_obj_state);

drivers/gpu/drm/i915/display/intel_global_state.c

270

assert_global_state_write_locked(display);

drivers/gpu/drm/i915/display/intel_global_state.c

301

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_global_state.c

304

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_global_state.c

334

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_global_state.c

337

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/intel_global_state.c

380

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_global_state.c

394

drm_err(display->drm, "global state timed out\n");

drivers/gpu/drm/i915/display/intel_global_state.h

38

void intel_atomic_global_obj_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_global_state.h

42

void intel_atomic_global_obj_cleanup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_gmbus.c

1004

mutex_unlock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

1014

void intel_gmbus_teardown(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

1018

for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {

drivers/gpu/drm/i915/display/intel_gmbus.c

1021

bus = display->gmbus.bus[pin];

drivers/gpu/drm/i915/display/intel_gmbus.c

1028

display->gmbus.bus[pin] = NULL;

drivers/gpu/drm/i915/display/intel_gmbus.c

1032

void intel_gmbus_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

1034

wake_up_all(&display->gmbus.wait_queue);

drivers/gpu/drm/i915/display/intel_gmbus.c

155

static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

161

if (INTEL_PCH_TYPE(display) >= PCH_MTL) {

drivers/gpu/drm/i915/display/intel_gmbus.c

164

} else if (INTEL_PCH_TYPE(display) >= PCH_DG2) {

drivers/gpu/drm/i915/display/intel_gmbus.c

167

} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {

drivers/gpu/drm/i915/display/intel_gmbus.c

170

} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {

drivers/gpu/drm/i915/display/intel_gmbus.c

173

} else if (HAS_PCH_CNP(display)) {

drivers/gpu/drm/i915/display/intel_gmbus.c

176

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_gmbus.c

179

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_gmbus.c

182

} else if (display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_gmbus.c

196

bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)

drivers/gpu/drm/i915/display/intel_gmbus.c

198

return get_gmbus_pin(display, pin);

drivers/gpu/drm/i915/display/intel_gmbus.c

212

intel_gmbus_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

214

intel_de_write(display, GMBUS0(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

215

intel_de_write(display, GMBUS4(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

218

static void pnv_gmbus_clock_gating(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

222

intel_de_rmw(display, DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_gmbus.c

227

static void pch_gmbus_clock_gating(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

230

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_gmbus.c

235

static void bxt_gmbus_clock_gating(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

238

intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,

drivers/gpu/drm/i915/display/intel_gmbus.c

244

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

247

if (display->platform.i830 || display->platform.i845g)

drivers/gpu/drm/i915/display/intel_gmbus.c

254

if (intel_display_wa(display, 16025573575))

drivers/gpu/drm/i915/display/intel_gmbus.c

258

return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits;

drivers/gpu/drm/i915/display/intel_gmbus.c

264

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

267

intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);

drivers/gpu/drm/i915/display/intel_gmbus.c

268

intel_de_write_notrace(display, bus->gpio_reg, reserved);

drivers/gpu/drm/i915/display/intel_gmbus.c

270

return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;

drivers/gpu/drm/i915/display/intel_gmbus.c

276

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

279

intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);

drivers/gpu/drm/i915/display/intel_gmbus.c

280

intel_de_write_notrace(display, bus->gpio_reg, reserved);

drivers/gpu/drm/i915/display/intel_gmbus.c

282

return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;

drivers/gpu/drm/i915/display/intel_gmbus.c

288

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

298

intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);

drivers/gpu/drm/i915/display/intel_gmbus.c

299

intel_de_posting_read(display, bus->gpio_reg);

drivers/gpu/drm/i915/display/intel_gmbus.c

305

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

315

intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);

drivers/gpu/drm/i915/display/intel_gmbus.c

316

intel_de_posting_read(display, bus->gpio_reg);

drivers/gpu/drm/i915/display/intel_gmbus.c

322

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

323

u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);

drivers/gpu/drm/i915/display/intel_gmbus.c

331

intel_de_write_notrace(display, bus->gpio_reg, reg_val);

drivers/gpu/drm/i915/display/intel_gmbus.c

332

intel_de_posting_read(display, bus->gpio_reg);

drivers/gpu/drm/i915/display/intel_gmbus.c

339

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

341

intel_gmbus_reset(display);

drivers/gpu/drm/i915/display/intel_gmbus.c

343

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_gmbus.c

344

pnv_gmbus_clock_gating(display, false);

drivers/gpu/drm/i915/display/intel_gmbus.c

346

if (intel_display_wa(display, 16025573575))

drivers/gpu/drm/i915/display/intel_gmbus.c

359

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

364

if (display->platform.pineview)

drivers/gpu/drm/i915/display/intel_gmbus.c

365

pnv_gmbus_clock_gating(display, true);

drivers/gpu/drm/i915/display/intel_gmbus.c

367

if (intel_display_wa(display, 16025573575))

drivers/gpu/drm/i915/display/intel_gmbus.c

391

static bool has_gmbus_irq(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

397

return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display);

drivers/gpu/drm/i915/display/intel_gmbus.c

400

static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)

drivers/gpu/drm/i915/display/intel_gmbus.c

410

if (!has_gmbus_irq(display))

drivers/gpu/drm/i915/display/intel_gmbus.c

413

add_wait_queue(&display->gmbus.wait_queue, &wait);

drivers/gpu/drm/i915/display/intel_gmbus.c

414

intel_de_write_fw(display, GMBUS4(display), irq_en);

drivers/gpu/drm/i915/display/intel_gmbus.c

418

ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),

drivers/gpu/drm/i915/display/intel_gmbus.c

422

ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),

drivers/gpu/drm/i915/display/intel_gmbus.c

426

intel_de_write_fw(display, GMBUS4(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

427

remove_wait_queue(&display->gmbus.wait_queue, &wait);

drivers/gpu/drm/i915/display/intel_gmbus.c

436

gmbus_wait_idle(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

444

if (has_gmbus_irq(display))

drivers/gpu/drm/i915/display/intel_gmbus.c

447

add_wait_queue(&display->gmbus.wait_queue, &wait);

drivers/gpu/drm/i915/display/intel_gmbus.c

448

intel_de_write_fw(display, GMBUS4(display), irq_enable);

drivers/gpu/drm/i915/display/intel_gmbus.c

450

ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);

drivers/gpu/drm/i915/display/intel_gmbus.c

452

intel_de_write_fw(display, GMBUS4(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

453

remove_wait_queue(&display->gmbus.wait_queue, &wait);

drivers/gpu/drm/i915/display/intel_gmbus.c

458

static unsigned int gmbus_max_xfer_size(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

460

return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :

drivers/gpu/drm/i915/display/intel_gmbus.c

465

gmbus_xfer_read_chunk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

470

bool burst_read = len > gmbus_max_xfer_size(display);

drivers/gpu/drm/i915/display/intel_gmbus.c

483

intel_de_write_fw(display, GMBUS0(display),

drivers/gpu/drm/i915/display/intel_gmbus.c

487

intel_de_write_fw(display, GMBUS1(display),

drivers/gpu/drm/i915/display/intel_gmbus.c

493

ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);

drivers/gpu/drm/i915/display/intel_gmbus.c

497

val = intel_de_read_fw(display, GMBUS3(display));

drivers/gpu/drm/i915/display/intel_gmbus.c

510

intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);

drivers/gpu/drm/i915/display/intel_gmbus.c

527

gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,

drivers/gpu/drm/i915/display/intel_gmbus.c

536

if (HAS_GMBUS_BURST_READ(display))

drivers/gpu/drm/i915/display/intel_gmbus.c

539

len = min(rx_size, gmbus_max_xfer_size(display));

drivers/gpu/drm/i915/display/intel_gmbus.c

54

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_gmbus.c

541

ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,

drivers/gpu/drm/i915/display/intel_gmbus.c

554

gmbus_xfer_write_chunk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

567

intel_de_write_fw(display, GMBUS3(display), val);

drivers/gpu/drm/i915/display/intel_gmbus.c

568

intel_de_write_fw(display, GMBUS1(display),

drivers/gpu/drm/i915/display/intel_gmbus.c

578

intel_de_write_fw(display, GMBUS3(display), val);

drivers/gpu/drm/i915/display/intel_gmbus.c

580

ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);

drivers/gpu/drm/i915/display/intel_gmbus.c

589

gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,

drivers/gpu/drm/i915/display/intel_gmbus.c

598

len = min(tx_size, gmbus_max_xfer_size(display));

drivers/gpu/drm/i915/display/intel_gmbus.c

600

ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,

drivers/gpu/drm/i915/display/intel_gmbus.c

627

gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,

drivers/gpu/drm/i915/display/intel_gmbus.c

643

intel_de_write_fw(display, GMBUS5(display), gmbus5);

drivers/gpu/drm/i915/display/intel_gmbus.c

646

ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,

drivers/gpu/drm/i915/display/intel_gmbus.c

649

ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);

drivers/gpu/drm/i915/display/intel_gmbus.c

653

intel_de_write_fw(display, GMBUS5(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

663

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

668

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_gmbus.c

669

bxt_gmbus_clock_gating(display, false);

drivers/gpu/drm/i915/display/intel_gmbus.c

670

else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))

drivers/gpu/drm/i915/display/intel_gmbus.c

671

pch_gmbus_clock_gating(display, false);

drivers/gpu/drm/i915/display/intel_gmbus.c

674

intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);

drivers/gpu/drm/i915/display/intel_gmbus.c

679

ret = gmbus_index_xfer(display, &msgs[i],

drivers/gpu/drm/i915/display/intel_gmbus.c

683

ret = gmbus_xfer_read(display, &msgs[i],

drivers/gpu/drm/i915/display/intel_gmbus.c

686

ret = gmbus_xfer_write(display, &msgs[i], 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

690

ret = gmbus_wait(display,

drivers/gpu/drm/i915/display/intel_gmbus.c

702

intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);

drivers/gpu/drm/i915/display/intel_gmbus.c

708

if (gmbus_wait_idle(display)) {

drivers/gpu/drm/i915/display/intel_gmbus.c

709

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_gmbus.c

714

intel_de_write_fw(display, GMBUS0(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

733

if (gmbus_wait_idle(display)) {

drivers/gpu/drm/i915/display/intel_gmbus.c

734

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_gmbus.c

744

intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);

drivers/gpu/drm/i915/display/intel_gmbus.c

745

intel_de_write_fw(display, GMBUS1(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

746

intel_de_write_fw(display, GMBUS0(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

748

drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",

drivers/gpu/drm/i915/display/intel_gmbus.c

759

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_gmbus.c

768

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_gmbus.c

771

intel_de_write_fw(display, GMBUS0(display), 0);

drivers/gpu/drm/i915/display/intel_gmbus.c

781

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_gmbus.c

782

bxt_gmbus_clock_gating(display, true);

drivers/gpu/drm/i915/display/intel_gmbus.c

783

else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))

drivers/gpu/drm/i915/display/intel_gmbus.c

784

pch_gmbus_clock_gating(display, true);

drivers/gpu/drm/i915/display/intel_gmbus.c

793

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

797

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

drivers/gpu/drm/i915/display/intel_gmbus.c

809

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

drivers/gpu/drm/i915/display/intel_gmbus.c

817

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

837

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

drivers/gpu/drm/i915/display/intel_gmbus.c

838

mutex_lock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

847

mutex_unlock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

848

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

drivers/gpu/drm/i915/display/intel_gmbus.c

871

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

873

mutex_lock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

880

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

882

return mutex_trylock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

889

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

891

mutex_unlock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

904

int intel_gmbus_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gmbus.c

906

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_gmbus.c

910

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_gmbus.c

911

display->gmbus.mmio_base = VLV_DISPLAY_BASE;

drivers/gpu/drm/i915/display/intel_gmbus.c

912

else if (!HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_gmbus.c

917

display->gmbus.mmio_base = PCH_DISPLAY_BASE;

drivers/gpu/drm/i915/display/intel_gmbus.c

919

mutex_init(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

920

init_waitqueue_head(&display->gmbus.wait_queue);

drivers/gpu/drm/i915/display/intel_gmbus.c

922

for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {

drivers/gpu/drm/i915/display/intel_gmbus.c

926

gmbus_pin = get_gmbus_pin(display, pin);

drivers/gpu/drm/i915/display/intel_gmbus.c

942

bus->display = display;

drivers/gpu/drm/i915/display/intel_gmbus.c

957

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_gmbus.c

960

intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));

drivers/gpu/drm/i915/display/intel_gmbus.c

968

display->gmbus.bus[pin] = bus;

drivers/gpu/drm/i915/display/intel_gmbus.c

971

intel_gmbus_reset(display);

drivers/gpu/drm/i915/display/intel_gmbus.c

976

intel_gmbus_teardown(display);

drivers/gpu/drm/i915/display/intel_gmbus.c

981

struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_gmbus.c

984

if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||

drivers/gpu/drm/i915/display/intel_gmbus.c

985

!display->gmbus.bus[pin]))

drivers/gpu/drm/i915/display/intel_gmbus.c

988

return &display->gmbus.bus[pin]->adapter;

drivers/gpu/drm/i915/display/intel_gmbus.c

994

struct intel_display *display = bus->display;

drivers/gpu/drm/i915/display/intel_gmbus.c

996

mutex_lock(&display->gmbus.mutex);

drivers/gpu/drm/i915/display/intel_gmbus.c

999

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_gmbus.h

37

int intel_gmbus_setup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_gmbus.h

38

void intel_gmbus_teardown(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_gmbus.h

39

bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);

drivers/gpu/drm/i915/display/intel_gmbus.h

43

intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);

drivers/gpu/drm/i915/display/intel_gmbus.h

46

void intel_gmbus_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_gmbus.h

48

void intel_gmbus_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_gvt_api.c

12

u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_gvt_api.c

14

return INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe);

drivers/gpu/drm/i915/display/intel_gvt_api.c

18

u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans)

drivers/gpu/drm/i915/display/intel_gvt_api.c

20

return INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans);

drivers/gpu/drm/i915/display/intel_gvt_api.c

24

u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_gvt_api.c

26

return INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe);

drivers/gpu/drm/i915/display/intel_gvt_api.c

30

u32 intel_display_device_mmio_base(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_gvt_api.c

32

return DISPLAY_MMIO_BASE(display);

drivers/gpu/drm/i915/display/intel_gvt_api.c

36

bool intel_display_device_pipe_valid(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_gvt_api.c

41

return DISPLAY_RUNTIME_INFO(display)->pipe_mask & BIT(pipe);

drivers/gpu/drm/i915/display/intel_gvt_api.h

15

u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_gvt_api.h

16

u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans);

drivers/gpu/drm/i915/display/intel_gvt_api.h

17

u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_gvt_api.h

18

u32 intel_display_device_mmio_base(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_gvt_api.h

19

bool intel_display_device_pipe_valid(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_hdcp.c

1002

drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1014

intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

1015

if (intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

1016

HDCP_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

1018

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1023

repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder,

drivers/gpu/drm/i915/display/intel_hdcp.c

1025

intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

1029

drm_err(display->drm, "Failed to disable HDCP signalling\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1033

drm_dbg_kms(display->drm, "HDCP is disabled\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1039

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1043

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1046

if (!hdcp_key_loadable(display)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

1047

drm_err(display->drm, "HDCP key Load is not possible\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1052

ret = intel_hdcp_load_keys(display);

drivers/gpu/drm/i915/display/intel_hdcp.c

1055

intel_hdcp_clear_keys(display);

drivers/gpu/drm/i915/display/intel_hdcp.c

1058

drm_err(display->drm, "Could not load HDCP keys, (%d)\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1073

drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1079

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1092

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1096

drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex));

drivers/gpu/drm/i915/display/intel_hdcp.c

1101

drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex));

drivers/gpu/drm/i915/display/intel_hdcp.c

1104

if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0))

drivers/gpu/drm/i915/display/intel_hdcp.c

1113

if (!queue_work(display->wq.unordered, &hdcp->prop_work))

drivers/gpu/drm/i915/display/intel_hdcp.c

1121

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1140

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1141

!intel_hdcp_in_use(display, cpu_transcoder, port))) {

drivers/gpu/drm/i915/display/intel_hdcp.c

1142

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1145

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)));

drivers/gpu/drm/i915/display/intel_hdcp.c

115

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_hdcp.c

1161

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1167

drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1176

drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1194

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1196

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

drivers/gpu/drm/i915/display/intel_hdcp.c

1209

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1214

bool is_hdcp_supported(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_hdcp.c

1216

return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&

drivers/gpu/drm/i915/display/intel_hdcp.c

1217

(DISPLAY_VER(display) >= 12 || port < PORT_E);

drivers/gpu/drm/i915/display/intel_hdcp.c

1224

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1230

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1231

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1234

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1240

drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1242

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1254

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1260

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1261

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1264

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1272

drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1274

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1282

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1288

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1289

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1292

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1298

drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1299

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1308

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

131

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hdcp.c

1314

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1315

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1318

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1324

drm_dbg_kms(display->drm, "Store pairing info failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1326

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1335

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1341

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1342

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1345

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1351

drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1353

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1362

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1368

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1369

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1372

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1378

drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1380

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1388

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1394

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1395

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1398

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1404

drm_dbg_kms(display->drm, "Get session key failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1406

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1417

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1423

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1424

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1427

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1436

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1438

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1447

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1453

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1454

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1457

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1463

drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1464

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1471

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1477

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1478

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1481

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1487

drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1489

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1496

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1501

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1502

arbiter = display->hdcp.arbiter;

drivers/gpu/drm/i915/display/intel_hdcp.c

1505

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1511

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

1524

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

153

if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0))

drivers/gpu/drm/i915/display/intel_hdcp.c

1587

drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1593

if (drm_hdcp_check_ksvs_revoked(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1596

drm_err(display->drm, "Receiver ID is revoked\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1747

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1768

drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1781

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1791

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1798

drm_dbg_kms(display->drm, "Seq_num_v roll over.\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1804

if (drm_hdcp_check_ksvs_revoked(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1807

drm_err(display->drm, "Revoked receiver ID(s) is in list\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1828

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1835

drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1841

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1848

drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret);

drivers/gpu/drm/i915/display/intel_hdcp.c

1863

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1874

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1882

if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1884

drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1893

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1897

drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

1905

drm_dbg_kms(display->drm, "Port deauth failed.\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

1915

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1922

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1923

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1929

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1936

if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1939

intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

1942

ret = intel_de_wait_for_set_ms(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

1943

HDCP2_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

1953

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

1960

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1961

!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1964

intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

1967

ret = intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

1968

HDCP2_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

1972

drm_dbg_kms(display->drm, "Disable Encryption Timedout");

drivers/gpu/drm/i915/display/intel_hdcp.c

1978

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

1991

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2004

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2009

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

201

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdcp.c

2020

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2029

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2037

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2046

drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2051

drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2054

drm_dbg_kms(display->drm, "Port deauth failed.\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2065

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2068

drm_dbg_kms(display->drm, "Port deauth failed.\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2081

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2085

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2093

drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2098

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2109

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2115

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2121

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2125

drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

213

drm_dbg_kms(display->drm, "Bksv is invalid\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2135

drm_dbg_kms(display->drm, "Port deauth failed.\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2147

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2165

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2166

!intel_hdcp2_in_use(display, cpu_transcoder, port))) {

drivers/gpu/drm/i915/display/intel_hdcp.c

2167

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2169

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)));

drivers/gpu/drm/i915/display/intel_hdcp.c

2192

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2203

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2208

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2215

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2237

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2243

queue_delayed_work(display->wq.unordered, &hdcp->check_work,

drivers/gpu/drm/i915/display/intel_hdcp.c

2246

queue_delayed_work(display->wq.unordered, &hdcp->check_work,

drivers/gpu/drm/i915/display/intel_hdcp.c

2253

struct intel_display *display = to_intel_display(drv_kdev);

drivers/gpu/drm/i915/display/intel_hdcp.c

2255

drm_dbg(display->drm, "I915 HDCP comp bind\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2256

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2257

display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data;

drivers/gpu/drm/i915/display/intel_hdcp.c

2258

display->hdcp.arbiter->hdcp_dev = mei_kdev;

drivers/gpu/drm/i915/display/intel_hdcp.c

2259

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2267

struct intel_display *display = to_intel_display(drv_kdev);

drivers/gpu/drm/i915/display/intel_hdcp.c

2269

drm_dbg(display->drm, "I915 HDCP comp unbind\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2270

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2271

display->hdcp.arbiter = NULL;

drivers/gpu/drm/i915/display/intel_hdcp.c

2272

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2306

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2310

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_hdcp.c

2331

INTEL_NUM_PIPES(display));

drivers/gpu/drm/i915/display/intel_hdcp.c

2333

drm_err(display->drm, "Out of Memory\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2340

static bool is_hdcp2_supported(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp.c

2342

if (USE_HDCP_GSC(display))

drivers/gpu/drm/i915/display/intel_hdcp.c

2348

return DISPLAY_VER(display) >= 10 ||

drivers/gpu/drm/i915/display/intel_hdcp.c

2349

display->platform.kabylake ||

drivers/gpu/drm/i915/display/intel_hdcp.c

2350

display->platform.coffeelake ||

drivers/gpu/drm/i915/display/intel_hdcp.c

2351

display->platform.cometlake;

drivers/gpu/drm/i915/display/intel_hdcp.c

2354

void intel_hdcp_component_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp.c

2358

if (!is_hdcp2_supported(display))

drivers/gpu/drm/i915/display/intel_hdcp.c

2361

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2362

drm_WARN_ON(display->drm, display->hdcp.comp_added);

drivers/gpu/drm/i915/display/intel_hdcp.c

2364

display->hdcp.comp_added = true;

drivers/gpu/drm/i915/display/intel_hdcp.c

2365

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2366

if (USE_HDCP_GSC(display))

drivers/gpu/drm/i915/display/intel_hdcp.c

2367

ret = intel_hdcp_gsc_init(display);

drivers/gpu/drm/i915/display/intel_hdcp.c

2369

ret = component_add_typed(display->drm->dev, &i915_hdcp_ops,

drivers/gpu/drm/i915/display/intel_hdcp.c

2373

drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

2375

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2376

display->hdcp.comp_added = false;

drivers/gpu/drm/i915/display/intel_hdcp.c

2377

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2386

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2392

drm_dbg_kms(display->drm, "Mei hdcp data init failed\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2403

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2410

if (is_hdcp2_supported(display))

drivers/gpu/drm/i915/display/intel_hdcp.c

2435

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdcp.c

2448

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

2460

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_hdcp.c

2476

drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

2488

queue_delayed_work(display->wq.unordered, &hdcp->check_work,

drivers/gpu/drm/i915/display/intel_hdcp.c

252

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2559

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2586

if (!queue_work(display->wq.unordered, &hdcp->prop_work))

drivers/gpu/drm/i915/display/intel_hdcp.c

260

if (USE_HDCP_GSC(display)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

2604

if (!queue_work(display->wq.unordered, &hdcp->prop_work))

drivers/gpu/drm/i915/display/intel_hdcp.c

261

if (!intel_parent_hdcp_gsc_check_status(display))

drivers/gpu/drm/i915/display/intel_hdcp.c

2623

void intel_hdcp_component_fini(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp.c

2625

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2626

if (!display->hdcp.comp_added) {

drivers/gpu/drm/i915/display/intel_hdcp.c

2627

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2631

display->hdcp.comp_added = false;

drivers/gpu/drm/i915/display/intel_hdcp.c

2632

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2634

if (USE_HDCP_GSC(display))

drivers/gpu/drm/i915/display/intel_hdcp.c

2635

intel_hdcp_gsc_fini(display);

drivers/gpu/drm/i915/display/intel_hdcp.c

2637

component_del(display->drm->dev, &i915_hdcp_ops);

drivers/gpu/drm/i915/display/intel_hdcp.c

266

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

267

if (!display->hdcp.comp_added || !display->hdcp.arbiter) {

drivers/gpu/drm/i915/display/intel_hdcp.c

268

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

271

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2727

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2735

queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

2780

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2783

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2798

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2830

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

2839

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

2852

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_hdcp.c

307

static bool intel_hdcp_in_use(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hdcp.c

310

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

311

HDCP_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

315

static bool intel_hdcp2_in_use(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hdcp.c

318

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

319

HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

341

static bool hdcp_key_loadable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp.c

350

if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_hdcp.c

356

with_intel_display_rpm(display)

drivers/gpu/drm/i915/display/intel_hdcp.c

357

enabled = intel_display_power_well_is_enabled(display, id);

drivers/gpu/drm/i915/display/intel_hdcp.c

368

static void intel_hdcp_clear_keys(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp.c

370

intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);

drivers/gpu/drm/i915/display/intel_hdcp.c

371

intel_de_write(display, HDCP_KEY_STATUS,

drivers/gpu/drm/i915/display/intel_hdcp.c

375

static int intel_hdcp_load_keys(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp.c

380

val = intel_de_read(display, HDCP_KEY_STATUS);

drivers/gpu/drm/i915/display/intel_hdcp.c

388

if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_hdcp.c

389

if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))

drivers/gpu/drm/i915/display/intel_hdcp.c

400

if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {

drivers/gpu/drm/i915/display/intel_hdcp.c

401

ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1);

drivers/gpu/drm/i915/display/intel_hdcp.c

403

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

409

intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);

drivers/gpu/drm/i915/display/intel_hdcp.c

413

ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE,

drivers/gpu/drm/i915/display/intel_hdcp.c

421

intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);

drivers/gpu/drm/i915/display/intel_hdcp.c

427

static int intel_write_sha_text(struct intel_display *display, u32 sha_text)

drivers/gpu/drm/i915/display/intel_hdcp.c

429

intel_de_write(display, HDCP_SHA_TEXT, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

430

if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

431

drm_err(display->drm, "Timed out waiting for SHA1 ready\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

438

u32 intel_hdcp_get_repeater_ctl(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hdcp.c

441

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_hdcp.c

456

drm_err(display->drm, "Unknown transcoder %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

474

drm_err(display->drm, "Unknown port %d\n", port);

drivers/gpu/drm/i915/display/intel_hdcp.c

484

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

49

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdcp.c

496

intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime);

drivers/gpu/drm/i915/display/intel_hdcp.c

512

rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port);

drivers/gpu/drm/i915/display/intel_hdcp.c

513

intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);

drivers/gpu/drm/i915/display/intel_hdcp.c

525

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

532

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

549

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

565

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

567

ret = intel_write_sha_text(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

57

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_hdcp.c

574

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

576

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

58

rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdcp.c

582

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

584

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

591

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

596

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

60

} else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) ||

drivers/gpu/drm/i915/display/intel_hdcp.c

602

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

604

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

61

IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

610

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

612

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

619

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

62

rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdcp.c

622

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

628

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

631

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

64

} else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

641

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

644

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

65

rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdcp.c

650

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

653

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

659

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

661

ret = intel_write_sha_text(display, bstatus[1]);

drivers/gpu/drm/i915/display/intel_hdcp.c

667

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

669

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

675

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

677

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

682

drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

687

intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);

drivers/gpu/drm/i915/display/intel_hdcp.c

690

ret = intel_write_sha_text(display, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

70

intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit);

drivers/gpu/drm/i915/display/intel_hdcp.c

702

ret = intel_write_sha_text(display, sha_text);

drivers/gpu/drm/i915/display/intel_hdcp.c

707

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

709

if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

711

drm_err(display->drm, "Timed out waiting for SHA1 complete\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

714

if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

715

drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

726

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

734

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

745

drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

758

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

765

drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

773

if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo,

drivers/gpu/drm/i915/display/intel_hdcp.c

775

drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

793

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

798

drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

809

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

843

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

851

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

852

HDCP_ANINIT(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

854

intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

858

if (intel_de_wait_for_set_ms(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

859

HDCP_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

861

drm_err(display->drm, "Timed out waiting for An\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

865

an.reg[0] = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

866

HDCP_ANLO(display, cpu_transcoder, port));

drivers/gpu/drm/i915/display/intel_hdcp.c

867

an.reg[1] = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

868

HDCP_ANHI(display, cpu_transcoder, port));

drivers/gpu/drm/i915/display/intel_hdcp.c

881

if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) {

drivers/gpu/drm/i915/display/intel_hdcp.c

882

drm_err(display->drm, "BKSV is revoked\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

886

intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

888

intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

895

intel_de_write(display, HDCP_REP_CTL,

drivers/gpu/drm/i915/display/intel_hdcp.c

896

intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port));

drivers/gpu/drm/i915/display/intel_hdcp.c

902

intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

906

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

drivers/gpu/drm/i915/display/intel_hdcp.c

910

drm_err(display->drm, "Timed out waiting for R0 ready\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

936

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

937

HDCP_RPRIME(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

941

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

drivers/gpu/drm/i915/display/intel_hdcp.c

949

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdcp.c

955

if (intel_de_wait_for_set_ms(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

956

HDCP_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdcp.c

959

drm_err(display->drm, "Timed out waiting for encryption\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

967

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

971

drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

978

drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n");

drivers/gpu/drm/i915/display/intel_hdcp.c

984

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdcp.c

992

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n",

drivers/gpu/drm/i915/display/intel_hdcp.c

998

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n",

drivers/gpu/drm/i915/display/intel_hdcp.h

41

bool is_hdcp_supported(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_hdcp.h

42

void intel_hdcp_component_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hdcp.h

43

void intel_hdcp_component_fini(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

108

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

112

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

117

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

145

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

151

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

152

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

156

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

170

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

174

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

179

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

194

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

200

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

201

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

205

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

220

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

224

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

229

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. Status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

23

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

246

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

252

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

253

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

257

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

268

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

272

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

277

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

29

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

295

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

30

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

301

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

302

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

306

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

321

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

325

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

330

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

34

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

347

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

353

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

354

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

358

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

369

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

373

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

378

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

402

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

408

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

409

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

413

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

434

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

438

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

443

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

464

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

47

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

471

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

472

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

476

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

503

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

508

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

51

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

513

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

528

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

534

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

535

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

539

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

551

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

555

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

56

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

560

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

574

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

580

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

581

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

585

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

597

byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

601

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

606

drm_dbg_kms(display->drm, "Session Close Failed. status: 0x%X\n",

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

630

int intel_hdcp_gsc_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

640

mutex_lock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

642

gsc_context = intel_parent_hdcp_gsc_context_alloc(display);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

649

display->hdcp.arbiter = arbiter;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

650

display->hdcp.arbiter->hdcp_dev = display->drm->dev;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

651

display->hdcp.arbiter->ops = &gsc_hdcp_ops;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

652

display->hdcp.gsc_context = gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

655

mutex_unlock(&display->hdcp.hdcp_mutex);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

660

void intel_hdcp_gsc_fini(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

662

intel_parent_hdcp_gsc_context_free(display, display->hdcp.gsc_context);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

663

display->hdcp.gsc_context = NULL;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

664

kfree(display->hdcp.arbiter);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

665

display->hdcp.arbiter = NULL;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

81

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

87

display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

88

if (!display) {

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

92

gsc_context = display->hdcp.gsc_context;

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h

11

int intel_hdcp_gsc_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h

12

void intel_hdcp_gsc_fini(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hdmi.c

1005

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

1006

reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1007

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_hdmi.c

1009

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

1014

intel_de_write(display, reg, crtc_state->infoframes.gcp);

drivers/gpu/drm/i915/display/intel_hdmi.c

102

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1022

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

103

intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

drivers/gpu/drm/i915/display/intel_hdmi.c

1030

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

1031

reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1032

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_hdmi.c

1034

else if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

1039

crtc_state->infoframes.gcp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1046

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1048

if (display->platform.g4x || !crtc_state->has_infoframe)

drivers/gpu/drm/i915/display/intel_hdmi.c

1069

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1074

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1088

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1089

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1094

drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,

drivers/gpu/drm/i915/display/intel_hdmi.c

1109

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1110

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1128

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1132

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1145

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1146

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1158

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1159

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1177

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1181

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1195

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1196

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1201

drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,

drivers/gpu/drm/i915/display/intel_hdmi.c

1216

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1217

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1234

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1235

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

1237

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1246

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1247

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1259

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1260

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

1262

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1264

assert_hdmi_transcoder_func_disabled(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

1273

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1274

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1281

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

1282

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1300

struct intel_display *display = to_intel_display(hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1306

drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1309

drm_dp_dual_mode_set_tmds_output(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1375

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1383

drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1390

drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);

drivers/gpu/drm/i915/display/intel_hdmi.c

1399

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1405

drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1414

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1420

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1430

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1436

drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1448

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1454

drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1463

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1469

drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1481

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1486

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1497

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1506

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1515

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

1522

scanline = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

1523

PIPEDSL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

1532

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1540

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1553

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1565

drm_err(display->drm, "%s HDCP signalling failed (%d)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1574

if (display->platform.kabylake && enable)

drivers/gpu/drm/i915/display/intel_hdmi.c

1585

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1598

intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1601

ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display, cpu_transcoder, port),

drivers/gpu/drm/i915/display/intel_hdmi.c

1604

drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1605

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,

drivers/gpu/drm/i915/display/intel_hdmi.c

1672

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1678

drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

1699

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

1713

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1735

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

1752

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

1761

drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

178

hsw_dip_data_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hdmi.c

1827

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1830

if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_hdmi.c

1832

else if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_hdmi.c

1834

else if (DISPLAY_VER(display) >= 8 || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_hdmi.c

1836

else if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_hdmi.c

185

return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

187

return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

189

return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

1892

struct intel_display *display = to_intel_display(hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1902

if (display->platform.geminilake && clock > 446666 && clock < 480000)

drivers/gpu/drm/i915/display/intel_hdmi.c

1906

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/intel_hdmi.c

191

return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

1911

if (display->platform.cherryview && clock > 216000 && clock < 240000)

drivers/gpu/drm/i915/display/intel_hdmi.c

193

return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

1940

static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)

drivers/gpu/drm/i915/display/intel_hdmi.c

1944

return !HAS_GMCH(display);

drivers/gpu/drm/i915/display/intel_hdmi.c

1946

return DISPLAY_VER(display) >= 11;

drivers/gpu/drm/i915/display/intel_hdmi.c

195

return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

197

return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

199

return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_hdmi.c

1994

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

2007

if (!intel_hdmi_source_bpc_possible(display, bpc))

drivers/gpu/drm/i915/display/intel_hdmi.c

2020

drm_WARN_ON(display->drm, status == MODE_OK);

drivers/gpu/drm/i915/display/intel_hdmi.c

2030

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

2034

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_hdmi.c

2039

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_hdmi.c

206

static int hsw_dip_data_size(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hdmi.c

2071

status = intel_pfit_mode_valid(display, mode, sink_format, 0);

drivers/gpu/drm/i915/display/intel_hdmi.c

2089

return intel_mode_valid_max_plane_size(display, mode, 1);

drivers/gpu/drm/i915/display/intel_hdmi.c

2114

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

2118

if (!intel_hdmi_source_bpc_possible(display, bpc))

drivers/gpu/drm/i915/display/intel_hdmi.c

2123

bpc == 10 && DISPLAY_VER(display) == 11 &&

drivers/gpu/drm/i915/display/intel_hdmi.c

217

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_hdmi.c

2170

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2193

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

2270

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2281

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

231

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

233

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

drivers/gpu/drm/i915/display/intel_hdmi.c

2342

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

236

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

drivers/gpu/drm/i915/display/intel_hdmi.c

2378

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

2415

drm_dbg_kms(display->drm, "bad AVI infoframe\n");

drivers/gpu/drm/i915/display/intel_hdmi.c

2420

drm_dbg_kms(display->drm, "bad SPD infoframe\n");

drivers/gpu/drm/i915/display/intel_hdmi.c

2425

drm_dbg_kms(display->drm, "bad HDMI infoframe\n");

drivers/gpu/drm/i915/display/intel_hdmi.c

2430

drm_dbg_kms(display->drm, "bad DRM infoframe\n");

drivers/gpu/drm/i915/display/intel_hdmi.c

244

intel_de_write(display, VIDEO_DIP_CTL, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

2465

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

247

intel_de_write(display, VIDEO_DIP_DATA, *data);

drivers/gpu/drm/i915/display/intel_hdmi.c

2471

type = drm_dp_dual_mode_detect(display->drm, ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2485

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

2498

drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2500

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

2506

if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) &&

drivers/gpu/drm/i915/display/intel_hdmi.c

2508

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

2518

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

252

intel_de_write(display, VIDEO_DIP_DATA, 0);

drivers/gpu/drm/i915/display/intel_hdmi.c

2525

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

drivers/gpu/drm/i915/display/intel_hdmi.c

2530

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

2548

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

drivers/gpu/drm/i915/display/intel_hdmi.c

2560

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

2566

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

2569

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

2572

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

2575

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

drivers/gpu/drm/i915/display/intel_hdmi.c

2577

if (DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/intel_hdmi.c

258

intel_de_write(display, VIDEO_DIP_CTL, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

2587

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

drivers/gpu/drm/i915/display/intel_hdmi.c

259

intel_de_posting_read(display, VIDEO_DIP_CTL);

drivers/gpu/drm/i915/display/intel_hdmi.c

2599

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

2601

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_hdmi.c

2604

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

2663

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_hdmi.c

2665

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

267

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2681

struct intel_display *display = to_intel_display(intel_hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

2690

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_hdmi.c

2693

if (!HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

271

intel_de_rmw(display, VIDEO_DIP_CTL,

drivers/gpu/drm/i915/display/intel_hdmi.c

2721

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2728

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

275

*data++ = intel_de_read(display, VIDEO_DIP_DATA);

drivers/gpu/drm/i915/display/intel_hdmi.c

2809

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

281

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2817

drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port));

drivers/gpu/drm/i915/display/intel_hdmi.c

282

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

drivers/gpu/drm/i915/display/intel_hdmi.c

2846

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2857

if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)

drivers/gpu/drm/i915/display/intel_hdmi.c

2865

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2868

drm_WARN_ON(display->drm, encoder->port == PORT_A);

drivers/gpu/drm/i915/display/intel_hdmi.c

2876

if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)

drivers/gpu/drm/i915/display/intel_hdmi.c

2928

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2931

if (display->platform.alderlake_s)

drivers/gpu/drm/i915/display/intel_hdmi.c

2933

else if (INTEL_PCH_TYPE(display) >= PCH_DG1)

drivers/gpu/drm/i915/display/intel_hdmi.c

2935

else if (display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_hdmi.c

2937

else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

2939

else if ((display->platform.jasperlake || display->platform.elkhartlake) &&

drivers/gpu/drm/i915/display/intel_hdmi.c

2940

HAS_PCH_TGP(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

2942

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_hdmi.c

2944

else if (HAS_PCH_CNP(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

2946

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_hdmi.c

2948

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_hdmi.c

2959

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2962

for_each_intel_encoder(display->drm, other) {

drivers/gpu/drm/i915/display/intel_hdmi.c

2973

if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))

drivers/gpu/drm/i915/display/intel_hdmi.c

2982

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

299

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

2995

if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {

drivers/gpu/drm/i915/display/intel_hdmi.c

2996

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

3004

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

3011

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

3021

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

3023

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_hdmi.c

3028

} else if (display->platform.g4x) {

drivers/gpu/drm/i915/display/intel_hdmi.c

303

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

3033

} else if (HAS_DDI(display)) {

drivers/gpu/drm/i915/display/intel_hdmi.c

3045

} else if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_hdmi.c

306

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

drivers/gpu/drm/i915/display/intel_hdmi.c

3061

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hdmi.c

3070

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

3074

if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))

drivers/gpu/drm/i915/display/intel_hdmi.c

3090

intel_gmbus_get_adapter(display, ddc_pin));

drivers/gpu/drm/i915/display/intel_hdmi.c

3094

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_hdmi.c

3099

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_hdmi.c

3105

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

3115

if (is_hdcp_supported(display, port)) {

drivers/gpu/drm/i915/display/intel_hdmi.c

3119

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

3129

drm_dbg_kms(display->drm, "CEC notifier get failed\n");

drivers/gpu/drm/i915/display/intel_hdmi.c

314

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

317

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),

drivers/gpu/drm/i915/display/intel_hdmi.c

323

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_hdmi.c

329

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

330

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

338

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

343

intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),

drivers/gpu/drm/i915/display/intel_hdmi.c

347

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

353

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

356

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

374

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

378

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

381

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

drivers/gpu/drm/i915/display/intel_hdmi.c

392

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

395

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),

drivers/gpu/drm/i915/display/intel_hdmi.c

401

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_hdmi.c

407

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

408

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

416

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

421

intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),

drivers/gpu/drm/i915/display/intel_hdmi.c

425

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

431

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

433

u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

448

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

452

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

455

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

drivers/gpu/drm/i915/display/intel_hdmi.c

463

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

466

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

472

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

479

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

480

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

488

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

493

intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),

drivers/gpu/drm/i915/display/intel_hdmi.c

497

*data++ = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

504

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

506

u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

524

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

527

i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

530

u32 val = intel_de_read(display, ctl_reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

532

data_size = hsw_dip_data_size(display, type);

drivers/gpu/drm/i915/display/intel_hdmi.c

534

drm_WARN_ON(display->drm, len > data_size);

drivers/gpu/drm/i915/display/intel_hdmi.c

537

intel_de_write(display, ctl_reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

540

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

541

hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),

drivers/gpu/drm/i915/display/intel_hdmi.c

547

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

548

hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),

drivers/gpu/drm/i915/display/intel_hdmi.c

552

if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&

drivers/gpu/drm/i915/display/intel_hdmi.c

559

intel_de_write(display, ctl_reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

560

intel_de_posting_read(display, ctl_reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

567

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

573

*data++ = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

574

hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2));

drivers/gpu/drm/i915/display/intel_hdmi.c

580

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

581

u32 val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

582

HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_hdmi.c

589

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_hdmi.c

592

if (HAS_AS_SDP(display))

drivers/gpu/drm/i915/display/intel_hdmi.c

624

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

635

if (HAS_DDI(display)) {

drivers/gpu/drm/i915/display/intel_hdmi.c

788

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

798

if (display->platform.dgfx)

drivers/gpu/drm/i915/display/intel_hdmi.c

850

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

854

if (DISPLAY_VER(display) < 10)

drivers/gpu/drm/i915/display/intel_hdmi.c

868

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

874

if (drm_WARN_ON(display->drm, ret))

drivers/gpu/drm/i915/display/intel_hdmi.c

88

struct intel_display *display = to_intel_display(intel_hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

885

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

889

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

909

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

91

enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;

drivers/gpu/drm/i915/display/intel_hdmi.c

916

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

917

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

923

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

93

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_hdmi.c

936

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_hdmi.c

937

intel_de_posting_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

94

intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,

drivers/gpu/drm/i915/display/intel_hdmi.c

99

assert_hdmi_transcoder_func_disabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hdmi.c

997

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug.c

1001

blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

1006

switch (display->hotplug.stats[pin].state) {

drivers/gpu/drm/i915/display/intel_hotplug.c

1014

MISSING_CASE(display->hotplug.stats[pin].state);

drivers/gpu/drm/i915/display/intel_hotplug.c

1022

queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);

drivers/gpu/drm/i915/display/intel_hotplug.c

1025

static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)

drivers/gpu/drm/i915/display/intel_hotplug.c

1027

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1029

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1036

static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin)

drivers/gpu/drm/i915/display/intel_hotplug.c

1038

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1040

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1042

if (drm_WARN_ON(display->drm, hotplug->stats[pin].blocked_count == 0))

drivers/gpu/drm/i915/display/intel_hotplug.c

1076

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug.c

1077

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1083

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1085

if (block_hpd_pin(display, encoder->hpd_pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

1088

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1090

if (do_flush && hpd_pin_has_pulse(display, encoder->hpd_pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

1105

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug.c

1110

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1112

if (unblock_hpd_pin(display, encoder->hpd_pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

1113

queue_work_for_missed_irqs(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

1115

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1128

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug.c

1129

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1135

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1137

if (unblock_hpd_pin(display, pin)) {

drivers/gpu/drm/i915/display/intel_hotplug.c

1144

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1147

void intel_hpd_enable_detection_work(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

1149

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1150

display->hotplug.detection_work_enabled = true;

drivers/gpu/drm/i915/display/intel_hotplug.c

1151

queue_work_for_missed_irqs(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

1152

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1155

void intel_hpd_disable_detection_work(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

1157

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1158

display->hotplug.detection_work_enabled = false;

drivers/gpu/drm/i915/display/intel_hotplug.c

1159

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1161

cancel_all_detection_work(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

1164

bool intel_hpd_schedule_detection(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

1169

spin_lock_irqsave(&display->irq.lock, flags);

drivers/gpu/drm/i915/display/intel_hotplug.c

1170

ret = queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);

drivers/gpu/drm/i915/display/intel_hotplug.c

1171

spin_unlock_irqrestore(&display->irq.lock, flags);

drivers/gpu/drm/i915/display/intel_hotplug.c

1178

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_hotplug.c

1179

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1184

intel_parent_irq_synchronize(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

1185

flush_work(&display->hotplug.dig_port_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

1186

flush_delayed_work(&display->hotplug.hotplug_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

1200

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_hotplug.c

1201

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1226

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

1230

drm_dbg_kms(display->drm, "Disabling HPD storm detection\n");

drivers/gpu/drm/i915/display/intel_hotplug.c

1232

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1237

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1240

flush_delayed_work(&display->hotplug.reenable_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

1261

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_hotplug.c

1264

str_yes_no(display->hotplug.hpd_short_storm_enabled));

drivers/gpu/drm/i915/display/intel_hotplug.c

1281

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_hotplug.c

1282

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

1303

new_state = !HAS_DP_MST(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

1307

drm_dbg_kms(display->drm, "%sabling HPD short storm detection\n",

drivers/gpu/drm/i915/display/intel_hotplug.c

1310

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1315

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

1318

flush_delayed_work(&display->hotplug.reenable_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

1332

void intel_hpd_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

1334

struct dentry *debugfs_root = display->drm->debugfs_root;

drivers/gpu/drm/i915/display/intel_hotplug.c

1337

display, &i915_hpd_storm_ctl_fops);

drivers/gpu/drm/i915/display/intel_hotplug.c

1339

display, &i915_hpd_short_storm_ctl_fops);

drivers/gpu/drm/i915/display/intel_hotplug.c

1341

&display->hotplug.ignore_long_hpd);

drivers/gpu/drm/i915/display/intel_hotplug.c

152

static bool intel_hpd_irq_storm_detect(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug.c

155

struct intel_hotplug *hpd = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

163

(!long_hpd && !display->hotplug.hpd_short_storm_enabled))

drivers/gpu/drm/i915/display/intel_hotplug.c

174

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

178

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

187

static bool detection_work_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

189

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

191

return display->hotplug.detection_work_enabled;

drivers/gpu/drm/i915/display/intel_hotplug.c

195

mod_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)

drivers/gpu/drm/i915/display/intel_hotplug.c

197

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

199

if (!detection_work_enabled(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

202

return mod_delayed_work(display->wq.unordered, work, delay);

drivers/gpu/drm/i915/display/intel_hotplug.c

206

queue_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)

drivers/gpu/drm/i915/display/intel_hotplug.c

208

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

210

if (!detection_work_enabled(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

213

return queue_delayed_work(display->wq.unordered, work, delay);

drivers/gpu/drm/i915/display/intel_hotplug.c

217

queue_detection_work(struct intel_display *display, struct work_struct *work)

drivers/gpu/drm/i915/display/intel_hotplug.c

219

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

221

if (!detection_work_enabled(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

224

return queue_work(display->wq.unordered, work);

drivers/gpu/drm/i915/display/intel_hotplug.c

228

intel_hpd_irq_storm_switch_to_polling(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

234

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

236

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hotplug.c

245

display->hotplug.stats[pin].state != HPD_MARK_DISABLED)

drivers/gpu/drm/i915/display/intel_hotplug.c

248

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

253

display->hotplug.stats[pin].state = HPD_DISABLED;

drivers/gpu/drm/i915/display/intel_hotplug.c

262

drm_kms_helper_poll_reschedule(display->drm);

drivers/gpu/drm/i915/display/intel_hotplug.c

263

mod_delayed_detection_work(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

264

&display->hotplug.reenable_work,

drivers/gpu/drm/i915/display/intel_hotplug.c

271

struct intel_display *display =

drivers/gpu/drm/i915/display/intel_hotplug.c

272

container_of(work, typeof(*display), hotplug.reenable_work.work);

drivers/gpu/drm/i915/display/intel_hotplug.c

278

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

280

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

282

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hotplug.c

286

display->hotplug.stats[pin].state != HPD_DISABLED)

drivers/gpu/drm/i915/display/intel_hotplug.c

290

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

298

if (display->hotplug.stats[pin].state == HPD_DISABLED)

drivers/gpu/drm/i915/display/intel_hotplug.c

299

display->hotplug.stats[pin].state = HPD_ENABLED;

drivers/gpu/drm/i915/display/intel_hotplug.c

302

intel_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

304

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

306

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_hotplug.c

355

static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin pin)

drivers/gpu/drm/i915/display/intel_hotplug.c

359

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_hotplug.c

370

static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin pin)

drivers/gpu/drm/i915/display/intel_hotplug.c

372

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

374

return display->hotplug.stats[pin].blocked_count;

drivers/gpu/drm/i915/display/intel_hotplug.c

377

static u32 get_blocked_hpd_pin_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

383

if (hpd_pin_is_blocked(display, pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

392

struct intel_display *display =

drivers/gpu/drm/i915/display/intel_hotplug.c

394

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

400

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

402

blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

408

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

410

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_hotplug.c

435

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

436

display->hotplug.event_bits |= old_bits;

drivers/gpu/drm/i915/display/intel_hotplug.c

437

queue_delayed_detection_work(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

438

&display->hotplug.hotplug_work, 0);

drivers/gpu/drm/i915/display/intel_hotplug.c

439

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

452

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_hotplug.c

453

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

456

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

459

if (!hpd_pin_is_blocked(display, encoder->hpd_pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

462

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

470

struct intel_display *display =

drivers/gpu/drm/i915/display/intel_hotplug.c

472

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

482

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

483

drm_dbg_kms(display->drm, "running encoder hotplug functions\n");

drivers/gpu/drm/i915/display/intel_hotplug.c

485

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

487

blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

494

intel_hpd_irq_storm_switch_to_polling(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

496

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

499

if (display->hotplug.ignore_long_hpd) {

drivers/gpu/drm/i915/display/intel_hotplug.c

500

drm_dbg_kms(display->drm, "Ignore HPD flag on - skip encoder hotplug handlers\n");

drivers/gpu/drm/i915/display/intel_hotplug.c

501

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

505

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hotplug.c

524

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

547

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

552

drm_kms_helper_hotplug_event(display->drm);

drivers/gpu/drm/i915/display/intel_hotplug.c

560

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

561

display->hotplug.retry_bits |= retry;

drivers/gpu/drm/i915/display/intel_hotplug.c

563

mod_delayed_detection_work(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

564

&display->hotplug.hotplug_work,

drivers/gpu/drm/i915/display/intel_hotplug.c

566

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

587

void intel_hpd_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug.c

600

spin_lock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

608

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_hotplug.c

620

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

625

if (!hpd_pin_is_blocked(display, pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

630

display->hotplug.long_hpd_pin_mask |= BIT(pin);

drivers/gpu/drm/i915/display/intel_hotplug.c

633

display->hotplug.short_hpd_pin_mask |= BIT(pin);

drivers/gpu/drm/i915/display/intel_hotplug.c

644

if (display->hotplug.stats[pin].state == HPD_DISABLED) {

drivers/gpu/drm/i915/display/intel_hotplug.c

651

drm_WARN_ONCE(display->drm, !HAS_GMCH(display),

drivers/gpu/drm/i915/display/intel_hotplug.c

657

if (display->hotplug.stats[pin].state != HPD_ENABLED)

drivers/gpu/drm/i915/display/intel_hotplug.c

668

display->hotplug.event_bits |= BIT(pin);

drivers/gpu/drm/i915/display/intel_hotplug.c

671

if (!hpd_pin_is_blocked(display, pin))

drivers/gpu/drm/i915/display/intel_hotplug.c

675

if (intel_hpd_irq_storm_detect(display, pin, long_hpd)) {

drivers/gpu/drm/i915/display/intel_hotplug.c

676

display->hotplug.event_bits &= ~BIT(pin);

drivers/gpu/drm/i915/display/intel_hotplug.c

687

intel_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

696

queue_work(display->hotplug.dp_wq, &display->hotplug.dig_port_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

698

queue_delayed_detection_work(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

699

&display->hotplug.hotplug_work, 0);

drivers/gpu/drm/i915/display/intel_hotplug.c

701

spin_unlock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

718

void intel_hpd_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

722

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

726

display->hotplug.stats[i].count = 0;

drivers/gpu/drm/i915/display/intel_hotplug.c

727

display->hotplug.stats[i].state = HPD_ENABLED;

drivers/gpu/drm/i915/display/intel_hotplug.c

734

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

735

intel_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

736

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

739

static void i915_hpd_poll_detect_connectors(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

746

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

748

if (!display->drm->mode_config.poll_enabled)

drivers/gpu/drm/i915/display/intel_hotplug.c

751

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hotplug.c

769

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

777

drm_kms_helper_hotplug_event(display->drm);

drivers/gpu/drm/i915/display/intel_hotplug.c

784

struct intel_display *display =

drivers/gpu/drm/i915/display/intel_hotplug.c

785

container_of(work, typeof(*display), hotplug.poll_init_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

791

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

793

enabled = READ_ONCE(display->hotplug.poll_enabled);

drivers/gpu/drm/i915/display/intel_hotplug.c

801

wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

803

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug.c

804

READ_ONCE(display->hotplug.poll_enabled));

drivers/gpu/drm/i915/display/intel_hotplug.c

805

cancel_work(&display->hotplug.poll_init_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

808

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

810

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hotplug.c

818

if (display->hotplug.stats[pin].state == HPD_DISABLED)

drivers/gpu/drm/i915/display/intel_hotplug.c

829

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

832

drm_kms_helper_poll_reschedule(display->drm);

drivers/gpu/drm/i915/display/intel_hotplug.c

834

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_hotplug.c

841

i915_hpd_poll_detect_connectors(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

843

intel_display_power_put(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

865

void intel_hpd_poll_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

867

if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

870

WRITE_ONCE(display->hotplug.poll_enabled, true);

drivers/gpu/drm/i915/display/intel_hotplug.c

878

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

879

queue_detection_work(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

880

&display->hotplug.poll_init_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

881

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

903

void intel_hpd_poll_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

907

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

910

for_each_intel_dp(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_hotplug.c

913

WRITE_ONCE(display->hotplug.poll_enabled, false);

drivers/gpu/drm/i915/display/intel_hotplug.c

915

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

916

queue_detection_work(display,

drivers/gpu/drm/i915/display/intel_hotplug.c

917

&display->hotplug.poll_init_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

918

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

921

void intel_hpd_poll_fini(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

927

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_hotplug.c

935

void intel_hpd_init_early(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

937

INIT_DELAYED_WORK(&display->hotplug.hotplug_work,

drivers/gpu/drm/i915/display/intel_hotplug.c

939

INIT_WORK(&display->hotplug.dig_port_work, i915_digport_work_func);

drivers/gpu/drm/i915/display/intel_hotplug.c

940

INIT_WORK(&display->hotplug.poll_init_work, i915_hpd_poll_init_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

941

INIT_DELAYED_WORK(&display->hotplug.reenable_work,

drivers/gpu/drm/i915/display/intel_hotplug.c

944

display->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;

drivers/gpu/drm/i915/display/intel_hotplug.c

951

display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(display);

drivers/gpu/drm/i915/display/intel_hotplug.c

954

static bool cancel_all_detection_work(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

958

if (cancel_delayed_work_sync(&display->hotplug.hotplug_work))

drivers/gpu/drm/i915/display/intel_hotplug.c

960

if (cancel_work_sync(&display->hotplug.poll_init_work))

drivers/gpu/drm/i915/display/intel_hotplug.c

962

if (cancel_delayed_work_sync(&display->hotplug.reenable_work))

drivers/gpu/drm/i915/display/intel_hotplug.c

968

void intel_hpd_cancel_work(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

970

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

973

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

975

display->hotplug.long_hpd_pin_mask = 0;

drivers/gpu/drm/i915/display/intel_hotplug.c

976

display->hotplug.short_hpd_pin_mask = 0;

drivers/gpu/drm/i915/display/intel_hotplug.c

977

display->hotplug.event_bits = 0;

drivers/gpu/drm/i915/display/intel_hotplug.c

978

display->hotplug.retry_bits = 0;

drivers/gpu/drm/i915/display/intel_hotplug.c

980

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.c

982

cancel_work_sync(&display->hotplug.dig_port_work);

drivers/gpu/drm/i915/display/intel_hotplug.c

988

if (cancel_all_detection_work(display))

drivers/gpu/drm/i915/display/intel_hotplug.c

989

drm_dbg_kms(display->drm, "Hotplug detection work still active\n");

drivers/gpu/drm/i915/display/intel_hotplug.c

992

static void queue_work_for_missed_irqs(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug.c

994

struct intel_hotplug *hotplug = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug.c

999

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug.h

17

void intel_hpd_poll_enable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

18

void intel_hpd_poll_disable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

19

void intel_hpd_poll_fini(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

22

void intel_hpd_irq_handler(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug.h

25

void intel_hpd_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

26

void intel_hpd_init_early(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

27

void intel_hpd_cancel_work(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

32

void intel_hpd_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

34

void intel_hpd_enable_detection_work(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

35

void intel_hpd_disable_detection_work(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug.h

36

bool intel_hpd_schedule_detection(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1001

static void mtp_ddi_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1003

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1004

intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1005

intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1010

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1012

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1017

static void mtp_tc_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1019

intel_de_rmw(display, SHOTPLUG_CTL_TC,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1020

intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1021

intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1026

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1028

intel_de_rmw(display, SHOTPLUG_CTL_TC,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1033

static void mtp_hpd_invert(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1044

intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1049

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1051

mtp_hpd_invert(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1056

static void mtp_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1060

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1061

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1067

intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1069

mtp_hpd_invert(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1070

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1072

mtp_ddi_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1073

mtp_tc_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1076

static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1080

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1081

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1083

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1085

mtp_ddi_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1086

mtp_tc_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1094

static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1103

intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1109

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1111

_xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1114

static void xelpdp_pica_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1122

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1126

_xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1135

static void xelpdp_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1139

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1140

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1142

intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1144

intel_de_posting_read(display, PICAINTERRUPT_IMR);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1146

xelpdp_pica_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1148

if (INTEL_PCH_TYPE(display) >= PCH_LNL)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1149

xe2lpd_sde_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1150

else if (INTEL_PCH_TYPE(display) >= PCH_MTL)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1151

mtp_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1190

static void spt_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1193

if (HAS_PCH_CNP(display)) {

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1194

intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1199

intel_de_rmw(display, PCH_PORT_HOTPLUG,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1200

intel_hpd_hotplug_mask(display, spt_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1201

intel_hpd_hotplug_enables(display, spt_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1203

intel_de_rmw(display, PCH_PORT_HOTPLUG2,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1204

intel_hpd_hotplug_mask(display, spt_hotplug2_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1205

intel_hpd_hotplug_enables(display, spt_hotplug2_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1210

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1213

if (HAS_PCH_CNP(display)) {

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1214

intel_de_rmw(display, SOUTH_CHICKEN1,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1219

intel_de_rmw(display, PCH_PORT_HOTPLUG,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1223

intel_de_rmw(display, PCH_PORT_HOTPLUG2,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1228

static void spt_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1232

if (INTEL_PCH_TYPE(display) >= PCH_CNP)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1233

intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1235

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1236

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1238

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1240

spt_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1265

static void ilk_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1272

intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1273

intel_hpd_hotplug_mask(display, ilk_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1274

intel_hpd_hotplug_enables(display, ilk_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1279

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1281

intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1288

static void ilk_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1292

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1293

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1295

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1296

bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1298

ilk_update_display_irq(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1300

ilk_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1302

ibx_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1344

static void bxt_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1346

intel_de_rmw(display, PCH_PORT_HOTPLUG,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1347

intel_hpd_hotplug_mask(display, bxt_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1348

intel_hpd_hotplug_enables(display, bxt_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1353

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1355

intel_de_rmw(display, PCH_PORT_HOTPLUG,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1360

static void bxt_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1364

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1365

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1367

bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1369

bxt_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

137

static void intel_hpd_init_pins(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1372

static void g45_hpd_peg_band_gap_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1379

intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1384

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1387

if (display->platform.g45)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1388

g45_hpd_peg_band_gap_wa(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

139

struct intel_hotplug *hpd = &display->hotplug;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1391

i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1394

static void i915_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1398

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1404

hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1409

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

141

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1413

if (display->platform.g45)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1414

g45_hpd_peg_band_gap_wa(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1417

i915_hotplug_interrupt_update_locked(display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

142

if (display->platform.g4x || display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1426

void (*hpd_irq_setup)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

143

display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1449

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1451

if (display->funcs.hotplug)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1452

display->funcs.hotplug->hpd_enable_detection(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1455

void intel_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1457

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1458

!display->irq.vlv_display_irqs_enabled)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1461

if (display->funcs.hotplug)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1462

display->funcs.hotplug->hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1465

void intel_hotplug_irq_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1467

intel_hpd_init_pins(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1469

intel_hpd_init_early(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1471

if (HAS_GMCH(display)) {

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1472

if (HAS_HOTPLUG(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1473

display->funcs.hotplug = &i915_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1475

if (HAS_PCH_DG2(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1476

display->funcs.hotplug = &icp_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1477

else if (HAS_PCH_DG1(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1478

display->funcs.hotplug = &dg1_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1479

else if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1480

display->funcs.hotplug = &xelpdp_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1481

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1482

display->funcs.hotplug = &gen11_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1483

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1484

display->funcs.hotplug = &bxt_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1485

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1486

display->funcs.hotplug = &icp_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1487

else if (INTEL_PCH_TYPE(display) >= PCH_SPT)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1488

display->funcs.hotplug = &spt_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

1490

display->funcs.hotplug = &ilk_hpd_funcs;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

150

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

152

else if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

154

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

156

else if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

158

else if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

160

else if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

165

if ((INTEL_PCH_TYPE(display) < PCH_DG1) &&

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

166

(!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display)))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

169

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

171

else if (INTEL_PCH_TYPE(display) >= PCH_DG1)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

173

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

175

else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

177

else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

179

else if (HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

182

MISSING_CASE(INTEL_PCH_TYPE(display));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

186

void i915_hotplug_interrupt_update_locked(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

189

lockdep_assert_held(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

190

drm_WARN_ON(display->drm, bits & ~mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

192

intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

207

void i915_hotplug_interrupt_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

211

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

212

i915_hotplug_interrupt_update_locked(display, mask, bits);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

213

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

344

static void intel_get_hpd_pins(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

364

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

369

static u32 intel_hpd_enabled_irqs(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

375

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

376

if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

382

static u32 intel_hpd_hotplug_irqs(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

388

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

394

static u32 intel_hpd_hotplug_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

406

static u32 intel_hpd_hotplug_enables(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

412

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

418

u32 i9xx_hpd_irq_ack(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

423

if (!HAS_HOTPLUG(display))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

426

if (display->platform.g4x ||

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

427

display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

443

u32 tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

444

PORT_HOTPLUG_STAT(display)) & hotplug_status_mask;

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

450

intel_de_write(display, PORT_HOTPLUG_STAT(display),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

454

drm_WARN_ONCE(display->drm, 1,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

456

intel_de_read(display, PORT_HOTPLUG_STAT(display)));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

461

void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

466

if (display->platform.g4x ||

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

467

display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

473

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

475

display->hotplug.hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

478

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

481

if ((display->platform.g4x ||

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

482

display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

484

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

487

void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

497

dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

506

intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

510

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

512

display->hotplug.pch_hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

515

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

518

void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

522

u32 trigger_aux = iir & xelpdp_pica_aux_mask(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

528

if (!(display->hotplug.hpd[pin] & hotplug_trigger))

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

533

val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

534

intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

541

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

545

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

549

intel_dp_aux_irq_handler(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

552

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

556

void icp_irq_handler(struct intel_display *display, u32 pch_iir)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

566

spin_lock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

567

dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

568

spin_unlock(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

570

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

572

display->hotplug.pch_hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

579

dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

581

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

583

display->hotplug.pch_hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

588

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

591

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

594

void spt_irq_handler(struct intel_display *display, u32 pch_iir)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

604

dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

606

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

608

display->hotplug.pch_hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

615

dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

617

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

619

display->hotplug.pch_hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

624

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

627

intel_gmbus_irq_handler(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

630

void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

634

dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

636

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

638

display->hotplug.hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

641

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

644

void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

648

dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

650

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

652

display->hotplug.hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

655

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

658

void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

667

dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

669

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

671

display->hotplug.hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

678

dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

680

intel_get_hpd_pins(display, &pin_mask, &long_mask,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

682

display->hotplug.hpd,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

687

intel_hpd_irq_handler(display, pin_mask, long_mask);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

689

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

711

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

719

return HAS_PCH_LPT_LP(display) ?

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

735

static void ibx_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

742

intel_de_rmw(display, PCH_PORT_HOTPLUG,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

743

intel_hpd_hotplug_mask(display, ibx_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

744

intel_hpd_hotplug_enables(display, ibx_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

749

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

751

intel_de_rmw(display, PCH_PORT_HOTPLUG,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

756

static void ibx_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

760

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

761

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

763

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

765

ibx_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

806

static void icp_ddi_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

808

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

809

intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

810

intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

815

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

817

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

822

static void icp_tc_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

824

intel_de_rmw(display, SHOTPLUG_CTL_TC,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

825

intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

826

intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

831

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

833

intel_de_rmw(display, SHOTPLUG_CTL_TC,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

844

static void icp_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

848

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

849

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

855

intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

857

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

859

icp_ddi_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

860

icp_tc_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

883

static void dg1_hpd_invert(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

889

intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

894

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

896

dg1_hpd_invert(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

900

static void dg1_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

902

dg1_hpd_invert(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

903

icp_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

906

static void gen11_tc_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

908

intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

909

intel_hpd_hotplug_mask(display, gen11_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

910

intel_hpd_hotplug_enables(display, gen11_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

915

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

917

intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

922

static void gen11_tbt_hpd_detection_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

924

intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

925

intel_hpd_hotplug_mask(display, gen11_hotplug_mask),

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

926

intel_hpd_hotplug_enables(display, gen11_hotplug_enables));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

931

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

933

intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

940

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

945

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

949

static void gen11_hpd_irq_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

953

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

954

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

956

intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

958

intel_de_posting_read(display, GEN11_DE_HPD_IMR);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

960

gen11_tc_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

961

gen11_tbt_hpd_detection_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

963

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

964

icp_hpd_irq_setup(display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

14

u32 i9xx_hpd_irq_ack(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

16

void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

17

void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

18

void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

19

void gen11_hpd_irq_handler(struct intel_display *display, u32 iir);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

20

void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

21

void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

22

void icp_irq_handler(struct intel_display *display, u32 pch_iir);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

23

void spt_irq_handler(struct intel_display *display, u32 pch_iir);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

25

void i915_hotplug_interrupt_update_locked(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

27

void i915_hotplug_interrupt_update(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

31

void intel_hpd_irq_setup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

33

void intel_hotplug_irq_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hti.c

14

void intel_hti_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hti.c

20

if (DISPLAY_INFO(display)->has_hti)

drivers/gpu/drm/i915/display/intel_hti.c

21

display->hti.state = intel_de_read(display, HDPORT_STATE);

drivers/gpu/drm/i915/display/intel_hti.c

24

bool intel_hti_uses_phy(struct intel_display *display, enum phy phy)

drivers/gpu/drm/i915/display/intel_hti.c

26

if (drm_WARN_ON(display->drm, phy == PHY_NONE))

drivers/gpu/drm/i915/display/intel_hti.c

29

return display->hti.state & HDPORT_ENABLED &&

drivers/gpu/drm/i915/display/intel_hti.c

30

display->hti.state & HDPORT_DDI_USED(phy);

drivers/gpu/drm/i915/display/intel_hti.c

33

u32 intel_hti_dpll_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_hti.c

35

if (!(display->hti.state & HDPORT_ENABLED))

drivers/gpu/drm/i915/display/intel_hti.c

42

return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state);

drivers/gpu/drm/i915/display/intel_hti.h

14

void intel_hti_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_hti.h

15

bool intel_hti_uses_phy(struct intel_display *display, enum phy phy);

drivers/gpu/drm/i915/display/intel_hti.h

16

u32 intel_hti_dpll_mask(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_initial_plane.c

108

ret = display->parent->initial_plane->setup(plane->base.state, plane_config, fb, vma);

drivers/gpu/drm/i915/display/intel_initial_plane.c

143

static void plane_config_fini(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_initial_plane.c

156

display->parent->initial_plane->config_fini(plane_config);

drivers/gpu/drm/i915/display/intel_initial_plane.c

159

void intel_initial_plane_config(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_initial_plane.c

16

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_initial_plane.c

164

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_initial_plane.c

18

display->parent->initial_plane->vblank_wait(&crtc->base);

drivers/gpu/drm/i915/display/intel_initial_plane.c

180

display->funcs.display->get_initial_plane_config(crtc, plane_config);

drivers/gpu/drm/i915/display/intel_initial_plane.c

188

if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config))

drivers/gpu/drm/i915/display/intel_initial_plane.c

191

plane_config_fini(display, plane_config);

drivers/gpu/drm/i915/display/intel_initial_plane.c

25

struct intel_display *display = to_intel_display(this);

drivers/gpu/drm/i915/display/intel_initial_plane.c

28

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_initial_plane.c

50

intel_alloc_initial_plane_obj(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_initial_plane.c

62

drm_dbg_kms(display->drm, "Unsupported modifier for initial FB: 0x%llx\n",

drivers/gpu/drm/i915/display/intel_initial_plane.c

67

return display->parent->initial_plane->alloc_obj(display->drm, plane_config);

drivers/gpu/drm/i915/display/intel_initial_plane.c

74

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_initial_plane.c

90

if (intel_alloc_initial_plane_obj(display, plane_config)) {

drivers/gpu/drm/i915/display/intel_initial_plane.h

12

void intel_initial_plane_config(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_link_bw.c

106

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_link_bw.c

111

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

drivers/gpu/drm/i915/display/intel_link_bw.c

220

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_link_bw.c

229

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_link_bw.c

262

assert_link_limit_change_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_link_bw.c

270

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_link_bw.c

275

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_link_bw.c

277

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_link_bw.c

288

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_link_bw.c

316

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_link_bw.c

324

if (!assert_link_limit_change_valid(display, &old_limits, new_limits))

drivers/gpu/drm/i915/display/intel_link_bw.c

419

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_link_bw.c

426

return HAS_DSC_MST(display);

drivers/gpu/drm/i915/display/intel_link_bw.c

428

return HAS_DSC(display);

drivers/gpu/drm/i915/display/intel_link_bw.c

439

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_link_bw.c

456

bpp_x16 > fxp_q4_from_int(intel_display_max_pipe_bpp(display))))

drivers/gpu/drm/i915/display/intel_link_bw.c

459

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_link_bw.c

465

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_link_bw.c

475

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_link_bw.c

487

if (HAS_FDI(display))

drivers/gpu/drm/i915/display/intel_link_bw.c

56

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_link_bw.c

61

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/intel_link_bw.c

62

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_load_detect.c

114

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_load_detect.c

121

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_load_detect.c

122

restore_state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_load_detect.c

167

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_load_detect.c

175

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_load_detect.c

207

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_load_detect.c

213

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_load_detect.c

222

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_load_detect.c

52

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_load_detect.c

57

struct drm_mode_config *config = &display->drm->mode_config;

drivers/gpu/drm/i915/display/intel_load_detect.c

63

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_load_detect.c

67

drm_WARN_ON(display->drm, !drm_modeset_is_locked(&config->connection_mutex));

drivers/gpu/drm/i915/display/intel_load_detect.c

92

for_each_intel_crtc(display->drm, possible_crtc) {

drivers/gpu/drm/i915/display/intel_lpe_audio.c

100

rsc[0].start = display->audio.lpe.irq;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

101

rsc[0].end = display->audio.lpe.irq;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

112

pinfo.parent = display->drm->dev;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

121

pdata->num_pipes = INTEL_NUM_PIPES(display);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

122

pdata->num_ports = display->platform.cherryview ? 3 : 2; /* B,C,D or B,C */

drivers/gpu/drm/i915/display/intel_lpe_audio.c

133

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

143

static void lpe_audio_platdev_destroy(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

153

platform_device_unregister(display->audio.lpe.platdev);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

170

static int lpe_audio_irq_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

172

int irq = display->audio.lpe.irq;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

181

static bool lpe_audio_detect(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

185

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_lpe_audio.c

195

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

203

static int lpe_audio_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

207

display->audio.lpe.irq = irq_alloc_desc(0);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

208

if (display->audio.lpe.irq < 0) {

drivers/gpu/drm/i915/display/intel_lpe_audio.c

209

drm_err(display->drm, "Failed to allocate IRQ desc: %d\n",

drivers/gpu/drm/i915/display/intel_lpe_audio.c

210

display->audio.lpe.irq);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

211

ret = display->audio.lpe.irq;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

215

drm_dbg(display->drm, "irq = %d\n", display->audio.lpe.irq);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

217

ret = lpe_audio_irq_init(display);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

220

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

226

display->audio.lpe.platdev = lpe_audio_platdev_create(display);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

228

if (IS_ERR(display->audio.lpe.platdev)) {

drivers/gpu/drm/i915/display/intel_lpe_audio.c

229

ret = PTR_ERR(display->audio.lpe.platdev);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

230

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

239

intel_de_write(display, VLV_AUD_CHICKEN_BIT_REG,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

244

irq_free_desc(display->audio.lpe.irq);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

246

display->audio.lpe.irq = -1;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

247

display->audio.lpe.platdev = NULL;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

258

void intel_lpe_audio_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

262

if (!HAS_LPE_AUDIO(display))

drivers/gpu/drm/i915/display/intel_lpe_audio.c

265

ret = generic_handle_irq(display->audio.lpe.irq);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

267

drm_err_ratelimited(display->drm,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

279

int intel_lpe_audio_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

283

if (lpe_audio_detect(display)) {

drivers/gpu/drm/i915/display/intel_lpe_audio.c

284

ret = lpe_audio_setup(display);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

286

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

299

void intel_lpe_audio_teardown(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

301

if (!HAS_LPE_AUDIO(display))

drivers/gpu/drm/i915/display/intel_lpe_audio.c

304

lpe_audio_platdev_destroy(display);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

306

irq_free_desc(display->audio.lpe.irq);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

308

display->audio.lpe.irq = -1;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

309

display->audio.lpe.platdev = NULL;

drivers/gpu/drm/i915/display/intel_lpe_audio.c

324

void intel_lpe_audio_notify(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lpe_audio.c

333

if (!HAS_LPE_AUDIO(display))

drivers/gpu/drm/i915/display/intel_lpe_audio.c

336

pdata = dev_get_platdata(&display->audio.lpe.platdev->dev);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

341

audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port));

drivers/gpu/drm/i915/display/intel_lpe_audio.c

350

intel_de_write(display, VLV_AUD_PORT_EN_DBG(port),

drivers/gpu/drm/i915/display/intel_lpe_audio.c

359

intel_de_write(display, VLV_AUD_PORT_EN_DBG(port),

drivers/gpu/drm/i915/display/intel_lpe_audio.c

364

pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

79

#define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

82

lpe_audio_platdev_create(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.c

84

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_lpe_audio.h

16

int intel_lpe_audio_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_lpe_audio.h

17

void intel_lpe_audio_teardown(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_lpe_audio.h

18

void intel_lpe_audio_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_lpe_audio.h

19

void intel_lpe_audio_notify(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lpe_audio.h

23

static inline int intel_lpe_audio_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.h

27

static inline void intel_lpe_audio_teardown(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.h

30

static inline void intel_lpe_audio_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lpe_audio.h

33

static inline void intel_lpe_audio_notify(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lspcon.c

108

drm_dbg_kms(display->drm, "Vendor: Mega Chips\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

113

drm_dbg_kms(display->drm, "Vendor: Parade Tech\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

117

drm_err(display->drm, "Invalid/Unknown vendor OUI\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

136

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

144

drm_dbg_kms(display->drm, "HDR capability detection failed\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

147

drm_dbg_kms(display->drm, "LSPCON capable of HDR\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

157

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

162

drm_dbg_kms(display->drm, "Error reading LSPCON mode\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

184

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

193

drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n",

drivers/gpu/drm/i915/display/intel_lspcon.c

202

drm_err(display->drm, "LSPCON mode hasn't settled\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

205

drm_dbg_kms(display->drm, "Current LSPCON mode %s\n",

drivers/gpu/drm/i915/display/intel_lspcon.c

215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

222

drm_err(display->drm, "Error reading LSPCON mode\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

227

drm_dbg_kms(display->drm, "Current mode = desired LSPCON mode\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

234

drm_err(display->drm, "LSPCON mode change failed\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

239

drm_dbg_kms(display->drm, "LSPCON mode changed done\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

246

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

251

drm_dbg_kms(display->drm, "Native AUX CH down\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

255

drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n",

drivers/gpu/drm/i915/display/intel_lspcon.c

264

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

284

drm_dbg_kms(display->drm, "No LSPCON detected, found %s\n",

drivers/gpu/drm/i915/display/intel_lspcon.c

290

drm_dbg_kms(display->drm, "LSPCON detected\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

300

drm_err(display->drm, "LSPCON mode change to PCON failed\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

310

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

316

drm_dbg_kms(display->drm, "LSPCON recovering in PCON mode after %u ms\n",

drivers/gpu/drm/i915/display/intel_lspcon.c

327

drm_dbg_kms(display->drm, "LSPCON DP descriptor mismatch after resume\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

498

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

513

drm_dbg_kms(display->drm, "Update HDR metadata for lspcon\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

522

drm_err(display->drm, "Failed to write infoframes\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

543

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

553

drm_err(display->drm, "Writing infoframes while LSPCON disabled ?\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

563

drm_err(display->drm, "couldn't fill AVI infoframe\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

604

drm_err(display->drm, "Failed to pack AVI IF\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

645

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

661

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_lspcon.c

662

HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_lspcon.c

681

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_lspcon.c

690

drm_err(display->drm, "Failed to probe lspcon\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

695

drm_err(display->drm, "LSPCON DPCD read failed\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

700

drm_err(display->drm, "LSPCON vendor detection failed\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

706

drm_dbg_kms(display->drm, "Success: LSPCON init\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

727

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_lspcon.c

736

drm_err(display->drm, "LSPCON init failed on port %c\n",

drivers/gpu/drm/i915/display/intel_lspcon.c

753

drm_err(display->drm, "LSPCON resume failed\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

755

drm_dbg_kms(display->drm, "LSPCON resume success\n");

drivers/gpu/drm/i915/display/intel_lspcon.c

92

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

97

drm_err(display->drm, "Can't read description\n");

drivers/gpu/drm/i915/display/intel_lt_phy.c

1044

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1046

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1052

assert_dc_off(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lt_phy.c

1056

enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1057

drm_WARN_ON(display->drm, !enabled);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1065

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1071

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1074

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1081

intel_de_rmw(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 0, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1083

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1094

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1120

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1124

assert_dc_off(display);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1135

drm_err_once(display->drm,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1172

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1188

intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1191

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1198

intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1201

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1205

if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1208

drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

1211

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1215

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1218

if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1221

drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

1224

if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1227

drm_warn(display->drm, "PHY %c PLL rate not changed\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

1230

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1238

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1241

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1254

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1256

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1264

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1266

XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |

drivers/gpu/drm/i915/display/intel_lt_phy.c

1330

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1335

wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1342

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1346

intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1370

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1373

if (intel_panel_use_ssc(display)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1692

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1738

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1755

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1776

drm_WARN_ON(display->drm, "Unsupported LT PHY Mode!\n");

drivers/gpu/drm/i915/display/intel_lt_phy.c

1934

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1985

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1989

if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1992

drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2000

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2004

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2009

if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2012

drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2019

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2024

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2037

if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2040

drm_warn(display->drm, "PHY %c PLL rate not changed\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2044

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2048

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2065

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2086

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2091

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,

drivers/gpu/drm/i915/display/intel_lt_phy.c

2095

if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2098

drm_warn(display->drm, "PHY %c failed to reset lane\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2102

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2111

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2115

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2118

if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2121

drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2129

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2130

XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_FORWARD_CLOCK_UNGATE, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2133

intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2142

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2157

if (drm_WARN_ON_ONCE(display->drm, !trans)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

2194

void intel_lt_phy_dump_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lt_phy.c

2199

drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");

drivers/gpu/drm/i915/display/intel_lt_phy.c

2201

drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2207

drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",

drivers/gpu/drm/i915/display/intel_lt_phy.c

2265

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2273

if (DISPLAY_VER(display) < 35)

drivers/gpu/drm/i915/display/intel_lt_phy.c

2291

INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],

drivers/gpu/drm/i915/display/intel_lt_phy.c

2295

INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],

drivers/gpu/drm/i915/display/intel_lt_phy.h

28

void intel_lt_phy_dump_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lvds.c

1002

drm_dbg_kms(display->drm, "detected %s-link lvds configuration\n",

drivers/gpu/drm/i915/display/intel_lvds.c

1010

drm_dbg_kms(display->drm, "No LVDS modes found, disabling.\n");

drivers/gpu/drm/i915/display/intel_lvds.c

106

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lvds.c

111

wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain);

drivers/gpu/drm/i915/display/intel_lvds.c

115

ret = intel_lvds_port_enabled(display, lvds_encoder->reg, pipe);

drivers/gpu/drm/i915/display/intel_lvds.c

117

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_lvds.c

125

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lvds.c

131

tmp = intel_de_read(display, lvds_encoder->reg);

drivers/gpu/drm/i915/display/intel_lvds.c

143

if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_lvds.c

148

if (DISPLAY_VER(display) < 4) {

drivers/gpu/drm/i915/display/intel_lvds.c

149

tmp = intel_de_read(display, PFIT_CONTROL(display));

drivers/gpu/drm/i915/display/intel_lvds.c

157

static void intel_lvds_pps_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lvds.c

162

pps->powerdown_on_reset = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_lvds.c

163

PP_CONTROL(display, 0)) & PANEL_POWER_RESET;

drivers/gpu/drm/i915/display/intel_lvds.c

165

val = intel_de_read(display, PP_ON_DELAYS(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

170

val = intel_de_read(display, PP_OFF_DELAYS(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

174

val = intel_de_read(display, PP_DIVISOR(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

187

if (DISPLAY_VER(display) < 5 &&

drivers/gpu/drm/i915/display/intel_lvds.c

192

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

203

drm_dbg(display->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d "

drivers/gpu/drm/i915/display/intel_lvds.c

211

static void intel_lvds_pps_init_hw(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lvds.c

216

val = intel_de_read(display, PP_CONTROL(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

217

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

221

intel_de_write(display, PP_CONTROL(display, 0), val);

drivers/gpu/drm/i915/display/intel_lvds.c

223

intel_de_write(display, PP_ON_DELAYS(display, 0),

drivers/gpu/drm/i915/display/intel_lvds.c

228

intel_de_write(display, PP_OFF_DELAYS(display, 0),

drivers/gpu/drm/i915/display/intel_lvds.c

232

intel_de_write(display, PP_DIVISOR(display, 0),

drivers/gpu/drm/i915/display/intel_lvds.c

243

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_lvds.c

250

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_lvds.c

251

assert_fdi_rx_pll_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_lvds.c

252

assert_dpll_disabled(display, crtc_state->intel_dpll);

drivers/gpu/drm/i915/display/intel_lvds.c

254

assert_pll_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_lvds.c

257

intel_lvds_pps_init_hw(display, &lvds_encoder->init_pps);

drivers/gpu/drm/i915/display/intel_lvds.c

262

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_lvds.c

297

if (DISPLAY_VER(display) == 4) {

drivers/gpu/drm/i915/display/intel_lvds.c

313

intel_de_write(display, lvds_encoder->reg, temp);

drivers/gpu/drm/i915/display/intel_lvds.c

324

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lvds.c

327

intel_de_rmw(display, lvds_encoder->reg, 0, LVDS_PORT_EN);

drivers/gpu/drm/i915/display/intel_lvds.c

329

intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON);

drivers/gpu/drm/i915/display/intel_lvds.c

330

intel_de_posting_read(display, lvds_encoder->reg);

drivers/gpu/drm/i915/display/intel_lvds.c

332

if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON, 5000))

drivers/gpu/drm/i915/display/intel_lvds.c

333

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

344

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lvds.c

347

intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0);

drivers/gpu/drm/i915/display/intel_lvds.c

348

if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON, 1000))

drivers/gpu/drm/i915/display/intel_lvds.c

349

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

352

intel_de_rmw(display, lvds_encoder->reg, LVDS_PORT_EN, 0);

drivers/gpu/drm/i915/display/intel_lvds.c

353

intel_de_posting_read(display, lvds_encoder->reg);

drivers/gpu/drm/i915/display/intel_lvds.c

385

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lvds.c

387

if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))

drivers/gpu/drm/i915/display/intel_lvds.c

388

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

396

struct intel_display *display = to_intel_display(_connector->dev);

drivers/gpu/drm/i915/display/intel_lvds.c

400

int max_pixclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_lvds.c

403

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_lvds.c

421

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_lvds.c

430

if (DISPLAY_VER(display) < 4 && crtc->pipe == 0) {

drivers/gpu/drm/i915/display/intel_lvds.c

431

drm_err(display->drm, "Can't support LVDS on pipe A\n");

drivers/gpu/drm/i915/display/intel_lvds.c

435

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_lvds.c

448

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

776

struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lvds.c

780

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_lvds.c

788

bool intel_is_dual_link_lvds(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lvds.c

790

struct intel_encoder *encoder = intel_get_lvds_encoder(display);

drivers/gpu/drm/i915/display/intel_lvds.c

797

struct intel_display *display = to_intel_display(&lvds_encoder->base);

drivers/gpu/drm/i915/display/intel_lvds.c

804

if (display->params.lvds_channel_mode > 0)

drivers/gpu/drm/i915/display/intel_lvds.c

805

return display->params.lvds_channel_mode == 2;

drivers/gpu/drm/i915/display/intel_lvds.c

820

val = intel_de_read(display, lvds_encoder->reg);

drivers/gpu/drm/i915/display/intel_lvds.c

821

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_lvds.c

843

void intel_lvds_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lvds.c

855

drm_WARN(display->drm, !display->vbt.int_lvds_support,

drivers/gpu/drm/i915/display/intel_lvds.c

860

if (!display->vbt.int_lvds_support) {

drivers/gpu/drm/i915/display/intel_lvds.c

861

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

866

if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_lvds.c

87

bool intel_lvds_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lvds.c

871

lvds = intel_de_read(display, lvds_reg);

drivers/gpu/drm/i915/display/intel_lvds.c

873

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_lvds.c

879

if (!intel_bios_is_lvds_present(display, &ddc_pin)) {

drivers/gpu/drm/i915/display/intel_lvds.c

881

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

885

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_lvds.c

902

drm_connector_init_with_ddc(display->drm, &connector->base,

drivers/gpu/drm/i915/display/intel_lvds.c

905

intel_gmbus_get_adapter(display, ddc_pin));

drivers/gpu/drm/i915/display/intel_lvds.c

907

drm_encoder_init(display->drm, &encoder->base, &intel_lvds_enc_funcs,

drivers/gpu/drm/i915/display/intel_lvds.c

913

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_lvds.c

92

val = intel_de_read(display, lvds_reg);

drivers/gpu/drm/i915/display/intel_lvds.c

931

if (DISPLAY_VER(display) < 4)

drivers/gpu/drm/i915/display/intel_lvds.c

943

intel_lvds_pps_get_hw_state(display, &lvds_encoder->init_pps);

drivers/gpu/drm/i915/display/intel_lvds.c

95

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_lvds.c

958

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_lvds.c

973

intel_bios_init_panel_late(display, &connector->panel, NULL,

drivers/gpu/drm/i915/display/intel_lvds.c

991

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_lvds.h

17

bool intel_lvds_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lvds.h

19

void intel_lvds_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_lvds.h

20

struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_lvds.h

21

bool intel_is_dual_link_lvds(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_lvds.h

23

static inline bool intel_lvds_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_lvds.h

28

static inline void intel_lvds_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lvds.h

31

static inline struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_lvds.h

35

static inline bool intel_is_dual_link_lvds(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

1005

if (drm_WARN_ON(display->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))

drivers/gpu/drm/i915/display/intel_modeset_setup.c

1009

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

1011

intel_power_domains_sanitize_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

123

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

125

to_intel_pmdemand_state(display->pmdemand.obj.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

129

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

135

intel_pmdemand_update_phys_mask(display, encoder,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

148

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

151

for_each_encoder_on_crtc(display->drm, &crtc->base, encoder) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

159

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

161

to_intel_pmdemand_state(display->pmdemand.obj.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

173

intel_update_watermarks(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

175

intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

182

intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

189

static u8 get_transcoder_pipes(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

195

for_each_intel_crtc(display->drm, temp_crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

219

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

238

*master_pipe_mask = get_transcoder_pipes(display, BIT(master_transcoder));

drivers/gpu/drm/i915/display/intel_modeset_setup.c

239

drm_WARN_ON(display->drm, !is_power_of_2(*master_pipe_mask));

drivers/gpu/drm/i915/display/intel_modeset_setup.c

241

master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

243

*slave_pipes_mask = get_transcoder_pipes(display, master_crtc_state->sync_mode_slaves_mask);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

246

static u8 get_joiner_secondary_pipes(struct intel_display *display, u8 primary_pipes_mask)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

251

for_each_intel_crtc_in_pipe_mask(display->drm, primary_crtc, primary_pipes_mask) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

264

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

272

joiner_secondaries_mask = get_joiner_secondary_pipes(display,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

276

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

281

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, joiner_secondaries_mask)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

284

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_slaves_mask)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

287

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_master_mask)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

290

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

297

static void intel_modeset_update_connector_atomic_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

302

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

324

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

337

if (DISPLAY_INFO(display)->color.degamma_lut_size) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

352

drm_WARN_ON(display->drm, crtc_state->post_csc_lut &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

371

intel_sanitize_plane_mapping(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

375

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

378

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

390

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

394

plane_crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

427

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

43

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

432

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

446

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

462

intel_init_fifo_underrun_reporting(display, crtc,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

464

!HAS_GMCH(display));

drivers/gpu/drm/i915/display/intel_modeset_setup.c

470

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

478

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

519

static void intel_sanitize_all_crtcs(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

534

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

54

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

547

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

557

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

569

return display->platform.sandybridge &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

577

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

583

to_intel_pmdemand_state(display->pmdemand.obj.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

594

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

602

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

608

intel_pmdemand_update_phys_mask(display, encoder,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

619

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

62

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

64

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

653

if (HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_modeset_setup.c

658

static void readout_plane_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

663

for_each_intel_plane(display->drm, plane) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

672

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

677

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

683

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

691

static void intel_modeset_readout_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

694

to_intel_pmdemand_state(display->pmdemand.obj.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

701

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

716

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

722

readout_plane_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

724

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

730

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

74

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

743

for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

752

intel_pmdemand_update_phys_mask(display, encoder,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

756

intel_pmdemand_update_phys_mask(display, encoder,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

766

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

773

intel_dpll_readout_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

775

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

809

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

816

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

83

drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

839

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

855

if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

86

display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

862

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

870

drm_dbg_kms(display->drm, "[CRTC:%d:%s] min_cdclk %d kHz\n",

drivers/gpu/drm/i915/display/intel_modeset_setup.c

873

intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

878

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

879

intel_wm_get_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

881

intel_bw_update_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

882

intel_dbuf_bw_update_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

883

intel_cdclk_update_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

885

intel_pmdemand_init_pmdemand_params(display, pmdemand_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

889

get_encoder_power_domains(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

893

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

90

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

911

static void intel_early_display_was(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

917

if (IS_DISPLAY_VER(display, 10, 12))

drivers/gpu/drm/i915/display/intel_modeset_setup.c

918

intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

924

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

925

intel_de_rmw(display, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

927

if (display->platform.kabylake || display->platform.coffeelake ||

drivers/gpu/drm/i915/display/intel_modeset_setup.c

928

display->platform.cometlake) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

930

intel_de_rmw(display, CHICKEN_PAR1_1,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

932

intel_de_rmw(display, CHICKEN_MISC_2,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

938

void intel_modeset_setup_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

945

wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

947

intel_early_display_was(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

948

intel_vga_disable(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

950

intel_modeset_readout_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

953

get_encoder_power_domains(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

955

intel_pch_sanitize(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

957

intel_cmtg_sanitize(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

963

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

977

intel_fbc_sanitize(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

979

intel_sanitize_plane_mapping(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

981

for_each_intel_encoder(display->drm, encoder)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

988

intel_modeset_update_connector_atomic_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

990

intel_sanitize_all_crtcs(display, ctx);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

992

intel_dpll_sanitize_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

995

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

996

intel_wm_get_hw_state(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

997

intel_wm_sanitize(display);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

999

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/intel_modeset_setup.h

12

void intel_modeset_setup_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

106

drm_WARN(display->drm, abs(fdi_dotclock - dotclock) > 1,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

115

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

121

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_modeset_verify.c

125

drm_dbg_kms(display->drm, "[ENCODER:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_modeset_verify.c

140

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

148

INTEL_DISPLAY_STATE_WARN(display, !!encoder->base.crtc != enabled,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

156

INTEL_DISPLAY_STATE_WARN(display, active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

167

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

178

drm_dbg_kms(display->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

186

if (display->platform.i830 && hw_crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_modeset_verify.c

189

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

194

INTEL_DISPLAY_STATE_WARN(display, crtc->active != sw_crtc_state->hw.active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

200

for_each_encoder_on_crtc(display->drm, &primary_crtc->base, encoder) {

drivers/gpu/drm/i915/display/intel_modeset_verify.c

205

INTEL_DISPLAY_STATE_WARN(display, active != sw_crtc_state->hw.active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

210

INTEL_DISPLAY_STATE_WARN(display, active && primary_crtc->pipe != pipe,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

225

INTEL_DISPLAY_STATE_WARN(display, 1, "pipe state doesn't match!\n");

drivers/gpu/drm/i915/display/intel_modeset_verify.c

32

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

34

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_modeset_verify.c

40

INTEL_DISPLAY_STATE_WARN(display, !crtc_state,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

46

INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

52

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

56

INTEL_DISPLAY_STATE_WARN(display, conn_state->crtc != encoder->base.crtc,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

59

INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

61

INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

70

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

87

INTEL_DISPLAY_STATE_WARN(display, new_conn_state->best_encoder != encoder,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

94

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

97

int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),

drivers/gpu/drm/i915/display/intel_opregion.c

1005

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

1023

if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {

drivers/gpu/drm/i915/display/intel_opregion.c

1024

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

1029

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

1040

display->opregion = NULL;

drivers/gpu/drm/i915/display/intel_opregion.c

1063

intel_opregion_get_panel_type(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1068

ret = swsci(display, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);

drivers/gpu/drm/i915/display/intel_opregion.c

1074

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

1081

drm_dbg_kms(display->drm, "No panel type in OpRegion\n");

drivers/gpu/drm/i915/display/intel_opregion.c

1091

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

1112

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_opregion.c

1113

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1131

drm_dbg_kms(display->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");

drivers/gpu/drm/i915/display/intel_opregion.c

1139

bool intel_opregion_vbt_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1141

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1149

const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size)

drivers/gpu/drm/i915/display/intel_opregion.c

1151

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1162

bool intel_opregion_headless_sku(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1164

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1179

void intel_opregion_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1181

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1192

intel_opregion_resume(display);

drivers/gpu/drm/i915/display/intel_opregion.c

1195

static void intel_opregion_resume_display(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1197

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1200

intel_didl_outputs(display);

drivers/gpu/drm/i915/display/intel_opregion.c

1201

intel_setup_cadls(display);

drivers/gpu/drm/i915/display/intel_opregion.c

1218

intel_dsm_get_bios_data_funcs_supported(display);

drivers/gpu/drm/i915/display/intel_opregion.c

1221

void intel_opregion_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1223

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1228

if (HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_opregion.c

1229

intel_opregion_resume_display(display);

drivers/gpu/drm/i915/display/intel_opregion.c

1231

intel_opregion_notify_adapter(display, PCI_D0);

drivers/gpu/drm/i915/display/intel_opregion.c

1234

static void intel_opregion_suspend_display(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1236

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1247

void intel_opregion_suspend(struct intel_display *display, pci_power_t state)

drivers/gpu/drm/i915/display/intel_opregion.c

1249

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1254

intel_opregion_notify_adapter(display, state);

drivers/gpu/drm/i915/display/intel_opregion.c

1256

if (HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_opregion.c

1257

intel_opregion_suspend_display(display);

drivers/gpu/drm/i915/display/intel_opregion.c

1260

void intel_opregion_unregister(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1262

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1264

intel_opregion_suspend(display, PCI_D1);

drivers/gpu/drm/i915/display/intel_opregion.c

1275

void intel_opregion_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1277

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1286

display->opregion = NULL;

drivers/gpu/drm/i915/display/intel_opregion.c

1291

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_opregion.c

1292

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

1302

void intel_opregion_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

1304

debugfs_create_file("i915_opregion", 0444, display->drm->debugfs_root,

drivers/gpu/drm/i915/display/intel_opregion.c

1305

display, &intel_opregion_fops);

drivers/gpu/drm/i915/display/intel_opregion.c

259

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_opregion.c

275

static int check_swsci_function(struct intel_display *display, u32 function)

drivers/gpu/drm/i915/display/intel_opregion.c

277

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

307

static int swsci(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_opregion.c

311

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_opregion.c

316

ret = check_swsci_function(display, function);

drivers/gpu/drm/i915/display/intel_opregion.c

320

swsci = display->opregion->swsci;

drivers/gpu/drm/i915/display/intel_opregion.c

338

drm_dbg(display->drm, "SWSCI request already in progress\n");

drivers/gpu/drm/i915/display/intel_opregion.c

364

drm_dbg(display->drm, "SWSCI request timed out\n");

drivers/gpu/drm/i915/display/intel_opregion.c

373

drm_dbg(display->drm, "SWSCI request error %u\n", scic);

drivers/gpu/drm/i915/display/intel_opregion.c

393

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_opregion.c

400

if (!HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_opregion.c

404

ret = check_swsci_function(display, SWSCI_SBCB_DISPLAY_POWER_STATE);

drivers/gpu/drm/i915/display/intel_opregion.c

428

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

453

drm_WARN_ONCE(display->drm, 1,

drivers/gpu/drm/i915/display/intel_opregion.c

461

return swsci(display, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL);

drivers/gpu/drm/i915/display/intel_opregion.c

475

int intel_opregion_notify_adapter(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_opregion.c

480

if (!HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_opregion.c

485

return swsci(display, SWSCI_SBCB_ADAPTER_POWER_STATE,

drivers/gpu/drm/i915/display/intel_opregion.c

492

static u32 asle_set_backlight(struct intel_display *display, u32 bclp)

drivers/gpu/drm/i915/display/intel_opregion.c

496

struct opregion_asle *asle = display->opregion->asle;

drivers/gpu/drm/i915/display/intel_opregion.c

498

drm_dbg(display->drm, "bclp = 0x%08x\n", bclp);

drivers/gpu/drm/i915/display/intel_opregion.c

501

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

513

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

drivers/gpu/drm/i915/display/intel_opregion.c

519

drm_dbg_kms(display->drm, "updating opregion backlight %d/255\n",

drivers/gpu/drm/i915/display/intel_opregion.c

521

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_opregion.c

527

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_opregion.c

533

static u32 asle_set_als_illum(struct intel_display *display, u32 alsi)

drivers/gpu/drm/i915/display/intel_opregion.c

537

drm_dbg(display->drm, "Illum is not supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

541

static u32 asle_set_pwm_freq(struct intel_display *display, u32 pfmb)

drivers/gpu/drm/i915/display/intel_opregion.c

543

drm_dbg(display->drm, "PWM freq is not supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

547

static u32 asle_set_pfit(struct intel_display *display, u32 pfit)

drivers/gpu/drm/i915/display/intel_opregion.c

551

drm_dbg(display->drm, "Pfit is not supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

555

static u32 asle_set_supported_rotation_angles(struct intel_display *display, u32 srot)

drivers/gpu/drm/i915/display/intel_opregion.c

557

drm_dbg(display->drm, "SROT is not supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

561

static u32 asle_set_button_array(struct intel_display *display, u32 iuer)

drivers/gpu/drm/i915/display/intel_opregion.c

564

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

567

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

570

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

573

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

576

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

579

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

585

static u32 asle_set_convertible(struct intel_display *display, u32 iuer)

drivers/gpu/drm/i915/display/intel_opregion.c

588

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

591

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

597

static u32 asle_set_docking(struct intel_display *display, u32 iuer)

drivers/gpu/drm/i915/display/intel_opregion.c

600

drm_dbg(display->drm, "Docking is not supported (docked)\n");

drivers/gpu/drm/i915/display/intel_opregion.c

602

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

608

static u32 asle_isct_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

610

drm_dbg(display->drm, "ISCT is not supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

618

struct intel_display *display = opregion->display;

drivers/gpu/drm/i915/display/intel_opregion.c

629

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

635

aslc_stat |= asle_set_als_illum(display, asle->alsi);

drivers/gpu/drm/i915/display/intel_opregion.c

638

aslc_stat |= asle_set_backlight(display, asle->bclp);

drivers/gpu/drm/i915/display/intel_opregion.c

641

aslc_stat |= asle_set_pfit(display, asle->pfit);

drivers/gpu/drm/i915/display/intel_opregion.c

644

aslc_stat |= asle_set_pwm_freq(display, asle->pfmb);

drivers/gpu/drm/i915/display/intel_opregion.c

647

aslc_stat |= asle_set_supported_rotation_angles(display,

drivers/gpu/drm/i915/display/intel_opregion.c

651

aslc_stat |= asle_set_button_array(display, asle->iuer);

drivers/gpu/drm/i915/display/intel_opregion.c

654

aslc_stat |= asle_set_convertible(display, asle->iuer);

drivers/gpu/drm/i915/display/intel_opregion.c

657

aslc_stat |= asle_set_docking(display, asle->iuer);

drivers/gpu/drm/i915/display/intel_opregion.c

660

aslc_stat |= asle_isct_state(display);

drivers/gpu/drm/i915/display/intel_opregion.c

665

bool intel_opregion_asle_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

667

return display->opregion && display->opregion->asle;

drivers/gpu/drm/i915/display/intel_opregion.c

670

void intel_opregion_asle_intr(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

672

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

675

queue_work(display->wq.unordered, &opregion->asle_work);

drivers/gpu/drm/i915/display/intel_opregion.c

729

static void intel_didl_outputs(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

731

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

746

intel_acpi_device_id_update(display);

drivers/gpu/drm/i915/display/intel_opregion.c

748

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_opregion.c

756

drm_dbg_kms(display->drm, "%d outputs detected\n", i);

drivers/gpu/drm/i915/display/intel_opregion.c

759

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

768

static void intel_setup_cadls(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

770

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

785

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_opregion.c

798

static void swsci_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

800

struct intel_opregion *opregion = display->opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

809

if (swsci(display, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {

drivers/gpu/drm/i915/display/intel_opregion.c

820

if (swsci(display, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {

drivers/gpu/drm/i915/display/intel_opregion.c

831

if (swsci(display, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {

drivers/gpu/drm/i915/display/intel_opregion.c

841

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

851

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.c

876

int intel_opregion_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.c

879

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_opregion.c

894

drm_dbg(display->drm, "graphic opregion physical addr: 0x%x\n",

drivers/gpu/drm/i915/display/intel_opregion.c

897

drm_dbg(display->drm, "ACPI OpRegion not supported!\n");

drivers/gpu/drm/i915/display/intel_opregion.c

905

opregion->display = display;

drivers/gpu/drm/i915/display/intel_opregion.c

906

display->opregion = opregion;

drivers/gpu/drm/i915/display/intel_opregion.c

919

drm_dbg(display->drm, "opregion signature mismatch\n");

drivers/gpu/drm/i915/display/intel_opregion.c

925

drm_dbg(display->drm, "ACPI OpRegion version %u.%u.%u\n",

drivers/gpu/drm/i915/display/intel_opregion.c

932

drm_dbg(display->drm, "Public ACPI methods supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

947

drm_err(display->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n");

drivers/gpu/drm/i915/display/intel_opregion.c

950

drm_dbg(display->drm, "SWSCI Mailbox #2 present for opregion v2.x\n");

drivers/gpu/drm/i915/display/intel_opregion.c

951

drm_dbg(display->drm, "SWSCI supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

953

swsci_setup(display);

drivers/gpu/drm/i915/display/intel_opregion.c

958

drm_dbg(display->drm, "ASLE supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

965

drm_dbg(display->drm, "ASLE extension supported\n");

drivers/gpu/drm/i915/display/intel_opregion.c

970

drm_dbg(display->drm, "Mailbox #2 for backlight present\n");

drivers/gpu/drm/i915/display/intel_opregion.c

988

drm_WARN_ON(display->drm, rvda < OPREGION_SIZE);

drivers/gpu/drm/i915/display/intel_opregion.c

998

if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {

drivers/gpu/drm/i915/display/intel_opregion.c

999

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_opregion.h

107

intel_opregion_notify_adapter(struct intel_display *display, pci_power_t state)

drivers/gpu/drm/i915/display/intel_opregion.h

112

static inline int intel_opregion_get_panel_type(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

123

static inline bool intel_opregion_vbt_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

129

intel_opregion_get_vbt(struct intel_display *display, size_t *size)

drivers/gpu/drm/i915/display/intel_opregion.h

134

static inline bool intel_opregion_headless_sku(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

139

static inline void intel_opregion_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

37

int intel_opregion_setup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

38

void intel_opregion_cleanup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

40

void intel_opregion_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

41

void intel_opregion_unregister(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

43

void intel_opregion_resume(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

44

void intel_opregion_suspend(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_opregion.h

47

bool intel_opregion_asle_present(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

48

void intel_opregion_asle_intr(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

51

int intel_opregion_notify_adapter(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_opregion.h

53

int intel_opregion_get_panel_type(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

56

bool intel_opregion_vbt_present(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

57

const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size);

drivers/gpu/drm/i915/display/intel_opregion.h

59

bool intel_opregion_headless_sku(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

61

void intel_opregion_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_opregion.h

65

static inline int intel_opregion_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

70

static inline void intel_opregion_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

74

static inline void intel_opregion_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

78

static inline void intel_opregion_unregister(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

82

static inline void intel_opregion_resume(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

86

static inline void intel_opregion_suspend(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_opregion.h

91

static inline bool intel_opregion_asle_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_opregion.h

96

static inline void intel_opregion_asle_intr(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.c

1007

static int check_overlay_src(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_overlay.c

1018

if (display->platform.i845g || display->platform.i830) {

drivers/gpu/drm/i915/display/intel_overlay.c

1070

if (display->platform.i830 || display->platform.i845g)

drivers/gpu/drm/i915/display/intel_overlay.c

1077

if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512)

drivers/gpu/drm/i915/display/intel_overlay.c

1121

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_overlay.c

1129

overlay = display->overlay;

drivers/gpu/drm/i915/display/intel_overlay.c

1131

drm_dbg(display->drm, "userspace bug: no overlay\n");

drivers/gpu/drm/i915/display/intel_overlay.c

1155

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_overlay.c

1204

ret = check_overlay_src(display, params, new_bo);

drivers/gpu/drm/i915/display/intel_overlay.c

1284

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_overlay.c

1289

overlay = display->overlay;

drivers/gpu/drm/i915/display/intel_overlay.c

1291

drm_dbg(display->drm, "userspace bug: no overlay\n");

drivers/gpu/drm/i915/display/intel_overlay.c

1304

if (DISPLAY_VER(display) != 2) {

drivers/gpu/drm/i915/display/intel_overlay.c

1305

attrs->gamma0 = intel_de_read(display, OGAMC0);

drivers/gpu/drm/i915/display/intel_overlay.c

1306

attrs->gamma1 = intel_de_read(display, OGAMC1);

drivers/gpu/drm/i915/display/intel_overlay.c

1307

attrs->gamma2 = intel_de_read(display, OGAMC2);

drivers/gpu/drm/i915/display/intel_overlay.c

1308

attrs->gamma3 = intel_de_read(display, OGAMC3);

drivers/gpu/drm/i915/display/intel_overlay.c

1309

attrs->gamma4 = intel_de_read(display, OGAMC4);

drivers/gpu/drm/i915/display/intel_overlay.c

1310

attrs->gamma5 = intel_de_read(display, OGAMC5);

drivers/gpu/drm/i915/display/intel_overlay.c

1328

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_overlay.c

1340

intel_de_write(display, OGAMC0, attrs->gamma0);

drivers/gpu/drm/i915/display/intel_overlay.c

1341

intel_de_write(display, OGAMC1, attrs->gamma1);

drivers/gpu/drm/i915/display/intel_overlay.c

1342

intel_de_write(display, OGAMC2, attrs->gamma2);

drivers/gpu/drm/i915/display/intel_overlay.c

1343

intel_de_write(display, OGAMC3, attrs->gamma3);

drivers/gpu/drm/i915/display/intel_overlay.c

1344

intel_de_write(display, OGAMC4, attrs->gamma4);

drivers/gpu/drm/i915/display/intel_overlay.c

1345

intel_de_write(display, OGAMC5, attrs->gamma5);

drivers/gpu/drm/i915/display/intel_overlay.c

1359

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

1360

struct drm_i915_private *i915 = to_i915(display->drm);

drivers/gpu/drm/i915/display/intel_overlay.c

1365

if (!display->platform.meteorlake) /* Wa_22018444074 */

drivers/gpu/drm/i915/display/intel_overlay.c

1398

void intel_overlay_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.c

1400

struct drm_i915_private *dev_priv = to_i915(display->drm);

drivers/gpu/drm/i915/display/intel_overlay.c

1405

if (!HAS_OVERLAY(display))

drivers/gpu/drm/i915/display/intel_overlay.c

1416

overlay->display = display;

drivers/gpu/drm/i915/display/intel_overlay.c

1427

ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display));

drivers/gpu/drm/i915/display/intel_overlay.c

1435

display->overlay = overlay;

drivers/gpu/drm/i915/display/intel_overlay.c

1436

drm_info(display->drm, "Initialized overlay support.\n");

drivers/gpu/drm/i915/display/intel_overlay.c

1443

bool intel_overlay_available(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.c

1445

return display->overlay;

drivers/gpu/drm/i915/display/intel_overlay.c

1448

void intel_overlay_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.c

1452

overlay = fetch_and_zero(&display->overlay);

drivers/gpu/drm/i915/display/intel_overlay.c

1461

drm_WARN_ON(display->drm, overlay->active);

drivers/gpu/drm/i915/display/intel_overlay.c

1479

intel_overlay_snapshot_capture(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.c

1481

struct intel_overlay *overlay = display->overlay;

drivers/gpu/drm/i915/display/intel_overlay.c

1491

error->dovsta = intel_de_read(display, DOVSTA);

drivers/gpu/drm/i915/display/intel_overlay.c

1492

error->isr = intel_de_read(display, GEN2_ISR);

drivers/gpu/drm/i915/display/intel_overlay.c

191

struct intel_display *display;

drivers/gpu/drm/i915/display/intel_overlay.c

213

static void i830_overlay_clock_gating(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_overlay.c

216

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_overlay.c

221

intel_de_write(display, DSPCLK_GATE_D, 0);

drivers/gpu/drm/i915/display/intel_overlay.c

223

intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

drivers/gpu/drm/i915/display/intel_overlay.c

260

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

264

drm_WARN_ON(display->drm, overlay->active);

drivers/gpu/drm/i915/display/intel_overlay.c

278

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_overlay.c

279

i830_overlay_clock_gating(display, false);

drivers/gpu/drm/i915/display/intel_overlay.c

295

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

299

drm_WARN_ON(display->drm, overlay->old_vma);

drivers/gpu/drm/i915/display/intel_overlay.c

323

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

328

drm_WARN_ON(display->drm, !overlay->active);

drivers/gpu/drm/i915/display/intel_overlay.c

334

tmp = intel_de_read(display, DOVSTA);

drivers/gpu/drm/i915/display/intel_overlay.c

336

drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp);

drivers/gpu/drm/i915/display/intel_overlay.c

360

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

364

if (drm_WARN_ON(display->drm, !vma))

drivers/gpu/drm/i915/display/intel_overlay.c

367

intel_frontbuffer_flip(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));

drivers/gpu/drm/i915/display/intel_overlay.c

381

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

389

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_overlay.c

390

i830_overlay_clock_gating(display, true);

drivers/gpu/drm/i915/display/intel_overlay.c

405

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

409

drm_WARN_ON(display->drm, !overlay->active);

drivers/gpu/drm/i915/display/intel_overlay.c

463

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

474

if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {

drivers/gpu/drm/i915/display/intel_overlay.c

498

void intel_overlay_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.c

500

struct intel_overlay *overlay = display->overlay;

drivers/gpu/drm/i915/display/intel_overlay.c

561

static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width)

drivers/gpu/drm/i915/display/intel_overlay.c

565

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_overlay.c

800

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

808

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_overlay.c

809

!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));

drivers/gpu/drm/i915/display/intel_overlay.c

815

atomic_inc(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_overlay.c

833

if (DISPLAY_VER(display) == 4)

drivers/gpu/drm/i915/display/intel_overlay.c

854

swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width);

drivers/gpu/drm/i915/display/intel_overlay.c

867

tmp_U = calc_swidthsw(display, params->offset_U,

drivers/gpu/drm/i915/display/intel_overlay.c

869

tmp_V = calc_swidthsw(display, params->offset_V,

drivers/gpu/drm/i915/display/intel_overlay.c

901

atomic_dec(&display->restore.pending_fb_pin);

drivers/gpu/drm/i915/display/intel_overlay.c

908

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

911

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_overlay.c

912

!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));

drivers/gpu/drm/i915/display/intel_overlay.c

945

struct intel_display *display = overlay->display;

drivers/gpu/drm/i915/display/intel_overlay.c

951

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_overlay.c

952

u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

drivers/gpu/drm/i915/display/intel_overlay.c

959

if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)

drivers/gpu/drm/i915/display/intel_overlay.c

960

tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));

drivers/gpu/drm/i915/display/intel_overlay.c

962

tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

drivers/gpu/drm/i915/display/intel_overlay.h

19

void intel_overlay_setup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_overlay.h

20

bool intel_overlay_available(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_overlay.h

21

void intel_overlay_cleanup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_overlay.h

27

void intel_overlay_reset(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_overlay.h

29

static inline void intel_overlay_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.h

32

static inline bool intel_overlay_available(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.h

36

static inline void intel_overlay_cleanup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.h

53

static inline void intel_overlay_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_overlay.h

60

intel_overlay_snapshot_capture(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_overlay.h

65

intel_overlay_snapshot_capture(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_panel.c

252

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

261

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_panel.c

272

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

290

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_panel.c

303

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

307

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_panel.c

312

drm_mode_destroy(display->drm, mode);

drivers/gpu/drm/i915/display/intel_panel.c

329

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

340

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s fixed mode: " DRM_MODE_FMT "\n",

drivers/gpu/drm/i915/display/intel_panel.c

349

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

357

drm_mode_duplicate(display->drm, mode),

drivers/gpu/drm/i915/display/intel_panel.c

363

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

371

drm_mode_duplicate(display->drm, mode),

drivers/gpu/drm/i915/display/intel_panel.c

386

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_panel.c

388

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_panel.c

391

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_panel.c

47

bool intel_panel_use_ssc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_panel.c

478

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

483

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

drivers/gpu/drm/i915/display/intel_panel.c

49

if (display->params.panel_use_ssc >= 0)

drivers/gpu/drm/i915/display/intel_panel.c

496

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Panel prepare\n",

drivers/gpu/drm/i915/display/intel_panel.c

50

return display->params.panel_use_ssc != 0;

drivers/gpu/drm/i915/display/intel_panel.c

502

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

drivers/gpu/drm/i915/display/intel_panel.c

51

return display->vbt.lvds_use_ssc &&

drivers/gpu/drm/i915/display/intel_panel.c

510

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_panel.c

52

!intel_has_quirk(display, QUIRK_LVDS_SSC_DISABLE);

drivers/gpu/drm/i915/display/intel_panel.c

524

if (drm_WARN_ON(display->drm, !dev))

drivers/gpu/drm/i915/display/intel_panel.c

553

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Registered panel device '%s', has fwnode: %s\n",

drivers/gpu/drm/i915/display/intel_panel.h

30

bool intel_panel_use_ssc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.c

101

void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence)

drivers/gpu/drm/i915/display/intel_parent.c

103

if (display->parent->rps)

drivers/gpu/drm/i915/display/intel_parent.c

104

display->parent->rps->boost_if_not_started(fence);

drivers/gpu/drm/i915/display/intel_parent.c

107

void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive)

drivers/gpu/drm/i915/display/intel_parent.c

109

if (display->parent->rps)

drivers/gpu/drm/i915/display/intel_parent.c

110

display->parent->rps->mark_interactive(display->drm, interactive);

drivers/gpu/drm/i915/display/intel_parent.c

113

void intel_parent_rps_ilk_irq_handler(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

115

if (display->parent->rps)

drivers/gpu/drm/i915/display/intel_parent.c

116

display->parent->rps->ilk_irq_handler(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

120

int intel_parent_stolen_insert_node_in_range(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.c

124

return display->parent->stolen->insert_node_in_range(node, size, align, start, end);

drivers/gpu/drm/i915/display/intel_parent.c

127

int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size,

drivers/gpu/drm/i915/display/intel_parent.c

130

if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->insert_node))

drivers/gpu/drm/i915/display/intel_parent.c

133

return display->parent->stolen->insert_node(node, size, align);

drivers/gpu/drm/i915/display/intel_parent.c

136

void intel_parent_stolen_remove_node(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.c

139

display->parent->stolen->remove_node(node);

drivers/gpu/drm/i915/display/intel_parent.c

142

bool intel_parent_stolen_initialized(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

144

return display->parent->stolen->initialized(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

147

bool intel_parent_stolen_node_allocated(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.c

150

return display->parent->stolen->node_allocated(node);

drivers/gpu/drm/i915/display/intel_parent.c

153

u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node)

drivers/gpu/drm/i915/display/intel_parent.c

155

return display->parent->stolen->node_offset(node);

drivers/gpu/drm/i915/display/intel_parent.c

158

u64 intel_parent_stolen_area_address(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

160

if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_address))

drivers/gpu/drm/i915/display/intel_parent.c

163

return display->parent->stolen->area_address(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

166

u64 intel_parent_stolen_area_size(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

168

if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_size))

drivers/gpu/drm/i915/display/intel_parent.c

171

return display->parent->stolen->area_size(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

174

u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node)

drivers/gpu/drm/i915/display/intel_parent.c

176

return display->parent->stolen->node_address(node);

drivers/gpu/drm/i915/display/intel_parent.c

179

u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node)

drivers/gpu/drm/i915/display/intel_parent.c

181

return display->parent->stolen->node_size(node);

drivers/gpu/drm/i915/display/intel_parent.c

184

struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

186

return display->parent->stolen->node_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

189

void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node)

drivers/gpu/drm/i915/display/intel_parent.c

191

display->parent->stolen->node_free(node);

drivers/gpu/drm/i915/display/intel_parent.c

195

void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence)

drivers/gpu/drm/i915/display/intel_parent.c

197

if (display->parent->fence_priority_display)

drivers/gpu/drm/i915/display/intel_parent.c

198

display->parent->fence_priority_display(fence);

drivers/gpu/drm/i915/display/intel_parent.c

201

bool intel_parent_has_auxccs(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

203

return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

206

bool intel_parent_has_fenced_regions(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

208

return display->parent->has_fenced_regions && display->parent->has_fenced_regions(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

211

bool intel_parent_vgpu_active(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

213

return display->parent->vgpu_active && display->parent->vgpu_active(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

27

ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.c

32

return display->parent->hdcp->gsc_msg_send(gsc_context, msg_in, msg_in_len, msg_out, msg_out_len);

drivers/gpu/drm/i915/display/intel_parent.c

35

bool intel_parent_hdcp_gsc_check_status(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

37

return display->parent->hdcp->gsc_check_status(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

40

struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

42

return display->parent->hdcp->gsc_context_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

45

void intel_parent_hdcp_gsc_context_free(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.c

48

display->parent->hdcp->gsc_context_free(gsc_context);

drivers/gpu/drm/i915/display/intel_parent.c

52

bool intel_parent_irq_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

54

return display->parent->irq->enabled(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

57

void intel_parent_irq_synchronize(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

59

display->parent->irq->synchronize(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

63

struct intel_panic *intel_parent_panic_alloc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

65

return display->parent->panic->alloc();

drivers/gpu/drm/i915/display/intel_parent.c

68

int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb)

drivers/gpu/drm/i915/display/intel_parent.c

70

return display->parent->panic->setup(panic, sb);

drivers/gpu/drm/i915/display/intel_parent.c

73

void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic)

drivers/gpu/drm/i915/display/intel_parent.c

75

display->parent->panic->finish(panic);

drivers/gpu/drm/i915/display/intel_parent.c

79

void intel_parent_pc8_block(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

81

if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8))

drivers/gpu/drm/i915/display/intel_parent.c

84

display->parent->pc8->block(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

87

void intel_parent_pc8_unblock(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

89

if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8))

drivers/gpu/drm/i915/display/intel_parent.c

92

display->parent->pc8->unblock(display->drm);

drivers/gpu/drm/i915/display/intel_parent.c

96

bool intel_parent_rps_available(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_parent.c

98

return display->parent->rps;

drivers/gpu/drm/i915/display/intel_parent.h

17

ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.h

21

bool intel_parent_hdcp_gsc_check_status(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

22

struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

23

void intel_parent_hdcp_gsc_context_free(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.h

27

bool intel_parent_irq_enabled(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

28

void intel_parent_irq_synchronize(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

31

struct intel_panic *intel_parent_panic_alloc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

32

int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb);

drivers/gpu/drm/i915/display/intel_parent.h

33

void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic);

drivers/gpu/drm/i915/display/intel_parent.h

36

void intel_parent_pc8_block(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

37

void intel_parent_pc8_unblock(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

40

bool intel_parent_rps_available(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

41

void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence);

drivers/gpu/drm/i915/display/intel_parent.h

42

void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive);

drivers/gpu/drm/i915/display/intel_parent.h

43

void intel_parent_rps_ilk_irq_handler(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

46

int intel_parent_stolen_insert_node_in_range(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.h

49

int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size,

drivers/gpu/drm/i915/display/intel_parent.h

51

void intel_parent_stolen_remove_node(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.h

53

bool intel_parent_stolen_initialized(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

54

bool intel_parent_stolen_node_allocated(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_parent.h

56

u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node);

drivers/gpu/drm/i915/display/intel_parent.h

57

u64 intel_parent_stolen_area_address(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

58

u64 intel_parent_stolen_area_size(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

59

u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node);

drivers/gpu/drm/i915/display/intel_parent.h

60

u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node);

drivers/gpu/drm/i915/display/intel_parent.h

61

struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

62

void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node);

drivers/gpu/drm/i915/display/intel_parent.h

65

bool intel_parent_has_auxccs(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

66

bool intel_parent_has_fenced_regions(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

67

bool intel_parent_vgpu_active(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_parent.h

68

void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);

drivers/gpu/drm/i915/display/intel_pch.c

100

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

101

!display->platform.haswell_ult &&

drivers/gpu/drm/i915/display/intel_pch.c

102

!display->platform.broadwell_ult);

drivers/gpu/drm/i915/display/intel_pch.c

105

drm_dbg_kms(display->drm, "Found WildcatPoint PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

106

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

107

!display->platform.haswell &&

drivers/gpu/drm/i915/display/intel_pch.c

108

!display->platform.broadwell);

drivers/gpu/drm/i915/display/intel_pch.c

109

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

110

display->platform.haswell_ult ||

drivers/gpu/drm/i915/display/intel_pch.c

111

display->platform.broadwell_ult);

drivers/gpu/drm/i915/display/intel_pch.c

115

drm_dbg_kms(display->drm, "Found WildcatPoint LP PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

116

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

117

!display->platform.haswell &&

drivers/gpu/drm/i915/display/intel_pch.c

118

!display->platform.broadwell);

drivers/gpu/drm/i915/display/intel_pch.c

119

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

120

!display->platform.haswell_ult &&

drivers/gpu/drm/i915/display/intel_pch.c

121

!display->platform.broadwell_ult);

drivers/gpu/drm/i915/display/intel_pch.c

125

drm_dbg_kms(display->drm, "Found SunrisePoint PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

126

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

127

!display->platform.skylake &&

drivers/gpu/drm/i915/display/intel_pch.c

128

!display->platform.kabylake &&

drivers/gpu/drm/i915/display/intel_pch.c

129

!display->platform.coffeelake);

drivers/gpu/drm/i915/display/intel_pch.c

132

drm_dbg_kms(display->drm, "Found SunrisePoint LP PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

133

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

134

!display->platform.skylake &&

drivers/gpu/drm/i915/display/intel_pch.c

135

!display->platform.kabylake &&

drivers/gpu/drm/i915/display/intel_pch.c

136

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

137

!display->platform.cometlake);

drivers/gpu/drm/i915/display/intel_pch.c

140

drm_dbg_kms(display->drm, "Found Kaby Lake PCH (KBP)\n");

drivers/gpu/drm/i915/display/intel_pch.c

141

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

142

!display->platform.skylake &&

drivers/gpu/drm/i915/display/intel_pch.c

143

!display->platform.kabylake &&

drivers/gpu/drm/i915/display/intel_pch.c

144

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

145

!display->platform.cometlake);

drivers/gpu/drm/i915/display/intel_pch.c

149

drm_dbg_kms(display->drm, "Found Cannon Lake PCH (CNP)\n");

drivers/gpu/drm/i915/display/intel_pch.c

150

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

151

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

152

!display->platform.cometlake);

drivers/gpu/drm/i915/display/intel_pch.c

155

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

157

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

158

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

159

!display->platform.cometlake);

drivers/gpu/drm/i915/display/intel_pch.c

163

drm_dbg_kms(display->drm, "Found Comet Lake PCH (CMP)\n");

drivers/gpu/drm/i915/display/intel_pch.c

164

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

165

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

166

!display->platform.cometlake &&

drivers/gpu/drm/i915/display/intel_pch.c

167

!display->platform.rocketlake);

drivers/gpu/drm/i915/display/intel_pch.c

171

drm_dbg_kms(display->drm, "Found Comet Lake V PCH (CMP-V)\n");

drivers/gpu/drm/i915/display/intel_pch.c

172

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

173

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

174

!display->platform.cometlake);

drivers/gpu/drm/i915/display/intel_pch.c

179

drm_dbg_kms(display->drm, "Found Ice Lake PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

180

drm_WARN_ON(display->drm, !display->platform.icelake);

drivers/gpu/drm/i915/display/intel_pch.c

183

drm_dbg_kms(display->drm, "Found Mule Creek Canyon PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

184

drm_WARN_ON(display->drm, !(display->platform.jasperlake ||

drivers/gpu/drm/i915/display/intel_pch.c

185

display->platform.elkhartlake));

drivers/gpu/drm/i915/display/intel_pch.c

190

drm_dbg_kms(display->drm, "Found Tiger Lake LP PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

191

drm_WARN_ON(display->drm, !display->platform.tigerlake &&

drivers/gpu/drm/i915/display/intel_pch.c

192

!display->platform.rocketlake &&

drivers/gpu/drm/i915/display/intel_pch.c

193

!display->platform.skylake &&

drivers/gpu/drm/i915/display/intel_pch.c

194

!display->platform.kabylake &&

drivers/gpu/drm/i915/display/intel_pch.c

195

!display->platform.coffeelake &&

drivers/gpu/drm/i915/display/intel_pch.c

196

!display->platform.cometlake);

drivers/gpu/drm/i915/display/intel_pch.c

199

drm_dbg_kms(display->drm, "Found Jasper Lake PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

200

drm_WARN_ON(display->drm, !(display->platform.jasperlake ||

drivers/gpu/drm/i915/display/intel_pch.c

201

display->platform.elkhartlake));

drivers/gpu/drm/i915/display/intel_pch.c

208

drm_dbg_kms(display->drm, "Found Alder Lake PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

209

drm_WARN_ON(display->drm, !display->platform.alderlake_s &&

drivers/gpu/drm/i915/display/intel_pch.c

210

!display->platform.alderlake_p);

drivers/gpu/drm/i915/display/intel_pch.c

228

intel_virt_detect_pch(const struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch.c

240

if (display->platform.alderlake_s || display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_pch.c

242

else if (display->platform.tigerlake || display->platform.rocketlake)

drivers/gpu/drm/i915/display/intel_pch.c

244

else if (display->platform.jasperlake || display->platform.elkhartlake)

drivers/gpu/drm/i915/display/intel_pch.c

246

else if (display->platform.icelake)

drivers/gpu/drm/i915/display/intel_pch.c

248

else if (display->platform.coffeelake ||

drivers/gpu/drm/i915/display/intel_pch.c

249

display->platform.cometlake)

drivers/gpu/drm/i915/display/intel_pch.c

251

else if (display->platform.kabylake || display->platform.skylake)

drivers/gpu/drm/i915/display/intel_pch.c

253

else if (display->platform.haswell_ult ||

drivers/gpu/drm/i915/display/intel_pch.c

254

display->platform.broadwell_ult)

drivers/gpu/drm/i915/display/intel_pch.c

256

else if (display->platform.haswell || display->platform.broadwell)

drivers/gpu/drm/i915/display/intel_pch.c

258

else if (DISPLAY_VER(display) == 6 || display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_pch.c

260

else if (DISPLAY_VER(display) == 5)

drivers/gpu/drm/i915/display/intel_pch.c

264

drm_dbg_kms(display->drm, "Assuming PCH ID %04x\n", id);

drivers/gpu/drm/i915/display/intel_pch.c

266

drm_dbg_kms(display->drm, "Assuming no PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

268

*pch_type = intel_pch_type(display, id);

drivers/gpu/drm/i915/display/intel_pch.c

271

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

278

void intel_pch_detect(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch.c

284

pch_type = intel_pch_fake_for_south_display(display);

drivers/gpu/drm/i915/display/intel_pch.c

286

display->pch_type = pch_type;

drivers/gpu/drm/i915/display/intel_pch.c

287

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

310

pch_type = intel_pch_type(display, id);

drivers/gpu/drm/i915/display/intel_pch.c

312

display->pch_type = pch_type;

drivers/gpu/drm/i915/display/intel_pch.c

316

intel_virt_detect_pch(display, &id, &pch_type);

drivers/gpu/drm/i915/display/intel_pch.c

317

display->pch_type = pch_type;

drivers/gpu/drm/i915/display/intel_pch.c

326

if (pch && !HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_pch.c

327

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

329

display->pch_type = PCH_NOP;

drivers/gpu/drm/i915/display/intel_pch.c

331

if (intel_display_run_as_guest(display) && HAS_DISPLAY(display)) {

drivers/gpu/drm/i915/display/intel_pch.c

332

intel_virt_detect_pch(display, &id, &pch_type);

drivers/gpu/drm/i915/display/intel_pch.c

333

display->pch_type = pch_type;

drivers/gpu/drm/i915/display/intel_pch.c

335

drm_dbg_kms(display->drm, "No PCH found.\n");

drivers/gpu/drm/i915/display/intel_pch.c

48

static enum intel_pch intel_pch_fake_for_south_display(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch.c

52

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_pch.c

54

else if (display->platform.battlemage || display->platform.meteorlake)

drivers/gpu/drm/i915/display/intel_pch.c

56

else if (display->platform.dg2)

drivers/gpu/drm/i915/display/intel_pch.c

58

else if (display->platform.dg1)

drivers/gpu/drm/i915/display/intel_pch.c

66

intel_pch_type(const struct intel_display *display, unsigned short id)

drivers/gpu/drm/i915/display/intel_pch.c

70

drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

71

drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5);

drivers/gpu/drm/i915/display/intel_pch.c

74

drm_dbg_kms(display->drm, "Found CougarPoint PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

75

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

76

DISPLAY_VER(display) != 6 &&

drivers/gpu/drm/i915/display/intel_pch.c

77

!display->platform.ivybridge);

drivers/gpu/drm/i915/display/intel_pch.c

80

drm_dbg_kms(display->drm, "Found PantherPoint PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

81

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

82

DISPLAY_VER(display) != 6 &&

drivers/gpu/drm/i915/display/intel_pch.c

83

!display->platform.ivybridge);

drivers/gpu/drm/i915/display/intel_pch.c

87

drm_dbg_kms(display->drm, "Found LynxPoint PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

88

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

89

!display->platform.haswell &&

drivers/gpu/drm/i915/display/intel_pch.c

90

!display->platform.broadwell);

drivers/gpu/drm/i915/display/intel_pch.c

91

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

92

display->platform.haswell_ult ||

drivers/gpu/drm/i915/display/intel_pch.c

93

display->platform.broadwell_ult);

drivers/gpu/drm/i915/display/intel_pch.c

96

drm_dbg_kms(display->drm, "Found LynxPoint LP PCH\n");

drivers/gpu/drm/i915/display/intel_pch.c

97

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pch.c

98

!display->platform.haswell &&

drivers/gpu/drm/i915/display/intel_pch.c

99

!display->platform.broadwell);

drivers/gpu/drm/i915/display/intel_pch.h

38

#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2)

drivers/gpu/drm/i915/display/intel_pch.h

39

#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP)

drivers/gpu/drm/i915/display/intel_pch.h

40

#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1)

drivers/gpu/drm/i915/display/intel_pch.h

41

#define HAS_PCH_TGP(display) (INTEL_PCH_TYPE(display) == PCH_TGP)

drivers/gpu/drm/i915/display/intel_pch.h

42

#define HAS_PCH_ICP(display) (INTEL_PCH_TYPE(display) == PCH_ICP)

drivers/gpu/drm/i915/display/intel_pch.h

43

#define HAS_PCH_CNP(display) (INTEL_PCH_TYPE(display) == PCH_CNP)

drivers/gpu/drm/i915/display/intel_pch.h

44

#define HAS_PCH_SPT(display) (INTEL_PCH_TYPE(display) == PCH_SPT)

drivers/gpu/drm/i915/display/intel_pch.h

45

#define HAS_PCH_LPT_H(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H)

drivers/gpu/drm/i915/display/intel_pch.h

46

#define HAS_PCH_LPT_LP(display) (INTEL_PCH_TYPE(display) == PCH_LPT_LP)

drivers/gpu/drm/i915/display/intel_pch.h

47

#define HAS_PCH_LPT(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H || \

drivers/gpu/drm/i915/display/intel_pch.h

48

INTEL_PCH_TYPE(display) == PCH_LPT_LP)

drivers/gpu/drm/i915/display/intel_pch.h

49

#define HAS_PCH_CPT(display) (INTEL_PCH_TYPE(display) == PCH_CPT)

drivers/gpu/drm/i915/display/intel_pch.h

50

#define HAS_PCH_IBX(display) (INTEL_PCH_TYPE(display) == PCH_IBX)

drivers/gpu/drm/i915/display/intel_pch.h

51

#define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP)

drivers/gpu/drm/i915/display/intel_pch.h

52

#define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE)

drivers/gpu/drm/i915/display/intel_pch.h

54

void intel_pch_detect(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pch_display.c

100

assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB);

drivers/gpu/drm/i915/display/intel_pch_display.c

101

assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC);

drivers/gpu/drm/i915/display/intel_pch_display.c

102

assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID);

drivers/gpu/drm/i915/display/intel_pch_display.c

105

static void assert_pch_transcoder_disabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

111

val = intel_de_read(display, PCH_TRANSCONF(pipe));

drivers/gpu/drm/i915/display/intel_pch_display.c

113

INTEL_DISPLAY_STATE_WARN(display, enabled,

drivers/gpu/drm/i915/display/intel_pch_display.c

118

static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

121

u32 val = intel_de_read(display, hdmi_reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

127

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch_display.c

134

intel_de_write(display, hdmi_reg, val);

drivers/gpu/drm/i915/display/intel_pch_display.c

137

static void ibx_sanitize_pch_dp_port(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

140

u32 val = intel_de_read(display, dp_reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

146

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch_display.c

153

intel_de_write(display, dp_reg, val);

drivers/gpu/drm/i915/display/intel_pch_display.c

156

static void ibx_sanitize_pch_ports(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_display.c

169

ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B);

drivers/gpu/drm/i915/display/intel_pch_display.c

170

ibx_sanitize_pch_dp_port(display, PORT_C, PCH_DP_C);

drivers/gpu/drm/i915/display/intel_pch_display.c

171

ibx_sanitize_pch_dp_port(display, PORT_D, PCH_DP_D);

drivers/gpu/drm/i915/display/intel_pch_display.c

174

ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB);

drivers/gpu/drm/i915/display/intel_pch_display.c

175

ibx_sanitize_pch_hdmi_port(display, PORT_C, PCH_HDMIC);

drivers/gpu/drm/i915/display/intel_pch_display.c

176

ibx_sanitize_pch_hdmi_port(display, PORT_D, PCH_HDMID);

drivers/gpu/drm/i915/display/intel_pch_display.c

182

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

185

intel_set_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_pch_display.c

193

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

196

intel_set_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_pch_display.c

204

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

207

intel_get_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_pch_display.c

215

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

218

intel_get_m_n(display, m_n,

drivers/gpu/drm/i915/display/intel_pch_display.c

226

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

229

intel_de_write(display, PCH_TRANS_HTOTAL(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

230

intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

231

intel_de_write(display, PCH_TRANS_HBLANK(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

232

intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

233

intel_de_write(display, PCH_TRANS_HSYNC(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

234

intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

236

intel_de_write(display, PCH_TRANS_VTOTAL(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

237

intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

238

intel_de_write(display, PCH_TRANS_VBLANK(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

239

intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

240

intel_de_write(display, PCH_TRANS_VSYNC(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

241

intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

242

intel_de_write(display, PCH_TRANS_VSYNCSHIFT(pch_transcoder),

drivers/gpu/drm/i915/display/intel_pch_display.c

243

intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

248

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

25

bool intel_has_pch_trancoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

255

assert_dpll_enabled(display, crtc_state->intel_dpll);

drivers/gpu/drm/i915/display/intel_pch_display.c

258

assert_fdi_tx_enabled(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

259

assert_fdi_rx_enabled(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

261

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

263

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

272

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_pch_display.c

276

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

277

pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));

drivers/gpu/drm/i915/display/intel_pch_display.c

279

if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

28

return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) ||

drivers/gpu/drm/i915/display/intel_pch_display.c

29

(HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

298

if (HAS_PCH_IBX(display) &&

drivers/gpu/drm/i915/display/intel_pch_display.c

307

intel_de_write(display, reg, val | TRANS_ENABLE);

drivers/gpu/drm/i915/display/intel_pch_display.c

308

if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE, 100))

drivers/gpu/drm/i915/display/intel_pch_display.c

309

drm_err(display->drm, "failed to enable transcoder %c\n",

drivers/gpu/drm/i915/display/intel_pch_display.c

315

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

320

assert_fdi_tx_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

321

assert_fdi_rx_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

324

assert_pch_ports_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

327

intel_de_rmw(display, reg, TRANS_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_pch_display.c

329

if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE, 50))

drivers/gpu/drm/i915/display/intel_pch_display.c

330

drm_err(display->drm, "failed to disable transcoder %c\n",

drivers/gpu/drm/i915/display/intel_pch_display.c

333

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_pch_display.c

335

intel_de_rmw(display, TRANS_CHICKEN2(pipe),

drivers/gpu/drm/i915/display/intel_pch_display.c

34

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

36

if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_pch_display.c

364

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

370

assert_pch_transcoder_disabled(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

379

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

382

temp = intel_de_read(display, PCH_DPLL_SEL);

drivers/gpu/drm/i915/display/intel_pch_display.c

386

intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))

drivers/gpu/drm/i915/display/intel_pch_display.c

390

intel_de_write(display, PCH_DPLL_SEL, temp);

drivers/gpu/drm/i915/display/intel_pch_display.c

405

assert_pps_unlocked(display, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

415

if (HAS_PCH_CPT(display) &&

drivers/gpu/drm/i915/display/intel_pch_display.c

419

u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))

drivers/gpu/drm/i915/display/intel_pch_display.c

42

static void assert_pch_dp_disabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

424

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

438

drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);

drivers/gpu/drm/i915/display/intel_pch_display.c

441

intel_de_write(display, reg, temp);

drivers/gpu/drm/i915/display/intel_pch_display.c

456

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

463

if (HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

465

intel_de_rmw(display, TRANS_DP_CTL(pipe),

drivers/gpu/drm/i915/display/intel_pch_display.c

470

intel_de_rmw(display, PCH_DPLL_SEL,

drivers/gpu/drm/i915/display/intel_pch_display.c

481

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

49

state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

492

intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),

drivers/gpu/drm/i915/display/intel_pch_display.c

498

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

506

if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_pch_display.c

51

INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pch_display.c

511

tmp = intel_de_read(display, FDI_RX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_pch_display.c

518

if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

525

tmp = intel_de_read(display, PCH_DPLL_SEL);

drivers/gpu/drm/i915/display/intel_pch_display.c

532

crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);

drivers/gpu/drm/i915/display/intel_pch_display.c

535

pll_active = intel_dpll_get_hw_state(display, pll,

drivers/gpu/drm/i915/display/intel_pch_display.c

537

drm_WARN_ON(display->drm, !pll_active);

drivers/gpu/drm/i915/display/intel_pch_display.c

549

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

55

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_pch_display.c

554

assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder);

drivers/gpu/drm/i915/display/intel_pch_display.c

555

assert_fdi_rx_enabled(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

557

val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));

drivers/gpu/drm/i915/display/intel_pch_display.c

56

HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,

drivers/gpu/drm/i915/display/intel_pch_display.c

563

intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);

drivers/gpu/drm/i915/display/intel_pch_display.c

566

pipeconf_val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_pch_display.c

567

TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_pch_display.c

574

intel_de_write(display, LPT_TRANSCONF, val);

drivers/gpu/drm/i915/display/intel_pch_display.c

575

if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,

drivers/gpu/drm/i915/display/intel_pch_display.c

577

drm_err(display->drm, "Failed to enable PCH transcoder\n");

drivers/gpu/drm/i915/display/intel_pch_display.c

580

static void lpt_disable_pch_transcoder(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_display.c

582

intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_pch_display.c

584

if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,

drivers/gpu/drm/i915/display/intel_pch_display.c

586

drm_err(display->drm, "Failed to disable PCH transcoder\n");

drivers/gpu/drm/i915/display/intel_pch_display.c

589

intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);

drivers/gpu/drm/i915/display/intel_pch_display.c

595

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

599

assert_pch_transcoder_disabled(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

61

static void assert_pch_hdmi_disabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

612

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

614

lpt_disable_pch_transcoder(display);

drivers/gpu/drm/i915/display/intel_pch_display.c

616

lpt_disable_iclkip(display);

drivers/gpu/drm/i915/display/intel_pch_display.c

621

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

625

if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_pch_display.c

630

tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_pch_display.c

637

crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);

drivers/gpu/drm/i915/display/intel_pch_display.c

640

void intel_pch_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_display.c

642

if (HAS_PCH_IBX(display))

drivers/gpu/drm/i915/display/intel_pch_display.c

643

ibx_sanitize_pch_ports(display);

drivers/gpu/drm/i915/display/intel_pch_display.c

68

state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

70

INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pch_display.c

74

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_pch_display.c

75

HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,

drivers/gpu/drm/i915/display/intel_pch_display.c

80

static void assert_pch_ports_disabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.c

85

assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B);

drivers/gpu/drm/i915/display/intel_pch_display.c

86

assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C);

drivers/gpu/drm/i915/display/intel_pch_display.c

87

assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D);

drivers/gpu/drm/i915/display/intel_pch_display.c

89

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_pch_display.c

90

intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pch_display.c

94

INTEL_DISPLAY_STATE_WARN(display,

drivers/gpu/drm/i915/display/intel_pch_display.c

95

intel_lvds_port_enabled(display, PCH_LVDS, &port_pipe) && port_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pch_display.h

19

bool intel_has_pch_trancoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.h

44

void intel_pch_sanitize(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pch_display.h

46

static inline bool intel_has_pch_trancoder(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_display.h

93

static inline void intel_pch_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

101

intel_sbi_write(display, 0x21C4, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

103

tmp = intel_sbi_read(display, 0x20EC, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

106

intel_sbi_write(display, 0x20EC, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

108

tmp = intel_sbi_read(display, 0x21EC, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

111

intel_sbi_write(display, 0x21EC, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

114

void lpt_disable_iclkip(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

118

intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

120

intel_sbi_lock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

122

temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

124

intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

126

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

18

static void lpt_fdi_reset_mphy(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

186

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

191

lpt_disable_iclkip(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

194

drm_WARN_ON(display->drm, lpt_iclkip_freq(&p) != clock);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

197

drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &

drivers/gpu/drm/i915/display/intel_pch_refclk.c

199

drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &

drivers/gpu/drm/i915/display/intel_pch_refclk.c

202

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

206

intel_sbi_lock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

209

temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

216

intel_sbi_write(display, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

219

temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

22

intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

222

intel_sbi_write(display, SBI_SSCAUXDIV6, temp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

225

temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

227

intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

229

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

234

intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_UNGATE);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

237

int lpt_get_iclkip(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

24

ret = intel_de_wait_for_set_us(display, SOUTH_CHICKEN2,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

242

if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

247

intel_sbi_lock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

249

temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

251

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

255

temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

261

temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

265

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

27

drm_err(display->drm, "FDI mPHY reset assert timeout\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

278

static void lpt_enable_clkout_dp(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

283

if (drm_WARN(display->drm, with_fdi && !with_spread,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

286

if (drm_WARN(display->drm, HAS_PCH_LPT_LP(display) &&

drivers/gpu/drm/i915/display/intel_pch_refclk.c

29

intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

290

intel_sbi_lock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

292

tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

295

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

300

tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

302

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

305

lpt_fdi_program_mphy(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

308

reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

309

tmp = intel_sbi_read(display, reg, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

31

ret = intel_de_wait_for_clear_us(display, SOUTH_CHICKEN2,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

311

intel_sbi_write(display, reg, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

313

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

317

void lpt_disable_clkout_dp(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

321

intel_sbi_lock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

323

reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

324

tmp = intel_sbi_read(display, reg, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

326

intel_sbi_write(display, reg, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

328

tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

332

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

336

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

339

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

34

drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

374

static void lpt_bend_clkout_dp(struct intel_display *display, int steps)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

379

if (drm_WARN_ON(display->drm, steps % 5 != 0))

drivers/gpu/drm/i915/display/intel_pch_refclk.c

38

static void lpt_fdi_program_mphy(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

382

if (drm_WARN_ON(display->drm, idx >= ARRAY_SIZE(sscdivintphase)))

drivers/gpu/drm/i915/display/intel_pch_refclk.c

385

intel_sbi_lock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

391

intel_sbi_write(display, SBI_SSCDITHPHASE, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

393

tmp = intel_sbi_read(display, SBI_SSCDIVINTPHASE, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

396

intel_sbi_write(display, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

398

intel_sbi_unlock(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

403

static bool spll_uses_pch_ssc(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

405

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

406

u32 ctl = intel_de_read(display, SPLL_CTL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

415

if (display->platform.broadwell &&

drivers/gpu/drm/i915/display/intel_pch_refclk.c

42

lpt_fdi_reset_mphy(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

422

static bool wrpll_uses_pch_ssc(struct intel_display *display, enum intel_dpll_id id)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

424

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

425

u32 ctl = intel_de_read(display, WRPLL_CTL(id));

drivers/gpu/drm/i915/display/intel_pch_refclk.c

433

if ((display->platform.broadwell || display->platform.haswell_ult) &&

drivers/gpu/drm/i915/display/intel_pch_refclk.c

44

tmp = intel_sbi_read(display, 0x8008, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

441

static void lpt_init_pch_refclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

446

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

47

intel_sbi_write(display, 0x8008, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

471

display->dpll.pch_ssc_use = 0;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

473

if (spll_uses_pch_ssc(display)) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

474

drm_dbg_kms(display->drm, "SPLL using PCH SSC\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

475

display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

478

if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL1)) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

479

drm_dbg_kms(display->drm, "WRPLL1 using PCH SSC\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

480

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

483

if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL2)) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

484

drm_dbg_kms(display->drm, "WRPLL2 using PCH SSC\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

485

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

488

if (display->dpll.pch_ssc_use)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

49

tmp = intel_sbi_read(display, 0x2008, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

492

lpt_bend_clkout_dp(display, 0);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

493

lpt_enable_clkout_dp(display, true, true);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

495

lpt_disable_clkout_dp(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

499

static void ilk_init_pch_refclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

51

intel_sbi_write(display, 0x2008, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

513

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

529

if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

53

tmp = intel_sbi_read(display, 0x2108, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

530

has_ck505 = display->vbt.display_clock_mode;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

538

for_each_dpll(display, pll, i) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

541

temp = intel_de_read(display, PCH_DPLL(pll->info->id));

drivers/gpu/drm/i915/display/intel_pch_refclk.c

55

intel_sbi_write(display, 0x2108, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

553

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

562

val = intel_de_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

57

tmp = intel_sbi_read(display, 0x206C, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

582

if (intel_panel_use_ssc(display) && can_ssc)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

586

if (intel_panel_use_ssc(display) && can_ssc)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

59

intel_sbi_write(display, 0x206C, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

61

tmp = intel_sbi_read(display, 0x216C, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

614

if (intel_panel_use_ssc(display) && can_ssc) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

615

drm_dbg_kms(display->drm, "Using SSC on panel\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

622

intel_de_write(display, PCH_DREF_CONTROL, val);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

623

intel_de_posting_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

63

intel_sbi_write(display, 0x216C, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

630

if (intel_panel_use_ssc(display) && can_ssc) {

drivers/gpu/drm/i915/display/intel_pch_refclk.c

631

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pch_refclk.c

641

intel_de_write(display, PCH_DREF_CONTROL, val);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

642

intel_de_posting_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

645

drm_dbg_kms(display->drm, "Disabling CPU source output\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

65

tmp = intel_sbi_read(display, 0x2080, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

652

intel_de_write(display, PCH_DREF_CONTROL, val);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

653

intel_de_posting_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

657

drm_dbg_kms(display->drm, "Disabling SSC source\n");

drivers/gpu/drm/i915/display/intel_pch_refclk.c

666

intel_de_write(display, PCH_DREF_CONTROL, val);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

667

intel_de_posting_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

672

drm_WARN_ON(display->drm, val != final);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

678

void intel_init_pch_refclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

68

intel_sbi_write(display, 0x2080, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

680

if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_pch_refclk.c

681

ilk_init_pch_refclk(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

682

else if (HAS_PCH_LPT(display))

drivers/gpu/drm/i915/display/intel_pch_refclk.c

683

lpt_init_pch_refclk(display);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

70

tmp = intel_sbi_read(display, 0x2180, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

73

intel_sbi_write(display, 0x2180, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

75

tmp = intel_sbi_read(display, 0x208C, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

78

intel_sbi_write(display, 0x208C, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

80

tmp = intel_sbi_read(display, 0x218C, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

83

intel_sbi_write(display, 0x218C, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

85

tmp = intel_sbi_read(display, 0x2098, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

88

intel_sbi_write(display, 0x2098, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

90

tmp = intel_sbi_read(display, 0x2198, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

93

intel_sbi_write(display, 0x2198, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

95

tmp = intel_sbi_read(display, 0x20C4, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

97

intel_sbi_write(display, 0x20C4, tmp, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

99

tmp = intel_sbi_read(display, 0x21C4, SBI_MPHY);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

16

void lpt_disable_iclkip(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

17

int lpt_get_iclkip(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

20

void intel_init_pch_refclk(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

21

void lpt_disable_clkout_dp(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

26

static inline void lpt_disable_iclkip(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.h

29

static inline int lpt_get_iclkip(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.h

37

static inline void intel_init_pch_refclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pch_refclk.h

40

static inline void lpt_disable_clkout_dp(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pfit.c

110

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

122

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

132

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

145

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

151

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

163

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

175

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

188

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

21

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

260

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_pfit.c

33

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

421

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

427

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_pfit.c

433

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

441

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

454

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

471

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

478

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

497

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_pfit.c

50

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

511

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_pfit.c

527

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_pfit.c

537

if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18)

drivers/gpu/drm/i915/display/intel_pfit.c

551

intel_pfit_mode_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pfit.c

556

return skl_scaler_mode_valid(display, mode, output_format,

drivers/gpu/drm/i915/display/intel_pfit.c

563

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

565

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_pfit.c

573

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

589

if (display->platform.ivybridge || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_pfit.c

590

intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |

drivers/gpu/drm/i915/display/intel_pfit.c

593

intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |

drivers/gpu/drm/i915/display/intel_pfit.c

595

intel_de_write_fw(display, PF_WIN_POS(pipe),

drivers/gpu/drm/i915/display/intel_pfit.c

597

intel_de_write_fw(display, PF_WIN_SZ(pipe),

drivers/gpu/drm/i915/display/intel_pfit.c

603

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

61

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

614

intel_de_write_fw(display, PF_CTL(pipe), 0);

drivers/gpu/drm/i915/display/intel_pfit.c

615

intel_de_write_fw(display, PF_WIN_POS(pipe), 0);

drivers/gpu/drm/i915/display/intel_pfit.c

616

intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);

drivers/gpu/drm/i915/display/intel_pfit.c

621

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

626

ctl = intel_de_read(display, PF_CTL(crtc->pipe));

drivers/gpu/drm/i915/display/intel_pfit.c

630

if (display->platform.ivybridge || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_pfit.c

637

pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));

drivers/gpu/drm/i915/display/intel_pfit.c

638

size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));

drivers/gpu/drm/i915/display/intel_pfit.c

651

drm_WARN_ON(display->drm, pipe != crtc->pipe);

drivers/gpu/drm/i915/display/intel_pfit.c

656

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

666

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.c

667

intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);

drivers/gpu/drm/i915/display/intel_pfit.c

668

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_pfit.c

670

intel_de_write(display, PFIT_PGM_RATIOS(display),

drivers/gpu/drm/i915/display/intel_pfit.c

672

intel_de_write(display, PFIT_CONTROL(display),

drivers/gpu/drm/i915/display/intel_pfit.c

679

intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_pfit.c

684

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

689

assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_pfit.c

691

drm_dbg_kms(display->drm, "disabling pfit, current: 0x%08x\n",

drivers/gpu/drm/i915/display/intel_pfit.c

692

intel_de_read(display, PFIT_CONTROL(display)));

drivers/gpu/drm/i915/display/intel_pfit.c

693

intel_de_write(display, PFIT_CONTROL(display), 0);

drivers/gpu/drm/i915/display/intel_pfit.c

696

static bool i9xx_has_pfit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pfit.c

698

if (display->platform.i830)

drivers/gpu/drm/i915/display/intel_pfit.c

701

return DISPLAY_VER(display) >= 4 ||

drivers/gpu/drm/i915/display/intel_pfit.c

702

display->platform.pineview || display->platform.mobile;

drivers/gpu/drm/i915/display/intel_pfit.c

707

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

712

if (!i9xx_has_pfit(display))

drivers/gpu/drm/i915/display/intel_pfit.c

715

tmp = intel_de_read(display, PFIT_CONTROL(display));

drivers/gpu/drm/i915/display/intel_pfit.c

72

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

720

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_pfit.c

730

intel_de_read(display, PFIT_PGM_RATIOS(display));

drivers/gpu/drm/i915/display/intel_pfit.c

78

if (DISPLAY_VER(display) >= 8) {

drivers/gpu/drm/i915/display/intel_pfit.c

81

} else if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/intel_pfit.c

98

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pfit.h

25

intel_pfit_mode_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

117

drm_WARN(display->drm, 1, "nonexisting DP port %c\n",

drivers/gpu/drm/i915/display/intel_pipe_crc.c

126

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

129

static int vlv_pipe_crc_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

137

i9xx_pipe_crc_auto_source(display, pipe, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

152

if (!display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

174

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

190

intel_de_write(display, PORT_DFT2_G4X(display), tmp);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

196

static int i9xx_pipe_crc_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

202

i9xx_pipe_crc_auto_source(display, pipe, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

209

if (!SUPPORTS_TV(display))

drivers/gpu/drm/i915/display/intel_pipe_crc.c

233

static void vlv_undo_pipe_scramble_reset(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

236

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

253

intel_de_write(display, PORT_DFT2_G4X(display), tmp);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

285

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

291

if (display->platform.i945gm || display->platform.i915gm)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

292

i915gm_irq_cstate_wa(display, enable);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

296

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

315

if (display->platform.haswell &&

drivers/gpu/drm/i915/display/intel_pipe_crc.c

331

drm_WARN(display->drm, ret,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

337

static int ivb_pipe_crc_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

365

static int skl_pipe_crc_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

408

static int get_new_crc_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

412

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

414

else if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

415

return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

416

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

417

return vlv_pipe_crc_ctl_reg(display, pipe, source, val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

418

else if (display->platform.ironlake || display->platform.sandybridge)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

420

else if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

421

return ivb_pipe_crc_ctl_reg(display, pipe, source, val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

423

return skl_pipe_crc_ctl_reg(display, pipe, source, val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

451

static int i8xx_crc_source_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

463

static int i9xx_crc_source_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

476

static int vlv_crc_source_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

491

static int ilk_crc_source_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

505

static int ivb_crc_source_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

519

static int skl_crc_source_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

539

intel_is_valid_crc_source(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

542

if (DISPLAY_VER(display) == 2)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

543

return i8xx_crc_source_valid(display, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

544

else if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

545

return i9xx_crc_source_valid(display, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

546

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

547

return vlv_crc_source_valid(display, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

548

else if (display->platform.ironlake || display->platform.sandybridge)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

549

return ilk_crc_source_valid(display, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

550

else if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

551

return ivb_crc_source_valid(display, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

553

return skl_crc_source_valid(display, source);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

566

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

570

drm_dbg_kms(display->drm, "unknown source %s\n", source_name);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

575

intel_is_valid_crc_source(display, source) == 0) {

drivers/gpu/drm/i915/display/intel_pipe_crc.c

586

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

597

drm_dbg_kms(display->drm, "unknown source %s\n", source_name);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

602

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

604

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

613

ret = get_new_crc_ctl_reg(display, pipe, &source, &val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

618

intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

619

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

622

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

623

vlv_undo_pipe_scramble_reset(display, pipe);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

632

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

639

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

647

if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0)

drivers/gpu/drm/i915/display/intel_pipe_crc.c

653

intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

654

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

659

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

668

intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

669

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

670

intel_parent_irq_synchronize(display);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

79

static void i9xx_pipe_crc_auto_source(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pipe_crc.c

89

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

90

for_each_intel_encoder(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_plane.c

1005

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_plane.c

1007

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_plane.c

1018

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1038

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

1055

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

1070

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1104

} else if (DISPLAY_VER(display) >= 20 &&

drivers/gpu/drm/i915/display/intel_plane.c

1114

if ((DISPLAY_VERx100(display) == 2000 ||

drivers/gpu/drm/i915/display/intel_plane.c

1115

DISPLAY_VERx100(display) == 3000 ||

drivers/gpu/drm/i915/display/intel_plane.c

1116

DISPLAY_VERx100(display) == 3002) &&

drivers/gpu/drm/i915/display/intel_plane.c

1120

if (DISPLAY_VER(display) == 35)

drivers/gpu/drm/i915/display/intel_plane.c

1131

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

1139

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

1201

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_plane.c

1248

intel_parent_fence_priority_display(display, new_plane_state->uapi.fence);

drivers/gpu/drm/i915/display/intel_plane.c

1261

intel_display_rps_mark_interactive(display, state, true);

drivers/gpu/drm/i915/display/intel_plane.c

1282

struct intel_display *display = to_intel_display(plane->dev);

drivers/gpu/drm/i915/display/intel_plane.c

1292

intel_display_rps_mark_interactive(display, state, false);

drivers/gpu/drm/i915/display/intel_plane.c

1345

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_plane.c

1351

intel_parent_panic_finish(display, fb->panic);

drivers/gpu/drm/i915/display/intel_plane.c

1359

if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {

drivers/gpu/drm/i915/display/intel_plane.c

1362

intel_fbdev_get_map(display->fbdev.fbdev, &map);

drivers/gpu/drm/i915/display/intel_plane.c

1407

struct intel_display *display = to_intel_display(plane->dev);

drivers/gpu/drm/i915/display/intel_plane.c

1419

if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {

drivers/gpu/drm/i915/display/intel_plane.c

1420

intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]);

drivers/gpu/drm/i915/display/intel_plane.c

1432

ret = intel_parent_panic_setup(display, fb->panic, sb);

drivers/gpu/drm/i915/display/intel_plane.c

1482

struct intel_display *display = to_intel_display(uv_plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1486

drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_plane.c

1518

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1529

drm_WARN_ON(display->drm, plane_state->uapi.visible);

drivers/gpu/drm/i915/display/intel_plane.c

1543

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_plane.c

1550

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/intel_plane.c

1577

for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {

drivers/gpu/drm/i915/display/intel_plane.c

1578

if (!icl_is_nv12_y_plane(display, y_plane->id))

drivers/gpu/drm/i915/display/intel_plane.c

1592

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

1609

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_plane.c

1612

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_plane.c

1639

static bool active_planes_affects_min_cdclk(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_plane.c

1642

return display->platform.broadwell || display->platform.haswell ||

drivers/gpu/drm/i915/display/intel_plane.c

1643

display->platform.cherryview || display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_plane.c

1644

display->platform.ivybridge;

drivers/gpu/drm/i915/display/intel_plane.c

1723

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_plane.c

1737

drm_dbg_atomic(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

175

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_plane.c

1757

if (!active_planes_affects_min_cdclk(display))

drivers/gpu/drm/i915/display/intel_plane.c

178

DISPLAY_INFO(display)->cursor_needs_physical;

drivers/gpu/drm/i915/display/intel_plane.c

329

struct intel_display *display = to_intel_display(new_plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

333

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_plane.c

477

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_plane.c

498

return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;

drivers/gpu/drm/i915/display/intel_plane.c

602

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_plane.c

611

if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {

drivers/gpu/drm/i915/display/intel_plane.c

620

if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))

drivers/gpu/drm/i915/display/intel_plane.c

644

drm_dbg_atomic(display->drm,

drivers/gpu/drm/i915/display/intel_plane.c

654

if (HAS_GMCH(display) &&

drivers/gpu/drm/i915/display/intel_plane.c

658

if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&

drivers/gpu/drm/i915/display/intel_plane.c

753

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_plane.c

756

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/intel_plane.c

767

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_plane.c

774

struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);

drivers/gpu/drm/i915/display/intel_pmdemand.c

109

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

112

&display->pmdemand.obj);

drivers/gpu/drm/i915/display/intel_pmdemand.c

120

int intel_pmdemand_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pmdemand.c

128

intel_atomic_global_obj_init(display, &display->pmdemand.obj,

drivers/gpu/drm/i915/display/intel_pmdemand.c

132

if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0))

drivers/gpu/drm/i915/display/intel_pmdemand.c

134

intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);

drivers/gpu/drm/i915/display/intel_pmdemand.c

139

void intel_pmdemand_init_early(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pmdemand.c

141

mutex_init(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

142

init_waitqueue_head(&display->pmdemand.waitqueue);

drivers/gpu/drm/i915/display/intel_pmdemand.c

146

intel_pmdemand_update_phys_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

153

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_pmdemand.c

171

intel_pmdemand_update_port_clock(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

175

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_pmdemand.c

182

intel_pmdemand_update_max_ddiclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

192

intel_pmdemand_update_port_clock(display, pmdemand_state,

drivers/gpu/drm/i915/display/intel_pmdemand.c

203

intel_pmdemand_update_connector_phys(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

224

intel_pmdemand_update_phys_mask(display, encoder, pmdemand_state,

drivers/gpu/drm/i915/display/intel_pmdemand.c

229

intel_pmdemand_update_active_non_tc_phys(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

244

intel_pmdemand_update_connector_phys(display, state,

drivers/gpu/drm/i915/display/intel_pmdemand.c

249

intel_pmdemand_update_connector_phys(display, state,

drivers/gpu/drm/i915/display/intel_pmdemand.c

260

intel_pmdemand_encoder_has_tc_phy(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

269

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

286

(intel_pmdemand_encoder_has_tc_phy(display, old_encoder) &&

drivers/gpu/drm/i915/display/intel_pmdemand.c

287

intel_pmdemand_encoder_has_tc_phy(display, new_encoder)))

drivers/gpu/drm/i915/display/intel_pmdemand.c

321

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

327

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_pmdemand.c

349

if (DISPLAY_VER(display) < 30) {

drivers/gpu/drm/i915/display/intel_pmdemand.c

356

min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));

drivers/gpu/drm/i915/display/intel_pmdemand.c

368

intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

370

intel_pmdemand_update_active_non_tc_phys(display, state, new_pmdemand_state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

391

static bool intel_pmdemand_check_prev_transaction(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pmdemand.c

393

return !(intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

396

intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

402

intel_pmdemand_init_pmdemand_params(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

407

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_pmdemand.c

410

mutex_lock(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

411

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pmdemand.c

412

!intel_pmdemand_check_prev_transaction(display))) {

drivers/gpu/drm/i915/display/intel_pmdemand.c

418

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

drivers/gpu/drm/i915/display/intel_pmdemand.c

420

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

drivers/gpu/drm/i915/display/intel_pmdemand.c

436

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_pmdemand.c

450

mutex_unlock(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

453

static bool intel_pmdemand_req_complete(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pmdemand.c

455

return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &

drivers/gpu/drm/i915/display/intel_pmdemand.c

459

static void intel_pmdemand_poll(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pmdemand.c

465

ret = intel_de_wait_ms(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),

drivers/gpu/drm/i915/display/intel_pmdemand.c

470

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_pmdemand.c

475

static void intel_pmdemand_wait(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pmdemand.c

478

if (DISPLAY_VER(display) == 20) {

drivers/gpu/drm/i915/display/intel_pmdemand.c

479

intel_pmdemand_poll(display);

drivers/gpu/drm/i915/display/intel_pmdemand.c

481

if (!wait_event_timeout(display->pmdemand.waitqueue,

drivers/gpu/drm/i915/display/intel_pmdemand.c

482

intel_pmdemand_req_complete(display),

drivers/gpu/drm/i915/display/intel_pmdemand.c

484

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_pmdemand.c

490

void intel_pmdemand_program_dbuf(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

496

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_pmdemand.c

499

mutex_lock(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

500

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pmdemand.c

501

!intel_pmdemand_check_prev_transaction(display)))

drivers/gpu/drm/i915/display/intel_pmdemand.c

504

intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),

drivers/gpu/drm/i915/display/intel_pmdemand.c

507

intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,

drivers/gpu/drm/i915/display/intel_pmdemand.c

510

intel_pmdemand_wait(display);

drivers/gpu/drm/i915/display/intel_pmdemand.c

513

mutex_unlock(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

517

intel_pmdemand_update_params(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

560

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/intel_pmdemand.c

573

intel_pmdemand_program_params(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.c

582

mutex_lock(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

583

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pmdemand.c

584

!intel_pmdemand_check_prev_transaction(display)))

drivers/gpu/drm/i915/display/intel_pmdemand.c

587

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

drivers/gpu/drm/i915/display/intel_pmdemand.c

590

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

drivers/gpu/drm/i915/display/intel_pmdemand.c

593

intel_pmdemand_update_params(display, new, old, &mod_reg1, &mod_reg2,

drivers/gpu/drm/i915/display/intel_pmdemand.c

597

intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),

drivers/gpu/drm/i915/display/intel_pmdemand.c

603

intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),

drivers/gpu/drm/i915/display/intel_pmdemand.c

612

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pmdemand.c

616

intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,

drivers/gpu/drm/i915/display/intel_pmdemand.c

619

intel_pmdemand_wait(display);

drivers/gpu/drm/i915/display/intel_pmdemand.c

622

mutex_unlock(&display->pmdemand.lock);

drivers/gpu/drm/i915/display/intel_pmdemand.c

634

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

640

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_pmdemand.c

650

intel_pmdemand_program_params(display, new_pmdemand_state,

drivers/gpu/drm/i915/display/intel_pmdemand.c

657

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

663

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_pmdemand.c

673

intel_pmdemand_program_params(display, new_pmdemand_state, NULL,

drivers/gpu/drm/i915/display/intel_pmdemand.c

81

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

84

&display->pmdemand.obj);

drivers/gpu/drm/i915/display/intel_pmdemand.c

95

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_pmdemand.c

98

&display->pmdemand.obj);

drivers/gpu/drm/i915/display/intel_pmdemand.h

22

void intel_pmdemand_init_early(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pmdemand.h

23

int intel_pmdemand_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pmdemand.h

24

void intel_pmdemand_init_pmdemand_params(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.h

26

void intel_pmdemand_update_port_clock(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.h

29

void intel_pmdemand_update_phys_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pmdemand.h

33

void intel_pmdemand_program_dbuf(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pps.c

1001

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

1002

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1007

if (IS_DISPLAY_VER(display, 13, 14))

drivers/gpu/drm/i915/display/intel_pps.c

1008

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_pps.c

1011

if (display->platform.ironlake) {

drivers/gpu/drm/i915/display/intel_pps.c

1013

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

1014

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1029

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1034

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1039

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",

drivers/gpu/drm/i915/display/intel_pps.c

1043

drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

105

if (drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1058

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

1059

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

106

intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,

drivers/gpu/drm/i915/display/intel_pps.c

1067

intel_display_power_put(display,

drivers/gpu/drm/i915/display/intel_pps.c

1084

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1101

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

1102

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1109

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

112

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1121

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

1122

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1135

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_pps.c

1145

drm_dbg_kms(display->drm, "panel power control backlight %s\n",

drivers/gpu/drm/i915/display/intel_pps.c

1156

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1159

i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1161

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1163

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_pps.c

1177

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1181

intel_de_write(display, pp_on_reg, 0);

drivers/gpu/drm/i915/display/intel_pps.c

1182

intel_de_posting_read(display, pp_on_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1187

static void vlv_steal_power_sequencer(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pps.c

1192

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1194

for_each_intel_dp(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_pps.c

1197

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pps.c

120

DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/intel_pps.c

1205

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1217

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1221

if (g4x_dp_port_enabled(display, intel_dp->output_reg,

drivers/gpu/drm/i915/display/intel_pps.c

125

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pps.c

1266

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1270

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1272

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1288

vlv_steal_power_sequencer(display, crtc->pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1298

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

130

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_pps.c

1320

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1323

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1334

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1338

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

1339

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

137

release_cl_override = display->platform.cherryview &&

drivers/gpu/drm/i915/display/intel_pps.c

1371

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

138

!chv_phy_powergate_ch(display, phy, ch, true);

drivers/gpu/drm/i915/display/intel_pps.c

1380

if (!HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_pps.c

1381

intel_de_write(display, regs.pp_ctrl, pp_ctl);

drivers/gpu/drm/i915/display/intel_pps.c

1383

pp_on = intel_de_read(display, regs.pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

1384

pp_off = intel_de_read(display, regs.pp_off);

drivers/gpu/drm/i915/display/intel_pps.c

1395

pp_div = intel_de_read(display, regs.pp_div);

drivers/gpu/drm/i915/display/intel_pps.c

140

if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) {

drivers/gpu/drm/i915/display/intel_pps.c

141

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1410

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1412

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1421

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1432

drm_err(display->drm, "PPS state mismatch\n");

drivers/gpu/drm/i915/display/intel_pps.c

1459

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1461

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1474

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1488

if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {

drivers/gpu/drm/i915/display/intel_pps.c

1490

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1501

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1503

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

1517

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1521

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

154

intel_de_write(display, intel_dp->output_reg, DP);

drivers/gpu/drm/i915/display/intel_pps.c

1549

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

155

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1555

drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",

drivers/gpu/drm/i915/display/intel_pps.c

157

intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);

drivers/gpu/drm/i915/display/intel_pps.c

1579

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

158

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1581

int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;

drivers/gpu/drm/i915/display/intel_pps.c

1586

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

160

intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);

drivers/gpu/drm/i915/display/intel_pps.c

1605

drm_WARN(display->drm, pp & PANEL_POWER_ON,

drivers/gpu/drm/i915/display/intel_pps.c

1609

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

161

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1614

intel_de_write(display, regs.pp_ctrl, pp);

drivers/gpu/drm/i915/display/intel_pps.c

1624

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_pps.c

1626

} else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {

drivers/gpu/drm/i915/display/intel_pps.c

164

vlv_force_pll_off(display, pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1645

intel_de_write(display, regs.pp_on, pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

1646

intel_de_write(display, regs.pp_off, pp_off);

drivers/gpu/drm/i915/display/intel_pps.c

1652

intel_de_write(display, regs.pp_div,

drivers/gpu/drm/i915/display/intel_pps.c

1658

intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,

drivers/gpu/drm/i915/display/intel_pps.c

1662

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1664

intel_de_read(display, regs.pp_on),

drivers/gpu/drm/i915/display/intel_pps.c

1665

intel_de_read(display, regs.pp_off),

drivers/gpu/drm/i915/display/intel_pps.c

1667

intel_de_read(display, regs.pp_div) :

drivers/gpu/drm/i915/display/intel_pps.c

1668

(intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));

drivers/gpu/drm/i915/display/intel_pps.c

167

chv_phy_powergate_ch(display, phy, ch, false);

drivers/gpu/drm/i915/display/intel_pps.c

1673

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1683

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pps.c

171

static enum pipe vlv_find_free_pps(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pps.c

1717

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1721

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pps.c

1724

if (intel_num_pps(display) < 2)

drivers/gpu/drm/i915/display/intel_pps.c

1727

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1755

void intel_pps_unlock_regs_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pps.c

1760

if (!HAS_DISPLAY(display) || HAS_DDI(display))

drivers/gpu/drm/i915/display/intel_pps.c

1766

pps_num = intel_num_pps(display);

drivers/gpu/drm/i915/display/intel_pps.c

1769

intel_de_rmw(display, PP_CONTROL(display, pps_idx),

drivers/gpu/drm/i915/display/intel_pps.c

1773

void intel_pps_setup(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pps.c

1775

if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_pps.c

1776

display->pps.mmio_base = PCH_PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1777

else if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pps.c

1778

display->pps.mmio_base = VLV_PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1780

display->pps.mmio_base = PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

180

for_each_intel_dp(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_pps.c

1816

void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)

drivers/gpu/drm/i915/display/intel_pps.c

1823

if (drm_WARN_ON(display->drm, HAS_DDI(display)))

drivers/gpu/drm/i915/display/intel_pps.c

1826

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_pps.c

1829

pp_reg = PP_CONTROL(display, 0);

drivers/gpu/drm/i915/display/intel_pps.c

1830

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

drivers/gpu/drm/i915/display/intel_pps.c

1835

intel_lvds_port_enabled(display, PCH_LVDS, &panel_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1838

g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

184

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1841

g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1844

g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1850

} else if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_pps.c

1852

pp_reg = PP_CONTROL(display, pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1857

pp_reg = PP_CONTROL(display, 0);

drivers/gpu/drm/i915/display/intel_pps.c

1858

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

drivers/gpu/drm/i915/display/intel_pps.c

1861

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

1863

intel_lvds_port_enabled(display, LVDS, &panel_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1866

val = intel_de_read(display, pp_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1871

INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,

drivers/gpu/drm/i915/display/intel_pps.c

192

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

209

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

213

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

216

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

218

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

224

pipe = vlv_find_free_pps(display);

drivers/gpu/drm/i915/display/intel_pps.c

230

if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))

drivers/gpu/drm/i915/display/intel_pps.c

233

vlv_steal_power_sequencer(display, pipe);

drivers/gpu/drm/i915/display/intel_pps.c

236

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

257

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

260

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

263

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

279

typedef bool (*pps_check)(struct intel_display *display, int pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

28

static void vlv_steal_power_sequencer(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pps.c

281

static bool pps_has_pp_on(struct intel_display *display, int pps_idx)

drivers/gpu/drm/i915/display/intel_pps.c

283

return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;

drivers/gpu/drm/i915/display/intel_pps.c

286

static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)

drivers/gpu/drm/i915/display/intel_pps.c

288

return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

291

static bool pps_any(struct intel_display *display, int pps_idx)

drivers/gpu/drm/i915/display/intel_pps.c

297

vlv_initial_pps_pipe(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_pps.c

303

u32 port_sel = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_pps.c

304

PP_ON_DELAYS(display, pipe)) &

drivers/gpu/drm/i915/display/intel_pps.c

310

if (!check(display, pipe))

drivers/gpu/drm/i915/display/intel_pps.c

322

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

326

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

330

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

334

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

338

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

343

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

349

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

355

static int intel_num_pps(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pps.c

357

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pps.c

36

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

360

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_pps.c

363

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

drivers/gpu/drm/i915/display/intel_pps.c

366

if (INTEL_PCH_TYPE(display) >= PCH_DG1)

drivers/gpu/drm/i915/display/intel_pps.c

369

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

drivers/gpu/drm/i915/display/intel_pps.c

377

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

380

INTEL_PCH_TYPE(display) >= PCH_ICP &&

drivers/gpu/drm/i915/display/intel_pps.c

381

INTEL_PCH_TYPE(display) <= PCH_ADP)

drivers/gpu/drm/i915/display/intel_pps.c

382

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

drivers/gpu/drm/i915/display/intel_pps.c

388

bxt_initial_pps_idx(struct intel_display *display, pps_check check)

drivers/gpu/drm/i915/display/intel_pps.c

39

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_pps.c

390

int pps_idx, pps_num = intel_num_pps(display);

drivers/gpu/drm/i915/display/intel_pps.c

393

if (check(display, pps_idx))

drivers/gpu/drm/i915/display/intel_pps.c

403

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

407

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

409

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_pps.c

415

if (intel_num_pps(display) > 1)

drivers/gpu/drm/i915/display/intel_pps.c

420

if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))

drivers/gpu/drm/i915/display/intel_pps.c

425

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

428

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);

drivers/gpu/drm/i915/display/intel_pps.c

431

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);

drivers/gpu/drm/i915/display/intel_pps.c

433

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

438

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

447

void vlv_pps_reset_all(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pps.c

451

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_pps.c

464

for_each_intel_dp(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_pps.c

467

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

474

void bxt_pps_reset_all(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_pps.c

478

if (!HAS_DISPLAY(display))

drivers/gpu/drm/i915/display/intel_pps.c

483

for_each_intel_dp(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_pps.c

502

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

507

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_pps.c

509

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/intel_pps.c

514

regs->pp_ctrl = PP_CONTROL(display, pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

515

regs->pp_stat = PP_STATUS(display, pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

516

regs->pp_on = PP_ON_DELAYS(display, pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

517

regs->pp_off = PP_OFF_DELAYS(display, pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

520

if (display->platform.geminilake || display->platform.broxton ||

drivers/gpu/drm/i915/display/intel_pps.c

521

INTEL_PCH_TYPE(display) >= PCH_CNP)

drivers/gpu/drm/i915/display/intel_pps.c

524

regs->pp_div = PP_DIVISOR(display, pps_idx);

drivers/gpu/drm/i915/display/intel_pps.c

549

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

551

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

553

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_pps.c

557

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

drivers/gpu/drm/i915/display/intel_pps.c

562

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

564

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

566

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_pps.c

570

return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

575

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

582

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_pps.c

586

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

590

intel_de_read(display, _pp_stat_reg(intel_dp)),

drivers/gpu/drm/i915/display/intel_pps.c

591

intel_de_read(display, _pp_ctrl_reg(intel_dp)));

drivers/gpu/drm/i915/display/intel_pps.c

609

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

615

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

622

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

627

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

628

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

630

ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

634

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

638

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

639

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

643

drm_dbg_kms(display->drm, "Wait complete\n");

drivers/gpu/drm/i915/display/intel_pps.c

648

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

651

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

660

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

663

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

672

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

684

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

72

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

724

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

727

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

729

control = intel_de_read(display, _pp_ctrl_reg(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

730

if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&

drivers/gpu/drm/i915/display/intel_pps.c

745

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

754

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

762

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

763

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

769

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",

drivers/gpu/drm/i915/display/intel_pps.c

779

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

78

wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);

drivers/gpu/drm/i915/display/intel_pps.c

780

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

781

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

785

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

786

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

79

mutex_lock(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

791

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

810

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

819

INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",

drivers/gpu/drm/i915/display/intel_pps.c

827

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

832

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

834

drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);

drivers/gpu/drm/i915/display/intel_pps.c

839

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",

drivers/gpu/drm/i915/display/intel_pps.c

849

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

850

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

853

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_pps.c

857

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

858

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

86

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

865

intel_display_power_put(display,

drivers/gpu/drm/i915/display/intel_pps.c

88

mutex_unlock(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

89

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

898

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

914

queue_delayed_work(display->wq.unordered,

drivers/gpu/drm/i915/display/intel_pps.c

925

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

930

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

932

INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

957

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

961

lockdep_assert_held(&display->pps.mutex);

drivers/gpu/drm/i915/display/intel_pps.c

966

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",

drivers/gpu/drm/i915/display/intel_pps.c

97

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

971

if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

982

if (display->platform.ironlake) {

drivers/gpu/drm/i915/display/intel_pps.c

985

intel_de_write(display, pp_ctrl_reg, pp);

drivers/gpu/drm/i915/display/intel_pps.c

986

intel_de_posting_read(display, pp_ctrl_reg);

drivers/gpu/drm/i915/display/intel_pps.c

993

if (IS_DISPLAY_VER(display, 13, 14))

drivers/gpu/drm/i915/display/intel_pps.c

994

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/intel_pps.c

998

if (!display->platform.ironlake)

drivers/gpu/drm/i915/display/intel_pps.h

57

void vlv_pps_reset_all(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pps.h

58

void bxt_pps_reset_all(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pps.h

60

void intel_pps_unlock_regs_wa(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pps.h

61

void intel_pps_setup(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_pps.h

65

void assert_pps_unlocked(struct intel_display *display, enum pipe pipe);

drivers/gpu/drm/i915/display/intel_pps_regs.h

16

#define _MMIO_PPS(display, pps_idx, reg) \

drivers/gpu/drm/i915/display/intel_pps_regs.h

17

_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)

drivers/gpu/drm/i915/display/intel_pps_regs.h

20

#define PP_STATUS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_STATUS)

drivers/gpu/drm/i915/display/intel_pps_regs.h

47

#define PP_CONTROL(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_CONTROL)

drivers/gpu/drm/i915/display/intel_pps_regs.h

57

#define PP_ON_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_ON_DELAYS)

drivers/gpu/drm/i915/display/intel_pps_regs.h

68

#define PP_OFF_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_OFF_DELAYS)

drivers/gpu/drm/i915/display/intel_pps_regs.h

73

#define PP_DIVISOR(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_DIVISOR)

drivers/gpu/drm/i915/display/intel_psr.c

1028

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1039

intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

1043

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

1044

PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

1047

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,

drivers/gpu/drm/i915/display/intel_psr.c

1053

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1060

if ((DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_psr.c

1061

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

drivers/gpu/drm/i915/display/intel_psr.c

1068

if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_psr.c

1071

if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13)

drivers/gpu/drm/i915/display/intel_psr.c

1078

if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) {

drivers/gpu/drm/i915/display/intel_psr.c

1086

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) {

drivers/gpu/drm/i915/display/intel_psr.c

1109

} else if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_psr.c

1111

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_psr.c

1114

} else if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_psr.c

1122

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_psr.c

1128

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

1129

PSR2_MAN_TRK_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

1130

drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));

drivers/gpu/drm/i915/display/intel_psr.c

1131

} else if (HAS_PSR2_SEL_FETCH(display)) {

drivers/gpu/drm/i915/display/intel_psr.c

1132

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_psr.c

1133

PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_psr.c

1143

intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val);

drivers/gpu/drm/i915/display/intel_psr.c

1145

intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_psr.c

1149

transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder)

drivers/gpu/drm/i915/display/intel_psr.c

1151

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_psr.c

1153

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_psr.c

1155

else if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_psr.c

1173

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1176

intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

1183

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1186

intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);

drivers/gpu/drm/i915/display/intel_psr.c

1191

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1193

intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);

drivers/gpu/drm/i915/display/intel_psr.c

1226

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1231

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_psr.c

1241

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1243

struct i915_power_domains *power_domains = &display->power.domains;

drivers/gpu/drm/i915/display/intel_psr.c

1267

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

1277

if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))

drivers/gpu/drm/i915/display/intel_psr.c

1286

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1288

if (!display->params.enable_psr2_sel_fetch &&

drivers/gpu/drm/i915/display/intel_psr.c

1290

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1302

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1335

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_psr.c

1356

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1370

if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)

drivers/gpu/drm/i915/display/intel_psr.c

1381

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1387

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1395

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_psr.c

1398

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1402

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1417

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

1423

if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))

drivers/gpu/drm/i915/display/intel_psr.c

1427

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_psr.c

1445

if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||

drivers/gpu/drm/i915/display/intel_psr.c

1448

else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||

drivers/gpu/drm/i915/display/intel_psr.c

1476

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1488

wake_lines = DISPLAY_VER(display) < 20 ?

drivers/gpu/drm/i915/display/intel_psr.c

1511

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1514

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1521

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1533

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1539

if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)

drivers/gpu/drm/i915/display/intel_psr.c

1543

if (display->platform.jasperlake || display->platform.elkhartlake) {

drivers/gpu/drm/i915/display/intel_psr.c

1544

drm_dbg_kms(display->drm, "PSR2 not supported by phy\n");

drivers/gpu/drm/i915/display/intel_psr.c

1549

if (display->platform.rocketlake || display->platform.alderlake_s ||

drivers/gpu/drm/i915/display/intel_psr.c

1550

display->platform.dg2) {

drivers/gpu/drm/i915/display/intel_psr.c

1551

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1556

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {

drivers/gpu/drm/i915/display/intel_psr.c

1557

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1562

if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {

drivers/gpu/drm/i915/display/intel_psr.c

1563

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1575

(DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) {

drivers/gpu/drm/i915/display/intel_psr.c

1576

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1581

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_psr.c

1585

} else if (IS_DISPLAY_VER(display, 12, 14)) {

drivers/gpu/drm/i915/display/intel_psr.c

1589

} else if (IS_DISPLAY_VER(display, 10, 11)) {

drivers/gpu/drm/i915/display/intel_psr.c

1593

} else if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/intel_psr.c

1600

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1608

display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {

drivers/gpu/drm/i915/display/intel_psr.c

1609

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1619

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1636

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1638

if (HAS_PSR2_SEL_FETCH(display) &&

drivers/gpu/drm/i915/display/intel_psr.c

1640

!HAS_PSR_HW_TRACKING(display)) {

drivers/gpu/drm/i915/display/intel_psr.c

1641

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1647

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1657

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1663

if (DISPLAY_VER(display) < 14)

drivers/gpu/drm/i915/display/intel_psr.c

1672

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1679

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1685

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1704

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1708

if (!CAN_PSR(intel_dp) || !display->params.enable_psr)

drivers/gpu/drm/i915/display/intel_psr.c

1723

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1749

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1759

drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");

drivers/gpu/drm/i915/display/intel_psr.c

1764

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1772

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1791

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1802

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1816

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1818

return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&

drivers/gpu/drm/i915/display/intel_psr.c

1826

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1832

if (DISPLAY_VER(display) != 20 &&

drivers/gpu/drm/i915/display/intel_psr.c

1833

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

1841

for_each_intel_crtc(display->drm, crtc)

drivers/gpu/drm/i915/display/intel_psr.c

1854

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1859

drm_dbg_kms(display->drm, "PSR disabled by flag\n");

drivers/gpu/drm/i915/display/intel_psr.c

1864

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1870

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1881

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1902

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

1935

if (HAS_PSR2_SEL_FETCH(display)) {

drivers/gpu/drm/i915/display/intel_psr.c

1936

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

1937

PSR2_MAN_TRK_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

1944

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/intel_psr.c

1945

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

1946

TRANS_EXITLINE(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

1955

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1958

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1959

transcoder_has_psr2(display, cpu_transcoder) &&

drivers/gpu/drm/i915/display/intel_psr.c

1960

intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

1962

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

1963

intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

1965

drm_WARN_ON(display->drm, intel_dp->psr.active);

drivers/gpu/drm/i915/display/intel_psr.c

1967

drm_WARN_ON(display->drm, !intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

1990

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1995

if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)

drivers/gpu/drm/i915/display/intel_psr.c

1999

if (DISPLAY_VER(display) == 12 &&

drivers/gpu/drm/i915/display/intel_psr.c

2005

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

drivers/gpu/drm/i915/display/intel_psr.c

2008

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

drivers/gpu/drm/i915/display/intel_psr.c

2015

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2023

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/intel_psr.c

2040

if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2054

if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult)

drivers/gpu/drm/i915/display/intel_psr.c

2057

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_psr.c

2064

if (IS_DISPLAY_VER(display, 9, 10))

drivers/gpu/drm/i915/display/intel_psr.c

2068

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_psr.c

2072

intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask);

drivers/gpu/drm/i915/display/intel_psr.c

2081

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

2082

TRANS_EXITLINE(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2086

if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))

drivers/gpu/drm/i915/display/intel_psr.c

2087

intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,

drivers/gpu/drm/i915/display/intel_psr.c

2098

if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/intel_psr.c

2099

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0,

drivers/gpu/drm/i915/display/intel_psr.c

2109

(IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||

drivers/gpu/drm/i915/display/intel_psr.c

2110

display->platform.alderlake_p))

drivers/gpu/drm/i915/display/intel_psr.c

2111

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2116

IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

2117

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

2118

MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2121

else if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_psr.c

2122

intel_de_rmw(display, CLKGATE_DIS_MISC, 0,

drivers/gpu/drm/i915/display/intel_psr.c

2127

if ((DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_psr.c

2128

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

drivers/gpu/drm/i915/display/intel_psr.c

2130

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

drivers/gpu/drm/i915/display/intel_psr.c

2137

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2152

val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

2156

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

2168

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2172

drm_WARN_ON(display->drm, intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

2198

drm_dbg_kms(display->drm, "Enabling Panel Replay\n");

drivers/gpu/drm/i915/display/intel_psr.c

2200

drm_dbg_kms(display->drm, "Enabling PSR%s\n",

drivers/gpu/drm/i915/display/intel_psr.c

2239

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2244

if (transcoder_has_psr2(display, cpu_transcoder)) {

drivers/gpu/drm/i915/display/intel_psr.c

2245

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

2246

EDP_PSR2_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

2247

drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

2250

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

2251

psr_ctl_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

2252

drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

2258

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2263

val = intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

2264

EDP_PSR2_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2267

drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));

drivers/gpu/drm/i915/display/intel_psr.c

2269

if ((DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_psr.c

2270

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

drivers/gpu/drm/i915/display/intel_psr.c

2272

intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

drivers/gpu/drm/i915/display/intel_psr.c

2276

val = intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

2277

psr_ctl_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2280

drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE));

drivers/gpu/drm/i915/display/intel_psr.c

2287

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2294

psr_status = EDP_PSR2_STATUS(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

2297

psr_status = psr_status_reg(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

2302

if (intel_de_wait_for_clear_ms(display, psr_status,

drivers/gpu/drm/i915/display/intel_psr.c

2304

drm_err(display->drm, "Timed out waiting PSR idle state\n");

drivers/gpu/drm/i915/display/intel_psr.c

2309

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2318

drm_dbg_kms(display->drm, "Disabling Panel Replay\n");

drivers/gpu/drm/i915/display/intel_psr.c

2320

drm_dbg_kms(display->drm, "Disabling PSR%s\n",

drivers/gpu/drm/i915/display/intel_psr.c

2330

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_psr.c

2331

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

drivers/gpu/drm/i915/display/intel_psr.c

2337

IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

2338

intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

2339

MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2341

else if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/intel_psr.c

2342

intel_de_rmw(display, CLKGATE_DIS_MISC,

drivers/gpu/drm/i915/display/intel_psr.c

2362

if ((DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_psr.c

2363

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

drivers/gpu/drm/i915/display/intel_psr.c

2365

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);

drivers/gpu/drm/i915/display/intel_psr.c

2387

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2392

if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) &&

drivers/gpu/drm/i915/display/intel_psr.c

2446

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2458

drm_warn(display->drm, "Unbalanced PSR pause/resume!\n");

drivers/gpu/drm/i915/display/intel_psr.c

2483

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2500

if ((DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_psr.c

2501

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

drivers/gpu/drm/i915/display/intel_psr.c

2523

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_psr.c

2526

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_psr.c

2527

CURSURFLIVE(display, crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2544

static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

2546

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 :

drivers/gpu/drm/i915/display/intel_psr.c

2550

static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

2552

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?

drivers/gpu/drm/i915/display/intel_psr.c

2557

static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

2559

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?

drivers/gpu/drm/i915/display/intel_psr.c

2564

static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

2566

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?

drivers/gpu/drm/i915/display/intel_psr.c

2573

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2588

intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2594

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2602

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_psr.c

2609

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2614

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_psr.c

2615

PSR2_MAN_TRK_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2621

intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),

drivers/gpu/drm/i915/display/intel_psr.c

2634

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2635

u32 val = man_trk_ctl_enable_bit_get(display);

drivers/gpu/drm/i915/display/intel_psr.c

2638

val |= man_trk_ctl_partial_frame_bit_get(display);

drivers/gpu/drm/i915/display/intel_psr.c

2641

val |= man_trk_ctl_continuos_full_frame(display);

drivers/gpu/drm/i915/display/intel_psr.c

2648

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_psr.c

266

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

269

display->params.enable_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

2701

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2708

(display->platform.alderlake_p || DISPLAY_VER(display) >= 14))

drivers/gpu/drm/i915/display/intel_psr.c

274

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

276

return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR :

drivers/gpu/drm/i915/display/intel_psr.c

2805

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

282

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2821

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_psr.c

2837

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

284

return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT :

drivers/gpu/drm/i915/display/intel_psr.c

2841

((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||

drivers/gpu/drm/i915/display/intel_psr.c

2842

display->platform.alderlake_p || display->platform.tigerlake)) &&

drivers/gpu/drm/i915/display/intel_psr.c

2847

if (DISPLAY_VER(display) == 30)

drivers/gpu/drm/i915/display/intel_psr.c

2854

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_psr.c

290

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

292

return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY :

drivers/gpu/drm/i915/display/intel_psr.c

2950

drm_info_once(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

298

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

300

return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK :

drivers/gpu/drm/i915/display/intel_psr.c

304

static i915_reg_t psr_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3062

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3065

u32 val = man_trk_ctl_enable_bit_get(display);

drivers/gpu/drm/i915/display/intel_psr.c

3068

val |= man_trk_ctl_partial_frame_bit_get(display);

drivers/gpu/drm/i915/display/intel_psr.c

3069

val |= man_trk_ctl_continuos_full_frame(display);

drivers/gpu/drm/i915/display/intel_psr.c

307

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

3072

intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val);

drivers/gpu/drm/i915/display/intel_psr.c

3077

intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

308

return EDP_PSR_CTL(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3083

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_psr.c

3090

if (!HAS_PSR(display))

drivers/gpu/drm/i915/display/intel_psr.c

3120

(DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled))

drivers/gpu/drm/i915/display/intel_psr.c

313

static i915_reg_t psr_debug_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3134

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3139

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3148

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_psr.c

316

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

3166

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

317

return EDP_PSR_DEBUG(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3178

if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3215

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

322

static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3224

intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

3230

return intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_psr.c

3231

EDP_PSR2_STATUS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

3240

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3244

intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

325

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

3250

return intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_psr.c

3251

psr_status_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

326

return EDP_PSR_PERF_CNT(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3265

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3271

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_psr.c

3289

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3308

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

331

static i915_reg_t psr_status_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3319

reg = EDP_PSR2_STATUS(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3322

reg = psr_status_reg(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3328

err = intel_de_wait_for_clear_ms(display, reg, mask, 50);

drivers/gpu/drm/i915/display/intel_psr.c

3330

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3338

static int intel_psr_fastset_force(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

334

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

3346

state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_psr.c

335

return EDP_PSR_STATUS(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3356

drm_connector_list_iter_begin(display->drm, &conn_iter);

drivers/gpu/drm/i915/display/intel_psr.c

340

static i915_reg_t psr_imr_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3403

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3414

drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val);

drivers/gpu/drm/i915/display/intel_psr.c

343

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_psr.c

3439

ret = intel_psr_fastset_force(display);

drivers/gpu/drm/i915/display/intel_psr.c

344

return TRANS_PSR_IMR(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

349

static i915_reg_t psr_iir_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3496

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3502

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_psr.c

3503

intel_de_write(display, LNL_SFF_CTL(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

3506

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_psr.c

3507

PSR2_MAN_TRK_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

3508

man_trk_ctl_enable_bit_get(display) |

drivers/gpu/drm/i915/display/intel_psr.c

3509

man_trk_ctl_partial_frame_bit_get(display) |

drivers/gpu/drm/i915/display/intel_psr.c

3510

man_trk_ctl_single_full_frame_bit_get(display) |

drivers/gpu/drm/i915/display/intel_psr.c

3511

man_trk_ctl_continuos_full_frame(display));

drivers/gpu/drm/i915/display/intel_psr.c

3516

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3518

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

352

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_psr.c

353

return TRANS_PSR_IIR(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3543

void intel_psr_invalidate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3551

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

358

static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3581

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3596

mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,

drivers/gpu/drm/i915/display/intel_psr.c

3602

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3604

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

361

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

362

return EDP_PSR_AUX_CTL(display, cpu_transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3637

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3653

void intel_psr_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3658

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

367

static i915_reg_t psr_aux_data_reg(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

370

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

3707

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

371

return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);

drivers/gpu/drm/i915/display/intel_psr.c

3711

if (!(HAS_PSR(display) || HAS_DP20(display)))

drivers/gpu/drm/i915/display/intel_psr.c

3723

if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) {

drivers/gpu/drm/i915/display/intel_psr.c

3724

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3729

if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_psr.c

3730

DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_psr.c

3733

if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3737

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/intel_psr.c

378

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3787

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3794

drm_err(display->drm, "Error reading DP_PSR_ESI\n");

drivers/gpu/drm/i915/display/intel_psr.c

3801

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3818

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3836

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3849

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3852

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3855

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3858

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

3862

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

390

intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

3928

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3934

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_psr.c

394

static void psr_event_print(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

3951

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3957

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

drivers/gpu/drm/i915/display/intel_psr.c

3969

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

397

drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val);

drivers/gpu/drm/i915/display/intel_psr.c

3981

intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

drivers/gpu/drm/i915/display/intel_psr.c

3988

struct intel_display *display = container_of(work, typeof(*display),

drivers/gpu/drm/i915/display/intel_psr.c

399

drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n");

drivers/gpu/drm/i915/display/intel_psr.c

3992

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

401

drm_dbg_kms(display->drm, "\tPSR2 disabled\n");

drivers/gpu/drm/i915/display/intel_psr.c

4012

void intel_psr_notify_dc5_dc6(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

4014

if (DISPLAY_VER(display) != 20 &&

drivers/gpu/drm/i915/display/intel_psr.c

4015

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

4018

schedule_work(&display->psr_dc5_dc6_wa_work);

drivers/gpu/drm/i915/display/intel_psr.c

4028

void intel_psr_dc5_dc6_wa_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

403

drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n");

drivers/gpu/drm/i915/display/intel_psr.c

4030

if (DISPLAY_VER(display) != 20 &&

drivers/gpu/drm/i915/display/intel_psr.c

4031

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

4034

INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work);

drivers/gpu/drm/i915/display/intel_psr.c

4049

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_psr.c

405

drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n");

drivers/gpu/drm/i915/display/intel_psr.c

4052

if (DISPLAY_VER(display) != 20 &&

drivers/gpu/drm/i915/display/intel_psr.c

4053

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

drivers/gpu/drm/i915/display/intel_psr.c

4056

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

407

drm_dbg_kms(display->drm, "\tGraphics reset\n");

drivers/gpu/drm/i915/display/intel_psr.c

409

drm_dbg_kms(display->drm, "\tPCH interrupt\n");

drivers/gpu/drm/i915/display/intel_psr.c

4098

void intel_psr_notify_vblank_enable_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.c

4103

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

411

drm_dbg_kms(display->drm, "\tMemory up\n");

drivers/gpu/drm/i915/display/intel_psr.c

4126

intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :

drivers/gpu/drm/i915/display/intel_psr.c

413

drm_dbg_kms(display->drm, "\tFront buffer modification\n");

drivers/gpu/drm/i915/display/intel_psr.c

4133

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4138

if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) &&

drivers/gpu/drm/i915/display/intel_psr.c

415

drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n");

drivers/gpu/drm/i915/display/intel_psr.c

4153

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4154

EDP_PSR2_STATUS(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4169

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

417

drm_dbg_kms(display->drm, "\tPIPE registers updated\n");

drivers/gpu/drm/i915/display/intel_psr.c

4170

psr_status_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

419

drm_dbg_kms(display->drm, "\tRegister updated\n");

drivers/gpu/drm/i915/display/intel_psr.c

421

drm_dbg_kms(display->drm, "\tHDCP enabled\n");

drivers/gpu/drm/i915/display/intel_psr.c

423

drm_dbg_kms(display->drm, "\tKVMR session enabled\n");

drivers/gpu/drm/i915/display/intel_psr.c

4235

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4247

wakeref = intel_display_rpm_get(display);

drivers/gpu/drm/i915/display/intel_psr.c

425

drm_dbg_kms(display->drm, "\tVBI enabled\n");

drivers/gpu/drm/i915/display/intel_psr.c

4260

val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4263

psr2_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4264

EDP_PSR2_CTL(display,

drivers/gpu/drm/i915/display/intel_psr.c

4269

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

427

drm_dbg_kms(display->drm, "\tLPSP mode exited\n");

drivers/gpu/drm/i915/display/intel_psr.c

4270

EDP_PSR2_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4273

val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4288

val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

429

drm_dbg_kms(display->drm, "\tPSR disabled\n");

drivers/gpu/drm/i915/display/intel_psr.c

4306

if (DISPLAY_VER(display) < 13) {

drivers/gpu/drm/i915/display/intel_psr.c

4312

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4313

PSR2_SU_STATUS(display, cpu_transcoder, frame));

drivers/gpu/drm/i915/display/intel_psr.c

4335

intel_display_rpm_put(display, wakeref);

drivers/gpu/drm/i915/display/intel_psr.c

434

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4342

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_psr.c

4346

if (!HAS_PSR(display))

drivers/gpu/drm/i915/display/intel_psr.c

4350

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

4365

struct intel_display *display = data;

drivers/gpu/drm/i915/display/intel_psr.c

4369

if (!HAS_PSR(display))

drivers/gpu/drm/i915/display/intel_psr.c

4372

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

4375

drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val);

drivers/gpu/drm/i915/display/intel_psr.c

4378

with_intel_display_rpm(display)

drivers/gpu/drm/i915/display/intel_psr.c

4388

struct intel_display *display = data;

drivers/gpu/drm/i915/display/intel_psr.c

4391

if (!HAS_PSR(display))

drivers/gpu/drm/i915/display/intel_psr.c

4394

for_each_intel_encoder_with_psr(display->drm, encoder) {

drivers/gpu/drm/i915/display/intel_psr.c

440

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

4409

void intel_psr_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_psr.c

4411

struct dentry *debugfs_root = display->drm->debugfs_root;

drivers/gpu/drm/i915/display/intel_psr.c

4414

display, &i915_edp_psr_debug_fops);

drivers/gpu/drm/i915/display/intel_psr.c

4417

display, &i915_edp_psr_status_fops);

drivers/gpu/drm/i915/display/intel_psr.c

447

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

4498

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_psr.c

4508

if (HAS_PSR(display) || HAS_DP20(display))

drivers/gpu/drm/i915/display/intel_psr.c

451

if (DISPLAY_VER(display) >= 9) {

drivers/gpu/drm/i915/display/intel_psr.c

4532

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4539

wake_lines = DISPLAY_VER(display) < 20 ?

drivers/gpu/drm/i915/display/intel_psr.c

454

val = intel_de_rmw(display,

drivers/gpu/drm/i915/display/intel_psr.c

455

PSR_EVENT(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

4553

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

4576

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

458

psr_event_print(display, val, intel_dp->psr.sel_update_enabled);

drivers/gpu/drm/i915/display/intel_psr.c

4585

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4595

wake_lines = DISPLAY_VER(display) < 20 ?

drivers/gpu/drm/i915/display/intel_psr.c

463

drm_warn(display->drm, "[transcoder %s] PSR aux error\n",

drivers/gpu/drm/i915/display/intel_psr.c

476

intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

479

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

485

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

492

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

500

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

518

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

529

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

605

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

624

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

631

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

649

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

658

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

669

drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",

drivers/gpu/drm/i915/display/intel_psr.c

673

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

679

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_psr.c

689

if (DISPLAY_VER(display) >= 9 &&

drivers/gpu/drm/i915/display/intel_psr.c

707

drm_dbg_kms(display->drm, "PSR2 %ssupported\n",

drivers/gpu/drm/i915/display/intel_psr.c

724

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

739

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_psr.c

740

psr_aux_data_reg(display, cpu_transcoder, i >> 2),

drivers/gpu/drm/i915/display/intel_psr.c

755

intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

762

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

764

if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||

drivers/gpu/drm/i915/display/intel_psr.c

803

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

812

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

857

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

861

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/intel_psr.c

864

if (display->params.psr_safest_params) {

drivers/gpu/drm/i915/display/intel_psr.c

892

if (DISPLAY_VER(display) < 9 &&

drivers/gpu/drm/i915/display/intel_psr.c

898

if (intel_dp_source_supports_tps3(display) &&

drivers/gpu/drm/i915/display/intel_psr.c

909

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

919

if (drm_WARN_ON(display->drm, idle_frames > 0xf))

drivers/gpu/drm/i915/display/intel_psr.c

927

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

928

u32 current_dc_state = intel_display_power_get_current_dc_state(display);

drivers/gpu/drm/i915/display/intel_psr.c

929

struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

940

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

947

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/intel_psr.c

950

if (display->platform.haswell)

drivers/gpu/drm/i915/display/intel_psr.c

958

if (DISPLAY_VER(display) >= 8)

drivers/gpu/drm/i915/display/intel_psr.c

961

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_psr.c

964

intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

968

if ((DISPLAY_VER(display) == 20 ||

drivers/gpu/drm/i915/display/intel_psr.c

969

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

drivers/gpu/drm/i915/display/intel_psr.c

971

intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

drivers/gpu/drm/i915/display/intel_psr.c

978

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

982

if (display->params.psr_safest_params)

drivers/gpu/drm/i915/display/intel_psr.h

40

void intel_psr_invalidate(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.h

43

void intel_psr_flush(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.h

68

void intel_psr_notify_dc5_dc6(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_psr.h

69

void intel_psr_dc5_dc6_wa_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_psr.h

70

void intel_psr_notify_vblank_enable_disable(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_psr.h

81

void intel_psr_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_quirks.c

113

void (*hook)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_quirks.c

14

static void intel_set_quirk(struct intel_display *display, enum intel_quirk_id quirk)

drivers/gpu/drm/i915/display/intel_quirks.c

16

display->quirks.mask |= BIT(quirk);

drivers/gpu/drm/i915/display/intel_quirks.c

257

void intel_init_quirks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

259

struct pci_dev *d = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_quirks.c

27

static void quirk_ssc_force_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

270

q->hook(display);

drivers/gpu/drm/i915/display/intel_quirks.c

274

intel_dmi_quirks[i].hook(display);

drivers/gpu/drm/i915/display/intel_quirks.c

281

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

282

struct pci_dev *d = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_quirks.c

29

intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE);

drivers/gpu/drm/i915/display/intel_quirks.c

30

drm_info(display->drm, "applying lvds SSC disable quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

301

bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk)

drivers/gpu/drm/i915/display/intel_quirks.c

303

return display->quirks.mask & BIT(quirk);

drivers/gpu/drm/i915/display/intel_quirks.c

37

static void quirk_invert_brightness(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

39

intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS);

drivers/gpu/drm/i915/display/intel_quirks.c

40

drm_info(display->drm, "applying inverted panel brightness quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

44

static void quirk_backlight_present(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

46

intel_set_quirk(display, QUIRK_BACKLIGHT_PRESENT);

drivers/gpu/drm/i915/display/intel_quirks.c

47

drm_info(display->drm, "applying backlight present quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

53

static void quirk_increase_t12_delay(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

55

intel_set_quirk(display, QUIRK_INCREASE_T12_DELAY);

drivers/gpu/drm/i915/display/intel_quirks.c

56

drm_info(display->drm, "Applying T12 delay quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

63

static void quirk_increase_ddi_disabled_time(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

65

intel_set_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME);

drivers/gpu/drm/i915/display/intel_quirks.c

66

drm_info(display->drm, "Applying Increase DDI Disabled quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

69

static void quirk_no_pps_backlight_power_hook(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

71

intel_set_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK);

drivers/gpu/drm/i915/display/intel_quirks.c

72

drm_info(display->drm, "Applying no pps backlight power quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

77

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

80

drm_info(display->drm, "Applying Fast Wake sync pulse count quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

83

static void quirk_edp_limit_rate_hbr2(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_quirks.c

85

intel_set_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2);

drivers/gpu/drm/i915/display/intel_quirks.c

86

drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");

drivers/gpu/drm/i915/display/intel_quirks.c

93

void (*hook)(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_quirks.h

26

void intel_init_quirks(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_quirks.h

29

bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk);

drivers/gpu/drm/i915/display/intel_sbi.c

16

static int intel_sbi_rw(struct intel_display *display, u16 reg,

drivers/gpu/drm/i915/display/intel_sbi.c

22

lockdep_assert_held(&display->sbi.lock);

drivers/gpu/drm/i915/display/intel_sbi.c

24

if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,

drivers/gpu/drm/i915/display/intel_sbi.c

26

drm_err(display->drm, "timeout waiting for SBI to become ready\n");

drivers/gpu/drm/i915/display/intel_sbi.c

30

intel_de_write_fw(display, SBI_ADDR, SBI_ADDR_VALUE(reg));

drivers/gpu/drm/i915/display/intel_sbi.c

31

intel_de_write_fw(display, SBI_DATA, is_read ? 0 : *val);

drivers/gpu/drm/i915/display/intel_sbi.c

39

intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);

drivers/gpu/drm/i915/display/intel_sbi.c

41

if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,

drivers/gpu/drm/i915/display/intel_sbi.c

43

drm_err(display->drm, "timeout waiting for SBI to complete read\n");

drivers/gpu/drm/i915/display/intel_sbi.c

48

drm_err(display->drm, "error during SBI read of reg %x\n", reg);

drivers/gpu/drm/i915/display/intel_sbi.c

53

*val = intel_de_read_fw(display, SBI_DATA);

drivers/gpu/drm/i915/display/intel_sbi.c

58

void intel_sbi_lock(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_sbi.c

60

mutex_lock(&display->sbi.lock);

drivers/gpu/drm/i915/display/intel_sbi.c

63

void intel_sbi_unlock(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_sbi.c

65

mutex_unlock(&display->sbi.lock);

drivers/gpu/drm/i915/display/intel_sbi.c

68

u32 intel_sbi_read(struct intel_display *display, u16 reg,

drivers/gpu/drm/i915/display/intel_sbi.c

73

intel_sbi_rw(display, reg, destination, &result, true);

drivers/gpu/drm/i915/display/intel_sbi.c

78

void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,

drivers/gpu/drm/i915/display/intel_sbi.c

81

intel_sbi_rw(display, reg, destination, &value, false);

drivers/gpu/drm/i915/display/intel_sbi.c

84

void intel_sbi_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_sbi.c

86

mutex_init(&display->sbi.lock);

drivers/gpu/drm/i915/display/intel_sbi.c

89

void intel_sbi_fini(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_sbi.c

91

mutex_destroy(&display->sbi.lock);

drivers/gpu/drm/i915/display/intel_sbi.h

18

void intel_sbi_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_sbi.h

19

void intel_sbi_fini(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_sbi.h

20

void intel_sbi_lock(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_sbi.h

21

void intel_sbi_unlock(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_sbi.h

22

u32 intel_sbi_read(struct intel_display *display, u16 reg,

drivers/gpu/drm/i915/display/intel_sbi.h

24

void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,

drivers/gpu/drm/i915/display/intel_sdvo.c

1011

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1024

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1051

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1081

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1102

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1128

if (drm_WARN_ON(display->drm, ret))

drivers/gpu/drm/i915/display/intel_sdvo.c

1137

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1146

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1151

if (drm_WARN_ON(display->drm, len < 0))

drivers/gpu/drm/i915/display/intel_sdvo.c

1162

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1174

drm_dbg_kms(display->drm, "failed to read AVI infoframe\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

1185

drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

1190

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1198

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1214

drm_dbg_kms(display->drm, "failed to read ELD\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

1284

struct intel_display *display = to_intel_display(pipe_config);

drivers/gpu/drm/i915/display/intel_sdvo.c

1305

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1361

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_sdvo.c

1368

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1374

drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

1453

drm_dbg_kms(display->drm, "bad AVI infoframe\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

1527

struct intel_display *display = to_intel_display(intel_encoder);

drivers/gpu/drm/i915/display/intel_sdvo.c

1572

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1602

drm_info(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1608

drm_WARN(display->drm, 1,

drivers/gpu/drm/i915/display/intel_sdvo.c

1619

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1623

if (DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_sdvo.c

1626

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1634

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

1639

if (DISPLAY_VER(display) >= 4) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1641

} else if (display->platform.i945g || display->platform.i945gm ||

drivers/gpu/drm/i915/display/intel_sdvo.c

1642

display->platform.g33 || display->platform.pineview) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1650

DISPLAY_VER(display) < 5)

drivers/gpu/drm/i915/display/intel_sdvo.c

1667

bool intel_sdvo_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sdvo.c

1672

val = intel_de_read(display, sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1675

if (HAS_PCH_CPT(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

1677

else if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_sdvo.c

1688

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_sdvo.c

1695

ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe);

drivers/gpu/drm/i915/display/intel_sdvo.c

1703

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_sdvo.c

1714

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1722

drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

1745

if (display->platform.i915g || display->platform.i915gm) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1774

drm_WARN(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1839

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_sdvo.c

1849

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1859

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1864

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_sdvo.c

1865

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

drivers/gpu/drm/i915/display/intel_sdvo.c

1874

intel_wait_for_vblank_if_active(display, PIPE_A);

drivers/gpu/drm/i915/display/intel_sdvo.c

1875

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_sdvo.c

1876

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

drivers/gpu/drm/i915/display/intel_sdvo.c

1900

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_sdvo.c

1910

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1925

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

1940

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

1945

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_sdvo.c

1949

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_sdvo.c

1981

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

1989

drm_dbg_kms(display->drm, "SDVO capabilities:\n"

drivers/gpu/drm/i915/display/intel_sdvo.c

2031

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2034

if (!HAS_HOTPLUG(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

2041

if (display->platform.i945g || display->platform.i945gm)

drivers/gpu/drm/i915/display/intel_sdvo.c

2085

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

2088

ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);

drivers/gpu/drm/i915/display/intel_sdvo.c

2139

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

2145

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

2148

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

2151

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

216

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2163

drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

2199

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

220

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_sdvo.c

2206

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

221

intel_de_write(display, intel_sdvo->sdvo_reg, val);

drivers/gpu/drm/i915/display/intel_sdvo.c

222

intel_de_posting_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

227

if (HAS_PCH_IBX(display)) {

drivers/gpu/drm/i915/display/intel_sdvo.c

228

intel_de_write(display, intel_sdvo->sdvo_reg, val);

drivers/gpu/drm/i915/display/intel_sdvo.c

229

intel_de_posting_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

2300

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

2310

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

2313

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

235

cval = intel_de_read(display, GEN3_SDVOC);

drivers/gpu/drm/i915/display/intel_sdvo.c

2352

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

2354

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

237

bval = intel_de_read(display, GEN3_SDVOB);

drivers/gpu/drm/i915/display/intel_sdvo.c

245

intel_de_write(display, GEN3_SDVOB, bval);

drivers/gpu/drm/i915/display/intel_sdvo.c

246

intel_de_posting_read(display, GEN3_SDVOB);

drivers/gpu/drm/i915/display/intel_sdvo.c

248

intel_de_write(display, GEN3_SDVOC, cval);

drivers/gpu/drm/i915/display/intel_sdvo.c

249

intel_de_posting_read(display, GEN3_SDVOC);

drivers/gpu/drm/i915/display/intel_sdvo.c

255

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2618

struct intel_display *display = to_intel_display(&sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2623

mapping = &display->vbt.sdvo_mappings[0];

drivers/gpu/drm/i915/display/intel_sdvo.c

2625

mapping = &display->vbt.sdvo_mappings[1];

drivers/gpu/drm/i915/display/intel_sdvo.c

2641

struct intel_display *display = to_intel_display(&sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2646

mapping = &display->vbt.sdvo_mappings[0];

drivers/gpu/drm/i915/display/intel_sdvo.c

2648

mapping = &display->vbt.sdvo_mappings[1];

drivers/gpu/drm/i915/display/intel_sdvo.c

2651

intel_gmbus_is_valid_pin(display, mapping->i2c_pin))

drivers/gpu/drm/i915/display/intel_sdvo.c

2656

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

2660

sdvo->i2c = intel_gmbus_get_adapter(display, pin);

drivers/gpu/drm/i915/display/intel_sdvo.c

2686

struct intel_display *display = to_intel_display(&sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2690

my_mapping = &display->vbt.sdvo_mappings[0];

drivers/gpu/drm/i915/display/intel_sdvo.c

2691

other_mapping = &display->vbt.sdvo_mappings[1];

drivers/gpu/drm/i915/display/intel_sdvo.c

2693

my_mapping = &display->vbt.sdvo_mappings[1];

drivers/gpu/drm/i915/display/intel_sdvo.c

2694

other_mapping = &display->vbt.sdvo_mappings[0];

drivers/gpu/drm/i915/display/intel_sdvo.c

2730

struct intel_display *display = to_intel_display(&encoder->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

275

drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret);

drivers/gpu/drm/i915/display/intel_sdvo.c

2755

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

2798

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2805

drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type);

drivers/gpu/drm/i915/display/intel_sdvo.c

2851

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2857

drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type);

drivers/gpu/drm/i915/display/intel_sdvo.c

2891

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2897

drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type);

drivers/gpu/drm/i915/display/intel_sdvo.c

2923

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

2929

drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type);

drivers/gpu/drm/i915/display/intel_sdvo.c

2950

intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL);

drivers/gpu/drm/i915/display/intel_sdvo.c

2959

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_sdvo.c

2964

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_sdvo.c

3013

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3032

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

3055

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3059

&display->drm->mode_config.connector_list, head) {

drivers/gpu/drm/i915/display/intel_sdvo.c

3071

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3096

drm_property_create(display->drm, DRM_MODE_PROP_ENUM,

drivers/gpu/drm/i915/display/intel_sdvo.c

3118

drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \

drivers/gpu/drm/i915/display/intel_sdvo.c

3123

drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \

drivers/gpu/drm/i915/display/intel_sdvo.c

3135

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3158

drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]);

drivers/gpu/drm/i915/display/intel_sdvo.c

3166

drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]);

drivers/gpu/drm/i915/display/intel_sdvo.c

3172

drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

3191

drm_property_create_range(display->drm, 0,

drivers/gpu/drm/i915/display/intel_sdvo.c

3200

drm_property_create_range(display->drm, 0,

drivers/gpu/drm/i915/display/intel_sdvo.c

3207

drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

3230

drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1);

drivers/gpu/drm/i915/display/intel_sdvo.c

3236

drm_dbg_kms(display->drm, "dot crawl: current %d\n", response);

drivers/gpu/drm/i915/display/intel_sdvo.c

3247

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3261

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3273

drm_dbg_kms(display->drm, "No enhancement is supported\n");

drivers/gpu/drm/i915/display/intel_sdvo.c

3348

struct intel_display *display = to_intel_display(&sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

3349

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_sdvo.c

3365

static bool is_sdvo_port_valid(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_sdvo.c

3367

if (HAS_PCH_SPLIT(display))

drivers/gpu/drm/i915/display/intel_sdvo.c

3373

static bool assert_sdvo_port_valid(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/intel_sdvo.c

3375

return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port),

drivers/gpu/drm/i915/display/intel_sdvo.c

3379

bool intel_sdvo_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sdvo.c

3386

if (!assert_port_valid(display, port))

drivers/gpu/drm/i915/display/intel_sdvo.c

3389

if (!assert_sdvo_port_valid(display, port))

drivers/gpu/drm/i915/display/intel_sdvo.c

3402

drm_encoder_init(display->drm, &intel_encoder->base,

drivers/gpu/drm/i915/display/intel_sdvo.c

3416

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

3424

if (HAS_PCH_SPLIT(display)) {

drivers/gpu/drm/i915/display/intel_sdvo.c

3454

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sdvo.c

3491

drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, "

drivers/gpu/drm/i915/display/intel_sdvo.c

417

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

438

drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);

drivers/gpu/drm/i915/display/intel_sdvo.c

441

drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),

drivers/gpu/drm/i915/display/intel_sdvo.c

467

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

517

drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret);

drivers/gpu/drm/i915/display/intel_sdvo.c

523

drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3);

drivers/gpu/drm/i915/display/intel_sdvo.c

542

struct intel_display *display = to_intel_display(&intel_sdvo->base);

drivers/gpu/drm/i915/display/intel_sdvo.c

607

drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);

drivers/gpu/drm/i915/display/intel_sdvo.c

610

drm_dbg_kms(display->drm, "%s: R: %s\n",

drivers/gpu/drm/i915/display/intel_sdvo.c

615

drm_dbg_kms(display->drm, "%s: R: ... failed %s\n",

drivers/gpu/drm/i915/display/intel_sdvo.h

18

bool intel_sdvo_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sdvo.h

20

bool intel_sdvo_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sdvo.h

23

static inline bool intel_sdvo_port_enabled(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sdvo.h

28

static inline bool intel_sdvo_init(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_snps_phy.c

1822

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1832

intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1833

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1834

intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1835

intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1836

intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1837

intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1838

intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1849

intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1858

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy),

drivers/gpu/drm/i915/display/intel_snps_phy.c

1866

if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))

drivers/gpu/drm/i915/display/intel_snps_phy.c

1867

drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1880

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1894

intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1900

intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1906

if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))

drivers/gpu/drm/i915/display/intel_snps_phy.c

1907

drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1952

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1955

pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1956

pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1957

pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1958

pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1959

pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1960

pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1961

pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1969

pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &

drivers/gpu/drm/i915/display/intel_snps_phy.c

1984

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1991

if (!display->platform.dg2)

drivers/gpu/drm/i915/display/intel_snps_phy.c

2006

INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \

drivers/gpu/drm/i915/display/intel_snps_phy.c

32

void intel_snps_phy_wait_for_calibration(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_snps_phy.c

37

if (!intel_phy_is_snps(display, phy))

drivers/gpu/drm/i915/display/intel_snps_phy.c

45

if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),

drivers/gpu/drm/i915/display/intel_snps_phy.c

47

display->snps.phy_failed_calibration |= BIT(phy);

drivers/gpu/drm/i915/display/intel_snps_phy.c

54

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_snps_phy.c

63

intel_de_rmw(display, SNPS_PHY_TX_REQ(phy),

drivers/gpu/drm/i915/display/intel_snps_phy.c

70

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_snps_phy.c

76

if (drm_WARN_ON_ONCE(display->drm, !trans))

drivers/gpu/drm/i915/display/intel_snps_phy.c

87

intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val);

drivers/gpu/drm/i915/display/intel_snps_phy.h

19

void intel_snps_phy_wait_for_calibration(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_sprite.c

1011

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1019

if (display->platform.sandybridge)

drivers/gpu/drm/i915/display/intel_sprite.c

104

intel_de_write_fw(display, SPCSCYGOFF(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

106

intel_de_write_fw(display, SPCSCCBOFF(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

108

intel_de_write_fw(display, SPCSCCROFF(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1080

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1096

intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),

drivers/gpu/drm/i915/display/intel_sprite.c

111

intel_de_write_fw(display, SPCSCC01(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1110

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1125

intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),

drivers/gpu/drm/i915/display/intel_sprite.c

1128

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

1129

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

113

intel_de_write_fw(display, SPCSCC23(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1130

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

1140

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

115

intel_de_write_fw(display, SPCSCC45(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1155

intel_de_write_fw(display, DVSSTRIDE(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

1157

intel_de_write_fw(display, DVSPOS(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

1159

intel_de_write_fw(display, DVSSIZE(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

1161

intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);

drivers/gpu/drm/i915/display/intel_sprite.c

117

intel_de_write_fw(display, SPCSCC67(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1170

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1180

intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);

drivers/gpu/drm/i915/display/intel_sprite.c

1181

intel_de_write_fw(display, DVSKEYMSK(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

1183

intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);

drivers/gpu/drm/i915/display/intel_sprite.c

1186

intel_de_write_fw(display, DVSLINOFF(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

1188

intel_de_write_fw(display, DVSTILEOFF(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

119

intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));

drivers/gpu/drm/i915/display/intel_sprite.c

1196

intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);

drivers/gpu/drm/i915/display/intel_sprite.c

1197

intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

1199

if (display->platform.g4x)

drivers/gpu/drm/i915/display/intel_sprite.c

121

intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1210

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1213

intel_de_write_fw(display, DVSCNTR(pipe), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

1215

intel_de_write_fw(display, DVSSCALE(pipe), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

1216

intel_de_write_fw(display, DVSSURF(pipe), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

1223

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1225

error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

1226

error->surf = intel_de_read(display, DVSSURF(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

1227

error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

123

intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1234

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1240

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_sprite.c

1244

ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;

drivers/gpu/drm/i915/display/intel_sprite.c

1248

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_sprite.c

125

intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1274

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

128

intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

130

intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1300

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sprite.c

1313

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sprite.c

132

intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

1320

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sprite.c

1327

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sprite.c

1340

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1346

if (DISPLAY_VER(display) < 7) {

drivers/gpu/drm/i915/display/intel_sprite.c

1349

} else if (display->platform.ivybridge) {

drivers/gpu/drm/i915/display/intel_sprite.c

1375

if (DISPLAY_VER(display) >= 7)

drivers/gpu/drm/i915/display/intel_sprite.c

1385

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1389

if (display->platform.cherryview &&

drivers/gpu/drm/i915/display/intel_sprite.c

1392

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_sprite.c

142

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1594

intel_sprite_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sprite.c

1609

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/intel_sprite.c

1622

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_sprite.c

1625

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_sprite.c

1634

} else if (DISPLAY_VER(display) >= 7) {

drivers/gpu/drm/i915/display/intel_sprite.c

1643

if (display->platform.broadwell || display->platform.haswell) {

drivers/gpu/drm/i915/display/intel_sprite.c

1653

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_sprite.c

1672

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_sprite.c

1675

if (display->platform.sandybridge) {

drivers/gpu/drm/i915/display/intel_sprite.c

1688

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_sprite.c

1701

modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);

drivers/gpu/drm/i915/display/intel_sprite.c

1703

ret = drm_universal_plane_init(display->drm, &plane->base,

drivers/gpu/drm/i915/display/intel_sprite.c

1707

"sprite %c", sprite_name(display, pipe, sprite));

drivers/gpu/drm/i915/display/intel_sprite.c

172

intel_de_write_fw(display, SPCLRC0(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

174

intel_de_write_fw(display, SPCLRC1(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

344

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

361

intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),

drivers/gpu/drm/i915/display/intel_sprite.c

371

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

379

intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

381

intel_de_write_fw(display, SPPOS(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

383

intel_de_write_fw(display, SPSIZE(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

393

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

403

if (display->platform.cherryview && pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_sprite.c

407

intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

409

intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

411

intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

415

intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

417

intel_de_write_fw(display, SPLINOFF(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

419

intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

427

intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);

drivers/gpu/drm/i915/display/intel_sprite.c

428

intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

439

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

443

intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

444

intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

451

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

453

error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/intel_sprite.c

454

error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/intel_sprite.c

455

error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/intel_sprite.c

462

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

469

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

drivers/gpu/drm/i915/display/intel_sprite.c

477

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_sprite.c

52

static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)

drivers/gpu/drm/i915/display/intel_sprite.c

54

return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';

drivers/gpu/drm/i915/display/intel_sprite.c

655

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

659

(display->platform.ivybridge || display->platform.haswell);

drivers/gpu/drm/i915/display/intel_sprite.c

664

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

672

if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_sprite.c

70

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

761

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

774

intel_de_write_fw(display, SPRGAMC(pipe, i),

drivers/gpu/drm/i915/display/intel_sprite.c

777

intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

778

intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

779

intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

782

intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

783

intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

784

intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);

drivers/gpu/drm/i915/display/intel_sprite.c

794

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

809

intel_de_write_fw(display, SPRSTRIDE(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

811

intel_de_write_fw(display, SPRPOS(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

813

intel_de_write_fw(display, SPRSIZE(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

815

if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_sprite.c

816

intel_de_write_fw(display, SPRSCALE(pipe), sprscale);

drivers/gpu/drm/i915/display/intel_sprite.c

825

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

835

intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);

drivers/gpu/drm/i915/display/intel_sprite.c

836

intel_de_write_fw(display, SPRKEYMSK(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

838

intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);

drivers/gpu/drm/i915/display/intel_sprite.c

843

if (display->platform.haswell || display->platform.broadwell) {

drivers/gpu/drm/i915/display/intel_sprite.c

844

intel_de_write_fw(display, SPROFFSET(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

847

intel_de_write_fw(display, SPRLINOFF(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

849

intel_de_write_fw(display, SPRTILEOFF(pipe),

drivers/gpu/drm/i915/display/intel_sprite.c

858

intel_de_write_fw(display, SPRCTL(pipe), sprctl);

drivers/gpu/drm/i915/display/intel_sprite.c

859

intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

869

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

872

intel_de_write_fw(display, SPRCTL(pipe), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

874

if (display->platform.ivybridge)

drivers/gpu/drm/i915/display/intel_sprite.c

875

intel_de_write_fw(display, SPRSCALE(pipe), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

876

intel_de_write_fw(display, SPRSURF(pipe), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

883

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

885

error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

886

error->surf = intel_de_read(display, SPRSURF(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

887

error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

894

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

900

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

drivers/gpu/drm/i915/display/intel_sprite.c

908

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_sprite.c

988

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/intel_sprite.c

990

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/intel_sprite.h

17

struct intel_plane *intel_sprite_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sprite.h

29

static inline struct intel_plane *intel_sprite_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

101

if (!ret && has_dst_key_in_primary_plane(display)) {

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

103

intel_crtc_for_pipe(display,

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

11

static bool has_dst_key_in_primary_plane(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

13

return DISPLAY_VER(display) >= 9;

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

19

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

37

if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_PRIMARY &&

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

45

struct intel_display *display = to_intel_display(dev);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

63

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

76

if (DISPLAY_VER(display) >= 9 &&

drivers/gpu/drm/i915/display/intel_tc.c

1008

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1011

u32 pica_isr_bits = display->hotplug.hpd[hpd_pin];

drivers/gpu/drm/i915/display/intel_tc.c

1012

u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];

drivers/gpu/drm/i915/display/intel_tc.c

1017

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) {

drivers/gpu/drm/i915/display/intel_tc.c

1018

pica_isr = intel_de_read(display, PICAINTERRUPT_ISR);

drivers/gpu/drm/i915/display/intel_tc.c

1019

pch_isr = intel_de_read(display, SDEISR);

drivers/gpu/drm/i915/display/intel_tc.c

1036

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1038

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_tc.c

1042

return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;

drivers/gpu/drm/i915/display/intel_tc.c

1048

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1056

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1070

static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/display/intel_tc.c

1073

if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,

drivers/gpu/drm/i915/display/intel_tc.c

1075

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1080

intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable ? 1 : 0);

drivers/gpu/drm/i915/display/intel_tc.c

1081

intel_de_write(display, TCSS_DISP_MAILBOX_IN_CMD,

drivers/gpu/drm/i915/display/intel_tc.c

1086

if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,

drivers/gpu/drm/i915/display/intel_tc.c

1088

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1096

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1098

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_tc.c

1103

if (DISPLAY_VER(display) == 30)

drivers/gpu/drm/i915/display/intel_tc.c

1104

xelpdp_tc_power_request_wa(display, enable);

drivers/gpu/drm/i915/display/intel_tc.c

1106

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_tc.c

1111

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_tc.c

1116

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1129

if (drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY))

drivers/gpu/drm/i915/display/intel_tc.c

1143

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1145

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_tc.c

1150

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_tc.c

1155

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/intel_tc.c

1160

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1162

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

drivers/gpu/drm/i915/display/intel_tc.c

1166

return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;

drivers/gpu/drm/i915/display/intel_tc.c

1171

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1190

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1268

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1274

drm_WARN_ON_ONCE(display->drm, hweight32(mask) > 1);

drivers/gpu/drm/i915/display/intel_tc.c

1298

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1300

if (DISPLAY_VER(display) < 20) {

drivers/gpu/drm/i915/display/intel_tc.c

1301

drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);

drivers/gpu/drm/i915/display/intel_tc.c

1312

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1322

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1335

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1343

drm_err(display->drm, "Port %s: timeout waiting for PHY ready\n",

drivers/gpu/drm/i915/display/intel_tc.c

1413

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1433

drm_WARN_ON(display->drm, live_mode == TC_PORT_TBT_ALT);

drivers/gpu/drm/i915/display/intel_tc.c

1437

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1477

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1491

drm_WARN_ON(display->drm, !connected);

drivers/gpu/drm/i915/display/intel_tc.c

1512

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1516

intel_display_power_flush_work(display);

drivers/gpu/drm/i915/display/intel_tc.c

1521

if (intel_display_power_is_enabled(display, aux_domain))

drivers/gpu/drm/i915/display/intel_tc.c

1522

drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n",

drivers/gpu/drm/i915/display/intel_tc.c

1530

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1564

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1569

return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &

drivers/gpu/drm/i915/display/intel_tc.c

1582

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1588

drm_WARN_ON(display->drm, tc->mode != TC_PORT_DISCONNECTED);

drivers/gpu/drm/i915/display/intel_tc.c

1589

drm_WARN_ON(display->drm, tc->lock_wakeref);

drivers/gpu/drm/i915/display/intel_tc.c

1590

drm_WARN_ON(display->drm, tc->link_refcount);

drivers/gpu/drm/i915/display/intel_tc.c

1613

drm_WARN_ON(display->drm, !tc->legacy_port);

drivers/gpu/drm/i915/display/intel_tc.c

1614

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1632

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1646

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1668

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1673

drm_WARN_ON(display->drm, tc->link_refcount != 1);

drivers/gpu/drm/i915/display/intel_tc.c

1683

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1691

drm_dbg_kms(display->drm, "Port %s: sanitize mode (%s) pin assignment: %c max lanes: %d\n",

drivers/gpu/drm/i915/display/intel_tc.c

1725

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tc.c

1730

drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));

drivers/gpu/drm/i915/display/intel_tc.c

1765

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1772

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, ctx);

drivers/gpu/drm/i915/display/intel_tc.c

178

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1783

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

drivers/gpu/drm/i915/display/intel_tc.c

1801

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1807

_state = drm_atomic_state_alloc(display->drm);

drivers/gpu/drm/i915/display/intel_tc.c

182

intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

drivers/gpu/drm/i915/display/intel_tc.c

1826

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1832

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_tc.c

1834

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

1838

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/intel_tc.c

1840

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/intel_tc.c

1868

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1878

drm_WARN_ON(display->drm, tc->mode == TC_PORT_DISCONNECTED);

drivers/gpu/drm/i915/display/intel_tc.c

1879

drm_WARN_ON(display->drm, tc->mode != TC_PORT_TBT_ALT && !tc_phy_is_owned(tc));

drivers/gpu/drm/i915/display/intel_tc.c

188

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

192

return intel_display_power_get(display, *domain);

drivers/gpu/drm/i915/display/intel_tc.c

1972

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

1977

if (drm_WARN_ON(display->drm, tc_port == TC_PORT_NONE))

drivers/gpu/drm/i915/display/intel_tc.c

1987

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_tc.c

1989

else if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_tc.c

1991

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_tc.c

212

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

214

intel_display_power_put(display, domain, wakeref);

drivers/gpu/drm/i915/display/intel_tc.c

220

struct intel_display __maybe_unused *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

224

drm_WARN_ON(display->drm, tc->lock_power_domain != domain);

drivers/gpu/drm/i915/display/intel_tc.c

232

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

234

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

235

!intel_display_power_is_enabled(display, POWER_DOMAIN_DISPLAY_CORE));

drivers/gpu/drm/i915/display/intel_tc.c

241

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

244

enabled = intel_display_power_is_enabled(display,

drivers/gpu/drm/i915/display/intel_tc.c

246

drm_WARN_ON(display->drm, !enabled);

drivers/gpu/drm/i915/display/intel_tc.c

263

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

265

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

266

!intel_display_power_is_enabled(display, tc_port_power_domain(tc)));

drivers/gpu/drm/i915/display/intel_tc.c

271

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

274

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE)

drivers/gpu/drm/i915/display/intel_tc.c

275

lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

277

drm_WARN_ON(display->drm, lane_mask == 0xffffffff);

drivers/gpu/drm/i915/display/intel_tc.c

295

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

305

if (DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/intel_tc.c

313

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE)

drivers/gpu/drm/i915/display/intel_tc.c

314

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_tc.c

316

drm_WARN_ON(display->drm, val == 0xffffffff);

drivers/gpu/drm/i915/display/intel_tc.c

325

drm_WARN_ON(display->drm, DISPLAY_VER(display) > 11);

drivers/gpu/drm/i915/display/intel_tc.c

384

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

389

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_tc.c

425

struct intel_display *display = to_intel_display(dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

430

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_tc.c

433

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

438

val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

459

intel_de_write(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia), val);

drivers/gpu/drm/i915/display/intel_tc.c

465

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

468

drm_WARN_ON(display->drm, tc->mode != TC_PORT_DISCONNECTED);

drivers/gpu/drm/i915/display/intel_tc.c

483

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

514

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

518

return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

drivers/gpu/drm/i915/display/intel_tc.c

525

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

527

u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin];

drivers/gpu/drm/i915/display/intel_tc.c

532

with_intel_display_power(display, tc_phy_cold_off_domain(tc)) {

drivers/gpu/drm/i915/display/intel_tc.c

533

fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

534

pch_isr = intel_de_read(display, SDEISR);

drivers/gpu/drm/i915/display/intel_tc.c

538

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

565

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

570

val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

572

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

584

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

589

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

591

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

602

intel_de_write(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia), val);

drivers/gpu/drm/i915/display/intel_tc.c

609

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

614

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

616

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

656

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

662

drm_WARN_ON(display->drm, max_lanes != 4);

drivers/gpu/drm/i915/display/intel_tc.c

666

drm_WARN_ON(display->drm, tc->mode != TC_PORT_DP_ALT);

drivers/gpu/drm/i915/display/intel_tc.c

673

drm_dbg_kms(display->drm, "Port %s: PHY sudden disconnect\n",

drivers/gpu/drm/i915/display/intel_tc.c

679

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

692

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

704

!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {

drivers/gpu/drm/i915/display/intel_tc.c

705

drm_dbg_kms(display->drm, "Port %s: can't take PHY ownership (ready %s)\n",

drivers/gpu/drm/i915/display/intel_tc.c

773

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

776

with_intel_display_power(display, tc_phy_cold_off_domain(tc))

drivers/gpu/drm/i915/display/intel_tc.c

777

val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));

drivers/gpu/drm/i915/display/intel_tc.c

779

drm_WARN_ON(display->drm, val == 0xffffffff);

drivers/gpu/drm/i915/display/intel_tc.c

802

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

806

return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

drivers/gpu/drm/i915/display/intel_tc.c

813

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

816

u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin];

drivers/gpu/drm/i915/display/intel_tc.c

817

u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];

drivers/gpu/drm/i915/display/intel_tc.c

822

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) {

drivers/gpu/drm/i915/display/intel_tc.c

823

cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR);

drivers/gpu/drm/i915/display/intel_tc.c

824

pch_isr = intel_de_read(display, SDEISR);

drivers/gpu/drm/i915/display/intel_tc.c

847

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

853

val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));

drivers/gpu/drm/i915/display/intel_tc.c

855

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tc.c

867

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

872

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,

drivers/gpu/drm/i915/display/intel_tc.c

880

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

886

val = intel_de_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_tc.c

892

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

897

port_wakeref = intel_display_power_get(display, port_power_domain);

drivers/gpu/drm/i915/display/intel_tc.c

906

intel_display_power_put(display, port_power_domain, port_wakeref);

drivers/gpu/drm/i915/display/intel_tc.c

911

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

924

port_wakeref = intel_display_power_get(display, port_power_domain);

drivers/gpu/drm/i915/display/intel_tc.c

927

!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {

drivers/gpu/drm/i915/display/intel_tc.c

928

drm_dbg_kms(display->drm, "Port %s: can't take PHY ownership\n",

drivers/gpu/drm/i915/display/intel_tc.c

934

!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {

drivers/gpu/drm/i915/display/intel_tc.c

935

drm_dbg_kms(display->drm, "Port %s: PHY not ready\n",

drivers/gpu/drm/i915/display/intel_tc.c

947

intel_display_power_put(display, port_power_domain, port_wakeref);

drivers/gpu/drm/i915/display/intel_tc.c

956

intel_display_power_put(display, port_power_domain, port_wakeref);

drivers/gpu/drm/i915/display/intel_tc.c

963

struct intel_display *display = to_intel_display(tc->dig_port);

drivers/gpu/drm/i915/display/intel_tc.c

968

port_wakeref = intel_display_power_get(display, port_power_domain);

drivers/gpu/drm/i915/display/intel_tc.c

983

intel_display_power_put(display, port_power_domain, port_wakeref);

drivers/gpu/drm/i915/display/intel_tdf.h

20

static inline void intel_td_flush(struct intel_display *display) {}

drivers/gpu/drm/i915/display/intel_tdf.h

22

void intel_td_flush(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_tv.c

1094

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tv.c

1106

tv_ctl = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1107

hctl1 = intel_de_read(display, TV_H_CTL_1);

drivers/gpu/drm/i915/display/intel_tv.c

1108

hctl3 = intel_de_read(display, TV_H_CTL_3);

drivers/gpu/drm/i915/display/intel_tv.c

1109

vctl1 = intel_de_read(display, TV_V_CTL_1);

drivers/gpu/drm/i915/display/intel_tv.c

1110

vctl2 = intel_de_read(display, TV_V_CTL_2);

drivers/gpu/drm/i915/display/intel_tv.c

1145

tmp = intel_de_read(display, TV_WIN_POS);

drivers/gpu/drm/i915/display/intel_tv.c

1149

tmp = intel_de_read(display, TV_WIN_SIZE);

drivers/gpu/drm/i915/display/intel_tv.c

1155

drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",

drivers/gpu/drm/i915/display/intel_tv.c

1168

if (display->platform.i965gm)

drivers/gpu/drm/i915/display/intel_tv.c

1173

static bool intel_tv_source_too_wide(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_tv.c

1176

return DISPLAY_VER(display) == 3 && hdisplay > 1024;

drivers/gpu/drm/i915/display/intel_tv.c

1194

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tv.c

1216

drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n");

drivers/gpu/drm/i915/display/intel_tv.c

1230

if (intel_tv_source_too_wide(display, hdisplay) ||

drivers/gpu/drm/i915/display/intel_tv.c

1237

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tv.c

1271

drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",

drivers/gpu/drm/i915/display/intel_tv.c

1349

if (display->platform.i965gm)

drivers/gpu/drm/i915/display/intel_tv.c

1357

set_tv_mode_timings(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_tv.c

1403

intel_de_write(display, TV_H_CTL_1, hctl1);

drivers/gpu/drm/i915/display/intel_tv.c

1404

intel_de_write(display, TV_H_CTL_2, hctl2);

drivers/gpu/drm/i915/display/intel_tv.c

1405

intel_de_write(display, TV_H_CTL_3, hctl3);

drivers/gpu/drm/i915/display/intel_tv.c

1406

intel_de_write(display, TV_V_CTL_1, vctl1);

drivers/gpu/drm/i915/display/intel_tv.c

1407

intel_de_write(display, TV_V_CTL_2, vctl2);

drivers/gpu/drm/i915/display/intel_tv.c

1408

intel_de_write(display, TV_V_CTL_3, vctl3);

drivers/gpu/drm/i915/display/intel_tv.c

1409

intel_de_write(display, TV_V_CTL_4, vctl4);

drivers/gpu/drm/i915/display/intel_tv.c

1410

intel_de_write(display, TV_V_CTL_5, vctl5);

drivers/gpu/drm/i915/display/intel_tv.c

1411

intel_de_write(display, TV_V_CTL_6, vctl6);

drivers/gpu/drm/i915/display/intel_tv.c

1412

intel_de_write(display, TV_V_CTL_7, vctl7);

drivers/gpu/drm/i915/display/intel_tv.c

1415

static void set_color_conversion(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_tv.c

1418

intel_de_write(display, TV_CSC_Y,

drivers/gpu/drm/i915/display/intel_tv.c

1420

intel_de_write(display, TV_CSC_Y2,

drivers/gpu/drm/i915/display/intel_tv.c

1422

intel_de_write(display, TV_CSC_U,

drivers/gpu/drm/i915/display/intel_tv.c

1424

intel_de_write(display, TV_CSC_U2,

drivers/gpu/drm/i915/display/intel_tv.c

1426

intel_de_write(display, TV_CSC_V,

drivers/gpu/drm/i915/display/intel_tv.c

1428

intel_de_write(display, TV_CSC_V2,

drivers/gpu/drm/i915/display/intel_tv.c

1437

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tv.c

1452

tv_ctl = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1524

if (display->platform.i915gm)

drivers/gpu/drm/i915/display/intel_tv.c

1527

set_tv_mode_timings(display, tv_mode, burst_ena);

drivers/gpu/drm/i915/display/intel_tv.c

1529

intel_de_write(display, TV_SC_CTL_1, scctl1);

drivers/gpu/drm/i915/display/intel_tv.c

1530

intel_de_write(display, TV_SC_CTL_2, scctl2);

drivers/gpu/drm/i915/display/intel_tv.c

1531

intel_de_write(display, TV_SC_CTL_3, scctl3);

drivers/gpu/drm/i915/display/intel_tv.c

1533

set_color_conversion(display, color_conversion);

drivers/gpu/drm/i915/display/intel_tv.c

1535

if (DISPLAY_VER(display) >= 4)

drivers/gpu/drm/i915/display/intel_tv.c

1536

intel_de_write(display, TV_CLR_KNOBS, 0x00404000);

drivers/gpu/drm/i915/display/intel_tv.c

1538

intel_de_write(display, TV_CLR_KNOBS, 0x00606000);

drivers/gpu/drm/i915/display/intel_tv.c

1541

intel_de_write(display, TV_CLR_LEVEL,

drivers/gpu/drm/i915/display/intel_tv.c

1544

assert_transcoder_disabled(display, pipe_config->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_tv.c

1550

intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl);

drivers/gpu/drm/i915/display/intel_tv.c

1561

intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos);

drivers/gpu/drm/i915/display/intel_tv.c

1562

intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize);

drivers/gpu/drm/i915/display/intel_tv.c

1566

intel_de_write(display, TV_H_LUMA(i),

drivers/gpu/drm/i915/display/intel_tv.c

1569

intel_de_write(display, TV_H_CHROMA(i),

drivers/gpu/drm/i915/display/intel_tv.c

1572

intel_de_write(display, TV_V_LUMA(i),

drivers/gpu/drm/i915/display/intel_tv.c

1575

intel_de_write(display, TV_V_CHROMA(i),

drivers/gpu/drm/i915/display/intel_tv.c

1577

intel_de_write(display, TV_DAC,

drivers/gpu/drm/i915/display/intel_tv.c

1578

intel_de_read(display, TV_DAC) & TV_DAC_SAVE);

drivers/gpu/drm/i915/display/intel_tv.c

1579

intel_de_write(display, TV_CTL, tv_ctl);

drivers/gpu/drm/i915/display/intel_tv.c

1586

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_tv.c

1594

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_tv.c

1595

i915_disable_pipestat(display, 0,

drivers/gpu/drm/i915/display/intel_tv.c

1598

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_tv.c

1601

save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1602

save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1624

if (display->platform.gm45)

drivers/gpu/drm/i915/display/intel_tv.c

1628

intel_de_write(display, TV_CTL, tv_ctl);

drivers/gpu/drm/i915/display/intel_tv.c

1629

intel_de_write(display, TV_DAC, tv_dac);

drivers/gpu/drm/i915/display/intel_tv.c

1630

intel_de_posting_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1635

tv_dac = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1636

drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);

drivers/gpu/drm/i915/display/intel_tv.c

1644

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tv.c

1648

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tv.c

1652

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tv.c

1656

drm_dbg_kms(display->drm, "Unrecognised TV connection\n");

drivers/gpu/drm/i915/display/intel_tv.c

1660

intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);

drivers/gpu/drm/i915/display/intel_tv.c

1661

intel_de_write(display, TV_CTL, save_tv_ctl);

drivers/gpu/drm/i915/display/intel_tv.c

1662

intel_de_posting_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1669

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_tv.c

1670

i915_enable_pipestat(display, 0,

drivers/gpu/drm/i915/display/intel_tv.c

1673

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/intel_tv.c

1712

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_tv.c

1717

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",

drivers/gpu/drm/i915/display/intel_tv.c

1720

if (!intel_display_device_enabled(display))

drivers/gpu/drm/i915/display/intel_tv.c

1723

if (!intel_display_driver_check_access(display))

drivers/gpu/drm/i915/display/intel_tv.c

1792

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_tv.c

1806

if (DISPLAY_VER(display) == 3 && input->w > 1024 &&

drivers/gpu/drm/i915/display/intel_tv.c

1823

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_tv.c

1889

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_tv.c

1905

if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1)

drivers/gpu/drm/i915/display/intel_tv.c

1910

drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names);

drivers/gpu/drm/i915/display/intel_tv.c

1913

display->drm->mode_config.legacy_tv_mode_property,

drivers/gpu/drm/i915/display/intel_tv.c

1916

display->drm->mode_config.tv_left_margin_property,

drivers/gpu/drm/i915/display/intel_tv.c

1919

display->drm->mode_config.tv_top_margin_property,

drivers/gpu/drm/i915/display/intel_tv.c

1922

display->drm->mode_config.tv_right_margin_property,

drivers/gpu/drm/i915/display/intel_tv.c

1925

display->drm->mode_config.tv_bottom_margin_property,

drivers/gpu/drm/i915/display/intel_tv.c

1930

intel_tv_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_tv.c

1938

if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)

drivers/gpu/drm/i915/display/intel_tv.c

1941

if (!intel_bios_is_tv_present(display)) {

drivers/gpu/drm/i915/display/intel_tv.c

1942

drm_dbg_kms(display->drm, "Integrated TV is not present.\n");

drivers/gpu/drm/i915/display/intel_tv.c

1950

save_tv_dac = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1952

intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);

drivers/gpu/drm/i915/display/intel_tv.c

1953

tv_dac_on = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1955

intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);

drivers/gpu/drm/i915/display/intel_tv.c

1956

tv_dac_off = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1958

intel_de_write(display, TV_DAC, save_tv_dac);

drivers/gpu/drm/i915/display/intel_tv.c

1996

drm_connector_init(display->drm, connector, &intel_tv_connector_funcs,

drivers/gpu/drm/i915/display/intel_tv.c

1999

drm_encoder_init(display->drm, &intel_encoder->base,

drivers/gpu/drm/i915/display/intel_tv.c

918

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tv.c

919

u32 tmp = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

932

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tv.c

937

intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE);

drivers/gpu/drm/i915/display/intel_tv.c

946

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/intel_tv.c

948

intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);

drivers/gpu/drm/i915/display/intel_tv.c

962

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/intel_tv.c

964

int max_dotclk = display->cdclk.max_dotclk_freq;

drivers/gpu/drm/i915/display/intel_tv.c

967

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/intel_tv.h

12

void intel_tv_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_tv.h

14

static inline void intel_tv_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vblank.c

112

frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),

drivers/gpu/drm/i915/display/intel_vblank.c

113

PIPEFRAME(display, pipe));

drivers/gpu/drm/i915/display/intel_vblank.c

128

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_vblank.c

135

return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));

drivers/gpu/drm/i915/display/intel_vblank.c

140

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vblank.c

159

scan_prev_time = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_vblank.c

166

scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);

drivers/gpu/drm/i915/display/intel_vblank.c

168

scan_post_time = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_vblank.c

201

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

229

if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)

drivers/gpu/drm/i915/display/intel_vblank.c

231

else if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_vblank.c

232

display->platform.broadwell || display->platform.haswell)

drivers/gpu/drm/i915/display/intel_vblank.c

234

else if (DISPLAY_VER(display) >= 3)

drivers/gpu/drm/i915/display/intel_vblank.c

246

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vblank.c

260

position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

274

if (HAS_DDI(display) && !position) {

drivers/gpu/drm/i915/display/intel_vblank.c

279

temp = intel_de_read_fw(display,

drivers/gpu/drm/i915/display/intel_vblank.c

280

PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

306

static void intel_vblank_section_enter(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vblank.c

309

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_vblank.c

313

static void intel_vblank_section_exit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vblank.c

316

struct intel_uncore *uncore = to_intel_uncore(display->drm);

drivers/gpu/drm/i915/display/intel_vblank.c

320

static void intel_vblank_section_enter(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vblank.c

324

static void intel_vblank_section_exit(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vblank.c

335

struct intel_display *display = to_intel_display(_crtc->dev);

drivers/gpu/drm/i915/display/intel_vblank.c

341

bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||

drivers/gpu/drm/i915/display/intel_vblank.c

342

display->platform.g4x || DISPLAY_VER(display) == 2 ||

drivers/gpu/drm/i915/display/intel_vblank.c

345

if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {

drivers/gpu/drm/i915/display/intel_vblank.c

346

drm_dbg(display->drm,

drivers/gpu/drm/i915/display/intel_vblank.c

364

intel_vblank_section_enter(display);

drivers/gpu/drm/i915/display/intel_vblank.c

396

position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

drivers/gpu/drm/i915/display/intel_vblank.c

432

intel_vblank_section_exit(display);

drivers/gpu/drm/i915/display/intel_vblank.c

467

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vblank.c

472

intel_vblank_section_enter(display);

drivers/gpu/drm/i915/display/intel_vblank.c

476

intel_vblank_section_exit(display);

drivers/gpu/drm/i915/display/intel_vblank.c

482

static bool pipe_scanline_is_moving(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_vblank.c

485

i915_reg_t reg = PIPEDSL(display, pipe);

drivers/gpu/drm/i915/display/intel_vblank.c

488

line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

490

line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

497

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vblank.c

503

ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),

drivers/gpu/drm/i915/display/intel_vblank.c

507

drm_err(display->drm,

drivers/gpu/drm/i915/display/intel_vblank.c

542

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

553

drm_WARN_ON(display->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);

drivers/gpu/drm/i915/display/intel_vblank.c

569

spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);

drivers/gpu/drm/i915/display/intel_vblank.c

570

intel_vblank_section_enter(display);

drivers/gpu/drm/i915/display/intel_vblank.c

579

intel_vblank_section_exit(display);

drivers/gpu/drm/i915/display/intel_vblank.c

580

spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);

drivers/gpu/drm/i915/display/intel_vblank.c

686

struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

694

evade->need_vlv_dsi_wa = (display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_vblank.c

695

display->platform.cherryview) &&

drivers/gpu/drm/i915/display/intel_vblank.c

739

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vblank.c

76

struct intel_display *display = to_intel_display(crtc->dev);

drivers/gpu/drm/i915/display/intel_vblank.c

761

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_vdsc.c

1005

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_vdsc.c

1021

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1033

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/intel_vdsc.c

1037

dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vdsc.c

1038

dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vdsc.c

1053

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_vdsc.c

1077

int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_vdsc.c

1084

if (drm_WARN_ON(display->drm, !htotal))

drivers/gpu/drm/i915/display/intel_vdsc.c

1095

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1105

pixel_rate = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

1134

int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;

drivers/gpu/drm/i915/display/intel_vdsc.c

1136

intel_dsc_get_pixel_rate_with_dsc_bubbles(display, pixel_clock,

drivers/gpu/drm/i915/display/intel_vdsc.c

26

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

274

struct intel_display *display = to_intel_display(pipe_config);

drivers/gpu/drm/i915/display/intel_vdsc.c

287

drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");

drivers/gpu/drm/i915/display/intel_vdsc.c

29

if (!HAS_DSC(display))

drivers/gpu/drm/i915/display/intel_vdsc.c

298

if (DISPLAY_VER(display) >= 14 &&

drivers/gpu/drm/i915/display/intel_vdsc.c

319

drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",

drivers/gpu/drm/i915/display/intel_vdsc.c

32

if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)

drivers/gpu/drm/i915/display/intel_vdsc.c

342

if (DISPLAY_VER(display) >= 13 && !is_dsi_dsc_1_1(pipe_config)) {

drivers/gpu/drm/i915/display/intel_vdsc.c

383

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

385

drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_vdsc.c

394

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

40

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

408

if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&

drivers/gpu/drm/i915/display/intel_vdsc.c

42

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/intel_vdsc.c

455

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

462

drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);

drivers/gpu/drm/i915/display/intel_vdsc.c

467

intel_de_write(display, dsc_reg[i], pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

472

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

51

drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);

drivers/gpu/drm/i915/display/intel_vdsc.c

567

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_vdsc.c

585

intel_de_write(display, DSCA_RC_BUF_THRESH_0,

drivers/gpu/drm/i915/display/intel_vdsc.c

587

intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

589

intel_de_write(display, DSCA_RC_BUF_THRESH_1,

drivers/gpu/drm/i915/display/intel_vdsc.c

591

intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

594

intel_de_write(display, DSCC_RC_BUF_THRESH_0,

drivers/gpu/drm/i915/display/intel_vdsc.c

596

intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

598

intel_de_write(display, DSCC_RC_BUF_THRESH_1,

drivers/gpu/drm/i915/display/intel_vdsc.c

600

intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

604

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

606

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

608

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

610

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

613

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

616

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

619

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

622

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

639

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,

drivers/gpu/drm/i915/display/intel_vdsc.c

641

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

643

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,

drivers/gpu/drm/i915/display/intel_vdsc.c

645

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

647

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,

drivers/gpu/drm/i915/display/intel_vdsc.c

649

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

651

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,

drivers/gpu/drm/i915/display/intel_vdsc.c

653

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,

drivers/gpu/drm/i915/display/intel_vdsc.c

656

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,

drivers/gpu/drm/i915/display/intel_vdsc.c

658

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

661

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,

drivers/gpu/drm/i915/display/intel_vdsc.c

663

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

666

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,

drivers/gpu/drm/i915/display/intel_vdsc.c

668

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

671

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,

drivers/gpu/drm/i915/display/intel_vdsc.c

673

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

678

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

680

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

683

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

685

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

688

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

690

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

693

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),

drivers/gpu/drm/i915/display/intel_vdsc.c

695

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

699

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

702

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

705

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

708

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

711

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

714

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

717

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

720

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vdsc.c

773

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

781

drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);

drivers/gpu/drm/i915/display/intel_vdsc.c

782

drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);

drivers/gpu/drm/i915/display/intel_vdsc.c

787

intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);

drivers/gpu/drm/i915/display/intel_vdsc.c

790

intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);

drivers/gpu/drm/i915/display/intel_vdsc.c

807

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

817

intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vdsc.c

824

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

858

intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

859

intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

864

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

870

intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vdsc.c

871

intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vdsc.c

878

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

886

drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);

drivers/gpu/drm/i915/display/intel_vdsc.c

892

val = intel_de_read(display, dsc_reg[0]);

drivers/gpu/drm/i915/display/intel_vdsc.c

895

if (intel_de_read(display, dsc_reg[i]) != val) {

drivers/gpu/drm/i915/display/intel_vdsc.c

906

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

911

drm_WARN_ON(display->drm, !all_equal);

drivers/gpu/drm/i915/display/intel_vdsc.c

918

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vga.c

100

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_vga.c

101

unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;

drivers/gpu/drm/i915/display/intel_vga.c

105

drm_err(display->drm, "failed to read control word\n");

drivers/gpu/drm/i915/display/intel_vga.c

118

drm_err(display->drm, "failed to write control word\n");

drivers/gpu/drm/i915/display/intel_vga.c

127

struct intel_display *display = to_intel_display(pdev);

drivers/gpu/drm/i915/display/intel_vga.c

129

intel_gmch_vga_set_state(display, enable_decode);

drivers/gpu/drm/i915/display/intel_vga.c

138

int intel_vga_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vga.c

141

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_vga.c

159

void intel_vga_unregister(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vga.c

161

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_vga.c

21

static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vga.c

23

if (display->platform.valleyview || display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_vga.c

25

else if (DISPLAY_VER(display) >= 5)

drivers/gpu/drm/i915/display/intel_vga.c

31

static bool has_vga_pipe_sel(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vga.c

33

if (display->platform.i845g ||

drivers/gpu/drm/i915/display/intel_vga.c

34

display->platform.i865g)

drivers/gpu/drm/i915/display/intel_vga.c

37

if (display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_vga.c

38

display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_vga.c

41

return DISPLAY_VER(display) < 7;

drivers/gpu/drm/i915/display/intel_vga.c

45

void intel_vga_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vga.c

47

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_vga.c

48

i915_reg_t vga_reg = intel_vga_cntrl_reg(display);

drivers/gpu/drm/i915/display/intel_vga.c

53

tmp = intel_de_read(display, vga_reg);

drivers/gpu/drm/i915/display/intel_vga.c

57

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/intel_vga.c

59

else if (has_vga_pipe_sel(display))

drivers/gpu/drm/i915/display/intel_vga.c

64

drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n",

drivers/gpu/drm/i915/display/intel_vga.c

75

intel_de_write(display, vga_reg, VGA_DISP_DISABLE);

drivers/gpu/drm/i915/display/intel_vga.c

76

intel_de_posting_read(display, vga_reg);

drivers/gpu/drm/i915/display/intel_vga.c

79

void intel_vga_reset_io_mem(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vga.c

81

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

drivers/gpu/drm/i915/display/intel_vga.c

98

static int intel_gmch_vga_set_state(struct intel_display *display, bool enable_decode)

drivers/gpu/drm/i915/display/intel_vga.h

11

void intel_vga_reset_io_mem(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_vga.h

12

void intel_vga_disable(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_vga.h

13

int intel_vga_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_vga.h

14

void intel_vga_unregister(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_vrr.c

1001

intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1003

intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1005

intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1007

intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1012

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1017

trans_vrr_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1018

TRANS_VRR_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1020

if (HAS_CMRR(display))

drivers/gpu/drm/i915/display/intel_vrr.c

1025

intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

1026

TRANS_CMRR_N_HI(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1028

intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

1029

TRANS_CMRR_M_HI(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1032

if (DISPLAY_VER(display) >= 13) {

drivers/gpu/drm/i915/display/intel_vrr.c

1047

crtc_state->vrr.flipline = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1048

TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;

drivers/gpu/drm/i915/display/intel_vrr.c

1049

crtc_state->vrr.vmax = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1050

TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;

drivers/gpu/drm/i915/display/intel_vrr.c

1051

crtc_state->vrr.vmin = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1052

TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;

drivers/gpu/drm/i915/display/intel_vrr.c

1054

if (DISPLAY_VER(display) < 13) {

drivers/gpu/drm/i915/display/intel_vrr.c

106

return DISPLAY_VER(display) < 13 ? 1 : 0;

drivers/gpu/drm/i915/display/intel_vrr.c

1060

crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);

drivers/gpu/drm/i915/display/intel_vrr.c

1069

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

1073

if (HAS_AS_SDP(display)) {

drivers/gpu/drm/i915/display/intel_vrr.c

1075

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1076

TRANS_VRR_VSYNC(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1086

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

109

static int intel_vrr_vmin_flipline_offset(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vrr.c

1109

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

1117

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1119

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_vrr.c

1145

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1149

tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1159

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1163

tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1173

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1177

tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1184

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1188

tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

119

return DISPLAY_VER(display) < 13 ? 1 : 0;

drivers/gpu/drm/i915/display/intel_vrr.c

177

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

182

if (!HAS_CMRR(display) || true)

drivers/gpu/drm/i915/display/intel_vrr.c

263

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

269

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_vrr.c

300

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

303

intel_vrr_vmin_flipline_offset(display);

drivers/gpu/drm/i915/display/intel_vrr.c

314

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

320

intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

322

intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

324

intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

35

struct intel_display *display = to_intel_display(connector);

drivers/gpu/drm/i915/display/intel_vrr.c

357

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

366

return (HAS_VRR_DC_BALANCE(display) &&

drivers/gpu/drm/i915/display/intel_vrr.c

39

if (!HAS_VRR(display))

drivers/gpu/drm/i915/display/intel_vrr.c

409

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

417

if (!HAS_VRR(display))

drivers/gpu/drm/i915/display/intel_vrr.c

440

if (HAS_LRR(display))

drivers/gpu/drm/i915/display/intel_vrr.c

454

if (HAS_AS_SDP(display)) {

drivers/gpu/drm/i915/display/intel_vrr.c

469

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

472

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_vrr.c

482

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

488

intel_vrr_extra_vblank_delay(display);

drivers/gpu/drm/i915/display/intel_vrr.c

501

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

513

prefill_latency_us = max(display->sagv.block_time_us,

drivers/gpu/drm/i915/display/intel_vrr.c

514

skl_watermark_max_latency(display, 1));

drivers/gpu/drm/i915/display/intel_vrr.c

544

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

559

if (intel_vrr_always_use_vrr_tg(display)) {

drivers/gpu/drm/i915/display/intel_vrr.c

570

if (DISPLAY_VER(display) < 13)

drivers/gpu/drm/i915/display/intel_vrr.c

578

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

580

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/intel_vrr.c

583

else if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/intel_vrr.c

594

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

597

if (!HAS_VRR(display))

drivers/gpu/drm/i915/display/intel_vrr.c

609

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/intel_vrr.c

610

!(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));

drivers/gpu/drm/i915/display/intel_vrr.c

617

if (IS_DISPLAY_VER(display, 12, 13))

drivers/gpu/drm/i915/display/intel_vrr.c

618

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

622

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vrr.c

623

TRANS_VRR_CTL(display, cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

628

intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

630

intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

632

intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

634

intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

640

if (!intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

641

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

644

if (HAS_AS_SDP(display))

drivers/gpu/drm/i915/display/intel_vrr.c

645

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vrr.c

646

TRANS_VRR_VSYNC(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

657

if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/intel_vrr.c

658

intel_de_write(display,

drivers/gpu/drm/i915/display/intel_vrr.c

659

EMP_AS_SDP_TL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

667

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

673

intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

681

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

687

intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

688

intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

694

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

703

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/intel_vrr.c

704

TRANS_PUSH(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

714

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

736

intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

740

drm_err(display->drm, "[CRTC:%d:%s] VRR push send still pending\n",

drivers/gpu/drm/i915/display/intel_vrr.c

747

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

753

return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;

drivers/gpu/drm/i915/display/intel_vrr.c

756

bool intel_vrr_always_use_vrr_tg(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vrr.c

758

if (!HAS_VRR(display))

drivers/gpu/drm/i915/display/intel_vrr.c

761

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/intel_vrr.c

769

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

772

intel_vrr_vmin_flipline_offset(display);

drivers/gpu/drm/i915/display/intel_vrr.c

787

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

790

intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

792

intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

794

intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

801

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

805

u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

810

intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

812

intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

814

intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

816

intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

818

intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

820

intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

822

intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

824

intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

826

intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

828

intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

830

intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

832

intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

834

intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

836

intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

838

intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),

drivers/gpu/drm/i915/display/intel_vrr.c

840

intel_dmc_configure_dc_balance_event(display, pipe, true);

drivers/gpu/drm/i915/display/intel_vrr.c

841

intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

846

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);

drivers/gpu/drm/i915/display/intel_vrr.c

852

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

856

u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

862

intel_dmc_configure_dc_balance_event(display, pipe, false);

drivers/gpu/drm/i915/display/intel_vrr.c

863

intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

864

intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

865

intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

866

intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

867

intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

868

intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

869

intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

870

intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

871

intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

872

intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

873

intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

874

intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

875

intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

876

intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

877

intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

878

intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

881

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);

drivers/gpu/drm/i915/display/intel_vrr.c

887

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

891

intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);

drivers/gpu/drm/i915/display/intel_vrr.c

903

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);

drivers/gpu/drm/i915/display/intel_vrr.c

908

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

911

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

914

if (intel_de_wait_for_clear_ms(display,

drivers/gpu/drm/i915/display/intel_vrr.c

915

TRANS_VRR_STATUS(display, cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vrr.c

917

drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");

drivers/gpu/drm/i915/display/intel_vrr.c

919

intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);

drivers/gpu/drm/i915/display/intel_vrr.c

924

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

932

if (!intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

938

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

943

if (!intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

952

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

959

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

965

struct intel_display *display = to_intel_display(old_crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

970

if (intel_vrr_always_use_vrr_tg(display))

drivers/gpu/drm/i915/display/intel_vrr.c

98

static int intel_vrr_extra_vblank_delay(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_vrr.c

985

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

992

reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

995

reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

999

intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));

drivers/gpu/drm/i915/display/intel_vrr.h

47

bool intel_vrr_always_use_vrr_tg(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_vrr_regs.h

105

#define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

112

#define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

121

#define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

141

#define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

151

#define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

158

#define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

165

#define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

170

#define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

178

#define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

183

#define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

186

#define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

189

#define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

192

#define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

82

#define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

98

#define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A)

drivers/gpu/drm/i915/display/intel_wm.c

101

if (display->funcs.wm->compute_global_watermarks)

drivers/gpu/drm/i915/display/intel_wm.c

102

return display->funcs.wm->compute_global_watermarks(state);

drivers/gpu/drm/i915/display/intel_wm.c

107

void intel_wm_get_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_wm.c

109

if (display->funcs.wm->get_hw_state)

drivers/gpu/drm/i915/display/intel_wm.c

110

return display->funcs.wm->get_hw_state(display);

drivers/gpu/drm/i915/display/intel_wm.c

113

void intel_wm_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_wm.c

115

if (display->funcs.wm->sanitize)

drivers/gpu/drm/i915/display/intel_wm.c

116

return display->funcs.wm->sanitize(display);

drivers/gpu/drm/i915/display/intel_wm.c

142

void intel_print_wm_latency(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_wm.c

147

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/intel_wm.c

151

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_wm.c

161

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

166

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/intel_wm.c

172

void intel_wm_init(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_wm.c

174

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

175

skl_wm_init(display);

drivers/gpu/drm/i915/display/intel_wm.c

177

i9xx_wm_init(display);

drivers/gpu/drm/i915/display/intel_wm.c

182

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

185

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_wm.c

187

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/intel_wm.c

194

if (DISPLAY_VER(display) >= 9 ||

drivers/gpu/drm/i915/display/intel_wm.c

195

display->platform.valleyview ||

drivers/gpu/drm/i915/display/intel_wm.c

196

display->platform.cherryview ||

drivers/gpu/drm/i915/display/intel_wm.c

197

display->platform.g4x)

drivers/gpu/drm/i915/display/intel_wm.c

206

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_wm.c

211

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

214

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

215

latencies = display->wm.skl_latency;

drivers/gpu/drm/i915/display/intel_wm.c

217

latencies = display->wm.pri_latency;

drivers/gpu/drm/i915/display/intel_wm.c

226

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

229

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

230

latencies = display->wm.skl_latency;

drivers/gpu/drm/i915/display/intel_wm.c

232

latencies = display->wm.spr_latency;

drivers/gpu/drm/i915/display/intel_wm.c

241

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

244

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

245

latencies = display->wm.skl_latency;

drivers/gpu/drm/i915/display/intel_wm.c

247

latencies = display->wm.cur_latency;

drivers/gpu/drm/i915/display/intel_wm.c

256

struct intel_display *display = inode->i_private;

drivers/gpu/drm/i915/display/intel_wm.c

258

if (DISPLAY_VER(display) < 5 && !display->platform.g4x)

drivers/gpu/drm/i915/display/intel_wm.c

261

return single_open(file, pri_wm_latency_show, display);

drivers/gpu/drm/i915/display/intel_wm.c

266

struct intel_display *display = inode->i_private;

drivers/gpu/drm/i915/display/intel_wm.c

268

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_wm.c

271

return single_open(file, spr_wm_latency_show, display);

drivers/gpu/drm/i915/display/intel_wm.c

276

struct intel_display *display = inode->i_private;

drivers/gpu/drm/i915/display/intel_wm.c

278

if (HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_wm.c

281

return single_open(file, cur_wm_latency_show, display);

drivers/gpu/drm/i915/display/intel_wm.c

288

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

305

if (ret != display->wm.num_levels)

drivers/gpu/drm/i915/display/intel_wm.c

308

drm_modeset_lock_all(display->drm);

drivers/gpu/drm/i915/display/intel_wm.c

310

for (level = 0; level < display->wm.num_levels; level++)

drivers/gpu/drm/i915/display/intel_wm.c

313

drm_modeset_unlock_all(display->drm);

drivers/gpu/drm/i915/display/intel_wm.c

322

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

325

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

326

latencies = display->wm.skl_latency;

drivers/gpu/drm/i915/display/intel_wm.c

328

latencies = display->wm.pri_latency;

drivers/gpu/drm/i915/display/intel_wm.c

337

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

340

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

341

latencies = display->wm.skl_latency;

drivers/gpu/drm/i915/display/intel_wm.c

343

latencies = display->wm.spr_latency;

drivers/gpu/drm/i915/display/intel_wm.c

352

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/intel_wm.c

355

if (DISPLAY_VER(display) >= 9)

drivers/gpu/drm/i915/display/intel_wm.c

356

latencies = display->wm.skl_latency;

drivers/gpu/drm/i915/display/intel_wm.c

358

latencies = display->wm.cur_latency;

drivers/gpu/drm/i915/display/intel_wm.c

390

void intel_wm_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_wm.c

392

struct dentry *debugfs_root = display->drm->debugfs_root;

drivers/gpu/drm/i915/display/intel_wm.c

395

display, &i915_pri_wm_latency_fops);

drivers/gpu/drm/i915/display/intel_wm.c

398

display, &i915_spr_wm_latency_fops);

drivers/gpu/drm/i915/display/intel_wm.c

401

display, &i915_cur_wm_latency_fops);

drivers/gpu/drm/i915/display/intel_wm.c

403

skl_watermark_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_wm.c

49

void intel_update_watermarks(struct intel_display *display)

drivers/gpu/drm/i915/display/intel_wm.c

51

if (display->funcs.wm->update_wm)

drivers/gpu/drm/i915/display/intel_wm.c

52

display->funcs.wm->update_wm(display);

drivers/gpu/drm/i915/display/intel_wm.c

58

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_wm.c

60

if (!display->funcs.wm->compute_watermarks)

drivers/gpu/drm/i915/display/intel_wm.c

63

return display->funcs.wm->compute_watermarks(state, crtc);

drivers/gpu/drm/i915/display/intel_wm.c

69

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_wm.c

71

if (display->funcs.wm->initial_watermarks) {

drivers/gpu/drm/i915/display/intel_wm.c

72

display->funcs.wm->initial_watermarks(state, crtc);

drivers/gpu/drm/i915/display/intel_wm.c

82

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_wm.c

84

if (display->funcs.wm->atomic_update_watermarks)

drivers/gpu/drm/i915/display/intel_wm.c

85

display->funcs.wm->atomic_update_watermarks(state, crtc);

drivers/gpu/drm/i915/display/intel_wm.c

91

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_wm.c

93

if (display->funcs.wm->optimize_watermarks)

drivers/gpu/drm/i915/display/intel_wm.c

94

display->funcs.wm->optimize_watermarks(state, crtc);

drivers/gpu/drm/i915/display/intel_wm.c

99

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/intel_wm.h

17

void intel_update_watermarks(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_wm.h

27

void intel_wm_get_hw_state(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_wm.h

28

void intel_wm_sanitize(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_wm.h

31

void intel_print_wm_latency(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_wm.h

33

void intel_wm_init(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_wm.h

34

void intel_wm_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_scaler.c

100

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/skl_scaler.c

1015

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1020

intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);

drivers/gpu/drm/i915/display/skl_scaler.c

1025

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

103

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_scaler.c

1033

intel_de_write_fw(display,

drivers/gpu/drm/i915/display/skl_scaler.c

1036

intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);

drivers/gpu/drm/i915/display/skl_scaler.c

106

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/skl_scaler.c

1084

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1092

return min(max_scale, DIV_ROUND_UP_ULL((u64)display->cdclk.max_dotclk_freq << 16,

drivers/gpu/drm/i915/display/skl_scaler.c

124

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

126

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_scaler.c

129

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/skl_scaler.c

139

skl_scaler_mode_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_scaler.c

147

skl_scaler_max_src_size(display, &max_w, &max_h);

drivers/gpu/drm/i915/display/skl_scaler.c

162

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

187

if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&

drivers/gpu/drm/i915/display/skl_scaler.c

189

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

210

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

222

skl_scaler_max_src_size(display, &max_src_w, &max_src_h);

drivers/gpu/drm/i915/display/skl_scaler.c

232

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

250

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

260

drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: "

drivers/gpu/drm/i915/display/skl_scaler.c

303

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

310

if (!icl_is_hdr_plane(display, plane->id) &&

drivers/gpu/drm/i915/display/skl_scaler.c

355

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

365

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/skl_scaler.c

378

} else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) {

drivers/gpu/drm/i915/display/skl_scaler.c

393

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

402

if (drm_WARN(display->drm, *scaler_id < 0,

drivers/gpu/drm/i915/display/skl_scaler.c

412

if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/skl_scaler.c

414

} else if (icl_is_hdr_plane(display, plane->id)) {

drivers/gpu/drm/i915/display/skl_scaler.c

430

} else if (DISPLAY_VER(display) >= 10) {

drivers/gpu/drm/i915/display/skl_scaler.c

466

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

503

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

516

drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n",

drivers/gpu/drm/i915/display/skl_scaler.c

546

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_scaler.c

554

if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))

drivers/gpu/drm/i915/display/skl_scaler.c

564

if (!plane_state && DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_scaler.c

597

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

621

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

642

to_intel_plane(drm_plane_from_index(display->drm, i));

drivers/gpu/drm/i915/display/skl_scaler.c

700

static void glk_program_nearest_filter_coefs(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_scaler.c

706

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_scaler.c

720

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_scaler.c

724

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_scaler.c

740

static void skl_scaler_setup_filter(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_scaler.c

748

glk_program_nearest_filter_coefs(display, dsb, pipe, id, set);

drivers/gpu/drm/i915/display/skl_scaler.c

765

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

794

intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);

drivers/gpu/drm/i915/display/skl_scaler.c

795

intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),

drivers/gpu/drm/i915/display/skl_scaler.c

797

intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),

drivers/gpu/drm/i915/display/skl_scaler.c

803

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

822

if (drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/skl_scaler.c

826

if (intel_display_wa(display, 14011503117))

drivers/gpu/drm/i915/display/skl_scaler.c

846

skl_scaler_setup_filter(display, NULL, pipe, id, 0,

drivers/gpu/drm/i915/display/skl_scaler.c

849

intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);

drivers/gpu/drm/i915/display/skl_scaler.c

851

intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id),

drivers/gpu/drm/i915/display/skl_scaler.c

853

intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id),

drivers/gpu/drm/i915/display/skl_scaler.c

855

intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),

drivers/gpu/drm/i915/display/skl_scaler.c

857

intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),

drivers/gpu/drm/i915/display/skl_scaler.c

867

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_scaler.c

891

!icl_is_hdr_plane(display, plane->id)) {

drivers/gpu/drm/i915/display/skl_scaler.c

913

skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0,

drivers/gpu/drm/i915/display/skl_scaler.c

916

intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id),

drivers/gpu/drm/i915/display/skl_scaler.c

918

intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id),

drivers/gpu/drm/i915/display/skl_scaler.c

920

intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id),

drivers/gpu/drm/i915/display/skl_scaler.c

922

intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id),

drivers/gpu/drm/i915/display/skl_scaler.c

924

intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id),

drivers/gpu/drm/i915/display/skl_scaler.c

931

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

935

intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0);

drivers/gpu/drm/i915/display/skl_scaler.c

936

intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0);

drivers/gpu/drm/i915/display/skl_scaler.c

937

intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0);

drivers/gpu/drm/i915/display/skl_scaler.c

969

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

97

static void skl_scaler_max_src_size(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_scaler.c

979

ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));

drivers/gpu/drm/i915/display/skl_scaler.c

986

if (HAS_CASF(display) && id == 1)

drivers/gpu/drm/i915/display/skl_scaler.c

992

pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));

drivers/gpu/drm/i915/display/skl_scaler.c

993

size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));

drivers/gpu/drm/i915/display/skl_scaler.h

42

skl_scaler_mode_valid(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1170

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1173

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1187

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1195

if (DISPLAY_VER(display) < 10) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1210

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1220

if (DISPLAY_VER(display) == 13)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1228

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1231

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1245

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1253

if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1295

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1300

drm_WARN_ON(display->drm, offset & 0x1fffff);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1303

drm_WARN_ON(display->drm, offset & 0xfff);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1332

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1343

if (DISPLAY_VER(display) < 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1381

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1385

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1386

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1388

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1389

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1391

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1392

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1394

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1395

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1396

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1398

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1399

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1400

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1409

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1424

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1426

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1428

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1440

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1455

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1459

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1461

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1463

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1466

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1469

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1472

intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1476

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1477

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1495

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1497

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1507

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1524

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1539

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1544

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1553

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1578

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1580

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1582

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1585

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1587

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1589

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1592

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1596

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1598

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1603

if (HAS_AUX_DIST(display))

drivers/gpu/drm/i915/display/skl_universal_plane.c

1604

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1607

if (icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

1608

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1611

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1614

if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

1634

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1641

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1653

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1681

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1690

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1692

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1700

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1702

error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1703

error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1704

error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1714

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1723

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1729

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1731

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1750

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1760

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1768

DISPLAY_VER(display) < 35) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1769

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1780

DISPLAY_VER(display) >= 20) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1781

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1789

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1801

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1814

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1827

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1834

if ((display->platform.alderlake_s || display->platform.tigerlake) &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

1837

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1849

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1864

if (DISPLAY_VER(display) == 10 &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

1866

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1880

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1891

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1900

static int skl_plane_max_scale(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1909

if (DISPLAY_VER(display) >= 10 ||

drivers/gpu/drm/i915/display/skl_universal_plane.c

2006

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2016

if (drm_WARN_ON(display->drm, alignment && !is_power_of_2(alignment)))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2040

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2057

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2075

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2103

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2110

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2111

drm_WARN_ON(display->drm, x > 65535 || y > 65535);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2113

drm_WARN_ON(display->drm, x > 8191 || y > 8191);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2131

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2150

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2185

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2192

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2193

drm_WARN_ON(display->drm, x > 65535 || y > 65535);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2195

drm_WARN_ON(display->drm, x > 8191 || y > 8191);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2281

struct intel_display *display;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2286

display = to_intel_display(fb->dev);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2295

return DISPLAY_VER(display) >= 11;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2303

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2307

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2356

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2370

max_scale = skl_plane_max_scale(display, fb);

drivers/gpu/drm/i915/display/skl_universal_plane.c

240

static u8 icl_nv12_y_plane_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2411

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2415

icl_is_hdr_plane(display, plane->id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

242

if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2429

struct intel_display *display = to_intel_display(uv_plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2433

drm_WARN_ON(display->drm, icl_is_nv12_y_plane(display, uv_plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

2434

drm_WARN_ON(display->drm, !icl_is_nv12_y_plane(display, y_plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

2438

if (icl_is_hdr_plane(display, uv_plane->id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2458

static struct intel_fbc *skl_plane_fbc(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2463

if (skl_plane_has_fbc(display, fbc_id, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2464

return display->fbc.instances[fbc_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

2469

static bool skl_plane_has_planar(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2473

if (display->platform.skylake || display->platform.broxton)

drivers/gpu/drm/i915/display/skl_universal_plane.c

248

bool icl_is_nv12_y_plane(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2482

static const u32 *skl_get_plane_formats(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2486

if (skl_plane_has_planar(display, pipe, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2495

static bool glk_plane_has_planar(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2501

static const u32 *glk_get_plane_formats(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2505

if (glk_plane_has_planar(display, pipe, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

251

return DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

2514

static const u32 *icl_get_plane_formats(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2518

if (icl_is_hdr_plane(display, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

252

icl_nv12_y_plane_mask(display) & BIT(plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2521

} else if (icl_is_nv12_y_plane(display, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

260

bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

262

return DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

2723

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2726

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2727

bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

2728

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2734

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2737

spin_lock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2738

bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

2739

spin_unlock_irq(&display->irq.lock);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2742

static bool skl_plane_has_rc_ccs(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2751

static u8 skl_plane_caps(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2758

if (skl_plane_has_rc_ccs(display, pipe, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2764

static bool glk_plane_has_rc_ccs(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2770

static u8 glk_plane_caps(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2777

if (glk_plane_has_rc_ccs(display, pipe))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2783

static u8 icl_plane_caps(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2792

static bool tgl_plane_has_mc_ccs(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2796

if (display->platform.dg1 || display->platform.rocketlake ||

drivers/gpu/drm/i915/display/skl_universal_plane.c

2797

(display->platform.tigerlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2803

static u8 tgl_plane_caps(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2810

if (HAS_4TILE(display))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2815

if (tgl_plane_has_mc_ccs(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2818

if (DISPLAY_VER(display) >= 14 && display->platform.dgfx)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2827

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2831

plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

2841

intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

2844

intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2846

intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

2851

skl_universal_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2873

intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2875

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2880

} else if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2881

if (DISPLAY_VER(display) >= 14 || display->platform.alderlake_p)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2885

if (icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2891

} else if (DISPLAY_VER(display) >= 10) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2904

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2909

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2914

if (intel_scanout_needs_vtd_wa(display))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2915

plane->vtd_guard = DISPLAY_VER(display) >= 10 ? 168 : 136;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2917

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2930

if (HAS_ASYNC_FLIPS(display) && plane_id == PLANE_1) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2931

plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(display, 9, 10);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2936

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2938

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2944

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2945

formats = icl_get_plane_formats(display, pipe,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2947

else if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2948

formats = glk_get_plane_formats(display, pipe,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2951

formats = skl_get_plane_formats(display, pipe,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2954

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2956

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2966

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2967

caps = tgl_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2968

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2969

caps = icl_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2970

else if (DISPLAY_VER(display) == 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2971

caps = glk_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2973

caps = skl_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2975

modifiers = intel_fb_plane_get_modifiers(display, caps);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2977

ret = drm_universal_plane_init(display->drm, &plane->base,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2989

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2996

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3005

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3015

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3026

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3029

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3048

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3063

drm_WARN_ON(display->drm, pipe != crtc->pipe);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3066

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

3074

drm_dbg_kms(display->drm, "failed to alloc fb\n");

drivers/gpu/drm/i915/display/skl_universal_plane.c

3080

fb->dev = display->drm;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3082

val = intel_de_read(display, PLANE_CTL(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3084

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3089

if (DISPLAY_VER(display) >= 10) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

3092

color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3111

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3113

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3118

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3126

if (HAS_4TILE(display)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

3150

fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3152

if (!display->params.enable_dpt &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

3153

intel_fb_modifier_uses_dpt(display, fb->modifier)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

3154

drm_dbg_kms(display->drm, "DPT disabled, skipping initial FB\n");

drivers/gpu/drm/i915/display/skl_universal_plane.c

3177

if (DISPLAY_VER(display) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3184

base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3187

offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3188

drm_WARN_ON(display->drm, offset != 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3190

val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3194

val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3203

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

3220

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3237

intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

448

static bool skl_plane_has_fbc(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.c

451

if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

454

if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/skl_universal_plane.c

455

return icl_is_hdr_plane(display, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

585

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

598

if (display->platform.alderlake_p &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

680

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

724

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),

drivers/gpu/drm/i915/display/skl_universal_plane.c

726

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),

drivers/gpu/drm/i915/display/skl_universal_plane.c

728

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),

drivers/gpu/drm/i915/display/skl_universal_plane.c

730

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),

drivers/gpu/drm/i915/display/skl_universal_plane.c

732

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),

drivers/gpu/drm/i915/display/skl_universal_plane.c

734

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),

drivers/gpu/drm/i915/display/skl_universal_plane.c

737

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),

drivers/gpu/drm/i915/display/skl_universal_plane.c

739

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

drivers/gpu/drm/i915/display/skl_universal_plane.c

741

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),

drivers/gpu/drm/i915/display/skl_universal_plane.c

743

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_universal_plane.c

745

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_universal_plane.c

747

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_universal_plane.c

825

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

838

for (level = 0; level < display->wm.num_levels; level++)

drivers/gpu/drm/i915/display/skl_universal_plane.c

839

intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),

drivers/gpu/drm/i915/display/skl_universal_plane.c

842

intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

845

if (HAS_HW_SAGV_WM(display)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

848

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

850

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

854

intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

857

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/skl_universal_plane.c

858

intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

861

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/skl_universal_plane.c

862

intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

871

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

877

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

878

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

885

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

891

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

896

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

898

return HAS_PIXEL_NORMALIZER(display) && icl_is_hdr_plane(display, plane->id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

915

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

919

if (icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

920

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

927

intel_de_write_dsb(display, dsb,

drivers/gpu/drm/i915/display/skl_universal_plane.c

930

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

931

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

938

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

945

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/skl_universal_plane.c

949

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

drivers/gpu/drm/i915/display/skl_universal_plane.c

953

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/skl_universal_plane.h

22

skl_universal_plane_create(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.h

38

bool icl_is_nv12_y_plane(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_universal_plane.h

41

bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id);

drivers/gpu/drm/i915/display/skl_watermark.c

100

intel_has_sagv(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

102

return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/skl_watermark.c

106

intel_sagv_block_time(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

108

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/skl_watermark.c

111

val = intel_de_read(display, MTL_LATENCY_SAGV);

drivers/gpu/drm/i915/display/skl_watermark.c

114

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_watermark.c

118

ret = intel_pcode_read(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

122

drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n");

drivers/gpu/drm/i915/display/skl_watermark.c

1248

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

1251

if (display->platform.dg2)

drivers/gpu/drm/i915/display/skl_watermark.c

1253

else if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/skl_watermark.c

1255

else if (DISPLAY_VER(display) == 12)

drivers/gpu/drm/i915/display/skl_watermark.c

1257

else if (DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/skl_watermark.c

127

} else if (DISPLAY_VER(display) == 11) {

drivers/gpu/drm/i915/display/skl_watermark.c

1270

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_watermark.c

1273

return IS_DISPLAY_VER(display, 13, 20) &&

drivers/gpu/drm/i915/display/skl_watermark.c

129

} else if (HAS_SAGV(display)) {

drivers/gpu/drm/i915/display/skl_watermark.c

1297

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1308

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/skl_watermark.c

136

static void intel_sagv_init(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

1370

static bool skl_need_wm_copy_wa(struct intel_display *display, int level,

drivers/gpu/drm/i915/display/skl_watermark.c

138

if (!HAS_SAGV(display))

drivers/gpu/drm/i915/display/skl_watermark.c

139

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/skl_watermark.c

1429

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

145

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/skl_watermark.c

146

skl_sagv_disable(display);

drivers/gpu/drm/i915/display/skl_watermark.c

1465

for (level = display->wm.num_levels - 1; level >= 0; level--) {

drivers/gpu/drm/i915/display/skl_watermark.c

1476

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

148

drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN);

drivers/gpu/drm/i915/display/skl_watermark.c

1495

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

1497

drm_dbg_kms(display->drm, "minimum required %d/%d\n",

drivers/gpu/drm/i915/display/skl_watermark.c

150

display->sagv.block_time_us = intel_sagv_block_time(display);

drivers/gpu/drm/i915/display/skl_watermark.c

152

drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n",

drivers/gpu/drm/i915/display/skl_watermark.c

1525

if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/skl_watermark.c

153

str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us);

drivers/gpu/drm/i915/display/skl_watermark.c

1536

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/skl_watermark.c

1541

drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0);

drivers/gpu/drm/i915/display/skl_watermark.c

1549

for (level++; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

1558

if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/skl_watermark.c

156

if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX,

drivers/gpu/drm/i915/display/skl_watermark.c

1566

if (skl_need_wm_copy_wa(display, level, wm)) {

drivers/gpu/drm/i915/display/skl_watermark.c

158

display->sagv.block_time_us))

drivers/gpu/drm/i915/display/skl_watermark.c

1588

if (DISPLAY_VER(display) < 11 &&

drivers/gpu/drm/i915/display/skl_watermark.c

159

display->sagv.block_time_us = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

1598

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/skl_watermark.c

161

if (!intel_has_sagv(display))

drivers/gpu/drm/i915/display/skl_watermark.c

1614

skl_wm_method1(struct intel_display *display, u32 pixel_rate,

drivers/gpu/drm/i915/display/skl_watermark.c

162

display->sagv.block_time_us = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

1626

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_watermark.c

1663

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1669

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

1687

if (DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/skl_watermark.c

1712

if (skl_needs_memory_bw_wa(display))

drivers/gpu/drm/i915/display/skl_watermark.c

1721

if (DISPLAY_VER(display) >= 30)

drivers/gpu/drm/i915/display/skl_watermark.c

1723

else if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_watermark.c

1732

if (!wp->x_tiled || DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_watermark.c

176

static void skl_sagv_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

1769

static bool skl_wm_has_lines(struct intel_display *display, int level)

drivers/gpu/drm/i915/display/skl_watermark.c

1771

if (DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_watermark.c

1778

static int skl_wm_max_lines(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

1780

if (DISPLAY_VER(display) >= 13)

drivers/gpu/drm/i915/display/skl_watermark.c

1788

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_watermark.c

1790

return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR;

drivers/gpu/drm/i915/display/skl_watermark.c

180

if (!intel_has_sagv(display))

drivers/gpu/drm/i915/display/skl_watermark.c

1801

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1813

method1 = skl_wm_method1(display, wp->plane_pixel_rate,

drivers/gpu/drm/i915/display/skl_watermark.c

1822

} else if (DISPLAY_VER(display) >= 35) {

drivers/gpu/drm/i915/display/skl_watermark.c

183

if (display->sagv.status == I915_SAGV_ENABLED)

drivers/gpu/drm/i915/display/skl_watermark.c

1830

if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/skl_watermark.c

1840

if (DISPLAY_VER(display) < 30)

drivers/gpu/drm/i915/display/skl_watermark.c

1859

if (skl_wm_has_lines(display, level))

drivers/gpu/drm/i915/display/skl_watermark.c

186

drm_dbg_kms(display->drm, "Enabling SAGV\n");

drivers/gpu/drm/i915/display/skl_watermark.c

1865

if (DISPLAY_VER(display) == 9) {

drivers/gpu/drm/i915/display/skl_watermark.c

187

ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL,

drivers/gpu/drm/i915/display/skl_watermark.c

1893

if (DISPLAY_VER(display) >= 11) {

drivers/gpu/drm/i915/display/skl_watermark.c

1910

if (!skl_wm_has_lines(display, level))

drivers/gpu/drm/i915/display/skl_watermark.c

1913

if (lines > skl_wm_max_lines(display)) {

drivers/gpu/drm/i915/display/skl_watermark.c

1932

if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us)

drivers/gpu/drm/i915/display/skl_watermark.c

1933

result->can_sagv = latency >= display->sagv.block_time_us;

drivers/gpu/drm/i915/display/skl_watermark.c

1942

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1946

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

1948

unsigned int latency = skl_wm_latency(display, level, wm_params);

drivers/gpu/drm/i915/display/skl_watermark.c

196

if (display->platform.skylake && ret == -ENXIO) {

drivers/gpu/drm/i915/display/skl_watermark.c

1962

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1967

if (display->sagv.block_time_us)

drivers/gpu/drm/i915/display/skl_watermark.c

1968

latency = display->sagv.block_time_us +

drivers/gpu/drm/i915/display/skl_watermark.c

1969

skl_wm_latency(display, 0, wm_params);

drivers/gpu/drm/i915/display/skl_watermark.c

197

drm_dbg(display->drm, "No SAGV found on system, ignoring\n");

drivers/gpu/drm/i915/display/skl_watermark.c

1976

static void skl_compute_transition_wm(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

198

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/skl_watermark.c

1985

if (!skl_watermark_ipc_enabled(display))

drivers/gpu/drm/i915/display/skl_watermark.c

1992

if (DISPLAY_VER(display) == 9)

drivers/gpu/drm/i915/display/skl_watermark.c

1995

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_watermark.c

2001

if (DISPLAY_VER(display) == 10)

drivers/gpu/drm/i915/display/skl_watermark.c

201

drm_err(display->drm, "Failed to enable SAGV\n");

drivers/gpu/drm/i915/display/skl_watermark.c

2043

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

205

display->sagv.status = I915_SAGV_ENABLED;

drivers/gpu/drm/i915/display/skl_watermark.c

2055

skl_compute_transition_wm(display, &wm->trans_wm,

drivers/gpu/drm/i915/display/skl_watermark.c

2058

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_watermark.c

2061

skl_compute_transition_wm(display, &wm->sagv.trans_wm,

drivers/gpu/drm/i915/display/skl_watermark.c

208

static void skl_sagv_disable(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

212

if (!intel_has_sagv(display))

drivers/gpu/drm/i915/display/skl_watermark.c

2121

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2136

drm_WARN_ON(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

2138

drm_WARN_ON(display->drm, !fb->format->is_yuv ||

drivers/gpu/drm/i915/display/skl_watermark.c

215

if (display->sagv.status == I915_SAGV_DISABLED)

drivers/gpu/drm/i915/display/skl_watermark.c

2162

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2174

drm_WARN_ON(display->drm, !HAS_VRR(display));

drivers/gpu/drm/i915/display/skl_watermark.c

2178

if (HAS_4TILE(display))

drivers/gpu/drm/i915/display/skl_watermark.c

218

drm_dbg_kms(display->drm, "Disabling SAGV\n");

drivers/gpu/drm/i915/display/skl_watermark.c

2183

info = drm_get_format_info(display->drm, format, modifier);

drivers/gpu/drm/i915/display/skl_watermark.c

2198

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/skl_watermark.c

220

ret = intel_pcode_request(display->drm, GEN9_PCODE_SAGV_CONTROL,

drivers/gpu/drm/i915/display/skl_watermark.c

2200

latency = skl_wm_latency(display, level, &wp);

drivers/gpu/drm/i915/display/skl_watermark.c

2206

wm.lines = skl_wm_max_lines(display);

drivers/gpu/drm/i915/display/skl_watermark.c

2240

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2244

for (level = display->wm.num_levels - 1; level >= 0; level--) {

drivers/gpu/drm/i915/display/skl_watermark.c

2248

latency = skl_wm_latency(display, level, NULL);

drivers/gpu/drm/i915/display/skl_watermark.c

2260

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Not enough time in vblank for prefill\n",

drivers/gpu/drm/i915/display/skl_watermark.c

2268

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

227

if (display->platform.skylake && ret == -ENXIO) {

drivers/gpu/drm/i915/display/skl_watermark.c

228

drm_dbg(display->drm, "No SAGV found on system, ignoring\n");

drivers/gpu/drm/i915/display/skl_watermark.c

2286

crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;

drivers/gpu/drm/i915/display/skl_watermark.c

229

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

drivers/gpu/drm/i915/display/skl_watermark.c

2295

for (level++; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

2311

if (DISPLAY_VER(display) >= 12 &&

drivers/gpu/drm/i915/display/skl_watermark.c

2312

display->sagv.block_time_us &&

drivers/gpu/drm/i915/display/skl_watermark.c

2314

display->sagv.block_time_us)) {

drivers/gpu/drm/i915/display/skl_watermark.c

232

drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret);

drivers/gpu/drm/i915/display/skl_watermark.c

2332

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

2348

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_watermark.c

236

display->sagv.status = I915_SAGV_DISABLED;

drivers/gpu/drm/i915/display/skl_watermark.c

2371

static bool skl_plane_wm_equals(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

2377

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

241

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2429

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2436

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

2447

drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n",

drivers/gpu/drm/i915/display/skl_watermark.c

2466

struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);

drivers/gpu/drm/i915/display/skl_watermark.c

2476

for_each_pipe(display, pipe)

drivers/gpu/drm/i915/display/skl_watermark.c

248

if (!intel_bw_can_enable_sagv(display, new_bw_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2485

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

249

skl_sagv_disable(display);

drivers/gpu/drm/i915/display/skl_watermark.c

2513

if (HAS_MBUS_JOINING(display)) {

drivers/gpu/drm/i915/display/skl_watermark.c

2524

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

254

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2547

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

2551

DISPLAY_INFO(display)->dbuf.slice_mask,

drivers/gpu/drm/i915/display/skl_watermark.c

2569

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

2594

skl_print_plane_changes(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

2599

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

261

if (intel_bw_can_enable_sagv(display, new_bw_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2618

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

262

skl_sagv_enable(display);

drivers/gpu/drm/i915/display/skl_watermark.c

2645

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

2664

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

267

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2687

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2704

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

2713

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

2720

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

2727

if (skl_plane_wm_equals(display, old_wm, new_wm))

drivers/gpu/drm/i915/display/skl_watermark.c

2730

skl_print_plane_changes(display, plane, old_wm, new_wm);

drivers/gpu/drm/i915/display/skl_watermark.c

2739

struct intel_display *display = to_intel_display(plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2742

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

2753

if (HAS_HW_SAGV_WM(display)) {

drivers/gpu/drm/i915/display/skl_watermark.c

276

if (!intel_has_sagv(display))

drivers/gpu/drm/i915/display/skl_watermark.c

279

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_watermark.c

2791

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2798

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

2817

drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n",

drivers/gpu/drm/i915/display/skl_watermark.c

2836

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2846

display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;

drivers/gpu/drm/i915/display/skl_watermark.c

2847

display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);

drivers/gpu/drm/i915/display/skl_watermark.c

2851

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

2852

if (display->pkgc.disable[crtc->pipe])

drivers/gpu/drm/i915/display/skl_watermark.c

2855

max_linetime = max(display->pkgc.linetime[crtc->pipe], max_linetime);

drivers/gpu/drm/i915/display/skl_watermark.c

2864

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2867

if (DISPLAY_VER(display) < 20)

drivers/gpu/drm/i915/display/skl_watermark.c

287

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2870

mutex_lock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/skl_watermark.c

2872

latency = skl_watermark_max_latency(display, 1);

drivers/gpu/drm/i915/display/skl_watermark.c

2875

if (display->params.enable_flipq)

drivers/gpu/drm/i915/display/skl_watermark.c

2876

added_wake_time = intel_flipq_exec_time_us(display);

drivers/gpu/drm/i915/display/skl_watermark.c

2882

if (latency && IS_DISPLAY_VER(display, 20, 30)) {

drivers/gpu/drm/i915/display/skl_watermark.c

2902

intel_de_write(display, LNL_PKG_C_LATENCY,

drivers/gpu/drm/i915/display/skl_watermark.c

2906

mutex_unlock(&display->wm.wm_mutex);

drivers/gpu/drm/i915/display/skl_watermark.c

2912

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

2952

pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) &&

drivers/gpu/drm/i915/display/skl_watermark.c

2953

DISPLAY_VER(display) >= 12 &&

drivers/gpu/drm/i915/display/skl_watermark.c

296

if (!intel_has_sagv(display))

drivers/gpu/drm/i915/display/skl_watermark.c

2966

static void skl_wm_level_from_reg_val(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

2973

level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ?

drivers/gpu/drm/i915/display/skl_watermark.c

2980

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

2989

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

299

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_watermark.c

2991

val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));

drivers/gpu/drm/i915/display/skl_watermark.c

2993

val = intel_de_read(display, CUR_WM(pipe, level));

drivers/gpu/drm/i915/display/skl_watermark.c

2995

skl_wm_level_from_reg_val(display, val, &wm->wm[level]);

drivers/gpu/drm/i915/display/skl_watermark.c

2999

val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3001

val = intel_de_read(display, CUR_WM_TRANS(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

3003

skl_wm_level_from_reg_val(display, val, &wm->trans_wm);

drivers/gpu/drm/i915/display/skl_watermark.c

3005

if (HAS_HW_SAGV_WM(display)) {

drivers/gpu/drm/i915/display/skl_watermark.c

3007

val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3009

val = intel_de_read(display, CUR_WM_SAGV(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

3011

skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);

drivers/gpu/drm/i915/display/skl_watermark.c

3014

val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3016

val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

3018

skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);

drivers/gpu/drm/i915/display/skl_watermark.c

3019

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_watermark.c

3026

static void skl_wm_get_hw_state(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3029

to_intel_dbuf_state(display->dbuf.obj.state);

drivers/gpu/drm/i915/display/skl_watermark.c

3032

if (HAS_MBUS_JOINING(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3033

dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

drivers/gpu/drm/i915/display/skl_watermark.c

3035

dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw);

drivers/gpu/drm/i915/display/skl_watermark.c

3038

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

3069

skl_ddb_get_hw_plane_state(display, crtc->pipe,

drivers/gpu/drm/i915/display/skl_watermark.c

307

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3085

mbus_offset = mbus_ddb_offset(display, slices);

drivers/gpu/drm/i915/display/skl_watermark.c

3091

skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

3093

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

3101

dbuf_state->enabled_slices = display->dbuf.enabled_slices;

drivers/gpu/drm/i915/display/skl_watermark.c

3104

bool skl_watermark_ipc_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3106

return display->wm.ipc_enabled;

drivers/gpu/drm/i915/display/skl_watermark.c

3109

void skl_watermark_ipc_update(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3111

if (!HAS_IPC(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3114

intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE,

drivers/gpu/drm/i915/display/skl_watermark.c

3115

skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0);

drivers/gpu/drm/i915/display/skl_watermark.c

3118

static bool skl_watermark_ipc_can_enable(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

312

if (!intel_has_sagv(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3121

if (display->platform.skylake)

drivers/gpu/drm/i915/display/skl_watermark.c

3125

if (display->platform.kabylake ||

drivers/gpu/drm/i915/display/skl_watermark.c

3126

display->platform.coffeelake ||

drivers/gpu/drm/i915/display/skl_watermark.c

3127

display->platform.cometlake) {

drivers/gpu/drm/i915/display/skl_watermark.c

3128

const struct dram_info *dram_info = intel_dram_info(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3136

void skl_watermark_ipc_init(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3138

if (!HAS_IPC(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3141

display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3143

skl_watermark_ipc_update(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3146

static void multiply_wm_latency(struct intel_display *display, int mult)

drivers/gpu/drm/i915/display/skl_watermark.c

3148

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3149

int level, num_levels = display->wm.num_levels;

drivers/gpu/drm/i915/display/skl_watermark.c

3155

static void increase_wm_latency(struct intel_display *display, int inc)

drivers/gpu/drm/i915/display/skl_watermark.c

3157

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3158

int level, num_levels = display->wm.num_levels;

drivers/gpu/drm/i915/display/skl_watermark.c

3170

static bool need_16gb_dimm_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3172

const struct dram_info *dram_info = intel_dram_info(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3174

return (display->platform.skylake || display->platform.kabylake ||

drivers/gpu/drm/i915/display/skl_watermark.c

3175

display->platform.coffeelake || display->platform.cometlake ||

drivers/gpu/drm/i915/display/skl_watermark.c

3176

DISPLAY_VER(display) == 11) && dram_info->has_16gb_dimms;

drivers/gpu/drm/i915/display/skl_watermark.c

3179

static int wm_read_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3181

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/skl_watermark.c

3183

else if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_watermark.c

3189

static void sanitize_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3191

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3192

int level, num_levels = display->wm.num_levels;

drivers/gpu/drm/i915/display/skl_watermark.c

3198

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/skl_watermark.c

3215

static void make_wm_latency_monotonic(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3217

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3218

int level, num_levels = display->wm.num_levels;

drivers/gpu/drm/i915/display/skl_watermark.c

3229

adjust_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3231

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3233

if (display->platform.dg2)

drivers/gpu/drm/i915/display/skl_watermark.c

3234

multiply_wm_latency(display, 2);

drivers/gpu/drm/i915/display/skl_watermark.c

3236

sanitize_wm_latency(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3238

make_wm_latency_monotonic(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3248

increase_wm_latency(display, wm_read_latency(display));

drivers/gpu/drm/i915/display/skl_watermark.c

3256

if (need_16gb_dimm_wa(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3257

increase_wm_latency(display, 1);

drivers/gpu/drm/i915/display/skl_watermark.c

3260

static void mtl_read_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3262

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3265

val = intel_de_read(display, MTL_LATENCY_LP0_LP1);

drivers/gpu/drm/i915/display/skl_watermark.c

3269

val = intel_de_read(display, MTL_LATENCY_LP2_LP3);

drivers/gpu/drm/i915/display/skl_watermark.c

3273

val = intel_de_read(display, MTL_LATENCY_LP4_LP5);

drivers/gpu/drm/i915/display/skl_watermark.c

3278

static void skl_read_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3280

u16 *wm = display->wm.skl_latency;

drivers/gpu/drm/i915/display/skl_watermark.c

3286

ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);

drivers/gpu/drm/i915/display/skl_watermark.c

3288

drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);

drivers/gpu/drm/i915/display/skl_watermark.c

3299

ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);

drivers/gpu/drm/i915/display/skl_watermark.c

3301

drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);

drivers/gpu/drm/i915/display/skl_watermark.c

331

for (level = display->wm.num_levels - 1;

drivers/gpu/drm/i915/display/skl_watermark.c

3311

static void skl_setup_wm_latency(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3313

if (HAS_HW_SAGV_WM(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3314

display->wm.num_levels = 6;

drivers/gpu/drm/i915/display/skl_watermark.c

3316

display->wm.num_levels = 8;

drivers/gpu/drm/i915/display/skl_watermark.c

3318

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/skl_watermark.c

3319

mtl_read_wm_latency(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3321

skl_read_wm_latency(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3323

intel_print_wm_latency(display, "original", display->wm.skl_latency);

drivers/gpu/drm/i915/display/skl_watermark.c

3325

adjust_wm_latency(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3327

intel_print_wm_latency(display, "adjusted", display->wm.skl_latency);

drivers/gpu/drm/i915/display/skl_watermark.c

3355

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3358

dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj);

drivers/gpu/drm/i915/display/skl_watermark.c

3365

int intel_dbuf_init(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3373

intel_atomic_global_obj_init(display, &display->dbuf.obj,

drivers/gpu/drm/i915/display/skl_watermark.c

3401

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

3404

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/skl_watermark.c

3407

if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_watermark.c

3413

if (DISPLAY_VER(display) >= 14)

drivers/gpu/drm/i915/display/skl_watermark.c

3416

else if (display->platform.alderlake_p)

drivers/gpu/drm/i915/display/skl_watermark.c

3423

if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/skl_watermark.c

3425

} else if (display->platform.alderlake_p) {

drivers/gpu/drm/i915/display/skl_watermark.c

3428

} else if (DISPLAY_VER(display) >= 12) {

drivers/gpu/drm/i915/display/skl_watermark.c

3436

if (DISPLAY_VERx100(display) == 1400) {

drivers/gpu/drm/i915/display/skl_watermark.c

3446

static void pipe_mbus_dbox_ctl_update(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

3451

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes)

drivers/gpu/drm/i915/display/skl_watermark.c

3452

intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe),

drivers/gpu/drm/i915/display/skl_watermark.c

3458

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3461

if (DISPLAY_VER(display) < 11)

drivers/gpu/drm/i915/display/skl_watermark.c

3471

pipe_mbus_dbox_ctl_update(display, new_dbuf_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3488

void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

3493

if (!HAS_MBUS_JOINING(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3496

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/skl_watermark.c

3497

intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,

drivers/gpu/drm/i915/display/skl_watermark.c

3499

else if (DISPLAY_VER(display) >= 20)

drivers/gpu/drm/i915/display/skl_watermark.c

3500

intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,

drivers/gpu/drm/i915/display/skl_watermark.c

3506

drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n",

drivers/gpu/drm/i915/display/skl_watermark.c

3509

for_each_dbuf_slice(display, slice)

drivers/gpu/drm/i915/display/skl_watermark.c

3510

if (DISPLAY_VER(display) >= 35)

drivers/gpu/drm/i915/display/skl_watermark.c

3511

intel_de_rmw(display, DBUF_CTL_S(slice),

drivers/gpu/drm/i915/display/skl_watermark.c

3515

intel_de_rmw(display, DBUF_CTL_S(slice),

drivers/gpu/drm/i915/display/skl_watermark.c

3522

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3537

intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio,

drivers/gpu/drm/i915/display/skl_watermark.c

3544

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3549

drm_WARN_ON(display->drm, !dbuf_state->joined_mbus);

drivers/gpu/drm/i915/display/skl_watermark.c

3550

drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes));

drivers/gpu/drm/i915/display/skl_watermark.c

3552

crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/skl_watermark.c

3561

static void mbus_ctl_join_update(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

3577

intel_de_rmw(display, MBUS_CTL,

drivers/gpu/drm/i915/display/skl_watermark.c

3585

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3591

drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",

drivers/gpu/drm/i915/display/skl_watermark.c

3596

mbus_ctl_join_update(display, new_dbuf_state, pipe);

drivers/gpu/drm/i915/display/skl_watermark.c

3622

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3641

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

drivers/gpu/drm/i915/display/skl_watermark.c

3657

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3675

gen9_dbuf_slices_update(display, new_slices);

drivers/gpu/drm/i915/display/skl_watermark.c

3680

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3698

gen9_dbuf_slices_update(display, new_slices);

drivers/gpu/drm/i915/display/skl_watermark.c

3713

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3723

if (DISPLAY_VER(display) < 30) {

drivers/gpu/drm/i915/display/skl_watermark.c

3733

static void skl_mbus_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3736

to_intel_dbuf_state(display->dbuf.obj.state);

drivers/gpu/drm/i915/display/skl_watermark.c

3738

if (!HAS_MBUS_JOINING(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3745

drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n",

drivers/gpu/drm/i915/display/skl_watermark.c

3749

intel_dbuf_mdclk_cdclk_ratio_update(display,

drivers/gpu/drm/i915/display/skl_watermark.c

3752

pipe_mbus_dbox_ctl_update(display, dbuf_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3753

mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE);

drivers/gpu/drm/i915/display/skl_watermark.c

3756

static bool skl_dbuf_is_misconfigured(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3759

to_intel_dbuf_state(display->dbuf.obj.state);

drivers/gpu/drm/i915/display/skl_watermark.c

3763

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

3770

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

3788

static void skl_dbuf_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

379

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3803

if (!skl_dbuf_is_misconfigured(display))

drivers/gpu/drm/i915/display/skl_watermark.c

3806

drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");

drivers/gpu/drm/i915/display/skl_watermark.c

3808

for_each_intel_crtc(display->drm, crtc) {

drivers/gpu/drm/i915/display/skl_watermark.c

381

if (!display->params.enable_sagv)

drivers/gpu/drm/i915/display/skl_watermark.c

3818

drm_WARN_ON(display->drm, crtc_state->active_planes != 0);

drivers/gpu/drm/i915/display/skl_watermark.c

3824

static void skl_wm_sanitize(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

3826

skl_mbus_sanitize(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3827

skl_dbuf_sanitize(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3832

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

3836

to_intel_dbuf_state(display->dbuf.obj.state);

drivers/gpu/drm/i915/display/skl_watermark.c

3839

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/skl_watermark.c

3855

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

3859

if (DISPLAY_VER(display) < 9)

drivers/gpu/drm/i915/display/skl_watermark.c

3877

struct intel_display *display = to_intel_display(state);

drivers/gpu/drm/i915/display/skl_watermark.c

3892

if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active)

drivers/gpu/drm/i915/display/skl_watermark.c

3903

hw_enabled_slices = intel_enabled_dbuf_slices_mask(display);

drivers/gpu/drm/i915/display/skl_watermark.c

3905

if (DISPLAY_VER(display) >= 11 &&

drivers/gpu/drm/i915/display/skl_watermark.c

3906

hw_enabled_slices != display->dbuf.enabled_slices)

drivers/gpu/drm/i915/display/skl_watermark.c

3907

drm_err(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

3909

display->dbuf.enabled_slices,

drivers/gpu/drm/i915/display/skl_watermark.c

3912

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

3917

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

392

if (DISPLAY_VER(display) >= 12)

drivers/gpu/drm/i915/display/skl_watermark.c

3924

drm_err(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

3939

drm_err(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

3953

if (HAS_HW_SAGV_WM(display) &&

drivers/gpu/drm/i915/display/skl_watermark.c

3955

drm_err(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

3969

if (HAS_HW_SAGV_WM(display) &&

drivers/gpu/drm/i915/display/skl_watermark.c

3971

drm_err(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

3987

drm_err(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

4004

void skl_wm_init(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

4006

intel_sagv_init(display);

drivers/gpu/drm/i915/display/skl_watermark.c

4008

skl_setup_wm_latency(display);

drivers/gpu/drm/i915/display/skl_watermark.c

4010

display->funcs.wm = &skl_wm_funcs;

drivers/gpu/drm/i915/display/skl_watermark.c

4015

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/skl_watermark.c

4018

str_yes_no(skl_watermark_ipc_enabled(display)));

drivers/gpu/drm/i915/display/skl_watermark.c

4024

struct intel_display *display = inode->i_private;

drivers/gpu/drm/i915/display/skl_watermark.c

4026

return single_open(file, skl_watermark_ipc_status_show, display);

drivers/gpu/drm/i915/display/skl_watermark.c

4034

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/skl_watermark.c

4042

with_intel_display_rpm(display) {

drivers/gpu/drm/i915/display/skl_watermark.c

4043

if (!skl_watermark_ipc_enabled(display) && enable)

drivers/gpu/drm/i915/display/skl_watermark.c

4044

drm_info(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

4046

display->wm.ipc_enabled = enable;

drivers/gpu/drm/i915/display/skl_watermark.c

4047

skl_watermark_ipc_update(display);

drivers/gpu/drm/i915/display/skl_watermark.c

4064

struct intel_display *display = m->private;

drivers/gpu/drm/i915/display/skl_watermark.c

407

static int intel_dbuf_slice_size(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

4072

seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display)));

drivers/gpu/drm/i915/display/skl_watermark.c

4074

str_enabled_disabled(display->params.enable_sagv));

drivers/gpu/drm/i915/display/skl_watermark.c

4075

seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]);

drivers/gpu/drm/i915/display/skl_watermark.c

4076

seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us);

drivers/gpu/drm/i915/display/skl_watermark.c

4083

void skl_watermark_debugfs_register(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

4085

struct dentry *debugfs_root = display->drm->debugfs_root;

drivers/gpu/drm/i915/display/skl_watermark.c

4087

if (HAS_IPC(display))

drivers/gpu/drm/i915/display/skl_watermark.c

4089

display, &skl_watermark_ipc_status_fops);

drivers/gpu/drm/i915/display/skl_watermark.c

409

return DISPLAY_INFO(display)->dbuf.size /

drivers/gpu/drm/i915/display/skl_watermark.c

4091

if (HAS_SAGV(display))

drivers/gpu/drm/i915/display/skl_watermark.c

4093

display, &intel_sagv_status_fops);

drivers/gpu/drm/i915/display/skl_watermark.c

4096

unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)

drivers/gpu/drm/i915/display/skl_watermark.c

410

hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);

drivers/gpu/drm/i915/display/skl_watermark.c

4100

for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) {

drivers/gpu/drm/i915/display/skl_watermark.c

4101

unsigned int latency = skl_wm_latency(display, level, NULL);

drivers/gpu/drm/i915/display/skl_watermark.c

414

skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask,

drivers/gpu/drm/i915/display/skl_watermark.c

417

int slice_size = intel_dbuf_slice_size(display);

drivers/gpu/drm/i915/display/skl_watermark.c

429

WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size);

drivers/gpu/drm/i915/display/skl_watermark.c

432

static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)

drivers/gpu/drm/i915/display/skl_watermark.c

441

skl_ddb_entry_for_slices(display, slice_mask, &ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

446

u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

449

int slice_size = intel_dbuf_slice_size(display);

drivers/gpu/drm/i915/display/skl_watermark.c

495

struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);

drivers/gpu/drm/i915/display/skl_watermark.c

502

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/display/skl_watermark.c

528

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

550

skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices);

drivers/gpu/drm/i915/display/skl_watermark.c

551

mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask);

drivers/gpu/drm/i915/display/skl_watermark.c

585

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/skl_watermark.c

59

static void skl_sagv_disable(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.c

610

static unsigned int skl_wm_latency(struct intel_display *display, int level,

drivers/gpu/drm/i915/display/skl_watermark.c

613

unsigned int latency = display->wm.skl_latency[level];

drivers/gpu/drm/i915/display/skl_watermark.c

622

if ((display->platform.kabylake || display->platform.coffeelake ||

drivers/gpu/drm/i915/display/skl_watermark.c

623

display->platform.cometlake) && skl_watermark_ipc_enabled(display))

drivers/gpu/drm/i915/display/skl_watermark.c

626

if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled)

drivers/gpu/drm/i915/display/skl_watermark.c

636

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

638

const struct drm_mode_config *mode_config = &display->drm->mode_config;

drivers/gpu/drm/i915/display/skl_watermark.c

650

info = drm_get_format_info(display->drm, format, modifier);

drivers/gpu/drm/i915/display/skl_watermark.c

655

drm_WARN_ON(display->drm, ret);

drivers/gpu/drm/i915/display/skl_watermark.c

657

for (level = 0; level < display->wm.num_levels; level++) {

drivers/gpu/drm/i915/display/skl_watermark.c

658

unsigned int latency = skl_wm_latency(display, level, &wp);

drivers/gpu/drm/i915/display/skl_watermark.c

680

skl_ddb_get_hw_plane_state(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.c

691

val = intel_de_read(display, CUR_BUF_CFG(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

696

val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

699

if (DISPLAY_VER(display) >= 30) {

drivers/gpu/drm/i915/display/skl_watermark.c

700

val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

706

if (DISPLAY_VER(display) >= 11)

drivers/gpu/drm/i915/display/skl_watermark.c

709

val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

718

struct intel_display *display = to_intel_display(crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

725

wakeref = intel_display_power_get_if_enabled(display, power_domain);

drivers/gpu/drm/i915/display/skl_watermark.c

730

skl_ddb_get_hw_plane_state(display, pipe,

drivers/gpu/drm/i915/display/skl_watermark.c

737

intel_display_power_put(display, power_domain, wakeref);

drivers/gpu/drm/i915/display/skl_watermark.c

77

u8 intel_enabled_dbuf_slices_mask(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

82

for_each_dbuf_slice(display, slice) {

drivers/gpu/drm/i915/display/skl_watermark.c

83

if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)

drivers/gpu/drm/i915/display/skl_watermark.c

94

static bool skl_needs_memory_bw_wa(struct intel_display *display)

drivers/gpu/drm/i915/display/skl_watermark.c

96

return DISPLAY_VER(display) == 9;

drivers/gpu/drm/i915/display/skl_watermark.h

23

u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

28

bool intel_has_sagv(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

30

u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.h

44

void skl_watermark_ipc_init(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

45

void skl_watermark_ipc_update(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

46

bool skl_watermark_ipc_enabled(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

47

void skl_watermark_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

49

unsigned int skl_watermark_max_latency(struct intel_display *display,

drivers/gpu/drm/i915/display/skl_watermark.h

51

void skl_wm_init(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

68

int intel_dbuf_init(struct intel_display *display);

drivers/gpu/drm/i915/display/skl_watermark.h

74

void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,

drivers/gpu/drm/i915/display/vlv_clock.c

21

struct intel_display *display = to_intel_display(drm);

drivers/gpu/drm/i915/display/vlv_clock.c

24

if (!display->vlv_clock.hpll_freq) {

drivers/gpu/drm/i915/display/vlv_clock.c

31

display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000;

drivers/gpu/drm/i915/display/vlv_clock.c

33

drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq);

drivers/gpu/drm/i915/display/vlv_clock.c

36

return display->vlv_clock.hpll_freq;

drivers/gpu/drm/i915/display/vlv_clock.c

67

struct intel_display *display = to_intel_display(drm);

drivers/gpu/drm/i915/display/vlv_clock.c

69

if (!display->vlv_clock.czclk_freq) {

drivers/gpu/drm/i915/display/vlv_clock.c

70

display->vlv_clock.czclk_freq = vlv_clock_get_cck(drm, "czclk", CCK_CZ_CLOCK_CONTROL,

drivers/gpu/drm/i915/display/vlv_clock.c

72

drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);

drivers/gpu/drm/i915/display/vlv_clock.c

75

return display->vlv_clock.czclk_freq;

drivers/gpu/drm/i915/display/vlv_dsi.c

1005

intel_display_power_put(display, encoder->power_domain, wakeref);

drivers/gpu/drm/i915/display/vlv_dsi.c

1013

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

102

static void write_data(struct intel_display *display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1035

if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)

drivers/gpu/drm/i915/display/vlv_dsi.c

1039

fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;

drivers/gpu/drm/i915/display/vlv_dsi.c

1051

intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1054

intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1057

intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1061

hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1067

hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1068

hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1085

vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1086

vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1087

vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1095

drm_WARN_ON(display->drm, adjusted_mode->crtc_vdisplay +

drivers/gpu/drm/i915/display/vlv_dsi.c

114

intel_de_write(display, reg, val);

drivers/gpu/drm/i915/display/vlv_dsi.c

1178

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

118

static void read_data(struct intel_display *display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1182

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

1186

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1218

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

125

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/vlv_dsi.c

1253

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1260

intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1262

intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1264

intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1268

intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1270

intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);

drivers/gpu/drm/i915/display/vlv_dsi.c

1274

intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1276

intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);

drivers/gpu/drm/i915/display/vlv_dsi.c

1279

intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);

drivers/gpu/drm/i915/display/vlv_dsi.c

1280

intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1282

intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);

drivers/gpu/drm/i915/display/vlv_dsi.c

1306

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

1315

drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));

drivers/gpu/drm/i915/display/vlv_dsi.c

1326

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1331

tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));

drivers/gpu/drm/i915/display/vlv_dsi.c

1333

intel_de_write(display, MIPI_CTRL(display, PORT_A),

drivers/gpu/drm/i915/display/vlv_dsi.c

1337

tmp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1339

intel_de_write(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1341

} else if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1344

intel_de_rmw(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1349

intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);

drivers/gpu/drm/i915/display/vlv_dsi.c

1350

intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);

drivers/gpu/drm/i915/display/vlv_dsi.c

1352

intel_de_write(display, MIPI_DPHY_PARAM(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1355

intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

137

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/vlv_dsi.c

1376

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1383

intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);

drivers/gpu/drm/i915/display/vlv_dsi.c

1404

intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1407

intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1410

intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1412

intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1414

intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1420

intel_de_write(display, MIPI_INIT_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1423

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/vlv_dsi.c

1431

intel_de_write(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1432

MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),

drivers/gpu/drm/i915/display/vlv_dsi.c

1437

intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);

drivers/gpu/drm/i915/display/vlv_dsi.c

1440

intel_de_write(display, MIPI_INIT_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1448

intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1457

intel_de_write(display, MIPI_LP_BYTECLK(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1460

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1461

intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1464

intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1473

intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1476

intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1504

intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);

drivers/gpu/drm/i915/display/vlv_dsi.c

1511

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

1515

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/vlv_dsi.c

152

data_reg = MIPI_LP_GEN_DATA(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

1520

intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);

drivers/gpu/drm/i915/display/vlv_dsi.c

1522

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/vlv_dsi.c

1526

intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);

drivers/gpu/drm/i915/display/vlv_dsi.c

1528

intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

1530

intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);

drivers/gpu/drm/i915/display/vlv_dsi.c

154

ctrl_reg = MIPI_LP_GEN_CTRL(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

1541

struct intel_display *display = to_intel_display(connector->dev);

drivers/gpu/drm/i915/display/vlv_dsi.c

1543

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/vlv_dsi.c

1546

status = intel_cpu_transcoder_mode_valid(display, mode);

drivers/gpu/drm/i915/display/vlv_dsi.c

157

data_reg = MIPI_HS_GEN_DATA(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

159

ctrl_reg = MIPI_HS_GEN_CTRL(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

1594

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/vlv_dsi.c

1643

mul = display->platform.geminilake ? 8 : 2;

drivers/gpu/drm/i915/display/vlv_dsi.c

165

if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1651

drm_dbg_kms(display->drm, "prepare count too high %u\n",

drivers/gpu/drm/i915/display/vlv_dsi.c

167

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

1672

drm_dbg_kms(display->drm, "exit zero count too high %u\n",

drivers/gpu/drm/i915/display/vlv_dsi.c

1683

drm_dbg_kms(display->drm, "clock zero count too high %u\n",

drivers/gpu/drm/i915/display/vlv_dsi.c

1693

drm_dbg_kms(display->drm, "trail count too high %u\n",

drivers/gpu/drm/i915/display/vlv_dsi.c

170

write_data(display, data_reg, packet.payload,

drivers/gpu/drm/i915/display/vlv_dsi.c

175

intel_de_write(display, MIPI_INTR_STAT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1759

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/vlv_dsi.c

1768

if (display->platform.valleyview)

drivers/gpu/drm/i915/display/vlv_dsi.c

1776

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/vlv_dsi.c

179

if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

181

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

185

intel_de_write(display, ctrl_reg,

drivers/gpu/drm/i915/display/vlv_dsi.c

1901

void vlv_dsi_init(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi.c

191

if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

1911

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

1914

if (!intel_bios_is_dsi_present(display, &port))

drivers/gpu/drm/i915/display/vlv_dsi.c

1917

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/vlv_dsi.c

1918

display->dsi.mmio_base = BXT_MIPI_BASE;

drivers/gpu/drm/i915/display/vlv_dsi.c

1920

display->dsi.mmio_base = VLV_MIPI_BASE;

drivers/gpu/drm/i915/display/vlv_dsi.c

193

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

1935

drm_encoder_init(display->drm, &encoder->base, &intel_dsi_funcs,

drivers/gpu/drm/i915/display/vlv_dsi.c

1940

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/vlv_dsi.c

196

read_data(display, data_reg, msg->rx_buf, msg->rx_len);

drivers/gpu/drm/i915/display/vlv_dsi.c

1960

if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/vlv_dsi.c

1969

intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);

drivers/gpu/drm/i915/display/vlv_dsi.c

1976

if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))

drivers/gpu/drm/i915/display/vlv_dsi.c

1979

if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))

drivers/gpu/drm/i915/display/vlv_dsi.c

1995

drm_dbg_kms(display->drm, "no device found\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

2002

drm_dbg_kms(display->drm, "Calculated pclk %d GOP %d\n",

drivers/gpu/drm/i915/display/vlv_dsi.c

2006

drm_dbg_kms(display->drm, "Using GOP pclk\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

2018

drm_connector_init(display->drm, &connector->base, &intel_dsi_connector_funcs,

drivers/gpu/drm/i915/display/vlv_dsi.c

2027

mutex_lock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/vlv_dsi.c

2029

mutex_unlock(&display->drm->mode_config.mutex);

drivers/gpu/drm/i915/display/vlv_dsi.c

2032

drm_dbg_kms(display->drm, "no fixed mode\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

229

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/vlv_dsi.c

239

intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);

drivers/gpu/drm/i915/display/vlv_dsi.c

242

if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))

drivers/gpu/drm/i915/display/vlv_dsi.c

243

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

246

intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);

drivers/gpu/drm/i915/display/vlv_dsi.c

249

if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port), mask, 100))

drivers/gpu/drm/i915/display/vlv_dsi.c

250

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

256

static void band_gap_reset(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi.c

258

vlv_flisdsi_get(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi.c

260

vlv_flisdsi_write(display->drm, 0x08, 0x0001);

drivers/gpu/drm/i915/display/vlv_dsi.c

261

vlv_flisdsi_write(display->drm, 0x0F, 0x0005);

drivers/gpu/drm/i915/display/vlv_dsi.c

262

vlv_flisdsi_write(display->drm, 0x0F, 0x0025);

drivers/gpu/drm/i915/display/vlv_dsi.c

264

vlv_flisdsi_write(display->drm, 0x0F, 0x0000);

drivers/gpu/drm/i915/display/vlv_dsi.c

265

vlv_flisdsi_write(display->drm, 0x08, 0x0000);

drivers/gpu/drm/i915/display/vlv_dsi.c

267

vlv_flisdsi_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi.c

274

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

280

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

303

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

330

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

340

intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);

drivers/gpu/drm/i915/display/vlv_dsi.c

343

intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

347

u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

349

intel_de_rmw(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

355

if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

357

drm_err(display->drm, "MIPIO port is powergated\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

363

!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);

drivers/gpu/drm/i915/display/vlv_dsi.c

371

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

377

if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

379

drm_err(display->drm, "PHY is not ON\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

383

intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);

drivers/gpu/drm/i915/display/vlv_dsi.c

387

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {

drivers/gpu/drm/i915/display/vlv_dsi.c

388

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

393

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

397

if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

399

drm_err(display->drm, "ULPS not active\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

402

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

406

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

410

intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

416

if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

418

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

424

if (intel_de_wait_for_set_ms(display, BXT_MIPI_PORT_CTRL(port),

drivers/gpu/drm/i915/display/vlv_dsi.c

426

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

433

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

438

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

442

intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);

drivers/gpu/drm/i915/display/vlv_dsi.c

448

val = intel_de_read(display, MIPI_DEVICE_READY(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

450

intel_de_write(display, MIPI_DEVICE_READY(display, port), val);

drivers/gpu/drm/i915/display/vlv_dsi.c

453

intel_de_write(display, MIPI_DEVICE_READY(display, port), val);

drivers/gpu/drm/i915/display/vlv_dsi.c

459

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

463

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

465

vlv_flisdsi_get(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi.c

468

vlv_flisdsi_write(display->drm, 0x04, 0x0004);

drivers/gpu/drm/i915/display/vlv_dsi.c

469

vlv_flisdsi_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi.c

472

band_gap_reset(display);

drivers/gpu/drm/i915/display/vlv_dsi.c

476

intel_de_write(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

484

intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);

drivers/gpu/drm/i915/display/vlv_dsi.c

487

intel_de_write(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

491

intel_de_write(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

499

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

501

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/vlv_dsi.c

503

else if (display->platform.geminilake || display->platform.broxton)

drivers/gpu/drm/i915/display/vlv_dsi.c

511

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

517

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

522

if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

524

drm_err(display->drm, "PHY is not turning OFF\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

529

if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

531

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi.c

538

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

543

intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

547

if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

549

drm_err(display->drm, "PHY is not turning OFF\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

554

intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

563

static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port)

drivers/gpu/drm/i915/display/vlv_dsi.c

565

return display->platform.geminilake || display->platform.broxton ?

drivers/gpu/drm/i915/display/vlv_dsi.c

571

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

575

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

578

i915_reg_t port_ctrl = display->platform.broxton ?

drivers/gpu/drm/i915/display/vlv_dsi.c

581

intel_de_write(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

585

intel_de_write(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

589

intel_de_write(display, MIPI_DEVICE_READY(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

597

if ((display->platform.broxton || port == PORT_A) &&

drivers/gpu/drm/i915/display/vlv_dsi.c

598

intel_de_wait_for_clear_ms(display, port_ctrl,

drivers/gpu/drm/i915/display/vlv_dsi.c

600

drm_err(display->drm, "DSI LP not going Low\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

603

intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

606

intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);

drivers/gpu/drm/i915/display/vlv_dsi.c

614

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

622

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

624

intel_de_rmw(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

628

intel_de_rmw(display, VLV_CHICKEN_3,

drivers/gpu/drm/i915/display/vlv_dsi.c

635

i915_reg_t port_ctrl = port_ctrl_reg(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

638

temp = intel_de_read(display, port_ctrl);

drivers/gpu/drm/i915/display/vlv_dsi.c

646

if (display->platform.broxton)

drivers/gpu/drm/i915/display/vlv_dsi.c

658

intel_de_write(display, port_ctrl, temp | DPI_ENABLE);

drivers/gpu/drm/i915/display/vlv_dsi.c

659

intel_de_posting_read(display, port_ctrl);

drivers/gpu/drm/i915/display/vlv_dsi.c

665

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

670

i915_reg_t port_ctrl = port_ctrl_reg(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

673

intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

674

intel_de_posting_read(display, port_ctrl);

drivers/gpu/drm/i915/display/vlv_dsi.c

728

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

735

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

739

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

drivers/gpu/drm/i915/display/vlv_dsi.c

745

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

753

if (display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

755

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);

drivers/gpu/drm/i915/display/vlv_dsi.c

758

intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);

drivers/gpu/drm/i915/display/vlv_dsi.c

759

intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

762

if (display->platform.valleyview || display->platform.cherryview) {

drivers/gpu/drm/i915/display/vlv_dsi.c

764

intel_de_rmw(display, VLV_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/vlv_dsi.c

768

if (!display->platform.geminilake)

drivers/gpu/drm/i915/display/vlv_dsi.c

776

if (display->platform.geminilake) {

drivers/gpu/drm/i915/display/vlv_dsi.c

788

if (display->platform.geminilake && !glk_cold_boot)

drivers/gpu/drm/i915/display/vlv_dsi.c

800

intel_de_write(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

801

MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);

drivers/gpu/drm/i915/display/vlv_dsi.c

836

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

840

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

860

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

862

if (display->platform.geminilake)

drivers/gpu/drm/i915/display/vlv_dsi.c

873

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

877

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

879

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

906

if (display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

908

intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);

drivers/gpu/drm/i915/display/vlv_dsi.c

909

intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,

drivers/gpu/drm/i915/display/vlv_dsi.c

91

struct intel_display *display = to_intel_display(&intel_dsi->base);

drivers/gpu/drm/i915/display/vlv_dsi.c

913

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);

drivers/gpu/drm/i915/display/vlv_dsi.c

916

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

921

intel_de_rmw(display, VLV_DSPCLK_GATE_D,

drivers/gpu/drm/i915/display/vlv_dsi.c

937

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi.c

943

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

945

wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

955

if ((display->platform.geminilake || display->platform.broxton) &&

drivers/gpu/drm/i915/display/vlv_dsi.c

956

!bxt_dsi_pll_is_enabled(display))

drivers/gpu/drm/i915/display/vlv_dsi.c

961

i915_reg_t port_ctrl = port_ctrl_reg(display, port);

drivers/gpu/drm/i915/display/vlv_dsi.c

962

bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;

drivers/gpu/drm/i915/display/vlv_dsi.c

969

if ((display->platform.valleyview || display->platform.cherryview) &&

drivers/gpu/drm/i915/display/vlv_dsi.c

97

if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port),

drivers/gpu/drm/i915/display/vlv_dsi.c

971

enabled = intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

972

TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

drivers/gpu/drm/i915/display/vlv_dsi.c

976

u32 tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

977

MIPI_DSI_FUNC_PRG(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

984

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))

drivers/gpu/drm/i915/display/vlv_dsi.c

987

if (display->platform.geminilake || display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi.c

988

u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

99

drm_err(display->drm, "DPI FIFOs are not empty\n");

drivers/gpu/drm/i915/display/vlv_dsi.c

992

if (drm_WARN_ON(display->drm, tmp > PIPE_C))

drivers/gpu/drm/i915/display/vlv_dsi.h

17

void vlv_dsi_init(struct intel_display *display);

drivers/gpu/drm/i915/display/vlv_dsi.h

26

static inline void vlv_dsi_init(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

121

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

127

int refclk = display->platform.cherryview ? 100000 : 25000;

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

150

drm_err(display->drm, "wrong P1 divisor\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

160

drm_err(display->drm, "wrong m_seed programmed\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

178

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

185

ret = dsi_calc_mnp(display, config, dsi_clk);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

187

drm_dbg_kms(display->drm, "dsi_calc_mnp failed\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

199

drm_dbg_kms(display->drm, "dsi pll div %08x, ctrl %08x\n",

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

216

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

220

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

222

vlv_cck_get(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

224

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, 0);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

225

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

226

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

234

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

236

ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL),

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

240

vlv_cck_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

241

drm_err(display->drm, "DSI PLL lock failed\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

244

vlv_cck_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

246

drm_dbg_kms(display->drm, "DSI PLL locked\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

251

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

254

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

256

vlv_cck_get(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

258

tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

261

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, tmp);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

263

vlv_cck_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

266

static bool has_dsic_clock(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

268

return display->platform.broxton;

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

271

bool bxt_dsi_pll_is_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

278

val = intel_de_read(display, BXT_DSI_PLL_ENABLE);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

292

val = intel_de_read(display, BXT_DSI_PLL_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

293

if (!has_dsic_clock(display)) {

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

295

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

301

drm_dbg_kms(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

312

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

314

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

316

intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

322

if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

324

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

331

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

334

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

336

vlv_cck_get(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

337

pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

338

pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

339

vlv_cck_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

363

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

366

config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

367

if (!has_dsic_clock(display))

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

372

drm_dbg_kms(display->drm, "Calculated pclk=%u\n", pclk);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

378

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

382

temp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

384

intel_de_write(display, MIPI_CTRL(display, port),

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

388

static void glk_dsi_program_esc_clock(struct intel_display *display,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

427

intel_de_write(display, MIPIO_TXESC_CLK_DIV1,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

429

intel_de_write(display, MIPIO_TXESC_CLK_DIV2,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

434

static void bxt_dsi_program_clocks(struct intel_display *display, enum port port,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

447

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

483

intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

489

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

505

if (display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

514

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

518

drm_dbg_kms(display->drm, "DSI PLL calculation is Done!!\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

526

if (has_dsic_clock(display))

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

532

if (display->platform.broxton && dsi_ratio <= 50)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

549

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

553

drm_dbg_kms(display->drm, "\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

556

intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

557

intel_de_posting_read(display, BXT_DSI_PLL_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

560

if (display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

562

bxt_dsi_program_clocks(display, port, config);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

564

glk_dsi_program_esc_clock(display, config);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

568

intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

571

if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

573

drm_err(display->drm,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

578

drm_dbg_kms(display->drm, "DSI PLL locked\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

583

struct intel_display *display = to_intel_display(encoder);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

587

if (display->platform.broxton) {

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

588

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

593

intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

595

intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

597

intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

599

intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

602

static void assert_dsi_pll(struct intel_display *display, bool state)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

606

vlv_cck_get(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

607

cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

608

vlv_cck_put(display->drm);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

610

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

615

void assert_dsi_pll_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

617

assert_dsi_pll(display, true);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

62

static int dsi_calc_mnp(struct intel_display *display,

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

620

void assert_dsi_pll_disabled(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

622

assert_dsi_pll(display, false);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

73

drm_err(display->drm, "DSI CLK Out of Range\n");

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

77

if (display->platform.cherryview) {

drivers/gpu/drm/i915/display/vlv_dsi_pll.h

35

bool bxt_dsi_pll_is_enabled(struct intel_display *display);

drivers/gpu/drm/i915/display/vlv_dsi_pll.h

36

void assert_dsi_pll_enabled(struct intel_display *display);

drivers/gpu/drm/i915/display/vlv_dsi_pll.h

37

void assert_dsi_pll_disabled(struct intel_display *display);

drivers/gpu/drm/i915/display/vlv_dsi_pll.h

39

static inline bool bxt_dsi_pll_is_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.h

43

static inline void assert_dsi_pll_enabled(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_pll.h

47

static inline void assert_dsi_pll_disabled(struct intel_display *display)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

107

#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

110

#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

14

#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

146

#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

169

#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

174

#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

179

#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

184

#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

189

#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

197

#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

205

#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

209

#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

213

#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

217

#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

221

#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

225

#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

229

#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

233

#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

237

#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

248

#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

254

#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

260

#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

266

#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

276

#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

290

#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

296

#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

300

#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

305

#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

310

#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

314

#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

317

#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

330

#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

348

#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

355

#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

367

#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

371

#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

379

#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

385

#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

388

#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

392

#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

407

#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

440

#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

447

#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

453

#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

462

#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

468

#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

472

#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

97

#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)

drivers/gpu/drm/i915/display/vlv_sideband.c

11

static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display,

drivers/gpu/drm/i915/display/vlv_sideband.c

18

if (display->platform.cherryview)

drivers/gpu/drm/i915/display/vlv_sideband.c

26

struct intel_display *display = to_intel_display(drm);

drivers/gpu/drm/i915/display/vlv_sideband.c

27

enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);

drivers/gpu/drm/i915/display/vlv_sideband.c

36

drm_WARN(display->drm, val == 0xffffffff,

drivers/gpu/drm/i915/display/vlv_sideband.c

46

struct intel_display *display = to_intel_display(drm);

drivers/gpu/drm/i915/display/vlv_sideband.c

47

enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

115

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

127

return intel_display_device_present(display);

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

333

struct intel_display *display = ggtt->vm.i915->display;

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

359

if (intel_has_pending_fb_unpin(display))

drivers/gpu/drm/i915/gt/intel_gt_pm.c

109

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gt/intel_gt_pm.c

127

intel_display_power_put_async(display, POWER_DOMAIN_GT_IRQ, wakeref);

drivers/gpu/drm/i915/gt/intel_gt_pm.c

75

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gt/intel_gt_pm.c

90

gt->awake = intel_display_power_get(display, POWER_DOMAIN_GT_IRQ);

drivers/gpu/drm/i915/gt/intel_reset.c

1205

struct intel_display *display = gt->i915->display;

drivers/gpu/drm/i915/gt/intel_reset.c

1251

intel_overlay_reset(display);

drivers/gpu/drm/i915/gt/intel_reset.c

1423

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gt/intel_reset.c

1430

reset_display = intel_display_reset_test(display) ||

drivers/gpu/drm/i915/gt/intel_reset.c

1434

reset_display = intel_display_reset_prepare(display,

drivers/gpu/drm/i915/gt/intel_reset.c

1441

intel_display_reset_finish(display, !need_display_reset);

drivers/gpu/drm/i915/gt/intel_rps.c

561

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gt/intel_rps.c

619

ilk_display_rps_enable(display);

drivers/gpu/drm/i915/gt/intel_rps.c

631

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gt/intel_rps.c

637

ilk_display_rps_disable(display);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1295

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1324

info->ctrl_reg = DSPCNTR(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1325

info->stride_reg = DSPSTRIDE(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1326

info->surf_reg = DSPSURF(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1342

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1391

info->ctrl_reg = DSPCNTR(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1392

info->stride_reg = DSPSTRIDE(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1393

info->surf_reg = DSPSURF(display, info->pipe);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1430

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1448

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;

drivers/gpu/drm/i915/gvt/display.c

190

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

203

gvt_for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/gvt/display.c

204

vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=

drivers/gpu/drm/i915/gvt/display.c

206

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

208

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

drivers/gpu/drm/i915/gvt/display.c

209

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

drivers/gpu/drm/i915/gvt/display.c

213

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=

drivers/gpu/drm/i915/gvt/display.c

217

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

265

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

266

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

274

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

drivers/gpu/drm/i915/gvt/display.c

275

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

drivers/gpu/drm/i915/gvt/display.c

276

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

drivers/gpu/drm/i915/gvt/display.c

277

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/gvt/display.c

278

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

drivers/gpu/drm/i915/gvt/display.c

301

TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |=

drivers/gpu/drm/i915/gvt/display.c

331

TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

362

TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

411

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

drivers/gpu/drm/i915/gvt/display.c

412

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

drivers/gpu/drm/i915/gvt/display.c

413

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

drivers/gpu/drm/i915/gvt/display.c

414

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/gvt/display.c

415

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

drivers/gpu/drm/i915/gvt/display.c

426

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

429

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

452

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

455

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

478

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

481

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

519

gvt_for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/gvt/display.c

520

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

522

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

drivers/gpu/drm/i915/gvt/display.c

523

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

drivers/gpu/drm/i915/gvt/display.c

526

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

585

vgpu->display.port_num = port_num;

drivers/gpu/drm/i915/gvt/display.c

611

intel_vgpu_port(vgpu, vgpu->display.port_num);

drivers/gpu/drm/i915/gvt/display.c

641

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

663

vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/display.c

671

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/gvt/display.c

675

gvt_for_each_pipe(display, pipe)

drivers/gpu/drm/i915/gvt/display.c

76

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

78

if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))

drivers/gpu/drm/i915/gvt/display.c

89

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/display.c

95

if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)

drivers/gpu/drm/i915/gvt/display.h

48

(&(vgpu->display.ports[port]))

drivers/gpu/drm/i915/gvt/display_helpers.h

11

#define DISPLAY_MMIO_BASE(display) \

drivers/gpu/drm/i915/gvt/display_helpers.h

12

intel_display_device_mmio_base((display))

drivers/gpu/drm/i915/gvt/display_helpers.h

24

#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, idx) \

drivers/gpu/drm/i915/gvt/display_helpers.h

25

intel_display_device_pipe_offset((display), (enum pipe)(idx))

drivers/gpu/drm/i915/gvt/display_helpers.h

27

#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \

drivers/gpu/drm/i915/gvt/display_helpers.h

28

intel_display_device_trans_offset((display), (trans))

drivers/gpu/drm/i915/gvt/display_helpers.h

30

#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \

drivers/gpu/drm/i915/gvt/display_helpers.h

31

intel_display_device_cursor_offset((display), (pipe))

drivers/gpu/drm/i915/gvt/display_helpers.h

33

#define gvt_for_each_pipe(display, __p) \

drivers/gpu/drm/i915/gvt/display_helpers.h

35

for_each_if(intel_display_device_pipe_valid((display), (__p)))

drivers/gpu/drm/i915/gvt/edid.c

137

if (!vgpu->display.i2c_edid.edid_available)

drivers/gpu/drm/i915/gvt/edid.c

139

vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;

drivers/gpu/drm/i915/gvt/edid.c

167

vgpu->display.i2c_edid.state = I2C_GMBUS;

drivers/gpu/drm/i915/gvt/edid.c

168

vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;

drivers/gpu/drm/i915/gvt/edid.c

175

vgpu->display.i2c_edid.port = port;

drivers/gpu/drm/i915/gvt/edid.c

176

vgpu->display.i2c_edid.edid_available = true;

drivers/gpu/drm/i915/gvt/edid.c

186

struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

drivers/gpu/drm/i915/gvt/edid.c

298

struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

drivers/gpu/drm/i915/gvt/edid.c

487

struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

drivers/gpu/drm/i915/gvt/edid.c

574

struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;

drivers/gpu/drm/i915/gvt/edid.c

59

struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;

drivers/gpu/drm/i915/gvt/fb_decoder.c

159

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/fb_decoder.c

161

u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;

drivers/gpu/drm/i915/gvt/fb_decoder.c

216

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/fb_decoder.c

224

val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

258

plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;

drivers/gpu/drm/i915/gvt/fb_decoder.c

274

plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>

drivers/gpu/drm/i915/gvt/fb_decoder.c

277

plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &

drivers/gpu/drm/i915/gvt/fb_decoder.c

281

val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

347

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/fb_decoder.c

356

val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

382

plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;

drivers/gpu/drm/i915/gvt/fb_decoder.c

393

val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));

drivers/gpu/drm/i915/gvt/gvt.h

206

struct intel_vgpu_display display;

drivers/gpu/drm/i915/gvt/handlers.c

1027

#define DSPSURF_TO_PIPE(display, offset) \

drivers/gpu/drm/i915/gvt/handlers.c

1028

calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

1034

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

1035

u32 pipe = DSPSURF_TO_PIPE(display, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1039

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1041

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/handlers.c

1043

if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)

drivers/gpu/drm/i915/gvt/handlers.c

1076

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

1083

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1084

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/handlers.c

1190

struct intel_vgpu_display *display = &vgpu->display;

drivers/gpu/drm/i915/gvt/handlers.c

1223

port = &display->ports[port_index];

drivers/gpu/drm/i915/gvt/handlers.c

1383

struct intel_vgpu_display *display = &vgpu->display;

drivers/gpu/drm/i915/gvt/handlers.c

1384

int num = display->sbi.number;

drivers/gpu/drm/i915/gvt/handlers.c

1388

if (display->sbi.registers[i].offset == sbi_offset)

drivers/gpu/drm/i915/gvt/handlers.c

1394

return display->sbi.registers[i].value;

drivers/gpu/drm/i915/gvt/handlers.c

1400

struct intel_vgpu_display *display = &vgpu->display;

drivers/gpu/drm/i915/gvt/handlers.c

1401

int num = display->sbi.number;

drivers/gpu/drm/i915/gvt/handlers.c

1405

if (display->sbi.registers[i].offset == offset)

drivers/gpu/drm/i915/gvt/handlers.c

1414

display->sbi.number++;

drivers/gpu/drm/i915/gvt/handlers.c

1417

display->sbi.registers[i].offset = offset;

drivers/gpu/drm/i915/gvt/handlers.c

1418

display->sbi.registers[i].value = value;

drivers/gpu/drm/i915/gvt/handlers.c

2211

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

2300

MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2302

MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2304

MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2306

MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2308

MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2311

MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2314

MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

670

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/gvt/handlers.c

675

port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &

drivers/gpu/drm/i915/gvt/handlers.c

691

link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));

drivers/gpu/drm/i915/gvt/handlers.c

692

link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));

drivers/gpu/drm/i915/gvt/handlers.c

695

htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);

drivers/gpu/drm/i915/gvt/handlers.c

696

vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);

drivers/gpu/drm/i915/gvt/handlers.c

701

u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);

drivers/gpu/drm/i915/i915_driver.c

1026

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_driver.c

1030

intel_power_domains_disable(display);

drivers/gpu/drm/i915/i915_driver.c

1033

if (intel_display_device_present(display)) {

drivers/gpu/drm/i915/i915_driver.c

1035

intel_display_driver_disable_user_access(display);

drivers/gpu/drm/i915/i915_driver.c

1040

intel_dp_mst_suspend(display);

drivers/gpu/drm/i915/i915_driver.c

1043

intel_hpd_cancel_work(display);

drivers/gpu/drm/i915/i915_driver.c

1045

if (intel_display_device_present(display))

drivers/gpu/drm/i915/i915_driver.c

1046

intel_display_driver_suspend_access(display);

drivers/gpu/drm/i915/i915_driver.c

1048

intel_encoder_suspend_all(display);

drivers/gpu/drm/i915/i915_driver.c

1049

intel_encoder_shutdown_all(display);

drivers/gpu/drm/i915/i915_driver.c

1051

intel_dmc_suspend(display);

drivers/gpu/drm/i915/i915_driver.c

1066

intel_power_domains_driver_remove(display);

drivers/gpu/drm/i915/i915_driver.c

1106

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1113

intel_power_domains_disable(display);

drivers/gpu/drm/i915/i915_driver.c

1115

if (intel_display_device_present(display)) {

drivers/gpu/drm/i915/i915_driver.c

1117

intel_display_driver_disable_user_access(display);

drivers/gpu/drm/i915/i915_driver.c

1120

intel_display_driver_suspend(display);

drivers/gpu/drm/i915/i915_driver.c

1123

intel_hpd_cancel_work(display);

drivers/gpu/drm/i915/i915_driver.c

1125

if (intel_display_device_present(display))

drivers/gpu/drm/i915/i915_driver.c

1126

intel_display_driver_suspend_access(display);

drivers/gpu/drm/i915/i915_driver.c

1128

intel_encoder_suspend_all(display);

drivers/gpu/drm/i915/i915_driver.c

1131

intel_dpt_suspend(display);

drivers/gpu/drm/i915/i915_driver.c

1134

i9xx_display_sr_save(display);

drivers/gpu/drm/i915/i915_driver.c

1137

intel_opregion_suspend(display, opregion_target_state);

drivers/gpu/drm/i915/i915_driver.c

1141

intel_dmc_suspend(display);

drivers/gpu/drm/i915/i915_driver.c

1153

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1168

intel_display_power_suspend_late(display, s2idle);

drivers/gpu/drm/i915/i915_driver.c

1173

intel_display_power_resume_early(display);

drivers/gpu/drm/i915/i915_driver.c

1240

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1263

intel_dpt_resume(display);

drivers/gpu/drm/i915/i915_driver.c

1265

intel_dmc_resume(display);

drivers/gpu/drm/i915/i915_driver.c

1267

i9xx_display_sr_restore(display);

drivers/gpu/drm/i915/i915_driver.c

1269

intel_gmbus_reset(display);

drivers/gpu/drm/i915/i915_driver.c

1271

intel_pps_unlock_regs_wa(display);

drivers/gpu/drm/i915/i915_driver.c

1273

intel_init_pch_refclk(display);

drivers/gpu/drm/i915/i915_driver.c

1287

if (intel_display_device_present(display))

drivers/gpu/drm/i915/i915_driver.c

1292

intel_display_driver_init_hw(display);

drivers/gpu/drm/i915/i915_driver.c

1296

if (intel_display_device_present(display))

drivers/gpu/drm/i915/i915_driver.c

1297

intel_display_driver_resume_access(display);

drivers/gpu/drm/i915/i915_driver.c

1299

intel_hpd_init(display);

drivers/gpu/drm/i915/i915_driver.c

1301

intel_display_driver_resume(display);

drivers/gpu/drm/i915/i915_driver.c

1303

if (intel_display_device_present(display)) {

drivers/gpu/drm/i915/i915_driver.c

1304

intel_display_driver_enable_user_access(display);

drivers/gpu/drm/i915/i915_driver.c

1307

intel_hpd_poll_disable(display);

drivers/gpu/drm/i915/i915_driver.c

1309

intel_opregion_resume(display);

drivers/gpu/drm/i915/i915_driver.c

1313

intel_power_domains_enable(display);

drivers/gpu/drm/i915/i915_driver.c

1325

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1349

intel_display_power_resume_early(display);

drivers/gpu/drm/i915/i915_driver.c

1548

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1578

intel_display_power_suspend(display);

drivers/gpu/drm/i915/i915_driver.c

1623

intel_opregion_notify_adapter(display, PCI_D3hot);

drivers/gpu/drm/i915/i915_driver.c

1632

intel_opregion_notify_adapter(display, PCI_D1);

drivers/gpu/drm/i915/i915_driver.c

1638

intel_hpd_poll_enable(display);

drivers/gpu/drm/i915/i915_driver.c

1647

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

1662

intel_opregion_notify_adapter(display, PCI_D0);

drivers/gpu/drm/i915/i915_driver.c

1672

intel_display_power_resume(display);

drivers/gpu/drm/i915/i915_driver.c

1696

intel_hpd_init(display);

drivers/gpu/drm/i915/i915_driver.c

1697

intel_hpd_poll_disable(display);

drivers/gpu/drm/i915/i915_driver.c

1700

skl_watermark_ipc_update(display);

drivers/gpu/drm/i915/i915_driver.c

229

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

240

intel_sbi_init(display);

drivers/gpu/drm/i915/i915_driver.c

266

intel_display_driver_early_probe(display);

drivers/gpu/drm/i915/i915_driver.c

290

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

293

intel_power_domains_cleanup(display);

drivers/gpu/drm/i915/i915_driver.c

302

intel_sbi_fini(display);

drivers/gpu/drm/i915/i915_driver.c

306

intel_display_device_remove(display);

drivers/gpu/drm/i915/i915_driver.c

320

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

343

intel_display_device_info_runtime_init(display);

drivers/gpu/drm/i915/i915_driver.c

465

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

563

intel_opregion_setup(display);

drivers/gpu/drm/i915/i915_driver.c

573

ret = intel_dram_detect(display);

drivers/gpu/drm/i915/i915_driver.c

577

intel_bw_init_hw(display);

drivers/gpu/drm/i915/i915_driver.c

582

intel_opregion_cleanup(display);

drivers/gpu/drm/i915/i915_driver.c

604

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

609

intel_opregion_cleanup(display);

drivers/gpu/drm/i915/i915_driver.c

624

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

658

intel_display_driver_register(display);

drivers/gpu/drm/i915/i915_driver.c

660

intel_power_domains_enable(display);

drivers/gpu/drm/i915/i915_driver.c

675

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_driver.c

682

intel_power_domains_disable(display);

drivers/gpu/drm/i915/i915_driver.c

684

intel_display_driver_unregister(display);

drivers/gpu/drm/i915/i915_driver.c

788

INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct drm_i915_private, drm, display);

drivers/gpu/drm/i915/i915_driver.c

796

struct intel_display *display;

drivers/gpu/drm/i915/i915_driver.c

811

display = intel_display_device_probe(pdev, &parent);

drivers/gpu/drm/i915/i915_driver.c

812

if (IS_ERR(display))

drivers/gpu/drm/i915/i915_driver.c

813

return ERR_CAST(display);

drivers/gpu/drm/i915/i915_driver.c

815

i915->display = display;

drivers/gpu/drm/i915/i915_driver.c

834

struct intel_display *display;

drivers/gpu/drm/i915/i915_driver.c

849

display = i915->display;

drivers/gpu/drm/i915/i915_driver.c

871

ret = intel_display_driver_probe_noirq(display);

drivers/gpu/drm/i915/i915_driver.c

879

ret = intel_display_driver_probe_nogem(display);

drivers/gpu/drm/i915/i915_driver.c

891

ret = intel_display_driver_probe(display);

drivers/gpu/drm/i915/i915_driver.c

914

intel_display_driver_remove(display);

drivers/gpu/drm/i915/i915_driver.c

916

intel_display_driver_remove_noirq(display);

drivers/gpu/drm/i915/i915_driver.c

921

intel_display_driver_remove_nogem(display);

drivers/gpu/drm/i915/i915_driver.c

942

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_driver.c

956

intel_display_driver_remove(display);

drivers/gpu/drm/i915/i915_driver.c

960

intel_display_driver_remove_noirq(display);

drivers/gpu/drm/i915/i915_driver.c

965

intel_display_driver_remove_nogem(display);

drivers/gpu/drm/i915/i915_drv.h

172

struct intel_display *display;

drivers/gpu/drm/i915/i915_getparam.c

21

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_getparam.c

44

value = intel_overlay_available(display);

drivers/gpu/drm/i915/i915_gpu_error.c

2172

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_gpu_error.c

2214

error->display_snapshot = intel_display_snapshot_capture(display);

drivers/gpu/drm/i915/i915_irq.c

1005

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

1027

hotplug_status = i9xx_hpd_irq_ack(display);

drivers/gpu/drm/i915/i915_irq.c

1031

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

1050

i9xx_hpd_irq_handler(display, hotplug_status);

drivers/gpu/drm/i915/i915_irq.c

1052

i965_pipestat_irq_handler(display, iir, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

1202

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

1212

intel_hpd_cancel_work(display);

drivers/gpu/drm/i915/i915_irq.c

228

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

275

hotplug_status = i9xx_hpd_irq_ack(display);

drivers/gpu/drm/i915/i915_irq.c

278

vlv_display_error_irq_ack(display, &eir, &dpinvgtt);

drivers/gpu/drm/i915/i915_irq.c

282

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

286

intel_lpe_audio_irq_handler(display);

drivers/gpu/drm/i915/i915_irq.c

304

i9xx_hpd_irq_handler(display, hotplug_status);

drivers/gpu/drm/i915/i915_irq.c

307

vlv_display_error_irq_handler(display, eir, dpinvgtt);

drivers/gpu/drm/i915/i915_irq.c

309

valleyview_pipestat_irq_handler(display, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

322

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

365

hotplug_status = i9xx_hpd_irq_ack(display);

drivers/gpu/drm/i915/i915_irq.c

368

vlv_display_error_irq_ack(display, &eir, &dpinvgtt);

drivers/gpu/drm/i915/i915_irq.c

372

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

377

intel_lpe_audio_irq_handler(display);

drivers/gpu/drm/i915/i915_irq.c

390

i9xx_hpd_irq_handler(display, hotplug_status);

drivers/gpu/drm/i915/i915_irq.c

393

vlv_display_error_irq_handler(display, eir, dpinvgtt);

drivers/gpu/drm/i915/i915_irq.c

395

valleyview_pipestat_irq_handler(display, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

416

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_irq.c

428

ilk_display_irq_master_disable(display, &de_ier, &sde_ier);

drivers/gpu/drm/i915/i915_irq.c

442

if (ilk_display_irq_handler(display))

drivers/gpu/drm/i915/i915_irq.c

455

ilk_display_irq_master_enable(display, de_ier, sde_ier);

drivers/gpu/drm/i915/i915_irq.c

486

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

505

gen8_de_irq_handler(display, master_ctl);

drivers/gpu/drm/i915/i915_irq.c

537

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_irq.c

557

gen11_display_irq_handler(display);

drivers/gpu/drm/i915/i915_irq.c

559

gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);

drivers/gpu/drm/i915/i915_irq.c

563

gen11_gu_misc_irq_handler(display, gu_misc_iir);

drivers/gpu/drm/i915/i915_irq.c

595

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/i915_irq.c

624

gen11_display_irq_handler(display);

drivers/gpu/drm/i915/i915_irq.c

626

gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);

drivers/gpu/drm/i915/i915_irq.c

630

gen11_gu_misc_irq_handler(display, gu_misc_iir);

drivers/gpu/drm/i915/i915_irq.c

639

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

642

ilk_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

648

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

655

vlv_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

660

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

666

gen8_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

672

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

679

gen11_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

687

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

697

gen11_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

707

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

717

vlv_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

722

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

726

ilk_de_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

731

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

735

vlv_display_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

743

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

746

gen8_de_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

753

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

759

gen11_de_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

769

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

780

dg1_de_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

788

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

792

vlv_display_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

863

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

866

i9xx_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

875

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

881

enable_mask = i9xx_display_irq_enable_mask(display) |

drivers/gpu/drm/i915/i915_irq.c

890

i915_display_irq_postinstall(display);

drivers/gpu/drm/i915/i915_irq.c

896

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

918

hotplug_status = i9xx_hpd_irq_ack(display);

drivers/gpu/drm/i915/i915_irq.c

922

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

936

i9xx_hpd_irq_handler(display, hotplug_status);

drivers/gpu/drm/i915/i915_irq.c

938

i915_pipestat_irq_handler(display, iir, pipe_stats);

drivers/gpu/drm/i915/i915_irq.c

950

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

953

i9xx_display_irq_reset(display);

drivers/gpu/drm/i915/i915_irq.c

981

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/i915_irq.c

987

enable_mask = i9xx_display_irq_enable_mask(display) |

drivers/gpu/drm/i915/i915_irq.c

999

i965_display_irq_postinstall(display);

drivers/gpu/drm/i915/i915_switcheroo.c

20

struct intel_display *display = i915 ? i915->display : NULL;

drivers/gpu/drm/i915/i915_switcheroo.c

27

if (!intel_display_device_present(display)) {

drivers/gpu/drm/i915/i915_switcheroo.c

50

struct intel_display *display = i915 ? i915->display : NULL;

drivers/gpu/drm/i915/i915_switcheroo.c

57

return i915 && intel_display_device_present(display) &&

drivers/gpu/drm/i915/intel_clock_gating.c

137

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/intel_clock_gating.c

140

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/intel_clock_gating.c

141

intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),

drivers/gpu/drm/i915/intel_clock_gating.c

144

intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),

drivers/gpu/drm/i915/intel_clock_gating.c

147

DSPSURF(display, pipe));

drivers/gpu/drm/i915/intel_clock_gating.c

208

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_clock_gating.c

224

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/intel_clock_gating.c

228

if (display->vbt.fdi_rx_polarity_inverted)

drivers/gpu/drm/i915/intel_clock_gating.c

235

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/intel_clock_gating.c

313

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_clock_gating.c

319

if (HAS_PCH_LPT_LP(display))

drivers/gpu/drm/i915/intel_clock_gating.c

363

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_clock_gating.c

365

if (!HAS_PCH_CNP(display))

drivers/gpu/drm/i915/intel_clock_gating.c

431

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_clock_gating.c

443

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/intel_clock_gating.c

479

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_clock_gating.c

488

for_each_pipe(display, pipe) {

drivers/gpu/drm/i915/intel_clock_gating.c

506

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_clock_gating.c

545

if (!HAS_PCH_NOP(display))

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1117

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1249

MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1250

MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1251

MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

139

MMIO_D(PIPEDSL(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

140

MMIO_D(PIPEDSL(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

141

MMIO_D(PIPEDSL(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

142

MMIO_D(PIPEDSL(display, _PIPE_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

143

MMIO_D(TRANSCONF(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

144

MMIO_D(TRANSCONF(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

145

MMIO_D(TRANSCONF(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

146

MMIO_D(TRANSCONF(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

147

MMIO_D(PIPESTAT(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

148

MMIO_D(PIPESTAT(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

149

MMIO_D(PIPESTAT(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

150

MMIO_D(PIPESTAT(display, _PIPE_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

151

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

152

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

153

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

154

MMIO_D(PIPE_FLIPCOUNT_G4X(display, _PIPE_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

155

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

156

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

157

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

158

MMIO_D(PIPE_FRMCOUNT_G4X(display, _PIPE_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

159

MMIO_D(CURCNTR(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

160

MMIO_D(CURCNTR(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

161

MMIO_D(CURCNTR(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

162

MMIO_D(CURPOS(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

163

MMIO_D(CURPOS(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

164

MMIO_D(CURPOS(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

165

MMIO_D(CURBASE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

166

MMIO_D(CURBASE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

167

MMIO_D(CURBASE(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

168

MMIO_D(CUR_FBC_CTL(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

169

MMIO_D(CUR_FBC_CTL(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

170

MMIO_D(CUR_FBC_CTL(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

178

MMIO_D(DSPCNTR(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

179

MMIO_D(DSPADDR(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

180

MMIO_D(DSPSTRIDE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

181

MMIO_D(DSPPOS(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

182

MMIO_D(DSPSIZE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

183

MMIO_D(DSPSURF(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

184

MMIO_D(DSPOFFSET(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

185

MMIO_D(DSPSURFLIVE(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

187

MMIO_D(DSPCNTR(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

188

MMIO_D(DSPADDR(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

189

MMIO_D(DSPSTRIDE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

190

MMIO_D(DSPPOS(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

191

MMIO_D(DSPSIZE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

192

MMIO_D(DSPSURF(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

193

MMIO_D(DSPOFFSET(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

194

MMIO_D(DSPSURFLIVE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

196

MMIO_D(DSPCNTR(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

197

MMIO_D(DSPADDR(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

198

MMIO_D(DSPSTRIDE(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

199

MMIO_D(DSPPOS(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

200

MMIO_D(DSPSIZE(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

201

MMIO_D(DSPSURF(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

202

MMIO_D(DSPOFFSET(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

203

MMIO_D(DSPSURFLIVE(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

244

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

245

MMIO_D(TRANS_HBLANK(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

246

MMIO_D(TRANS_HSYNC(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

247

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

248

MMIO_D(TRANS_VBLANK(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

249

MMIO_D(TRANS_VSYNC(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

250

MMIO_D(BCLRPAT(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

251

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

252

MMIO_D(PIPESRC(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

253

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

254

MMIO_D(TRANS_HBLANK(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

255

MMIO_D(TRANS_HSYNC(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

256

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

257

MMIO_D(TRANS_VBLANK(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

258

MMIO_D(TRANS_VSYNC(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

259

MMIO_D(BCLRPAT(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

260

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

261

MMIO_D(PIPESRC(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

262

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

263

MMIO_D(TRANS_HBLANK(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

264

MMIO_D(TRANS_HSYNC(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

265

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

266

MMIO_D(TRANS_VBLANK(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

267

MMIO_D(TRANS_VSYNC(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

268

MMIO_D(BCLRPAT(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

269

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

270

MMIO_D(PIPESRC(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

271

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

272

MMIO_D(TRANS_HBLANK(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

273

MMIO_D(TRANS_HSYNC(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

274

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

275

MMIO_D(TRANS_VBLANK(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

276

MMIO_D(TRANS_VSYNC(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

277

MMIO_D(BCLRPAT(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

278

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

279

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

280

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

281

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

282

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

283

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

284

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

285

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

286

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

287

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

288

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

289

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

290

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

291

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

292

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

293

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

294

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

295

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

296

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

297

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

298

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

299

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

300

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

301

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

302

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

303

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

304

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

305

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

306

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

307

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

308

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

309

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

310

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_EDP));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

519

MMIO_D(TRANS_MULT(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

520

MMIO_D(TRANS_MULT(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

521

MMIO_D(TRANS_MULT(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

522

MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

523

MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

524

MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

67

struct intel_display *display = dev_priv->display;

drivers/gpu/drm/i915/intel_uncore.c

2506

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/intel_uncore.c

2541

if (HAS_FPGA_DBG_UNCLAIMED(display))

drivers/gpu/drm/i915/selftests/intel_uncore.c

281

struct intel_display *display = i915->display;

drivers/gpu/drm/i915/selftests/intel_uncore.c

286

if (!HAS_FPGA_DBG_UNCLAIMED(display) &&

drivers/gpu/drm/i915/selftests/mock_gem_device.c

147

struct intel_display *display;

drivers/gpu/drm/i915/selftests/mock_gem_device.c

188

display = intel_display_device_probe(pdev, i915_driver_parent_interface());

drivers/gpu/drm/i915/selftests/mock_gem_device.c

189

if (IS_ERR(display))

drivers/gpu/drm/i915/selftests/mock_gem_device.c

192

i915->display = display;

drivers/gpu/drm/i915/selftests/mock_gem_device.c

279

intel_display_device_remove(i915->display);

drivers/gpu/drm/meson/meson_dw_hdmi.c

359

const struct drm_display_info *display,

drivers/gpu/drm/meson/meson_dw_hdmi.c

363

bool is_hdmi2_sink = display->hdmi.scdc.supported;

drivers/gpu/drm/meson/meson_dw_hdmi.c

372

if (drm_mode_is_420_only(display, mode) ||

drivers/gpu/drm/meson/meson_dw_hdmi.c

373

(!is_hdmi2_sink && drm_mode_is_420_also(display, mode)) ||

drivers/gpu/drm/meson/meson_dw_hdmi.c

401

dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);

drivers/gpu/drm/msm/dp/dp_display.c

1310

static int msm_dp_display_get_io(struct msm_dp_display_private *display)

drivers/gpu/drm/msm/dp/dp_display.c

1312

struct platform_device *pdev = display->msm_dp_display.pdev;

drivers/gpu/drm/msm/dp/dp_display.c

1314

display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len);

drivers/gpu/drm/msm/dp/dp_display.c

1315

if (IS_ERR(display->ahb_base))

drivers/gpu/drm/msm/dp/dp_display.c

1316

return PTR_ERR(display->ahb_base);

drivers/gpu/drm/msm/dp/dp_display.c

1318

display->aux_base = msm_dp_ioremap(pdev, 1, &display->aux_len);

drivers/gpu/drm/msm/dp/dp_display.c

1319

if (IS_ERR(display->aux_base)) {

drivers/gpu/drm/msm/dp/dp_display.c

1320

if (display->aux_base != ERR_PTR(-EINVAL)) {

drivers/gpu/drm/msm/dp/dp_display.c

1321

DRM_ERROR("unable to remap aux region: %pe\n", display->aux_base);

drivers/gpu/drm/msm/dp/dp_display.c

1322

return PTR_ERR(display->aux_base);

drivers/gpu/drm/msm/dp/dp_display.c

1332

if (display->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) {

drivers/gpu/drm/msm/dp/dp_display.c

1337

display->ahb_len = DP_DEFAULT_AHB_SIZE;

drivers/gpu/drm/msm/dp/dp_display.c

1338

display->aux_base = display->ahb_base + DP_DEFAULT_AUX_OFFSET;

drivers/gpu/drm/msm/dp/dp_display.c

1339

display->aux_len = DP_DEFAULT_AUX_SIZE;

drivers/gpu/drm/msm/dp/dp_display.c

1340

display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET;

drivers/gpu/drm/msm/dp/dp_display.c

1341

display->link_len = DP_DEFAULT_LINK_SIZE;

drivers/gpu/drm/msm/dp/dp_display.c

1342

display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET;

drivers/gpu/drm/msm/dp/dp_display.c

1343

display->p0_len = DP_DEFAULT_P0_SIZE;

drivers/gpu/drm/msm/dp/dp_display.c

1348

display->link_base = msm_dp_ioremap(pdev, 2, &display->link_len);

drivers/gpu/drm/msm/dp/dp_display.c

1349

if (IS_ERR(display->link_base)) {

drivers/gpu/drm/msm/dp/dp_display.c

1350

DRM_ERROR("unable to remap link region: %pe\n", display->link_base);

drivers/gpu/drm/msm/dp/dp_display.c

1351

return PTR_ERR(display->link_base);

drivers/gpu/drm/msm/dp/dp_display.c

1354

display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len);

drivers/gpu/drm/msm/dp/dp_display.c

1355

if (IS_ERR(display->p0_base)) {

drivers/gpu/drm/msm/dp/dp_display.c

1356

DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base);

drivers/gpu/drm/msm/dp/dp_display.c

1357

return PTR_ERR(display->p0_base);

drivers/gpu/drm/nouveau/dispnv50/disp.c

237

struct nvif_object *disp = &drm->display->disp.object;

drivers/gpu/drm/nouveau/nouveau_bios.c

1029

parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));

drivers/gpu/drm/nouveau/nouveau_display.c

649

disp = drm->display = kzalloc_obj(*disp);

drivers/gpu/drm/nouveau/nouveau_display.c

759

drm->display = NULL;

drivers/gpu/drm/nouveau/nouveau_display.h

45

return nouveau_drm(dev)->display;

drivers/gpu/drm/nouveau/nouveau_drv.h

287

struct nouveau_display *display;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

282

nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

302

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

319

if (!mps && display)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

326

u32 ustatus_new, int display, const char *name)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

348

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

365

nv50_gr_mp_trap(gr, i, display);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

368

if (ustatus && display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

377

if (display)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

384

if (display)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

390

if (!tps && display)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

395

nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

404

if (!status && display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

414

if (!ustatus && display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

431

if (display && (addr & 0x80000000)) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

439

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

457

if (display && (addr & 0x80000000)) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

464

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

472

if (ustatus && display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

487

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

510

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

530

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

553

if (display) {

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

579

if (display)

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

587

nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

595

nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

604

nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display,

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

611

if (display)

drivers/gpu/drm/radeon/atombios_encoders.c

2538

if (rdev->asic->display.hdmi_enable)

drivers/gpu/drm/radeon/radeon.h

1899

} display;

drivers/gpu/drm/radeon/radeon.h

2720

#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))

drivers/gpu/drm/radeon/radeon.h

2721

#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))

drivers/gpu/drm/radeon/radeon.h

2722

#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))

drivers/gpu/drm/radeon/radeon.h

2723

#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))

drivers/gpu/drm/radeon/radeon.h

2724

#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))

drivers/gpu/drm/radeon/radeon.h

2745

#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))

drivers/gpu/drm/radeon/radeon.h

2758

#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))

drivers/gpu/drm/radeon/radeon_asic.c

1043

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1136

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1242

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1362

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1456

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1550

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1698

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1818

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

1956

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

2126

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

220

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

2239

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

2364

rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;

drivers/gpu/drm/radeon/radeon_asic.c

288

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

384

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

452

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

520

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

588

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

656

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

724

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

792

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

860

.display = {

drivers/gpu/drm/radeon/radeon_asic.c

957

.display = {

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

334

const struct drm_display_info *display,

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

339

dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

320

struct drm_display_info *display;

drivers/gpu/drm/rockchip/rk3066_hdmi.c

335

display = &connector->display_info;

drivers/gpu/drm/rockchip/rk3066_hdmi.c

370

if (display->is_hdmi) {

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

169

if (display->is_hdmi)

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

99

struct drm_display_info *display = &connector->display_info;

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

143

const struct drm_display_info *display,

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

229

const struct drm_display_info *display,

drivers/gpu/drm/vboxvideo/modesetting.c

29

void hgsmi_process_display_info(struct gen_pool *ctx, u32 display,

drivers/gpu/drm/vboxvideo/modesetting.c

41

p->view_index = display;

drivers/gpu/drm/vboxvideo/vboxvideo.h

408

u32 display;

drivers/gpu/drm/vboxvideo/vboxvideo_guest.h

50

void hgsmi_process_display_info(struct gen_pool *ctx, u32 display,

drivers/gpu/drm/vc4/vc4_hdmi.c

120

struct drm_display_info *display = &vc4_hdmi->connector.display_info;

drivers/gpu/drm/vc4/vc4_hdmi.c

124

if (!display->is_hdmi)

drivers/gpu/drm/vc4/vc4_hdmi.c

127

if (!display->hdmi.scdc.supported ||

drivers/gpu/drm/vc4/vc4_hdmi.c

128

!display->hdmi.scdc.scrambling.supported)

drivers/gpu/drm/vc4/vc4_hdmi.c

1626

struct drm_display_info *display = &vc4_hdmi->connector.display_info;

drivers/gpu/drm/vc4/vc4_hdmi.c

1654

if (display->is_hdmi) {

drivers/gpu/drm/vc4/vc4_hdmi.c

1681

if (display->is_hdmi) {

drivers/gpu/drm/vc4/vc4_hdmi.c

1961

struct drm_display_info *display = &vc4_hdmi->connector.display_info;

drivers/gpu/drm/vc4/vc4_hdmi.c

1969

if (!display->is_hdmi)

drivers/gpu/drm/xe/display/xe_display.c

102

intel_hpd_cancel_work(display);

drivers/gpu/drm/xe/display/xe_display.c

103

intel_display_driver_remove_nogem(display);

drivers/gpu/drm/xe/display/xe_display.c

104

intel_display_driver_remove_noirq(display);

drivers/gpu/drm/xe/display/xe_display.c

105

intel_opregion_cleanup(display);

drivers/gpu/drm/xe/display/xe_display.c

106

intel_power_domains_cleanup(display);

drivers/gpu/drm/xe/display/xe_display.c

111

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

120

intel_display_driver_early_probe(display);

drivers/gpu/drm/xe/display/xe_display.c

123

intel_opregion_setup(display);

drivers/gpu/drm/xe/display/xe_display.c

129

err = intel_dram_detect(display);

drivers/gpu/drm/xe/display/xe_display.c

133

intel_bw_init_hw(display);

drivers/gpu/drm/xe/display/xe_display.c

135

intel_display_device_info_runtime_init(display);

drivers/gpu/drm/xe/display/xe_display.c

137

err = intel_display_driver_probe_noirq(display);

drivers/gpu/drm/xe/display/xe_display.c

141

err = intel_display_driver_probe_nogem(display);

drivers/gpu/drm/xe/display/xe_display.c

147

intel_display_driver_remove_noirq(display);

drivers/gpu/drm/xe/display/xe_display.c

148

intel_power_domains_cleanup(display);

drivers/gpu/drm/xe/display/xe_display.c

150

intel_opregion_cleanup(display);

drivers/gpu/drm/xe/display/xe_display.c

157

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

159

intel_hpd_poll_fini(display);

drivers/gpu/drm/xe/display/xe_display.c

160

intel_hdcp_component_fini(display);

drivers/gpu/drm/xe/display/xe_display.c

161

intel_audio_deinit(display);

drivers/gpu/drm/xe/display/xe_display.c

162

intel_display_driver_remove(display);

drivers/gpu/drm/xe/display/xe_display.c

167

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

173

err = intel_display_driver_probe(display);

drivers/gpu/drm/xe/display/xe_display.c

182

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

187

intel_display_driver_register(display);

drivers/gpu/drm/xe/display/xe_display.c

188

intel_power_domains_enable(display);

drivers/gpu/drm/xe/display/xe_display.c

193

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

198

intel_power_domains_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

199

intel_display_driver_unregister(display);

drivers/gpu/drm/xe/display/xe_display.c

206

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

212

gen11_display_irq_handler(display);

drivers/gpu/drm/xe/display/xe_display.c

217

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

223

intel_opregion_asle_intr(display);

drivers/gpu/drm/xe/display/xe_display.c

228

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

233

gen11_display_irq_reset(display);

drivers/gpu/drm/xe/display/xe_display.c

238

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

243

gen11_de_irq_postinstall(display);

drivers/gpu/drm/xe/display/xe_display.c

278

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

287

intel_power_domains_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

291

intel_opregion_suspend(display, PCI_D3cold);

drivers/gpu/drm/xe/display/xe_display.c

293

intel_dmc_suspend(display);

drivers/gpu/drm/xe/display/xe_display.c

295

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

296

intel_hpd_poll_enable(display);

drivers/gpu/drm/xe/display/xe_display.c

301

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

306

intel_dmc_resume(display);

drivers/gpu/drm/xe/display/xe_display.c

308

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

311

intel_display_driver_init_hw(display);

drivers/gpu/drm/xe/display/xe_display.c

313

intel_hpd_init(display);

drivers/gpu/drm/xe/display/xe_display.c

315

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

316

intel_hpd_poll_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

318

intel_opregion_resume(display);

drivers/gpu/drm/xe/display/xe_display.c

320

intel_power_domains_enable(display);

drivers/gpu/drm/xe/display/xe_display.c

325

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

335

intel_power_domains_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

338

if (intel_display_device_present(display)) {

drivers/gpu/drm/xe/display/xe_display.c

340

intel_display_driver_disable_user_access(display);

drivers/gpu/drm/xe/display/xe_display.c

341

intel_display_driver_suspend(display);

drivers/gpu/drm/xe/display/xe_display.c

346

intel_encoder_block_all_hpds(display);

drivers/gpu/drm/xe/display/xe_display.c

348

intel_hpd_cancel_work(display);

drivers/gpu/drm/xe/display/xe_display.c

350

if (intel_display_device_present(display)) {

drivers/gpu/drm/xe/display/xe_display.c

351

intel_display_driver_suspend_access(display);

drivers/gpu/drm/xe/display/xe_display.c

352

intel_encoder_suspend_all(display);

drivers/gpu/drm/xe/display/xe_display.c

355

intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);

drivers/gpu/drm/xe/display/xe_display.c

357

intel_dmc_suspend(display);

drivers/gpu/drm/xe/display/xe_display.c

362

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

367

intel_power_domains_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

370

if (intel_display_device_present(display)) {

drivers/gpu/drm/xe/display/xe_display.c

372

intel_display_driver_disable_user_access(display);

drivers/gpu/drm/xe/display/xe_display.c

373

intel_display_driver_suspend(display);

drivers/gpu/drm/xe/display/xe_display.c

377

intel_dp_mst_suspend(display);

drivers/gpu/drm/xe/display/xe_display.c

378

intel_encoder_block_all_hpds(display);

drivers/gpu/drm/xe/display/xe_display.c

379

intel_hpd_cancel_work(display);

drivers/gpu/drm/xe/display/xe_display.c

381

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

382

intel_display_driver_suspend_access(display);

drivers/gpu/drm/xe/display/xe_display.c

384

intel_encoder_suspend_all(display);

drivers/gpu/drm/xe/display/xe_display.c

385

intel_encoder_shutdown_all(display);

drivers/gpu/drm/xe/display/xe_display.c

387

intel_opregion_suspend(display, PCI_D3cold);

drivers/gpu/drm/xe/display/xe_display.c

389

intel_dmc_suspend(display);

drivers/gpu/drm/xe/display/xe_display.c

394

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

404

intel_hpd_poll_enable(display);

drivers/gpu/drm/xe/display/xe_display.c

409

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

415

intel_display_power_suspend_late(display, s2idle);

drivers/gpu/drm/xe/display/xe_display.c

420

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

433

intel_dmc_wl_flush_release_work(display);

drivers/gpu/drm/xe/display/xe_display.c

438

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

448

intel_power_domains_driver_remove(display);

drivers/gpu/drm/xe/display/xe_display.c

453

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

458

intel_display_power_resume_early(display);

drivers/gpu/drm/xe/display/xe_display.c

46

INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct xe_device, drm, display);

drivers/gpu/drm/xe/display/xe_display.c

463

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

468

intel_dmc_resume(display);

drivers/gpu/drm/xe/display/xe_display.c

470

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

473

intel_display_driver_init_hw(display);

drivers/gpu/drm/xe/display/xe_display.c

475

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

476

intel_display_driver_resume_access(display);

drivers/gpu/drm/xe/display/xe_display.c

478

intel_hpd_init(display);

drivers/gpu/drm/xe/display/xe_display.c

480

intel_encoder_unblock_all_hpds(display);

drivers/gpu/drm/xe/display/xe_display.c

482

if (intel_display_device_present(display)) {

drivers/gpu/drm/xe/display/xe_display.c

483

intel_display_driver_resume(display);

drivers/gpu/drm/xe/display/xe_display.c

485

intel_display_driver_enable_user_access(display);

drivers/gpu/drm/xe/display/xe_display.c

488

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

489

intel_hpd_poll_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

491

intel_opregion_resume(display);

drivers/gpu/drm/xe/display/xe_display.c

495

intel_power_domains_enable(display);

drivers/gpu/drm/xe/display/xe_display.c

500

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display.c

510

intel_hpd_init(display);

drivers/gpu/drm/xe/display/xe_display.c

511

intel_hpd_poll_disable(display);

drivers/gpu/drm/xe/display/xe_display.c

512

skl_watermark_ipc_update(display);

drivers/gpu/drm/xe/display/xe_display.c

518

struct intel_display *display = arg;

drivers/gpu/drm/xe/display/xe_display.c

520

intel_display_device_remove(display);

drivers/gpu/drm/xe/display/xe_display.c

563

struct intel_display *display;

drivers/gpu/drm/xe/display/xe_display.c

569

display = intel_display_device_probe(pdev, &parent);

drivers/gpu/drm/xe/display/xe_display.c

570

if (IS_ERR(display))

drivers/gpu/drm/xe/display/xe_display.c

571

return PTR_ERR(display);

drivers/gpu/drm/xe/display/xe_display.c

573

err = drmm_add_action_or_reset(&xe->drm, display_device_remove, display);

drivers/gpu/drm/xe/display/xe_display.c

577

xe->display = display;

drivers/gpu/drm/xe/display/xe_display.c

579

if (intel_display_device_present(display))

drivers/gpu/drm/xe/display/xe_display.c

97

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_display_wa.c

13

bool intel_display_needs_wa_16023588340(struct intel_display *display)

drivers/gpu/drm/xe/display/xe_display_wa.c

15

struct xe_device *xe = to_xe_device(display->drm);

drivers/gpu/drm/xe/display/xe_fb_pin.c

390

struct intel_display *display = xe->display;

drivers/gpu/drm/xe/display/xe_fb_pin.c

401

if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {

drivers/gpu/drm/xe/display/xe_fb_pin.c

402

vma = intel_fbdev_vma_pointer(display->fbdev.fbdev);

drivers/gpu/drm/xe/display/xe_tdf.c

10

void intel_td_flush(struct intel_display *display)

drivers/gpu/drm/xe/display/xe_tdf.c

12

struct xe_device *xe = to_xe_device(display->drm);

drivers/gpu/drm/xe/xe_device_types.h

265

struct intel_display *display;

drivers/media/pci/ivtv/ivtv-yuv.c

953

int draw, display;

drivers/media/pci/ivtv/ivtv-yuv.c

960

display = atomic_read(&yi->next_dma_frame);

drivers/media/pci/ivtv/ivtv-yuv.c

962

if (display > draw)

drivers/media/pci/ivtv/ivtv-yuv.c

963

display -= IVTV_YUV_BUFFERS;

drivers/media/pci/ivtv/ivtv-yuv.c

965

if (draw - display >= yi->max_frames_buffered)

drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

1295

vpu_buf->display = false;

drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

431

dst_vpu_buf->display = true;

drivers/media/platform/chips-media/wave5/wave5-vpu.h

31

bool display;

drivers/media/platform/ti/davinci/vpif.c

48

struct platform_device *display;

drivers/media/platform/ti/davinci/vpif.c

524

data->display = pdev_display;

drivers/media/platform/ti/davinci/vpif.c

548

if (data->display)

drivers/media/platform/ti/davinci/vpif.c

549

platform_device_unregister(data->display);

drivers/media/platform/ti/omap/omap_vout.c

1312

struct omap_dss_device *display = ovl->get_device(ovl);

drivers/media/platform/ti/omap/omap_vout.c

1332

vout->fbuf.fmt.width = display->panel.timings.x_res;

drivers/media/platform/ti/omap/omap_vout.c

1333

vout->fbuf.fmt.height = display->panel.timings.y_res;

drivers/media/platform/ti/omap/omap_vout.c

1688

struct omap_dss_device *display = vid_dev->displays[i];

drivers/media/platform/ti/omap/omap_vout.c

1690

if (display->driver->update)

drivers/media/platform/ti/omap/omap_vout.c

1691

display->driver->update(display, 0, 0,

drivers/media/platform/ti/omap/omap_vout.c

1692

display->panel.timings.x_res,

drivers/media/platform/ti/omap/omap_vout.c

1693

display->panel.timings.y_res);

drivers/net/wireless/intel/iwlegacy/3945.h

181

bool display);

drivers/net/wireless/intel/iwlegacy/4965-mac.c

1207

il4965_dump_fh(struct il_priv *il, char **buf, bool display)

drivers/net/wireless/intel/iwlegacy/4965-mac.c

1226

if (display) {

drivers/net/wireless/intel/iwlegacy/4965.h

43

int il4965_dump_fh(struct il_priv *il, char **buf, bool display);

drivers/net/wireless/intel/iwlegacy/common.h

1558

int (*dump_fh) (struct il_priv *il, char **buf, bool display);

drivers/pinctrl/pinconf-generic.c

152

seq_printf(s, "%s: 0x%x", conf_items[i].display,

drivers/pinctrl/pinconf-generic.c

165

pctldev->desc->custom_conf_items[i].display,

drivers/pinctrl/pinconf-generic.c

92

seq_puts(s, item->display);

drivers/platform/x86/asus-laptop.c

1129

static DEVICE_ATTR_WO(display);

drivers/platform/x86/hp/hp-wmi.c

1082

static DEVICE_ATTR_RO(display);

drivers/staging/fbtft/fb_agm1264k-fl.c

420

static struct fbtft_display display = {

drivers/staging/fbtft/fb_agm1264k-fl.c

436

FBTFT_REGISTER_DRIVER(DRVNAME, "displaytronic,fb_agm1264k-fl", &display);

drivers/staging/fbtft/fb_bd663474.c

150

static struct fbtft_display display = {

drivers/staging/fbtft/fb_bd663474.c

162

FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display);

drivers/staging/fbtft/fb_hx8340bn.c

200

static struct fbtft_display display = {

drivers/staging/fbtft/fb_hx8340bn.c

216

FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8340bn", &display);

drivers/staging/fbtft/fb_hx8347d.c

159

static struct fbtft_display display = {

drivers/staging/fbtft/fb_hx8347d.c

174

FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8347d", &display);

drivers/staging/fbtft/fb_hx8353d.c

124

static struct fbtft_display display = {

drivers/staging/fbtft/fb_hx8353d.c

139

FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8353d", &display);

drivers/staging/fbtft/fb_hx8357d.c

179

static struct fbtft_display display = {

drivers/staging/fbtft/fb_hx8357d.c

192

FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8357d", &display);

drivers/staging/fbtft/fb_ili9163.c

230

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9163.c

251

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9163", &display);

drivers/staging/fbtft/fb_ili9320.c

241

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9320.c

256

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);

drivers/staging/fbtft/fb_ili9325.c

235

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9325.c

252

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display);

drivers/staging/fbtft/fb_ili9340.c

119

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9340.c

130

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9340", &display);

drivers/staging/fbtft/fb_ili9341.c

132

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9341.c

148

FBTFT_REGISTER_SPI_DRIVER(DRVNAME, "ilitek", "ili9341", &display);

drivers/staging/fbtft/fb_ili9481.c

83

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9481.c

94

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9481", &display);

drivers/staging/fbtft/fb_ili9486.c

83

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ili9486.c

94

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9486", &display);

drivers/staging/fbtft/fb_pcd8544.c

143

static struct fbtft_display display = {

drivers/staging/fbtft/fb_pcd8544.c

160

FBTFT_REGISTER_DRIVER(DRVNAME, "philips,pcd8544", &display);

drivers/staging/fbtft/fb_ra8875.c

278

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ra8875.c

289

FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);

drivers/staging/fbtft/fb_s6d02a1.c

146

static struct fbtft_display display = {

drivers/staging/fbtft/fb_s6d02a1.c

157

FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d02a1", &display);

drivers/staging/fbtft/fb_s6d1121.c

156

static struct fbtft_display display = {

drivers/staging/fbtft/fb_s6d1121.c

173

FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d1121", &display);

drivers/staging/fbtft/fb_seps525.c

192

static struct fbtft_display display = {

drivers/staging/fbtft/fb_seps525.c

203

FBTFT_REGISTER_DRIVER(DRVNAME, "syncoam,seps525", &display);

drivers/staging/fbtft/fb_sh1106.c

154

static struct fbtft_display display = {

drivers/staging/fbtft/fb_sh1106.c

173

FBTFT_REGISTER_SPI_DRIVER(DRVNAME, "sinowealth", "sh1106", &display);

drivers/staging/fbtft/fb_ssd1289.c

152

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ssd1289.c

167

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1289", &display);

drivers/staging/fbtft/fb_ssd1305.c

181

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ssd1305.c

198

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1305", &display);

drivers/staging/fbtft/fb_ssd1306.c

200

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ssd1306.c

216

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1306", &display);

drivers/staging/fbtft/fb_ssd1325.c

159

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ssd1325.c

176

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1325", &display);

drivers/staging/fbtft/fb_ssd1331.c

177

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ssd1331.c

193

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1331", &display);

drivers/staging/fbtft/fb_ssd1351.c

174

static struct fbtft_display display = {

drivers/staging/fbtft/fb_ssd1351.c

231

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1351", &display);

drivers/staging/fbtft/fb_ssd1351.c

32

par->pdata->display.backlight == FBTFT_ONBOARD_BACKLIGHT) {

drivers/staging/fbtft/fb_st7735r.c

162

static struct fbtft_display display = {

drivers/staging/fbtft/fb_st7735r.c

177

FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7735r", &display);

drivers/staging/fbtft/fb_st7789v.c

244

switch (par->pdata->display.buswidth) {

drivers/staging/fbtft/fb_st7789v.c

256

par->pdata->display.buswidth);

drivers/staging/fbtft/fb_st7789v.c

369

static struct fbtft_display display = {

drivers/staging/fbtft/fb_st7789v.c

385

FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7789v", &display);

drivers/staging/fbtft/fb_tinylcd.c

85

static struct fbtft_display display = {

drivers/staging/fbtft/fb_tinylcd.c

96

FBTFT_REGISTER_DRIVER(DRVNAME, "neosec,tinylcd", &display);

drivers/staging/fbtft/fb_tls8204.c

136

static struct fbtft_display display = {

drivers/staging/fbtft/fb_tls8204.c

153

FBTFT_REGISTER_DRIVER(DRVNAME, "teralane,tls8204", &display);

drivers/staging/fbtft/fb_uc1611.c

227

switch (par->pdata->display.buswidth) {

drivers/staging/fbtft/fb_uc1611.c

299

par->pdata->display.buswidth);

drivers/staging/fbtft/fb_uc1611.c

309

static struct fbtft_display display = {

drivers/staging/fbtft/fb_uc1611.c

325

FBTFT_REGISTER_DRIVER(DRVNAME, "ultrachip,uc1611", &display);

drivers/staging/fbtft/fb_uc1701.c

151

static struct fbtft_display display = {

drivers/staging/fbtft/fb_uc1701.c

163

FBTFT_REGISTER_DRIVER(DRVNAME, "UltraChip,uc1701", &display);

drivers/staging/fbtft/fb_upd161704.c

164

static struct fbtft_display display = {

drivers/staging/fbtft/fb_upd161704.c

175

FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);

drivers/staging/fbtft/fbtft-core.c

1054

if (pdata->display.buswidth != 9 && par->startbyte == 0 &&

drivers/staging/fbtft/fbtft-core.c

1068

for (i = 0; i < pdata->display.buswidth; i++) {

drivers/staging/fbtft/fbtft-core.c

1105

pdata->display.width = fbtft_property_value(dev, "width");

drivers/staging/fbtft/fbtft-core.c

1106

pdata->display.height = fbtft_property_value(dev, "height");

drivers/staging/fbtft/fbtft-core.c

1107

pdata->display.regwidth = fbtft_property_value(dev, "regwidth");

drivers/staging/fbtft/fbtft-core.c

1108

pdata->display.buswidth = fbtft_property_value(dev, "buswidth");

drivers/staging/fbtft/fbtft-core.c

1109

pdata->display.backlight = fbtft_property_value(dev, "backlight");

drivers/staging/fbtft/fbtft-core.c

1110

pdata->display.bpp = fbtft_property_value(dev, "bpp");

drivers/staging/fbtft/fbtft-core.c

1111

pdata->display.debug = fbtft_property_value(dev, "debug");

drivers/staging/fbtft/fbtft-core.c

1120

pdata->display.backlight = 1;

drivers/staging/fbtft/fbtft-core.c

1122

pdata->display.fbtftops.init_display =

drivers/staging/fbtft/fbtft-core.c

1125

pdata->display.fbtftops.request_gpios = fbtft_request_gpios;

drivers/staging/fbtft/fbtft-core.c

1142

int fbtft_probe_common(struct fbtft_display *display,

drivers/staging/fbtft/fbtft-core.c

1164

info = fbtft_framebuffer_alloc(display, dev, pdata);

drivers/staging/fbtft/fbtft-core.c

1172

if (display->buswidth == 0) {

drivers/staging/fbtft/fbtft-core.c

1178

if (display->regwidth == 8 && display->buswidth == 8)

drivers/staging/fbtft/fbtft-core.c

1180

else if (display->regwidth == 8 && display->buswidth == 9 && par->spi)

drivers/staging/fbtft/fbtft-core.c

1182

else if (display->regwidth == 16 && display->buswidth == 8)

drivers/staging/fbtft/fbtft-core.c

1184

else if (display->regwidth == 16 && display->buswidth == 16)

drivers/staging/fbtft/fbtft-core.c

1189

display->regwidth, display->buswidth);

drivers/staging/fbtft/fbtft-core.c

1192

if (display->buswidth == 8)

drivers/staging/fbtft/fbtft-core.c

1194

else if (display->buswidth == 9)

drivers/staging/fbtft/fbtft-core.c

1196

else if (display->buswidth == 16)

drivers/staging/fbtft/fbtft-core.c

1201

if (display->buswidth == 8)

drivers/staging/fbtft/fbtft-core.c

1203

else if (display->buswidth == 16)

drivers/staging/fbtft/fbtft-core.c

1208

if (par->spi && display->buswidth == 9) {

drivers/staging/fbtft/fbtft-core.c

1231

fbtft_merge_fbtftops(&par->fbtftops, &display->fbtftops);

drivers/staging/fbtft/fbtft-core.c

1238

fbtft_merge_fbtftops(&par->fbtftops, &pdata->display.fbtftops);

drivers/staging/fbtft/fbtft-core.c

495

struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,

drivers/staging/fbtft/fbtft-core.c

507

int txbuflen = display->txbuflen;

drivers/staging/fbtft/fbtft-core.c

508

unsigned int bpp = display->bpp;

drivers/staging/fbtft/fbtft-core.c

509

unsigned int fps = display->fps;

drivers/staging/fbtft/fbtft-core.c

511

const s16 *init_sequence = display->init_sequence;

drivers/staging/fbtft/fbtft-core.c

512

char *gamma = display->gamma;

drivers/staging/fbtft/fbtft-core.c

516

if (display->gamma_num * display->gamma_len >

drivers/staging/fbtft/fbtft-core.c

539

if (pdata->display.init_sequence)

drivers/staging/fbtft/fbtft-core.c

540

init_sequence = pdata->display.init_sequence;

drivers/staging/fbtft/fbtft-core.c

543

if (pdata->display.debug)

drivers/staging/fbtft/fbtft-core.c

544

display->debug = pdata->display.debug;

drivers/staging/fbtft/fbtft-core.c

545

if (pdata->display.backlight)

drivers/staging/fbtft/fbtft-core.c

546

display->backlight = pdata->display.backlight;

drivers/staging/fbtft/fbtft-core.c

547

if (pdata->display.width)

drivers/staging/fbtft/fbtft-core.c

548

display->width = pdata->display.width;

drivers/staging/fbtft/fbtft-core.c

549

if (pdata->display.height)

drivers/staging/fbtft/fbtft-core.c

550

display->height = pdata->display.height;

drivers/staging/fbtft/fbtft-core.c

551

if (pdata->display.buswidth)

drivers/staging/fbtft/fbtft-core.c

552

display->buswidth = pdata->display.buswidth;

drivers/staging/fbtft/fbtft-core.c

553

if (pdata->display.regwidth)

drivers/staging/fbtft/fbtft-core.c

554

display->regwidth = pdata->display.regwidth;

drivers/staging/fbtft/fbtft-core.c

556

display->debug |= debug;

drivers/staging/fbtft/fbtft-core.c

557

fbtft_expand_debug_value(&display->debug);

drivers/staging/fbtft/fbtft-core.c

562

width = display->height;

drivers/staging/fbtft/fbtft-core.c

563

height = display->width;

drivers/staging/fbtft/fbtft-core.c

566

width = display->width;

drivers/staging/fbtft/fbtft-core.c

567

height = display->height;

drivers/staging/fbtft/fbtft-core.c

578

if (display->gamma_num && display->gamma_len) {

drivers/staging/fbtft/fbtft-core.c

580

display->gamma_num *

drivers/staging/fbtft/fbtft-core.c

581

display->gamma_len,

drivers/staging/fbtft/fbtft-core.c

592

vmem_size = display->width * display->height * bpp / 8;

drivers/staging/fbtft/fbtft-core.c

640

par->debug = display->debug;

drivers/staging/fbtft/fbtft-core.c

647

par->gamma.num_curves = display->gamma_num;

drivers/staging/fbtft/fbtft-core.c

648

par->gamma.num_values = display->gamma_len;

drivers/staging/fbtft/fbtft-core.c

686

if (display->backlight)

drivers/staging/fbtft/fbtft-core.c

690

fbtft_merge_fbtftops(&par->fbtftops, &display->fbtftops);

drivers/staging/fbtft/fbtft.h

136

struct fbtft_display display;

drivers/staging/fbtft/fbtft.h

246

struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,

drivers/staging/fbtft/fbtft.h

255

int fbtft_probe_common(struct fbtft_display *display, struct spi_device *sdev,

drivers/staging/fbtft/fbtft.h

428

(((struct fbtft_platform_data *)(dev)->platform_data)->display.debug & DEBUG_DRIVER_INIT_FUNCTIONS))) \

drivers/video/fbdev/cirrusfb.c

1905

unsigned long *display, unsigned long *registers)

drivers/video/fbdev/cirrusfb.c

1908

assert(display != NULL);

drivers/video/fbdev/cirrusfb.c

1911

*display = 0;

drivers/video/fbdev/cirrusfb.c

1917

*display = pci_resource_start(pdev, 1);

drivers/video/fbdev/cirrusfb.c

1920

*display = pci_resource_start(pdev, 0);

drivers/video/fbdev/cirrusfb.c

1924

assert(*display != 0);

drivers/video/fbdev/neofb.c

1767

unsigned char type, display;

drivers/video/fbdev/neofb.c

1779

display = vga_rgfx(NULL, 0x20);

drivers/video/fbdev/neofb.c

1781

par->internal_display = display & 2 || !(display & 3) ? 1 : 0;

drivers/video/fbdev/neofb.c

1782

par->external_display = display & 1;

drivers/video/fbdev/omap2/omapfb/dss/manager-sysfs.c

427

static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

205

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

215

if (display && display->driver->sync)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

216

display->driver->sync(display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

280

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

283

if (!display)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

289

display->driver->get_resolution(display, &dw, &dh);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

294

return display->driver->update(display, x, y, w, h);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

300

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

306

if (!display)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

314

d = get_display_data(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

323

if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

325

omapfb_start_auto_update(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

327

omapfb_stop_auto_update(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

343

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

348

if (!display)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

353

d = get_display_data(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

477

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

481

if (!display || !display->driver->memory_read)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

496

r = display->driver->memory_read(display, buf, mr->buffer_size,

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

575

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

602

if (!display || !display->driver->sync) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

608

r = display->driver->sync(display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

613

if (!display || !display->driver->update) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

631

if (!display || !display->driver->update) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

686

if (!display) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

692

if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

694

if (display->caps & OMAP_DSS_DISPLAY_CAP_TEAR_ELIM)

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

767

if (!display) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

772

mgr = omapdss_find_mgr_from_display(display);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

783

if (!display) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

799

if (!display || !display->driver->run_test) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

804

r = display->driver->run_test(display, p.test_num);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

814

if (!display || !display->driver->run_test) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

819

r = display->driver->run_test(display, p.test_num);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

862

if (!display || !display->driver->enable_te) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

867

r = display->driver->enable_te(display,

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

878

if (display == NULL) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

883

display->driver->get_resolution(display, &xres, &yres);

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

888

if (display->driver->get_dimensions) {

drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c

890

display->driver->get_dimensions(display, &w, &h);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1219

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1223

if (!display)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1228

d = get_display_data(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1232

if (display->state == OMAP_DSS_DISPLAY_ACTIVE)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1235

r = display->driver->enable(display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1237

if ((display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) &&

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1240

omapfb_start_auto_update(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1250

if (display->state != OMAP_DSS_DISPLAY_ACTIVE)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1254

omapfb_stop_auto_update(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1256

display->driver->disable(display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1422

struct omap_dss_device *display;

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1425

display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1427

if (!display)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1430

switch (omapfb_get_recommended_bpp(fbdev, display)) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1445

display->driver->get_resolution(display, &w, &h);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1688

struct omap_dss_device *display)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1706

d = get_display_data(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1716

struct omap_dss_device *display)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1720

d = get_display_data(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1731

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1748

if (display) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1752

display->driver->get_resolution(display, &w, &h);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1767

switch (omapfb_get_recommended_bpp(fbdev, display)) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

1998

struct omap_dss_device *display,

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2052

if (display->driver->get_timings) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2053

display->driver->get_timings(display, timings);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2099

struct omap_dss_device *display, char *mode_str)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2106

r = omapfb_mode_to_timings(mode_str, display, &timings, &bpp);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2110

d = get_display_data(fbdev, display);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2113

if (display->driver->check_timings) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2114

r = display->driver->check_timings(display, &timings);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2119

if (display->driver->get_timings) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2120

display->driver->get_timings(display, &temp_timings);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2128

if (display->driver->set_timings)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2129

display->driver->set_timings(display, &timings);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2161

struct omap_dss_device *display;

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2174

display = NULL;

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2178

display = fbdev->displays[i].dssdev;

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2183

if (!display) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2188

r = omapfb_set_def_mode(fbdev, display, mode_str);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2199

struct omap_dss_device *display,

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2202

if (display->driver->get_timings) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2203

display->driver->get_timings(display, t);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2228

static int omapfb_find_best_mode(struct omap_dss_device *display,

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2235

if (!display->driver->read_edid)

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2243

r = display->driver->read_edid(display, edid, len);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2274

fb_videomode_to_omap_timings(m, display, &t);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2276

r = display->driver->check_timings(display, &t);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

2288

fb_videomode_to_omap_timings(&specs->modedb[best_idx], display,

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

657

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

698

if (display && display->driver->get_dimensions) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

700

display->driver->get_dimensions(display, &w, &h);

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

710

if (display && display->driver->get_timings) {

drivers/video/fbdev/omap2/omapfb/omapfb-main.c

712

display->driver->get_timings(display, &timings);

drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c

428

struct omap_dss_device *display = fb2display(fbi);

drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c

442

if (display && display->driver->sync)

drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c

443

display->driver->sync(display);

drivers/video/fbdev/omap2/omapfb/omapfb.h

127

struct omap_dss_device *display);

drivers/video/fbdev/omap2/omapfb/omapfb.h

129

struct omap_dss_device *display);

drivers/video/fbdev/pxafb.c

2158

struct device_node *display, *np;

drivers/video/fbdev/pxafb.c

2174

display = of_graph_get_remote_port_parent(np);

drivers/video/fbdev/pxafb.c

2176

if (!display) {

drivers/video/fbdev/pxafb.c

2181

ret = of_get_pxafb_display(dev, display, info, bus_width);

drivers/video/fbdev/pxafb.c

2182

of_node_put(display);

drivers/video/fbdev/s1d13xxxfb.c

206

if ((s1dfb->display & 0x01)) /* LCD */

drivers/video/fbdev/s1d13xxxfb.c

237

if ((s1dfb->display & 0x01)) /* LCD */

drivers/video/fbdev/s1d13xxxfb.c

337

if ((par->display & 0x01) != 0)

drivers/video/fbdev/s1d13xxxfb.c

339

if ((par->display & 0x02) != 0)

drivers/video/fbdev/s1d13xxxfb.c

382

if ((par->display & 0x01)) {

drivers/video/fbdev/s1d13xxxfb.c

646

u8 panel, display;

drivers/video/fbdev/s1d13xxxfb.c

657

par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);

drivers/video/fbdev/s1d13xxxfb.c

658

crt_enabled = (par->display & 0x02) != 0;

drivers/video/fbdev/s1d13xxxfb.c

659

lcd_enabled = (par->display & 0x01) != 0;

drivers/video/fbdev/s1d13xxxfb.c

665

display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);

drivers/video/fbdev/s1d13xxxfb.c

667

display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);

drivers/video/fbdev/s1d13xxxfb.c

669

bpp = display & 0x07;

drivers/video/fbdev/s1d13xxxfb.c

990

if ((s1dfb->display & 0x01) != 0)

drivers/video/fbdev/s1d13xxxfb.c

992

if ((s1dfb->display & 0x02) != 0)

drivers/video/fbdev/sh_mobile_lcdcfb.c

1761

if (fb_mode_is_equal(&ch->display.mode, &mode))

drivers/video/fbdev/sh_mobile_lcdcfb.c

1766

fb_videomode_to_var(&var, &ch->display.mode);

drivers/video/fbdev/sh_mobile_lcdcfb.c

1767

var.width = ch->display.width;

drivers/video/fbdev/sh_mobile_lcdcfb.c

1768

var.height = ch->display.height;

drivers/video/fbdev/sh_mobile_lcdcfb.c

2097

var->width = ch->display.width;

drivers/video/fbdev/sh_mobile_lcdcfb.c

2098

var->height = ch->display.height;

drivers/video/fbdev/sh_mobile_lcdcfb.c

2466

ch->display.width = cfg->panel_cfg.width;

drivers/video/fbdev/sh_mobile_lcdcfb.c

2467

ch->display.height = cfg->panel_cfg.height;

drivers/video/fbdev/sh_mobile_lcdcfb.c

2468

ch->display.mode = *mode;

drivers/video/fbdev/sh_mobile_lcdcfb.c

724

const struct fb_videomode *mode = &ch->display.mode;

drivers/video/fbdev/sh_mobile_lcdcfb.h

101

} display;

include/drm/bridge/dw_hdmi.h

117

const struct drm_display_info *display,

include/drm/bridge/dw_hdmi.h

197

const struct drm_display_info *display);

include/drm/drm_modes.h

464

bool drm_mode_is_420_only(const struct drm_display_info *display,

include/drm/drm_modes.h

466

bool drm_mode_is_420_also(const struct drm_display_info *display,

include/drm/drm_modes.h

468

bool drm_mode_is_420(const struct drm_display_info *display,

include/drm/intel/display_member.h

23

struct intel_display *display;

include/drm/intel/display_member.h

38

offsetof(struct __intel_generic_device, display) - offsetof(struct __intel_generic_device, drm) == \

include/linux/pinctrl/pinconf-generic.h

193

.param = a, .display = b, .format = c, .has_arg = d, \

include/linux/pinctrl/pinconf-generic.h

201

const char * const display;

include/video/omapfb_dss.h

696

int (*enable)(struct omap_dss_device *display);

include/video/omapfb_dss.h

697

void (*disable)(struct omap_dss_device *display);

include/video/omapfb_dss.h

698

int (*run_test)(struct omap_dss_device *display, int test);

include/video/s1d13xxxfb.h

152

unsigned char display;

tools/perf/builtin-c2c.c

112

int display;

tools/perf/builtin-c2c.c

1253

switch (c2c.display) {

tools/perf/builtin-c2c.c

2144

switch (c2c.display) {

tools/perf/builtin-c2c.c

2179

switch (c2c.display) {

tools/perf/builtin-c2c.c

2260

bool display = he__display(he, &c2c.shared_clines_stats);

tools/perf/builtin-c2c.c

2265

if (display && c2c_hists) {

tools/perf/builtin-c2c.c

2294

if (c2c.display == DISPLAY_SNP_PEER)

tools/perf/builtin-c2c.c

2505

if (c2c.display != DISPLAY_SNP_PEER)

tools/perf/builtin-c2c.c

2557

display_str[c2c.display]);

tools/perf/builtin-c2c.c

2757

display_str[c2c.display]);

tools/perf/builtin-c2c.c

2869

dim_percent_costly_snoop.header = percent_costly_snoop_header[c2c.display];

tools/perf/builtin-c2c.c

2954

const char *display = str;

tools/perf/builtin-c2c.c

2956

if (!strcmp(display, "tot"))

tools/perf/builtin-c2c.c

2957

c2c.display = DISPLAY_TOT_HITM;

tools/perf/builtin-c2c.c

2958

else if (!strcmp(display, "rmt"))

tools/perf/builtin-c2c.c

2959

c2c.display = DISPLAY_RMT_HITM;

tools/perf/builtin-c2c.c

2960

else if (!strcmp(display, "lcl"))

tools/perf/builtin-c2c.c

2961

c2c.display = DISPLAY_LCL_HITM;

tools/perf/builtin-c2c.c

2962

else if (!strcmp(display, "peer"))

tools/perf/builtin-c2c.c

2963

c2c.display = DISPLAY_SNP_PEER;

tools/perf/builtin-c2c.c

3012

c2c.display == DISPLAY_SNP_PEER ? "percent_rmt_peer,"

tools/perf/builtin-c2c.c

3023

c2c.display == DISPLAY_SNP_PEER ? "mean_rmt_peer,"

tools/perf/builtin-c2c.c

3055

if (c2c.display == DISPLAY_TOT_HITM)

tools/perf/builtin-c2c.c

3057

else if (c2c.display == DISPLAY_RMT_HITM)

tools/perf/builtin-c2c.c

3059

else if (c2c.display == DISPLAY_LCL_HITM)

tools/perf/builtin-c2c.c

3061

else if (c2c.display == DISPLAY_SNP_PEER)

tools/perf/builtin-c2c.c

3087

const char *display = NULL;

tools/perf/builtin-c2c.c

3111

OPT_STRING('d', "display", &display, "Switch HITM output type", "tot,lcl,rmt,peer"),

tools/perf/builtin-c2c.c

3203

if (!display) {

tools/perf/builtin-c2c.c

3205

display = "peer";

tools/perf/builtin-c2c.c

3207

display = "tot";

tools/perf/builtin-c2c.c

3210

err = setup_display(display);

tools/perf/builtin-c2c.c

3291

if (c2c.display != DISPLAY_SNP_PEER)

tools/perf/builtin-c2c.c

3322

if (c2c.display == DISPLAY_TOT_HITM)

tools/perf/builtin-c2c.c

3324

else if (c2c.display == DISPLAY_RMT_HITM)

tools/perf/builtin-c2c.c

3326

else if (c2c.display == DISPLAY_LCL_HITM)

tools/perf/builtin-c2c.c

3328

else if (c2c.display == DISPLAY_SNP_PEER)

tools/perf/builtin-c2c.c

842

switch (c2c.display) {

tools/perf/builtin-help.c

142

const char *display = getenv("DISPLAY");

tools/perf/builtin-help.c

144

if (display && *display) {

tools/perf/builtin-timechart.c

102

int display;

tools/perf/builtin-timechart.c

1154

if (!c->display) {

tools/perf/builtin-timechart.c

119

int display;

tools/perf/builtin-timechart.c

1267

if (!c->display) {

tools/perf/builtin-timechart.c

1351

p->display = 0;

tools/perf/builtin-timechart.c

1362

c->display = 0;

tools/perf/builtin-timechart.c

1368

c->display = 1;

tools/perf/builtin-timechart.c

1369

p->display = 1;

tools/perf/builtin-timechart.c

1391

p->display = 0;

tools/perf/builtin-timechart.c

1399

p->display = 1;

tools/perf/builtin-timechart.c

1404

c->display = 0;

tools/perf/builtin-timechart.c

1410

c->display = 1;

tools/perf/builtin-timechart.c

1439

c->display = 0;

tools/perf/builtin-timechart.c

1442

c->display = 1;