/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2019 Intel Corporation
 */

#ifndef __INTEL_DP_H__
#define __INTEL_DP_H__

#include <linux/types.h>

enum intel_output_format;
enum pipe;
enum port;
struct drm_connector_state;
struct drm_dp_desc;
struct drm_dp_vsc_sdp;
struct drm_encoder;
struct drm_modeset_acquire_ctx;
struct intel_atomic_state;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_display;
struct intel_dp;
struct intel_encoder;

struct link_config_limits {
        int min_rate, max_rate;
        int min_lane_count, max_lane_count;
        struct {
                /* Uncompressed DSC input or link output bpp in 1 bpp units */
                int min_bpp, max_bpp;
        } pipe;
        struct {
                /* Compressed or uncompressed link output bpp in 1/16 bpp units */
                int min_bpp_x16, max_bpp_x16;
        } link;
};

void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
                                  const struct drm_connector_state *conn_state);
int intel_dp_min_bpp(enum intel_output_format output_format);
void intel_dp_init_modeset_retry_work(struct intel_connector *connector);
void
intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
                                      struct intel_encoder *encoder,
                                      const struct intel_crtc_state *crtc_state);
bool intel_dp_init_connector(struct intel_digital_port *dig_port,
                             struct intel_connector *intel_connector);
void intel_dp_connector_sync_state(struct intel_connector *connector,
                                   const struct intel_crtc_state *crtc_state);
void intel_dp_set_link_params(struct intel_dp *intel_dp,
                              int link_rate, int lane_count);
int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
                              struct drm_modeset_acquire_ctx *ctx,
                              u8 *pipe_mask);
void intel_dp_flush_connector_commits(struct intel_connector *connector);
void intel_dp_link_check(struct intel_encoder *encoder);
void intel_dp_check_link_state(struct intel_dp *intel_dp);
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
                                           const struct intel_crtc_state *crtc_state);
void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
                                        struct intel_connector *connector,
                                        const struct intel_crtc_state *new_crtc_state);
void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
                                         struct intel_connector *connector,
                                         const struct intel_crtc_state *old_crtc_state);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
int intel_dp_compute_config(struct intel_encoder *encoder,
                            struct intel_crtc_state *pipe_config,
                            struct drm_connector_state *conn_state);
bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
                              bool dsc_enabled_on_crtc);
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                                struct intel_crtc_state *pipe_config,
                                struct drm_connector_state *conn_state,
                                const struct link_config_limits *limits,
                                int timeslots);
void intel_dp_audio_compute_config(struct intel_encoder *encoder,
                                   struct intel_crtc_state *pipe_config,
                                   struct drm_connector_state *conn_state);
bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
bool intel_dp_is_edp(struct intel_dp *intel_dp);
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
bool intel_dp_has_dsc(const struct intel_connector *connector);
int intel_dp_link_symbol_size(int rate);
int intel_dp_link_symbol_clock(int rate);
bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
                                  bool long_hpd);
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
                            const struct drm_connector_state *conn_state);
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
void intel_dp_mst_suspend(struct intel_display *display);
void intel_dp_mst_resume(struct intel_display *display);
int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
int intel_dp_max_common_rate(struct intel_dp *intel_dp);
int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
int intel_dp_rate_index(const int *rates, int len, int rate);
int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
void intel_dp_reset_link_params(struct intel_dp *intel_dp);

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
                           u8 *link_bw, u8 *rate_select);
bool intel_dp_source_supports_tps3(struct intel_display *display);
bool intel_dp_source_supports_tps4(struct intel_display *display);

int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay,
                              int dsc_slice_count, int bpp_x16, unsigned long flags);
int intel_dp_link_required(int link_clock, int lane_count,
                           int mode_clock, int mode_hdisplay,
                           int link_bpp_x16, unsigned long bw_overhead_flags);
int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
                                 int bw_overhead);
int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
                                int max_dprx_rate, int max_dprx_lanes);
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
                               int num_joined_pipes);
bool intel_dp_has_joiner(struct intel_dp *intel_dp);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
                            const struct drm_connector_state *conn_state);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
                             const struct intel_crtc_state *crtc_state,
                             const struct drm_connector_state *conn_state);
void intel_read_dp_sdp(struct intel_encoder *encoder,
                       struct intel_crtc_state *crtc_state,
                       unsigned int type);
void intel_digital_port_lock(struct intel_encoder *encoder);
void intel_digital_port_unlock(struct intel_encoder *encoder);
bool intel_digital_port_connected(struct intel_encoder *encoder);
bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
                                 u8 dsc_max_bpc);
bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector,
                                  int link_clock, int lane_count,
                                  int mode_clock, int mode_hdisplay,
                                  int num_joined_pipes,
                                  enum intel_output_format output_format,
                                  int pipe_bpp, unsigned long bw_overhead_flags);
bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16);
u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
                                int mode_clock, int mode_hdisplay,
                                int num_joined_pipes);
int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
                              struct intel_connector *connector,
                              int hdisplay, int clock);

static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
        return ~((1 << lane_count) - 1) & 0xf;
}

bool intel_dp_supports_fec(struct intel_dp *intel_dp,
                           const struct intel_connector *connector,
                           const struct intel_crtc_state *pipe_config);
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
int intel_dp_bw_fec_overhead(bool fec_enabled);

bool intel_dp_supports_fec(struct intel_dp *intel_dp,
                           const struct intel_connector *connector,
                           const struct intel_crtc_state *pipe_config);

bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
                           const struct intel_connector *connector,
                           const struct intel_crtc_state *crtc_state);

void intel_ddi_update_pipe(struct intel_atomic_state *state,
                           struct intel_encoder *encoder,
                           const struct intel_crtc_state *crtc_state,
                           const struct drm_connector_state *conn_state);

bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
                                    struct intel_crtc_state *crtc_state);
void intel_dp_sync_state(struct intel_encoder *encoder,
                         const struct intel_crtc_state *crtc_state);

void intel_dp_check_frl_training(struct intel_dp *intel_dp);
void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
                                 const struct intel_crtc_state *crtc_state);

void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format,
                                        int pipe_bpp);

bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
                                    struct drm_connector_state *conn_state,
                                    struct intel_crtc_state *crtc_state,
                                    bool respect_downstream_limits,
                                    bool dsc,
                                    struct link_config_limits *limits);

void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
                               const struct drm_dp_desc *desc, bool is_branch,
                               struct intel_connector *connector);
bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);

bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
                                u8 lane_count);
bool intel_dp_has_connector(struct intel_dp *intel_dp,
                            const struct drm_connector_state *conn_state);
int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
int intel_dp_dsc_min_src_input_bpc(void);
int intel_dp_dsc_min_src_compressed_bpp(void);
int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
                                const struct drm_connector_state *conn_state);

int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
int intel_dp_compute_config_late(struct intel_encoder *encoder,
                                 struct intel_crtc_state *crtc_state,
                                 struct drm_connector_state *conn_state);
int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
                               bool assume_all_enabled);

#endif /* __INTEL_DP_H__ */