arch/mips/mm/cerr-sb1.c

450

static struct dc_state dc_states[] = {

arch/mips/mm/cerr-sb1.c

466

struct dc_state *dsc = dc_states;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10394

dc_plane = dm_new_plane_state->dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10995

struct dc_state *dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11007

struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11149

dm_enable_per_frame_crtc_master_sync(dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11188

status = dc_state_get_stream_status(dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11474

struct dc_state *dc_state = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11492

dc_state = dm_state->context;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11493

amdgpu_dm_commit_streams(state, dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12651

dm_old_plane_state->dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12657

if (dm_old_plane_state->dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12658

dc_plane_state_release(dm_old_plane_state->dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12660

dm_new_plane_state->dc_state = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12686

WARN_ON(dm_new_plane_state->dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12731

dm_new_plane_state->dc_state = dc_new_plane_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12738

dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3316

struct dc_state *state, bool enable)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3368

DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3372

struct dc_state *context __free(state_release) = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3471

if (dm_new_plane_state->dc_state) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3472

WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3473

dc_plane_state_release(dm_new_plane_state->dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3474

dm_new_plane_state->dc_state = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3654

static void dm_gpureset_commit_state(struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3673

for (k = 0; k < dc_state->stream_count; k++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3674

bundle->stream_update.stream = dc_state->streams[k];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3676

for (m = 0; m < dc_state->stream_status[k].plane_count; m++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3678

dc_state->stream_status[k].plane_states[m];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3685

dc_state->stream_status[k].plane_count,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3686

dc_state->streams[k],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3781

struct dc_state *dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3800

dc_state = dm->cached_dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3817

link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3833

for (i = 0; i < dc_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3834

dc_state->streams[i]->mode_changed = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3835

for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3836

dc_state->stream_status[i].plane_states[j]->update_flags.raw

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3846

commit_params.streams = dc_state->streams;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3847

commit_params.stream_count = dc_state->stream_count;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5135

struct dc_state *context;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5372

struct dc_state *cur_dc_state = dm->dc->current_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7226

static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8366

struct dc_state *dc_state = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8375

dc_state = dc_state_create(dc, NULL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8376

if (!dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8402

dc_result = dc_state_add_stream(dc, dc_state, stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8408

dc_state))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8412

dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8415

if (dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8416

dc_state_release(dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8836

struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8862

for (j = 0; j < dc_state->stream_count; j++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8863

stream = dc_state->streams[j];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8878

for (j = 0; j < dc_state->stream_count; j++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8885

if (j == dc_state->stream_count || pbn_div == 0)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1041

struct dc_state *context;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

594

struct dc_state *cached_dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

927

struct dc_plane_state *dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1421

struct dc_state *dc_state = ctx->dc->current_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1524

dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1525

dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1527

dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1530

dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1258

struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1282

DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1283

for (i = 0; i < dc_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1286

stream = dc_state->streams[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1431

struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1455

DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_count);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1458

for (i = 0; i < dc_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1462

stream = dc_state->streams[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1562

struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1574

for (i = 0; i < dc_state->stream_count; i++)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1577

for (i = 0; i < dc_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1578

stream = dc_state->streams[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1599

res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1602

if (!is_dsc_need_re_compute(state, dc_state, stream->link))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1606

ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1611

for (j = 0; j < dc_state->stream_count; j++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1612

if (dc_state->streams[j]->link == stream->link)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1617

for (i = 0; i < dc_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1618

stream = dc_state->streams[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1621

if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1632

struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1643

for (i = 0; i < dc_state->stream_count; i++)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1646

for (i = 0; i < dc_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1647

stream = dc_state->streams[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1666

if (!is_dsc_need_re_compute(state, dc_state, stream->link))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1670

ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1675

for (j = 0; j < dc_state->stream_count; j++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1676

if (dc_state->streams[j]->link == stream->link)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1742

struct dc_state *local_dc_state = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1762

local_dc_state = vmalloc(sizeof(struct dc_state));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1765

memcpy(local_dc_state, dm_state->context, sizeof(struct dc_state));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h

84

struct dc_state *dc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1001

if (dm_plane_state_new->dc_state &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1002

dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1004

dm_plane_state_new->dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1245

if (!dm_plane_state->dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1270

if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1463

if (!dm_plane_state || !dm_plane_state->dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1466

dc_plane_state = dm_plane_state->dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1520

if (old_dm_plane_state->dc_state) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1521

dm_plane_state->dc_state = old_dm_plane_state->dc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1522

dc_plane_state_retain(dm_plane_state->dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1627

if (dm_plane_state->dc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1628

dc_plane_state_release(dm_plane_state->dc_state);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

56

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

80

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

168

uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

319

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

330

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

36

uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

108

const struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

185

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

244

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

80

uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

34

const struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

40

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

42

uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

164

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

73

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

188

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

105

struct dc_state *context, bool safe_to_lower)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

127

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

217

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

347

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

453

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

30

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

34

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

37

struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

49

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

54

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

85

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

107

struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

132

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

55

static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

91

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

194

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

64

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

96

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

117

static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

138

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

645

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

78

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

46

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

112

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

151

static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

209

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

58

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

103

static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

129

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

59

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

105

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

139

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

71

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

267

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

327

struct dc_state *context, bool safe_to_lower)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

362

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

520

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

634

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

36

struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1217

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1251

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

158

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

189

void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

257

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

295

struct dc_state *context, bool safe_to_lower)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

355

static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

392

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

53

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

69

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1086

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1243

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1355

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

414

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

526

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

560

struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

618

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

770

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

56

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

62

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

67

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

158

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

168

struct dc_state *context, bool safe_to_lower)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

212

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

757

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

789

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

88

bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

53

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

75

bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

76

int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int *all_active_disps);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

77

bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

78

void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

79

void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

84

void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr, struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/core/dc.c

1137

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

1148

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

1174

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1339

static void disable_dangling_plane(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

1342

struct dc_state *dangling_context = dc_state_create_current_copy(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1343

struct dc_state *current_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1449

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

1615

struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1639

struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

189

static int get_seamless_boot_stream_count(struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

2081

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

2089

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

2098

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

2123

void dc_trigger_sync(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2133

static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2166

static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2204

static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2211

struct dc_state *old_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

2433

struct dc_state *transition_base_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2450

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/core/dc.c

2609

static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2652

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

2749

const struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3202

struct dc_state *ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

3366

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3482

struct dc_state *dsc_validate_context = dc_state_create_copy(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

3561

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3596

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3617

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3659

struct dc_state **new_context)

drivers/gpu/drm/amd/display/dc/core/dc.c

3661

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/core/dc.c

3827

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3875

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

4074

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

4245

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

4435

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

4495

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

4584

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc.c

4597

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

4639

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

4759

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

5294

struct dc_state *minimal_transition_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5295

struct dc_state *base_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5302

static void force_vsync_flip_in_minimal_transition_context(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

5316

static struct dc_state *create_minimal_transition_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5317

struct dc_state *base_context, struct pipe_split_policy_backup *policy)

drivers/gpu/drm/amd/display/dc/core/dc.c

5319

struct dc_state *minimal_transition_context = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

5345

struct dc_state *initial_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

5346

struct dc_state *intermediate_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

5347

struct dc_state *final_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

5356

struct dc_state *new_context, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

5360

struct dc_state *old = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

5399

struct dc_state *new_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5407

struct dc_state *intermediate_context =

drivers/gpu/drm/amd/display/dc/core/dc.c

5433

struct dc_state *new_context, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

5437

struct dc_state *intermediate_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

5438

struct dc_state *old_current_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

5507

struct dc_state *new_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5542

struct dc_state *transition_base_context)

drivers/gpu/drm/amd/display/dc/core/dc.c

5544

struct dc_state *transition_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

5756

const struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

5847

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/core/dc.c

5966

struct dc_state *new_context)

drivers/gpu/drm/amd/display/dc/core/dc.c

6032

struct dc_state *new_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

6108

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6374

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

6467

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

7168

struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

7191

unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

7283

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/core/dc.c

7925

struct dc_state *new_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

7927

struct dc_state *backup_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

7928

struct dc_state *intermediate_context;

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

186

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1966

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2473

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2493

void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2515

void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2540

void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2586

void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3040

struct dc_state *context = params->update_force_pstate_params.context;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3833

struct dc_state *state = params->link_set_dpms_on_params.state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4770

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5125

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5136

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

640

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

713

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

738

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

126

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

163

const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

190

static bool is_avail_link_enc(struct dc_state *state, enum engine_id eng_id, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

229

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

252

static void clear_enc_assignments(const struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

275

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

282

void link_enc_cfg_copy(const struct dc_state *src_ctx, struct dc_state *dst_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

291

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

330

struct dc_state *prev_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

440

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

622

bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

72

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

734

void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

91

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

586

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

125

static void start_new_topology_snapshot(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1776

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2295

bool resource_is_pipe_topology_changed(const struct dc_state *state_a,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2296

const struct dc_state *state_b)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2456

static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2493

static int resource_stream_to_stream_idx(struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2513

void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2591

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2614

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3037

static void swap_dio_link_enc_to_muxable_ctx(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3060

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3118

static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3129

enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3139

void resource_remove_otg_master_for_stream_output(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3223

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3274

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3275

struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3320

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3321

struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3348

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3415

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3416

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3495

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3554

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3555

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3617

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3641

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3642

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3676

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3677

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3870

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4084

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4085

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4165

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4326

static bool planes_changed_for_existing_stream(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4368

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4409

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4701

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5228

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5660

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5688

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5722

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5841

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5895

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5941

static bool resource_allocate_mcache(struct dc_state *context, const struct dc_mcache_params *mcache_params)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5988

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

6015

bool resource_is_hpo_acquired(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1011

const struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1025

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1038

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1054

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1067

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

107

static bool dc_state_untrack_phantom_plane(struct dc_state *state, struct dc_plane_state *phantom_plane)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1083

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1103

bool dc_state_is_subvp_in_use(struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

133

static bool dc_state_is_phantom_plane_tracked(struct dc_state *state, struct dc_plane_state *phantom_plane)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

145

static void dc_state_copy_internal(struct dc_state *dst_state, struct dc_state *src_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

149

memcpy(dst_state, src_state, sizeof(struct dc_state));

drivers/gpu/drm/amd/display/dc/core/dc_state.c

184

static void init_state(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

194

struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

196

struct dc_state *state;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

198

state = kvzalloc_obj(struct dc_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

240

void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

270

struct dc_state *dc_state_create_copy(struct dc_state *src_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

272

struct dc_state *new_state;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

274

new_state = kvmalloc_obj(struct dc_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

315

void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

320

struct dc_state *dc_state_create_current_copy(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

325

void dc_state_construct(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

334

void dc_state_destruct(struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

375

void dc_state_retain(struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

382

struct dc_state *state = container_of(kref, struct dc_state, refcount);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

399

void dc_state_release(struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

409

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

439

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

47

static bool dc_state_track_phantom_stream(struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

486

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

487

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

502

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

570

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

58

static bool dc_state_untrack_phantom_stream(struct dc_state *state, struct dc_stream_state *phantom_stream)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

630

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

664

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

689

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

705

enum mall_stream_type dc_state_get_pipe_subvp_type(const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

711

enum mall_stream_type dc_state_get_stream_subvp_type(const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

728

struct dc_stream_state *dc_state_get_paired_subvp_stream(const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

746

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

771

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

785

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

807

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

822

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

84

static bool dc_state_is_phantom_stream_tracked(struct dc_state *state, struct dc_stream_state *phantom_stream)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

857

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

884

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

901

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

909

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

947

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

954

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

96

static bool dc_state_track_phantom_plane(struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

976

struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

994

struct dc_stream_state *dc_state_get_stream_from_id(const struct dc_state *state, unsigned int id)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

360

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

921

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

69

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

75

struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc.h

1033

struct dc_state;

drivers/gpu/drm/amd/display/dc/dc.h

1869

struct dc_state *current_state;

drivers/gpu/drm/amd/display/dc/dc.h

2080

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc.h

2088

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/dc.h

2777

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/dc.h

2998

struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc.h

3000

unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc.h

542

struct dc_state;

drivers/gpu/drm/amd/display/dc/dc.h

548

bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1238

void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1812

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1879

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1927

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1963

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

429

static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

447

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

586

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

666

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

723

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

788

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

883

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

100

void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

198

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

209

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

345

void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

37

struct dc_state;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

90

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

33

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_state.h

31

struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params);

drivers/gpu/drm/amd/display/dc/dc_state.h

32

void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state);

drivers/gpu/drm/amd/display/dc/dc_state.h

33

struct dc_state *dc_state_create_copy(struct dc_state *src_state);

drivers/gpu/drm/amd/display/dc/dc_state.h

34

void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state);

drivers/gpu/drm/amd/display/dc/dc_state.h

35

struct dc_state *dc_state_create_current_copy(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_state.h

36

void dc_state_construct(struct dc *dc, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

37

void dc_state_destruct(struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

38

void dc_state_retain(struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

39

void dc_state_release(struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

42

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state.h

47

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state.h

54

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

60

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

65

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

72

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

75

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

102

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

106

const struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

110

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

114

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

117

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

121

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

124

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

126

bool dc_state_is_subvp_in_use(struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

32

struct dc_stream_state *dc_state_get_stream_from_id(const struct dc_state *state, unsigned int id);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

37

enum mall_stream_type dc_state_get_pipe_subvp_type(const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

39

enum mall_stream_type dc_state_get_stream_subvp_type(const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

43

struct dc_stream_state *dc_state_get_paired_subvp_stream(const struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

48

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

51

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

56

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

59

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

64

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

68

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

75

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

81

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

86

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

94

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

98

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_stream.h

424

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_stream.h

468

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_stream.h

485

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_stream.h

490

void dc_trigger_sync(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc_stream.h

531

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dc_stream.h

621

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

94

bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

68

bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

558

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

707

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

752

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1031

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1046

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1060

static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1144

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1319

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1740

void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2039

static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2089

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2166

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2246

static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2331

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

36

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

40

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

45

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

49

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

64

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

76

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

79

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

293

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

308

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

627

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

41

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

44

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

64

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

428

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h

37

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

454

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

465

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

483

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

38

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

39

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

42

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

56

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

307

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

36

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1041

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1096

static void assign_subvp_index(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1172

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1204

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1271

static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1289

static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1305

struct dc_state *context, struct vba_vars_st *v, int *split,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1399

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1429

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1442

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1604

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1619

static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1781

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

183

static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1909

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2110

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2274

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

279

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

337

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3410

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3466

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3501

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3538

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3579

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3594

unsigned int dcn32_get_max_dispclk_mhz(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

470

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

561

static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

603

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

683

static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

729

static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

800

static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

901

static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

989

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

35

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

40

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

48

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

54

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

62

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

72

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

74

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

76

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

80

unsigned int dcn32_get_max_dispclk_mhz(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

439

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

575

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

38

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

42

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

471

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

607

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

13

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

17

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

1009

void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

491

const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

520

const struct dc_state *context, unsigned int stream_index, const struct dml2_soc_bb *soc_bb)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

709

static bool dml21_wrapper_get_plane_id(const struct dc_state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

746

const struct dc_plane_state *plane, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

792

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

878

void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

960

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

10

struct dc_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

21

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

22

void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

25

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

27

unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

28

void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

147

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

163

void dml21_populate_mall_allocation_size(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

197

static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

213

void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

244

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

281

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

322

void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

36

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

380

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

499

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

85

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

21

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

23

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

26

void dml21_populate_mall_allocation_size(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

35

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

41

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

45

void dml21_handle_phantom_streams_planes(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

48

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

9

struct dc_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h

14

struct dc_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

141

static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

170

static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

199

static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

259

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

273

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

51

static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

13

struct dc_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

54

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

58

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1000

const struct dc_state *existing_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1028

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1031

const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1050

bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

109

static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

124

struct dc_state *state, unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

142

struct dc_state *state, unsigned int plane_id, unsigned int *pipes)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

179

static bool validate_pipe_assignment(const struct dml2_context *ctx, const struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, const struct dml2_dml_to_dc_pipe_mapping *mapping)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

247

static unsigned int find_preferred_pipe_candidates(const struct dc_state *existing_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

294

static unsigned int find_last_resort_pipe_candidates(const struct dc_state *existing_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

346

struct dc_state *state, // The state we want to find a free mapping in

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

351

const struct dc_state *existing_state) // The state (optional) that we want to minimize remapping relative to

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

415

struct dc_state *state, // The state we want to find a free mapping in

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

420

const struct dc_state *existing_state) // The state (optional) that we want to minimize remapping relative to

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

545

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

570

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

58

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

597

static unsigned int find_pipes_assigned_to_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id, unsigned int *pipes)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

617

static struct pipe_ctx *assign_pipes_to_stream(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

621

const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

651

static struct pipe_ctx *assign_pipes_to_plane(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

658

const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

714

static void free_unused_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

731

static void remove_pipes_from_blend_trees(struct dml2_context *ctx, struct dc_state *state, struct dc_plane_pipe_pool *pipe_pool, unsigned int odm_slice)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

749

static void map_pipes_for_stream(struct dml2_context *ctx, struct dc_state *state, const struct dc_stream_state *stream,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

750

struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

769

static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state, const struct dc_stream_state *stream, const struct dc_plane_state *plane,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

770

int plane_index, struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

807

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

865

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

911

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

923

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

939

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

957

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

970

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

971

const struct dc_state *existing_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

999

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h

50

bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

102

static void merge_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

147

static bool all_pipes_have_stream_and_plane(struct dml2_context *ctx, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

163

static bool mpo_in_use(const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

186

static unsigned int get_num_free_pipes(struct dml2_context *ctx, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

229

static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context, unsigned int *index)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

310

static bool enough_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

33

unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

358

static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

440

bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

521

static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

626

bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc_state *context, enum dml_dram_clock_change_support pstate_change_type)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

675

static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

738

static struct dc_stream_state *enable_phantom_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int dc_pipe_idx, unsigned int svp_height, unsigned int vstartup)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

760

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

813

static void add_phantom_pipes_for_main_pipe(struct dml2_context *ctx, struct dc_state *state, unsigned int main_pipe_idx, unsigned int svp_height, unsigned int vstartup)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

841

static bool remove_all_phantom_planes_for_stream(struct dml2_context *ctx, struct dc_stream_state *stream, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

871

bool dml2_svp_remove_all_phantom_pipes(struct dml2_context *ctx, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

905

bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_state *state, struct dml_mode_support_info_st *mode_support_info)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h

42

unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h

44

bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_state *state, struct dml_mode_support_info_st *mode_support_info);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h

46

bool dml2_svp_remove_all_phantom_pipes(struct dml2_context *ctx, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h

48

bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc_state *context, enum dml_dram_clock_change_support pstate_change_type);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h

50

bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1071

const struct dc_plane_state *in, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1158

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1183

const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1205

static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1280

static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct dml2_context *dml2, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1303

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

990

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

37

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

169

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

184

void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

218

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

282

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

417

void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

515

bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc_state *display_state, struct dml2_helper_det_policy_scratch *det_scratch)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

122

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

141

bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc_state *display_state, struct dml2_helper_det_policy_scratch *det_scratch);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

34

struct dc_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

41

void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

43

void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

45

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

71

void dml2_dc_construct_pipes(struct dc_state *context, struct dml_mode_support_info_st *dml_mode_support_st,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

84

bool dml2_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

96

enum dc_status dml2_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

27

bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

105

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

107

struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

111

bool (*allocate_mcache)(struct dc_state *context, const struct dc_mcache_params *mcache_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

118

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

121

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

124

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

127

bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

131

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

133

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

136

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

139

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

142

enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

143

enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

144

struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

147

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

150

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

298

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

310

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

313

bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

314

bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

76

bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

77

bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

79

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

80

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

85

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

86

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

160

static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

269

struct dc_state *display_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

359

static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode validate_mode)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

401

bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

511

bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

558

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2)

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

110

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

122

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

33

struct dc_state;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

39

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

43

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1476

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1631

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1697

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1938

static void get_edp_streams(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2054

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2204

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2355

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2421

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2445

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2517

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2647

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2929

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3009

static void dce110_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3097

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3111

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3238

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3276

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3282

static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

114

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

123

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

33

struct dc_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

40

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

44

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

62

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

72

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

76

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

116

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

385

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

51

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1225

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1330

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1486

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1598

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1615

void dcn10_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1994

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

224

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2586

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2780

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3030

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3257

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3304

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3337

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3368

static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3386

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3424

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4118

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4156

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

110

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

113

void dcn10_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

117

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

119

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

124

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

127

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

203

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

206

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

45

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

49

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

52

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

84

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

85

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

88

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

92

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1184

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1308

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1487

void dcn20_detect_pipe_changes(struct dc_state *old_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1488

struct dc_state *new_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1678

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1905

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1929

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2045

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2245

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2375

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2426

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2488

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2542

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2827

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2919

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3154

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

738

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

821

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

117

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

158

struct dc_state *old_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

159

struct dc_state *new_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

165

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

169

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

39

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

42

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

57

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

72

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

75

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

78

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

81

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

84

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

92

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

232

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

379

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

36

void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

109

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

128

void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

288

struct dc_state *context, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

99

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

41

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

45

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

47

void dcn21_PLAT_58856_wa(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

57

struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1246

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

434

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

457

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

531

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

579

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

111

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

38

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

42

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

46

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

528

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

629

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

53

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

57

struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

58

void dcn31_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

173

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

368

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

401

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

42

void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

44

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1145

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1239

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1259

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1264

struct dc_state *dc_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1269

dc_state = context;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1272

dc_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1279

&& dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1455

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1540

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1562

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1595

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1745

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1746

const struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1763

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1764

const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1816

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1849

struct dc_state *context, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1872

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

227

static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

352

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

379

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

608

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

675

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

729

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

101

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

111

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

114

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

116

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

123

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

124

const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

127

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

130

struct dc_state *context, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

133

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

48

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

66

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

68

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

70

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

78

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

81

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

94

void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1060

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1410

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1431

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1775

void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

431

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

639

void dcn35_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

835

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

913

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

944

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

110

void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

62

void dcn35_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

65

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

66

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

68

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

70

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

81

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

85

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

38

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

58

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

32

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

34

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1314

static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1446

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1508

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1560

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1596

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1612

static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1651

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1696

static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1788

void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1896

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1930

struct dc_state *context, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2037

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2049

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2152

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2213

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2237

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2366

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2514

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2677

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2809

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2860

void dcn401_detect_pipe_changes(struct dc_state *old_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2861

struct dc_state *new_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3186

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3308

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3366

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3425

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3532

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3631

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3693

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4035

void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

761

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

805

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

102

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

106

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

109

void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

110

void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

111

bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

113

struct dc_state *old_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

114

struct dc_state *new_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

125

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

139

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

145

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

157

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

168

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

180

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

185

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

204

void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

50

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

71

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

75

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

78

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

80

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

84

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

86

void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

89

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

90

void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

91

void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

95

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

98

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1067

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1085

void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1107

void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1486

void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

965

void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

38

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

39

void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

40

void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

42

void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

50

void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

46

void dcn42b_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.h

13

void dcn42b_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1239

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1241

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1242

void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1243

void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1248

int num_planes, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1250

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1252

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1254

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1272

void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1279

struct dc_state *context, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1296

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1318

void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1319

bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1320

void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1341

void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1364

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1367

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1378

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1380

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1382

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1438

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1448

void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1449

void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1450

void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1452

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1462

struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1479

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1483

void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1485

void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1494

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1495

const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1499

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1502

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1507

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1510

void (*detect_pipe_changes)(struct dc_state *old_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1511

struct dc_state *new_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1516

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1519

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1523

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1526

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1586

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1609

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1628

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1631

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1634

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1637

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1640

struct dc_state *dc_context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1643

struct dc_state *dc_context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1974

struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

221

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2345

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2472

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2475

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

294

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

358

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

39

struct dc_state;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

485

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

899

struct dc_state *context;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

903

struct dc_state *state;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

113

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

161

void (*update_odm)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

163

void (*update_odm_sequence)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

167

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

171

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

182

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

186

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

196

void (*PLAT_58856_wa)(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

200

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

201

void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

202

void (*program_mall_pipe_config_sequence)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

204

void (*update_force_pstate)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

205

void (*update_mall_sel)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

210

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

214

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

219

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

57

struct dc_state;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

79

void (*init_pipes)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

80

void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

82

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

85

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

105

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

114

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

126

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

136

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

141

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

144

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

145

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

150

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

151

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

155

void (*release_pipe)(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

165

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

170

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

188

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

209

struct dc *dc, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

214

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

225

int (*get_power_profile)(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

226

unsigned int (*get_det_buffer_size)(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

229

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

231

bool (*program_mcache_pipe_config)(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

66

struct dc_state;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

90

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

93

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

98

struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

37

struct dc_state;

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

38

struct dc_state;

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

624

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

330

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

347

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

568

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

572

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

111

bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

118

void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

40

struct dc_state *state);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

45

void link_enc_cfg_copy(const struct dc_state *src_ctx, struct dc_state *dst_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

59

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

70

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

146

const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

158

void (*set_dpms_on)(struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

119

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

130

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/resource.h

169

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

301

enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

310

void resource_remove_otg_master_for_stream_output(struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

320

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

321

struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

332

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

352

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

353

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

376

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

377

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/inc/resource.h

475

bool resource_is_pipe_topology_changed(const struct dc_state *state_a,

drivers/gpu/drm/amd/display/dc/inc/resource.h

476

const struct dc_state *state_b);

drivers/gpu/drm/amd/display/dc/inc/resource.h

489

void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/inc/resource.h

582

const struct dc_state *old_context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

583

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

588

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

593

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

618

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/resource.h

621

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

625

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

637

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/resource.h

648

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/resource.h

665

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/inc/resource.h

667

bool resource_is_hpo_acquired(struct dc_state *context);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

71

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

159

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2030

static enum dc_status enable_link_dp(struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

214

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2154

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2180

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2231

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2478

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

31

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

40

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/link/link_validation.c

670

static const struct dc_tunnel_settings *get_dp_tunnel_settings(const struct dc_state *context,

drivers/gpu/drm/amd/display/dc/link/link_validation.c

692

enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/link/link_validation.h

37

const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

329

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

850

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

868

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

909

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

930

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

941

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

46

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

50

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

55

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1057

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1103

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1114

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1132

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1133

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

949

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

972

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1005

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1026

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1045

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

877

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

895

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

968

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

42

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

43

struct dc_state *old_context);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

47

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

52

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1083

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1098

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1116

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1117

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1168

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1191

static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1346

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1414

struct dc_state *dc_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1448

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1470

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1490

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1633

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1682

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1799

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1863

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2059

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2180

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2200

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2201

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2265

void dcn20_release_pipe(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

119

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

122

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

125

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

128

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

135

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

156

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

163

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

164

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

165

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

166

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

62

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

63

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

66

void dcn20_release_pipe(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1034

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1035

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

796

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

960

static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

49

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1437

enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1477

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1533

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1743

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1785

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2045

static int get_refresh_rate(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2074

static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2104

static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2121

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2172

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2182

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2190

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2201

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

103

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

104

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

105

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

50

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

59

enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

63

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

70

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

74

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

79

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

98

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1409

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1773

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1798

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1877

const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1883

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1905

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1915

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2424

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

41

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

44

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

49

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

58

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

67

const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1827

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1857

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

43

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1792

static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1823

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1969

static int dcn315_get_power_profile(const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1766

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1808

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1853

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1880

void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1914

static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1983

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2035

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2225

void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2251

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2910

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2982

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2983

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3019

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3020

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

102

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

106

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

111

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

123

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

126

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

129

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

132

struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

134

bool dcn32_mpo_in_use(struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

136

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

147

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

148

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

153

const struct dc_state *cur_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

154

struct dc_state *new_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

158

void dcn32_release_pipe(struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

163

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

166

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

169

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

177

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

181

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

183

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

185

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

187

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

192

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

96

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

109

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

155

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

172

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

185

bool dcn32_mpo_in_use(struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

197

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

244

static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

313

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

382

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

517

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

646

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

706

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

752

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

779

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

93

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1889

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1919

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1869

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1891

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1876

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1899

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1796

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1850

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1924

int dcn401_get_power_profile(const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

26

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

29

void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

35

int dcn401_get_power_profile(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1840

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1865

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1905

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

593

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

596

void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

597

int dcn42_get_power_profile(const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

13

void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

49

bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h

31

void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h

32

bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1806

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1826

struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1866

struct dc_state *state,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

553

struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

556

void dcn42b_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/include/logger_interface.h

35

struct dc_state;

drivers/gpu/drm/amd/display/include/logger_interface.h

52

struct dc_state *context);

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

36

bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

171

bool mod_power_only_edp(const struct dc_state *context,

drivers/gpu/drm/i915/display/intel_display_power.h

143

u32 dc_state;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1062

u32 old_state = power_domains->dc_state;

drivers/gpu/drm/i915/display/intel_display_power_well.c

799

power_domains->dc_state, val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

800

power_domains->dc_state = val;

drivers/gpu/drm/i915/display/intel_display_power_well.c

849

if ((val & mask) != power_domains->dc_state)

drivers/gpu/drm/i915/display/intel_display_power_well.c

851

power_domains->dc_state, val & mask);

drivers/gpu/drm/i915/display/intel_display_power_well.c

854

dc6_was_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6;

drivers/gpu/drm/i915/display/intel_display_power_well.c

866

power_domains->dc_state = val & mask;

drivers/gpu/drm/i915/display/intel_dmc.c

1606

dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6;

drivers/gpu/drm/i915/display/intel_dmc.c

940

power_domains->dc_state = 0;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

251

u32 dc_state)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

269

switch (dc_state) {

drivers/gpu/drm/i915/display/intel_dmc_wl.c

349

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)

drivers/gpu/drm/i915/display/intel_dmc_wl.c

359

wl->dc_state = dc_state;

drivers/gpu/drm/i915/display/intel_dmc_wl.c

452

!intel_dmc_wl_check_range(display, reg, wl->dc_state))

drivers/gpu/drm/i915/display/intel_dmc_wl.c

485

!intel_dmc_wl_check_range(display, reg, wl->dc_state))

drivers/gpu/drm/i915/display/intel_dmc_wl.h

28

u32 dc_state;

drivers/gpu/drm/i915/display/intel_dmc_wl.h

33

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);

drivers/gpu/drm/tegra/dc.c

2416

struct tegra_dc_state *dc_state = to_dc_state(crtc_state);

drivers/gpu/drm/tegra/dc.c

2420

value = dc_state->planes << 8 | GENERAL_UPDATE;

drivers/gpu/drm/tegra/dc.c

2424

value = dc_state->planes | GENERAL_ACT_REQ;