CCR
val = readl_relaxed(ccm_base + CCR);
writel_relaxed(val, ccm_base + CCR);
val = readl_relaxed(ccm_base + CCR);
writel(val, ccm_base + CCR);
val = readl_relaxed(ccm_base + CCR);
writel_relaxed(val, ccm_base + CCR);
l = dma_read(CCR, lch);
dma_write(l, CCR, lch);
[CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
ccr = p->dma_read(CCR, lch);
p->dma_write(ccr, CCR, lch);
l = p->dma_read(CCR, lch);
p->dma_write(l, CCR, lch);
l = p->dma_read(CCR, lch);
p->dma_write(l, CCR, lch);
p->dma_write(dev_id | (1 << 10), CCR, free_ch);
p->dma_write(dev_id, CCR, free_ch);
p->dma_write(0, CCR, lch);
l = p->dma_read(CCR, lch);
p->dma_write(l, CCR, lch);
l = p->dma_read(CCR, lch);
l = p->dma_read(CCR, lch);
p->dma_write(l, CCR, lch);
l = p->dma_read(CCR, lch);
l = p->dma_read(CCR, lch);
p->dma_write(l, CCR, lch);
return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
[CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
ATMEL_TC_REG(2, CCR));
tcaddr + ATMEL_TC_REG(2, CCR));
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
ATMEL_TC_REG(priv->channel[1], CCR),
ret = regmap_write(regmap, ATMEL_TC_REG(priv->channel[0], CCR),
off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
if (omap_dma_chan_read(c, CCR) & CCR_ENABLE)
omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
val = omap_dma_chan_read(c, CCR);
val = omap_dma_chan_read(c, CCR);
val = omap_dma_chan_read(c, CCR);
omap_dma_chan_write(c, CCR, val);
omap_dma_chan_write(c, CCR, val);
omap_dma_chan_write(c, CCR, d->ccr);
uint32_t ccr = omap_dma_chan_read(c, CCR);
channel64_readl(dc, CCR),
channel32_readl(dc, CCR),
channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
channel_writel(dc, CCR, 0);
channel64_writel(dc, CCR, dc->ccr);
channel32_writel(dc, CCR, dc->ccr);
channel32_writel(dc, CCR, dc->ccr);
desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
d->SAIR, d->DAIR, d->CCR, d->CSR);
desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT;
desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT;
desc->hwdesc.CCR = ccr;
desc->hwdesc32.CCR = ccr;
TXX9_DMA_REG32(CCR); /* Channel Control Register */
u32 CCR;
tnt_writeb(tnt_priv, nec_priv->auxa_bits | HR_HLDA, CCR);
tnt_writeb(tnt_priv, AUX_SEOI, CCR);
ATMEL_TC_REG(tcbpwmc->channel, CCR),
ATMEL_TC_REG(tcbpwmc->channel, CCR),
regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
ATMEL_TC_REG(channel, CCR));
wr_reg8(info, CCR, 0x49);
wr_reg8(info, CCR, 0x69);
wr_reg8(info, CCR, (unsigned char)val);
SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
CCR, REG_VAL_PUT(CCR_CACHEINVALIDSIZE, 64),
CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
CCR, 0,
snd_emu10k1_ptr_write(emu, CCR, voice + 1, ccr);
snd_emu10k1_ptr_write(emu, CCR, voice, ccr);
i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
writel(kmb_i2s->ccr, kmb_i2s->i2s_base + CCR);