clocksource_register_hz
clocksource_register_hz(&qemu_cs, NSEC_PER_SEC);
clocksource_register_hz(&clocksource_rpcc, cycle_freq);
clocksource_register_hz(&cksrc_dc21285, rate);
clocksource_register_hz(&cksrc, rate);
WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ));
res = clocksource_register_hz(&clocksource_const, freq);
clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
clocksource_register_hz(&amiga_clk, amiga_eclock);
clocksource_register_hz(&atari_clk, INT_CLK);
clocksource_register_hz(&bvme6000_clk, RTC_TIMER_CLOCK_FREQ);
return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
clocksource_register_hz(&pit_clk, FREQ);
clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
clocksource_register_hz(&mcftmr_clk, FREQ);
clocksource_register_hz(&hp300_clk, HP300_TIMER_CLOCK_FREQ);
clocksource_register_hz(&mac_clk, VIA_CLOCK_FREQ);
clocksource_register_hz(&mvme147_clk, PCC_TIMER_CLOCK_FREQ);
clocksource_register_hz(&mvme16x_clk, PCC_TIMER_CLOCK_FREQ);
ret = clocksource_register_hz(&clocksource_microblaze,
clocksource_register_hz(&au1x_counter1_clocksource, 32768);
clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
clocksource_register_hz(cs, zbbus);
clocksource_register_hz(&clocksource_dec, freq);
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
return clocksource_register_hz(&csrc_hpet, HPET_FREQ);
clocksource_register_hz(cs, CYCLES_PER_SEC);
clocksource_register_hz(cs, HEART_CYCLES_PER_SEC);
ret = clocksource_register_hz(&nios2_cs.cs, freq);
if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
clocksource_register_hz(&clocksource_cr16, cr16_clock_freq);
if (clocksource_register_hz(clock, tb_ticks_per_sec)) {
return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
clocksource_register_hz(&clocksource_tick, freq);
err = clocksource_register_hz(&timer_clocksource, NSEC_PER_SEC/TIMER_MULTIPLIER);
clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
clocksource_register_hz(&kvm_clock, NSEC_PER_SEC);
rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
clocksource_register_hz(&xen_clocksource, NSEC_PER_SEC);
clocksource_register_hz(&ccount_clocksource, ccount_freq);
return clocksource_register_hz(&clocksource_acpi_pm, PMTMR_TICKS_PER_SEC);
return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
clocksource_register_hz(&clocksource_counter, arch_timer_rate);
clocksource_register_hz(&at->cs, at->rate);
return clocksource_register_hz(>_clocksource, gt_target_rate);
return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
clocksource_register_hz(cs, p->rate);
if (clocksource_register_hz(&mct_frc, clk_rate))
clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100);
clocksource_register_hz(&hyperv_cs_msr, NSEC_PER_SEC/100);
return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
err = clocksource_register_hz(cs, rate);
err = clocksource_register_hz(cs, rate);
err = clocksource_register_hz(cs, rate);
ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
return clocksource_register_hz(&cs->clksrc, hz);
clocksource_register_hz(&clocksource_mxs, c);
clocksource_register_hz(&numachip2_clocksource, NSEC_PER_SEC);
return clocksource_register_hz(&samsung_clocksource, clock_rate);
return clocksource_register_hz(&cs_hrt, freq);
clocksource_register_hz(cs, ch->cmt->rate);
clocksource_register_hz(cs, ch->tmu->rate);
ret = clocksource_register_hz(&data->clksrc, pit_rate);
return clocksource_register_hz(&clk32k, sclk_rate);
ret = clocksource_register_hz(&clksrc, divided_rate);
err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
clocksource_register_hz(&timerdrv->cs, NSEC_PER_SEC);
return clocksource_register_hz(&ls1x_clocksource.clksrc,
ret = clocksource_register_hz(&cs->clksrc, clk_rate);
clocksource_register_hz(&csky_clocksource, timer_of_rate(to));
return clocksource_register_hz(&pit->cs, rate);
ret = clocksource_register_hz(&stm_timer->cs, stm_timer->rate);
return clocksource_register_hz(&pcs_gpt.cs, rate);
res = clocksource_register_hz(cs, dgt_hz);
clocksource_register_hz(&rda_hwtimer_clocksource, rate);
error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC);
clocksource_register_hz(&suspend_clocksource,
clocksource_register_hz(&cs->clksrc, ndata->new_rate);
ret = clocksource_register_hz(&cs->clksrc, rate);
return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
return clocksource_register_hz(&tegra->tsc, 31250000);
return clocksource_register_hz(&tegra->osc, 38400000);
return clocksource_register_hz(&tegra->usec, USEC_PER_SEC);
ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
if (clocksource_register_hz(dev, t->rate))
ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);