clk_prepare
ret = clk_prepare(sachip->clk);
clk_prepare(wdog_clk);
clk_prepare(oh->_clk);
clk_prepare(os->_clk);
clk_prepare(oc->_clk);
} else if (clk_prepare(ce->clk)) {
ret = clk_prepare(ctx->clk);
return clk_prepare(ctx->clk);
error = clk_prepare(ddata->clocks[index]);
ret = clk_prepare(clks[i].clk);
return __devm_clk_get(dev, id, clk_get, clk_prepare, clk_unprepare);
clk_prepare, clk_unprepare);
ret = clk_prepare(cinfo->hw.clk);
clk_prepare(data->clk[i].hw.clk);
EXPORT_SYMBOL_GPL(clk_prepare);
return clk_prepare(usb0->fck);
ret = clk_prepare(td->ref_clk);
ret = clk_prepare(td->soc_clk);
ret = clk_prepare(td->i2c_clk);
ret = clk_prepare(p->clk);
ret = clk_prepare(cmt->clk);
clk_prepare(ch->cmt->clk);
ret = clk_prepare(mtu->clk);
ret = clk_prepare(tmu->clk);
ret = clk_prepare(sdma->clk_ipg);
ret = clk_prepare(sdma->clk_ahb);
ret = clk_prepare(pcdev->pclk);
ret = clk_prepare(bdev->bamclk);
ret = clk_prepare(tdma->dma_clk);
clk_prepare(clk);
clk_prepare(bank->dbck);
cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) |
err = clk_prepare(ipu->clk);
temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
temp = 8 * ui + (timing->clk_prepare << 3) * ui;
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false);
temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff;
timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,
temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
timing->clk_prepare = linear_inter(tmax, tmin, 50, 0, false);
timing->clk_prepare, timing->hs_exit, timing->hs_rqst);
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
u32 clk_prepare;
writel(timing->clk_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2);
u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
writel(DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
writel(DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2);
ret = clk_prepare(vop->dclk);
ret = clk_prepare(i2c->clk);
ret = clk_prepare(i2c->pclk);
ret = clk_prepare(info->clk);
ret = clk_prepare(info->sclk);
ret = clk_prepare(priv->clk);
ret = clk_prepare(cec->clk_cec);
ret = clk_prepare(cec->clk_hdmi_cec);
val = tc358746_ps_to_cnt(cfg->clk_prepare, hs_byte_clk) - 1;
rc = clk_prepare(video->eclk);
rc = clk_prepare(video->vclk);
clk_prepare(cam->clk[0]);
clk_prepare(vpu->clk);
ret = clk_prepare(vpu->clk);
ret = clk_prepare(fimc->clock[i]);
ret = clk_prepare(state->clock[i]);
ret = clk_prepare(camif->clock[i]);
ret = clk_prepare(dev->clk);
ret = clk_prepare(dev->gate);
ret = clk_prepare(bdisp->clock);
ret = clk_prepare(hva->clk);
ret = clk_prepare(dev->gate);
clk_prepare(tll->ch_clk[i]);
clk_prepare(ssc->clk);
ret = clk_prepare(host->fclk);
clk_prepare(priv->refclk);
ret = clk_prepare(gmac->tx_clk);
clk_prepare(gmac->tx_clk);
ret = clk_prepare(cpts->refclk);
ret = clk_prepare(otp->clk);
ret = clk_prepare(otp->clk);
(DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
if (2 * dphy_opts->clk_prepare > 3 * lp_t) {
dphy_opts->clk_prepare, lp_t);
cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;
if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
cfg->clk_prepare = 38000;
return clk_prepare(lpc->clk);
return clk_prepare(priv->pclk);
val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare);
u8 clk_prepare;
error = clk_prepare(phy->refclk);
ret = clk_prepare(plgpio->clk);
ret = clk_prepare(pc->tbclk);
return clk_prepare(scp->clk);
return clk_prepare(scp->clk);
err = clk_prepare(ddata->clk);
clk_prepare(sr_info->fck);
ret = clk_prepare(aq->pclk);
ret = clk_prepare(aq->qspick);
ret = clk_prepare(data->clk_sec);
ret = clk_prepare(data->clk);
ret = clk_prepare(data->clk);
ret = clk_prepare(uap->clk);
ret = clk_prepare(uap->clk);
ret = clk_prepare(sport->clk);
retval = clk_prepare(udc->fclk);
retval = clk_prepare(udc->clk);
retval = clk_prepare(priv->usb_host_ck);
retval = clk_prepare(priv->usb_dc_ck);
ret = clk_prepare(clk);
int clk_prepare(struct clk *clk);
unsigned int clk_prepare;
DEFINE_EVENT(clk, clk_prepare,
return clk_prepare(clk);
ret = clk_prepare(dev->gclk);
ret = clk_prepare(clk);
ret = clk_prepare(saif->clk);
ret = clk_prepare(master_saif->clk);
ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
int ret = clk_prepare(clk);
ret = clk_prepare(sai->pdata->pclk);