arch/alpha/kernel/sys_ruffian.c

184

unsigned long bank_addr, bank, ret = 0;

arch/alpha/kernel/sys_ruffian.c

189

bank = *(vulp)bank_addr;

arch/alpha/kernel/sys_ruffian.c

192

if (bank & 0x01) {

arch/alpha/kernel/sys_ruffian.c

205

bank = (bank & 0x1e) >> 1;

arch/alpha/kernel/sys_ruffian.c

206

if (bank < ARRAY_SIZE(size))

arch/alpha/kernel/sys_ruffian.c

207

ret = size[bank];

arch/arm/kernel/tcm.c

111

static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,

arch/arm/kernel/tcm.c

127

: "r" (bank));

arch/arm/kernel/tcm.c

140

type ? "I" : "D", bank);

arch/arm/kernel/tcm.c

144

type ? "I" : "D", bank);

arch/arm/kernel/tcm.c

149

bank,

arch/arm/kernel/tcm.c

176

bank,

arch/arm/mach-mxs/mach-mxs.c

47

#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))

arch/arm/mach-omap1/irq.c

103

signed int bank;

arch/arm/mach-omap1/irq.c

106

bank = IRQ_BANK(irq);

arch/arm/mach-omap1/irq.c

108

fiq = bank ? 0 : (fiq & 0x1);

arch/arm/mach-omap1/irq.c

111

irq_bank_writel(val, bank, offset);

arch/arm/mach-omap1/irq.c

69

static inline unsigned int irq_bank_readl(int bank, int offset)

arch/arm/mach-omap1/irq.c

71

return readl_relaxed(irq_banks[bank].va + offset);

arch/arm/mach-omap1/irq.c

73

static inline void irq_bank_writel(unsigned long value, int bank, int offset)

arch/arm/mach-omap1/irq.c

75

writel_relaxed(value, irq_banks[bank].va + offset);

arch/arm/mach-omap2/powerdomain-common.c

47

u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)

arch/arm/mach-omap2/powerdomain-common.c

49

switch (bank) {

arch/arm/mach-omap2/powerdomain-common.c

67

u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)

arch/arm/mach-omap2/powerdomain-common.c

69

switch (bank) {

arch/arm/mach-omap2/powerdomain-common.c

87

u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)

arch/arm/mach-omap2/powerdomain-common.c

89

switch (bank) {

arch/arm/mach-omap2/powerdomain.c

665

int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)

arch/arm/mach-omap2/powerdomain.c

672

if (pwrdm->banks < (bank + 1))

arch/arm/mach-omap2/powerdomain.c

675

if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))

arch/arm/mach-omap2/powerdomain.c

679

pwrdm->name, bank, pwrst);

arch/arm/mach-omap2/powerdomain.c

682

ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);

arch/arm/mach-omap2/powerdomain.c

703

int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)

arch/arm/mach-omap2/powerdomain.c

710

if (pwrdm->banks < (bank + 1))

arch/arm/mach-omap2/powerdomain.c

713

if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))

arch/arm/mach-omap2/powerdomain.c

717

pwrdm->name, bank, pwrst);

arch/arm/mach-omap2/powerdomain.c

720

ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);

arch/arm/mach-omap2/powerdomain.c

799

int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/powerdomain.c

806

if (pwrdm->banks < (bank + 1))

arch/arm/mach-omap2/powerdomain.c

810

bank = 1;

arch/arm/mach-omap2/powerdomain.c

813

ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank);

arch/arm/mach-omap2/powerdomain.c

829

int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/powerdomain.c

836

if (pwrdm->banks < (bank + 1))

arch/arm/mach-omap2/powerdomain.c

840

bank = 1;

arch/arm/mach-omap2/powerdomain.c

843

ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank);

arch/arm/mach-omap2/powerdomain.c

858

int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/powerdomain.c

865

if (pwrdm->banks < (bank + 1))

arch/arm/mach-omap2/powerdomain.c

869

ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank);

arch/arm/mach-omap2/powerdomain.h

185

int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);

arch/arm/mach-omap2/powerdomain.h

186

int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);

arch/arm/mach-omap2/powerdomain.h

190

int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/powerdomain.h

191

int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/powerdomain.h

192

int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/powerdomain.h

226

int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);

arch/arm/mach-omap2/powerdomain.h

227

int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);

arch/arm/mach-omap2/powerdomain.h

232

int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/powerdomain.h

233

int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/powerdomain.h

234

int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/powerdomain.h

262

extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);

arch/arm/mach-omap2/powerdomain.h

263

extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);

arch/arm/mach-omap2/powerdomain.h

264

extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);

arch/arm/mach-omap2/prm2xxx_3xxx.c

111

int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm2xxx_3xxx.c

116

m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);

arch/arm/mach-omap2/prm2xxx_3xxx.c

124

int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm2xxx_3xxx.c

129

m = omap2_pwrdm_get_mem_bank_retst_mask(bank);

arch/arm/mach-omap2/prm2xxx_3xxx.c

137

int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm2xxx_3xxx.c

141

m = omap2_pwrdm_get_mem_bank_stst_mask(bank);

arch/arm/mach-omap2/prm2xxx_3xxx.c

147

int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm2xxx_3xxx.c

151

m = omap2_pwrdm_get_mem_bank_retst_mask(bank);

arch/arm/mach-omap2/prm2xxx_3xxx.h

107

extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm2xxx_3xxx.h

109

extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm2xxx_3xxx.h

111

extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/prm2xxx_3xxx.h

112

extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);

arch/arm/mach-omap2/prm33xx.c

224

static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm33xx.c

229

m = pwrdm->mem_on_mask[bank];

arch/arm/mach-omap2/prm33xx.c

239

static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm33xx.c

244

m = pwrdm->mem_ret_mask[bank];

arch/arm/mach-omap2/prm33xx.c

254

static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm33xx.c

258

m = pwrdm->mem_pwrst_mask[bank];

arch/arm/mach-omap2/prm33xx.c

269

static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm33xx.c

273

m = pwrdm->mem_retst_mask[bank];

arch/arm/mach-omap2/prm3xxx.c

588

static int omap3_get_mem_bank_lastmemst_mask(u8 bank)

arch/arm/mach-omap2/prm3xxx.c

590

switch (bank) {

arch/arm/mach-omap2/prm3xxx.c

606

static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm3xxx.c

610

m = omap3_get_mem_bank_lastmemst_mask(bank);

arch/arm/mach-omap2/prm44xx.c

502

static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm44xx.c

507

m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);

arch/arm/mach-omap2/prm44xx.c

516

static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

arch/arm/mach-omap2/prm44xx.c

521

m = omap2_pwrdm_get_mem_bank_retst_mask(bank);

arch/arm/mach-omap2/prm44xx.c

582

static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm44xx.c

586

m = omap2_pwrdm_get_mem_bank_stst_mask(bank);

arch/arm/mach-omap2/prm44xx.c

596

static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm44xx.c

600

m = omap2_pwrdm_get_mem_bank_retst_mask(bank);

arch/arm/mach-omap2/prm44xx.c

624

static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

arch/arm/mach-omap2/prm44xx.c

636

return omap4_pwrdm_read_mem_retst(pwrdm, bank);

arch/arm/mach-pxa/generic.h

19

mi->bank[__nr].start = (__start), \

arch/arm/mach-pxa/generic.h

20

mi->bank[__nr].size = (__size)

arch/arm/mach-pxa/mfp-pxa2xx.c

101

gpdr_lpm[bank] |= mask;

arch/arm/mach-pxa/mfp-pxa2xx.c

103

gpdr_lpm[bank] &= ~mask;

arch/arm/mach-pxa/mfp-pxa2xx.c

57

int bank = gpio_to_bank(gpio);

arch/arm/mach-pxa/mfp-pxa2xx.c

67

gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);

arch/arm/mach-pxa/mfp-pxa2xx.c

71

GAFR_L(bank) = gafr;

arch/arm/mach-pxa/mfp-pxa2xx.c

73

GAFR_U(bank) = gafr;

arch/arm/mach-pxa/mfp-pxa2xx.c

83

PGSR(bank) |= mask;

arch/arm/mach-pxa/mfp-pxa2xx.c

87

PGSR(bank) &= ~mask;

arch/arm/mach-sa1100/generic.h

18

mi->bank[__nr].start = (__start), \

arch/arm/mach-sa1100/generic.h

19

mi->bank[__nr].size = (__size)

arch/mips/sgi-ip22/ip22-mc.c

38

static inline unsigned int get_bank_config(int bank)

arch/mips/sgi-ip22/ip22-mc.c

40

unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;

arch/mips/sgi-ip22/ip22-mc.c

41

return bank % 2 ? res & 0xffff : res >> 16;

arch/mips/sgi-ip32/ip32-memory.c

25

int bank;

arch/mips/sgi-ip32/ip32-memory.c

29

for (bank=0; bank < CRIME_MAXBANKS; bank++) {

arch/mips/sgi-ip32/ip32-memory.c

30

u64 bankctl = crime->bank_ctrl[bank];

arch/mips/sgi-ip32/ip32-memory.c

32

if (bank != 0 && base == 0)

arch/mips/sgi-ip32/ip32-memory.c

40

bank, base, size >> 20);

arch/powerpc/boot/4xx.c

204

u32 cs, col, row, bank, dpath;

arch/powerpc/boot/4xx.c

247

bank = 8; /* 8 banks */

arch/powerpc/boot/4xx.c

249

bank = 4; /* 4 banks */

arch/powerpc/boot/4xx.c

251

memsize = cs * (1 << (col+row)) * bank * dpath;

arch/powerpc/include/asm/fsl_lbc.h

91

struct fsl_lbc_bank bank[12];

arch/powerpc/platforms/85xx/p1022_ds.c

234

br0 = in_be32(&lbc->bank[0].br);

arch/powerpc/platforms/85xx/p1022_ds.c

235

br1 = in_be32(&lbc->bank[1].br);

arch/powerpc/platforms/85xx/p1022_ds.c

236

or0 = in_be32(&lbc->bank[0].or);

arch/powerpc/platforms/85xx/p1022_ds.c

237

or1 = in_be32(&lbc->bank[1].or);

arch/powerpc/platforms/85xx/p1022_ds.c

253

out_be32(&lbc->bank[0].br, br0);

arch/powerpc/platforms/85xx/p1022_ds.c

254

out_be32(&lbc->bank[0].or, or0);

arch/powerpc/platforms/85xx/p1022_ds.c

259

out_be32(&lbc->bank[1].br, br1);

arch/powerpc/platforms/85xx/p1022_ds.c

260

out_be32(&lbc->bank[1].or, or1);

arch/powerpc/platforms/powermac/nvram.c

280

static int sm_erase_bank(int bank)

arch/powerpc/platforms/powermac/nvram.c

287

DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);

arch/powerpc/platforms/powermac/nvram.c

311

static int sm_write_bank(int bank, u8* datas)

arch/powerpc/platforms/powermac/nvram.c

318

DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);

arch/powerpc/platforms/powermac/nvram.c

345

static int amd_erase_bank(int bank)

arch/powerpc/platforms/powermac/nvram.c

352

DBG("nvram: AMD Erasing bank %d...\n", bank);

arch/powerpc/platforms/powermac/nvram.c

391

static int amd_write_bank(int bank, u8* datas)

arch/powerpc/platforms/powermac/nvram.c

398

DBG("nvram: AMD Writing bank %d...\n", bank);

arch/powerpc/platforms/powermac/nvram.c

79

static int (*core99_write_bank)(int bank, u8* datas);

arch/powerpc/platforms/powermac/nvram.c

80

static int (*core99_erase_bank)(int bank);

arch/powerpc/sysdev/fsl_lbc.c

101

bank = fsl_lbc_find(addr_base);

arch/powerpc/sysdev/fsl_lbc.c

102

if (bank < 0)

arch/powerpc/sysdev/fsl_lbc.c

103

return bank;

arch/powerpc/sysdev/fsl_lbc.c

109

br = in_be32(&lbc->bank[bank].br);

arch/powerpc/sysdev/fsl_lbc.c

74

for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {

arch/powerpc/sysdev/fsl_lbc.c

75

u32 br = in_be32(&lbc->bank[i].br);

arch/powerpc/sysdev/fsl_lbc.c

76

u32 or = in_be32(&lbc->bank[i].or);

arch/powerpc/sysdev/fsl_lbc.c

97

int bank;

arch/um/drivers/pty.c

81

char *pty, *bank, *cp;

arch/um/drivers/pty.c

85

for (bank = "pqrs"; *bank; bank++) {

arch/um/drivers/pty.c

86

line[strlen("/dev/pty")] = *bank;

arch/x86/events/amd/iommu.c

160

u32 shift, bank, cntr;

arch/x86/events/amd/iommu.c

166

for (bank = 0; bank < max_banks; bank++) {

arch/x86/events/amd/iommu.c

168

shift = bank + (bank*3) + cntr;

arch/x86/events/amd/iommu.c

173

event->hw.iommu_bank = bank;

arch/x86/events/amd/iommu.c

187

u8 bank, u8 cntr)

arch/x86/events/amd/iommu.c

196

if ((bank > max_banks) || (cntr > max_cntrs))

arch/x86/events/amd/iommu.c

199

shift = bank + cntr + (bank*3);

arch/x86/events/amd/iommu.c

243

u8 bank = hwc->iommu_bank;

arch/x86/events/amd/iommu.c

248

amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, &reg);

arch/x86/events/amd/iommu.c

254

amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, &reg);

arch/x86/events/amd/iommu.c

260

amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, &reg);

arch/x86/events/amd/iommu.c

266

amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, &reg);

arch/x86/include/asm/mce.h

311

extern void mce_disable_bank(int bank);

arch/x86/include/asm/mce.h

390

enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);

arch/x86/include/uapi/asm/kvm.h

584

__u8 bank;

arch/x86/include/uapi/asm/mce.h

28

__u8 bank; /* Machine check bank reporting the error */

arch/x86/kernel/cpu/mce/amd.c

1034

static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)

arch/x86/kernel/cpu/mce/amd.c

1039

if (b && bank == 4)

arch/x86/kernel/cpu/mce/amd.c

1042

return th_names[bank];

arch/x86/kernel/cpu/mce/amd.c

1045

bank_type = smca_get_bank_type(cpu, bank);

arch/x86/kernel/cpu/mce/amd.c

1058

snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_bank_%u", bank);

arch/x86/kernel/cpu/mce/amd.c

1067

per_cpu(smca_banks, cpu)[bank].sysfs_id);

arch/x86/kernel/cpu/mce/amd.c

1072

unsigned int bank, unsigned int block,

arch/x86/kernel/cpu/mce/amd.c

1079

if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))

arch/x86/kernel/cpu/mce/amd.c

1101

b->bank = bank;

arch/x86/kernel/cpu/mce/amd.c

1105

b->interrupt_capable = lvt_interrupt_supported(bank, high);

arch/x86/kernel/cpu/mce/amd.c

1119

err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));

arch/x86/kernel/cpu/mce/amd.c

1123

address = get_block_address(address, low, high, bank, ++block, cpu);

arch/x86/kernel/cpu/mce/amd.c

1127

err = allocate_threshold_blocks(cpu, tb, bank, block, address);

arch/x86/kernel/cpu/mce/amd.c

1145

unsigned int bank)

arch/x86/kernel/cpu/mce/amd.c

1149

const char *name = get_name(cpu, bank, NULL);

arch/x86/kernel/cpu/mce/amd.c

1170

err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));

arch/x86/kernel/cpu/mce/amd.c

1174

bp[bank] = b;

arch/x86/kernel/cpu/mce/amd.c

1190

static void threshold_remove_bank(struct threshold_bank *bank)

arch/x86/kernel/cpu/mce/amd.c

1194

list_for_each_entry_safe(pos, tmp, &bank->miscj, miscj) {

arch/x86/kernel/cpu/mce/amd.c

1199

kobject_put(bank->kobj);

arch/x86/kernel/cpu/mce/amd.c

1200

kfree(bank);

arch/x86/kernel/cpu/mce/amd.c

1205

unsigned int bank, numbanks = this_cpu_read(mce_num_banks);

arch/x86/kernel/cpu/mce/amd.c

1207

for (bank = 0; bank < numbanks; bank++) {

arch/x86/kernel/cpu/mce/amd.c

1208

if (!bp[bank])

arch/x86/kernel/cpu/mce/amd.c

1211

threshold_remove_bank(bp[bank]);

arch/x86/kernel/cpu/mce/amd.c

1212

bp[bank] = NULL;

arch/x86/kernel/cpu/mce/amd.c

1247

unsigned int numbanks, bank;

arch/x86/kernel/cpu/mce/amd.c

1262

for (bank = 0; bank < numbanks; ++bank) {

arch/x86/kernel/cpu/mce/amd.c

1263

if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))

arch/x86/kernel/cpu/mce/amd.c

1265

if (threshold_create_bank(bp, cpu, bank)) {

arch/x86/kernel/cpu/mce/amd.c

141

enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)

arch/x86/kernel/cpu/mce/amd.c

145

if (bank >= MAX_NR_BANKS)

arch/x86/kernel/cpu/mce/amd.c

148

b = &per_cpu(smca_banks, cpu)[bank];

arch/x86/kernel/cpu/mce/amd.c

235

unsigned int bank;

arch/x86/kernel/cpu/mce/amd.c

275

static void smca_configure(unsigned int bank, unsigned int cpu)

arch/x86/kernel/cpu/mce/amd.c

282

u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);

arch/x86/kernel/cpu/mce/amd.c

309

__set_bit(bank, data->dfr_intr_banks);

arch/x86/kernel/cpu/mce/amd.c

326

__set_bit(bank, data->thr_intr_banks);

arch/x86/kernel/cpu/mce/amd.c

330

this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));

arch/x86/kernel/cpu/mce/amd.c

333

this_cpu_ptr(smca_banks)[bank].paddrv = 1;

arch/x86/kernel/cpu/mce/amd.c

338

if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {

arch/x86/kernel/cpu/mce/amd.c

339

pr_warn("Failed to read MCA_IPID for bank %d\n", bank);

arch/x86/kernel/cpu/mce/amd.c

350

this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;

arch/x86/kernel/cpu/mce/amd.c

351

this_cpu_ptr(smca_banks)[bank].id = low;

arch/x86/kernel/cpu/mce/amd.c

352

this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;

arch/x86/kernel/cpu/mce/amd.c

385

static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)

arch/x86/kernel/cpu/mce/amd.c

390

if (bank == 4)

arch/x86/kernel/cpu/mce/amd.c

415

b->bank, b->block, b->address, hi, lo);

arch/x86/kernel/cpu/mce/amd.c

422

b->cpu, apic, b->bank, b->block, b->address, hi, lo);

arch/x86/kernel/cpu/mce/amd.c

479

static void threshold_restart_bank(unsigned int bank, bool intr_en)

arch/x86/kernel/cpu/mce/amd.c

485

if (!thr_banks || !thr_banks[bank])

arch/x86/kernel/cpu/mce/amd.c

490

list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) {

arch/x86/kernel/cpu/mce/amd.c

531

unsigned int bank, unsigned int block,

arch/x86/kernel/cpu/mce/amd.c

536

if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))

arch/x86/kernel/cpu/mce/amd.c

541

return MSR_AMD64_SMCA_MCx_MISC(bank);

arch/x86/kernel/cpu/mce/amd.c

546

return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);

arch/x86/kernel/cpu/mce/amd.c

552

addr = mca_msr_reg(bank, MCA_MISC);

arch/x86/kernel/cpu/mce/amd.c

565

static int prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,

arch/x86/kernel/cpu/mce/amd.c

573

per_cpu(bank_map, cpu) |= BIT_ULL(bank);

arch/x86/kernel/cpu/mce/amd.c

577

b.bank = bank;

arch/x86/kernel/cpu/mce/amd.c

580

b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);

arch/x86/kernel/cpu/mce/amd.c

585

__set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks);

arch/x86/kernel/cpu/mce/amd.c

604

enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);

arch/x86/kernel/cpu/mce/amd.c

615

if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)

arch/x86/kernel/cpu/mce/amd.c

628

static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)

arch/x86/kernel/cpu/mce/amd.c

635

if (c->x86 == 0x15 && bank == 4) {

arch/x86/kernel/cpu/mce/amd.c

642

if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)

arch/x86/kernel/cpu/mce/amd.c

645

msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);

arch/x86/kernel/cpu/mce/amd.c

718

unsigned int bank, block, cpu = smp_processor_id();

arch/x86/kernel/cpu/mce/amd.c

728

for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {

arch/x86/kernel/cpu/mce/amd.c

730

smca_configure(bank, cpu);

arch/x86/kernel/cpu/mce/amd.c

736

disable_err_thresholding(c, bank);

arch/x86/kernel/cpu/mce/amd.c

739

address = get_block_address(address, low, high, bank, block, cpu);

arch/x86/kernel/cpu/mce/amd.c

753

offset = prepare_threshold_block(bank, block, address, offset, high);

arch/x86/kernel/cpu/mce/amd.c

770

return m->bank == 4 && XEC(m->status, 0x1f) == 8;

arch/x86/kernel/cpu/mce/amd.c

784

bank_type = smca_get_bank_type(m->extcpu, m->bank);

arch/x86/kernel/cpu/mce/amd.c

825

else if (m->bank == 4)

arch/x86/kernel/cpu/mce/amd.c

829

if (this_cpu_ptr(smca_banks)[m->bank].paddrv)

arch/x86/kernel/cpu/mce/amd.c

855

void mce_amd_handle_storm(unsigned int bank, bool on)

arch/x86/kernel/cpu/mce/amd.c

857

threshold_restart_bank(bank, on);

arch/x86/kernel/cpu/mce/amd.c

860

static void amd_reset_thr_limit(unsigned int bank)

arch/x86/kernel/cpu/mce/amd.c

862

threshold_restart_bank(bank, true);

arch/x86/kernel/cpu/mce/amd.c

876

amd_reset_thr_limit(m->bank);

arch/x86/kernel/cpu/mce/amd.c

884

mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0);

arch/x86/kernel/cpu/mce/amd.c

891

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/apei.c

115

m->bank = (ctx_info->msr_addr >> 4) & 0xFF;

arch/x86/kernel/cpu/mce/apei.c

50

m->bank = -1;

arch/x86/kernel/cpu/mce/core.c

1009

m->bank = i;

arch/x86/kernel/cpu/mce/core.c

1376

m->bank = i;

arch/x86/kernel/cpu/mce/core.c

183

m->mcgstatus, m->bank, m->status);

arch/x86/kernel/cpu/mce/core.c

2323

int bank = *((int *)arg);

arch/x86/kernel/cpu/mce/core.c

2324

__clear_bit(bank, this_cpu_ptr(mce_poll_banks));

arch/x86/kernel/cpu/mce/core.c

2325

cmci_disable_bank(bank);

arch/x86/kernel/cpu/mce/core.c

2328

void mce_disable_bank(int bank)

arch/x86/kernel/cpu/mce/core.c

2330

if (bank >= this_cpu_read(mce_num_banks)) {

arch/x86/kernel/cpu/mce/core.c

2333

bank);

arch/x86/kernel/cpu/mce/core.c

2336

set_bit(bank, mce_banks_ce_disabled);

arch/x86/kernel/cpu/mce/core.c

2337

on_each_cpu(__mce_disable_bank, &bank, 1);

arch/x86/kernel/cpu/mce/core.c

2535

u8 bank = attr_to_bank(attr)->bank;

arch/x86/kernel/cpu/mce/core.c

2538

if (bank >= per_cpu(mce_num_banks, s->id))

arch/x86/kernel/cpu/mce/core.c

2541

b = &per_cpu(mce_banks_array, s->id)[bank];

arch/x86/kernel/cpu/mce/core.c

2552

u8 bank = attr_to_bank(attr)->bank;

arch/x86/kernel/cpu/mce/core.c

2559

if (bank >= per_cpu(mce_num_banks, s->id))

arch/x86/kernel/cpu/mce/core.c

2562

b = &per_cpu(mce_banks_array, s->id)[bank];

arch/x86/kernel/cpu/mce/core.c

2821

b->bank = i;

arch/x86/kernel/cpu/mce/core.c

357

unsigned bank = __this_cpu_read(injectm.bank);

arch/x86/kernel/cpu/mce/core.c

361

if (msr == mca_msr_reg(bank, MCA_STATUS))

arch/x86/kernel/cpu/mce/core.c

363

if (msr == mca_msr_reg(bank, MCA_ADDR))

arch/x86/kernel/cpu/mce/core.c

365

if (msr == mca_msr_reg(bank, MCA_MISC))

arch/x86/kernel/cpu/mce/core.c

735

m->status = mce_rdmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank));

arch/x86/kernel/cpu/mce/core.c

798

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

81

u8 bank; /* bank number */

arch/x86/kernel/cpu/mce/core.c

837

m->bank = i;

arch/x86/kernel/cpu/mce/core.c

893

quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)

arch/x86/kernel/cpu/mce/core.c

895

if (bank != 0)

arch/x86/kernel/cpu/mce/core.c

976

static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_regs *regs)

arch/x86/kernel/cpu/mce/core.c

978

if (bank != 1)

arch/x86/kernel/cpu/mce/inject.c

477

u8 b = m.bank;

arch/x86/kernel/cpu/mce/inject.c

508

u8 b = i_mce.bank;

arch/x86/kernel/cpu/mce/inject.c

601

m->bank = val;

arch/x86/kernel/cpu/mce/inject.c

637

MCE_INJECT_GET(bank);

arch/x86/kernel/cpu/mce/inject.c

730

u8 bank;

arch/x86/kernel/cpu/mce/inject.c

741

for (bank = 0; bank < MAX_NR_BANKS; ++bank) {

arch/x86/kernel/cpu/mce/inject.c

745

rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);

arch/x86/kernel/cpu/mce/inject.c

751

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), status);

arch/x86/kernel/cpu/mce/inject.c

752

rdmsrq_safe(mca_msr_reg(bank, MCA_STATUS), &status);

arch/x86/kernel/cpu/mce/inject.c

753

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/intel.c

138

static void cmci_set_threshold(int bank, int thresh)

arch/x86/kernel/cpu/mce/intel.c

144

rdmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

146

wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh);

arch/x86/kernel/cpu/mce/intel.c

150

void mce_intel_handle_storm(int bank, bool on)

arch/x86/kernel/cpu/mce/intel.c

153

cmci_set_threshold(bank, CMCI_STORM_THRESHOLD);

arch/x86/kernel/cpu/mce/intel.c

155

cmci_set_threshold(bank, cmci_threshold[bank]);

arch/x86/kernel/cpu/mce/intel.c

176

static bool cmci_skip_bank(int bank, u64 *val)

arch/x86/kernel/cpu/mce/intel.c

180

if (test_bit(bank, owned))

arch/x86/kernel/cpu/mce/intel.c

184

if (test_bit(bank, mce_banks_ce_disabled))

arch/x86/kernel/cpu/mce/intel.c

187

rdmsrq(MSR_IA32_MCx_CTL2(bank), *val);

arch/x86/kernel/cpu/mce/intel.c

191

clear_bit(bank, owned);

arch/x86/kernel/cpu/mce/intel.c

192

__clear_bit(bank, this_cpu_ptr(mce_poll_banks));

arch/x86/kernel/cpu/mce/intel.c

230

static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_wrong_thresh)

arch/x86/kernel/cpu/mce/intel.c

235

wrmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

236

rdmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

240

WARN_ON(!test_bit(bank, this_cpu_ptr(mce_poll_banks)));

arch/x86/kernel/cpu/mce/intel.c

241

storm->banks[bank].poll_only = true;

arch/x86/kernel/cpu/mce/intel.c

246

set_bit(bank, (void *)this_cpu_ptr(&mce_banks_owned));

arch/x86/kernel/cpu/mce/intel.c

249

pr_notice("CPU%d BANK%d CMCI inherited storm\n", smp_processor_id(), bank);

arch/x86/kernel/cpu/mce/intel.c

250

mce_inherit_storm(bank);

arch/x86/kernel/cpu/mce/intel.c

251

cmci_storm_begin(bank);

arch/x86/kernel/cpu/mce/intel.c

253

__clear_bit(bank, this_cpu_ptr(mce_poll_banks));

arch/x86/kernel/cpu/mce/intel.c

267

if (cmci_threshold[bank] == 0)

arch/x86/kernel/cpu/mce/intel.c

268

cmci_threshold[bank] = val & MCI_CTL2_CMCI_THRESHOLD_MASK;

arch/x86/kernel/cpu/mce/intel.c

321

static void __cmci_disable_bank(int bank)

arch/x86/kernel/cpu/mce/intel.c

325

if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))

arch/x86/kernel/cpu/mce/intel.c

327

rdmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

329

wrmsrq(MSR_IA32_MCx_CTL2(bank), val);

arch/x86/kernel/cpu/mce/intel.c

330

__clear_bit(bank, this_cpu_ptr(mce_banks_owned));

arch/x86/kernel/cpu/mce/intel.c

333

cmci_storm_end(bank);

arch/x86/kernel/cpu/mce/intel.c

384

void cmci_disable_bank(int bank)

arch/x86/kernel/cpu/mce/intel.c

393

__cmci_disable_bank(bank);

arch/x86/kernel/cpu/mce/intel.c

512

(m->bank == 0) &&

arch/x86/kernel/cpu/mce/internal.h

153

return m1->bank != m2->bank ||

arch/x86/kernel/cpu/mce/internal.h

272

void mce_amd_handle_storm(unsigned int bank, bool on);

arch/x86/kernel/cpu/mce/internal.h

288

if (this_cpu_ptr(mce_banks_array)[m->bank].lsb_in_status) {

arch/x86/kernel/cpu/mce/internal.h

305

static inline void mce_amd_handle_storm(unsigned int bank, bool on) { }

arch/x86/kernel/cpu/mce/internal.h

330

static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)

arch/x86/kernel/cpu/mce/internal.h

334

case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank);

arch/x86/kernel/cpu/mce/internal.h

335

case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank);

arch/x86/kernel/cpu/mce/internal.h

336

case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank);

arch/x86/kernel/cpu/mce/internal.h

337

case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank);

arch/x86/kernel/cpu/mce/internal.h

342

case MCA_CTL: return MSR_IA32_MCx_CTL(bank);

arch/x86/kernel/cpu/mce/internal.h

343

case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank);

arch/x86/kernel/cpu/mce/internal.h

344

case MCA_MISC: return MSR_IA32_MCx_MISC(bank);

arch/x86/kernel/cpu/mce/internal.h

345

case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank);

arch/x86/kernel/cpu/mce/internal.h

44

void mce_intel_handle_storm(int bank, bool on);

arch/x86/kernel/cpu/mce/internal.h

45

void cmci_disable_bank(int bank);

arch/x86/kernel/cpu/mce/internal.h

52

static inline void mce_intel_handle_storm(int bank, bool on) { }

arch/x86/kernel/cpu/mce/internal.h

53

static inline void cmci_disable_bank(int bank) { }

arch/x86/kernel/cpu/mce/internal.h

64

void cmci_storm_begin(unsigned int bank);

arch/x86/kernel/cpu/mce/internal.h

65

void cmci_storm_end(unsigned int bank);

arch/x86/kernel/cpu/mce/internal.h

67

void mce_inherit_storm(unsigned int bank);

arch/x86/kernel/cpu/mce/internal.h

72

static inline void cmci_storm_begin(unsigned int bank) {}

arch/x86/kernel/cpu/mce/internal.h

73

static inline void cmci_storm_end(unsigned int bank) {}

arch/x86/kernel/cpu/mce/internal.h

75

static inline void mce_inherit_storm(unsigned int bank) {}

arch/x86/kernel/cpu/mce/severity.c

403

if (s->bank_lo && (m->bank < s->bank_lo || m->bank > s->bank_hi))

arch/x86/kernel/cpu/mce/threshold.c

100

void cmci_storm_end(unsigned int bank)

arch/x86/kernel/cpu/mce/threshold.c

105

__clear_bit(bank, this_cpu_ptr(mce_poll_banks));

arch/x86/kernel/cpu/mce/threshold.c

106

storm->banks[bank].history = 0;

arch/x86/kernel/cpu/mce/threshold.c

107

storm->banks[bank].in_storm_mode = false;

arch/x86/kernel/cpu/mce/threshold.c

122

if (storm->banks[mce->bank].poll_only)

arch/x86/kernel/cpu/mce/threshold.c

133

if (!storm->banks[mce->bank].in_storm_mode) {

arch/x86/kernel/cpu/mce/threshold.c

134

delta = now - storm->banks[mce->bank].timestamp;

arch/x86/kernel/cpu/mce/threshold.c

140

history = storm->banks[mce->bank].history << shift;

arch/x86/kernel/cpu/mce/threshold.c

142

storm->banks[mce->bank].timestamp = now;

arch/x86/kernel/cpu/mce/threshold.c

148

storm->banks[mce->bank].history = history;

arch/x86/kernel/cpu/mce/threshold.c

150

if (storm->banks[mce->bank].in_storm_mode) {

arch/x86/kernel/cpu/mce/threshold.c

153

printk_deferred(KERN_NOTICE "CPU%d BANK%d CMCI storm subsided\n", smp_processor_id(), mce->bank);

arch/x86/kernel/cpu/mce/threshold.c

154

mce_handle_storm(mce->bank, false);

arch/x86/kernel/cpu/mce/threshold.c

155

cmci_storm_end(mce->bank);

arch/x86/kernel/cpu/mce/threshold.c

159

printk_deferred(KERN_NOTICE "CPU%d BANK%d CMCI storm detected\n", smp_processor_id(), mce->bank);

arch/x86/kernel/cpu/mce/threshold.c

160

mce_handle_storm(mce->bank, true);

arch/x86/kernel/cpu/mce/threshold.c

161

cmci_storm_begin(mce->bank);

arch/x86/kernel/cpu/mce/threshold.c

48

void mce_inherit_storm(unsigned int bank)

arch/x86/kernel/cpu/mce/threshold.c

59

storm->banks[bank].history = ~0ull;

arch/x86/kernel/cpu/mce/threshold.c

60

storm->banks[bank].timestamp = jiffies;

arch/x86/kernel/cpu/mce/threshold.c

73

static void mce_handle_storm(unsigned int bank, bool on)

arch/x86/kernel/cpu/mce/threshold.c

77

mce_intel_handle_storm(bank, on);

arch/x86/kernel/cpu/mce/threshold.c

80

mce_amd_handle_storm(bank, on);

arch/x86/kernel/cpu/mce/threshold.c

85

void cmci_storm_begin(unsigned int bank)

arch/x86/kernel/cpu/mce/threshold.c

89

__set_bit(bank, this_cpu_ptr(mce_poll_banks));

arch/x86/kernel/cpu/mce/threshold.c

90

storm->banks[bank].in_storm_mode = true;

arch/x86/kvm/hyperv.c

1801

int bank, sbank = 0;

arch/x86/kvm/hyperv.c

1823

for_each_set_bit(bank, (unsigned long *)&valid_bank_mask,

arch/x86/kvm/hyperv.c

1825

bitmap[bank] = sparse_banks[sbank++];

arch/x86/kvm/x86.c

5419

unsigned bank_num = mcg_cap & 0xff, bank;

arch/x86/kvm/x86.c

5432

for (bank = 0; bank < bank_num; bank++) {

arch/x86/kvm/x86.c

5433

vcpu->arch.mce_banks[bank*4] = ~(u64)0;

arch/x86/kvm/x86.c

5435

vcpu->arch.mci_ctl2_banks[bank] = 0;

arch/x86/kvm/x86.c

5472

!(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))

arch/x86/kvm/x86.c

5488

if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))

arch/x86/kvm/x86.c

5491

banks += array_index_nospec(4 * mce->bank, 4 * bank_num);

arch/x86/platform/scx200/scx200_32.c

51

int bank;

arch/x86/platform/scx200/scx200_32.c

54

for (bank = 0; bank < 2; ++bank)

arch/x86/platform/scx200/scx200_32.c

55

scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank);

drivers/acpi/acpi_extlog.c

187

int bank = mce->bank;

drivers/acpi/acpi_extlog.c

196

estatus = extlog_elog_entry_check(cpu, bank);

drivers/acpi/acpi_extlog.c

65

#define ELOG_IDX(cpu, bank) \

drivers/acpi/acpi_extlog.c

66

(cpu_physical_id(cpu) * l1_percpu_entry + (bank))

drivers/acpi/acpi_extlog.c

74

static struct acpi_hest_generic_status *extlog_elog_entry_check(int cpu, int bank)

drivers/acpi/acpi_extlog.c

81

idx = ELOG_IDX(cpu, bank);

drivers/bus/uniphier-system-bus.c

100

for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {

drivers/bus/uniphier-system-bus.c

101

for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) {

drivers/bus/uniphier-system-bus.c

102

if (priv->bank[i].end > priv->bank[j].base &&

drivers/bus/uniphier-system-bus.c

103

priv->bank[i].base < priv->bank[j].end) {

drivers/bus/uniphier-system-bus.c

130

swap(priv->bank[0], priv->bank[1]);

drivers/bus/uniphier-system-bus.c

140

for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {

drivers/bus/uniphier-system-bus.c

141

base = priv->bank[i].base;

drivers/bus/uniphier-system-bus.c

142

end = priv->bank[i].end;

drivers/bus/uniphier-system-bus.c

35

struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS];

drivers/bus/uniphier-system-bus.c

39

int bank, u32 addr, u64 paddr, u32 size)

drivers/bus/uniphier-system-bus.c

45

bank, addr, paddr, size);

drivers/bus/uniphier-system-bus.c

47

if (bank >= ARRAY_SIZE(priv->bank)) {

drivers/bus/uniphier-system-bus.c

48

dev_err(priv->dev, "unsupported bank number %d\n", bank);

drivers/bus/uniphier-system-bus.c

52

if (priv->bank[bank].base || priv->bank[bank].end) {

drivers/bus/uniphier-system-bus.c

54

"range for bank %d has already been specified\n", bank);

drivers/bus/uniphier-system-bus.c

86

priv->bank[bank].base = paddr;

drivers/bus/uniphier-system-bus.c

87

priv->bank[bank].end = end;

drivers/bus/uniphier-system-bus.c

90

bank, priv->bank[bank].base, priv->bank[bank].end);

drivers/char/tpm/tpm2-cmd.c

520

struct tpm_bank_info *bank = chip->allocated_banks + bank_index;

drivers/char/tpm/tpm2-cmd.c

521

struct tpm_digest digest = { .alg_id = bank->alg_id };

drivers/char/tpm/tpm2-cmd.c

531

if (bank->alg_id != tpm2_hash_map[i].tpm_id)

drivers/char/tpm/tpm2-cmd.c

534

bank->digest_size = hash_digest_size[crypto_algo];

drivers/char/tpm/tpm2-cmd.c

535

bank->crypto_id = crypto_algo;

drivers/char/tpm/tpm2-cmd.c

539

bank->crypto_id = HASH_ALGO__LAST;

drivers/char/tpm/tpm2-cmd.c

541

return tpm2_pcr_read(chip, 0, &digest, &bank->digest_size);

drivers/clk/qcom/clk-rcg.c

201

int bank, new_bank, ret, index;

drivers/clk/qcom/clk-rcg.c

216

bank = reg_to_bank(rcg, reg);

drivers/clk/qcom/clk-rcg.c

217

new_bank = enabled ? !bank : bank;

drivers/clk/qcom/clk-rcg.c

295

int bank;

drivers/clk/qcom/clk-rcg.c

301

bank = reg_to_bank(rcg, reg);

drivers/clk/qcom/clk-rcg.c

303

regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

drivers/clk/qcom/clk-rcg.c

306

regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);

drivers/clk/qcom/clk-rcg.c

307

f.m = md_to_m(&rcg->mn[bank], md);

drivers/clk/qcom/clk-rcg.c

308

f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);

drivers/clk/qcom/clk-rcg.c

312

f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;

drivers/clk/qcom/clk-rcg.c

314

f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);

drivers/clk/qcom/clk-rcg.c

371

int bank;

drivers/clk/qcom/clk-rcg.c

377

bank = reg_to_bank(rcg, reg);

drivers/clk/qcom/clk-rcg.c

379

regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

drivers/clk/qcom/clk-rcg.c

383

mn = &rcg->mn[bank];

drivers/clk/qcom/clk-rcg.c

384

regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);

drivers/clk/qcom/clk-rcg.c

394

pre_div = ns_to_pre_div(&rcg->p[bank], ns);

drivers/clk/qcom/clk-rcg.c

449

int bank;

drivers/clk/qcom/clk-rcg.c

453

bank = reg_to_bank(rcg, reg);

drivers/clk/qcom/clk-rcg.c

454

s = &rcg->s[bank];

drivers/clk/qcom/clk-rcg.c

58

static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)

drivers/clk/qcom/clk-rcg.c

60

bank &= BIT(rcg->mux_sel_bit);

drivers/clk/qcom/clk-rcg.c

61

return !!bank;

drivers/clk/qcom/clk-rcg.c

69

int bank;

drivers/clk/qcom/clk-rcg.c

76

bank = reg_to_bank(rcg, reg);

drivers/clk/qcom/clk-rcg.c

77

s = &rcg->s[bank];

drivers/clk/qcom/clk-rcg.c

79

ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

drivers/clk/rockchip/softrst.c

29

int bank, offset;

drivers/clk/rockchip/softrst.c

34

bank = id / softrst->num_per_reg;

drivers/clk/rockchip/softrst.c

39

softrst->reg_base + (bank * 4));

drivers/clk/rockchip/softrst.c

46

reg = readl(softrst->reg_base + (bank * 4));

drivers/clk/rockchip/softrst.c

47

writel(reg | BIT(offset), softrst->reg_base + (bank * 4));

drivers/clk/rockchip/softrst.c

61

int bank, offset;

drivers/clk/rockchip/softrst.c

66

bank = id / softrst->num_per_reg;

drivers/clk/rockchip/softrst.c

70

writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));

drivers/clk/rockchip/softrst.c

77

reg = readl(softrst->reg_base + (bank * 4));

drivers/clk/rockchip/softrst.c

78

writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));

drivers/clk/stm32/reset-stm32.c

39

int bank = id / (reg_width * BITS_PER_BYTE);

drivers/clk/stm32/reset-stm32.c

42

line->offset = bank * reg_width;

drivers/clk/tegra/clk-periph.c

170

const struct tegra_clk_periph_regs *bank;

drivers/clk/tegra/clk-periph.c

186

bank = get_reg_bank(periph->gate.clk_num);

drivers/clk/tegra/clk-periph.c

187

if (!bank)

drivers/clk/tegra/clk-periph.c

196

periph->gate.regs = bank;

drivers/clk/tegra/clk-sdmmc-mux.c

240

const struct tegra_clk_periph_regs *bank;

drivers/clk/tegra/clk-sdmmc-mux.c

249

bank = get_reg_bank(clk_num);

drivers/clk/tegra/clk-sdmmc-mux.c

250

if (!bank)

drivers/clk/tegra/clk-sdmmc-mux.c

262

sdmmc_mux->gate.regs = bank;

drivers/clk/tegra/clk-tegra-periph.c

868

const struct tegra_clk_periph_regs *bank;

drivers/clk/tegra/clk-tegra-periph.c

877

bank = get_reg_bank(data->periph.gate.clk_num);

drivers/clk/tegra/clk-tegra-periph.c

878

if (!bank)

drivers/clk/tegra/clk-tegra-periph.c

881

data->periph.gate.regs = bank;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

78

#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + (bank) * 8)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

80

#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

83

#define ADF_GEN6_CSR_RINGMODECTL(bank) (0x9000 + (bank) * 4)

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

164

u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

166

void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

168

u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

170

void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

172

u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

173

u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

174

u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

175

u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

176

u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

177

u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

178

u32 (*read_csr_c_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

179

u32 (*read_csr_exp_stat)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

180

u32 (*read_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

181

void (*write_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

183

u32 (*read_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

185

void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

187

dma_addr_t (*read_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

189

void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

191

u32 (*read_csr_int_en)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

192

void (*write_csr_int_en)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

194

u32 (*read_csr_int_flag)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

195

void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

197

u32 (*read_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

198

void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

200

u32 bank, u32 value);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

201

u32 (*read_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

202

void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

204

u32 (*read_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

205

void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

208

u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

210

u32 bank, u32 value);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

211

u32 (*read_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

212

void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

100

val = ops->read_csr_int_srcsel(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

102

ops->write_csr_int_srcsel_w_val(base, bank, val);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

110

ops->write_csr_ring_tail(base, bank, rx, state->rings[rx].tail);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

113

ops->write_csr_int_flag_and_col(base, bank, state->iaintflagandcolen);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

114

ops->write_csr_int_en(base, bank, state->iaintflagen);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

115

ops->write_csr_int_col_en(base, bank, state->iaintcolen);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

116

ops->write_csr_int_srcsel_w_val(base, bank, state->iaintflagsrcsel0);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

117

ops->write_csr_exp_int_en(base, bank, state->ringexpintenable);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

118

ops->write_csr_int_col_ctl(base, bank, state->iaintcolctl);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

129

bank, val);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

134

tmp_val = ops->read_csr_exp_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

136

pr_err("Bank %u restored with exception: %#x\n", bank, tmp_val);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

140

ops->write_csr_ring_srv_arb_en(base, bank, state->ringsrvarben);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

144

base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

149

base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

154

base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

159

base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

164

base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

169

base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

19

const char *name, void __iomem *base, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

21

u32 actual_val = op(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

33

u32 bank, struct adf_bank_state *state, u32 num_rings)

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

37

state->ringstat0 = ops->read_csr_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

38

state->ringuostat = ops->read_csr_uo_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

39

state->ringestat = ops->read_csr_e_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

40

state->ringnestat = ops->read_csr_ne_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

41

state->ringnfstat = ops->read_csr_nf_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

42

state->ringfstat = ops->read_csr_f_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

43

state->ringcstat0 = ops->read_csr_c_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

44

state->iaintflagen = ops->read_csr_int_en(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

45

state->iaintflagreg = ops->read_csr_int_flag(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

46

state->iaintflagsrcsel0 = ops->read_csr_int_srcsel(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

47

state->iaintcolen = ops->read_csr_int_col_en(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

48

state->iaintcolctl = ops->read_csr_int_col_ctl(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

49

state->iaintflagandcolen = ops->read_csr_int_flag_and_col(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

50

state->ringexpstat = ops->read_csr_exp_stat(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

51

state->ringexpintenable = ops->read_csr_exp_int_en(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

52

state->ringsrvarben = ops->read_csr_ring_srv_arb_en(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

55

state->rings[i].head = ops->read_csr_ring_head(base, bank, i);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

56

state->rings[i].tail = ops->read_csr_ring_tail(base, bank, i);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

57

state->rings[i].config = ops->read_csr_ring_config(base, bank, i);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

58

state->rings[i].base = ops->read_csr_ring_base(base, bank, i);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

63

u32 bank, struct adf_bank_state *state, u32 num_rings,

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

70

ops->write_csr_ring_base(base, bank, i, state->rings[i].base);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

73

ops->write_csr_ring_config(base, bank, i, state->rings[i].config);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

79

ops->write_csr_ring_head(base, bank, tx, state->rings[tx].head);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

80

ops->write_csr_ring_tail(base, bank, tx, state->rings[tx].tail);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

88

val = ops->read_csr_int_srcsel(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

90

ops->write_csr_int_srcsel_w_val(base, bank, val);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

91

ops->write_csr_ring_head(base, bank, tx, state->rings[tx].head);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

94

ops->write_csr_ring_tail(base, bank, rx, state->rings[rx].tail);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

95

val = ops->read_csr_int_srcsel(base, bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

97

ops->write_csr_int_srcsel_w_val(base, bank, val);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

99

ops->write_csr_ring_head(base, bank, rx, state->rings[rx].head);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

11

static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

13

return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

16

static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

19

WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

22

static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

24

return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

27

static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

30

WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

33

static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

35

return READ_CSR_E_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

38

static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

41

WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

44

static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

47

WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

50

static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

52

WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

55

static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

57

WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

60

static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

63

WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

66

static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

69

WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

72

static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

75

WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

78

static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

81

WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

30

#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

31

ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

33

#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

34

ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

36

#define READ_CSR_E_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

37

ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

39

#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

40

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

42

#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

47

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

49

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

53

#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

54

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

56

#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

57

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

59

#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

60

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

62

#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

64

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

66

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

69

#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

70

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

72

#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

73

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

76

#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

77

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_config.c

19

unsigned long bank, val;

drivers/crypto/intel/qat/qat_common/adf_gen4_config.c

31

bank = i * 2;

drivers/crypto/intel/qat/qat_common/adf_gen4_config.c

34

key, &bank, ADF_DEC);

drivers/crypto/intel/qat/qat_common/adf_gen4_config.c

38

bank += 1;

drivers/crypto/intel/qat/qat_common/adf_gen4_config.c

41

key, &bank, ADF_DEC);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

102

static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

105

WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

108

static u32 read_csr_int_en(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

11

static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

110

return READ_CSR_INT_EN(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

113

static void write_csr_int_en(void __iomem *csr_base_addr, u32 bank, u32 value)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

115

WRITE_CSR_INT_EN(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

118

static u32 read_csr_int_flag(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

120

return READ_CSR_INT_FLAG(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

123

static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

126

WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

129

static u32 read_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

13

return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

131

return READ_CSR_INT_SRCSEL(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

134

static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

136

WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

139

static void write_csr_int_srcsel_w_val(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

142

WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

145

static u32 read_csr_int_col_en(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

147

return READ_CSR_INT_COL_EN(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

150

static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

152

WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

155

static u32 read_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

157

return READ_CSR_INT_COL_CTL(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

16

static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

160

static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

163

WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

166

static u32 read_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

168

return READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

171

static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

174

WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

177

static u32 read_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

179

return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

182

static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

185

WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

19

WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

22

static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

24

return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

27

static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

30

WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

33

static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

35

return READ_CSR_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

38

static u32 read_csr_uo_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

40

return READ_CSR_UO_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

43

static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

45

return READ_CSR_E_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

48

static u32 read_csr_ne_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

50

return READ_CSR_NE_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

53

static u32 read_csr_nf_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

55

return READ_CSR_NF_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

58

static u32 read_csr_f_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

60

return READ_CSR_F_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

63

static u32 read_csr_c_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

65

return READ_CSR_C_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

68

static u32 read_csr_exp_stat(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

70

return READ_CSR_EXP_STAT(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

73

static u32 read_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

75

return READ_CSR_EXP_INT_EN(csr_base_addr, bank);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

78

static void write_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

81

WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

84

static u32 read_csr_ring_config(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

87

return READ_CSR_RING_CONFIG(csr_base_addr, bank, ring);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

90

static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

93

WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

96

static dma_addr_t read_csr_ring_base(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

99

return READ_CSR_RING_BASE(csr_base_addr, bank, ring);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

101

static inline u64 read_base(void __iomem *csr_base_addr, u32 bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

109

l_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) +

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

111

u_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) +

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

117

#define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

118

read_base((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, (bank), (ring))

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

120

#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

122

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

124

#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

126

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

128

#define READ_CSR_INT_EN(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

130

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_FLAG_EN)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

131

#define WRITE_CSR_INT_EN(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

133

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

135

#define READ_CSR_INT_FLAG(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

137

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_FLAG)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

138

#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

140

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

142

#define READ_CSR_INT_SRCSEL(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

144

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_SRCSEL)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

145

#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

147

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

149

#define WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

151

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

153

#define READ_CSR_INT_COL_EN(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

155

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_COL_EN)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

156

#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

158

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

160

#define READ_CSR_INT_COL_CTL(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

162

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_COL_CTL)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

163

#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

165

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

168

#define READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

170

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

172

#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

174

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

177

#define READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

179

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

181

#define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

183

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

37

#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

39

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

41

#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

43

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

45

#define READ_CSR_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

47

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

48

#define READ_CSR_UO_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

50

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

51

#define READ_CSR_E_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

53

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

54

#define READ_CSR_NE_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

56

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_NE_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

57

#define READ_CSR_NF_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

59

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_NF_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

60

#define READ_CSR_F_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

62

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_F_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

63

#define READ_CSR_C_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

65

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_C_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

66

#define READ_CSR_EXP_STAT(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

68

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_EXP_STAT)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

69

#define READ_CSR_EXP_INT_EN(csr_base_addr, bank) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

71

ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_EXP_INT_EN)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

72

#define WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

74

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

76

#define READ_CSR_RING_CONFIG(csr_base_addr, bank, ring) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

78

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

80

#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

82

ADF_RING_BUNDLE_SIZE * (bank) + \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

84

#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

87

u32 _bank = bank; \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

82

#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3))

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

84

#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

89

#define ADF_WQM_CSR_RPINTSOU(bank) (0x200000 + ((bank) << 12))

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

50

struct adf_accel_dev *accel_dev = ring->bank->accel_dev;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

65

arben_tx = (ring->bank->ring_mask & tx_ring_mask) >> 0;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

66

arben_rx = (ring->bank->ring_mask & rx_ring_mask) >> shift;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

69

csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

70

ring->bank->bank_number, arben);

drivers/crypto/intel/qat/qat_common/adf_isr.c

215

struct adf_etr_bank_data *bank = &etr_data->banks[i];

drivers/crypto/intel/qat/qat_common/adf_isr.c

230

&name[0], bank);

drivers/crypto/intel/qat/qat_common/adf_isr.c

49

struct adf_etr_bank_data *bank = bank_ptr;

drivers/crypto/intel/qat/qat_common/adf_isr.c

50

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_isr.c

52

csr_ops->write_csr_int_flag_and_col(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_isr.c

54

tasklet_hi_schedule(&bank->resp_handler);

drivers/crypto/intel/qat/qat_common/adf_transport.c

104

csr_ops->write_csr_ring_tail(ring->bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_transport.c

105

ring->bank->bank_number, ring->ring_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

114

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

129

csr_ops->write_csr_ring_head(ring->bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_transport.c

130

ring->bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

138

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

141

csr_ops->write_csr_ring_config(ring->bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_transport.c

142

ring->bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

149

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

155

csr_ops->write_csr_ring_config(ring->bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_transport.c

156

ring->bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

162

struct adf_etr_bank_data *bank = ring->bank;

drivers/crypto/intel/qat/qat_common/adf_transport.c

163

struct adf_accel_dev *accel_dev = bank->accel_dev;

drivers/crypto/intel/qat/qat_common/adf_transport.c

196

csr_ops->write_csr_ring_base(ring->bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_transport.c

197

ring->bank->bank_number, ring->ring_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

211

dma_free_coherent(&GET_DEV(ring->bank->accel_dev),

drivers/crypto/intel/qat/qat_common/adf_transport.c

225

struct adf_etr_bank_data *bank;

drivers/crypto/intel/qat/qat_common/adf_transport.c

261

bank = &transport_data->banks[bank_num];

drivers/crypto/intel/qat/qat_common/adf_transport.c

262

if (adf_reserve_ring(bank, ring_num)) {

drivers/crypto/intel/qat/qat_common/adf_transport.c

267

ring = &bank->rings[ring_num];

drivers/crypto/intel/qat/qat_common/adf_transport.c

269

ring->bank = bank;

drivers/crypto/intel/qat/qat_common/adf_transport.c

294

adf_enable_ring_irq(bank, ring->ring_number);

drivers/crypto/intel/qat/qat_common/adf_transport.c

299

adf_unreserve_ring(bank, ring_num);

drivers/crypto/intel/qat/qat_common/adf_transport.c

306

struct adf_etr_bank_data *bank = ring->bank;

drivers/crypto/intel/qat/qat_common/adf_transport.c

307

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

310

adf_disable_ring_irq(bank, ring->ring_number);

drivers/crypto/intel/qat/qat_common/adf_transport.c

314

csr_ops->write_csr_ring_config(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

316

csr_ops->write_csr_ring_base(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

319

adf_unreserve_ring(bank, ring->ring_number);

drivers/crypto/intel/qat/qat_common/adf_transport.c

325

static void adf_ring_response_handler(struct adf_etr_bank_data *bank)

drivers/crypto/intel/qat/qat_common/adf_transport.c

327

struct adf_accel_dev *accel_dev = bank->accel_dev;

drivers/crypto/intel/qat/qat_common/adf_transport.c

333

empty_rings = csr_ops->read_csr_e_stat(bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_transport.c

334

bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport.c

335

empty_rings = ~empty_rings & bank->irq_mask;

drivers/crypto/intel/qat/qat_common/adf_transport.c

338

adf_handle_response(&bank->rings[i]);

drivers/crypto/intel/qat/qat_common/adf_transport.c

343

struct adf_etr_bank_data *bank = (void *)bank_addr;

drivers/crypto/intel/qat/qat_common/adf_transport.c

344

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

347

adf_ring_response_handler(bank);

drivers/crypto/intel/qat/qat_common/adf_transport.c

349

csr_ops->write_csr_int_flag_and_col(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

350

bank->irq_mask);

drivers/crypto/intel/qat/qat_common/adf_transport.c

370

static void adf_get_coalesc_timer(struct adf_etr_bank_data *bank,

drivers/crypto/intel/qat/qat_common/adf_transport.c

374

if (adf_get_cfg_int(bank->accel_dev, section,

drivers/crypto/intel/qat/qat_common/adf_transport.c

376

bank_num_in_accel, &bank->irq_coalesc_timer))

drivers/crypto/intel/qat/qat_common/adf_transport.c

377

bank->irq_coalesc_timer = ADF_COALESCING_DEF_TIME;

drivers/crypto/intel/qat/qat_common/adf_transport.c

379

if (ADF_COALESCING_MAX_TIME < bank->irq_coalesc_timer ||

drivers/crypto/intel/qat/qat_common/adf_transport.c

380

ADF_COALESCING_MIN_TIME > bank->irq_coalesc_timer)

drivers/crypto/intel/qat/qat_common/adf_transport.c

381

bank->irq_coalesc_timer = ADF_COALESCING_DEF_TIME;

drivers/crypto/intel/qat/qat_common/adf_transport.c

385

struct adf_etr_bank_data *bank,

drivers/crypto/intel/qat/qat_common/adf_transport.c

398

memset(bank, 0, sizeof(*bank));

drivers/crypto/intel/qat/qat_common/adf_transport.c

399

bank->bank_number = bank_num;

drivers/crypto/intel/qat/qat_common/adf_transport.c

40

static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_transport.c

400

bank->csr_addr = csr_addr;

drivers/crypto/intel/qat/qat_common/adf_transport.c

401

bank->accel_dev = accel_dev;

drivers/crypto/intel/qat/qat_common/adf_transport.c

402

spin_lock_init(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

406

bank->rings = kzalloc_node(size, GFP_KERNEL,

drivers/crypto/intel/qat/qat_common/adf_transport.c

408

if (!bank->rings)

drivers/crypto/intel/qat/qat_common/adf_transport.c

417

adf_get_coalesc_timer(bank, "Accelerator0", bank_num);

drivers/crypto/intel/qat/qat_common/adf_transport.c

419

bank->irq_coalesc_timer = ADF_COALESCING_MIN_TIME;

drivers/crypto/intel/qat/qat_common/adf_transport.c

42

spin_lock(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

425

ring = &bank->rings[i];

drivers/crypto/intel/qat/qat_common/adf_transport.c

43

if (bank->ring_mask & (1 << ring)) {

drivers/crypto/intel/qat/qat_common/adf_transport.c

439

tx_ring = &bank->rings[i - hw_data->tx_rx_gap];

drivers/crypto/intel/qat/qat_common/adf_transport.c

44

spin_unlock(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

443

if (adf_bank_debugfs_add(bank)) {

drivers/crypto/intel/qat/qat_common/adf_transport.c

456

ring = &bank->rings[i];

drivers/crypto/intel/qat/qat_common/adf_transport.c

460

kfree(bank->rings);

drivers/crypto/intel/qat/qat_common/adf_transport.c

47

bank->ring_mask |= (1 << ring);

drivers/crypto/intel/qat/qat_common/adf_transport.c

48

spin_unlock(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

52

static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_transport.c

522

static void cleanup_bank(struct adf_etr_bank_data *bank)

drivers/crypto/intel/qat/qat_common/adf_transport.c

524

struct adf_accel_dev *accel_dev = bank->accel_dev;

drivers/crypto/intel/qat/qat_common/adf_transport.c

530

struct adf_etr_ring_data *ring = &bank->rings[i];

drivers/crypto/intel/qat/qat_common/adf_transport.c

532

if (bank->ring_mask & (1 << i))

drivers/crypto/intel/qat/qat_common/adf_transport.c

538

kfree(bank->rings);

drivers/crypto/intel/qat/qat_common/adf_transport.c

539

adf_bank_debugfs_rm(bank);

drivers/crypto/intel/qat/qat_common/adf_transport.c

54

spin_lock(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

540

memset(bank, 0, sizeof(*bank));

drivers/crypto/intel/qat/qat_common/adf_transport.c

55

bank->ring_mask &= ~(1 << ring);

drivers/crypto/intel/qat/qat_common/adf_transport.c

56

spin_unlock(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

59

static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_transport.c

61

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

63

spin_lock_bh(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

64

bank->irq_mask |= (1 << ring);

drivers/crypto/intel/qat/qat_common/adf_transport.c

65

spin_unlock_bh(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

66

csr_ops->write_csr_int_col_en(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

67

bank->irq_mask);

drivers/crypto/intel/qat/qat_common/adf_transport.c

68

csr_ops->write_csr_int_col_ctl(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

69

bank->irq_coalesc_timer);

drivers/crypto/intel/qat/qat_common/adf_transport.c

72

static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, u32 ring)

drivers/crypto/intel/qat/qat_common/adf_transport.c

74

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport.c

76

spin_lock_bh(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

77

bank->irq_mask &= ~(1 << ring);

drivers/crypto/intel/qat/qat_common/adf_transport.c

78

spin_unlock_bh(&bank->lock);

drivers/crypto/intel/qat/qat_common/adf_transport.c

79

csr_ops->write_csr_int_col_en(bank->csr_addr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport.c

80

bank->irq_mask);

drivers/crypto/intel/qat/qat_common/adf_transport.c

90

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

111

ring->bank->bank_debug_dir,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

128

struct adf_etr_bank_data *bank = sfile->private;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

129

u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

143

struct adf_etr_bank_data *bank = sfile->private;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

144

u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

154

struct adf_etr_bank_data *bank = sfile->private;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

155

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

159

bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

162

struct adf_etr_ring_data *ring = &bank->rings[ring_id];

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

163

void __iomem *csr = bank->csr_addr;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

166

if (!(bank->ring_mask & 1 << ring_id))

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

169

head = csr_ops->read_csr_ring_head(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

171

tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

173

empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

198

int adf_bank_debugfs_add(struct adf_etr_bank_data *bank)

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

200

struct adf_accel_dev *accel_dev = bank->accel_dev;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

204

snprintf(name, sizeof(name), "bank_%02d", bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

205

bank->bank_debug_dir = debugfs_create_dir(name, parent);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

206

bank->bank_debug_cfg = debugfs_create_file("config", S_IRUSR,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

207

bank->bank_debug_dir, bank,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

212

void adf_bank_debugfs_rm(struct adf_etr_bank_data *bank)

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

214

debugfs_remove(bank->bank_debug_cfg);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

215

debugfs_remove(bank->bank_debug_dir);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

51

struct adf_etr_bank_data *bank = ring->bank;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

52

struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

53

void __iomem *csr = ring->bank->csr_addr;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

58

head = csr_ops->read_csr_ring_head(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

60

tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

62

empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

68

ring->ring_number, ring->bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport_internal.h

19

struct adf_etr_bank_data *bank;

drivers/crypto/intel/qat/qat_common/adf_transport_internal.h

53

int adf_bank_debugfs_add(struct adf_etr_bank_data *bank);

drivers/crypto/intel/qat/qat_common/adf_transport_internal.h

54

void adf_bank_debugfs_rm(struct adf_etr_bank_data *bank);

drivers/crypto/intel/qat/qat_common/adf_transport_internal.h

58

static inline int adf_bank_debugfs_add(struct adf_etr_bank_data *bank)

drivers/crypto/intel/qat/qat_common/adf_transport_internal.h

63

#define adf_bank_debugfs_rm(bank) do {} while (0)

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

168

struct adf_etr_bank_data *bank = &etr_data->banks[0];

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

171

csr_ops->write_csr_int_flag_and_col(bank->csr_addr,

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

172

bank->bank_number, 0);

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

173

tasklet_hi_schedule(&bank->resp_handler);

drivers/crypto/intel/qat/qat_common/qat_compression.c

120

unsigned long bank;

drivers/crypto/intel/qat/qat_common/qat_compression.c

153

ret = kstrtoul(val, 10, &bank);

drivers/crypto/intel/qat/qat_common/qat_compression.c

168

ret = adf_create_ring(accel_dev, SEC, bank, num_msg_dc,

drivers/crypto/intel/qat/qat_common/qat_compression.c

175

ret = adf_create_ring(accel_dev, SEC, bank, num_msg_dc,

drivers/cxl/core/edac.c

1005

rec->bank == attrbs->bank &&

drivers/cxl/core/edac.c

1190

u8 bank;

drivers/cxl/core/edac.c

1254

u8 bank;

drivers/cxl/core/edac.c

1307

attrbs.bank = ctx->bank;

drivers/cxl/core/edac.c

1315

attrbs.bank = ctx->bank;

drivers/cxl/core/edac.c

1321

attrbs.bank = ctx->bank;

drivers/cxl/core/edac.c

1387

sparing_pi.bank = cxl_sparing_ctx->bank;

drivers/cxl/core/edac.c

1443

CXL_SPARING_GET_ATTR(bank, u32)

drivers/cxl/core/edac.c

1462

CXL_SPARING_SET_ATTR(bank, u32)

drivers/cxl/core/edac.c

911

u8 bank;

drivers/cxl/core/edac.c

971

rec->bank == attrbs->bank &&

drivers/cxl/core/edac.c

990

rec->bank == attrbs->bank &&

drivers/cxl/core/trace.h

618

__field(u8, bank) /* Out of order to pack trace record */

drivers/cxl/core/trace.h

646

__entry->bank = rec->bank;

drivers/cxl/core/trace.h

684

__entry->bank_group, __entry->bank,

drivers/cxl/core/trace.h

946

__field(u8, bank)

drivers/cxl/core/trace.h

966

__entry->bank = rec->bank;

drivers/cxl/core/trace.h

984

__entry->nibble_mask, __entry->bank_group, __entry->bank,

drivers/dma/ti/edma.c

1497

u32 bank;

drivers/dma/ti/edma.c

1511

bank = 1;

drivers/dma/ti/edma.c

1514

bank = 0;

drivers/dma/ti/edma.c

1525

channel = (bank << 5) | slot;

drivers/dma/ti/edma.c

1527

edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));

drivers/edac/al_mc_edac.c

104

bank = FIELD_GET(AL_MC_ECC_CE_ADDR1_BANK, ecccaddr1);

drivers/edac/al_mc_edac.c

108

rank, row, bg, bank, column,

drivers/edac/al_mc_edac.c

126

u8 rank, bg, bank;

drivers/edac/al_mc_edac.c

149

bank = FIELD_GET(AL_MC_ECC_UE_ADDR1_BANK, eccuaddr1);

drivers/edac/al_mc_edac.c

153

rank, row, bg, bank, column,

drivers/edac/al_mc_edac.c

65

u8 rank, u32 row, u8 bg, u8 bank, u16 column,

drivers/edac/al_mc_edac.c

71

rank, row, bg, bank, column, syn0, syn1, syn2);

drivers/edac/al_mc_edac.c

81

u8 rank, bg, bank;

drivers/edac/amd64_edac.c

1047

if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2)

drivers/edac/armada_xp_edac.c

105

((bank & 0x7) << 16) |

drivers/edac/armada_xp_edac.c

110

((bank & 0x7) << 12) |

drivers/edac/armada_xp_edac.c

117

((bank & 0x7) << 16) |

drivers/edac/armada_xp_edac.c

122

((bank & 0x7) << 11) |

drivers/edac/armada_xp_edac.c

85

uint8_t cs, uint8_t bank, uint16_t row,

drivers/edac/armada_xp_edac.c

93

((bank & 0x7) << 16) |

drivers/edac/armada_xp_edac.c

98

((bank & 0x7) << 13) |

drivers/edac/cpc925_edac.c

438

u32 bcnt, rank, col, bank, row;

drivers/edac/cpc925_edac.c

446

bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT;

drivers/edac/cpc925_edac.c

471

pa |= bank << 19;

drivers/edac/dmc520_edac.c

107

u32 bank;

drivers/edac/dmc520_edac.c

247

info->bank = FIELD_GET(REG_FIELD_ERR_INFO_HIGH_BANK, reg_val_high);

drivers/edac/dmc520_edac.c

381

info.rank, info.bank,

drivers/edac/ghes_edac.c

102

const char *bank = NULL, *device = NULL;

drivers/edac/ghes_edac.c

104

dmi_memdev_name(handle, &bank, &device);

drivers/edac/ghes_edac.c

111

(bank && *bank) ? bank : "",

drivers/edac/ghes_edac.c

112

(bank && *bank && device && *device) ? " " : "",

drivers/edac/i10nm_base.c

562

u8 bank;

drivers/edac/i10nm_base.c

571

bank = mce->bank;

drivers/edac/i10nm_base.c

576

if (!(ICX_IMCx_CHy & (1 << bank)))

drivers/edac/i10nm_base.c

580

if (bank < 13 || bank > 20)

drivers/edac/i10nm_base.c

601

u8 bank;

drivers/edac/i10nm_base.c

616

bank = m->bank - 13;

drivers/edac/i10nm_base.c

617

res->imc = bank / 4;

drivers/edac/i10nm_base.c

618

res->channel = bank % 2;

drivers/edac/i10nm_base.c

629

bank = m->bank - 13;

drivers/edac/i10nm_base.c

630

res->imc = bank / 2;

drivers/edac/i10nm_base.c

631

res->channel = bank % 2;

drivers/edac/i5000_edac.c

468

int bank;

drivers/edac/i5000_edac.c

481

bank = NREC_BANK(info->nrecmema);

drivers/edac/i5000_edac.c

488

rank, channel, bank,

drivers/edac/i5000_edac.c

525

bank, ras, cas, allErrors, specific);

drivers/edac/i5000_edac.c

553

int bank;

drivers/edac/i5000_edac.c

576

bank = NREC_BANK(info->nrecmema);

drivers/edac/i5000_edac.c

583

rank, channel, channel + 1, branch >> 1, bank,

drivers/edac/i5000_edac.c

624

rank, bank, ras, cas, ue_errors, specific);

drivers/edac/i5000_edac.c

648

bank = REC_BANK(info->recmema);

drivers/edac/i5000_edac.c

655

rank, channel, branch >> 1, bank,

drivers/edac/i5000_edac.c

676

"CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,

drivers/edac/i5100_edac.c

429

unsigned bank,

drivers/edac/i5100_edac.c

441

bank, cas, ras);

drivers/edac/i5100_edac.c

451

unsigned bank,

drivers/edac/i5100_edac.c

463

bank, cas, ras);

drivers/edac/i5100_edac.c

480

unsigned bank;

drivers/edac/i5100_edac.c

498

bank = i5100_recmema_bank(dw2);

drivers/edac/i5100_edac.c

512

i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);

drivers/edac/i5100_edac.c

520

bank = i5100_nrecmema_bank(dw2);

drivers/edac/i5100_edac.c

534

i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);

drivers/edac/i5400_edac.c

520

int bank;

drivers/edac/i5400_edac.c

546

bank = nrec_bank(info);

drivers/edac/i5400_edac.c

554

type, rank, channel, channel + 1, branch >> 1, bank,

drivers/edac/i5400_edac.c

563

bank, buf_id, ras, cas, allErrors, error_name[errnum]);

drivers/edac/i5400_edac.c

585

int bank;

drivers/edac/i5400_edac.c

617

bank = rec_bank(info);

drivers/edac/i5400_edac.c

627

rank, channel, branch >> 1, bank,

drivers/edac/i5400_edac.c

634

branch >> 1, bank, rdwr_str(rdwr), ras, cas,

drivers/edac/i7300_edac.c

412

unsigned branch, channel, bank, rank, cas, ras;

drivers/edac/i7300_edac.c

433

bank = NRECMEMA_BANK(val16);

drivers/edac/i7300_edac.c

448

bank, ras, cas, errors, specific);

drivers/edac/i7300_edac.c

472

bank = RECMEMA_BANK(val16);

drivers/edac/i7300_edac.c

495

bank, ras, cas, errors, specific);

drivers/edac/i7core_edac.c

1829

if (mce->bank != 8)

drivers/edac/i7core_edac.c

218

int channel, dimm, rank, bank, page, col;

drivers/edac/i7core_edac.c

2211

pvt->inject.bank = -1;

drivers/edac/i7core_edac.c

416

static inline int numbank(u32 bank)

drivers/edac/i7core_edac.c

420

return banks[bank & 0x3];

drivers/edac/i7core_edac.c

853

DECLARE_ADDR_MATCH(bank, 32);

drivers/edac/i7core_edac.c

860

ATTR_ADDR_MATCH(bank);

drivers/edac/i7core_edac.c

955

if (pvt->inject.bank < 0)

drivers/edac/i7core_edac.c

958

mask |= (pvt->inject.bank & 0x15LL) << 30;

drivers/edac/ie31200_edac.c

567

mce->bank, mce->status);

drivers/edac/igen6_edac.c

1050

mce->bank, mce->status);

drivers/edac/mce_amd.c

735

enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);

drivers/edac/mce_amd.c

742

pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);

drivers/edac/mce_amd.c

810

m->bank,

drivers/edac/mce_amd.c

819

rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config_lo, &dummy);

drivers/edac/mce_amd.c

836

if (fam != 0x15 || m->bank != 4)

drivers/edac/mce_amd.c

880

switch (m->bank) {

drivers/edac/mem_repair.c

126

MR_ATTR_STORE(bank, set_bank, unsigned long, kstrtoul)

drivers/edac/mem_repair.c

301

[MR_BANK] = __ATTR_RW(bank),

drivers/edac/mem_repair.c

90

MR_ATTR_SHOW(bank, get_bank, u32, "%u\n")

drivers/edac/octeon_edac-lmc.c

158

TEMPLATE_SHOW(bank);

drivers/edac/octeon_edac-lmc.c

159

TEMPLATE_STORE(bank);

drivers/edac/octeon_edac-lmc.c

205

static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,

drivers/edac/octeon_edac-lmc.c

33

unsigned long bank;

drivers/edac/octeon_edac-lmc.c

95

fadr.cn61xx.fbank = pvt->bank;

drivers/edac/pnd2_edac.c

1000

daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2);

drivers/edac/pnd2_edac.c

1003

daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2);

drivers/edac/pnd2_edac.c

1004

daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 3);

drivers/edac/pnd2_edac.c

1006

daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 0);

drivers/edac/pnd2_edac.c

1007

daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 1);

drivers/edac/pnd2_edac.c

1009

daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2);

drivers/edac/pnd2_edac.c

1011

daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2);

drivers/edac/pnd2_edac.c

1117

addr, pmiaddr, daddr->chan, daddr->dimm, daddr->rank, daddr->bank, daddr->row, daddr->col);

drivers/edac/pnd2_edac.c

1187

errcode, daddr->chan, daddr->dimm, daddr->rank, daddr->row, daddr->bank, daddr->col);

drivers/edac/pnd2_edac.c

1394

mce->extcpu, type, mce->mcgstatus, mce->bank, mce->status);

drivers/edac/pnd2_edac.c

1440

m.addr, daddr.chan, daddr.dimm, daddr.rank, daddr.bank, daddr.row, daddr.col);

drivers/edac/pnd2_edac.c

59

int bank;

drivers/edac/pnd2_edac.c

912

int column = 0, bank = 0, row = 0, rank = 0;

drivers/edac/pnd2_edac.c

941

bank |= (bit << idx);

drivers/edac/pnd2_edac.c

943

bank ^= bank_hash(pmiaddr, idx, d->addrdec);

drivers/edac/pnd2_edac.c

964

daddr->bank = bank;

drivers/edac/pnd2_edac.c

989

daddr->bank = dnv_get_bit(pmiaddr, dmap[pmiidx].ba0 + 6, 0);

drivers/edac/pnd2_edac.c

990

daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].ba1 + 6, 1);

drivers/edac/pnd2_edac.c

991

daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg0 + 6, 2);

drivers/edac/pnd2_edac.c

993

daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg1 + 6, 3);

drivers/edac/pnd2_edac.c

996

daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 0);

drivers/edac/pnd2_edac.c

997

daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row7 + 6, 1);

drivers/edac/qcom_edac.c

207

dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)

drivers/edac/qcom_edac.c

218

ret = regmap_read(drv->regmaps[bank], synd_reg,

drivers/edac/qcom_edac.c

227

ret = regmap_read(drv->regmaps[bank], regs.count_status_reg,

drivers/edac/qcom_edac.c

237

ret = regmap_read(drv->regmaps[bank], regs.ways_status_reg,

drivers/edac/qcom_edac.c

253

dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)

drivers/edac/qcom_edac.c

258

ret = dump_syn_reg_values(drv, bank, err_type);

drivers/edac/qcom_edac.c

264

edac_device_handle_ce(edev_ctl, 0, bank,

drivers/edac/qcom_edac.c

268

edac_device_handle_ue(edev_ctl, 0, bank,

drivers/edac/qcom_edac.c

272

edac_device_handle_ce(edev_ctl, 0, bank,

drivers/edac/qcom_edac.c

276

edac_device_handle_ue(edev_ctl, 0, bank,

drivers/edac/sb_edac.c

1016

static u8 sbridge_get_ha(u8 bank)

drivers/edac/sb_edac.c

1026

static u8 ibridge_get_ha(u8 bank)

drivers/edac/sb_edac.c

1028

switch (bank) {

drivers/edac/sb_edac.c

1030

return bank - 7;

drivers/edac/sb_edac.c

1032

return (bank - 9) / 4;

drivers/edac/sb_edac.c

1039

static u8 knl_get_ha(u8 bank)

drivers/edac/sb_edac.c

2390

*ha = pvt->info.get_ha(m->bank);

drivers/edac/sb_edac.c

2392

sprintf(msg, "Impossible bank %d", m->bank);

drivers/edac/sb_edac.c

3158

m->bank);

drivers/edac/sb_edac.c

3168

channel = knl_channel_remap(m->bank == 16, channel);

drivers/edac/sb_edac.c

3299

mce->mcgstatus, mce->bank, mce->status);

drivers/edac/sb_edac.c

331

u8 (*get_ha)(u8 bank);

drivers/edac/skx_common.c

767

pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank);

drivers/edac/skx_common.c

792

mce->mcgstatus, mce->bank, mce->status);

drivers/edac/synopsys_edac.c

1027

bank |= (((hif_addr >> priv->bank_shift[index]) &

drivers/edac/synopsys_edac.c

1049

regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;

drivers/edac/synopsys_edac.c

280

u32 bank;

drivers/edac/synopsys_edac.c

391

p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;

drivers/edac/synopsys_edac.c

405

p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;

drivers/edac/synopsys_edac.c

466

p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>

drivers/edac/synopsys_edac.c

484

p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>

drivers/edac/synopsys_edac.c

518

"CE", pinf->row, pinf->bank,

drivers/edac/synopsys_edac.c

524

"CE", pinf->row, pinf->bank, pinf->col,

drivers/edac/synopsys_edac.c

538

"UE", pinf->row, pinf->bank,

drivers/edac/synopsys_edac.c

543

"UE", pinf->row, pinf->bank, pinf->col);

drivers/edac/synopsys_edac.c

997

int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;

drivers/edac/thunderx_edac.c

488

int bank, xbits;

drivers/edac/thunderx_edac.c

496

bank = LMC_FADR_FBANK(faddr) << lmc->bank_lsb;

drivers/edac/thunderx_edac.c

499

bank ^= get_bits(addr, 12 + lmc->xbits, lmc->bank_width);

drivers/edac/thunderx_edac.c

501

addr |= bank << lmc->bank_lsb;

drivers/edac/versal_edac.c

166

u32 bank:2;

drivers/edac/versal_edac.c

383

err_addr |= (pinf.bank & BIT(0)) << priv->bank_bit[index];

drivers/edac/versal_edac.c

384

pinf.bank >>= 1;

drivers/edac/versal_edac.c

684

u32 col = 0, row = 0, bank = 0, grp = 0, rank = 0, lrank = 0, ch = 0;

drivers/edac/versal_edac.c

698

bank |= (((priv->err_inject_addr >> priv->bank_bit[index]) &

drivers/edac/versal_edac.c

728

regval |= FIELD_PREP(XDDR_NOC_BANK_MATCH_MASK, bank);

drivers/edac/versalnet_edac.c

359

err_addr |= (pinf.bank & BIT(0)) << (reg & MASK_0);

drivers/edac/versalnet_edac.c

360

pinf.bank >>= MC5_EACHBIT;

drivers/edac/versalnet_edac.c

361

err_addr |= (pinf.bank & BIT(0)) << FIELD_GET(MC5_BANK1_MASK, reg);

drivers/edac/versalnet_edac.c

362

pinf.bank >>= MC5_EACHBIT;

drivers/edac/versalnet_edac.c

364

err_addr |= (pinf.bank & BIT(0)) << FIELD_GET(MC5_GRP_0_MASK, reg);

drivers/edac/versalnet_edac.c

366

err_addr |= (pinf.bank & BIT(0)) << FIELD_GET(MC5_GRP_1_MASK, reg);

drivers/edac/versalnet_edac.c

368

err_addr |= (pinf.bank & BIT(0)) << FIELD_GET(MASK_24, reg);

drivers/edac/versalnet_edac.c

92

u32 bank:2;

drivers/edac/xgene_edac.c

182

u32 bank;

drivers/edac/xgene_edac.c

209

bank = readl(ctx->mcu_csr + MCUEBLRR0 +

drivers/edac/xgene_edac.c

217

rank, MCU_EBLRR_ERRBANK_RD(bank),

drivers/firmware/dmi_scan.c

1153

void dmi_memdev_name(u16 handle, const char **bank, const char **device)

drivers/firmware/dmi_scan.c

1162

*bank = dmi_memdev[n].bank;

drivers/firmware/dmi_scan.c

39

const char *bank;

drivers/firmware/dmi_scan.c

448

dmi_memdev[nr].bank = dmi_string(dm, d[0x11]);

drivers/firmware/efi/cper.c

319

n += scnprintf(msg + n, len - n, "bank:%d ", mem->bank);

drivers/firmware/efi/cper.c

322

mem->bank >> CPER_MEM_BANK_GROUP_SHIFT);

drivers/firmware/efi/cper.c

325

mem->bank & CPER_MEM_BANK_ADDRESS_MASK);

drivers/firmware/efi/cper.c

359

const char *bank = NULL, *device = NULL;

drivers/firmware/efi/cper.c

365

dmi_memdev_name(mem->mem_dev_handle, &bank, &device);

drivers/firmware/efi/cper.c

366

if (bank && device)

drivers/firmware/efi/cper.c

367

n = snprintf(msg, len, "DIMM location: %s %s ", bank, device);

drivers/firmware/efi/cper.c

384

cmem->bank = mem->bank;

drivers/gpio/gpio-74x164.c

45

u8 bank = chip->registers - 1 - offset / 8;

drivers/gpio/gpio-74x164.c

50

return !!(chip->buffer[bank] & BIT(pin));

drivers/gpio/gpio-74x164.c

57

u8 bank = chip->registers - 1 - offset / 8;

drivers/gpio/gpio-74x164.c

63

chip->buffer[bank] |= BIT(pin);

drivers/gpio/gpio-74x164.c

65

chip->buffer[bank] &= ~BIT(pin);

drivers/gpio/gpio-74x164.c

76

size_t bank;

drivers/gpio/gpio-74x164.c

82

bank = chip->registers - 1 - offset / 8;

drivers/gpio/gpio-74x164.c

85

chip->buffer[bank] &= ~bankmask;

drivers/gpio/gpio-74x164.c

86

chip->buffer[bank] |= bitmask;

drivers/gpio/gpio-adp5585.c

105

return regmap_clear_bits(adp5585_gpio->regmap, info->gpio_dir_a + info->bank(off),

drivers/gpio/gpio-adp5585.c

113

unsigned int bank = info->bank(off);

drivers/gpio/gpio-adp5585.c

117

ret = regmap_update_bits(adp5585_gpio->regmap, info->gpo_data_a + bank,

drivers/gpio/gpio-adp5585.c

122

return regmap_set_bits(adp5585_gpio->regmap, info->gpio_dir_a + bank,

drivers/gpio/gpio-adp5585.c

130

unsigned int bank = info->bank(off);

drivers/gpio/gpio-adp5585.c

146

regmap_read(adp5585_gpio->regmap, info->gpio_dir_a + bank, &val);

drivers/gpio/gpio-adp5585.c

148

regmap_read(adp5585_gpio->regmap, reg + bank, &val);

drivers/gpio/gpio-adp5585.c

160

return regmap_update_bits(adp5585_gpio->regmap, info->gpo_data_a + info->bank(off),

drivers/gpio/gpio-adp5585.c

192

info->gpo_out_a + info->bank(off), bit,

drivers/gpio/gpio-adp5585.c

203

info->debounce_dis_a + info->bank(off), bit,

drivers/gpio/gpio-adp5585.c

256

regs->pin_cfg_a + info->bank(off),

drivers/gpio/gpio-adp5585.c

328

unsigned int bank = adp5585_gpio->info->bank(hwirq);

drivers/gpio/gpio-adp5585.c

336

regmap_update_bits(adp5585_gpio->regmap, info->gpi_int_lvl_a + bank, bit,

drivers/gpio/gpio-adp5585.c

338

regmap_update_bits(adp5585_gpio->regmap, info->gpi_ev_a + bank, bit,

drivers/gpio/gpio-adp5585.c

42

int (*bank)(unsigned int off);

drivers/gpio/gpio-adp5585.c

479

.bank = adp5585_gpio_bank,

drivers/gpio/gpio-adp5585.c

495

.bank = adp5589_gpio_bank,

drivers/gpio/gpio-adp5585.c

95

regmap_read(adp5585_gpio->regmap, info->gpio_dir_a + info->bank(off), &val);

drivers/gpio/gpio-aspeed-sgpio.c

137

const struct aspeed_sgpio_bank *bank,

drivers/gpio/gpio-aspeed-sgpio.c

142

return gpio->base + bank->val_regs + GPIO_VAL_VALUE;

drivers/gpio/gpio-aspeed-sgpio.c

144

return gpio->base + bank->rdata_reg;

drivers/gpio/gpio-aspeed-sgpio.c

146

return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;

drivers/gpio/gpio-aspeed-sgpio.c

148

return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;

drivers/gpio/gpio-aspeed-sgpio.c

150

return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;

drivers/gpio/gpio-aspeed-sgpio.c

152

return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;

drivers/gpio/gpio-aspeed-sgpio.c

154

return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;

drivers/gpio/gpio-aspeed-sgpio.c

156

return gpio->base + bank->tolerance_regs;

drivers/gpio/gpio-aspeed-sgpio.c

193

unsigned int bank;

drivers/gpio/gpio-aspeed-sgpio.c

195

bank = GPIO_BANK(offset);

drivers/gpio/gpio-aspeed-sgpio.c

197

WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));

drivers/gpio/gpio-aspeed-sgpio.c

198

return &aspeed_sgpio_banks[bank];

drivers/gpio/gpio-aspeed-sgpio.c

450

const struct aspeed_sgpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed-sgpio.c

451

void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg);

drivers/gpio/gpio-aspeed-sgpio.c

456

addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_rdata);

drivers/gpio/gpio-aspeed-sgpio.c

463

addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_val);

drivers/gpio/gpio-aspeed-sgpio.c

482

const struct aspeed_sgpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed-sgpio.c

483

void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg);

drivers/gpio/gpio-aspeed-sgpio.c

491

const struct aspeed_sgpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed-sgpio.c

492

void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg);

drivers/gpio/gpio-aspeed.c

1040

const struct aspeed_gpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed.c

1041

void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);

drivers/gpio/gpio-aspeed.c

1062

const struct aspeed_gpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed.c

1063

void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);

drivers/gpio/gpio-aspeed.c

1071

const struct aspeed_gpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed.c

1072

void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);

drivers/gpio/gpio-aspeed.c

253

const struct aspeed_gpio_bank *bank,

drivers/gpio/gpio-aspeed.c

258

return gpio->base + bank->val_regs + GPIO_VAL_VALUE;

drivers/gpio/gpio-aspeed.c

260

return gpio->base + bank->rdata_reg;

drivers/gpio/gpio-aspeed.c

262

return gpio->base + bank->val_regs + GPIO_VAL_DIR;

drivers/gpio/gpio-aspeed.c

264

return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;

drivers/gpio/gpio-aspeed.c

266

return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;

drivers/gpio/gpio-aspeed.c

268

return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;

drivers/gpio/gpio-aspeed.c

270

return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;

drivers/gpio/gpio-aspeed.c

272

return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;

drivers/gpio/gpio-aspeed.c

274

return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;

drivers/gpio/gpio-aspeed.c

276

return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;

drivers/gpio/gpio-aspeed.c

278

return gpio->base + bank->tolerance_regs;

drivers/gpio/gpio-aspeed.c

280

return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;

drivers/gpio/gpio-aspeed.c

282

return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;

drivers/gpio/gpio-aspeed.c

326

unsigned int bank = GPIO_BANK(offset);

drivers/gpio/gpio-aspeed.c

328

WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));

drivers/gpio/gpio-aspeed.c

329

return &aspeed_gpio_banks[bank];

drivers/gpio/gpio-aspeed.c

343

if (props->bank == GPIO_BANK(offset))

drivers/gpio/gpio-aspeed.c

52

unsigned int bank;

drivers/gpio/gpio-aspeed.c

662

unsigned int i = props->bank * 32 + offset;

drivers/gpio/gpio-aspeed.c

942

const struct aspeed_gpio_bank *bank = to_bank(offset);

drivers/gpio/gpio-aspeed.c

969

*vreg_offset = bank->val_regs;

drivers/gpio/gpio-aspeed.c

971

*dreg_offset = bank->rdata_reg;

drivers/gpio/gpio-bcm-kona.c

106

struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];

drivers/gpio/gpio-bcm-kona.c

108

if (bank->gpio_unlock_count[bit] == 0) {

drivers/gpio/gpio-bcm-kona.c

114

if (--bank->gpio_unlock_count[bit] == 0) {

drivers/gpio/gpio-bcm-kona.c

129

struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];

drivers/gpio/gpio-bcm-kona.c

131

if (bank->gpio_unlock_count[bit] == 0) {

drivers/gpio/gpio-bcm-kona.c

139

++bank->gpio_unlock_count[bit];

drivers/gpio/gpio-bcm-kona.c

32

#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

33

#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

34

#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

35

#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

36

#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

37

#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

38

#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

39

#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))

drivers/gpio/gpio-bcm-kona.c

454

struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);

drivers/gpio/gpio-bcm-kona.c

464

reg_base = bank->kona_gpio->reg_base;

drivers/gpio/gpio-bcm-kona.c

465

bank_id = bank->id;

drivers/gpio/gpio-bcm-kona.c

478

generic_handle_domain_irq(bank->kona_gpio->irq_domain,

drivers/gpio/gpio-bcm-kona.c

581

struct bcm_kona_gpio_bank *bank;

drivers/gpio/gpio-bcm-kona.c

633

bank = &kona_gpio->banks[i];

drivers/gpio/gpio-bcm-kona.c

634

bank->id = i;

drivers/gpio/gpio-bcm-kona.c

635

bank->irq = platform_get_irq(pdev, i);

drivers/gpio/gpio-bcm-kona.c

636

bank->kona_gpio = kona_gpio;

drivers/gpio/gpio-bcm-kona.c

637

if (bank->irq < 0) {

drivers/gpio/gpio-bcm-kona.c

654

bank = &kona_gpio->banks[i];

drivers/gpio/gpio-bcm-kona.c

655

irq_set_chained_handler_and_data(bank->irq,

drivers/gpio/gpio-bcm-kona.c

657

bank);

drivers/gpio/gpio-brcmstb.c

101

struct brcmstb_gpio_priv *priv = bank->parent_priv;

drivers/gpio/gpio-brcmstb.c

102

u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));

drivers/gpio/gpio-brcmstb.c

105

guard(gpio_generic_lock_irqsave)(&bank->chip);

drivers/gpio/gpio-brcmstb.c

107

imask = gpio_generic_read_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

108

priv->reg_base + GIO_MASK(bank->id));

drivers/gpio/gpio-brcmstb.c

113

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

114

priv->reg_base + GIO_MASK(bank->id), imask);

drivers/gpio/gpio-brcmstb.c

133

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

135

brcmstb_gpio_set_imask(bank, d->hwirq, false);

drivers/gpio/gpio-brcmstb.c

141

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

143

brcmstb_gpio_set_imask(bank, d->hwirq, true);

drivers/gpio/gpio-brcmstb.c

149

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

150

struct brcmstb_gpio_priv *priv = bank->parent_priv;

drivers/gpio/gpio-brcmstb.c

151

u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));

drivers/gpio/gpio-brcmstb.c

153

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

154

priv->reg_base + GIO_STAT(bank->id), mask);

drivers/gpio/gpio-brcmstb.c

160

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

161

struct brcmstb_gpio_priv *priv = bank->parent_priv;

drivers/gpio/gpio-brcmstb.c

162

u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));

drivers/gpio/gpio-brcmstb.c

197

guard(gpio_generic_lock_irqsave)(&bank->chip);

drivers/gpio/gpio-brcmstb.c

199

iedge_config = gpio_generic_read_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

200

priv->reg_base + GIO_EC(bank->id)) & ~mask;

drivers/gpio/gpio-brcmstb.c

201

iedge_insensitive = gpio_generic_read_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

202

priv->reg_base + GIO_EI(bank->id)) & ~mask;

drivers/gpio/gpio-brcmstb.c

203

ilevel = gpio_generic_read_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

204

priv->reg_base + GIO_LEVEL(bank->id)) & ~mask;

drivers/gpio/gpio-brcmstb.c

206

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

207

priv->reg_base + GIO_EC(bank->id),

drivers/gpio/gpio-brcmstb.c

209

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

210

priv->reg_base + GIO_EI(bank->id),

drivers/gpio/gpio-brcmstb.c

212

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

213

priv->reg_base + GIO_LEVEL(bank->id),

drivers/gpio/gpio-brcmstb.c

237

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

238

struct brcmstb_gpio_priv *priv = bank->parent_priv;

drivers/gpio/gpio-brcmstb.c

239

u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));

drivers/gpio/gpio-brcmstb.c

246

bank->wake_active |= mask;

drivers/gpio/gpio-brcmstb.c

248

bank->wake_active &= ~mask;

drivers/gpio/gpio-brcmstb.c

264

static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)

drivers/gpio/gpio-brcmstb.c

266

struct brcmstb_gpio_priv *priv = bank->parent_priv;

drivers/gpio/gpio-brcmstb.c

268

int hwbase = bank->chip.gc.offset;

drivers/gpio/gpio-brcmstb.c

271

while ((status = brcmstb_gpio_get_active_irqs(bank))) {

drivers/gpio/gpio-brcmstb.c

275

if (offset >= bank->width)

drivers/gpio/gpio-brcmstb.c

278

bank->id, offset);

drivers/gpio/gpio-brcmstb.c

28

#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))

drivers/gpio/gpio-brcmstb.c

289

struct brcmstb_gpio_bank *bank;

drivers/gpio/gpio-brcmstb.c

29

#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)

drivers/gpio/gpio-brcmstb.c

295

list_for_each_entry(bank, &priv->bank_list, node)

drivers/gpio/gpio-brcmstb.c

296

brcmstb_gpio_irq_bank_handler(bank);

drivers/gpio/gpio-brcmstb.c

30

#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)

drivers/gpio/gpio-brcmstb.c

303

struct brcmstb_gpio_bank *bank;

drivers/gpio/gpio-brcmstb.c

305

list_for_each_entry(bank, &priv->bank_list, node) {

drivers/gpio/gpio-brcmstb.c

306

if (hwirq >= bank->chip.gc.offset &&

drivers/gpio/gpio-brcmstb.c

307

hwirq < (bank->chip.gc.offset + bank->chip.gc.ngpio))

drivers/gpio/gpio-brcmstb.c

308

return bank;

drivers/gpio/gpio-brcmstb.c

31

#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)

drivers/gpio/gpio-brcmstb.c

32

#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)

drivers/gpio/gpio-brcmstb.c

325

struct brcmstb_gpio_bank *bank =

drivers/gpio/gpio-brcmstb.c

33

#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)

drivers/gpio/gpio-brcmstb.c

330

if (!bank)

drivers/gpio/gpio-brcmstb.c

334

irq, (int)hwirq, bank->id);

drivers/gpio/gpio-brcmstb.c

335

ret = irq_set_chip_data(irq, &bank->chip.gc);

drivers/gpio/gpio-brcmstb.c

34

#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)

drivers/gpio/gpio-brcmstb.c

35

#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)

drivers/gpio/gpio-brcmstb.c

36

#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)

drivers/gpio/gpio-brcmstb.c

377

struct brcmstb_gpio_bank *bank;

drivers/gpio/gpio-brcmstb.c

396

list_for_each_entry(bank, &priv->bank_list, node)

drivers/gpio/gpio-brcmstb.c

397

gpiochip_remove(&bank->chip.gc);

drivers/gpio/gpio-brcmstb.c

404

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

415

offset = gpiospec->args[0] - bank->chip.gc.offset;

drivers/gpio/gpio-brcmstb.c

419

if (unlikely(offset >= bank->width)) {

drivers/gpio/gpio-brcmstb.c

494

struct brcmstb_gpio_bank *bank)

drivers/gpio/gpio-brcmstb.c

499

bank->saved_regs[i] = gpio_generic_read_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

500

priv->reg_base + GIO_BANK_OFF(bank->id, i));

drivers/gpio/gpio-brcmstb.c

506

struct brcmstb_gpio_bank *bank;

drivers/gpio/gpio-brcmstb.c

513

list_for_each_entry(bank, &priv->bank_list, node) {

drivers/gpio/gpio-brcmstb.c

515

brcmstb_gpio_bank_save(priv, bank);

drivers/gpio/gpio-brcmstb.c

519

imask = bank->wake_active;

drivers/gpio/gpio-brcmstb.c

522

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

523

priv->reg_base + GIO_MASK(bank->id),

drivers/gpio/gpio-brcmstb.c

535

struct brcmstb_gpio_bank *bank)

drivers/gpio/gpio-brcmstb.c

540

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

541

priv->reg_base + GIO_BANK_OFF(bank->id, i),

drivers/gpio/gpio-brcmstb.c

542

bank->saved_regs[i]);

drivers/gpio/gpio-brcmstb.c

554

struct brcmstb_gpio_bank *bank;

drivers/gpio/gpio-brcmstb.c

557

list_for_each_entry(bank, &priv->bank_list, node) {

drivers/gpio/gpio-brcmstb.c

558

need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);

drivers/gpio/gpio-brcmstb.c

559

brcmstb_gpio_bank_restore(priv, bank);

drivers/gpio/gpio-brcmstb.c

629

struct brcmstb_gpio_bank *bank;

drivers/gpio/gpio-brcmstb.c

644

bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);

drivers/gpio/gpio-brcmstb.c

645

if (!bank) {

drivers/gpio/gpio-brcmstb.c

650

bank->parent_priv = priv;

drivers/gpio/gpio-brcmstb.c

651

bank->id = num_banks;

drivers/gpio/gpio-brcmstb.c

657

bank->width = bank_width;

drivers/gpio/gpio-brcmstb.c

660

gc = &bank->chip.gc;

drivers/gpio/gpio-brcmstb.c

67

struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-brcmstb.c

670

.dat = reg_base + GIO_DATA(bank->id),

drivers/gpio/gpio-brcmstb.c

671

.dirin = reg_base + GIO_IODIR(bank->id),

drivers/gpio/gpio-brcmstb.c

675

err = gpio_generic_chip_init(&bank->chip, &config);

drivers/gpio/gpio-brcmstb.c

68

return bank->parent_priv;

drivers/gpio/gpio-brcmstb.c

691

gc->offset = bank->id * MAX_GPIO_PER_BANK;

drivers/gpio/gpio-brcmstb.c

701

need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);

drivers/gpio/gpio-brcmstb.c

702

gpio_generic_write_reg(&bank->chip,

drivers/gpio/gpio-brcmstb.c

703

reg_base + GIO_MASK(bank->id), 0);

drivers/gpio/gpio-brcmstb.c

705

err = gpiochip_add_data(gc, bank);

drivers/gpio/gpio-brcmstb.c

708

bank->id);

drivers/gpio/gpio-brcmstb.c

713

dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,

drivers/gpio/gpio-brcmstb.c

714

gc->base, gc->ngpio, bank->width);

drivers/gpio/gpio-brcmstb.c

717

list_add(&bank->node, &priv->bank_list);

drivers/gpio/gpio-brcmstb.c

72

__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)

drivers/gpio/gpio-brcmstb.c

74

void __iomem *reg_base = bank->parent_priv->reg_base;

drivers/gpio/gpio-brcmstb.c

76

return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) &

drivers/gpio/gpio-brcmstb.c

77

gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id));

drivers/gpio/gpio-brcmstb.c

81

brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)

drivers/gpio/gpio-brcmstb.c

85

guard(gpio_generic_lock_irqsave)(&bank->chip);

drivers/gpio/gpio-brcmstb.c

87

status = __brcmstb_gpio_get_active_irqs(bank);

drivers/gpio/gpio-brcmstb.c

93

struct brcmstb_gpio_bank *bank)

drivers/gpio/gpio-brcmstb.c

95

return hwirq - bank->chip.gc.offset;

drivers/gpio/gpio-brcmstb.c

98

static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,

drivers/gpio/gpio-davinci.c

118

int bank = offset / 32;

drivers/gpio/gpio-davinci.c

120

g = d->regs[bank];

drivers/gpio/gpio-davinci.c

140

int bank = offset / 32;

drivers/gpio/gpio-davinci.c

142

g = d->regs[bank];

drivers/gpio/gpio-davinci.c

155

int bank = offset / 32;

drivers/gpio/gpio-davinci.c

157

g = d->regs[bank];

drivers/gpio/gpio-davinci.c

167

int bank, i, ret = 0;

drivers/gpio/gpio-davinci.c

238

for (bank = 0; bank < nbank; bank++)

drivers/gpio/gpio-davinci.c

239

chips->regs[bank] = gpio_base + offset_array[bank];

drivers/gpio/gpio-davinci.c

464

unsigned gpio, bank;

drivers/gpio/gpio-davinci.c

553

for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {

drivers/gpio/gpio-davinci.c

558

g = chips->regs[bank / 2];

drivers/gpio/gpio-davinci.c

575

irqdata->bank_num = bank;

drivers/gpio/gpio-davinci.c

578

irq_set_chained_handler_and_data(chips->irqs[bank],

drivers/gpio/gpio-davinci.c

581

binten |= BIT(bank);

drivers/gpio/gpio-davinci.c

599

u32 bank;

drivers/gpio/gpio-davinci.c

605

for (bank = 0; bank < nbank; bank++) {

drivers/gpio/gpio-davinci.c

606

g = chips->regs[bank];

drivers/gpio/gpio-davinci.c

607

context = &chips->context[bank];

drivers/gpio/gpio-davinci.c

623

u32 bank;

drivers/gpio/gpio-davinci.c

631

for (bank = 0; bank < nbank; bank++) {

drivers/gpio/gpio-davinci.c

632

g = chips->regs[bank];

drivers/gpio/gpio-davinci.c

633

context = &chips->context[bank];

drivers/gpio/gpio-davinci.c

84

int bank = offset / 32;

drivers/gpio/gpio-davinci.c

87

g = d->regs[bank];

drivers/gpio/gpio-eic-sprd.c

135

unsigned int bank)

drivers/gpio/gpio-eic-sprd.c

137

if (bank >= SPRD_EIC_MAX_BANK)

drivers/gpio/gpio-eic-sprd.c

140

return sprd_eic->base[bank];

drivers/gpio/gpio-eic-sprd.c

529

u32 bank, n, girq;

drivers/gpio/gpio-eic-sprd.c

531

for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {

drivers/gpio/gpio-eic-sprd.c

532

void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);

drivers/gpio/gpio-eic-sprd.c

558

u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;

drivers/gpio/gpio-f7188x.c

292

struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-f7188x.c

293

struct f7188x_sio *sio = bank->data->sio;

drivers/gpio/gpio-f7188x.c

301

dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));

drivers/gpio/gpio-f7188x.c

317

struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-f7188x.c

318

struct f7188x_sio *sio = bank->data->sio;

drivers/gpio/gpio-f7188x.c

326

dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));

drivers/gpio/gpio-f7188x.c

332

superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);

drivers/gpio/gpio-f7188x.c

342

struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-f7188x.c

343

struct f7188x_sio *sio = bank->data->sio;

drivers/gpio/gpio-f7188x.c

351

dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));

drivers/gpio/gpio-f7188x.c

354

data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));

drivers/gpio/gpio-f7188x.c

356

data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase));

drivers/gpio/gpio-f7188x.c

367

struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-f7188x.c

368

struct f7188x_sio *sio = bank->data->sio;

drivers/gpio/gpio-f7188x.c

376

data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));

drivers/gpio/gpio-f7188x.c

381

superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);

drivers/gpio/gpio-f7188x.c

383

dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));

drivers/gpio/gpio-f7188x.c

388

superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);

drivers/gpio/gpio-f7188x.c

399

struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-f7188x.c

400

struct f7188x_sio *sio = bank->data->sio;

drivers/gpio/gpio-f7188x.c

409

data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));

drivers/gpio/gpio-f7188x.c

414

superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);

drivers/gpio/gpio-f7188x.c

426

struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-f7188x.c

427

struct f7188x_sio *sio = bank->data->sio;

drivers/gpio/gpio-f7188x.c

439

data = superio_inb(sio->addr, f7188x_gpio_out_mode(bank->regbase));

drivers/gpio/gpio-f7188x.c

444

superio_outb(sio->addr, f7188x_gpio_out_mode(bank->regbase), data);

drivers/gpio/gpio-f7188x.c

468

data->bank = f71869_gpio_bank;

drivers/gpio/gpio-f7188x.c

472

data->bank = f71869a_gpio_bank;

drivers/gpio/gpio-f7188x.c

476

data->bank = f71882_gpio_bank;

drivers/gpio/gpio-f7188x.c

480

data->bank = f71889a_gpio_bank;

drivers/gpio/gpio-f7188x.c

484

data->bank = f71889_gpio_bank;

drivers/gpio/gpio-f7188x.c

488

data->bank = f81866_gpio_bank;

drivers/gpio/gpio-f7188x.c

492

data->bank = f81804_gpio_bank;

drivers/gpio/gpio-f7188x.c

496

data->bank = f81865_gpio_bank;

drivers/gpio/gpio-f7188x.c

500

data->bank = nct6126d_gpio_bank;

drivers/gpio/gpio-f7188x.c

511

struct f7188x_gpio_bank *bank = &data->bank[i];

drivers/gpio/gpio-f7188x.c

513

bank->chip.parent = &pdev->dev;

drivers/gpio/gpio-f7188x.c

514

bank->data = data;

drivers/gpio/gpio-f7188x.c

516

err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);

drivers/gpio/gpio-f7188x.c

95

struct f7188x_gpio_bank *bank;

drivers/gpio/gpio-lpc32xx.c

501

u32 bank = gpiospec->args[0];

drivers/gpio/gpio-lpc32xx.c

502

if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||

drivers/gpio/gpio-lpc32xx.c

503

(gc != &lpc32xx_gpiochip[bank].chip)))

drivers/gpio/gpio-mpsse.c

166

static int gpio_mpsse_set_bank(struct mpsse_priv *priv, u8 bank)

drivers/gpio/gpio-mpsse.c

170

SET_BITS_CMD | (bank << 1),

drivers/gpio/gpio-mpsse.c

171

priv->gpio_outputs[bank],

drivers/gpio/gpio-mpsse.c

172

priv->gpio_dir[bank],

drivers/gpio/gpio-mpsse.c

180

static int gpio_mpsse_get_bank(struct mpsse_priv *priv, u8 bank)

drivers/gpio/gpio-mpsse.c

183

u8 buf = GET_BITS_CMD | (bank << 1);

drivers/gpio/gpio-mpsse.c

225

unsigned long i, bank, bank_mask, bank_bits;

drivers/gpio/gpio-mpsse.c

235

bank = i / 8;

drivers/gpio/gpio-mpsse.c

240

priv->gpio_outputs[bank] &= ~bank_mask;

drivers/gpio/gpio-mpsse.c

242

priv->gpio_outputs[bank] |= bank_bits & bank_mask;

drivers/gpio/gpio-mpsse.c

244

ret = gpio_mpsse_set_bank(priv, bank);

drivers/gpio/gpio-mpsse.c

256

unsigned long i, bank, bank_mask;

drivers/gpio/gpio-mpsse.c

266

bank = i / 8;

drivers/gpio/gpio-mpsse.c

269

ret = gpio_mpsse_get_bank(priv, bank);

drivers/gpio/gpio-mpsse.c

314

int bank = (offset & 8) >> 3;

drivers/gpio/gpio-mpsse.c

322

priv->gpio_dir[bank] |= BIT(bank_offset);

drivers/gpio/gpio-mpsse.c

332

int bank = (offset & 8) >> 3;

drivers/gpio/gpio-mpsse.c

340

priv->gpio_dir[bank] &= ~BIT(bank_offset);

drivers/gpio/gpio-mpsse.c

342

return gpio_mpsse_set_bank(priv, bank);

drivers/gpio/gpio-mpsse.c

349

int bank = (offset & 8) >> 3;

drivers/gpio/gpio-mpsse.c

355

if (priv->gpio_dir[bank] & BIT(bank_offset))

drivers/gpio/gpio-mt7621.c

200

if (rg->bank != gpio / MTK_BANK_WIDTH)

drivers/gpio/gpio-mt7621.c

220

mediatek_gpio_bank_probe(struct device *dev, int bank)

drivers/gpio/gpio-mt7621.c

228

rg = &mtk->gc_map[bank];

drivers/gpio/gpio-mt7621.c

231

rg->bank = bank;

drivers/gpio/gpio-mt7621.c

233

dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);

drivers/gpio/gpio-mt7621.c

234

set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);

drivers/gpio/gpio-mt7621.c

235

ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);

drivers/gpio/gpio-mt7621.c

236

diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);

drivers/gpio/gpio-mt7621.c

257

dev_name(dev), bank);

drivers/gpio/gpio-mt7621.c

261

rg->chip.gc.offset = bank * MTK_BANK_WIDTH;

drivers/gpio/gpio-mt7621.c

34

int bank;

drivers/gpio/gpio-mt7621.c

72

offset = (rg->bank * GPIO_BANK_STRIDE) + offset;

drivers/gpio/gpio-mt7621.c

82

offset = (rg->bank * GPIO_BANK_STRIDE) + offset;

drivers/gpio/gpio-nomadik.c

561

nmk_chip->bank = id;

drivers/gpio/gpio-nomadik.c

623

seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,

drivers/gpio/gpio-nomadik.c

660

pdev->id = nmk_chip->bank;

drivers/gpio/gpio-npcm-sgpio.c

138

const struct npcm_sgpio_bank *bank,

drivers/gpio/gpio-npcm-sgpio.c

143

return gpio->base + bank->rdata_reg;

drivers/gpio/gpio-npcm-sgpio.c

145

return gpio->base + bank->wdata_reg;

drivers/gpio/gpio-npcm-sgpio.c

147

return gpio->base + bank->event_config;

drivers/gpio/gpio-npcm-sgpio.c

149

return gpio->base + bank->event_status;

drivers/gpio/gpio-npcm-sgpio.c

159

unsigned int bank = GPIO_BANK(offset);

drivers/gpio/gpio-npcm-sgpio.c

161

return &npcm_sgpio_banks[bank];

drivers/gpio/gpio-npcm-sgpio.c

166

const struct npcm_sgpio_bank **bank,

drivers/gpio/gpio-npcm-sgpio.c

176

*bank = offset_to_bank(*offset);

drivers/gpio/gpio-npcm-sgpio.c

230

const struct npcm_sgpio_bank *bank = offset_to_bank(offset);

drivers/gpio/gpio-npcm-sgpio.c

234

addr = bank_reg(gpio, bank, WRITE_DATA);

drivers/gpio/gpio-npcm-sgpio.c

250

const struct npcm_sgpio_bank *bank;

drivers/gpio/gpio-npcm-sgpio.c

255

bank = offset_to_bank(offset);

drivers/gpio/gpio-npcm-sgpio.c

256

addr = bank_reg(gpio, bank, WRITE_DATA);

drivers/gpio/gpio-npcm-sgpio.c

259

bank = offset_to_bank(offset);

drivers/gpio/gpio-npcm-sgpio.c

260

addr = bank_reg(gpio, bank, READ_DATA);

drivers/gpio/gpio-npcm-sgpio.c

319

const struct npcm_sgpio_bank *bank;

drivers/gpio/gpio-npcm-sgpio.c

327

npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);

drivers/gpio/gpio-npcm-sgpio.c

328

addr = bank_reg(gpio, bank, EVENT_CFG);

drivers/gpio/gpio-npcm-sgpio.c

346

addr = bank_reg(gpio, bank, EVENT_STS);

drivers/gpio/gpio-npcm-sgpio.c

356

const struct npcm_sgpio_bank *bank;

drivers/gpio/gpio-npcm-sgpio.c

363

npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);

drivers/gpio/gpio-npcm-sgpio.c

364

status_addr = bank_reg(gpio, bank, EVENT_STS);

drivers/gpio/gpio-npcm-sgpio.c

382

const struct npcm_sgpio_bank *bank;

drivers/gpio/gpio-npcm-sgpio.c

391

npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);

drivers/gpio/gpio-npcm-sgpio.c

418

addr = bank_reg(gpio, bank, EVENT_CFG);

drivers/gpio/gpio-npcm-sgpio.c

443

const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];

drivers/gpio/gpio-npcm-sgpio.c

445

reg = ioread8(bank_reg(gpio, bank, EVENT_STS));

drivers/gpio/gpio-npcm-sgpio.c

480

const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];

drivers/gpio/gpio-npcm-sgpio.c

482

iowrite16(0, bank_reg(gpio, bank, EVENT_CFG));

drivers/gpio/gpio-npcm-sgpio.c

483

iowrite8(0xff, bank_reg(gpio, bank, EVENT_STS));

drivers/gpio/gpio-omap.c

1006

static void omap_gpio_mod_init(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

1008

void __iomem *base = bank->base;

drivers/gpio/gpio-omap.c

1011

if (bank->width == 16)

drivers/gpio/gpio-omap.c

1014

if (bank->is_mpuio) {

drivers/gpio/gpio-omap.c

1015

writel_relaxed(l, bank->base + bank->regs->irqenable);

drivers/gpio/gpio-omap.c

1019

omap_gpio_rmw(base + bank->regs->irqenable, l,

drivers/gpio/gpio-omap.c

1020

bank->regs->irqenable_inv);

drivers/gpio/gpio-omap.c

1021

omap_gpio_rmw(base + bank->regs->irqstatus, l,

drivers/gpio/gpio-omap.c

1022

!bank->regs->irqenable_inv);

drivers/gpio/gpio-omap.c

1023

if (bank->regs->debounce_en)

drivers/gpio/gpio-omap.c

1024

writel_relaxed(0, base + bank->regs->debounce_en);

drivers/gpio/gpio-omap.c

1027

bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);

drivers/gpio/gpio-omap.c

1029

if (bank->regs->ctrl)

drivers/gpio/gpio-omap.c

1030

writel_relaxed(0, base + bank->regs->ctrl);

drivers/gpio/gpio-omap.c

1033

static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev)

drivers/gpio/gpio-omap.c

1044

bank->chip.request = omap_gpio_request;

drivers/gpio/gpio-omap.c

1045

bank->chip.free = omap_gpio_free;

drivers/gpio/gpio-omap.c

1046

bank->chip.get_direction = omap_gpio_get_direction;

drivers/gpio/gpio-omap.c

1047

bank->chip.direction_input = omap_gpio_input;

drivers/gpio/gpio-omap.c

1048

bank->chip.get = omap_gpio_get;

drivers/gpio/gpio-omap.c

1049

bank->chip.get_multiple = omap_gpio_get_multiple;

drivers/gpio/gpio-omap.c

1050

bank->chip.direction_output = omap_gpio_output;

drivers/gpio/gpio-omap.c

1051

bank->chip.set_config = omap_gpio_set_config;

drivers/gpio/gpio-omap.c

1052

bank->chip.set = omap_gpio_set;

drivers/gpio/gpio-omap.c

1053

bank->chip.set_multiple = omap_gpio_set_multiple;

drivers/gpio/gpio-omap.c

1054

if (bank->is_mpuio) {

drivers/gpio/gpio-omap.c

1055

bank->chip.label = "mpuio";

drivers/gpio/gpio-omap.c

1056

if (bank->regs->wkup_en)

drivers/gpio/gpio-omap.c

1057

bank->chip.parent = &omap_mpuio_device.dev;

drivers/gpio/gpio-omap.c

1059

label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",

drivers/gpio/gpio-omap.c

1060

gpio, gpio + bank->width - 1);

drivers/gpio/gpio-omap.c

1063

bank->chip.label = label;

drivers/gpio/gpio-omap.c

1065

bank->chip.base = -1;

drivers/gpio/gpio-omap.c

1066

bank->chip.ngpio = bank->width;

drivers/gpio/gpio-omap.c

1068

irq = &bank->chip.irq;

drivers/gpio/gpio-omap.c

1070

if (bank->is_mpuio && !bank->regs->wkup_en)

drivers/gpio/gpio-omap.c

1077

irq->parents = &bank->irq;

drivers/gpio/gpio-omap.c

1079

ret = gpiochip_add_data(&bank->chip, bank);

drivers/gpio/gpio-omap.c

1081

return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");

drivers/gpio/gpio-omap.c

1083

irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);

drivers/gpio/gpio-omap.c

1084

ret = devm_request_irq(bank->chip.parent, bank->irq,

drivers/gpio/gpio-omap.c

1086

0, dev_name(bank->chip.parent), bank);

drivers/gpio/gpio-omap.c

1088

gpiochip_remove(&bank->chip);

drivers/gpio/gpio-omap.c

109

static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,

drivers/gpio/gpio-omap.c

1090

if (!bank->is_mpuio)

drivers/gpio/gpio-omap.c

1091

gpio += bank->width;

drivers/gpio/gpio-omap.c

1116

static void omap_gpio_restore_context(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

1118

const struct omap_gpio_reg_offs *regs = bank->regs;

drivers/gpio/gpio-omap.c

1119

void __iomem *base = bank->base;

drivers/gpio/gpio-omap.c

112

bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,

drivers/gpio/gpio-omap.c

1121

writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);

drivers/gpio/gpio-omap.c

1122

writel_relaxed(bank->context.wake_en, base + regs->wkup_en);

drivers/gpio/gpio-omap.c

1123

writel_relaxed(bank->context.ctrl, base + regs->ctrl);

drivers/gpio/gpio-omap.c

1124

writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);

drivers/gpio/gpio-omap.c

1125

writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);

drivers/gpio/gpio-omap.c

1126

writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);

drivers/gpio/gpio-omap.c

1127

writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);

drivers/gpio/gpio-omap.c

1128

writel_relaxed(bank->context.dataout, base + regs->dataout);

drivers/gpio/gpio-omap.c

1129

writel_relaxed(bank->context.oe, base + regs->direction);

drivers/gpio/gpio-omap.c

1131

if (bank->dbck_enable_mask) {

drivers/gpio/gpio-omap.c

1132

writel_relaxed(bank->context.debounce, base + regs->debounce);

drivers/gpio/gpio-omap.c

1133

writel_relaxed(bank->context.debounce_en,

drivers/gpio/gpio-omap.c

1137

writel_relaxed(bank->context.irqenable1, base + regs->irqenable);

drivers/gpio/gpio-omap.c

1138

writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);

drivers/gpio/gpio-omap.c

1141

static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)

drivers/gpio/gpio-omap.c

1143

struct device *dev = bank->chip.parent;

drivers/gpio/gpio-omap.c

1144

void __iomem *base = bank->base;

drivers/gpio/gpio-omap.c

1147

bank->saved_datain = readl_relaxed(base + bank->regs->datain);

drivers/gpio/gpio-omap.c

1150

if (bank->loses_context)

drivers/gpio/gpio-omap.c

1151

bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);

drivers/gpio/gpio-omap.c

1153

if (!bank->enabled_non_wakeup_gpios)

drivers/gpio/gpio-omap.c

1157

mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;

drivers/gpio/gpio-omap.c

1158

mask &= ~bank->context.risingdetect;

drivers/gpio/gpio-omap.c

1159

bank->saved_datain |= mask;

drivers/gpio/gpio-omap.c

1162

mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;

drivers/gpio/gpio-omap.c

1163

mask &= ~bank->context.fallingdetect;

drivers/gpio/gpio-omap.c

1164

bank->saved_datain &= ~mask;

drivers/gpio/gpio-omap.c

1174

if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {

drivers/gpio/gpio-omap.c

1175

nowake = bank->enabled_non_wakeup_gpios;

drivers/gpio/gpio-omap.c

1176

omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);

drivers/gpio/gpio-omap.c

1177

omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);

drivers/gpio/gpio-omap.c

118

static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,

drivers/gpio/gpio-omap.c

1181

if (bank->get_context_loss_count)

drivers/gpio/gpio-omap.c

1182

bank->context_loss_count =

drivers/gpio/gpio-omap.c

1183

bank->get_context_loss_count(dev);

drivers/gpio/gpio-omap.c

1185

omap_gpio_dbck_disable(bank);

drivers/gpio/gpio-omap.c

1188

static void omap_gpio_unidle(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

1190

struct device *dev = bank->chip.parent;

drivers/gpio/gpio-omap.c

1199

if (bank->loses_context && !bank->context_valid) {

drivers/gpio/gpio-omap.c

1200

omap_gpio_init_context(bank);

drivers/gpio/gpio-omap.c

1202

if (bank->get_context_loss_count)

drivers/gpio/gpio-omap.c

1203

bank->context_loss_count =

drivers/gpio/gpio-omap.c

1204

bank->get_context_loss_count(dev);

drivers/gpio/gpio-omap.c

1207

omap_gpio_dbck_enable(bank);

drivers/gpio/gpio-omap.c

1209

if (bank->loses_context) {

drivers/gpio/gpio-omap.c

121

void __iomem *reg = bank->base;

drivers/gpio/gpio-omap.c

1210

if (!bank->get_context_loss_count) {

drivers/gpio/gpio-omap.c

1211

omap_gpio_restore_context(bank);

drivers/gpio/gpio-omap.c

1213

c = bank->get_context_loss_count(dev);

drivers/gpio/gpio-omap.c

1214

if (c != bank->context_loss_count) {

drivers/gpio/gpio-omap.c

1215

omap_gpio_restore_context(bank);

drivers/gpio/gpio-omap.c

1222

writel_relaxed(bank->context.fallingdetect,

drivers/gpio/gpio-omap.c

1223

bank->base + bank->regs->fallingdetect);

drivers/gpio/gpio-omap.c

1224

writel_relaxed(bank->context.risingdetect,

drivers/gpio/gpio-omap.c

1225

bank->base + bank->regs->risingdetect);

drivers/gpio/gpio-omap.c

1228

l = readl_relaxed(bank->base + bank->regs->datain);

drivers/gpio/gpio-omap.c

1236

l ^= bank->saved_datain;

drivers/gpio/gpio-omap.c

1237

l &= bank->enabled_non_wakeup_gpios;

drivers/gpio/gpio-omap.c

1243

gen0 = l & bank->context.fallingdetect;

drivers/gpio/gpio-omap.c

1244

gen0 &= bank->saved_datain;

drivers/gpio/gpio-omap.c

1246

gen1 = l & bank->context.risingdetect;

drivers/gpio/gpio-omap.c

1247

gen1 &= ~(bank->saved_datain);

drivers/gpio/gpio-omap.c

125

reg += bank->regs->set_dataout;

drivers/gpio/gpio-omap.c

1250

gen = l & (~(bank->context.fallingdetect) &

drivers/gpio/gpio-omap.c

1251

~(bank->context.risingdetect));

drivers/gpio/gpio-omap.c

1258

old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);

drivers/gpio/gpio-omap.c

1259

old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);

drivers/gpio/gpio-omap.c

126

bank->context.dataout |= l;

drivers/gpio/gpio-omap.c

1261

if (!bank->regs->irqstatus_raw0) {

drivers/gpio/gpio-omap.c

1262

writel_relaxed(old0 | gen, bank->base +

drivers/gpio/gpio-omap.c

1263

bank->regs->leveldetect0);

drivers/gpio/gpio-omap.c

1264

writel_relaxed(old1 | gen, bank->base +

drivers/gpio/gpio-omap.c

1265

bank->regs->leveldetect1);

drivers/gpio/gpio-omap.c

1268

if (bank->regs->irqstatus_raw0) {

drivers/gpio/gpio-omap.c

1269

writel_relaxed(old0 | l, bank->base +

drivers/gpio/gpio-omap.c

1270

bank->regs->leveldetect0);

drivers/gpio/gpio-omap.c

1271

writel_relaxed(old1 | l, bank->base +

drivers/gpio/gpio-omap.c

1272

bank->regs->leveldetect1);

drivers/gpio/gpio-omap.c

1274

writel_relaxed(old0, bank->base + bank->regs->leveldetect0);

drivers/gpio/gpio-omap.c

1275

writel_relaxed(old1, bank->base + bank->regs->leveldetect1);

drivers/gpio/gpio-omap.c

128

reg += bank->regs->clr_dataout;

drivers/gpio/gpio-omap.c

1282

struct gpio_bank *bank;

drivers/gpio/gpio-omap.c

1287

bank = container_of(nb, struct gpio_bank, nb);

drivers/gpio/gpio-omap.c

1289

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

129

bank->context.dataout &= ~l;

drivers/gpio/gpio-omap.c

1290

if (bank->is_suspended)

drivers/gpio/gpio-omap.c

1295

mask = omap_get_gpio_irqbank_mask(bank);

drivers/gpio/gpio-omap.c

1296

isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;

drivers/gpio/gpio-omap.c

1301

omap_gpio_idle(bank, true);

drivers/gpio/gpio-omap.c

1305

omap_gpio_unidle(bank);

drivers/gpio/gpio-omap.c

1310

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

136

static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,

drivers/gpio/gpio-omap.c

139

bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,

drivers/gpio/gpio-omap.c

1405

struct gpio_bank *bank;

drivers/gpio/gpio-omap.c

1414

bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);

drivers/gpio/gpio-omap.c

1415

if (!bank)

drivers/gpio/gpio-omap.c

1418

bank->dev = dev;

drivers/gpio/gpio-omap.c

1420

bank->irq = platform_get_irq(pdev, 0);

drivers/gpio/gpio-omap.c

1421

if (bank->irq < 0)

drivers/gpio/gpio-omap.c

1422

return bank->irq;

drivers/gpio/gpio-omap.c

1424

bank->chip.parent = dev;

drivers/gpio/gpio-omap.c

1425

bank->chip.owner = THIS_MODULE;

drivers/gpio/gpio-omap.c

1426

bank->dbck_flag = pdata->dbck_flag;

drivers/gpio/gpio-omap.c

1427

bank->stride = pdata->bank_stride;

drivers/gpio/gpio-omap.c

1428

bank->width = pdata->bank_width;

drivers/gpio/gpio-omap.c

1429

bank->is_mpuio = pdata->is_mpuio;

drivers/gpio/gpio-omap.c

143

static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

1430

bank->non_wakeup_gpios = pdata->non_wakeup_gpios;

drivers/gpio/gpio-omap.c

1431

bank->regs = pdata->regs;

drivers/gpio/gpio-omap.c

1435

bank->loses_context = true;

drivers/gpio/gpio-omap.c

1437

bank->loses_context = pdata->loses_context;

drivers/gpio/gpio-omap.c

1439

if (bank->loses_context)

drivers/gpio/gpio-omap.c

1440

bank->get_context_loss_count =

drivers/gpio/gpio-omap.c

1444

if (bank->regs->set_dataout && bank->regs->clr_dataout)

drivers/gpio/gpio-omap.c

1445

bank->set_dataout = omap_set_gpio_dataout_reg;

drivers/gpio/gpio-omap.c

1447

bank->set_dataout = omap_set_gpio_dataout_mask;

drivers/gpio/gpio-omap.c

1449

raw_spin_lock_init(&bank->lock);

drivers/gpio/gpio-omap.c

145

if (bank->dbck_enable_mask && !bank->dbck_enabled) {

drivers/gpio/gpio-omap.c

1450

raw_spin_lock_init(&bank->wa_lock);

drivers/gpio/gpio-omap.c

1453

bank->base = devm_platform_ioremap_resource(pdev, 0);

drivers/gpio/gpio-omap.c

1454

if (IS_ERR(bank->base)) {

drivers/gpio/gpio-omap.c

1455

return PTR_ERR(bank->base);

drivers/gpio/gpio-omap.c

1458

if (bank->dbck_flag) {

drivers/gpio/gpio-omap.c

1459

bank->dbck = devm_clk_get(dev, "dbclk");

drivers/gpio/gpio-omap.c

146

clk_enable(bank->dbck);

drivers/gpio/gpio-omap.c

1460

if (IS_ERR(bank->dbck)) {

drivers/gpio/gpio-omap.c

1463

bank->dbck_flag = false;

drivers/gpio/gpio-omap.c

1465

clk_prepare(bank->dbck);

drivers/gpio/gpio-omap.c

1469

platform_set_drvdata(pdev, bank);

drivers/gpio/gpio-omap.c

147

bank->dbck_enabled = true;

drivers/gpio/gpio-omap.c

1474

if (bank->is_mpuio)

drivers/gpio/gpio-omap.c

1475

omap_mpuio_init(bank);

drivers/gpio/gpio-omap.c

1477

omap_gpio_mod_init(bank);

drivers/gpio/gpio-omap.c

1479

ret = omap_gpio_chip_init(bank, dev);

drivers/gpio/gpio-omap.c

1483

if (bank->dbck_flag)

drivers/gpio/gpio-omap.c

1484

clk_unprepare(bank->dbck);

drivers/gpio/gpio-omap.c

1488

omap_gpio_show_rev(bank);

drivers/gpio/gpio-omap.c

149

writel_relaxed(bank->dbck_enable_mask,

drivers/gpio/gpio-omap.c

1490

bank->nb.notifier_call = gpio_omap_cpu_notifier;

drivers/gpio/gpio-omap.c

1491

cpu_pm_register_notifier(&bank->nb);

drivers/gpio/gpio-omap.c

150

bank->base + bank->regs->debounce_en);

drivers/gpio/gpio-omap.c

1500

struct gpio_bank *bank = platform_get_drvdata(pdev);

drivers/gpio/gpio-omap.c

1502

cpu_pm_unregister_notifier(&bank->nb);

drivers/gpio/gpio-omap.c

1503

gpiochip_remove(&bank->chip);

drivers/gpio/gpio-omap.c

1505

if (bank->dbck_flag)

drivers/gpio/gpio-omap.c

1506

clk_unprepare(bank->dbck);

drivers/gpio/gpio-omap.c

1511

struct gpio_bank *bank = dev_get_drvdata(dev);

drivers/gpio/gpio-omap.c

1514

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

1515

omap_gpio_idle(bank, true);

drivers/gpio/gpio-omap.c

1516

bank->is_suspended = true;

drivers/gpio/gpio-omap.c

1517

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

1524

struct gpio_bank *bank = dev_get_drvdata(dev);

drivers/gpio/gpio-omap.c

1527

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

1528

omap_gpio_unidle(bank);

drivers/gpio/gpio-omap.c

1529

bank->is_suspended = false;

drivers/gpio/gpio-omap.c

1530

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

1537

struct gpio_bank *bank = dev_get_drvdata(dev);

drivers/gpio/gpio-omap.c

1539

if (bank->is_suspended)

drivers/gpio/gpio-omap.c

154

static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

1542

bank->needs_resume = 1;

drivers/gpio/gpio-omap.c

1549

struct gpio_bank *bank = dev_get_drvdata(dev);

drivers/gpio/gpio-omap.c

1551

if (!bank->needs_resume)

drivers/gpio/gpio-omap.c

1554

bank->needs_resume = 0;

drivers/gpio/gpio-omap.c

156

if (bank->dbck_enable_mask && bank->dbck_enabled) {

drivers/gpio/gpio-omap.c

162

writel_relaxed(0, bank->base + bank->regs->debounce_en);

drivers/gpio/gpio-omap.c

164

clk_disable(bank->dbck);

drivers/gpio/gpio-omap.c

165

bank->dbck_enabled = false;

drivers/gpio/gpio-omap.c

181

static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,

drivers/gpio/gpio-omap.c

188

if (!bank->dbck_flag)

drivers/gpio/gpio-omap.c

199

clk_enable(bank->dbck);

drivers/gpio/gpio-omap.c

200

writel_relaxed(debounce, bank->base + bank->regs->debounce);

drivers/gpio/gpio-omap.c

202

val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);

drivers/gpio/gpio-omap.c

203

bank->dbck_enable_mask = val;

drivers/gpio/gpio-omap.c

205

clk_disable(bank->dbck);

drivers/gpio/gpio-omap.c

214

omap_gpio_dbck_enable(bank);

drivers/gpio/gpio-omap.c

215

if (bank->dbck_enable_mask) {

drivers/gpio/gpio-omap.c

216

bank->context.debounce = debounce;

drivers/gpio/gpio-omap.c

217

bank->context.debounce_en = val;

drivers/gpio/gpio-omap.c

233

static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)

drivers/gpio/gpio-omap.c

237

if (!bank->dbck_flag)

drivers/gpio/gpio-omap.c

240

if (!(bank->dbck_enable_mask & gpio_bit))

drivers/gpio/gpio-omap.c

243

bank->dbck_enable_mask &= ~gpio_bit;

drivers/gpio/gpio-omap.c

244

bank->context.debounce_en &= ~gpio_bit;

drivers/gpio/gpio-omap.c

245

writel_relaxed(bank->context.debounce_en,

drivers/gpio/gpio-omap.c

246

bank->base + bank->regs->debounce_en);

drivers/gpio/gpio-omap.c

248

if (!bank->dbck_enable_mask) {

drivers/gpio/gpio-omap.c

249

bank->context.debounce = 0;

drivers/gpio/gpio-omap.c

250

writel_relaxed(bank->context.debounce, bank->base +

drivers/gpio/gpio-omap.c

251

bank->regs->debounce);

drivers/gpio/gpio-omap.c

252

clk_disable(bank->dbck);

drivers/gpio/gpio-omap.c

253

bank->dbck_enabled = false;

drivers/gpio/gpio-omap.c

263

static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)

drivers/gpio/gpio-omap.c

265

u32 no_wake = bank->non_wakeup_gpios;

drivers/gpio/gpio-omap.c

273

static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,

drivers/gpio/gpio-omap.c

276

void __iomem *base = bank->base;

drivers/gpio/gpio-omap.c

279

omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,

drivers/gpio/gpio-omap.c

281

omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,

drivers/gpio/gpio-omap.c

289

omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,

drivers/gpio/gpio-omap.c

291

omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,

drivers/gpio/gpio-omap.c

294

bank->context.leveldetect0 =

drivers/gpio/gpio-omap.c

295

readl_relaxed(bank->base + bank->regs->leveldetect0);

drivers/gpio/gpio-omap.c

296

bank->context.leveldetect1 =

drivers/gpio/gpio-omap.c

297

readl_relaxed(bank->base + bank->regs->leveldetect1);

drivers/gpio/gpio-omap.c

298

bank->context.risingdetect =

drivers/gpio/gpio-omap.c

299

readl_relaxed(bank->base + bank->regs->risingdetect);

drivers/gpio/gpio-omap.c

300

bank->context.fallingdetect =

drivers/gpio/gpio-omap.c

301

readl_relaxed(bank->base + bank->regs->fallingdetect);

drivers/gpio/gpio-omap.c

303

bank->level_mask = bank->context.leveldetect0 |

drivers/gpio/gpio-omap.c

304

bank->context.leveldetect1;

drivers/gpio/gpio-omap.c

307

if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {

drivers/gpio/gpio-omap.c

315

bank->enabled_non_wakeup_gpios |= gpio_bit;

drivers/gpio/gpio-omap.c

317

bank->enabled_non_wakeup_gpios &= ~gpio_bit;

drivers/gpio/gpio-omap.c

325

static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)

drivers/gpio/gpio-omap.c

327

if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {

drivers/gpio/gpio-omap.c

328

void __iomem *reg = bank->base + bank->regs->irqctrl;

drivers/gpio/gpio-omap.c

334

static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,

drivers/gpio/gpio-omap.c

337

void __iomem *reg = bank->base;

drivers/gpio/gpio-omap.c

340

if (bank->regs->leveldetect0 && bank->regs->wkup_en) {

drivers/gpio/gpio-omap.c

341

omap_set_gpio_trigger(bank, gpio, trigger);

drivers/gpio/gpio-omap.c

342

} else if (bank->regs->irqctrl) {

drivers/gpio/gpio-omap.c

343

reg += bank->regs->irqctrl;

drivers/gpio/gpio-omap.c

347

bank->toggle_mask |= BIT(gpio);

drivers/gpio/gpio-omap.c

356

} else if (bank->regs->edgectrl1) {

drivers/gpio/gpio-omap.c

358

reg += bank->regs->edgectrl2;

drivers/gpio/gpio-omap.c

360

reg += bank->regs->edgectrl1;

drivers/gpio/gpio-omap.c

374

static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)

drivers/gpio/gpio-omap.c

376

if (bank->regs->pinctrl) {

drivers/gpio/gpio-omap.c

377

void __iomem *reg = bank->base + bank->regs->pinctrl;

drivers/gpio/gpio-omap.c

383

if (bank->regs->ctrl && !BANK_USED(bank)) {

drivers/gpio/gpio-omap.c

384

void __iomem *reg = bank->base + bank->regs->ctrl;

drivers/gpio/gpio-omap.c

391

bank->context.ctrl = ctrl;

drivers/gpio/gpio-omap.c

395

static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)

drivers/gpio/gpio-omap.c

397

if (bank->regs->ctrl && !BANK_USED(bank)) {

drivers/gpio/gpio-omap.c

398

void __iomem *reg = bank->base + bank->regs->ctrl;

drivers/gpio/gpio-omap.c

405

bank->context.ctrl = ctrl;

drivers/gpio/gpio-omap.c

409

static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)

drivers/gpio/gpio-omap.c

411

void __iomem *reg = bank->base + bank->regs->direction;

drivers/gpio/gpio-omap.c

416

static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)

drivers/gpio/gpio-omap.c

418

if (!LINE_USED(bank->mod_usage, offset)) {

drivers/gpio/gpio-omap.c

419

omap_enable_gpio_module(bank, offset);

drivers/gpio/gpio-omap.c

420

omap_set_gpio_direction(bank, offset, 1);

drivers/gpio/gpio-omap.c

422

bank->irq_usage |= BIT(offset);

drivers/gpio/gpio-omap.c

427

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

435

if (!bank->regs->leveldetect0 &&

drivers/gpio/gpio-omap.c

439

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

440

retval = omap_set_gpio_triggering(bank, offset, type);

drivers/gpio/gpio-omap.c

442

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

445

omap_gpio_init_irq(bank, offset);

drivers/gpio/gpio-omap.c

446

if (!omap_gpio_is_input(bank, offset)) {

drivers/gpio/gpio-omap.c

447

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

451

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

470

static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)

drivers/gpio/gpio-omap.c

472

void __iomem *reg = bank->base;

drivers/gpio/gpio-omap.c

474

reg += bank->regs->irqstatus;

drivers/gpio/gpio-omap.c

478

if (bank->regs->irqstatus2) {

drivers/gpio/gpio-omap.c

479

reg = bank->base + bank->regs->irqstatus2;

drivers/gpio/gpio-omap.c

487

static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,

drivers/gpio/gpio-omap.c

490

omap_clear_gpio_irqbank(bank, BIT(offset));

drivers/gpio/gpio-omap.c

493

static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

495

void __iomem *reg = bank->base;

drivers/gpio/gpio-omap.c

497

u32 mask = (BIT(bank->width)) - 1;

drivers/gpio/gpio-omap.c

499

reg += bank->regs->irqenable;

drivers/gpio/gpio-omap.c

501

if (bank->regs->irqenable_inv)

drivers/gpio/gpio-omap.c

507

static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,

drivers/gpio/gpio-omap.c

510

void __iomem *reg = bank->base;

drivers/gpio/gpio-omap.c

513

if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {

drivers/gpio/gpio-omap.c

515

reg += bank->regs->set_irqenable;

drivers/gpio/gpio-omap.c

516

bank->context.irqenable1 |= gpio_mask;

drivers/gpio/gpio-omap.c

518

reg += bank->regs->clr_irqenable;

drivers/gpio/gpio-omap.c

519

bank->context.irqenable1 &= ~gpio_mask;

drivers/gpio/gpio-omap.c

523

bank->context.irqenable1 =

drivers/gpio/gpio-omap.c

524

omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,

drivers/gpio/gpio-omap.c

525

enable ^ bank->regs->irqenable_inv);

drivers/gpio/gpio-omap.c

534

if (bank->regs->wkup_en &&

drivers/gpio/gpio-omap.c

535

(bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {

drivers/gpio/gpio-omap.c

536

bank->context.wake_en =

drivers/gpio/gpio-omap.c

537

omap_gpio_rmw(bank->base + bank->regs->wkup_en,

drivers/gpio/gpio-omap.c

545

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

547

return irq_set_irq_wake(bank->irq, enable);

drivers/gpio/gpio-omap.c

564

struct gpio_bank *bank = gpiobank;

drivers/gpio/gpio-omap.c

568

isr_reg = bank->base + bank->regs->irqstatus;

drivers/gpio/gpio-omap.c

572

if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),

drivers/gpio/gpio-omap.c

577

raw_spin_lock_irqsave(&bank->lock, lock_flags);

drivers/gpio/gpio-omap.c

579

enabled = omap_get_gpio_irqbank_mask(bank);

drivers/gpio/gpio-omap.c

587

edge = isr & ~bank->level_mask;

drivers/gpio/gpio-omap.c

589

omap_clear_gpio_irqbank(bank, edge);

drivers/gpio/gpio-omap.c

591

raw_spin_unlock_irqrestore(&bank->lock, lock_flags);

drivers/gpio/gpio-omap.c

600

raw_spin_lock_irqsave(&bank->lock, lock_flags);

drivers/gpio/gpio-omap.c

608

if (bank->toggle_mask & (BIT(bit)))

drivers/gpio/gpio-omap.c

609

omap_toggle_gpio_edge_triggering(bank, bit);

drivers/gpio/gpio-omap.c

611

raw_spin_unlock_irqrestore(&bank->lock, lock_flags);

drivers/gpio/gpio-omap.c

613

raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);

drivers/gpio/gpio-omap.c

615

generic_handle_domain_irq(bank->chip.irq.domain, bit);

drivers/gpio/gpio-omap.c

617

raw_spin_unlock_irqrestore(&bank->wa_lock,

drivers/gpio/gpio-omap.c

627

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

631

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

633

if (!LINE_USED(bank->mod_usage, offset))

drivers/gpio/gpio-omap.c

634

omap_set_gpio_direction(bank, offset, 1);

drivers/gpio/gpio-omap.c

635

omap_enable_gpio_module(bank, offset);

drivers/gpio/gpio-omap.c

636

bank->irq_usage |= BIT(offset);

drivers/gpio/gpio-omap.c

638

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

646

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

650

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

651

bank->irq_usage &= ~(BIT(offset));

drivers/gpio/gpio-omap.c

652

omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);

drivers/gpio/gpio-omap.c

653

omap_clear_gpio_irqstatus(bank, offset);

drivers/gpio/gpio-omap.c

654

omap_set_gpio_irqenable(bank, offset, 0);

drivers/gpio/gpio-omap.c

655

if (!LINE_USED(bank->mod_usage, offset))

drivers/gpio/gpio-omap.c

656

omap_clear_gpio_debounce(bank, offset);

drivers/gpio/gpio-omap.c

657

omap_disable_gpio_module(bank, offset);

drivers/gpio/gpio-omap.c

658

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

663

struct gpio_bank *bank = omap_irq_data_get_bank(data);

drivers/gpio/gpio-omap.c

665

pm_runtime_get_sync(bank->chip.parent);

drivers/gpio/gpio-omap.c

670

struct gpio_bank *bank = omap_irq_data_get_bank(data);

drivers/gpio/gpio-omap.c

672

pm_runtime_put(bank->chip.parent);

drivers/gpio/gpio-omap.c

677

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

681

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

682

omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);

drivers/gpio/gpio-omap.c

683

omap_set_gpio_irqenable(bank, offset, 0);

drivers/gpio/gpio-omap.c

684

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

685

gpiochip_disable_irq(&bank->chip, offset);

drivers/gpio/gpio-omap.c

690

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

695

gpiochip_enable_irq(&bank->chip, offset);

drivers/gpio/gpio-omap.c

696

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

697

omap_set_gpio_irqenable(bank, offset, 1);

drivers/gpio/gpio-omap.c

704

if (bank->regs->leveldetect0 && bank->regs->wkup_en &&

drivers/gpio/gpio-omap.c

706

omap_clear_gpio_irqstatus(bank, offset);

drivers/gpio/gpio-omap.c

709

omap_set_gpio_triggering(bank, offset, trigger);

drivers/gpio/gpio-omap.c

711

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

716

struct gpio_bank *bank = omap_irq_data_get_bank(d);

drivers/gpio/gpio-omap.c

718

seq_puts(p, dev_name(bank->dev));

drivers/gpio/gpio-omap.c

752

struct gpio_bank *bank = dev_get_drvdata(dev);

drivers/gpio/gpio-omap.c

753

void __iomem *mask_reg = bank->base +

drivers/gpio/gpio-omap.c

754

OMAP_MPUIO_GPIO_MASKIT / bank->stride;

drivers/gpio/gpio-omap.c

757

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

758

writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);

drivers/gpio/gpio-omap.c

759

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

766

struct gpio_bank *bank = dev_get_drvdata(dev);

drivers/gpio/gpio-omap.c

767

void __iomem *mask_reg = bank->base +

drivers/gpio/gpio-omap.c

768

OMAP_MPUIO_GPIO_MASKIT / bank->stride;

drivers/gpio/gpio-omap.c

771

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

772

writel_relaxed(bank->context.wake_en, mask_reg);

drivers/gpio/gpio-omap.c

773

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

78

void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);

drivers/gpio/gpio-omap.c

800

static inline void omap_mpuio_init(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

804

platform_set_drvdata(&omap_mpuio_device, bank);

drivers/gpio/gpio-omap.c

815

struct gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

820

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

821

omap_enable_gpio_module(bank, offset);

drivers/gpio/gpio-omap.c

822

bank->mod_usage |= BIT(offset);

drivers/gpio/gpio-omap.c

823

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

830

struct gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

833

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

834

bank->mod_usage &= ~(BIT(offset));

drivers/gpio/gpio-omap.c

835

if (!LINE_USED(bank->irq_usage, offset)) {

drivers/gpio/gpio-omap.c

836

omap_set_gpio_direction(bank, offset, 1);

drivers/gpio/gpio-omap.c

837

omap_clear_gpio_debounce(bank, offset);

drivers/gpio/gpio-omap.c

839

omap_disable_gpio_module(bank, offset);

drivers/gpio/gpio-omap.c

84

#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)

drivers/gpio/gpio-omap.c

840

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

847

struct gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

849

if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))

drivers/gpio/gpio-omap.c

857

struct gpio_bank *bank;

drivers/gpio/gpio-omap.c

860

bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

861

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

862

omap_set_gpio_direction(bank, offset, 1);

drivers/gpio/gpio-omap.c

863

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

869

struct gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

872

if (omap_gpio_is_input(bank, offset))

drivers/gpio/gpio-omap.c

873

reg = bank->base + bank->regs->datain;

drivers/gpio/gpio-omap.c

875

reg = bank->base + bank->regs->dataout;

drivers/gpio/gpio-omap.c

882

struct gpio_bank *bank;

drivers/gpio/gpio-omap.c

885

bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

886

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

887

bank->set_dataout(bank, offset, value);

drivers/gpio/gpio-omap.c

888

omap_set_gpio_direction(bank, offset, 0);

drivers/gpio/gpio-omap.c

889

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

896

struct gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

897

void __iomem *base = bank->base;

drivers/gpio/gpio-omap.c

900

direction = readl_relaxed(base + bank->regs->direction);

drivers/gpio/gpio-omap.c

904

val |= readl_relaxed(base + bank->regs->datain) & m;

drivers/gpio/gpio-omap.c

908

val |= readl_relaxed(base + bank->regs->dataout) & m;

drivers/gpio/gpio-omap.c

918

struct gpio_bank *bank;

drivers/gpio/gpio-omap.c

922

bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

924

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

925

ret = omap2_set_gpio_debounce(bank, offset, debounce);

drivers/gpio/gpio-omap.c

926

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

961

struct gpio_bank *bank;

drivers/gpio/gpio-omap.c

964

bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

965

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

966

bank->set_dataout(bank, offset, value);

drivers/gpio/gpio-omap.c

967

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

975

struct gpio_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-omap.c

976

void __iomem *reg = bank->base + bank->regs->dataout;

drivers/gpio/gpio-omap.c

980

raw_spin_lock_irqsave(&bank->lock, flags);

drivers/gpio/gpio-omap.c

983

bank->context.dataout = l;

drivers/gpio/gpio-omap.c

984

raw_spin_unlock_irqrestore(&bank->lock, flags);

drivers/gpio/gpio-omap.c

991

static void omap_gpio_show_rev(struct gpio_bank *bank)

drivers/gpio/gpio-omap.c

996

if (called || bank->regs->revision == USHRT_MAX)

drivers/gpio/gpio-omap.c

999

rev = readw_relaxed(bank->base + bank->regs->revision);

drivers/gpio/gpio-pca953x.c

321

int bank = (reg & REG_ADDR_MASK) >> bank_shift;

drivers/gpio/gpio-pca953x.c

328

bank += 8;

drivers/gpio/gpio-pca953x.c

332

if (!(BIT(bank) & checkbank))

drivers/gpio/gpio-pca953x.c

353

int bank;

drivers/gpio/gpio-pca953x.c

374

bank = bank_shift + reg / NBANK(chip);

drivers/gpio/gpio-pca953x.c

378

if (!(BIT(bank) & checkbank))

drivers/gpio/gpio-pca953x.c

410

u32 bank;

drivers/gpio/gpio-pca953x.c

414

bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |

drivers/gpio/gpio-pca953x.c

422

bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |

drivers/gpio/gpio-pca953x.c

428

bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |

drivers/gpio/gpio-pca953x.c

433

return chip->check_reg(chip, reg, bank);

drivers/gpio/gpio-pca953x.c

439

u32 bank;

drivers/gpio/gpio-pca953x.c

443

bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |

drivers/gpio/gpio-pca953x.c

450

bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |

drivers/gpio/gpio-pca953x.c

456

bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |

drivers/gpio/gpio-pca953x.c

459

return chip->check_reg(chip, reg, bank);

drivers/gpio/gpio-pca953x.c

465

u32 bank;

drivers/gpio/gpio-pca953x.c

469

bank = PCA957x_BANK_INPUT;

drivers/gpio/gpio-pca953x.c

475

bank = PCA953x_BANK_INPUT;

drivers/gpio/gpio-pca953x.c

480

bank |= PCAL9xxx_BANK_IRQ_STAT;

drivers/gpio/gpio-pca953x.c

482

return chip->check_reg(chip, reg, bank);

drivers/gpio/gpio-pxa.c

162

struct pxa_gpio_bank *bank = p->banks + (gpio / 32);

drivers/gpio/gpio-pxa.c

164

return bank->regbase;

drivers/gpio/gpio-pxa.c

346

struct pxa_gpio_bank *bank;

drivers/gpio/gpio-pxa.c

370

bank = pchip->banks + i;

drivers/gpio/gpio-pxa.c

371

bank->regbase = regbase + BANK_OFF(i);

drivers/gpio/gpio-rockchip.c

107

static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,

drivers/gpio/gpio-rockchip.c

111

void __iomem *reg = bank->reg_base + offset;

drivers/gpio/gpio-rockchip.c

114

if (bank->gpio_type == GPIO_TYPE_V2) {

drivers/gpio/gpio-rockchip.c

129

static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,

drivers/gpio/gpio-rockchip.c

132

void __iomem *reg = bank->reg_base + offset;

drivers/gpio/gpio-rockchip.c

135

if (bank->gpio_type == GPIO_TYPE_V2) {

drivers/gpio/gpio-rockchip.c

149

struct rockchip_pin_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-rockchip.c

152

data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);

drivers/gpio/gpio-rockchip.c

162

struct rockchip_pin_bank *bank = gpiochip_get_data(chip);

drivers/gpio/gpio-rockchip.c

166

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

167

rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);

drivers/gpio/gpio-rockchip.c

168

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

176

struct rockchip_pin_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-rockchip.c

179

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

180

rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);

drivers/gpio/gpio-rockchip.c

181

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

188

struct rockchip_pin_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-rockchip.c

191

data = readl(bank->reg_base + bank->gpio_regs->ext_port);

drivers/gpio/gpio-rockchip.c

202

struct rockchip_pin_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-rockchip.c

203

const struct rockchip_gpio_regs *reg = bank->gpio_regs;

drivers/gpio/gpio-rockchip.c

209

if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {

drivers/gpio/gpio-rockchip.c

211

freq = clk_get_rate(bank->db_clk);

drivers/gpio/gpio-rockchip.c

222

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

228

cur_div_reg = readl(bank->reg_base +

drivers/gpio/gpio-rockchip.c

231

writel(div_reg, bank->reg_base +

drivers/gpio/gpio-rockchip.c

233

rockchip_gpio_writel_bit(bank, offset, 1,

drivers/gpio/gpio-rockchip.c

237

rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);

drivers/gpio/gpio-rockchip.c

240

rockchip_gpio_writel_bit(bank, offset, 0,

drivers/gpio/gpio-rockchip.c

243

rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);

drivers/gpio/gpio-rockchip.c

246

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

251

clk_prepare_enable(bank->db_clk);

drivers/gpio/gpio-rockchip.c

253

clk_disable_unprepare(bank->db_clk);

drivers/gpio/gpio-rockchip.c

309

struct rockchip_pin_bank *bank = gpiochip_get_data(gc);

drivers/gpio/gpio-rockchip.c

312

if (!bank->domain)

drivers/gpio/gpio-rockchip.c

315

virq = irq_create_mapping(bank->domain, offset);

drivers/gpio/gpio-rockchip.c

336

struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);

drivers/gpio/gpio-rockchip.c

340

dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);

drivers/gpio/gpio-rockchip.c

344

pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);

drivers/gpio/gpio-rockchip.c

346

dev_dbg(bank->dev, "handling irq %d\n", irq);

drivers/gpio/gpio-rockchip.c

352

if (bank->toggle_edge_mode & BIT(irq)) {

drivers/gpio/gpio-rockchip.c

356

data = readl_relaxed(bank->reg_base +

drivers/gpio/gpio-rockchip.c

357

bank->gpio_regs->ext_port);

drivers/gpio/gpio-rockchip.c

359

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

361

polarity = readl_relaxed(bank->reg_base +

drivers/gpio/gpio-rockchip.c

362

bank->gpio_regs->int_polarity);

drivers/gpio/gpio-rockchip.c

368

bank->reg_base +

drivers/gpio/gpio-rockchip.c

369

bank->gpio_regs->int_polarity);

drivers/gpio/gpio-rockchip.c

371

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

374

data = readl_relaxed(bank->reg_base +

drivers/gpio/gpio-rockchip.c

375

bank->gpio_regs->ext_port);

drivers/gpio/gpio-rockchip.c

379

generic_handle_domain_irq(bank->domain, irq);

drivers/gpio/gpio-rockchip.c

388

struct rockchip_pin_bank *bank = gc->private;

drivers/gpio/gpio-rockchip.c

396

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

398

rockchip_gpio_writel_bit(bank, d->hwirq, 0,

drivers/gpio/gpio-rockchip.c

399

bank->gpio_regs->port_ddr);

drivers/gpio/gpio-rockchip.c

401

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

408

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

410

level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);

drivers/gpio/gpio-rockchip.c

411

polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);

drivers/gpio/gpio-rockchip.c

414

if (bank->gpio_type == GPIO_TYPE_V2) {

drivers/gpio/gpio-rockchip.c

415

rockchip_gpio_writel_bit(bank, d->hwirq, 1,

drivers/gpio/gpio-rockchip.c

416

bank->gpio_regs->int_bothedge);

drivers/gpio/gpio-rockchip.c

419

bank->toggle_edge_mode |= mask;

drivers/gpio/gpio-rockchip.c

426

data = readl(bank->reg_base + bank->gpio_regs->ext_port);

drivers/gpio/gpio-rockchip.c

433

if (bank->gpio_type == GPIO_TYPE_V2) {

drivers/gpio/gpio-rockchip.c

434

rockchip_gpio_writel_bit(bank, d->hwirq, 0,

drivers/gpio/gpio-rockchip.c

435

bank->gpio_regs->int_bothedge);

drivers/gpio/gpio-rockchip.c

437

bank->toggle_edge_mode &= ~mask;

drivers/gpio/gpio-rockchip.c

462

rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);

drivers/gpio/gpio-rockchip.c

463

rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);

drivers/gpio/gpio-rockchip.c

465

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/gpio/gpio-rockchip.c

473

struct rockchip_pin_bank *bank = gc->private;

drivers/gpio/gpio-rockchip.c

475

return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);

drivers/gpio/gpio-rockchip.c

481

struct rockchip_pin_bank *bank = gc->private;

drivers/gpio/gpio-rockchip.c

483

gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);

drivers/gpio/gpio-rockchip.c

489

struct rockchip_pin_bank *bank = gc->private;

drivers/gpio/gpio-rockchip.c

491

bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);

drivers/gpio/gpio-rockchip.c

492

irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);

drivers/gpio/gpio-rockchip.c

498

struct rockchip_pin_bank *bank = gc->private;

drivers/gpio/gpio-rockchip.c

500

irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);

drivers/gpio/gpio-rockchip.c

513

static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)

drivers/gpio/gpio-rockchip.c

519

bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32, &irq_generic_chip_ops,

drivers/gpio/gpio-rockchip.c

521

if (!bank->domain) {

drivers/gpio/gpio-rockchip.c

522

dev_warn(bank->dev, "could not init irq domain for bank %s\n",

drivers/gpio/gpio-rockchip.c

523

bank->name);

drivers/gpio/gpio-rockchip.c

527

ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,

drivers/gpio/gpio-rockchip.c

532

dev_err(bank->dev, "could not alloc generic chips for bank %s\n",

drivers/gpio/gpio-rockchip.c

533

bank->name);

drivers/gpio/gpio-rockchip.c

534

irq_domain_remove(bank->domain);

drivers/gpio/gpio-rockchip.c

538

gc = irq_get_domain_generic_chip(bank->domain, 0);

drivers/gpio/gpio-rockchip.c

539

if (bank->gpio_type == GPIO_TYPE_V2) {

drivers/gpio/gpio-rockchip.c

544

gc->reg_base = bank->reg_base;

drivers/gpio/gpio-rockchip.c

545

gc->private = bank;

drivers/gpio/gpio-rockchip.c

546

gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;

drivers/gpio/gpio-rockchip.c

547

gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;

drivers/gpio/gpio-rockchip.c

559

gc->wake_enabled = IRQ_MSK(bank->nr_pins);

drivers/gpio/gpio-rockchip.c

566

rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);

drivers/gpio/gpio-rockchip.c

567

rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);

drivers/gpio/gpio-rockchip.c

568

rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);

drivers/gpio/gpio-rockchip.c

571

irq_set_chained_handler_and_data(bank->irq,

drivers/gpio/gpio-rockchip.c

572

rockchip_irq_demux, bank);

drivers/gpio/gpio-rockchip.c

577

static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)

drivers/gpio/gpio-rockchip.c

582

bank->gpio_chip = rockchip_gpiolib_chip;

drivers/gpio/gpio-rockchip.c

584

gc = &bank->gpio_chip;

drivers/gpio/gpio-rockchip.c

585

gc->base = bank->pin_base;

drivers/gpio/gpio-rockchip.c

586

gc->ngpio = bank->nr_pins;

drivers/gpio/gpio-rockchip.c

587

gc->label = bank->name;

drivers/gpio/gpio-rockchip.c

588

gc->parent = bank->dev;

drivers/gpio/gpio-rockchip.c

590

ret = gpiochip_add_data(gc, bank);

drivers/gpio/gpio-rockchip.c

592

dev_err(bank->dev, "failed to add gpiochip %s, %d\n",

drivers/gpio/gpio-rockchip.c

607

if (!of_property_present(bank->of_node, "gpio-ranges")) {

drivers/gpio/gpio-rockchip.c

608

struct device_node *pctlnp = of_get_parent(bank->of_node);

drivers/gpio/gpio-rockchip.c

622

dev_err(bank->dev, "Failed to add pin range\n");

drivers/gpio/gpio-rockchip.c

627

ret = rockchip_interrupts_register(bank);

drivers/gpio/gpio-rockchip.c

629

dev_err(bank->dev, "failed to register interrupt, %d\n", ret);

drivers/gpio/gpio-rockchip.c

636

gpiochip_remove(&bank->gpio_chip);

drivers/gpio/gpio-rockchip.c

641

static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)

drivers/gpio/gpio-rockchip.c

646

if (of_address_to_resource(bank->of_node, 0, &res)) {

drivers/gpio/gpio-rockchip.c

647

dev_err(bank->dev, "cannot find IO resource for bank\n");

drivers/gpio/gpio-rockchip.c

651

bank->reg_base = devm_ioremap_resource(bank->dev, &res);

drivers/gpio/gpio-rockchip.c

652

if (IS_ERR(bank->reg_base))

drivers/gpio/gpio-rockchip.c

653

return PTR_ERR(bank->reg_base);

drivers/gpio/gpio-rockchip.c

655

bank->irq = irq_of_parse_and_map(bank->of_node, 0);

drivers/gpio/gpio-rockchip.c

656

if (!bank->irq)

drivers/gpio/gpio-rockchip.c

659

bank->clk = of_clk_get(bank->of_node, 0);

drivers/gpio/gpio-rockchip.c

660

if (IS_ERR(bank->clk))

drivers/gpio/gpio-rockchip.c

661

return PTR_ERR(bank->clk);

drivers/gpio/gpio-rockchip.c

663

clk_prepare_enable(bank->clk);

drivers/gpio/gpio-rockchip.c

664

id = readl(bank->reg_base + gpio_regs_v2.version_id);

drivers/gpio/gpio-rockchip.c

670

bank->gpio_regs = &gpio_regs_v2;

drivers/gpio/gpio-rockchip.c

671

bank->gpio_type = GPIO_TYPE_V2;

drivers/gpio/gpio-rockchip.c

672

bank->db_clk = of_clk_get(bank->of_node, 1);

drivers/gpio/gpio-rockchip.c

673

if (IS_ERR(bank->db_clk)) {

drivers/gpio/gpio-rockchip.c

674

dev_err(bank->dev, "cannot find debounce clk\n");

drivers/gpio/gpio-rockchip.c

675

clk_disable_unprepare(bank->clk);

drivers/gpio/gpio-rockchip.c

680

bank->gpio_regs = &gpio_regs_v1;

drivers/gpio/gpio-rockchip.c

681

bank->gpio_type = GPIO_TYPE_V1;

drivers/gpio/gpio-rockchip.c

684

dev_err(bank->dev, "unsupported version ID: 0x%08x\n", id);

drivers/gpio/gpio-rockchip.c

695

struct rockchip_pin_bank *bank;

drivers/gpio/gpio-rockchip.c

699

bank = info->ctrl->pin_banks;

drivers/gpio/gpio-rockchip.c

700

for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {

drivers/gpio/gpio-rockchip.c

701

if (bank->bank_num == id) {

drivers/gpio/gpio-rockchip.c

707

return found ? bank : NULL;

drivers/gpio/gpio-rockchip.c

716

struct rockchip_pin_bank *bank = NULL;

drivers/gpio/gpio-rockchip.c

733

bank = rockchip_gpio_find_bank(pctldev, id);

drivers/gpio/gpio-rockchip.c

734

if (!bank)

drivers/gpio/gpio-rockchip.c

737

bank->dev = dev;

drivers/gpio/gpio-rockchip.c

738

bank->of_node = np;

drivers/gpio/gpio-rockchip.c

740

raw_spin_lock_init(&bank->slock);

drivers/gpio/gpio-rockchip.c

742

ret = rockchip_get_bank_data(bank);

drivers/gpio/gpio-rockchip.c

750

mutex_lock(&bank->deferred_lock);

drivers/gpio/gpio-rockchip.c

752

ret = rockchip_gpiolib_register(bank);

drivers/gpio/gpio-rockchip.c

754

clk_disable_unprepare(bank->clk);

drivers/gpio/gpio-rockchip.c

755

mutex_unlock(&bank->deferred_lock);

drivers/gpio/gpio-rockchip.c

759

while (!list_empty(&bank->deferred_pins)) {

drivers/gpio/gpio-rockchip.c

760

cfg = list_first_entry(&bank->deferred_pins,

drivers/gpio/gpio-rockchip.c

766

ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);

drivers/gpio/gpio-rockchip.c

772

ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);

drivers/gpio/gpio-rockchip.c

783

mutex_unlock(&bank->deferred_lock);

drivers/gpio/gpio-rockchip.c

785

platform_set_drvdata(pdev, bank);

drivers/gpio/gpio-rockchip.c

793

struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);

drivers/gpio/gpio-rockchip.c

795

clk_disable_unprepare(bank->clk);

drivers/gpio/gpio-rockchip.c

796

gpiochip_remove(&bank->gpio_chip);

drivers/gpio/gpio-rockchip.c

82

static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,

drivers/gpio/gpio-rockchip.c

85

void __iomem *reg = bank->reg_base + offset;

drivers/gpio/gpio-rockchip.c

87

if (bank->gpio_type == GPIO_TYPE_V2)

drivers/gpio/gpio-rockchip.c

93

static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,

drivers/gpio/gpio-rockchip.c

96

void __iomem *reg = bank->reg_base + offset;

drivers/gpio/gpio-rockchip.c

99

if (bank->gpio_type == GPIO_TYPE_V2)

drivers/gpio/gpio-sim.c

1018

struct gpio_sim_bank *bank;

drivers/gpio/gpio-sim.c

1027

list_for_each_entry(bank, &dev->bank_list, siblings) {

drivers/gpio/gpio-sim.c

1028

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

1105

struct gpio_sim_bank *bank = to_gpio_sim_bank(item);

drivers/gpio/gpio-sim.c

1106

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1107

struct gpio_sim_chip_name_ctx ctx = { bank->swnode, page };

drivers/gpio/gpio-sim.c

1123

struct gpio_sim_bank *bank = to_gpio_sim_bank(item);

drivers/gpio/gpio-sim.c

1124

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1128

return sprintf(page, "%s\n", bank->label ?: "");

drivers/gpio/gpio-sim.c

1134

struct gpio_sim_bank *bank = to_gpio_sim_bank(item);

drivers/gpio/gpio-sim.c

1135

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1147

kfree(bank->label);

drivers/gpio/gpio-sim.c

1148

bank->label = trimmed;

drivers/gpio/gpio-sim.c

1158

struct gpio_sim_bank *bank = to_gpio_sim_bank(item);

drivers/gpio/gpio-sim.c

1159

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1163

return sprintf(page, "%u\n", bank->num_lines);

drivers/gpio/gpio-sim.c

1170

struct gpio_sim_bank *bank = to_gpio_sim_bank(item);

drivers/gpio/gpio-sim.c

1171

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1187

bank->num_lines = num_lines;

drivers/gpio/gpio-sim.c

1455

struct gpio_sim_bank *bank = to_gpio_sim_bank(&group->cg_item);

drivers/gpio/gpio-sim.c

1456

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1477

line->parent = bank;

drivers/gpio/gpio-sim.c

1480

list_add_tail(&line->siblings, &bank->line_list);

drivers/gpio/gpio-sim.c

1487

struct gpio_sim_bank *bank = to_gpio_sim_bank(item);

drivers/gpio/gpio-sim.c

1488

struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

1491

list_del(&bank->siblings);

drivers/gpio/gpio-sim.c

1493

kfree(bank->label);

drivers/gpio/gpio-sim.c

1494

kfree(bank);

drivers/gpio/gpio-sim.c

1517

struct gpio_sim_bank *bank;

drivers/gpio/gpio-sim.c

1524

bank = kzalloc_obj(*bank);

drivers/gpio/gpio-sim.c

1525

if (!bank)

drivers/gpio/gpio-sim.c

1528

config_group_init_type_name(&bank->group, name,

drivers/gpio/gpio-sim.c

1530

bank->num_lines = 1;

drivers/gpio/gpio-sim.c

1531

bank->parent = dev;

drivers/gpio/gpio-sim.c

1532

INIT_LIST_HEAD(&bank->line_list);

drivers/gpio/gpio-sim.c

1533

list_add_tail(&bank->siblings, &dev->bank_list);

drivers/gpio/gpio-sim.c

1535

return &bank->group;

drivers/gpio/gpio-sim.c

610

static bool gpio_sim_bank_has_label(struct gpio_sim_bank *bank)

drivers/gpio/gpio-sim.c

612

return bank->label && *bank->label;

drivers/gpio/gpio-sim.c

616

gpio_sim_bank_get_device(struct gpio_sim_bank *bank)

drivers/gpio/gpio-sim.c

618

return bank->parent;

drivers/gpio/gpio-sim.c

647

struct gpio_sim_bank *bank = line->parent;

drivers/gpio/gpio-sim.c

649

return gpio_sim_bank_get_device(bank);

drivers/gpio/gpio-sim.c

719

static unsigned int gpio_sim_get_line_names_size(struct gpio_sim_bank *bank)

drivers/gpio/gpio-sim.c

724

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

725

if (!line->name || (line->offset >= bank->num_lines))

drivers/gpio/gpio-sim.c

735

gpio_sim_set_line_names(struct gpio_sim_bank *bank, char **line_names)

drivers/gpio/gpio-sim.c

739

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

740

if (!line->name || (line->offset >= bank->num_lines))

drivers/gpio/gpio-sim.c

747

static unsigned int gpio_sim_get_reserved_ranges_size(struct gpio_sim_bank *bank)

drivers/gpio/gpio-sim.c

752

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

762

static void gpio_sim_set_reserved_ranges(struct gpio_sim_bank *bank,

drivers/gpio/gpio-sim.c

768

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

798

struct gpio_sim_bank *bank;

drivers/gpio/gpio-sim.c

802

list_for_each_entry(bank, &dev->bank_list, siblings) {

drivers/gpio/gpio-sim.c

803

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

804

if (line->offset >= bank->num_lines)

drivers/gpio/gpio-sim.c

820

list_for_each_entry(bank, &dev->bank_list, siblings) {

drivers/gpio/gpio-sim.c

821

list_for_each_entry(line, &bank->line_list, siblings) {

drivers/gpio/gpio-sim.c

822

if (line->offset >= bank->num_lines)

drivers/gpio/gpio-sim.c

835

if (gpio_sim_bank_has_label(bank))

drivers/gpio/gpio-sim.c

836

hog->chip_label = kstrdup(bank->label,

drivers/gpio/gpio-sim.c

842

bank->swnode);

drivers/gpio/gpio-sim.c

874

gpio_sim_make_bank_swnode(struct gpio_sim_bank *bank,

drivers/gpio/gpio-sim.c

884

properties[prop_idx++] = PROPERTY_ENTRY_U32("ngpios", bank->num_lines);

drivers/gpio/gpio-sim.c

886

if (gpio_sim_bank_has_label(bank))

drivers/gpio/gpio-sim.c

888

bank->label);

drivers/gpio/gpio-sim.c

890

line_names_size = gpio_sim_get_line_names_size(bank);

drivers/gpio/gpio-sim.c

897

gpio_sim_set_line_names(bank, line_names);

drivers/gpio/gpio-sim.c

904

ranges_size = gpio_sim_get_reserved_ranges_size(bank);

drivers/gpio/gpio-sim.c

910

gpio_sim_set_reserved_ranges(bank, ranges);

drivers/gpio/gpio-sim.c

951

struct gpio_sim_bank *bank;

drivers/gpio/gpio-sim.c

973

list_for_each_entry(bank, &dev->bank_list, siblings) {

drivers/gpio/gpio-sim.c

974

bank->swnode = gpio_sim_make_bank_swnode(bank, swnode);

drivers/gpio/gpio-sim.c

975

if (IS_ERR(bank->swnode)) {

drivers/gpio/gpio-sim.c

976

ret = PTR_ERR(bank->swnode);

drivers/gpio/gpio-sprd.c

196

u32 bank, n;

drivers/gpio/gpio-sprd.c

200

for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {

drivers/gpio/gpio-sprd.c

201

void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);

drivers/gpio/gpio-sprd.c

207

bank * SPRD_GPIO_BANK_NR + n);

drivers/gpio/gpio-sprd.c

43

unsigned int bank)

drivers/gpio/gpio-sprd.c

45

return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;

drivers/gpio/gpio-stmpe.c

271

u8 bank = offset / 8;

drivers/gpio/gpio-stmpe.c

272

u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];

drivers/gpio/gpio-stmpe.c

322

edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];

drivers/gpio/gpio-stmpe.c

329

rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];

drivers/gpio/gpio-stmpe.c

330

fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];

drivers/gpio/gpio-stmpe.c

343

irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];

drivers/gpio/gpio-stmpe.c

416

int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :

drivers/gpio/gpio-stmpe.c

418

unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];

drivers/gpio/gpio-stmpe.c

427

int line = bank * 8 + bit;

drivers/gpio/gpio-tegra.c

114

static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,

drivers/gpio/gpio-tegra.c

117

return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);

drivers/gpio/gpio-tegra.c

232

struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];

drivers/gpio/gpio-tegra.c

249

spin_lock_irqsave(&bank->dbc_lock[port], flags);

drivers/gpio/gpio-tegra.c

250

if (bank->dbc_cnt[port] < debounce_ms) {

drivers/gpio/gpio-tegra.c

252

bank->dbc_cnt[port] = debounce_ms;

drivers/gpio/gpio-tegra.c

254

spin_unlock_irqrestore(&bank->dbc_lock[port], flags);

drivers/gpio/gpio-tegra.c

307

struct tegra_gpio_bank *bank;

drivers/gpio/gpio-tegra.c

312

bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];

drivers/gpio/gpio-tegra.c

339

raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);

drivers/gpio/gpio-tegra.c

346

raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

drivers/gpio/gpio-tegra.c

386

struct tegra_gpio_bank *bank = NULL;

drivers/gpio/gpio-tegra.c

394

bank = &tgi->bank_info[i];

drivers/gpio/gpio-tegra.c

399

if (WARN_ON(bank == NULL))

drivers/gpio/gpio-tegra.c

405

gpio = tegra_gpio_compose(bank->bank, port, 0);

drivers/gpio/gpio-tegra.c

469

struct tegra_gpio_bank *bank = &tgi->bank_info[b];

drivers/gpio/gpio-tegra.c

471

for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {

drivers/gpio/gpio-tegra.c

474

tegra_gpio_writel(tgi, bank->cnf[p],

drivers/gpio/gpio-tegra.c

478

tegra_gpio_writel(tgi, bank->dbc_cnt[p],

drivers/gpio/gpio-tegra.c

480

tegra_gpio_writel(tgi, bank->dbc_enb[p],

drivers/gpio/gpio-tegra.c

484

tegra_gpio_writel(tgi, bank->out[p],

drivers/gpio/gpio-tegra.c

486

tegra_gpio_writel(tgi, bank->oe[p],

drivers/gpio/gpio-tegra.c

488

tegra_gpio_writel(tgi, bank->int_lvl[p],

drivers/gpio/gpio-tegra.c

490

tegra_gpio_writel(tgi, bank->int_enb[p],

drivers/gpio/gpio-tegra.c

504

struct tegra_gpio_bank *bank = &tgi->bank_info[b];

drivers/gpio/gpio-tegra.c

506

for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {

drivers/gpio/gpio-tegra.c

509

bank->cnf[p] = tegra_gpio_readl(tgi,

drivers/gpio/gpio-tegra.c

511

bank->out[p] = tegra_gpio_readl(tgi,

drivers/gpio/gpio-tegra.c

513

bank->oe[p] = tegra_gpio_readl(tgi,

drivers/gpio/gpio-tegra.c

516

bank->dbc_enb[p] = tegra_gpio_readl(tgi,

drivers/gpio/gpio-tegra.c

518

bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |

drivers/gpio/gpio-tegra.c

519

bank->dbc_enb[p];

drivers/gpio/gpio-tegra.c

522

bank->int_enb[p] = tegra_gpio_readl(tgi,

drivers/gpio/gpio-tegra.c

524

bank->int_lvl[p] = tegra_gpio_readl(tgi,

drivers/gpio/gpio-tegra.c

528

tegra_gpio_writel(tgi, bank->wake_enb[p],

drivers/gpio/gpio-tegra.c

540

struct tegra_gpio_bank *bank;

drivers/gpio/gpio-tegra.c

545

bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];

drivers/gpio/gpio-tegra.c

551

err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);

drivers/gpio/gpio-tegra.c

558

irq_set_irq_wake(tgi->irqs[bank->bank], !enable);

drivers/gpio/gpio-tegra.c

564

bank->wake_enb[port] |= mask;

drivers/gpio/gpio-tegra.c

566

bank->wake_enb[port] &= ~mask;

drivers/gpio/gpio-tegra.c

64

unsigned int bank;

drivers/gpio/gpio-tegra.c

692

struct tegra_gpio_bank *bank;

drivers/gpio/gpio-tegra.c

749

bank = &tgi->bank_info[i];

drivers/gpio/gpio-tegra.c

750

bank->bank = i;

drivers/gpio/gpio-tegra.c

755

raw_spin_lock_init(&bank->lvl_lock[j]);

drivers/gpio/gpio-tegra.c

756

spin_lock_init(&bank->dbc_lock[j]);

drivers/gpio/gpio-tegra186.c

1029

irq->map[offset + j] = irq->parents[port->bank];

drivers/gpio/gpio-tegra186.c

1040

.bank = _bank, \

drivers/gpio/gpio-tegra186.c

167

offset = port->bank * 0x1000 + port->port * 0x200;

drivers/gpio/gpio-tegra186.c

182

offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;

drivers/gpio/gpio-tegra186.c

675

base = gpio->base + port->bank * 0x1000 + port->port * 0x200;

drivers/gpio/gpio-tegra186.c

679

if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])

drivers/gpio/gpio-tegra186.c

792

base = gpio->secure + port->bank * 0x1000 + 0x800;

drivers/gpio/gpio-tegra186.c

872

if (gpio->soc->ports[i].bank > gpio->num_banks)

drivers/gpio/gpio-tegra186.c

873

gpio->num_banks = gpio->soc->ports[i].bank;

drivers/gpio/gpio-tegra186.c

99

unsigned int bank;

drivers/gpio/gpio-thunderx.c

123

int bank = line / 64;

drivers/gpio/gpio-thunderx.c

127

(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);

drivers/gpio/gpio-thunderx.c

187

int bank = line / 64;

drivers/gpio/gpio-thunderx.c

191

void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;

drivers/gpio/gpio-thunderx.c

263

int bank = line / 64;

drivers/gpio/gpio-thunderx.c

265

u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);

drivers/gpio/gpio-thunderx.c

278

int bank;

drivers/gpio/gpio-thunderx.c

282

for (bank = 0; bank <= chip->ngpio / 64; bank++) {

drivers/gpio/gpio-thunderx.c

283

set_bits = bits[bank] & mask[bank];

drivers/gpio/gpio-thunderx.c

284

clear_bits = ~bits[bank] & mask[bank];

drivers/gpio/gpio-thunderx.c

285

writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);

drivers/gpio/gpio-thunderx.c

286

writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);

drivers/gpio/gpio-uniphier.c

101

unsigned int bank, reg_offset;

drivers/gpio/gpio-uniphier.c

104

uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);

drivers/gpio/gpio-uniphier.c

105

reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;

drivers/gpio/gpio-uniphier.c

152

unsigned long i, bank, bank_mask, bank_bits;

drivers/gpio/gpio-uniphier.c

155

bank = i / UNIPHIER_GPIO_LINES_PER_BANK;

drivers/gpio/gpio-uniphier.c

158

uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,

drivers/gpio/gpio-uniphier.c

36

static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)

drivers/gpio/gpio-uniphier.c

40

reg = (bank + 1) * 8;

drivers/gpio/gpio-uniphier.c

53

unsigned int *bank, u32 *mask)

drivers/gpio/gpio-uniphier.c

55

*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;

drivers/gpio/gpio-uniphier.c

73

static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,

drivers/gpio/gpio-uniphier.c

81

uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,

drivers/gpio/gpio-uniphier.c

89

unsigned int bank;

drivers/gpio/gpio-uniphier.c

92

uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);

drivers/gpio/gpio-uniphier.c

94

uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);

drivers/gpio/gpio-usbio.c

101

usbio_gpio_get_bank_and_pin(gc, offset, &bank, &pin);

drivers/gpio/gpio-usbio.c

116

struct usbio_gpio_bank *bank;

drivers/gpio/gpio-usbio.c

120

usbio_gpio_get_bank_and_pin(gc, offset, &bank, &pin);

drivers/gpio/gpio-usbio.c

124

bank->config[pin] &= ~mask;

drivers/gpio/gpio-usbio.c

125

bank->config[pin] |= value;

drivers/gpio/gpio-usbio.c

128

gbuf.config = bank->config[pin];

drivers/gpio/gpio-usbio.c

186

int bank, ret;

drivers/gpio/gpio-usbio.c

204

for (bank = 0; bank < USBIO_MAX_GPIOBANKS && bank_desc[bank].bmap; bank++)

drivers/gpio/gpio-usbio.c

205

gpio->banks[bank].bitmap = le32_to_cpu(bank_desc[bank].bmap);

drivers/gpio/gpio-usbio.c

218

gpio->gc.ngpio = bank * USBIO_GPIOSPERBANK;

drivers/gpio/gpio-usbio.c

43

struct usbio_gpio_bank *bank;

drivers/gpio/gpio-usbio.c

46

bank = &gpio->banks[offset / USBIO_GPIOSPERBANK];

drivers/gpio/gpio-usbio.c

48

if (~bank->bitmap & BIT(pin)) {

drivers/gpio/gpio-usbio.c

53

*bank_ret = bank;

drivers/gpio/gpio-usbio.c

59

struct usbio_gpio_bank *bank;

drivers/gpio/gpio-usbio.c

63

usbio_gpio_get_bank_and_pin(gc, offset, &bank, &pin);

drivers/gpio/gpio-usbio.c

65

cfg = bank->config[pin] & USBIO_GPIO_PINMOD_MASK;

drivers/gpio/gpio-usbio.c

74

struct usbio_gpio_bank *bank;

drivers/gpio/gpio-usbio.c

79

usbio_gpio_get_bank_and_pin(gc, offset, &bank, &pin);

drivers/gpio/gpio-usbio.c

97

struct usbio_gpio_bank *bank;

drivers/gpio/gpio-xgene.c

137

unsigned int bank;

drivers/gpio/gpio-xgene.c

139

for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {

drivers/gpio/gpio-xgene.c

140

bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;

drivers/gpio/gpio-xgene.c

141

gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);

drivers/gpio/gpio-xgene.c

150

unsigned int bank;

drivers/gpio/gpio-xgene.c

152

for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {

drivers/gpio/gpio-xgene.c

153

bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;

drivers/gpio/gpio-xgene.c

154

iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);

drivers/gpio/gpio-zynq.c

196

int bank;

drivers/gpio/gpio-zynq.c

198

for (bank = 0; bank < gpio->p_data->max_bank; bank++) {

drivers/gpio/gpio-zynq.c

199

if ((pin_num >= gpio->p_data->bank_min[bank]) &&

drivers/gpio/gpio-zynq.c

200

(pin_num <= gpio->p_data->bank_max[bank])) {

drivers/gpio/gpio-zynq.c

201

*bank_num = bank;

drivers/gpio/gpio-zynq.c

203

gpio->p_data->bank_min[bank];

drivers/gpio/gpio-zynq.c

207

bank = bank + VERSAL_UNUSED_BANKS;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

113

static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

120

bank->smu_err_type == ACA_SMU_TYPE_CE &&

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

121

!ACA_BANK_ERR_IS_DEFFERED(bank))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

128

idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

130

if (ACA_REG__STATUS__SCRUB(bank->regs[ACA_REG_IDX_STATUS]))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

134

static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

141

if (!bank || type == ACA_HWIP_TYPE_UNKNOW)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

148

ipid = bank->regs[ACA_REG_IDX_IPID];

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

161

struct aca_bank bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

186

memset(&bank, 0, sizeof(bank));

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

187

ret = smu_funcs->get_valid_aca_bank(adev, type, start + i, &bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

191

bank.smu_err_type = type;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

198

ACA_REG__STATUS__POISON(bank.regs[ACA_REG_IDX_STATUS]) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

199

!aca_bank_hwip_is_matched(&bank, ACA_HWIP_TYPE_UMC))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

202

aca_smu_bank_dump(adev, i, count, &bank, qctx);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

204

ret = aca_banks_add_bank(banks, &bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

212

static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

217

if (ACA_BANK_ERR_IS_DEFFERED(bank))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

220

if (!aca_bank_hwip_is_matched(bank, handle->hwip))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

226

return bank_ops->aca_bank_is_valid(handle, bank, type, handle->data);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

31

typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

318

static int aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

322

if (!bank)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

328

return bank_ops->aca_bank_parser(handle, bank, type,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

332

static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

337

ret = aca_bank_parser(handle, bank, type);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

344

static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

354

if (!aca_bank_is_valid(handle, bank, type))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

357

ret = handler(handle, bank, type, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

369

struct aca_bank *bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

380

bank = &node->bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

382

ret = aca_dispatch_bank(mgr, bank, type, handler, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

416

struct aca_bank *bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

433

bank = &node->bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

434

if (bank->aca_err_type == ACA_ERROR_TYPE_DEFERRED) {

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

435

r = aca_banks_add_bank(&de_banks, bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

439

if (amdgpu_cper_generate_ue_record(adev, bank))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

48

static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

52

if (!bank)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

59

memcpy(&node->bank, bank, sizeof(*bank));

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

813

int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

818

if (!bank || !info)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

821

ipid = bank->regs[ACA_REG_IDX_IPID];

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

837

static int aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

845

return smu_funcs->parse_error_code(adev, bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

848

int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

852

if (!bank || !err_codes)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

855

error_code = aca_bank_get_error_code(adev, bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

893

static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_smu_type type, int idx)

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

898

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

907

seq_printf(m, "aca entry[%d].regs[%d]: 0x%016llx\n", idx, aca_regs[i].reg_idx, bank->regs[aca_regs[i].reg_idx]);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

915

static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

920

aca_dump_entry(ctx->m, bank, type, ctx->idx++);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

922

return handler_aca_log_bank_error(handle, bank, type, NULL);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

133

struct aca_bank bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

186

int (*aca_bank_parser)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

187

bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

196

int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_smu_type type, int idx, struct aca_bank *bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

197

int (*parse_error_code)(struct amdgpu_device *adev, struct aca_bank *bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

219

int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

220

int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

79

#define ACA_BANK_ERR_IS_DEFFERED(bank) \

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

80

(ACA_REG__STATUS__POISON((bank)->regs[ACA_REG_IDX_STATUS]) || \

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

81

ACA_REG__STATUS__DEFERRED((bank)->regs[ACA_REG_IDX_STATUS]))

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

291

struct aca_bank *bank)

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

304

reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

305

reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

306

reg_data.addr_lo = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

307

reg_data.addr_hi = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

308

reg_data.ipid_lo = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

309

reg_data.ipid_hi = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

310

reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

311

reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

374

struct aca_bank *bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

386

bank = &node->bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

387

if (bank->aca_err_type == ACA_ERROR_TYPE_DEFERRED) {

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

397

bank = &node->bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

398

reg_data[CPER_ACA_REG_CTL_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

399

reg_data[CPER_ACA_REG_CTL_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

400

reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

401

reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

402

reg_data[CPER_ACA_REG_ADDR_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

403

reg_data[CPER_ACA_REG_ADDR_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

404

reg_data[CPER_ACA_REG_MISC0_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

405

reg_data[CPER_ACA_REG_MISC0_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

406

reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

407

reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

408

reg_data[CPER_ACA_REG_IPID_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

409

reg_data[CPER_ACA_REG_IPID_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

410

reg_data[CPER_ACA_REG_SYND_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

411

reg_data[CPER_ACA_REG_SYND_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

414

amdgpu_aca_err_type_to_cper_sev(adev, bank->aca_err_type),

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h

93

struct aca_bank *bank);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1140

uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1153

bank = (*pos & GENMASK_ULL(61, 60)) >> 60;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1171

if (bank == 0) {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

3143

err_data->err_addr[i].bank = bps[0].bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

3199

err_data->err_addr[i].bank = bps->bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

4942

if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1366

record.bank,

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

530

buf[i++] = record->bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

558

record->bank = buf[i++];

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h

139

unsigned char bank;

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1152

static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1161

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1165

status = bank->regs[ACA_REG_IDX_STATUS];

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1173

count = ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1180

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1185

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1186

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, count);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1560

uint32_t bank, way, mem;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1566

bank = instance / (blk->num_mem_blocks * blk->num_ways);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1573

bank, vml2_way_str[way], mem, sec_cnt, ded_cnt);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1577

vml2_walker_mems[bank], sec_cnt, ded_cnt);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1583

bank, utcl2_router_str[mem], sec_cnt, ded_cnt);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1589

bank, way, sec_cnt, ded_cnt);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1595

bank, way, mem, sec_cnt, ded_cnt);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1601

bank, way, mem, sec_cnt, ded_cnt);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

855

struct aca_bank *bank, enum aca_smu_type type,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

863

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

868

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

872

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

876

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

877

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

880

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

881

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

891

static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

896

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1387

static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1394

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1398

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1401

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1406

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1407

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1423

static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1428

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1434

if (aca_bank_check_error_codes(handle->adev, bank,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1005

static int jpeg_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1012

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1016

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1019

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1024

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1025

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1042

static bool jpeg_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1047

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1053

if (aca_bank_check_error_codes(handle->adev, bank,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

775

static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

782

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

786

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

789

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

794

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

795

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

815

static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

820

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

826

if (aca_bank_check_error_codes(handle->adev, bank,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2528

static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2535

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2539

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2542

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2547

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2548

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2561

static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2566

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2572

if (aca_bank_check_error_codes(handle->adev, bank,

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

171

uint32_t bank;

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

241

uint32_t col, col_lower, row, row_lower, row_high, bank;

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

254

err_addr = bank = 0;

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

266

bank = paddr_out->pa.bank;

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

315

soc_pa, row, col, bank, channel_index);

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

457

static int umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

467

status = bank->regs[ACA_REG_IDX_STATUS];

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

476

bank->aca_err_type = err_type;

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

478

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

483

bank->regs[ACA_REG_IDX_STATUS],

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

484

bank->regs[ACA_REG_IDX_IPID],

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

485

bank->regs[ACA_REG_IDX_ADDR]);

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

493

ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]) : 1ULL;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2131

static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2138

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2142

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2145

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2150

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2151

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2166

static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2171

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2177

if (aca_bank_check_error_codes(handle->adev, bank,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1715

static int vcn_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1722

ret = aca_bank_info_decode(bank, &info);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1726

misc0 = bank->regs[ACA_REG_IDX_MISC0];

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1729

bank->aca_err_type = ACA_ERROR_TYPE_UE;

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1734

bank->aca_err_type = ACA_ERROR_TYPE_CE;

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1735

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1750

static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1755

instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1761

if (aca_bank_check_error_codes(handle->adev, bank,

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3721

u32 tmp, width, row, column, bank, density;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3735

bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3737

density = (1 << (row + column - 20 + bank)) * width;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3777

enum aca_smu_type type, int idx, struct aca_bank *bank)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3781

count = min_t(int, 16, ARRAY_SIZE(bank->regs));

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3783

ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3791

static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3797

error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3799

error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

112

int idx, int total, struct aca_bank_reg *bank,

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

119

bank->seq_no);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

124

bank->seq_no, idx + 1, total,

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

125

aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

129

struct aca_bank_reg *bank, struct aca_bank_ecc *bank_ecc,

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

133

ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_UE, bank->regs, batch);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

135

ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_DE, bank->regs, batch);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

137

ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_CE, bank->regs, batch);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

146

static bool aca_match_bank(struct aca_block *aca_blk, struct aca_bank_reg *bank)

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

157

return bank_ops->bank_match(aca_blk, bank);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

162

struct aca_bank_reg *bank,

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

170

return bank_ops->bank_parse(ras_core, aca_blk, bank, ecc);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

204

struct aca_block *aca_blk, struct aca_bank_reg *bank,

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

241

ras_ecc.seq_no = bank->seq_no;

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

250

bank->seq_no, aca_blk->blk_info->ras_block_id, info->socket_id, info->die_id,

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

257

struct aca_bank_reg *bank)

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

262

if (aca_match_bank(&ras_core->ras_aca.aca_blk[i], bank))

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

271

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

274

reg_cnt = min_t(int, 16, ARRAY_SIZE(bank->regs));

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

276

ret = ras_mp1_dump_bank(ras_core, ecc_type, idx, i, &bank->regs[i]);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

348

struct aca_bank_reg bank;

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

370

memset(&bank, 0, sizeof(bank));

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

371

ret = aca_dump_bank(ras_core, ecc_type, i, &bank);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

375

bank.ecc_type = ecc_type;

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

378

aca_blk = aca_get_bank_aca_block(ras_core, &bank);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

380

ret = aca_parse_bank(ras_core, aca_blk, &bank, &bank_ecc);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

382

bank.seq_no = aca_get_bank_seqno(ras_core, ecc_type, aca_blk, &bank_ecc);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

384

aca_log_bank_data(ras_core, &bank, &bank_ecc, batch_tag);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

385

aca_bank_log(ras_core, i, count, &bank, &bank_ecc);

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

388

ret = aca_log_bad_bank(ras_core, aca_blk, &bank, &bank_ecc);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

100

instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

116

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

122

if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip))

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

125

instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

130

errcode = ACA_REG_SYND_ERRORINFORMATION(bank->regs[ACA_REG_IDX__SYND]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

144

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

157

if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip))

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

160

instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

165

errcode = ACA_REG_SYND_ERRORINFORMATION(bank->regs[ACA_REG_IDX__SYND]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

213

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

219

status0 = bank->regs[ACA_REG_IDX__STATUS];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

224

aca_decode_bank_info(ras_blk, bank, &bank_info);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

226

ecc->bank_info.status = bank->regs[ACA_REG_IDX__STATUS];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

227

ecc->bank_info.ipid = bank->regs[ACA_REG_IDX__IPID];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

228

ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

236

1 : ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

239

1 : ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

255

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

258

u64 misc0 = bank->regs[ACA_REG_IDX__MISC0];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

259

u64 status = bank->regs[ACA_REG_IDX__STATUS];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

262

aca_decode_bank_info(ras_blk, bank, &bank_info);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

265

ecc->bank_info.ipid = bank->regs[ACA_REG_IDX__IPID];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

266

ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

271

if (bank->ecc_type == RAS_ERR_TYPE__UE)

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

273

else if (bank->ecc_type == RAS_ERR_TYPE__CE)

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

284

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

291

aca_decode_bank_info(ras_blk, bank, &bank_info);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

293

ecc->bank_info.status = bank->regs[ACA_REG_IDX__STATUS];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

294

ecc->bank_info.ipid = bank->regs[ACA_REG_IDX__IPID];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

295

ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

297

status = bank->regs[ACA_REG_IDX__STATUS];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

300

count = ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

301

if (bank->ecc_type == RAS_ERR_TYPE__UE) {

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

305

} else if (bank->ecc_type == RAS_ERR_TYPE__CE) {

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

41

struct aca_bank_reg *bank, struct aca_ecc_info *info)

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

46

ipid = bank->regs[ACA_REG_IDX__IPID];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

67

static bool aca_check_bank_hwip(struct aca_bank_reg *bank, enum aca_ecc_hwip type)

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

73

if (!bank || (type == ACA_ECC_HWIP__UNKNOWN))

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

80

ipid = bank->regs[ACA_REG_IDX__IPID];

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

94

struct aca_bank_reg *bank = (struct aca_bank_reg *)data;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

97

if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip))

drivers/gpu/drm/amd/ras/rascore/ras_cmd.c

494

bank_addr->bank = umc_bank.bank;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.c

510

umc_bank.bank = bank_addr.bank;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.c

80

ras_cmd_record->bank = record->bank;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

238

unsigned char bank;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

302

uint32_t bank;

drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c

511

buf[i++] = record->bank;

drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c

539

record->bank = buf[i++];

drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h

162

unsigned char bank;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

183

uint32_t bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

117

out->bank = addr_out.pa.bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

197

int ras_umc_log_bad_bank_pending(struct ras_core_context *ras_core, struct ras_bank_ecc *bank)

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

206

memcpy(&ecc_node->ecc, bank, sizeof(ecc_node->ecc));

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

235

int ras_umc_log_bad_bank(struct ras_core_context *ras_core, struct ras_bank_ecc *bank)

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

245

ret = ras_umc->ip_func->bank_to_eeprom_record(ras_core, bank, &umc_rec);

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

670

err_rec->cur_nps_bank = cur_nps_addr->bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc.h

101

struct ras_bank_ecc *bank, struct eeprom_umc_record *record);

drivers/gpu/drm/amd/ras/rascore/ras_umc.h

150

int ras_umc_log_bad_bank(struct ras_core_context *ras, struct ras_bank_ecc *bank);

drivers/gpu/drm/amd/ras/rascore/ras_umc.h

151

int ras_umc_log_bad_bank_pending(struct ras_core_context *ras_core, struct ras_bank_ecc *bank);

drivers/gpu/drm/amd/ras/rascore/ras_umc.h

85

uint32_t bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc.h

92

uint32_t bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

203

uint32_t bank0, bank1, bank2, bank3, bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

248

bank = bank0 | (bank1 << 1) | (bank2 << 2) | (bank3 << 3);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

250

err_addr |= (bank << UMC_V12_0_MCA_B0_BIT);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

310

addr_out->bank = bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

333

struct ras_bank_ecc *bank, struct umc_phy_addr *pa_addr, uint32_t nps)

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

342

addr_in.err_addr = ACA_ADDR_2_ERR_ADDR(bank->addr);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

343

addr_in.ch_inst = ACA_IPID_2_UMC_CH(bank->ipid);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

344

addr_in.umc_inst = ACA_IPID_2_UMC_INST(bank->ipid);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

345

addr_in.node_inst = ACA_IPID_2_DIE_ID(bank->ipid);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

346

addr_in.socket_id = ACA_IPID_2_SOCKET_ID(bank->ipid);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

353

pa_addr->bank = addr_out.bank;

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

360

struct ras_bank_ecc *bank, struct eeprom_umc_record *record)

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

367

ret = convert_bank_to_nps_addr(ras_core, bank,

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

368

&nps_addr, bank->nps);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

373

ACA_ADDR_2_ERR_ADDR(bank->addr), ACA_IPID_2_UMC_INST(bank->ipid),

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

374

&nps_addr, bank->nps, record);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

377

bank->nps, NULL, 0, bank->seq_no, true);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

450

bank_addr->bank = UMC_V12_0_SOC_PA_TO_BANK(soc_pa);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c

481

tmp_pa |= UMC_V12_0_SOC_BANK_TO_PA(bank_addr.bank);

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

157

#define UMC_V12_0_SOC_BANK_TO_PA(bank) \

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

158

((((bank >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_B0_BIT) | \

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

159

(((bank >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_B1_BIT) | \

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

160

(((bank >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_B2_BIT) | \

drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h

161

(((bank >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_B3_BIT))

drivers/gpu/drm/i915/gt/intel_gt_irq.c

149

gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)

drivers/gpu/drm/i915/gt/intel_gt_irq.c

157

intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));

drivers/gpu/drm/i915/gt/intel_gt_irq.c

160

const u32 ident = gen11_gt_engine_identity(gt, bank, bit);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

166

raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

171

unsigned int bank;

drivers/gpu/drm/i915/gt/intel_gt_irq.c

175

for (bank = 0; bank < 2; bank++) {

drivers/gpu/drm/i915/gt/intel_gt_irq.c

176

if (master_ctl & GEN11_GT_DW_IRQ(bank))

drivers/gpu/drm/i915/gt/intel_gt_irq.c

177

gen11_gt_bank_handler(gt, bank);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

184

const unsigned int bank, const unsigned int bit)

drivers/gpu/drm/i915/gt/intel_gt_irq.c

191

dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));

drivers/gpu/drm/i915/gt/intel_gt_irq.c

197

gen11_gt_engine_identity(gt, bank, bit);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

205

raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));

drivers/gpu/drm/i915/gt/intel_gt_irq.c

32

const unsigned int bank, const unsigned int bit)

drivers/gpu/drm/i915/gt/intel_gt_irq.c

40

raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));

drivers/gpu/drm/i915/gt/intel_gt_irq.c

48

ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));

drivers/gpu/drm/i915/gt/intel_gt_irq.c

54

bank, bit, ident);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

58

raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),

drivers/gpu/drm/i915/gt/intel_gt_irq.h

28

const unsigned int bank,

drivers/gpu/drm/i915/i915_irq.c

161

u32 error_status, row, bank, subbank;

drivers/gpu/drm/i915/i915_irq.c

189

bank = GEN7_PARITY_ERROR_BANK(error_status);

drivers/gpu/drm/i915/i915_irq.c

197

parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);

drivers/gpu/drm/i915/i915_irq.c

207

slice, row, bank, subbank);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2293

u8 bank[GPC_MAX] = {}, gpc, i, j;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2298

data |= bank[gr->tile[i + j]] << (j * 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2299

bank[gr->tile[i + j]]++;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c

131

u8 bank[GPC_MAX] = {}, gpc, i, j;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c

136

data |= bank[gr->tile[i + j]] << (j * 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c

137

bank[gr->tile[i + j]]++;

drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

60

u8 bank[GPC_MAX] = {}, gpc, i, j;

drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

65

data |= bank[gr->tile[i + j]] << (j * 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

66

bank[gr->tile[i + j]]++;

drivers/gpu/drm/radeon/si_dpm.c

3151

u32 tmp, width, row, column, bank, density;

drivers/gpu/drm/radeon/si_dpm.c

3165

bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;

drivers/gpu/drm/radeon/si_dpm.c

3167

density = (1 << (row + column - 20 + bank)) * width;

drivers/gpu/drm/xe/xe_gt_mcr.c

316

u32 bank = __ffs(mslice_mask) * 8;

drivers/gpu/drm/xe/xe_gt_mcr.c

323

gt->steering[L3BANK].group_target = (bank >> 2) & 0x7;

drivers/gpu/drm/xe/xe_gt_mcr.c

324

gt->steering[L3BANK].instance_target = bank & 0x3;

drivers/gpu/drm/xe/xe_irq.c

274

const unsigned int bank,

drivers/gpu/drm/xe/xe_irq.c

282

xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));

drivers/gpu/drm/xe/xe_irq.c

290

ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));

drivers/gpu/drm/xe/xe_irq.c

296

bank, bit, ident);

drivers/gpu/drm/xe/xe_irq.c

300

xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident);

drivers/gpu/drm/xe/xe_irq.c

358

unsigned int bank, bit;

drivers/gpu/drm/xe/xe_irq.c

365

for (bank = 0; bank < 2; bank++) {

drivers/gpu/drm/xe/xe_irq.c

366

if (!(master_ctl & GT_DW_IRQ(bank)))

drivers/gpu/drm/xe/xe_irq.c

369

intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));

drivers/gpu/drm/xe/xe_irq.c

370

for_each_set_bit(bit, intr_dw + bank, 32)

drivers/gpu/drm/xe/xe_irq.c

371

identity[bit] = gt_engine_identity(xe, mmio, bank, bit);

drivers/gpu/drm/xe/xe_irq.c

372

xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);

drivers/gpu/drm/xe/xe_irq.c

374

for_each_set_bit(bit, intr_dw + bank, 32) {

drivers/hwmon/abituguru3.c

737

static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset,

drivers/hwmon/abituguru3.c

750

"sending 0x1A, status: 0x%02x\n", (unsigned int)bank,

drivers/hwmon/abituguru3.c

755

outb(bank, data->addr + ABIT_UGURU3_CMD);

drivers/hwmon/abituguru3.c

760

(unsigned int)bank, (unsigned int)offset, x);

drivers/hwmon/abituguru3.c

769

(unsigned int)bank, (unsigned int)offset, x);

drivers/hwmon/abituguru3.c

778

(unsigned int)bank, (unsigned int)offset, x);

drivers/hwmon/abituguru3.c

787

(unsigned int)bank, (unsigned int)offset, x);

drivers/hwmon/abituguru3.c

800

u8 bank, u8 offset, u8 count,

drivers/hwmon/abituguru3.c

806

x = abituguru3_read(data, bank, offset + i, count,

drivers/hwmon/asb100.c

844

int res, bank;

drivers/hwmon/asb100.c

848

bank = (reg >> 8) & 0x0f;

drivers/hwmon/asb100.c

849

if (bank > 2)

drivers/hwmon/asb100.c

851

i2c_smbus_write_byte_data(client, ASB100_REG_BANK, bank);

drivers/hwmon/asb100.c

853

if (bank == 0 || bank > 2) {

drivers/hwmon/asb100.c

857

cl = data->lm75[bank - 1];

drivers/hwmon/asb100.c

877

if (bank > 2)

drivers/hwmon/asb100.c

889

int bank;

drivers/hwmon/asb100.c

893

bank = (reg >> 8) & 0x0f;

drivers/hwmon/asb100.c

894

if (bank > 2)

drivers/hwmon/asb100.c

896

i2c_smbus_write_byte_data(client, ASB100_REG_BANK, bank);

drivers/hwmon/asb100.c

898

if (bank == 0 || bank > 2) {

drivers/hwmon/asb100.c

902

cl = data->lm75[bank - 1];

drivers/hwmon/asb100.c

918

if (bank > 2)

drivers/hwmon/asus-ec-sensors.c

100

.addr = MAKE_SENSOR_ADDRESS(size, bank, index), \

drivers/hwmon/asus-ec-sensors.c

1011

u8 bank;

drivers/hwmon/asus-ec-sensors.c

1023

bank = ec->sensors_info[s->info_index].addr.components.bank;

drivers/hwmon/asus-ec-sensors.c

1025

if (ec->banks[j] == bank) {

drivers/hwmon/asus-ec-sensors.c

1031

ec->banks[ec->nr_banks++] = bank;

drivers/hwmon/asus-ec-sensors.c

1047

(si->addr.components.bank << 8) +

drivers/hwmon/asus-ec-sensors.c

1085

static int asus_ec_bank_switch(u8 bank, u8 *old)

drivers/hwmon/asus-ec-sensors.c

1092

if (status || (old && (*old == bank)))

drivers/hwmon/asus-ec-sensors.c

1094

return ec_write(ASUS_EC_BANK_REGISTER, bank);

drivers/hwmon/asus-ec-sensors.c

1101

u8 bank, reg_bank, prev_bank;

drivers/hwmon/asus-ec-sensors.c

1103

bank = 0;

drivers/hwmon/asus-ec-sensors.c

1104

status = asus_ec_bank_switch(bank, &prev_bank);

drivers/hwmon/asus-ec-sensors.c

1118

if (bank != ec->banks[ibank]) {

drivers/hwmon/asus-ec-sensors.c

1119

bank = ec->banks[ibank];

drivers/hwmon/asus-ec-sensors.c

1120

if (asus_ec_bank_switch(bank, NULL)) {

drivers/hwmon/asus-ec-sensors.c

1122

bank);

drivers/hwmon/asus-ec-sensors.c

1128

if (reg_bank < bank) {

drivers/hwmon/asus-ec-sensors.c

74

u8 bank;

drivers/hwmon/asus-ec-sensors.c

80

#define MAKE_SENSOR_ADDRESS(size, bank, index) { \

drivers/hwmon/asus-ec-sensors.c

81

.value = (size << 16) + (bank << 8) + index \

drivers/hwmon/asus-ec-sensors.c

98

#define EC_SENSOR(sensor_label, sensor_type, size, bank, index) { \

drivers/hwmon/nct6775-core.c

3526

data->bank = 0xff; /* Force initial bank selection */

drivers/hwmon/nct6775-i2c.c

32

u8 bank = reg >> 8;

drivers/hwmon/nct6775-i2c.c

36

if (bank != data->bank) {

drivers/hwmon/nct6775-i2c.c

37

ret = i2c_smbus_write_byte_data(client, NCT6775_REG_BANK, bank);

drivers/hwmon/nct6775-i2c.c

40

data->bank = bank;

drivers/hwmon/nct6775-platform.c

129

static int nct6775_asuswmi_evaluate_method(u32 method_id, u8 bank, u8 reg, u8 val, u32 *retval)

drivers/hwmon/nct6775-platform.c

133

u32 args = bank | (reg << 8) | (val << 16);

drivers/hwmon/nct6775-platform.c

162

static inline int nct6775_asuswmi_write(u8 bank, u8 reg, u8 val)

drivers/hwmon/nct6775-platform.c

164

return nct6775_asuswmi_evaluate_method(ASUSWMI_METHODID_WHWM, bank,

drivers/hwmon/nct6775-platform.c

168

static inline int nct6775_asuswmi_read(u8 bank, u8 reg, u8 *val)

drivers/hwmon/nct6775-platform.c

173

ret = nct6775_asuswmi_evaluate_method(ASUSWMI_METHODID_RHWM, bank,

drivers/hwmon/nct6775-platform.c

260

u8 bank = reg >> 8;

drivers/hwmon/nct6775-platform.c

262

data->bank = bank;

drivers/hwmon/nct6775-platform.c

274

err = nct6775_asuswmi_read(data->bank, reg & 0xff, &tmp);

drivers/hwmon/nct6775-platform.c

280

err = nct6775_asuswmi_read(data->bank, (reg & 0xff) + 1, &tmp);

drivers/hwmon/nct6775-platform.c

298

res = nct6775_asuswmi_write(data->bank, reg & 0xff, value >> 8);

drivers/hwmon/nct6775-platform.c

302

res = nct6775_asuswmi_write(data->bank, (reg & 0xff) + 1, value);

drivers/hwmon/nct6775-platform.c

304

res = nct6775_asuswmi_write(data->bank, reg & 0xff, value);

drivers/hwmon/nct6775-platform.c

318

u8 bank = reg >> 8;

drivers/hwmon/nct6775-platform.c

320

if (data->bank != bank) {

drivers/hwmon/nct6775-platform.c

322

outb_p(bank, data->addr + DATA_REG_OFFSET);

drivers/hwmon/nct6775-platform.c

323

data->bank = bank;

drivers/hwmon/nct6775-platform.c

410

data->bank = 0xff; /* Force initial bank selection */

drivers/hwmon/nct6775.h

99

u8 bank; /* current register bank */

drivers/hwmon/nct7904.c

143

static int nct7904_bank_select(struct nct7904_data *data, unsigned int bank)

drivers/hwmon/nct7904.c

147

if (data->bank_sel == bank)

drivers/hwmon/nct7904.c

149

ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);

drivers/hwmon/nct7904.c

154

data->bank_sel = bank;

drivers/hwmon/nct7904.c

160

unsigned int bank, unsigned int reg)

drivers/hwmon/nct7904.c

165

ret = nct7904_bank_select(data, bank);

drivers/hwmon/nct7904.c

176

unsigned int bank, unsigned int reg)

drivers/hwmon/nct7904.c

181

ret = nct7904_bank_select(data, bank);

drivers/hwmon/nct7904.c

195

unsigned int bank, unsigned int reg, u8 val)

drivers/hwmon/nct7904.c

200

ret = nct7904_bank_select(data, bank);

drivers/hwmon/pc87360.c

229

static int pc87360_read_value(struct pc87360_data *data, u8 ldi, u8 bank,

drivers/hwmon/pc87360.c

235

if (bank != NO_BANK)

drivers/hwmon/pc87360.c

236

outb_p(bank, data->address[ldi] + PC87365_REG_BANK);

drivers/hwmon/pc87360.c

243

static void pc87360_write_value(struct pc87360_data *data, u8 ldi, u8 bank,

drivers/hwmon/pc87360.c

247

if (bank != NO_BANK)

drivers/hwmon/pc87360.c

248

outb_p(bank, data->address[ldi] + PC87365_REG_BANK);

drivers/hwmon/pc87427.c

151

u8 bank, u8 reg)

drivers/hwmon/pc87427.c

153

outb(bank, data->address[ldi] + PC87427_REG_BANK);

drivers/hwmon/pc87427.c

159

u8 bank, u8 reg, u8 value)

drivers/hwmon/pc87427.c

161

outb(bank, data->address[ldi] + PC87427_REG_BANK);

drivers/hwmon/spd5118.c

303

static bool spd5118_vendor_valid(u8 bank, u8 id)

drivers/hwmon/spd5118.c

305

if (parity8(bank) == 0 || parity8(id) == 0)

drivers/hwmon/spd5118.c

525

unsigned int capability, revision, vendor, bank;

drivers/hwmon/spd5118.c

546

err = regmap_read(regmap, SPD5118_REG_VENDOR, &bank);

drivers/hwmon/spd5118.c

552

if (!spd5118_vendor_valid(bank, vendor))

drivers/hwmon/spd5118.c

578

bank & 0x7f, vendor, ((revision >> 4) & 0x03) + 1, ((revision >> 1) & 0x07) + 1);

drivers/hwmon/w83627ehf.c

1720

data->bank = 0xff; /* Force initial bank selection */

drivers/hwmon/w83627ehf.c

1967

data->bank = 0xff; /* Force initial bank selection */

drivers/hwmon/w83627ehf.c

327

u8 bank; /* current register bank */

drivers/hwmon/w83627ehf.c

394

u8 bank = reg >> 8;

drivers/hwmon/w83627ehf.c

395

if (data->bank != bank) {

drivers/hwmon/w83627ehf.c

397

outb_p(bank, data->addr + DATA_REG_OFFSET);

drivers/hwmon/w83627ehf.c

398

data->bank = bank;

drivers/hwmon/w83781d.c

1257

int res, bank;

drivers/hwmon/w83781d.c

1260

bank = (reg >> 8) & 0x0f;

drivers/hwmon/w83781d.c

1261

if (bank > 2)

drivers/hwmon/w83781d.c

1264

bank);

drivers/hwmon/w83781d.c

1265

if (bank == 0 || bank > 2) {

drivers/hwmon/w83781d.c

1269

cl = data->lm75[bank - 1];

drivers/hwmon/w83781d.c

1287

if (bank > 2)

drivers/hwmon/w83781d.c

1297

int bank;

drivers/hwmon/w83781d.c

1300

bank = (reg >> 8) & 0x0f;

drivers/hwmon/w83781d.c

1301

if (bank > 2)

drivers/hwmon/w83781d.c

1304

bank);

drivers/hwmon/w83781d.c

1305

if (bank == 0 || bank > 2) {

drivers/hwmon/w83781d.c

1310

cl = data->lm75[bank - 1];

drivers/hwmon/w83781d.c

1324

if (bank > 2)

drivers/hwmon/w83793.c

1604

u8 tmp, bank, chip_id;

drivers/hwmon/w83793.c

1611

bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL);

drivers/hwmon/w83793.c

1613

tmp = bank & 0x80 ? 0x5c : 0xa3;

drivers/hwmon/w83793.c

1624

if ((bank & 0x07) == 0

drivers/hwmon/w83793.c

1660

data->bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL);

drivers/hwmon/w83793.c

2094

new_bank |= data->bank & 0xfc;

drivers/hwmon/w83793.c

2095

if (data->bank != new_bank) {

drivers/hwmon/w83793.c

2098

data->bank = new_bank;

drivers/hwmon/w83793.c

2103

new_bank, data->bank, reg);

drivers/hwmon/w83793.c

2120

new_bank |= data->bank & 0xfc;

drivers/hwmon/w83793.c

2121

if (data->bank != new_bank) {

drivers/hwmon/w83793.c

2128

new_bank, data->bank, reg);

drivers/hwmon/w83793.c

213

u8 bank;

drivers/hwmon/w83793.c

2131

data->bank = new_bank;

drivers/hwmon/w83795.c

1905

int bank, vendor_id, device_id, expected, i2c_addr, config;

drivers/hwmon/w83795.c

1912

bank = i2c_smbus_read_byte_data(client, W83795_REG_BANKSEL);

drivers/hwmon/w83795.c

1913

if (bank < 0 || (bank & 0x7c)) {

drivers/hwmon/w83795.c

1922

expected = bank & 0x80 ? 0x5c : 0xa3;

drivers/hwmon/w83795.c

1944

if ((bank & 0x07) == 0) {

drivers/hwmon/w83795.c

1961

if ((bank & 0x07) != 0)

drivers/hwmon/w83795.c

1963

bank & ~0x07);

drivers/hwmon/w83795.c

2151

data->bank = i2c_smbus_read_byte_data(client, W83795_REG_BANKSEL);

drivers/hwmon/w83795.c

326

u8 bank;

drivers/hwmon/w83795.c

393

static int w83795_set_bank(struct i2c_client *client, u8 bank)

drivers/hwmon/w83795.c

399

if ((data->bank & 0x07) == bank)

drivers/hwmon/w83795.c

403

bank |= data->bank & ~0x07;

drivers/hwmon/w83795.c

404

err = i2c_smbus_write_byte_data(client, W83795_REG_BANKSEL, bank);

drivers/hwmon/w83795.c

408

(int)bank, err);

drivers/hwmon/w83795.c

411

data->bank = bank;

drivers/hwspinlock/hwspinlock_core.c

133

ret = hwlock->bank->ops->trylock(hwlock);

drivers/hwspinlock/hwspinlock_core.c

241

if (hwlock->bank->ops->relax)

drivers/hwspinlock/hwspinlock_core.c

242

hwlock->bank->ops->relax(hwlock);

drivers/hwspinlock/hwspinlock_core.c

287

hwlock->bank->ops->unlock(hwlock);

drivers/hwspinlock/hwspinlock_core.c

327

if (!hwlock->bank->ops->bust) {

drivers/hwspinlock/hwspinlock_core.c

332

return hwlock->bank->ops->bust(hwlock, id);

drivers/hwspinlock/hwspinlock_core.c

401

if (device_match_of_node(hwlock->bank->dev, args.np)) {

drivers/hwspinlock/hwspinlock_core.c

411

if (id < 0 || id >= hwlock->bank->num_locks) {

drivers/hwspinlock/hwspinlock_core.c

415

id += hwlock->bank->base_id;

drivers/hwspinlock/hwspinlock_core.c

518

int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev,

drivers/hwspinlock/hwspinlock_core.c

524

if (!bank || !ops || !dev || !num_locks || !ops->trylock ||

drivers/hwspinlock/hwspinlock_core.c

530

bank->dev = dev;

drivers/hwspinlock/hwspinlock_core.c

531

bank->ops = ops;

drivers/hwspinlock/hwspinlock_core.c

532

bank->base_id = base_id;

drivers/hwspinlock/hwspinlock_core.c

533

bank->num_locks = num_locks;

drivers/hwspinlock/hwspinlock_core.c

536

hwlock = &bank->lock[i];

drivers/hwspinlock/hwspinlock_core.c

539

hwlock->bank = bank;

drivers/hwspinlock/hwspinlock_core.c

566

int hwspin_lock_unregister(struct hwspinlock_device *bank)

drivers/hwspinlock/hwspinlock_core.c

571

for (i = 0; i < bank->num_locks; i++) {

drivers/hwspinlock/hwspinlock_core.c

572

hwlock = &bank->lock[i];

drivers/hwspinlock/hwspinlock_core.c

574

tmp = hwspin_lock_unregister_single(bank->base_id + i);

drivers/hwspinlock/hwspinlock_core.c

594

struct hwspinlock_device **bank = res;

drivers/hwspinlock/hwspinlock_core.c

596

if (WARN_ON(!bank || !*bank))

drivers/hwspinlock/hwspinlock_core.c

599

return *bank == data;

drivers/hwspinlock/hwspinlock_core.c

616

struct hwspinlock_device *bank)

drivers/hwspinlock/hwspinlock_core.c

621

devm_hwspin_lock_device_match, bank);

drivers/hwspinlock/hwspinlock_core.c

645

struct hwspinlock_device *bank,

drivers/hwspinlock/hwspinlock_core.c

656

ret = hwspin_lock_register(bank, dev, ops, base_id, num_locks);

drivers/hwspinlock/hwspinlock_core.c

658

*ptr = bank;

drivers/hwspinlock/hwspinlock_core.c

681

struct device *dev = hwlock->bank->dev;

drivers/hwspinlock/hwspinlock_core.c

784

dev = hwlock->bank->dev;

drivers/hwspinlock/hwspinlock_internal.h

44

struct hwspinlock_device *bank;

drivers/hwspinlock/hwspinlock_internal.h

67

int local_id = hwlock - &hwlock->bank->lock[0];

drivers/hwspinlock/hwspinlock_internal.h

69

return hwlock->bank->base_id + local_id;

drivers/hwspinlock/omap_hwspinlock.c

114

bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),

drivers/hwspinlock/omap_hwspinlock.c

116

if (!bank)

drivers/hwspinlock/omap_hwspinlock.c

120

bank->lock[i].priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;

drivers/hwspinlock/omap_hwspinlock.c

122

return devm_hwspin_lock_register(&pdev->dev, bank, &omap_hwspinlock_ops,

drivers/hwspinlock/omap_hwspinlock.c

77

struct hwspinlock_device *bank;

drivers/hwspinlock/qcom_hwspinlock.c

204

struct hwspinlock_device *bank;

drivers/hwspinlock/qcom_hwspinlock.c

220

bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL);

drivers/hwspinlock/qcom_hwspinlock.c

221

if (!bank)

drivers/hwspinlock/qcom_hwspinlock.c

224

platform_set_drvdata(pdev, bank);

drivers/hwspinlock/qcom_hwspinlock.c

231

bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev,

drivers/hwspinlock/qcom_hwspinlock.c

233

if (IS_ERR(bank->lock[i].priv))

drivers/hwspinlock/qcom_hwspinlock.c

234

return PTR_ERR(bank->lock[i].priv);

drivers/hwspinlock/qcom_hwspinlock.c

237

return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops,

drivers/hwspinlock/qcom_hwspinlock.c

75

dev_err(lock->bank->dev, "unable to query spinlock owner\n");

drivers/hwspinlock/qcom_hwspinlock.c

84

dev_err(lock->bank->dev, "failed to bust spinlock\n");

drivers/hwspinlock/sprd_hwspinlock.c

127

lock = &sprd_hwlock->bank.lock[i];

drivers/hwspinlock/sprd_hwspinlock.c

133

return devm_hwspin_lock_register(&pdev->dev, &sprd_hwlock->bank,

drivers/hwspinlock/sprd_hwspinlock.c

36

struct hwspinlock_device bank;

drivers/hwspinlock/sprd_hwspinlock.c

43

dev_get_drvdata(lock->bank->dev);

drivers/hwspinlock/sprd_hwspinlock.c

53

dev_warn(sprd_hwlock->bank.dev,

drivers/hwspinlock/sprd_hwspinlock.c

96

struct_size(sprd_hwlock, bank.lock, SPRD_HWLOCKS_NUM),

drivers/hwspinlock/stm32_hwspinlock.c

110

hw->bank.lock[i].priv = io_base + i * sizeof(u32);

drivers/hwspinlock/stm32_hwspinlock.c

112

ret = devm_hwspin_lock_register(dev, &hw->bank, &stm32_hwspinlock_ops,

drivers/hwspinlock/stm32_hwspinlock.c

25

struct hwspinlock_device bank;

drivers/hwspinlock/stm32_hwspinlock.c

82

hw = devm_kzalloc(dev, struct_size(hw, bank.lock, STM32_MUTEX_NUM_LOCKS), GFP_KERNEL);

drivers/hwspinlock/sun6i_hwspinlock.c

157

priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),

drivers/hwspinlock/sun6i_hwspinlock.c

159

if (!priv->bank) {

drivers/hwspinlock/sun6i_hwspinlock.c

165

hwlock = &priv->bank->lock[i];

drivers/hwspinlock/sun6i_hwspinlock.c

182

return devm_hwspin_lock_register(&pdev->dev, priv->bank, &sun6i_hwspinlock_ops,

drivers/hwspinlock/sun6i_hwspinlock.c

30

struct hwspinlock_device *bank;

drivers/hwspinlock/u8500_hsem.c

108

bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),

drivers/hwspinlock/u8500_hsem.c

110

if (!bank)

drivers/hwspinlock/u8500_hsem.c

113

platform_set_drvdata(pdev, bank);

drivers/hwspinlock/u8500_hsem.c

115

for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)

drivers/hwspinlock/u8500_hsem.c

118

return devm_hwspin_lock_register(&pdev->dev, bank,

drivers/hwspinlock/u8500_hsem.c

125

struct hwspinlock_device *bank = platform_get_drvdata(pdev);

drivers/hwspinlock/u8500_hsem.c

126

void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;

drivers/hwspinlock/u8500_hsem.c

88

struct hwspinlock_device *bank;

drivers/i2c/busses/i2c-amd-asf-plat.c

63

u8 bank, reg, cmd;

drivers/i2c/busses/i2c-amd-asf-plat.c

78

bank = (reg & BIT(3)) ? 1 : 0;

drivers/i2c/busses/i2c-amd-asf-plat.c

81

if (bank) {

drivers/i2c/busses/i2c-amd-asf-plat.c

97

if (bank) {

drivers/i2c/busses/i2c-npcm7xx.c

600

enum i2c_bank bank)

drivers/i2c/busses/i2c-npcm7xx.c

604

if (bank == I2C_BANK_0)

drivers/iio/gyro/mpu3050-core.c

773

u8 bank,

drivers/iio/gyro/mpu3050-core.c

782

bank);

drivers/infiniband/hw/hns/hns_roce_cq.c

100

struct hns_roce_bank *bank, struct ib_udata *udata)

drivers/infiniband/hw/hns/hns_roce_cq.c

109

return get_least_load_bankid_for_cq(bank);

drivers/infiniband/hw/hns/hns_roce_cq.c

116

struct hns_roce_bank *bank;

drivers/infiniband/hw/hns/hns_roce_cq.c

121

bankid = select_cq_bankid(hr_dev, cq_table->bank, udata);

drivers/infiniband/hw/hns/hns_roce_cq.c

122

bank = &cq_table->bank[bankid];

drivers/infiniband/hw/hns/hns_roce_cq.c

124

id = ida_alloc_range(&bank->ida, bank->min, bank->max, GFP_KERNEL);

drivers/infiniband/hw/hns/hns_roce_cq.c

132

bank->inuse++;

drivers/infiniband/hw/hns/hns_roce_cq.c

147

struct hns_roce_bank *bank;

drivers/infiniband/hw/hns/hns_roce_cq.c

149

bank = &cq_table->bank[get_cq_bankid(cqn)];

drivers/infiniband/hw/hns/hns_roce_cq.c

151

ida_free(&bank->ida, cqn >> CQ_BANKID_SHIFT);

drivers/infiniband/hw/hns/hns_roce_cq.c

154

bank->inuse--;

drivers/infiniband/hw/hns/hns_roce_cq.c

578

cq_table->bank[get_cq_bankid(i)].inuse++;

drivers/infiniband/hw/hns/hns_roce_cq.c

579

cq_table->bank[get_cq_bankid(i)].min++;

drivers/infiniband/hw/hns/hns_roce_cq.c

583

ida_init(&cq_table->bank[i].ida);

drivers/infiniband/hw/hns/hns_roce_cq.c

584

cq_table->bank[i].max = hr_dev->caps.num_cqs /

drivers/infiniband/hw/hns/hns_roce_cq.c

599

ida_destroy(&hr_dev->cq_table.bank[i].ida);

drivers/infiniband/hw/hns/hns_roce_cq.c

81

static u8 get_least_load_bankid_for_cq(struct hns_roce_bank *bank)

drivers/infiniband/hw/hns/hns_roce_cq.c

83

u32 least_load = bank[0].inuse;

drivers/infiniband/hw/hns/hns_roce_cq.c

89

bankcnt = bank[i].inuse;

drivers/infiniband/hw/hns/hns_roce_device.h

497

struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];

drivers/infiniband/hw/hns/hns_roce_device.h

505

struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];

drivers/infiniband/hw/hns/hns_roce_qp.c

1613

hr_dev->qp_table.bank[get_qp_bankid(i)].inuse++;

drivers/infiniband/hw/hns/hns_roce_qp.c

1614

hr_dev->qp_table.bank[get_qp_bankid(i)].min++;

drivers/infiniband/hw/hns/hns_roce_qp.c

1618

ida_init(&hr_dev->qp_table.bank[i].ida);

drivers/infiniband/hw/hns/hns_roce_qp.c

1619

hr_dev->qp_table.bank[i].max = hr_dev->caps.num_qps /

drivers/infiniband/hw/hns/hns_roce_qp.c

1621

hr_dev->qp_table.bank[i].next = hr_dev->qp_table.bank[i].min;

drivers/infiniband/hw/hns/hns_roce_qp.c

1632

ida_destroy(&hr_dev->qp_table.bank[i].ida);

drivers/infiniband/hw/hns/hns_roce_qp.c

200

static u8 get_least_load_bankid_for_qp(struct hns_roce_bank *bank, u8 valid_qp_bank_mask)

drivers/infiniband/hw/hns/hns_roce_qp.c

212

bankcnt = bank[i].inuse;

drivers/infiniband/hw/hns/hns_roce_qp.c

222

static int alloc_qpn_with_bankid(struct hns_roce_bank *bank, u8 bankid,

drivers/infiniband/hw/hns/hns_roce_qp.c

227

id = ida_alloc_range(&bank->ida, bank->next, bank->max, GFP_KERNEL);

drivers/infiniband/hw/hns/hns_roce_qp.c

229

id = ida_alloc_range(&bank->ida, bank->min, bank->max,

drivers/infiniband/hw/hns/hns_roce_qp.c

236

bank->next = (id + 1) > bank->max ? bank->min : id + 1;

drivers/infiniband/hw/hns/hns_roce_qp.c

255

struct hns_roce_bank *bank = qp_table->bank;

drivers/infiniband/hw/hns/hns_roce_qp.c

276

return get_least_load_bankid_for_qp(bank, valid_qp_bank_mask);

drivers/infiniband/hw/hns/hns_roce_qp.c

292

ret = alloc_qpn_with_bankid(&qp_table->bank[bankid], bankid,

drivers/infiniband/hw/hns/hns_roce_qp.c

301

qp_table->bank[bankid].inuse++;

drivers/infiniband/hw/hns/hns_roce_qp.c

464

ida_free(&hr_dev->qp_table.bank[bankid].ida,

drivers/infiniband/hw/hns/hns_roce_qp.c

468

hr_dev->qp_table.bank[bankid].inuse--;

drivers/input/keyboard/adp5588-keys.c

221

unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]);

drivers/input/keyboard/adp5588-keys.c

227

if (kpad->dir[bank] & bit)

drivers/input/keyboard/adp5588-keys.c

228

val = kpad->dat_out[bank];

drivers/input/keyboard/adp5588-keys.c

230

val = adp5588_read(kpad->client, GPIO_DAT_STAT1 + bank);

drivers/input/keyboard/adp5588-keys.c

239

unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]);

drivers/input/keyboard/adp5588-keys.c

245

kpad->dat_out[bank] |= bit;

drivers/input/keyboard/adp5588-keys.c

247

kpad->dat_out[bank] &= ~bit;

drivers/input/keyboard/adp5588-keys.c

249

return adp5588_write(kpad->client, GPIO_DAT_OUT1 + bank,

drivers/input/keyboard/adp5588-keys.c

250

kpad->dat_out[bank]);

drivers/input/keyboard/adp5588-keys.c

257

unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]);

drivers/input/keyboard/adp5588-keys.c

275

kpad->pull_dis[bank] |= bit;

drivers/input/keyboard/adp5588-keys.c

277

kpad->pull_dis[bank] &= bit;

drivers/input/keyboard/adp5588-keys.c

279

return adp5588_write(kpad->client, GPIO_PULL1 + bank,

drivers/input/keyboard/adp5588-keys.c

280

kpad->pull_dis[bank]);

drivers/input/keyboard/adp5588-keys.c

286

unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]);

drivers/input/keyboard/adp5588-keys.c

291

kpad->dir[bank] &= ~bit;

drivers/input/keyboard/adp5588-keys.c

292

return adp5588_write(kpad->client, GPIO_DIR1 + bank, kpad->dir[bank]);

drivers/input/keyboard/adp5588-keys.c

299

unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]);

drivers/input/keyboard/adp5588-keys.c

305

kpad->dir[bank] |= bit;

drivers/input/keyboard/adp5588-keys.c

308

kpad->dat_out[bank] |= bit;

drivers/input/keyboard/adp5588-keys.c

310

kpad->dat_out[bank] &= ~bit;

drivers/input/keyboard/adp5588-keys.c

312

error = adp5588_write(kpad->client, GPIO_DAT_OUT1 + bank,

drivers/input/keyboard/adp5588-keys.c

313

kpad->dat_out[bank]);

drivers/input/keyboard/adp5588-keys.c

317

error = adp5588_write(kpad->client, GPIO_DIR1 + bank, kpad->dir[bank]);

drivers/input/misc/pmic8xxx-pwrkey.c

163

u8 vref_sel, vlow_sel, band, vprog, bank;

drivers/input/misc/pmic8xxx-pwrkey.c

166

bank = PM8058_REGULATOR_BANK_SEL(7);

drivers/input/misc/pmic8xxx-pwrkey.c

167

error = regmap_write(regmap, test2_addr, bank);

drivers/input/misc/pmic8xxx-pwrkey.c

209

bank = PM8058_REGULATOR_BANK_SEL(1);

drivers/input/misc/pmic8xxx-pwrkey.c

210

error = regmap_write(regmap, test2_addr, bank);

drivers/input/misc/pmic8xxx-pwrkey.c

223

bank = PM8058_REGULATOR_BANK_SEL(7);

drivers/input/misc/pmic8xxx-pwrkey.c

224

error = regmap_write(regmap, test2_addr, bank);

drivers/iommu/amd/init.c

3918

static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,

drivers/iommu/amd/init.c

3932

offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);

drivers/iommu/amd/init.c

3956

int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)

drivers/iommu/amd/init.c

3961

return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);

drivers/iommu/amd/init.c

3964

int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)

drivers/iommu/amd/init.c

3969

return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);

drivers/iommu/mtk_iommu.c

1080

const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];

drivers/iommu/mtk_iommu.c

1081

const struct mtk_iommu_bank_data *bank0 = &data->bank[0];

drivers/iommu/mtk_iommu.c

1304

struct mtk_iommu_bank_data *bank;

drivers/iommu/mtk_iommu.c

1365

data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);

drivers/iommu/mtk_iommu.c

1366

if (!data->bank)

drivers/iommu/mtk_iommu.c

1372

bank = &data->bank[i];

drivers/iommu/mtk_iommu.c

1373

bank->id = i;

drivers/iommu/mtk_iommu.c

1374

bank->base = base + i * MTK_IOMMU_BANK_SZ;

drivers/iommu/mtk_iommu.c

1375

bank->m4u_dom = NULL;

drivers/iommu/mtk_iommu.c

1377

bank->irq = platform_get_irq(pdev, i);

drivers/iommu/mtk_iommu.c

1378

if (bank->irq < 0)

drivers/iommu/mtk_iommu.c

1379

return bank->irq;

drivers/iommu/mtk_iommu.c

1380

bank->parent_dev = dev;

drivers/iommu/mtk_iommu.c

1381

bank->parent_data = data;

drivers/iommu/mtk_iommu.c

1382

spin_lock_init(&bank->tlb_lock);

drivers/iommu/mtk_iommu.c

1465

struct mtk_iommu_bank_data *bank;

drivers/iommu/mtk_iommu.c

1482

bank = &data->bank[i];

drivers/iommu/mtk_iommu.c

1483

if (!bank->m4u_dom)

drivers/iommu/mtk_iommu.c

1485

devm_free_irq(&pdev->dev, bank->irq, bank);

drivers/iommu/mtk_iommu.c

1496

base = data->bank[i].base;

drivers/iommu/mtk_iommu.c

1505

base = data->bank[i].base;

drivers/iommu/mtk_iommu.c

1535

base = data->bank[i].base;

drivers/iommu/mtk_iommu.c

1542

m4u_dom = data->bank[i].m4u_dom;

drivers/iommu/mtk_iommu.c

1545

base = data->bank[i].base;

drivers/iommu/mtk_iommu.c

268

struct mtk_iommu_bank_data *bank;

drivers/iommu/mtk_iommu.c

288

struct mtk_iommu_bank_data *bank;

drivers/iommu/mtk_iommu.c

393

struct mtk_iommu_bank_data *bank = &data->bank[0];

drivers/iommu/mtk_iommu.c

394

void __iomem *base = bank->base;

drivers/iommu/mtk_iommu.c

397

spin_lock_irqsave(&bank->tlb_lock, flags);

drivers/iommu/mtk_iommu.c

401

spin_unlock_irqrestore(&bank->tlb_lock, flags);

drivers/iommu/mtk_iommu.c

405

struct mtk_iommu_bank_data *bank)

drivers/iommu/mtk_iommu.c

407

struct list_head *head = bank->parent_data->hw_list;

drivers/iommu/mtk_iommu.c

439

curbank = &data->bank[bank->id];

drivers/iommu/mtk_iommu.c

472

struct mtk_iommu_bank_data *bank = dev_id;

drivers/iommu/mtk_iommu.c

473

struct mtk_iommu_data *data = bank->parent_data;

drivers/iommu/mtk_iommu.c

474

struct mtk_iommu_domain *dom = bank->m4u_dom;

drivers/iommu/mtk_iommu.c

478

void __iomem *base = bank->base;

drivers/iommu/mtk_iommu.c

522

if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,

drivers/iommu/mtk_iommu.c

525

bank->parent_dev,

drivers/iommu/mtk_iommu.c

617

larb_mmu->bank[portid] = upper_32_bits(region->iova_base);

drivers/iommu/mtk_iommu.c

728

struct mtk_iommu_bank_data *bank;

drivers/iommu/mtk_iommu.c

738

if (!dom->bank) {

drivers/iommu/mtk_iommu.c

749

dom->bank = &data->bank[bankid];

drivers/iommu/mtk_iommu.c

754

bank = &data->bank[bankid];

drivers/iommu/mtk_iommu.c

755

if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */

drivers/iommu/mtk_iommu.c

767

bank->m4u_dom = dom;

drivers/iommu/mtk_iommu.c

768

writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);

drivers/iommu/mtk_iommu.c

818

if (dom->bank->parent_data->enable_4GB)

drivers/iommu/mtk_iommu.c

839

if (dom->bank)

drivers/iommu/mtk_iommu.c

840

mtk_iommu_tlb_flush_all(dom->bank->parent_data);

drivers/iommu/mtk_iommu.c

849

mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);

drivers/iommu/mtk_iommu.c

857

mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);

drivers/iommu/mtk_iommu.c

869

dom->bank->parent_data->enable_4GB &&

drivers/irqchip/irq-bcm2835.c

213

static u32 armctrl_translate_bank(int bank)

drivers/irqchip/irq-bcm2835.c

215

u32 stat = readl_relaxed(intc.pending[bank]);

drivers/irqchip/irq-bcm2835.c

217

return MAKE_HWIRQ(bank, ffs(stat) - 1);

drivers/irqchip/irq-bcm2835.c

220

static u32 armctrl_translate_shortcut(int bank, u32 stat)

drivers/irqchip/irq-bcm2835.c

222

return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);

drivers/irqchip/irq-stm32mp-exti.c

268

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

272

chip_data->rtsr_cache = readl_relaxed(base + bank->rtsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

273

chip_data->ftsr_cache = readl_relaxed(base + bank->ftsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

275

writel_relaxed(wake_active, base + bank->imr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

280

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

284

writel_relaxed(chip_data->rtsr_cache, base + bank->rtsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

285

writel_relaxed(chip_data->ftsr_cache, base + bank->ftsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

287

writel_relaxed(mask_cache, base + bank->imr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

329

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

333

stm32mp_exti_write_bit(d, bank->rpr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

334

stm32mp_exti_write_bit(d, bank->fpr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

345

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

348

chip_data->mask_cache = stm32mp_exti_clr_bit(d, bank->imr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

358

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

361

chip_data->mask_cache = stm32mp_exti_set_bit(d, bank->imr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

371

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

387

rtsr = readl_relaxed(base + bank->rtsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

388

ftsr = readl_relaxed(base + bank->ftsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

392

writel_relaxed(rtsr, base + bank->rtsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

393

writel_relaxed(ftsr, base + bank->ftsr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

459

const struct stm32mp_exti_bank *bank = chip_data->reg_bank;

drivers/irqchip/irq-stm32mp-exti.c

463

writel_relaxed(mask, base + bank->swier_ofst);

drivers/irqchip/irq-stm32mp-exti.c

505

int bank;

drivers/irqchip/irq-stm32mp-exti.c

511

bank = hwirq / IRQS_PER_BANK;

drivers/irqchip/irq-stm32mp-exti.c

512

chip_data = &host_data->chips_data[bank];

drivers/irqchip/irq-stm32mp-exti.c

564

const struct stm32mp_exti_bank *bank;

drivers/irqchip/irq-stm32mp-exti.c

567

bank = h_data->drv_data->exti_banks[bank_idx];

drivers/irqchip/irq-stm32mp-exti.c

570

chip_data->reg_bank = bank;

drivers/irqchip/irq-stm32mp-exti.c

578

writel_relaxed(0, base + bank->imr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

581

chip_data->event_reserved = readl_relaxed(base + bank->seccfgr_ofst);

drivers/irqchip/irq-stm32mp-exti.c

596

unsigned int bank, i, event;

drivers/irqchip/irq-stm32mp-exti.c

604

for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) {

drivers/irqchip/irq-stm32mp-exti.c

606

event = bank * IRQS_PER_BANK + i;

drivers/irqchip/irq-stm32mp-exti.c

610

host_data->chips_data[bank].event_reserved |= BIT(i);

drivers/irqchip/qcom-pdc.c

72

static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)

drivers/irqchip/qcom-pdc.c

77

switch (bank) {

drivers/irqchip/qcom-pdc.c

81

bank += 3;

drivers/irqchip/qcom-pdc.c

86

bank -= 2;

drivers/irqchip/qcom-pdc.c

97

pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable);

drivers/leds/leds-mc13783.c

59

unsigned int reg, bank, off, shift;

drivers/leds/leds-mc13783.c

78

bank = off / 3;

drivers/leds/leds-mc13783.c

79

reg = 3 + bank;

drivers/leds/leds-mc13783.c

80

shift = (off - bank * 3) * 5 + 6;

drivers/leds/leds-mc13783.c

93

bank = off / 2;

drivers/leds/leds-mc13783.c

94

reg = 2 + bank;

drivers/leds/leds-mc13783.c

95

shift = (off - bank * 2) * 12 + 3;

drivers/leds/leds-tca6507.c

164

} bank[3];

drivers/leds/leds-tca6507.c

175

int bank; /* Bank used, or -1 */

drivers/leds/leds-tca6507.c

278

static void set_code(struct tca6507_chip *tca, int reg, int bank, int new)

drivers/leds/leds-tca6507.c

282

if (bank) {

drivers/leds/leds-tca6507.c

295

static void set_level(struct tca6507_chip *tca, int bank, int level)

drivers/leds/leds-tca6507.c

297

switch (bank) {

drivers/leds/leds-tca6507.c

300

set_code(tca, TCA6507_MAX_INTENSITY, bank, level);

drivers/leds/leds-tca6507.c

306

tca->bank[bank].level = level;

drivers/leds/leds-tca6507.c

310

static void set_times(struct tca6507_chip *tca, int bank)

drivers/leds/leds-tca6507.c

315

result = choose_times(tca->bank[bank].ontime, &c1, &c2);

drivers/leds/leds-tca6507.c

321

c2, time_codes[c2], tca->bank[bank].ontime);

drivers/leds/leds-tca6507.c

322

set_code(tca, TCA6507_FADE_ON, bank, c2);

drivers/leds/leds-tca6507.c

323

set_code(tca, TCA6507_FULL_ON, bank, c1);

drivers/leds/leds-tca6507.c

324

tca->bank[bank].ontime = result;

drivers/leds/leds-tca6507.c

326

result = choose_times(tca->bank[bank].offtime, &c1, &c2);

drivers/leds/leds-tca6507.c

330

c2, time_codes[c2], tca->bank[bank].offtime);

drivers/leds/leds-tca6507.c

331

set_code(tca, TCA6507_FADE_OFF, bank, c2);

drivers/leds/leds-tca6507.c

332

set_code(tca, TCA6507_FIRST_OFF, bank, c1);

drivers/leds/leds-tca6507.c

333

set_code(tca, TCA6507_SECOND_OFF, bank, c1);

drivers/leds/leds-tca6507.c

334

tca->bank[bank].offtime = result;

drivers/leds/leds-tca6507.c

336

set_code(tca, TCA6507_INITIALIZE, bank, INIT_CODE);

drivers/leds/leds-tca6507.c

365

if (led->bank >= 0) {

drivers/leds/leds-tca6507.c

366

struct bank *b = tca->bank + led->bank;

drivers/leds/leds-tca6507.c

372

led->bank = -1;

drivers/leds/leds-tca6507.c

383

struct bank *b;

drivers/leds/leds-tca6507.c

409

if (tca->bank[i].level == level ||

drivers/leds/leds-tca6507.c

410

tca->bank[i].level_use == 0) {

drivers/leds/leds-tca6507.c

414

d = abs(level - tca->bank[i].level);

drivers/leds/leds-tca6507.c

427

if (!tca->bank[best].level_use)

drivers/leds/leds-tca6507.c

430

tca->bank[best].level_use++;

drivers/leds/leds-tca6507.c

431

led->bank = best;

drivers/leds/leds-tca6507.c

433

led->led_cdev.brightness = TO_BRIGHT(tca->bank[best].level);

drivers/leds/leds-tca6507.c

448

if (tca->bank[i].level_use == 0)

drivers/leds/leds-tca6507.c

451

if (tca->bank[i].level != level)

drivers/leds/leds-tca6507.c

458

if (tca->bank[i].time_use == 0)

drivers/leds/leds-tca6507.c

462

if (!(tca->bank[i].on_dflt ||

drivers/leds/leds-tca6507.c

464

tca->bank[i].ontime == led->ontime))

drivers/leds/leds-tca6507.c

468

if (!(tca->bank[i].off_dflt ||

drivers/leds/leds-tca6507.c

470

tca->bank[i].offtime == led->offtime))

drivers/leds/leds-tca6507.c

482

b = &tca->bank[i];

drivers/leds/leds-tca6507.c

486

led->bank = i;

drivers/leds/leds-tca6507.c

753

l->bank = -1;

drivers/media/common/b2c2/flexcop-sram.c

101

static void flex_sram_read(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)

drivers/media/common/b2c2/flexcop-sram.c

107

command = bank | addr | 0x04008000;

drivers/media/common/b2c2/flexcop-sram.c

142

u32 bank;

drivers/media/common/b2c2/flexcop-sram.c

144

bank = 0;

drivers/media/common/b2c2/flexcop-sram.c

147

bank = (addr & 0x18000) << 0x0d;

drivers/media/common/b2c2/flexcop-sram.c

152

bank = 0x20000000;

drivers/media/common/b2c2/flexcop-sram.c

154

bank = 0x10000000;

drivers/media/common/b2c2/flexcop-sram.c

156

flex_sram_write(adapter, bank, addr & 0x7fff, buf, len);

drivers/media/common/b2c2/flexcop-sram.c

161

u32 bank;

drivers/media/common/b2c2/flexcop-sram.c

162

bank = 0;

drivers/media/common/b2c2/flexcop-sram.c

165

bank = (addr & 0x18000) << 0x0d;

drivers/media/common/b2c2/flexcop-sram.c

170

bank = 0x20000000;

drivers/media/common/b2c2/flexcop-sram.c

172

bank = 0x10000000;

drivers/media/common/b2c2/flexcop-sram.c

174

flex_sram_read(adapter, bank, addr & 0x7fff, buf, len);

drivers/media/common/b2c2/flexcop-sram.c

76

static void flexcop_sram_write(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)

drivers/media/common/b2c2/flexcop-sram.c

82

command = bank | addr | 0x04000000 | (*buf << 0x10);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

1859

0x00, tnr_dmd->cfg_mem[i].bank);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

1877

u8 bank, u8 address, u8 value, u8 bit_mask)

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

1888

tnr_dmd->cfg_mem[i].bank == bank &&

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

1904

tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].bank = bank;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

3248

u8 bank, u8 address,

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

3260

ret = tnr_dmd->io->write_reg(tnr_dmd->io, tgt, 0x00, bank);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c

3269

return set_cfg_mem(tnr_dmd, tgt, bank, address, value, bit_mask);

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.h

154

u8 bank;

drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.h

319

u8 bank, u8 address,

drivers/media/i2c/max2175.c

428

u8 bank, const u16 *coeffs)

drivers/media/i2c/max2175.c

433

mxm_dbg(ctx, "set_filter_coeffs: m_sel %d bank %d\n", m_sel, bank);

drivers/media/i2c/max2175.c

440

coeff_addr = i + bank * 24;

drivers/media/i2c/rj54n1cb0c.c

166

u8 bank;

drivers/media/i2c/rj54n1cb0c.c

436

if (rj54n1->bank != reg >> 8) {

drivers/media/i2c/rj54n1cb0c.c

441

rj54n1->bank = reg >> 8;

drivers/media/i2c/rj54n1cb0c.c

453

if (rj54n1->bank != reg >> 8) {

drivers/media/i2c/rj54n1cb0c.c

458

rj54n1->bank = reg >> 8;

drivers/media/rc/winbond-cir.c

242

wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)

drivers/media/rc/winbond-cir.c

244

outb(bank, data->sbase + WBCIR_REG_SP3_BSR);

drivers/memory/jz4780-nemc.c

104

nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));

drivers/memory/jz4780-nemc.c

107

nfcsr &= ~NEMC_NFCSR_TNFEn(bank);

drivers/memory/jz4780-nemc.c

108

nfcsr |= NEMC_NFCSR_NFEn(bank);

drivers/memory/jz4780-nemc.c

125

void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)

drivers/memory/jz4780-nemc.c

133

nfcsr |= NEMC_NFCSR_NFCEn(bank);

drivers/memory/jz4780-nemc.c

135

nfcsr &= ~NEMC_NFCSR_NFCEn(bank);

drivers/memory/jz4780-nemc.c

159

unsigned int bank,

drivers/memory/jz4780-nemc.c

187

smcr = readl(nemc->base + NEMC_SMCRn(bank));

drivers/memory/jz4780-nemc.c

266

writel(smcr, nemc->base + NEMC_SMCRn(bank));

drivers/memory/jz4780-nemc.c

277

unsigned int bank;

drivers/memory/jz4780-nemc.c

344

bank = of_read_number(prop, 1);

drivers/memory/jz4780-nemc.c

345

if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {

drivers/memory/jz4780-nemc.c

348

child, bank);

drivers/memory/jz4780-nemc.c

355

referenced |= BIT(bank);

drivers/memory/jz4780-nemc.c

369

for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {

drivers/memory/jz4780-nemc.c

370

if (!jz4780_nemc_configure_bank(nemc, bank, child)) {

drivers/memory/jz4780-nemc.c

71

unsigned int bank, count = 0;

drivers/memory/jz4780-nemc.c

76

bank = of_read_number(prop, 1);

drivers/memory/jz4780-nemc.c

77

if (!(referenced & BIT(bank))) {

drivers/memory/jz4780-nemc.c

78

referenced |= BIT(bank);

drivers/memory/jz4780-nemc.c

93

void jz4780_nemc_set_type(struct device *dev, unsigned int bank,

drivers/memory/mtk-smi.c

159

unsigned char *bank;

drivers/memory/mtk-smi.c

173

larb->bank = larb_mmu[i].bank;

drivers/memory/mtk-smi.c

280

reg |= BANK_SEL(larb->bank[i]);

drivers/memory/samsung/exynos-srom.c

100

srom->reg_base + EXYNOS_SROM_BC0 + bank);

drivers/memory/samsung/exynos-srom.c

70

u32 bank, width, pmc = 0;

drivers/memory/samsung/exynos-srom.c

74

if (of_property_read_u32(np, "reg", &bank))

drivers/memory/samsung/exynos-srom.c

84

bank *= 4; /* Convert bank into shift/offset */

drivers/memory/samsung/exynos-srom.c

91

bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);

drivers/memory/stm32-fmc2-ebi.c

1577

u32 bank;

drivers/memory/stm32-fmc2-ebi.c

1581

ret = of_property_read_u32(child, "reg", &bank);

drivers/memory/stm32-fmc2-ebi.c

1585

if (bank >= FMC2_MAX_BANKS) {

drivers/memory/stm32-fmc2-ebi.c

1586

dev_err(dev, "invalid reg value: %d\n", bank);

drivers/memory/stm32-fmc2-ebi.c

1590

if (ebi->bank_assigned & BIT(bank)) {

drivers/memory/stm32-fmc2-ebi.c

1591

dev_err(dev, "bank already assigned: %d\n", bank);

drivers/memory/stm32-fmc2-ebi.c

1596

ret = ebi->data->check_rif(ebi, bank + 1);

drivers/memory/stm32-fmc2-ebi.c

1598

dev_err(dev, "bank access failed: %d\n", bank);

drivers/memory/stm32-fmc2-ebi.c

1603

if (bank < FMC2_MAX_EBI_CE) {

drivers/memory/stm32-fmc2-ebi.c

1604

ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);

drivers/memory/stm32-fmc2-ebi.c

1607

"setup chip select %d failed\n", bank);

drivers/memory/stm32-fmc2-ebi.c

1610

ebi->bank_assigned |= BIT(bank);

drivers/memory/tegra/tegra210-emc-cc-r21021.c

848

if (emc->num_channels < 2 && burst[i].bank >= 1)

drivers/memory/tegra/tegra210-emc-cc-r21021.c

853

emc_channel_writel(emc, burst[i].bank,

drivers/memory/tegra/tegra210-emc-cc-r21021.c

868

if (emc->num_channels < 2 && vref[i].bank >= 1)

drivers/memory/tegra/tegra210-emc-cc-r21021.c

873

emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i],

drivers/memory/tegra/tegra210-emc-cc-r21021.c

921

if (emc->num_channels < 2 && trim[i].bank >= 1)

drivers/memory/tegra/tegra210-emc-cc-r21021.c

942

emc_channel_writel(emc, trim[i].bank, value, offset);

drivers/memory/tegra/tegra210-emc-cc-r21021.c

946

emc_channel_writel(emc, trim[i].bank,

drivers/memory/tegra/tegra210-emc-core.c

521

{ .bank = 0, .offset = EMC_MRW10, },

drivers/memory/tegra/tegra210-emc-core.c

522

{ .bank = 1, .offset = EMC_MRW10, },

drivers/memory/tegra/tegra210-emc-core.c

523

{ .bank = 0, .offset = EMC_MRW11, },

drivers/memory/tegra/tegra210-emc-core.c

524

{ .bank = 1, .offset = EMC_MRW11, },

drivers/memory/tegra/tegra210-emc-core.c

525

{ .bank = 0, .offset = EMC_MRW12, },

drivers/memory/tegra/tegra210-emc-core.c

526

{ .bank = 1, .offset = EMC_MRW12, },

drivers/memory/tegra/tegra210-emc-core.c

527

{ .bank = 0, .offset = EMC_MRW13, },

drivers/memory/tegra/tegra210-emc-core.c

528

{ .bank = 1, .offset = EMC_MRW13, },

drivers/memory/tegra/tegra210-emc-core.c

531

{ .bank = 0, .offset = EMC_CMD_BRLSHFT_0, },

drivers/memory/tegra/tegra210-emc-core.c

532

{ .bank = 1, .offset = EMC_CMD_BRLSHFT_1, },

drivers/memory/tegra/tegra210-emc-core.c

533

{ .bank = 0, .offset = EMC_DATA_BRLSHFT_0, },

drivers/memory/tegra/tegra210-emc-core.c

534

{ .bank = 1, .offset = EMC_DATA_BRLSHFT_0, },

drivers/memory/tegra/tegra210-emc-core.c

535

{ .bank = 0, .offset = EMC_DATA_BRLSHFT_1, },

drivers/memory/tegra/tegra210-emc-core.c

536

{ .bank = 1, .offset = EMC_DATA_BRLSHFT_1, },

drivers/memory/tegra/tegra210-emc-core.c

537

{ .bank = 0, .offset = EMC_QUSE_BRLSHFT_0, },

drivers/memory/tegra/tegra210-emc-core.c

538

{ .bank = 1, .offset = EMC_QUSE_BRLSHFT_1, },

drivers/memory/tegra/tegra210-emc-core.c

539

{ .bank = 0, .offset = EMC_QUSE_BRLSHFT_2, },

drivers/memory/tegra/tegra210-emc-core.c

540

{ .bank = 1, .offset = EMC_QUSE_BRLSHFT_3, },

drivers/memory/tegra/tegra210-emc-core.c

544

.bank = 0,

drivers/memory/tegra/tegra210-emc-core.c

547

.bank = 1,

drivers/memory/tegra/tegra210-emc-core.c

550

.bank = 0,

drivers/memory/tegra/tegra210-emc-core.c

553

.bank = 1,

drivers/memory/tegra/tegra210-emc.h

788

u16 bank;

drivers/mfd/ab8500-core.c

202

static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,

drivers/mfd/ab8500-core.c

210

u16 addr = ((u16)bank) << 8 | reg;

drivers/mfd/ab8500-core.c

225

static int ab8500_set_register(struct device *dev, u8 bank,

drivers/mfd/ab8500-core.c

232

ret = set_register_interruptible(ab8500, bank, reg, value);

drivers/mfd/ab8500-core.c

237

static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,

drivers/mfd/ab8500-core.c

241

u16 addr = ((u16)bank) << 8 | reg;

drivers/mfd/ab8500-core.c

258

static int ab8500_get_register(struct device *dev, u8 bank,

drivers/mfd/ab8500-core.c

265

ret = get_register_interruptible(ab8500, bank, reg, value);

drivers/mfd/ab8500-core.c

270

static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,

drivers/mfd/ab8500-core.c

274

u16 addr = ((u16)bank) << 8 | reg;

drivers/mfd/ab8500-core.c

310

u8 bank, u8 reg, u8 bitmask, u8 bitvalues)

drivers/mfd/ab8500-core.c

316

ret = mask_and_set_register_interruptible(ab8500, bank, reg,

drivers/mfd/ab8500-sysctrl.c

101

u8 bank;

drivers/mfd/ab8500-sysctrl.c

106

bank = (reg >> 8);

drivers/mfd/ab8500-sysctrl.c

107

if (!valid_bank(bank))

drivers/mfd/ab8500-sysctrl.c

110

return abx500_get_register_interruptible(sysctrl_dev, bank,

drivers/mfd/ab8500-sysctrl.c

117

u8 bank;

drivers/mfd/ab8500-sysctrl.c

122

bank = (reg >> 8);

drivers/mfd/ab8500-sysctrl.c

123

if (!valid_bank(bank)) {

drivers/mfd/ab8500-sysctrl.c

128

return abx500_mask_and_set_register_interruptible(sysctrl_dev, bank,

drivers/mfd/ab8500-sysctrl.c

93

static inline bool valid_bank(u8 bank)

drivers/mfd/ab8500-sysctrl.c

95

return ((bank == AB8500_SYS_CTRL1_BLOCK) ||

drivers/mfd/ab8500-sysctrl.c

96

(bank == AB8500_SYS_CTRL2_BLOCK));

drivers/mfd/abx500-core.c

102

int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,

drivers/mfd/abx500-core.c

109

return ops->mask_and_set_register(dev, bank,

drivers/mfd/abx500-core.c

62

int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,

drivers/mfd/abx500-core.c

69

return ops->set_register(dev, bank, reg, value);

drivers/mfd/abx500-core.c

75

int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,

drivers/mfd/abx500-core.c

82

return ops->get_register(dev, bank, reg, value);

drivers/mfd/abx500-core.c

88

int abx500_get_register_page_interruptible(struct device *dev, u8 bank,

drivers/mfd/abx500-core.c

95

return ops->get_register_page(dev, bank,

drivers/mfd/ezx-pcap.c

21

u8 bank;

drivers/mfd/ezx-pcap.c

251

if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)

drivers/mfd/ezx-pcap.c

298

int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],

drivers/mfd/ezx-pcap.c

309

req->bank = bank;

drivers/mfd/mt6360-core.c

404

u8 bank = *(u8 *)reg;

drivers/mfd/mt6360-core.c

413

if (bank >= MT6360_SLAVE_MAX)

drivers/mfd/mt6360-core.c

416

i2c = ddata->i2c[bank];

drivers/mfd/mt6360-core.c

418

if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {

drivers/mfd/mt6360-core.c

454

u8 bank = *(u8 *)val;

drivers/mfd/mt6360-core.c

463

if (bank >= MT6360_SLAVE_MAX)

drivers/mfd/mt6360-core.c

466

i2c = ddata->i2c[bank];

drivers/mfd/mt6360-core.c

468

if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {

drivers/mfd/stmpe.c

1108

int bank = num - i - 1;

drivers/mfd/stmpe.c

1112

status &= stmpe->ier[bank];

drivers/mfd/stmpe.c

1119

int line = bank * 8 + bit;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

283

unsigned int bank = gpio / 32;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

286

priv->gpio_wake_mask[bank] |= (1 << bitpos);

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

288

priv->gpio_wake_mask[bank] &= ~(1 << bitpos);

drivers/mtd/chips/jedec_probe.c

1916

int bank = 0;

drivers/mtd/chips/jedec_probe.c

1923

uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi);

drivers/mtd/chips/jedec_probe.c

1928

bank++;

drivers/mtd/devices/spear_smi.c

196

u32 bank;

drivers/mtd/devices/spear_smi.c

221

static int spear_smi_read_sr(struct spear_smi *dev, u32 bank)

drivers/mtd/devices/spear_smi.c

234

writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,

drivers/mtd/devices/spear_smi.c

264

static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank,

drivers/mtd/devices/spear_smi.c

272

status = spear_smi_read_sr(dev, bank);

drivers/mtd/devices/spear_smi.c

379

static int spear_smi_write_enable(struct spear_smi *dev, u32 bank)

drivers/mtd/devices/spear_smi.c

392

writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);

drivers/mtd/devices/spear_smi.c

407

if (dev->status & (1 << (bank + WM_SHIFT)))

drivers/mtd/devices/spear_smi.c

445

u32 bank, u32 command, u32 bytes)

drivers/mtd/devices/spear_smi.c

450

ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);

drivers/mtd/devices/spear_smi.c

454

ret = spear_smi_write_enable(dev, bank);

drivers/mtd/devices/spear_smi.c

466

writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),

drivers/mtd/devices/spear_smi.c

498

u32 addr, command, bank;

drivers/mtd/devices/spear_smi.c

504

bank = flash->bank;

drivers/mtd/devices/spear_smi.c

505

if (bank > dev->num_flashes - 1) {

drivers/mtd/devices/spear_smi.c

519

ret = spear_smi_erase_sector(dev, bank, command, 4);

drivers/mtd/devices/spear_smi.c

557

if (flash->bank > dev->num_flashes - 1) {

drivers/mtd/devices/spear_smi.c

568

ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT);

drivers/mtd/devices/spear_smi.c

615

static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,

drivers/mtd/devices/spear_smi.c

622

ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);

drivers/mtd/devices/spear_smi.c

627

ret = spear_smi_write_enable(dev, bank);

drivers/mtd/devices/spear_smi.c

686

if (flash->bank > dev->num_flashes - 1) {

drivers/mtd/devices/spear_smi.c

699

ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len);

drivers/mtd/devices/spear_smi.c

708

ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf,

drivers/mtd/devices/spear_smi.c

721

ret = spear_smi_cpy_toio(dev, flash->bank, dest + i,

drivers/mtd/devices/spear_smi.c

745

static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank)

drivers/mtd/devices/spear_smi.c

750

ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT);

drivers/mtd/devices/spear_smi.c

764

val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) |

drivers/mtd/devices/spear_smi.c

842

u32 bank, struct device_node *np)

drivers/mtd/devices/spear_smi.c

854

if (bank > pdata->num_flashes - 1)

drivers/mtd/devices/spear_smi.c

857

flash_info = &pdata->board_flash_info[bank];

drivers/mtd/devices/spear_smi.c

864

flash->bank = bank;

drivers/mtd/devices/spear_smi.c

869

flash_index = spear_smi_probe_flash(dev, bank);

drivers/mtd/devices/spear_smi.c

871

dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank);

drivers/mtd/devices/spear_smi.c

880

dev->flash[bank] = flash;

drivers/mtd/nand/raw/cadence-nand-controller.c

448

u16 bank;

drivers/mtd/nand/raw/cadence-nand-controller.c

979

cdma_desc->bank = nf_mem;

drivers/mtd/nand/raw/denali.c

108

int bank, u32 irq_status)

drivers/mtd/nand/raw/denali.c

111

iowrite32(irq_status, denali->reg + INTR_STATUS(bank));

drivers/mtd/nand/raw/denali.c

1191

unsigned int bank = dchip->sels[i].bank;

drivers/mtd/nand/raw/denali.c

1193

if (bank >= denali->nbanks) {

drivers/mtd/nand/raw/denali.c

1194

dev_err(denali->dev, "unsupported bank %d\n", bank);

drivers/mtd/nand/raw/denali.c

1199

if (bank == dchip->sels[j].bank) {

drivers/mtd/nand/raw/denali.c

1202

bank);

drivers/mtd/nand/raw/denali.c

1209

if (bank == dchip2->sels[j].bank) {

drivers/mtd/nand/raw/denali.c

1212

bank);

drivers/mtd/nand/raw/denali.c

198

denali->active_bank = sel->bank;

drivers/mtd/nand/raw/denali.c

443

int bank = denali->active_bank;

drivers/mtd/nand/raw/denali.c

447

ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));

drivers/mtd/nand/raw/denali.c

448

ecc_cor >>= ECC_COR_INFO__SHIFT(bank);

drivers/mtd/nand/raw/denali.h

18

#define DEVICE_RESET__BANK(bank) BIT(bank)

drivers/mtd/nand/raw/denali.h

208

#define INTR_STATUS(bank) (0x410 + (bank) * 0x50)

drivers/mtd/nand/raw/denali.h

209

#define INTR_EN(bank) (0x420 + (bank) * 0x50)

drivers/mtd/nand/raw/denali.h

230

#define PAGE_CNT(bank) (0x430 + (bank) * 0x50)

drivers/mtd/nand/raw/denali.h

231

#define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)

drivers/mtd/nand/raw/denali.h

232

#define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)

drivers/mtd/nand/raw/denali.h

254

#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)

drivers/mtd/nand/raw/denali.h

255

#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)

drivers/mtd/nand/raw/denali.h

308

int bank;

drivers/mtd/nand/raw/denali.h

36

#define RB_PIN_ENABLED__BANK(bank) BIT(bank)

drivers/mtd/nand/raw/denali_dt.c

100

ret = of_property_read_u32_index(chip_np, "reg", i, &bank);

drivers/mtd/nand/raw/denali_dt.c

104

dchip->sels[i].bank = bank;

drivers/mtd/nand/raw/denali_dt.c

85

u32 bank;

drivers/mtd/nand/raw/denali_pci.c

107

dchip->sels[i].bank = i;

drivers/mtd/nand/raw/fsl_elbc_nand.c

222

in_be32(&lbc->fbcr), priv->bank);

drivers/mtd/nand/raw/fsl_elbc_nand.c

226

out_be32(&lbc->lsor, priv->bank);

drivers/mtd/nand/raw/fsl_elbc_nand.c

41

int bank; /* Chip select bank number */

drivers/mtd/nand/raw/fsl_elbc_nand.c

687

dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);

drivers/mtd/nand/raw/fsl_elbc_nand.c

695

if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)

drivers/mtd/nand/raw/fsl_elbc_nand.c

736

if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==

drivers/mtd/nand/raw/fsl_elbc_nand.c

769

br = in_be32(&lbc->bank[priv->bank].br) & ~BR_DECC;

drivers/mtd/nand/raw/fsl_elbc_nand.c

771

out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_CHK_GEN);

drivers/mtd/nand/raw/fsl_elbc_nand.c

773

out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_OFF);

drivers/mtd/nand/raw/fsl_elbc_nand.c

822

clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);

drivers/mtd/nand/raw/fsl_elbc_nand.c

825

setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);

drivers/mtd/nand/raw/fsl_elbc_nand.c

850

elbc_fcm_ctrl->chips[priv->bank] = NULL;

drivers/mtd/nand/raw/fsl_elbc_nand.c

866

int bank;

drivers/mtd/nand/raw/fsl_elbc_nand.c

885

for (bank = 0; bank < MAX_BANKS; bank++)

drivers/mtd/nand/raw/fsl_elbc_nand.c

886

if ((in_be32(&lbc->bank[bank].br) & BR_V) &&

drivers/mtd/nand/raw/fsl_elbc_nand.c

887

(in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&

drivers/mtd/nand/raw/fsl_elbc_nand.c

888

(in_be32(&lbc->bank[bank].br) &

drivers/mtd/nand/raw/fsl_elbc_nand.c

889

in_be32(&lbc->bank[bank].or) & BR_BA)

drivers/mtd/nand/raw/fsl_elbc_nand.c

893

if (bank >= MAX_BANKS) {

drivers/mtd/nand/raw/fsl_elbc_nand.c

919

elbc_fcm_ctrl->chips[bank] = priv;

drivers/mtd/nand/raw/fsl_elbc_nand.c

920

priv->bank = bank;

drivers/mtd/nand/raw/fsl_elbc_nand.c

955

(unsigned long long)res.start, priv->bank);

drivers/mtd/nand/raw/fsl_ifc_nand.c

1004

for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {

drivers/mtd/nand/raw/fsl_ifc_nand.c

1005

if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))

drivers/mtd/nand/raw/fsl_ifc_nand.c

1009

if (bank >= fsl_ifc_ctrl_dev->banks) {

drivers/mtd/nand/raw/fsl_ifc_nand.c

1038

ifc_nand_ctrl->chips[bank] = priv;

drivers/mtd/nand/raw/fsl_ifc_nand.c

1039

priv->bank = bank;

drivers/mtd/nand/raw/fsl_ifc_nand.c

1086

(unsigned long long)res.start, priv->bank);

drivers/mtd/nand/raw/fsl_ifc_nand.c

183

ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,

drivers/mtd/nand/raw/fsl_ifc_nand.c

35

int bank; /* Chip select bank number */

drivers/mtd/nand/raw/fsl_ifc_nand.c

714

csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);

drivers/mtd/nand/raw/fsl_ifc_nand.c

783

uint32_t cs = priv->bank;

drivers/mtd/nand/raw/fsl_ifc_nand.c

870

if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))

drivers/mtd/nand/raw/fsl_ifc_nand.c

893

if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)

drivers/mtd/nand/raw/fsl_ifc_nand.c

907

csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);

drivers/mtd/nand/raw/fsl_ifc_nand.c

960

ifc_nand_ctrl->chips[priv->bank] = NULL;

drivers/mtd/nand/raw/fsl_ifc_nand.c

965

static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,

drivers/mtd/nand/raw/fsl_ifc_nand.c

968

u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);

drivers/mtd/nand/raw/fsl_ifc_nand.c

988

int bank;

drivers/mtd/nand/raw/fsmc_nand.c

1073

(host->bank * FSMC_NAND_BANK_SZ);

drivers/mtd/nand/raw/fsmc_nand.c

148

unsigned int bank;

drivers/mtd/nand/raw/fsmc_nand.c

57

#define FSMC_NOR_REG(base, bank, reg) ((base) + \

drivers/mtd/nand/raw/fsmc_nand.c

58

(FSMC_NOR_BANK_SZ * (bank)) + \

drivers/mtd/nand/raw/fsmc_nand.c

904

host->bank = 0;

drivers/mtd/nand/raw/fsmc_nand.c

910

host->bank = val;

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

325

jz4780_nemc_assert(nfc->dev, cs->bank, true);

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

334

jz4780_nemc_assert(nfc->dev, cs->bank, false);

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

363

cs->bank = be32_to_cpu(*reg);

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

365

jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

38

unsigned int bank;

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

394

cs->bank);

drivers/mtd/spi-nor/core.c

1305

int bank;

drivers/mtd/spi-nor/core.c

1313

for (bank = first; bank <= last; bank++) {

drivers/mtd/spi-nor/core.c

1314

if (rww->used_banks & BIT(bank))

drivers/mtd/spi-nor/core.c

1317

used_banks |= BIT(bank);

drivers/mtd/spi-nor/core.c

1330

int bank;

drivers/mtd/spi-nor/core.c

1335

for (bank = first; bank <= last; bank++)

drivers/mtd/spi-nor/core.c

1336

rww->used_banks &= ~BIT(bank);

drivers/mtd/spi-nor/core.c

1376

int bank;

drivers/mtd/spi-nor/core.c

1384

for (bank = first; bank <= last; bank++) {

drivers/mtd/spi-nor/core.c

1385

if (rww->used_banks & BIT(bank))

drivers/mtd/spi-nor/core.c

1388

used_banks |= BIT(bank);

drivers/mtd/spi-nor/core.c

1402

int bank;

drivers/mtd/spi-nor/core.c

1407

for (bank = first; bank <= last; bank++)

drivers/mtd/spi-nor/core.c

1408

nor->rww.used_banks &= ~BIT(bank);

drivers/net/can/flexcan/flexcan-core.c

473

bool bank;

drivers/net/can/flexcan/flexcan-core.c

480

bank = mb_index >= bank_size;

drivers/net/can/flexcan/flexcan-core.c

481

if (bank)

drivers/net/can/flexcan/flexcan-core.c

485

(&priv->regs->mb[bank][priv->mb_size * mb_index]);

drivers/net/dsa/sja1105/sja1105_mdio.c

103

int offset, bank;

drivers/net/dsa/sja1105/sja1105_mdio.c

113

bank = addr >> 8;

drivers/net/dsa/sja1105/sja1105_mdio.c

122

tmp = bank;

drivers/net/dsa/sja1105/sja1105_mdio.c

57

int offset, bank;

drivers/net/dsa/sja1105/sja1105_mdio.c

72

bank = addr >> 8;

drivers/net/dsa/sja1105/sja1105_mdio.c

81

tmp = bank;

drivers/net/ethernet/airoha/airoha_eth.c

42

int bank = irq_bank - &qdma->irq_banks[0];

drivers/net/ethernet/airoha/airoha_eth.c

52

airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),

drivers/net/ethernet/airoha/airoha_eth.c

57

airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5823

u16 bank;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5838

for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5839

bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5841

bank,

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5850

bank,

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5907

u16 bank, i = 0;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5910

for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5911

bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5913

bank,

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5918

for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5919

bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5921

bank,

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

4604

u16 page_number, u8 bank,

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

4631

(bank ?

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

4782

if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

4801

page_data->page, page_data->bank,

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

4826

req->bank_number = page->bank;

drivers/net/ethernet/fungible/funcore/fun_hci.h

605

u8 bank;

drivers/net/ethernet/fungible/funcore/fun_hci.h

647

.bank = (_bank), .page = (_page), .offset = (_offset), \

drivers/net/ethernet/fungible/funcore/fun_hci.h

692

u8 bank;

drivers/net/ethernet/fungible/funeth/funeth_ethtool.c

1132

req->bank, req->page,

drivers/net/ethernet/intel/e1000e/ich8lan.c

3299

static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)

drivers/net/ethernet/intel/e1000e/ich8lan.c

3322

*bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3332

*bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3345

*bank = 1;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3357

*bank = 1;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3359

*bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3367

*bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3376

*bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3388

*bank = 1;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3413

u32 bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3427

ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3430

bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3433

act_offset = (bank) ? nvm->flash_bank_size : 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3506

u32 bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3518

ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3521

bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3524

act_offset = (bank) ? nvm->flash_bank_size : 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3933

u32 i, act_offset, new_bank_offset, old_bank_offset, bank;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3950

ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3953

bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3956

if (bank == 0) {

drivers/net/ethernet/intel/e1000e/ich8lan.c

4094

u32 i, act_offset, new_bank_offset, old_bank_offset, bank;

drivers/net/ethernet/intel/e1000e/ich8lan.c

4111

ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4114

bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

4117

if (bank == 0) {

drivers/net/ethernet/intel/e1000e/ich8lan.c

4598

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)

drivers/net/ethernet/intel/e1000e/ich8lan.c

4648

flash_linear_addr += (bank) ? flash_bank_size : 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

5835

u32 bank = 0;

drivers/net/ethernet/intel/e1000e/ich8lan.c

5869

if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {

drivers/net/ethernet/intel/e1000e/ich8lan.c

99

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

drivers/net/ethernet/intel/ice/ice_nvm.c

1052

ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,

drivers/net/ethernet/intel/ice/ice_nvm.c

1059

status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,

drivers/net/ethernet/intel/ice/ice_nvm.c

1064

status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,

drivers/net/ethernet/intel/ice/ice_nvm.c

246

static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)

drivers/net/ethernet/intel/ice/ice_nvm.c

291

switch (bank) {

drivers/net/ethernet/intel/ice/ice_nvm.c

298

ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);

drivers/net/ethernet/intel/ice/ice_nvm.c

320

ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,

drivers/net/ethernet/intel/ice/ice_nvm.c

326

start = ice_get_flash_bank_offset(hw, bank, module);

drivers/net/ethernet/intel/ice/ice_nvm.c

355

ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)

drivers/net/ethernet/intel/ice/ice_nvm.c

360

status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),

drivers/net/ethernet/intel/ice/ice_nvm.c

382

ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)

drivers/net/ethernet/intel/ice/ice_nvm.c

386

switch (bank) {

drivers/net/ethernet/intel/ice/ice_nvm.c

395

return ice_read_nvm_module(hw, bank, sr_copy + offset, data);

drivers/net/ethernet/intel/ice/ice_nvm.c

408

ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)

drivers/net/ethernet/intel/ice/ice_nvm.c

413

status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),

drivers/net/ethernet/intel/ice/ice_nvm.c

590

ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)

drivers/net/ethernet/intel/ice/ice_nvm.c

595

status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);

drivers/net/ethernet/intel/ice/ice_nvm.c

604

status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);

drivers/net/ethernet/intel/ice/ice_nvm.c

609

status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);

drivers/net/ethernet/intel/ice/ice_nvm.c

644

ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,

drivers/net/ethernet/intel/ice/ice_nvm.c

668

status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,

drivers/net/ethernet/intel/ice/ice_nvm.c

722

ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)

drivers/net/ethernet/intel/ice/ice_nvm.c

728

status = ice_get_orom_civd_data(hw, bank, &civd);

drivers/net/ethernet/intel/ice/ice_nvm.c

768

ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,

drivers/net/ethernet/intel/ice/ice_nvm.c

775

status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);

drivers/net/ethernet/intel/ice/ice_nvm.c

785

status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);

drivers/net/ethernet/intel/ice/ice_nvm.c

796

status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);

drivers/net/ethernet/intel/ice/ice_nvm.c

806

status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2716

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2759

switch (bank) {

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2789

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2795

start = ixgbe_get_flash_bank_offset(hw, bank, module);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2823

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2829

err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_NVM_BANK_PTR,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2851

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2857

err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2880

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2886

err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_OROM_BANK_PTR,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2907

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2914

err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_L,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2919

err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_H,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2946

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2952

err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2958

return ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2973

enum ixgbe_bank_select bank, u32 *srev)

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2978

err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_L, &srev_l);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2982

err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_H, &srev_h);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3007

ixgbe_get_orom_civd_data(struct ixgbe_hw *hw, enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3019

err = ixgbe_read_flash_module(hw, bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3079

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3087

err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3098

err = ixgbe_read_orom_module(hw, bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3104

err = ixgbe_read_orom_module(hw, bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3127

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3134

err = ixgbe_get_orom_civd_data(hw, bank, &civd);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3144

return ixgbe_get_orom_srev(hw, bank, &orom->srev);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3176

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3182

err = ixgbe_read_nvm_sr_copy(hw, bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3190

err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_LO,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3195

err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_HI,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3202

ixgbe_get_nvm_srev(hw, bank, &nvm->srev);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3252

enum ixgbe_bank_select bank,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3259

err = ixgbe_read_netlist_module(hw, bank, IXGBE_NETLIST_TYPE_OFFSET,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3267

err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_MODULE_LEN,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3278

err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_NODE_COUNT,

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3290

err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR,

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

1501

int bank, max_bank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

1513

for (bank = 0; bank < max_bank; bank++) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

1514

seq_printf(s, "BANK:%d\n", bank);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

1517

NDC_AF_BANKX_HIT_PC(bank)));

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

1520

NDC_AF_BANKX_MISS_PC(bank)));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

577

int bank, max_bank, line, max_line, err;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

597

for (bank = 0; bank < max_bank; bank++) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

604

NDC_AF_BANKX_LINEX_METADATA(bank, line));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

607

NDC_AF_BANKX_LINEX_METADATA(bank, line),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1007

int blkaddr, index, bank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1028

bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1032

NPC_AF_MCAMEX_BANKX_ACTION(index, bank));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1043

NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

176

int bank = index / mcam->banksize;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

180

return bank ? 2 : 0;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

182

return bank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

188

int bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

192

cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

199

int bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

200

int actbank = bank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

203

for (; bank < (actbank + mcam->banks_per_entry); bank++) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

205

NPC_AF_MCAMEX_BANKX_CFG(index, bank),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2089

int blkaddr, entry, bank, err;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2100

for (bank = 0; bank < mcam->banks; bank++) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2103

NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

213

int bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

214

int actbank = bank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

217

for (; bank < (actbank + mcam->banks_per_entry); bank++) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

219

NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

221

NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

224

NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2257

u32 bank = npc_get_bank(mcam, entry);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

226

NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2265

NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2274

u32 bank = npc_get_bank(mcam, entry);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

2281

NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

229

NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

231

NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

3552

u32 bank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

3561

bank = npc_get_bank(mcam, req->entry);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

3564

regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

369

int bank, nixlf, index;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

381

bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

385

NPC_AF_MCAMEX_BANKX_ACTION(index, bank));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

435

int bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

441

actbank = bank; /* Save bank id, to set action later on */

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

457

for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

469

NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

472

NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

478

NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

480

NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

484

NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

486

NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

511

int bank, kw = 0;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

515

bank = sbank;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

517

for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

519

NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

521

NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

525

NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

527

NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

548

int bank, i;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

554

for (bank = 0; bank < mcam->banks_per_entry; bank++) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

555

sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

556

dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

585

int bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

589

NPC_AF_MCAMEX_BANKX_ACTION(index, bank));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

595

int bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

599

NPC_AF_MCAMEX_BANKX_ACTION(index, bank), cfg);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

934

int actindex, index, bank, entry;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

952

bank = npc_get_bank(mcam, index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

964

NPC_AF_MCAMEX_BANKX_ACTION(entry, bank),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

981

int bank, op_rss;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

988

bank = npc_get_bank(mcam, mcam_index);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

994

NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

999

NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), *(u64 *)&action);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

1637

int blkaddr, bank, index;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

1666

bank = npc_get_bank(mcam, rule->entry);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

1669

(rule->entry, bank), def_action);

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

2125

query.bank = page_data->bank;

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

128

u32 bank;

drivers/net/ethernet/mellanox/mlxsw/core_env.c

495

mlxsw_reg_mcia_bank_number_set(mcia_pl, page->bank);

drivers/net/ethernet/mellanox/mlxsw/core_env.c

552

mlxsw_reg_mcia_bank_number_set(mcia_pl, page->bank);

drivers/net/ethernet/mellanox/mlxsw/reg.h

3756

u8 state, u8 bank, u32 bf_index)

drivers/net/ethernet/mellanox/mlxsw/reg.h

3763

mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);

drivers/net/ethernet/meta/fbnic/fbnic_ethtool.c

1669

fw_cmpl->u.qsfp.bank = page_data->bank;

drivers/net/ethernet/meta/fbnic/fbnic_ethtool.c

1672

page_data->bank, page_data->offset,

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

1204

u32 page, u32 bank, u32 offset, u32 length)

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

1216

err = fbnic_tlv_attr_put_int(msg, FBNIC_FW_QSFP_BANK, bank);

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

1259

u32 length, offset, page, bank;

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

1269

bank = fta_get_uint(results, FBNIC_FW_QSFP_BANK);

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

1270

if (bank != cmpl_data->u.qsfp.bank) {

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

1272

bank, cmpl_data->u.qsfp.bank);

drivers/net/ethernet/meta/fbnic/fbnic_fw.h

124

u32 page, u32 bank, u32 offset, u32 length);

drivers/net/ethernet/meta/fbnic/fbnic_fw.h

87

u8 bank;

drivers/net/ethernet/micrel/ks8842.c

171

static inline void ks8842_select_bank(struct ks8842_adapter *adapter, u16 bank)

drivers/net/ethernet/micrel/ks8842.c

173

iowrite16(bank, adapter->hw_addr + REG_SELECT_BANK);

drivers/net/ethernet/micrel/ks8842.c

176

static inline void ks8842_write8(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

179

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

183

static inline void ks8842_write16(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

186

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

190

static inline void ks8842_enable_bits(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

194

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

200

static inline void ks8842_clear_bits(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

204

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

210

static inline void ks8842_write32(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

213

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

217

static inline u8 ks8842_read8(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

220

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

224

static inline u16 ks8842_read16(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

227

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/micrel/ks8842.c

231

static inline u32 ks8842_read32(struct ks8842_adapter *adapter, u16 bank,

drivers/net/ethernet/micrel/ks8842.c

234

ks8842_select_bank(adapter, bank);

drivers/net/ethernet/microchip/enc28j60.c

205

if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {

drivers/net/ethernet/microchip/enc28j60.c

213

if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {

drivers/net/ethernet/microchip/enc28j60.c

221

priv->bank = b;

drivers/net/ethernet/microchip/enc28j60.c

63

u8 bank; /* current register bank selected */

drivers/net/ethernet/microchip/enc28j60.c

662

priv->bank = 0;

drivers/net/ethernet/microchip/encx24j600-regmap.c

116

u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);

drivers/net/ethernet/microchip/encx24j600-regmap.c

127

if ((banked_reg < 0x16) && (ctx->bank != bank))

drivers/net/ethernet/microchip/encx24j600-regmap.c

128

ret = encx24j600_switch_bank(ctx, bank);

drivers/net/ethernet/microchip/encx24j600-regmap.c

21

int bank)

drivers/net/ethernet/microchip/encx24j600-regmap.c

24

int bank_opcode = BANK_SELECT(bank);

drivers/net/ethernet/microchip/encx24j600-regmap.c

28

ctx->bank = bank;

drivers/net/ethernet/microchip/encx24j600-regmap.c

65

u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);

drivers/net/ethernet/microchip/encx24j600-regmap.c

73

if ((banked_reg < 0x16) && (ctx->bank != bank))

drivers/net/ethernet/microchip/encx24j600-regmap.c

74

ret = encx24j600_switch_bank(ctx, bank);

drivers/net/ethernet/microchip/encx24j600_hw.h

15

int bank;

drivers/net/ethernet/microchip/encx24j600_hw.h

22

#define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1))

drivers/net/ethernet/pensando/ionic/ionic_ethtool.c

976

if (page_data->bank != 0) {

drivers/net/ethernet/smsc/smc9194.c

848

unsigned int bank;

drivers/net/ethernet/smsc/smc9194.c

869

bank = inw( ioaddr + BANK_SELECT );

drivers/net/ethernet/smsc/smc9194.c

870

if ( (bank & 0xFF00) != 0x3300 ) {

drivers/net/ethernet/smsc/smc9194.c

877

bank = inw( ioaddr + BANK_SELECT );

drivers/net/ethernet/smsc/smc9194.c

878

if ( (bank & 0xFF00 ) != 0x3300 ) {

drivers/net/ethernet/smsc/smc91x.h

816

#define SMC_REG(lp, reg, bank) \

drivers/net/ethernet/smsc/smc91x.h

819

if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \

drivers/net/ethernet/smsc/smc91x.h

827

#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)

drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c

556

buffer.bank = page_data->bank;

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

403

u8 bank;

drivers/net/fddi/skfp/h/skfbi.h

733

#define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank)

drivers/net/phy/meson-gxl.c

103

FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |

drivers/net/phy/meson-gxl.c

66

unsigned int bank, unsigned int reg)

drivers/net/phy/meson-gxl.c

75

FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |

drivers/net/phy/meson-gxl.c

89

unsigned int bank, unsigned int reg,

drivers/net/phy/microchip_t1.c

300

u8 bank;

drivers/net/phy/microchip_t1.c

334

static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)

drivers/net/phy/microchip_t1.c

349

if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {

drivers/net/phy/microchip_t1.c

365

static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,

drivers/net/phy/microchip_t1.c

371

if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)

drivers/net/phy/microchip_t1.c

374

if (bank == PHYACC_ATTR_BANK_SMI) {

drivers/net/phy/microchip_t1.c

391

ereg |= (bank << 8) | offset;

drivers/net/phy/microchip_t1.c

395

rc = lan937x_dsp_workaround(phydev, ereg, bank);

drivers/net/phy/microchip_t1.c

411

u8 bank, u8 offset, u16 val, u16 mask)

drivers/net/phy/microchip_t1.c

415

if (bank > PHYACC_ATTR_BANK_MAX)

drivers/net/phy/microchip_t1.c

418

rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);

drivers/net/phy/microchip_t1.c

423

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);

drivers/net/phy/microchip_t1.c

481

cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) {

drivers/net/phy/microchip_t1.c

488

cmd_seq[i].bank, cmd_seq[i].offset,

drivers/net/phy/microchip_t1.c

881

cable_test[i].bank,

drivers/net/phy/microchip_t1.c

889

cable_test[i].bank,

drivers/net/phy/mscc/mscc_macsec.c

100

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,

drivers/net/phy/mscc/mscc_macsec.c

107

enum macsec_bank bank,

drivers/net/phy/mscc/mscc_macsec.c

110

u32 port = (bank == MACSEC_INGR) ?

drivers/net/phy/mscc/mscc_macsec.c

117

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,

drivers/net/phy/mscc/mscc_macsec.c

134

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,

drivers/net/phy/mscc/mscc_macsec.c

154

enum macsec_bank bank)

drivers/net/phy/mscc/mscc_macsec.c

158

if (bank != MACSEC_INGR)

drivers/net/phy/mscc/mscc_macsec.c

162

val = vsc8584_macsec_phy_read(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

166

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,

drivers/net/phy/mscc/mscc_macsec.c

169

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,

drivers/net/phy/mscc/mscc_macsec.c

176

enum macsec_bank bank)

drivers/net/phy/mscc/mscc_macsec.c

181

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,

drivers/net/phy/mscc/mscc_macsec.c

186

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,

drivers/net/phy/mscc/mscc_macsec.c

189

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,

drivers/net/phy/mscc/mscc_macsec.c

190

bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);

drivers/net/phy/mscc/mscc_macsec.c

191

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,

drivers/net/phy/mscc/mscc_macsec.c

192

MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |

drivers/net/phy/mscc/mscc_macsec.c

193

MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));

drivers/net/phy/mscc/mscc_macsec.c

196

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);

drivers/net/phy/mscc/mscc_macsec.c

198

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);

drivers/net/phy/mscc/mscc_macsec.c

201

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,

drivers/net/phy/mscc/mscc_macsec.c

204

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);

drivers/net/phy/mscc/mscc_macsec.c

206

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);

drivers/net/phy/mscc/mscc_macsec.c

208

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);

drivers/net/phy/mscc/mscc_macsec.c

211

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,

drivers/net/phy/mscc/mscc_macsec.c

216

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),

drivers/net/phy/mscc/mscc_macsec.c

220

if (bank == MACSEC_EGR) {

drivers/net/phy/mscc/mscc_macsec.c

221

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);

drivers/net/phy/mscc/mscc_macsec.c

223

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);

drivers/net/phy/mscc/mscc_macsec.c

225

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,

drivers/net/phy/mscc/mscc_macsec.c

23

enum macsec_bank bank, u32 reg)

drivers/net/phy/mscc/mscc_macsec.c

233

vsc8584_macsec_classification(phydev, bank);

drivers/net/phy/mscc/mscc_macsec.c

234

vsc8584_macsec_flow_default_action(phydev, bank, false);

drivers/net/phy/mscc/mscc_macsec.c

235

vsc8584_macsec_integrity_checks(phydev, bank);

drivers/net/phy/mscc/mscc_macsec.c

238

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,

drivers/net/phy/mscc/mscc_macsec.c

245

enum macsec_bank bank)

drivers/net/phy/mscc/mscc_macsec.c

252

vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);

drivers/net/phy/mscc/mscc_macsec.c

254

val = vsc8584_macsec_phy_read(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

259

vsc8584_macsec_phy_write(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

262

val = vsc8584_macsec_phy_read(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

265

vsc8584_macsec_phy_write(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

268

val = vsc8584_macsec_phy_read(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

270

if (bank == HOST_MAC)

drivers/net/phy/mscc/mscc_macsec.c

278

vsc8584_macsec_phy_write(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

281

vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,

drivers/net/phy/mscc/mscc_macsec.c

287

(bank == HOST_MAC ?

drivers/net/phy/mscc/mscc_macsec.c

292

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);

drivers/net/phy/mscc/mscc_macsec.c

294

vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);

drivers/net/phy/mscc/mscc_macsec.c

296

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);

drivers/net/phy/mscc/mscc_macsec.c

299

vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);

drivers/net/phy/mscc/mscc_macsec.c

301

vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,

drivers/net/phy/mscc/mscc_macsec.c

307

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);

drivers/net/phy/mscc/mscc_macsec.c

309

vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);

drivers/net/phy/mscc/mscc_macsec.c

311

vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,

drivers/net/phy/mscc/mscc_macsec.c

34

MSCC_PHY_MACSEC_20_TARGET(bank >> 2));

drivers/net/phy/mscc/mscc_macsec.c

36

if (bank >> 2 == 0x1)

drivers/net/phy/mscc/mscc_macsec.c

374

enum macsec_bank bank = flow->bank;

drivers/net/phy/mscc/mscc_macsec.c

38

bank &= 0x3;

drivers/net/phy/mscc/mscc_macsec.c

382

if (bank == MACSEC_INGR && flow->assoc_num >= 0) {

drivers/net/phy/mscc/mscc_macsec.c

387

if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {

drivers/net/phy/mscc/mscc_macsec.c

394

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),

drivers/net/phy/mscc/mscc_macsec.c

396

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),

drivers/net/phy/mscc/mscc_macsec.c

40

bank = 0;

drivers/net/phy/mscc/mscc_macsec.c

403

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),

drivers/net/phy/mscc/mscc_macsec.c

409

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);

drivers/net/phy/mscc/mscc_macsec.c

410

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);

drivers/net/phy/mscc/mscc_macsec.c

418

action = (bank == MACSEC_INGR) ?

drivers/net/phy/mscc/mscc_macsec.c

428

if (bank == MACSEC_INGR) {

drivers/net/phy/mscc/mscc_macsec.c

435

} else if (bank == MACSEC_EGR) {

drivers/net/phy/mscc/mscc_macsec.c

445

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);

drivers/net/phy/mscc/mscc_macsec.c

449

enum macsec_bank bank)

drivers/net/phy/mscc/mscc_macsec.c

45

MSCC_PHY_MACSEC_19_TARGET(bank));

drivers/net/phy/mscc/mscc_macsec.c

455

if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)

drivers/net/phy/mscc/mscc_macsec.c

464

enum macsec_bank bank = flow->bank;

drivers/net/phy/mscc/mscc_macsec.c

467

if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||

drivers/net/phy/mscc/mscc_macsec.c

468

(flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))

drivers/net/phy/mscc/mscc_macsec.c

472

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));

drivers/net/phy/mscc/mscc_macsec.c

475

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));

drivers/net/phy/mscc/mscc_macsec.c

477

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);

drivers/net/phy/mscc/mscc_macsec.c

483

enum macsec_bank bank = flow->bank;

drivers/net/phy/mscc/mscc_macsec.c

487

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));

drivers/net/phy/mscc/mscc_macsec.c

490

val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));

drivers/net/phy/mscc/mscc_macsec.c

492

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);

drivers/net/phy/mscc/mscc_macsec.c

497

if (flow->bank == MACSEC_INGR)

drivers/net/phy/mscc/mscc_macsec.c

524

enum macsec_bank bank = flow->bank;

drivers/net/phy/mscc/mscc_macsec.c

545

control |= (bank == MACSEC_EGR) ?

drivers/net/phy/mscc/mscc_macsec.c

555

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),

drivers/net/phy/mscc/mscc_macsec.c

559

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),

drivers/net/phy/mscc/mscc_macsec.c

564

vsc8584_macsec_phy_write(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

570

vsc8584_macsec_phy_write(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

575

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),

drivers/net/phy/mscc/mscc_macsec.c

576

bank == MACSEC_INGR ?

drivers/net/phy/mscc/mscc_macsec.c

579

if (bank == MACSEC_INGR)

drivers/net/phy/mscc/mscc_macsec.c

581

vsc8584_macsec_phy_write(phydev, bank,

drivers/net/phy/mscc/mscc_macsec.c

586

sci = (__force u64)(bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci);

drivers/net/phy/mscc/mscc_macsec.c

587

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),

drivers/net/phy/mscc/mscc_macsec.c

589

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),

drivers/net/phy/mscc/mscc_macsec.c

593

vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),

drivers/net/phy/mscc/mscc_macsec.c

601

enum macsec_bank bank)

drivers/net/phy/mscc/mscc_macsec.c

603

unsigned long *bitmap = bank == MACSEC_INGR ?

drivers/net/phy/mscc/mscc_macsec.c

619

flow->bank = bank;

drivers/net/phy/mscc/mscc_macsec.c

62

enum macsec_bank bank, u32 reg, u32 val)

drivers/net/phy/mscc/mscc_macsec.c

630

unsigned long *bitmap = flow->bank == MACSEC_INGR ?

drivers/net/phy/mscc/mscc_macsec.c

72

MSCC_PHY_MACSEC_20_TARGET(bank >> 2));

drivers/net/phy/mscc/mscc_macsec.c

74

if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))

drivers/net/phy/mscc/mscc_macsec.c

75

bank &= 0x3;

drivers/net/phy/mscc/mscc_macsec.c

78

bank = 0;

drivers/net/phy/mscc/mscc_macsec.c

820

if (flow->bank == MACSEC_INGR && flow->rx_sa &&

drivers/net/phy/mscc/mscc_macsec.c

85

MSCC_PHY_MACSEC_19_TARGET(bank));

drivers/net/phy/mscc/mscc_macsec.c

97

enum macsec_bank bank)

drivers/net/phy/mscc/mscc_macsec.c

989

if (flow->bank != MACSEC_EGR || !flow->has_transformation)

drivers/net/phy/mscc/mscc_macsec.h

76

enum macsec_bank bank;

drivers/net/phy/sfp.c

2958

if (page->bank) {

drivers/net/wireless/ath/ath5k/phy.c

198

u8 offset, bank, num_bits, col, position;

drivers/net/wireless/ath/ath5k/phy.c

221

bank = rfreg->bank;

drivers/net/wireless/ath/ath5k/phy.c

230

offset = ah->ah_offset[bank];

drivers/net/wireless/ath/ath5k/phy.c

822

int i, obdb = -1, bank = -1;

drivers/net/wireless/ath/ath5k/phy.c

908

if (bank != ini_rfb[i].rfb_bank) {

drivers/net/wireless/ath/ath5k/phy.c

909

bank = ini_rfb[i].rfb_bank;

drivers/net/wireless/ath/ath5k/phy.c

910

ah->ah_offset[bank] = i;

drivers/net/wireless/ath/ath5k/rfbuffer.h

94

u8 bank;

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

24

u8 bank, reg;

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

29

bank = MT_RF_BANK(offset);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

32

if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8))

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

44

FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

54

bank, reg, ret);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

63

u8 bank, reg;

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

68

bank = MT_RF_BANK(offset);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

71

if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8))

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

80

FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

89

FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

97

bank, reg, ret);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

21

#define MT_RF(bank, reg) ((bank) << 16 | (reg))

drivers/net/wireless/mediatek/mt7601u/initvals_phy.h

10

#define RF_REG_PAIR(bank, reg, value) \

drivers/net/wireless/mediatek/mt7601u/initvals_phy.h

11

{ MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value }

drivers/net/wireless/mediatek/mt7601u/phy.c

103

ret = mt7601u_rf_wr(dev, bank, offset, val);

drivers/net/wireless/mediatek/mt7601u/phy.c

111

mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val)

drivers/net/wireless/mediatek/mt7601u/phy.c

113

return mt7601u_rf_rmw(dev, bank, offset, 0, val);

drivers/net/wireless/mediatek/mt7601u/phy.c

117

mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask)

drivers/net/wireless/mediatek/mt7601u/phy.c

119

return mt7601u_rf_rmw(dev, bank, offset, mask, 0);

drivers/net/wireless/mediatek/mt7601u/phy.c

19

mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value)

drivers/net/wireless/mediatek/mt7601u/phy.c

38

FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |

drivers/net/wireless/mediatek/mt7601u/phy.c

42

trace_rf_write(dev, bank, offset, value);

drivers/net/wireless/mediatek/mt7601u/phy.c

48

bank, offset, ret);

drivers/net/wireless/mediatek/mt7601u/phy.c

54

mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset)

drivers/net/wireless/mediatek/mt7601u/phy.c

71

FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |

drivers/net/wireless/mediatek/mt7601u/phy.c

80

FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) {

drivers/net/wireless/mediatek/mt7601u/phy.c

82

trace_rf_read(dev, bank, offset, ret);

drivers/net/wireless/mediatek/mt7601u/phy.c

89

bank, offset, ret);

drivers/net/wireless/mediatek/mt7601u/phy.c

95

mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val)

drivers/net/wireless/mediatek/mt7601u/phy.c

99

ret = mt7601u_rf_rr(dev, bank, offset);

drivers/net/wireless/mediatek/mt7601u/trace.h

142

TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val),

drivers/net/wireless/mediatek/mt7601u/trace.h

143

TP_ARGS(dev, bank, reg, val),

drivers/net/wireless/mediatek/mt7601u/trace.h

146

__field(u8, bank)

drivers/net/wireless/mediatek/mt7601u/trace.h

153

__entry->bank = bank;

drivers/net/wireless/mediatek/mt7601u/trace.h

157

DEV_PR_ARG, __entry->bank, __entry->reg, __entry->val

drivers/net/wireless/mediatek/mt7601u/trace.h

162

TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val),

drivers/net/wireless/mediatek/mt7601u/trace.h

163

TP_ARGS(dev, bank, reg, val)

drivers/net/wireless/mediatek/mt7601u/trace.h

167

TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val),

drivers/net/wireless/mediatek/mt7601u/trace.h

168

TP_ARGS(dev, bank, reg, val)

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

183

static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

186

rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

277

static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

280

return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9116

rf_reg_record[CHAIN_0][0].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9120

rf_reg_record[CHAIN_0][1].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9124

rf_reg_record[CHAIN_0][2].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9128

rf_reg_record[CHAIN_0][3].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9132

rf_reg_record[CHAIN_0][4].bank = 4;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9136

rf_reg_record[CHAIN_0][5].bank = 4;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9140

rf_reg_record[CHAIN_0][6].bank = 4;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9144

rf_reg_record[CHAIN_0][7].bank = 5;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9148

rf_reg_record[CHAIN_0][8].bank = 5;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9152

rf_reg_record[CHAIN_0][9].bank = 5;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9156

rf_reg_record[CHAIN_0][10].bank = 5;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9160

rf_reg_record[CHAIN_0][11].bank = 5;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9164

rf_reg_record[CHAIN_0][12].bank = 5;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9169

rf_reg_record[CHAIN_1][0].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9173

rf_reg_record[CHAIN_1][1].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9177

rf_reg_record[CHAIN_1][2].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9181

rf_reg_record[CHAIN_1][3].bank = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9185

rf_reg_record[CHAIN_1][4].bank = 6;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9189

rf_reg_record[CHAIN_1][5].bank = 6;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9193

rf_reg_record[CHAIN_1][6].bank = 6;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9197

rf_reg_record[CHAIN_1][7].bank = 7;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9201

rf_reg_record[CHAIN_1][8].bank = 7;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9205

rf_reg_record[CHAIN_1][9].bank = 7;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9209

rf_reg_record[CHAIN_1][10].bank = 7;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9213

rf_reg_record[CHAIN_1][11].bank = 7;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9217

rf_reg_record[CHAIN_1][12].bank = 7;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9229

u8 bank = 0, rf_register = 0, value = 0;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9233

bank = rf_record[chain_index][record_index].bank;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9236

rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9238

bank, rf_register, value);

drivers/net/wireless/ralink/rt2x00/rt2800lib.h

26

u8 bank;

drivers/net/wireless/realtek/rtw89/efuse.c

43

enum rtw89_efuse_bank bank)

drivers/net/wireless/realtek/rtw89/efuse.c

52

if (bank == val)

drivers/net/wireless/realtek/rtw89/efuse.c

56

bank);

drivers/net/wireless/realtek/rtw89/efuse.c

60

if (bank == val)

drivers/nvmem/imx-iim.c

44

int bank = i >> 5;

drivers/nvmem/imx-iim.c

47

*buf8++ = readl(iim->base + IIM_BANK_BASE(bank) + reg * 4);

drivers/nvmem/nintendo-otp.c

54

u32 bank, addr;

drivers/nvmem/nintendo-otp.c

57

bank = (reg / BANK_SIZE) << 8;

drivers/nvmem/nintendo-otp.c

59

iowrite32be(OTP_READ | bank | addr, priv->regs + HW_OTPCMD);

drivers/nvmem/rcar-efuse.c

100

.bank = 0,

drivers/nvmem/rcar-efuse.c

106

.bank = 0,

drivers/nvmem/rcar-efuse.c

112

.bank = 1,

drivers/nvmem/rcar-efuse.c

118

.bank = 1,

drivers/nvmem/rcar-efuse.c

25

unsigned int bank; /* 0: PFC + E-FUSE, 1: OPT_MEM + E-FUSE */

drivers/nvmem/rcar-efuse.c

75

fuse->base = devm_platform_get_and_ioremap_resource(pdev, data->bank,

drivers/pci/controller/cadence/pcie-cadence.h

182

static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank)

drivers/pci/controller/cadence/pcie-cadence.h

186

switch (bank) {

drivers/pci/controller/cadence/pcie-cadence.h

232

enum cdns_pcie_reg_bank bank,

drivers/pci/controller/cadence/pcie-cadence.h

236

u32 offset = cdns_reg_bank_to_off(pcie, bank);

drivers/pci/controller/cadence/pcie-cadence.h

243

enum cdns_pcie_reg_bank bank,

drivers/pci/controller/cadence/pcie-cadence.h

246

u32 offset = cdns_reg_bank_to_off(pcie, bank);

drivers/perf/arm_brbe.c

259

static void select_brbe_bank(int bank)

drivers/perf/arm_brbe.c

265

brbfcr |= SYS_FIELD_PREP(BRBFCR_EL1, BANK, bank);

drivers/perf/arm_brbe.c

784

for (int bank = 0; bank < nr_banks; bank++) {

drivers/perf/arm_brbe.c

785

int nr_remaining = nr_hw - (bank * BRBE_BANK_MAX_ENTRIES);

drivers/perf/arm_brbe.c

788

select_brbe_bank(bank);

drivers/perf/arm_cspmu/ampere_cspmu.c

107

ARM_CSPMU_FORMAT_ATTR(bank, "config1:24-55"),

drivers/perf/arm_cspmu/ampere_cspmu.c

147

u32 threshold, rank, bank;

drivers/perf/arm_cspmu/ampere_cspmu.c

151

bank = get_bank(event);

drivers/perf/arm_cspmu/ampere_cspmu.c

155

writel(bank, cspmu->base0 + PMAUXR2);

drivers/perf/arm_cspmu/ampere_cspmu.c

38

SOC_PMU_EVENT_ATTR_EXTRACTOR(bank, config1, 24, 55);

drivers/perf/xgene_pmu.c

289

XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b),

drivers/perf/xgene_pmu.c

292

XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e),

drivers/perf/xgene_pmu.c

293

XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f),

drivers/perf/xgene_pmu.c

389

XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b),

drivers/phy/broadcom/phy-brcm-sata.c

211

static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,

drivers/phy/broadcom/phy-brcm-sata.c

219

bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);

drivers/phy/broadcom/phy-brcm-sata.c

223

writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);

drivers/phy/broadcom/phy-brcm-sata.c

229

static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)

drivers/phy/broadcom/phy-brcm-sata.c

235

bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);

drivers/phy/broadcom/phy-brcm-sata.c

239

writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);

drivers/phy/mediatek/phy-mtk-tphy.c

1004

struct u3phy_banks *bank = &instance->u3_banks;

drivers/phy/mediatek/phy-mtk-tphy.c

1006

mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,

drivers/phy/mediatek/phy-mtk-tphy.c

1009

mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,

drivers/phy/mediatek/phy-mtk-tphy.c

1017

struct u3phy_banks *bank = &instance->u3_banks;

drivers/phy/mediatek/phy-mtk-tphy.c

1019

mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,

drivers/phy/mediatek/phy-mtk-tphy.c

1022

mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,

drivers/phy/renesas/r8a779f0-ether-serdes.c

46

static void r8a779f0_eth_serdes_write32(void __iomem *addr, u32 offs, u32 bank, u32 data)

drivers/phy/renesas/r8a779f0-ether-serdes.c

48

iowrite32(bank, addr + R8A779F0_ETH_SERDES_BANK_SELECT);

drivers/phy/renesas/r8a779f0-ether-serdes.c

52

static u32 r8a779f0_eth_serdes_read32(void __iomem *addr, u32 offs, u32 bank)

drivers/phy/renesas/r8a779f0-ether-serdes.c

54

iowrite32(bank, addr + R8A779F0_ETH_SERDES_BANK_SELECT);

drivers/phy/renesas/r8a779f0-ether-serdes.c

61

u32 offs, u32 bank, u32 mask, u32 expected)

drivers/phy/renesas/r8a779f0-ether-serdes.c

66

iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT);

drivers/phy/renesas/r8a779f0-ether-serdes.c

74

__func__, channel->index, offs, bank, mask, expected);

drivers/phy/st/phy-miphy28lp.c

272

int bank;

drivers/phy/st/phy-miphy28lp.c

289

.bank = 0x00,

drivers/phy/st/phy-miphy28lp.c

302

.bank = 0x01,

drivers/phy/st/phy-miphy28lp.c

315

.bank = 0x02,

drivers/phy/st/phy-miphy28lp.c

331

.bank = 0x00,

drivers/phy/st/phy-miphy28lp.c

345

.bank = 0x01,

drivers/phy/st/phy-miphy28lp.c

434

writeb_relaxed(gen->bank, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

461

writeb_relaxed(gen->bank, base + MIPHY_CONF);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

426

unsigned int bank, u32 mask)

drivers/pinctrl/bcm/pinctrl-bcm2835.c

432

events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

434

events &= pc->enabled_irq_map[bank];

drivers/pinctrl/bcm/pinctrl-bcm2835.c

436

gpio = (32 * bank) + offset;

drivers/pinctrl/bcm/pinctrl-bcm2835.c

530

unsigned bank = GPIO_REG_OFFSET(gpio);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

535

raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

536

set_bit(offset, &pc->enabled_irq_map[bank]);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

538

raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

547

unsigned bank = GPIO_REG_OFFSET(gpio);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

550

raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

554

clear_bit(offset, &pc->enabled_irq_map[bank]);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

555

raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

656

unsigned bank = GPIO_REG_OFFSET(gpio);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

660

raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);

drivers/pinctrl/bcm/pinctrl-bcm2835.c

662

if (test_bit(offset, &pc->enabled_irq_map[bank]))

drivers/pinctrl/bcm/pinctrl-bcm2835.c

672

raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);

drivers/pinctrl/freescale/pinctrl-mxs.c

209

u8 bank, shift;

drivers/pinctrl/freescale/pinctrl-mxs.c

214

bank = PINID_TO_BANK(g->pins[i]);

drivers/pinctrl/freescale/pinctrl-mxs.c

217

reg += bank * 0x20 + pin / 16 * 0x10;

drivers/pinctrl/freescale/pinctrl-mxs.c

263

u8 ma, vol, pull, bank, shift;

drivers/pinctrl/freescale/pinctrl-mxs.c

277

bank = PINID_TO_BANK(g->pins[i]);

drivers/pinctrl/freescale/pinctrl-mxs.c

282

reg += bank * 0x40 + pin / 8 * 0x10;

drivers/pinctrl/freescale/pinctrl-mxs.c

302

reg += bank * 0x10;

drivers/pinctrl/freescale/pinctrl-mxs.h

17

#define PINID(bank, pin) ((bank) * 32 + (pin))

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1001

struct aml_gpio_bank *bank = &info->banks[bank_nr];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1010

bank->bank_id = ret;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1012

bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux");

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1013

if (IS_ERR_OR_NULL(bank->reg_mux)) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1014

if (bank->bank_id == AMLOGIC_GPIO_TEST_N ||

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1015

bank->bank_id == AMLOGIC_GPIO_ANALOG)

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1016

bank->reg_mux = NULL;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1018

return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT,

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1022

bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio");

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1023

if (IS_ERR_OR_NULL(bank->reg_gpio))

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1024

return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT,

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1027

bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds");

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1028

if (IS_ERR_OR_NULL(bank->reg_ds)) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1030

bank->reg_ds = bank->reg_gpio;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1033

bank->gpio_chip = aml_gpio_template;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1034

bank->gpio_chip.base = -1;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1035

bank->gpio_chip.ngpio = aml_bank_pins(np);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1036

bank->gpio_chip.fwnode = of_fwnode_handle(np);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1037

bank->gpio_chip.parent = dev;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1039

init_bank_register_bit(info, bank);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1040

bank->gpio_chip.label = aml_bank_name[bank->bank_id];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1042

bank->pin_base = bank->bank_id << 8;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1055

int i = 0, j = 0, k = 0, bank;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1085

bank = 0;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1091

ret = aml_gpiolib_register_bank(info, bank, child);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1095

k = info->banks[bank].pin_base;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1096

bank_name = info->banks[bank].gpio_chip.label;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1099

info->banks[bank].gpio_chip.ngpio);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1103

for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

1108

bank++;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

177

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

181

unsigned int offset = bank->mux_bit_offs;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

185

if (bank->p_mux) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

186

p_mux = bank->p_mux;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

188

bank = NULL;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

191

bank = &info->banks[i];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

196

if (!bank || !bank->reg_mux)

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

202

return regmap_update_bits(bank->reg_mux, reg,

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

208

if (!bank->reg_mux)

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

212

return regmap_update_bits(bank->reg_mux, reg,

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

282

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

285

+ bank->pc.bit_offset[reg_type];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

286

*reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

296

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

302

ret = regmap_read(bank->reg_gpio, reg, &val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

311

ret = regmap_read(bank->reg_gpio, reg, &val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

330

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

335

if (!bank->reg_ds)

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

339

ret = regmap_read(bank->reg_ds, reg, &val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

369

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

374

ret = regmap_read(bank->reg_gpio, reg, &val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

453

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

458

return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

466

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

474

ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

479

return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit));

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

488

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

491

if (!bank->reg_ds) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

513

return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

523

struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

527

return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

879

static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank,

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

885

*bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

886

*reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

894

struct aml_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

898

aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

900

ret = regmap_read(bank->reg_gpio, reg, &val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

909

struct aml_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

912

aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

914

return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit));

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

920

struct aml_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

924

aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

925

ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

929

aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, &reg, &bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

931

return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

937

struct aml_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

940

aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, &reg, &bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

942

return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

948

struct aml_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

951

aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, &reg, &bit);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

952

regmap_read(bank->reg_gpio, reg, &val);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

970

struct aml_gpio_bank *bank)

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

977

bank->pc.reg_offset[i] = aml_def_regoffs[i];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

978

bank->pc.bit_offset[i] = 0;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

981

bank->mux_bit_offs = 0;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

986

if (bank->bank_id == p_mux->m_bank_id) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

987

bank->mux_bit_offs = p_mux->m_bit_offs;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

990

if (p_mux->sid >> 8 == bank->bank_id) {

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

991

bank->p_mux = p_mux;

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

30

const struct meson_pmx_bank **bank)

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

38

*bank = &pmx->pmx_banks[i];

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

45

static int meson_pmx_calc_reg_and_offset(const struct meson_pmx_bank *bank,

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

51

shift = pin - bank->first;

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

53

*reg = bank->reg + (bank->offset + (shift << 2)) / 32;

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

54

*offset = (bank->offset + (shift << 2)) % 32;

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

62

const struct meson_pmx_bank *bank;

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

67

ret = meson_axg_pmx_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c

71

meson_pmx_calc_reg_and_offset(bank, pin, &reg, &offset);

drivers/pinctrl/meson/pinctrl-meson.c

102

const struct meson_reg_desc *desc = &bank->regs[reg_type];

drivers/pinctrl/meson/pinctrl-meson.c

104

*bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];

drivers/pinctrl/meson/pinctrl-meson.c

185

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

189

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

193

meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

202

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

206

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

210

meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

265

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

269

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

273

meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

284

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

288

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

292

meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

300

meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

312

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

321

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

325

meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

403

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

407

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

411

meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

420

meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

439

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

447

ret = meson_get_bank(pc, pin, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

451

meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

591

const struct meson_bank *bank;

drivers/pinctrl/meson/pinctrl-meson.c

595

ret = meson_get_bank(pc, gpio, &bank);

drivers/pinctrl/meson/pinctrl-meson.c

599

meson_calc_reg_and_bit(bank, gpio, MESON_REG_IN, &reg, &bit);

drivers/pinctrl/meson/pinctrl-meson.c

73

const struct meson_bank **bank)

drivers/pinctrl/meson/pinctrl-meson.c

80

*bank = &pc->data->banks[i];

drivers/pinctrl/meson/pinctrl-meson.c

97

static void meson_calc_reg_and_bit(const struct meson_bank *bank,

drivers/pinctrl/nomadik/pinctrl-nomadik.c

935

slpm[nmk_chip->bank] &= ~BIT(bit);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

321

struct ma35_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

322

void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

333

struct ma35_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

334

void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

335

void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

354

struct ma35_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

355

void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

362

struct ma35_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

363

void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

378

struct ma35_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

383

reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

387

reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

391

regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, &regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

393

regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

400

struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

401

void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

409

struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

410

void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

423

struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

424

void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

425

void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

429

bval = bank->irqtype & BIT(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

434

bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

442

struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

448

bank->irqtype &= ~BIT(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

449

bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

454

bank->irqtype &= ~BIT(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

455

bank->irqinten |= MA35_GP_INTEN_H(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

456

bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

461

bank->irqtype &= ~BIT(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

462

bank->irqinten |= MA35_GP_INTEN_L(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

463

bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

469

writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

470

writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

489

struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

490

struct irq_domain *irqdomain = bank->chip.irq.domain;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

497

isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

499

for_each_set_bit(offset, &isr, bank->nr_pins)

drivers/pinctrl/nuvoton/pinctrl-ma35.c

508

struct ma35_pin_bank *bank = ctrl->pin_banks;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

512

for (i = 0; i < ctrl->nr_banks; i++, bank++) {

drivers/pinctrl/nuvoton/pinctrl-ma35.c

513

if (!bank->valid) {

drivers/pinctrl/nuvoton/pinctrl-ma35.c

514

dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

517

bank->irqtype = 0;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

518

bank->irqinten = 0;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

519

bank->chip.label = bank->name;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

520

bank->chip.parent = &pdev->dev;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

521

bank->chip.request = ma35_gpio_core_to_request;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

522

bank->chip.direction_input = ma35_gpio_core_direction_in;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

523

bank->chip.direction_output = ma35_gpio_core_direction_out;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

524

bank->chip.get = ma35_gpio_core_get;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

525

bank->chip.set = ma35_gpio_core_set;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

526

bank->chip.base = -1;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

527

bank->chip.ngpio = bank->nr_pins;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

528

bank->chip.can_sleep = false;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

530

if (bank->irq > 0) {

drivers/pinctrl/nuvoton/pinctrl-ma35.c

533

girq = &bank->chip.irq;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

543

girq->parents[0] = bank->irq;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

548

ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

551

bank->chip.label, ret);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

558

static int ma35_get_bank_data(struct ma35_pin_bank *bank)

drivers/pinctrl/nuvoton/pinctrl-ma35.c

560

bank->reg_base = fwnode_iomap(bank->fwnode, 0);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

561

if (!bank->reg_base)

drivers/pinctrl/nuvoton/pinctrl-ma35.c

564

bank->irq = fwnode_irq_get(bank->fwnode, 0);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

566

bank->nr_pins = MA35_GPIO_PORT_MAX;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

568

bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

569

if (IS_ERR(bank->clk))

drivers/pinctrl/nuvoton/pinctrl-ma35.c

570

return PTR_ERR(bank->clk);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

572

return clk_prepare_enable(bank->clk);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

579

struct ma35_pin_bank *bank;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

596

bank = &ctrl->pin_banks[id];

drivers/pinctrl/nuvoton/pinctrl-ma35.c

597

bank->fwnode = child;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

598

bank->regmap = pctl->regmap;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

599

bank->dev = &pdev->dev;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

600

if (!ma35_get_bank_data(bank))

drivers/pinctrl/nuvoton/pinctrl-ma35.c

601

bank->valid = true;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

127

struct npcm7xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

130

bank->chip.gc.base / bank->chip.gc.ngpio,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

131

bank->chip.gc.base,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

132

bank->chip.gc.base + bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

134

ioread32(bank->base + NPCM7XX_GP_N_DIN),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

135

ioread32(bank->base + NPCM7XX_GP_N_DOUT),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

136

ioread32(bank->base + NPCM7XX_GP_N_IEM),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

137

ioread32(bank->base + NPCM7XX_GP_N_OE));

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

139

ioread32(bank->base + NPCM7XX_GP_N_PU),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

140

ioread32(bank->base + NPCM7XX_GP_N_PD),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

141

ioread32(bank->base + NPCM7XX_GP_N_DBNC),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1417

static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

142

ioread32(bank->base + NPCM7XX_GP_N_POL));

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1421

int gpio = (pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1425

return ioread32(bank->base + NPCM7XX_GP_N_OSRC)

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1437

static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

144

ioread32(bank->base + NPCM7XX_GP_N_EVTYP),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1441

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1446

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

145

ioread32(bank->base + NPCM7XX_GP_N_EVBE),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1450

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

146

ioread32(bank->base + NPCM7XX_GP_N_EVEN),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

147

ioread32(bank->base + NPCM7XX_GP_N_EVST));

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1481

struct npcm7xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1483

int gpio = (pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

149

ioread32(bank->base + NPCM7XX_GP_N_OTYP),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1491

val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1494

dev_dbg(bank->chip.gc.parent,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

150

ioread32(bank->base + NPCM7XX_GP_N_OSRC),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1507

struct npcm7xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1509

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

151

ioread32(bank->base + NPCM7XX_GP_N_ODSC));

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1515

dev_dbg(bank->chip.gc.parent,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1517

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1520

dev_dbg(bank->chip.gc.parent,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1522

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

153

ioread32(bank->base + NPCM7XX_GP_N_OBL0),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

154

ioread32(bank->base + NPCM7XX_GP_N_OBL1),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

155

ioread32(bank->base + NPCM7XX_GP_N_OBL2),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

156

ioread32(bank->base + NPCM7XX_GP_N_OBL3));

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

158

ioread32(bank->base + NPCM7XX_GP_N_SPLCK),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

159

ioread32(bank->base + NPCM7XX_GP_N_MPLCK));

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

164

struct npcm7xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1653

struct npcm7xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1655

int gpio = BIT(offset % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1657

dev_dbg(bank->chip.gc.parent, "GPIO Set Direction: %d = %d\n", offset,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1660

iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1662

iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1683

struct npcm7xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1685

int gpio = (pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1694

pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1695

pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1705

ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1706

oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

171

return bank->direction_input(chip, offset);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1713

rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1716

rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1719

rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1727

rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1746

struct npcm7xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1748

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1750

dev_dbg(bank->chip.gc.parent, "param=%d %d[GPIO]\n", param, pin);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1753

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1754

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1757

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1758

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1761

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1762

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1765

iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1766

bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1769

bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1770

iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1773

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1776

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1779

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_DBNC, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

178

struct npcm7xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1782

return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

188

return bank->direction_output(chip, offset, value);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

193

struct npcm7xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

201

return bank->request(chip, offset);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

208

struct npcm7xx_gpio *bank;

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

212

bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

216

sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

217

en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

218

dev_dbg(bank->chip.gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

230

struct npcm7xx_gpio *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

233

dev_dbg(bank->chip.gc.parent, "setirqtype: %u.%u = %u\n", gpio,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

237

dev_dbg(bank->chip.gc.parent, "edge.rising\n");

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

238

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

239

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

242

dev_dbg(bank->chip.gc.parent, "edge.falling\n");

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

243

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

244

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

247

dev_dbg(bank->chip.gc.parent, "edge.both\n");

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

248

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

251

dev_dbg(bank->chip.gc.parent, "level.low\n");

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

252

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

255

dev_dbg(bank->chip.gc.parent, "level.high\n");

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

256

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

259

dev_dbg(bank->chip.gc.parent, "invalid irq type\n");

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

264

npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

268

npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

278

struct npcm7xx_gpio *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

281

dev_dbg(bank->chip.gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

282

iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

289

struct npcm7xx_gpio *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

293

dev_dbg(bank->chip.gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

294

iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

302

struct npcm7xx_gpio *bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

307

dev_dbg(bank->chip.gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

308

iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

137

struct npcm8xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

140

ioread32(bank->base + NPCM8XX_GP_N_DIN),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

141

ioread32(bank->base + NPCM8XX_GP_N_DOUT),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

142

ioread32(bank->base + NPCM8XX_GP_N_IEM),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

143

ioread32(bank->base + NPCM8XX_GP_N_OE));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

145

ioread32(bank->base + NPCM8XX_GP_N_PU),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

146

ioread32(bank->base + NPCM8XX_GP_N_PD),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

147

ioread32(bank->base + NPCM8XX_GP_N_DBNC),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

148

ioread32(bank->base + NPCM8XX_GP_N_POL));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

150

ioread32(bank->base + NPCM8XX_GP_N_EVTYP),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

151

ioread32(bank->base + NPCM8XX_GP_N_EVBE),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

152

ioread32(bank->base + NPCM8XX_GP_N_EVEN),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

153

ioread32(bank->base + NPCM8XX_GP_N_EVST));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

155

ioread32(bank->base + NPCM8XX_GP_N_OTYP),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

156

ioread32(bank->base + NPCM8XX_GP_N_OSRC),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

157

ioread32(bank->base + NPCM8XX_GP_N_ODSC));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

159

ioread32(bank->base + NPCM8XX_GP_N_OBL0),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

160

ioread32(bank->base + NPCM8XX_GP_N_OBL1),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

161

ioread32(bank->base + NPCM8XX_GP_N_OBL2),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

162

ioread32(bank->base + NPCM8XX_GP_N_OBL3));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

164

ioread32(bank->base + NPCM8XX_GP_N_SPLCK),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

165

ioread32(bank->base + NPCM8XX_GP_N_MPLCK));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

170

struct npcm8xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

177

return bank->direction_input(chip, offset);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

183

struct npcm8xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1839

static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1842

int gpio = pin % bank->chip.gc.ngpio;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1847

return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1857

static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1861

void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1862

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1867

npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1870

npcm_gpio_set(&bank->chip, OSRC_Offset, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

190

return bank->direction_output(chip, offset, value);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1900

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1902

int gpio = pin % bank->chip.gc.ngpio;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1911

val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1913

dev_dbg(bank->chip.gc.parent, "pin %d strength %d = %d\n", pin, val, ds);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1921

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1923

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1929

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1931

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

195

struct npcm8xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

202

return bank->request(chip, offset);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2052

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2054

int gpio = BIT(offset % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2057

iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2059

iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2074

static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2077

void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

208

struct npcm8xx_gpio *bank;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2082

if (bank->debounce.set_val[i]) {

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2083

if (bank->debounce.nanosec_val[i] == nanosecs) {

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2085

npcm_gpio_set(&bank->chip, DBNCS_offset,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2090

bank->debounce.set_val[i] = true;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2091

bank->debounce.nanosec_val[i] = nanosecs;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2093

npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2096

iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2099

iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2102

iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2105

iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2108

iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2111

iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2114

iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2117

iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2127

bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

213

bank = gpiochip_get_data(gc);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2143

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2145

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2149

ret = debounce_timing_setting(bank, pin % bank->chip.gc.ngpio,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2154

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2159

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

217

sts = ioread32(bank->base + NPCM8XX_GP_N_EVST);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2170

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2172

int gpio = pin % bank->chip.gc.ngpio;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

218

en = ioread32(bank->base + NPCM8XX_GP_N_EVEN);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2181

pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2182

pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2192

ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2193

oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2200

rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2203

rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2206

rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask;

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2214

rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2232

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2235

int gpio = BIT(pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2239

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2240

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2243

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2244

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2247

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2248

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2251

iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2252

bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2255

bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2256

iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2259

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2262

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2267

return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

227

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2311

struct npcm8xx_gpio *bank = gpiochip_get_data(chip);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2313

return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2314

bank->pinctrl_id, bank->chip.gc.base,

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2315

bank->chip.gc.ngpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

233

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

234

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

237

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

238

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

241

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

242

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

245

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

248

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

255

npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

258

npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

267

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

271

iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

276

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

280

iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

285

struct npcm8xx_gpio *bank =

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

289

iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS);

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1015

const struct wpcm450_bank *bank = gpio->bank;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1018

0, bank->base, bank->length);

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

102

const struct wpcm450_bank *bank = gpio->bank;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1039

const struct wpcm450_bank *bank;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

105

if (hwirq < bank->first_irq_gpio)

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1056

bank = &wpcm450_banks[reg];

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1057

gpio->bank = bank;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1059

dat = pctrl->gpio_base + bank->datain;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1060

if (bank->dataout) {

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1061

set = pctrl->gpio_base + bank->dataout;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1062

dirout = pctrl->gpio_base + bank->cfg0;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

108

if (hwirq - bank->first_irq_gpio >= bank->num_irqs)

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

1080

gpio->chip.gc.ngpio = bank->length;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

111

return hwirq - bank->first_irq_gpio + bank->first_irq_bit;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

116

const struct wpcm450_bank *bank = gpio->bank;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

118

if (bitnum < bank->first_irq_bit)

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

121

if (bitnum - bank->first_irq_bit > bank->num_irqs)

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

124

return bitnum - bank->first_irq_bit + bank->first_irq_gpio;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

197

void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

317

ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

53

const struct wpcm450_bank *bank;

drivers/pinctrl/pinctrl-amd.c

199

unsigned int bank, i, pin_num;

drivers/pinctrl/pinctrl-amd.c

220

for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {

drivers/pinctrl/pinctrl-amd.c

224

switch (bank) {

drivers/pinctrl/pinctrl-amd.c

245

seq_printf(s, "GPIO bank%d\n", bank);

drivers/pinctrl/pinctrl-at91-pio4.c

101

unsigned int bank;

drivers/pinctrl/pinctrl-at91-pio4.c

1158

unsigned int bank = ATMEL_PIO_BANK(i);

drivers/pinctrl/pinctrl-at91-pio4.c

1167

atmel_pioctrl->pins[i]->bank = bank;

drivers/pinctrl/pinctrl-at91-pio4.c

1173

bank + 'A', line);

drivers/pinctrl/pinctrl-at91-pio4.c

1180

dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);

drivers/pinctrl/pinctrl-at91-pio4.c

162

unsigned int bank, unsigned int reg)

drivers/pinctrl/pinctrl-at91-pio4.c

165

+ ATMEL_PIO_BANK_OFFSET * bank + reg);

drivers/pinctrl/pinctrl-at91-pio4.c

169

unsigned int bank, unsigned int reg,

drivers/pinctrl/pinctrl-at91-pio4.c

173

+ ATMEL_PIO_BANK_OFFSET * bank + reg);

drivers/pinctrl/pinctrl-at91-pio4.c

190

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,

drivers/pinctrl/pinctrl-at91-pio4.c

192

reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);

drivers/pinctrl/pinctrl-at91-pio4.c

221

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);

drivers/pinctrl/pinctrl-at91-pio4.c

231

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,

drivers/pinctrl/pinctrl-at91-pio4.c

240

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,

drivers/pinctrl/pinctrl-at91-pio4.c

247

int bank = ATMEL_PIO_BANK(d->hwirq);

drivers/pinctrl/pinctrl-at91-pio4.c

251

irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);

drivers/pinctrl/pinctrl-at91-pio4.c

254

atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);

drivers/pinctrl/pinctrl-at91-pio4.c

256

atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));

drivers/pinctrl/pinctrl-at91-pio4.c

283

int n, bank = -1;

drivers/pinctrl/pinctrl-at91-pio4.c

288

bank = n;

drivers/pinctrl/pinctrl-at91-pio4.c

293

if (bank < 0) {

drivers/pinctrl/pinctrl-at91-pio4.c

302

isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,

drivers/pinctrl/pinctrl-at91-pio4.c

304

isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,

drivers/pinctrl/pinctrl-at91-pio4.c

312

bank * ATMEL_PIO_NPINS_PER_BANK + n));

drivers/pinctrl/pinctrl-at91-pio4.c

325

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,

drivers/pinctrl/pinctrl-at91-pio4.c

327

reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);

drivers/pinctrl/pinctrl-at91-pio4.c

329

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);

drivers/pinctrl/pinctrl-at91-pio4.c

340

reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);

drivers/pinctrl/pinctrl-at91-pio4.c

349

unsigned int bank;

drivers/pinctrl/pinctrl-at91-pio4.c

353

for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {

drivers/pinctrl/pinctrl-at91-pio4.c

354

unsigned int word = bank;

drivers/pinctrl/pinctrl-at91-pio4.c

359

word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);

drivers/pinctrl/pinctrl-at91-pio4.c

360

offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;

drivers/pinctrl/pinctrl-at91-pio4.c

365

reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);

drivers/pinctrl/pinctrl-at91-pio4.c

380

atmel_gpio_write(atmel_pioctrl, pin->bank,

drivers/pinctrl/pinctrl-at91-pio4.c

384

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,

drivers/pinctrl/pinctrl-at91-pio4.c

386

reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);

drivers/pinctrl/pinctrl-at91-pio4.c

388

atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);

drivers/pinctrl/pinctrl-at91-pio4.c

398

atmel_gpio_write(atmel_pioctrl, pin->bank,

drivers/pinctrl/pinctrl-at91-pio4.c

409

unsigned int bank;

drivers/pinctrl/pinctrl-at91-pio4.c

411

for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {

drivers/pinctrl/pinctrl-at91-pio4.c

413

unsigned int word = bank;

drivers/pinctrl/pinctrl-at91-pio4.c

420

word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);

drivers/pinctrl/pinctrl-at91-pio4.c

426

atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);

drivers/pinctrl/pinctrl-at91-pio4.c

429

atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);

drivers/pinctrl/pinctrl-at91-pio4.c

456

unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;

drivers/pinctrl/pinctrl-at91-pio4.c

459

+ bank * ATMEL_PIO_BANK_OFFSET;

drivers/pinctrl/pinctrl-at91-pio4.c

472

unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;

drivers/pinctrl/pinctrl-at91-pio4.c

475

+ bank * ATMEL_PIO_BANK_OFFSET;

drivers/pinctrl/pinctrl-at91-pio4.c

807

unsigned int bank, pin, pin_id = grp->pin;

drivers/pinctrl/pinctrl-at91-pio4.c

867

bank = ATMEL_PIO_BANK(pin_id);

drivers/pinctrl/pinctrl-at91-pio4.c

873

bank * ATMEL_PIO_BANK_OFFSET +

drivers/pinctrl/pinctrl-at91-pio4.c

877

bank * ATMEL_PIO_BANK_OFFSET +

drivers/pinctrl/pinctrl-at91.c

1231

pin->bank = be32_to_cpu(*list++);

drivers/pinctrl/pinctrl-at91.c

1233

grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;

drivers/pinctrl/pinctrl-at91.c

141

uint32_t bank;

drivers/pinctrl/pinctrl-at91.c

361

unsigned int bank)

drivers/pinctrl/pinctrl-at91.c

363

if (!gpio_chips[bank])

drivers/pinctrl/pinctrl-at91.c

366

return gpio_chips[bank]->regbase;

drivers/pinctrl/pinctrl-at91.c

780

pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);

drivers/pinctrl/pinctrl-at91.c

783

pin->bank + 'A', pin->pin, pin->conf);

drivers/pinctrl/pinctrl-at91.c

793

if (pin->bank >= gpio_banks) {

drivers/pinctrl/pinctrl-at91.c

795

name, index, pin->bank, gpio_banks);

drivers/pinctrl/pinctrl-at91.c

799

if (!gpio_chips[pin->bank]) {

drivers/pinctrl/pinctrl-at91.c

801

name, index, pin->bank);

drivers/pinctrl/pinctrl-at91.c

822

if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {

drivers/pinctrl/pinctrl-at91.c

824

name, index, mux, pin->bank + 'A', pin->pin);

drivers/pinctrl/pinctrl-at91.c

868

pio = pin_to_controller(info, pin->bank);

drivers/pinctrl/pinctrl-equilibrium.c

253

.sz = gctrl->bank->nr_pins / 8,

drivers/pinctrl/pinctrl-equilibrium.c

281

struct eqbr_pin_bank *bank;

drivers/pinctrl/pinctrl-equilibrium.c

285

bank = &pctl->pin_banks[i];

drivers/pinctrl/pinctrl-equilibrium.c

286

if (pin >= bank->pin_base &&

drivers/pinctrl/pinctrl-equilibrium.c

287

(pin - bank->pin_base) < bank->nr_pins)

drivers/pinctrl/pinctrl-equilibrium.c

288

return bank;

drivers/pinctrl/pinctrl-equilibrium.c

305

struct eqbr_pin_bank *bank;

drivers/pinctrl/pinctrl-equilibrium.c

310

bank = find_pinbank_via_pin(pctl, pin);

drivers/pinctrl/pinctrl-equilibrium.c

311

if (!bank) {

drivers/pinctrl/pinctrl-equilibrium.c

315

mem = bank->membase;

drivers/pinctrl/pinctrl-equilibrium.c

316

offset = pin - bank->pin_base;

drivers/pinctrl/pinctrl-equilibrium.c

318

if (!(bank->aval_pinmap & BIT(offset))) {

drivers/pinctrl/pinctrl-equilibrium.c

321

pin, bank->pin_base, bank->aval_pinmap);

drivers/pinctrl/pinctrl-equilibrium.c

383

struct eqbr_pin_bank *bank)

drivers/pinctrl/pinctrl-equilibrium.c

388

if (pctl->gpio_ctrls[i].bank == bank)

drivers/pinctrl/pinctrl-equilibrium.c

401

struct eqbr_pin_bank *bank;

drivers/pinctrl/pinctrl-equilibrium.c

407

bank = find_pinbank_via_pin(pctl, pin);

drivers/pinctrl/pinctrl-equilibrium.c

408

if (!bank) {

drivers/pinctrl/pinctrl-equilibrium.c

412

mem = bank->membase;

drivers/pinctrl/pinctrl-equilibrium.c

413

offset = pin - bank->pin_base;

drivers/pinctrl/pinctrl-equilibrium.c

415

if (!(bank->aval_pinmap & BIT(offset))) {

drivers/pinctrl/pinctrl-equilibrium.c

418

pin, bank->pin_base, bank->aval_pinmap);

drivers/pinctrl/pinctrl-equilibrium.c

440

gctrl = get_gpio_ctrls_via_bank(pctl, bank);

drivers/pinctrl/pinctrl-equilibrium.c

443

bank->pin_base, pin);

drivers/pinctrl/pinctrl-equilibrium.c

465

struct eqbr_pin_bank *bank;

drivers/pinctrl/pinctrl-equilibrium.c

477

bank = find_pinbank_via_pin(pctl, pin);

drivers/pinctrl/pinctrl-equilibrium.c

478

if (!bank) {

drivers/pinctrl/pinctrl-equilibrium.c

483

mem = bank->membase;

drivers/pinctrl/pinctrl-equilibrium.c

484

offset = pin - bank->pin_base;

drivers/pinctrl/pinctrl-equilibrium.c

509

gctrl = get_gpio_ctrls_via_bank(pctl, bank);

drivers/pinctrl/pinctrl-equilibrium.c

512

bank->pin_base, pin);

drivers/pinctrl/pinctrl-equilibrium.c

840

struct eqbr_pin_bank *bank, unsigned int id)

drivers/pinctrl/pinctrl-equilibrium.c

846

bank->membase = drvdata->membase + id * PAD_REG_OFF;

drivers/pinctrl/pinctrl-equilibrium.c

854

bank->pin_base = spec.args[1];

drivers/pinctrl/pinctrl-equilibrium.c

855

bank->nr_pins = spec.args[2];

drivers/pinctrl/pinctrl-equilibrium.c

858

bank->aval_pinmap = readl(bank->membase + REG_AVAIL);

drivers/pinctrl/pinctrl-equilibrium.c

859

bank->id = id;

drivers/pinctrl/pinctrl-equilibrium.c

862

id, bank->membase, bank->pin_base,

drivers/pinctrl/pinctrl-equilibrium.c

863

bank->nr_pins, bank->aval_pinmap);

drivers/pinctrl/pinctrl-equilibrium.c

908

gctrls[i].bank = banks + i;

drivers/pinctrl/pinctrl-equilibrium.h

101

struct eqbr_pin_bank *bank;

drivers/pinctrl/pinctrl-eyeq5.c

202

enum eq5p_bank bank, enum eq5p_regs reg,

drivers/pinctrl/pinctrl-eyeq5.c

205

void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];

drivers/pinctrl/pinctrl-eyeq5.c

211

enum eq5p_bank bank, enum eq5p_regs reg, int offset)

drivers/pinctrl/pinctrl-eyeq5.c

213

u32 val = readl(pctrl->base + eq5p_regs[bank][reg]);

drivers/pinctrl/pinctrl-eyeq5.c

264

enum eq5p_bank bank = eq5p_pin_to_bank(pin);

drivers/pinctrl/pinctrl-eyeq5.c

268

pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);

drivers/pinctrl/pinctrl-eyeq5.c

269

pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);

drivers/pinctrl/pinctrl-eyeq5.c

284

val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);

drivers/pinctrl/pinctrl-eyeq5.c

287

val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);

drivers/pinctrl/pinctrl-eyeq5.c

306

enum eq5p_bank bank = eq5p_pin_to_bank(pin);

drivers/pinctrl/pinctrl-eyeq5.c

317

if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {

drivers/pinctrl/pinctrl-eyeq5.c

348

pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);

drivers/pinctrl/pinctrl-eyeq5.c

349

pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);

drivers/pinctrl/pinctrl-eyeq5.c

406

enum eq5p_bank bank = eq5p_pin_to_bank(pin);

drivers/pinctrl/pinctrl-eyeq5.c

413

eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val);

drivers/pinctrl/pinctrl-eyeq5.c

439

enum eq5p_bank bank = eq5p_pin_to_bank(pin);

drivers/pinctrl/pinctrl-eyeq5.c

459

eq5p_update_bits(pctrl, bank, reg, mask, val);

drivers/pinctrl/pinctrl-eyeq5.c

469

enum eq5p_bank bank = eq5p_pin_to_bank(pin);

drivers/pinctrl/pinctrl-eyeq5.c

482

eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);

drivers/pinctrl/pinctrl-eyeq5.c

483

eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);

drivers/pinctrl/pinctrl-eyeq5.c

493

eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val);

drivers/pinctrl/pinctrl-eyeq5.c

494

eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);

drivers/pinctrl/pinctrl-eyeq5.c

504

eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);

drivers/pinctrl/pinctrl-eyeq5.c

505

eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val);

drivers/pinctrl/pinctrl-falcon.c

102

pad_count[bank] = len;

drivers/pinctrl/pinctrl-falcon.c

434

const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);

drivers/pinctrl/pinctrl-falcon.c

443

if (!bank || *bank >= PORTS)

drivers/pinctrl/pinctrl-falcon.c

454

falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);

drivers/pinctrl/pinctrl-falcon.c

456

if (IS_ERR(falcon_info.clk[*bank])) {

drivers/pinctrl/pinctrl-falcon.c

459

return PTR_ERR(falcon_info.clk[*bank]);

drivers/pinctrl/pinctrl-falcon.c

461

falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,

drivers/pinctrl/pinctrl-falcon.c

463

if (IS_ERR(falcon_info.membase[*bank])) {

drivers/pinctrl/pinctrl-falcon.c

465

return PTR_ERR(falcon_info.membase[*bank]);

drivers/pinctrl/pinctrl-falcon.c

468

avail = pad_r32(falcon_info.membase[*bank],

drivers/pinctrl/pinctrl-falcon.c

471

lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);

drivers/pinctrl/pinctrl-falcon.c

473

clk_enable(falcon_info.clk[*bank]);

drivers/pinctrl/pinctrl-falcon.c

93

static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)

drivers/pinctrl/pinctrl-falcon.c

95

int base = bank * PINS;

drivers/pinctrl/pinctrl-ingenic.c

4418

unsigned int bank;

drivers/pinctrl/pinctrl-ingenic.c

4421

err = fwnode_property_read_u32(fwnode, "reg", &bank);

drivers/pinctrl/pinctrl-ingenic.c

4434

jzgc->reg_base = bank * jzpc->info->reg_offset;

drivers/pinctrl/pinctrl-ingenic.c

4436

jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);

drivers/pinctrl/pinctrl-ingenic.c

4444

jzgc->gc.base = bank * 32;

drivers/pinctrl/pinctrl-microchip-sgpio.c

355

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

357

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

365

val = bank->is_input;

drivers/pinctrl/pinctrl-microchip-sgpio.c

369

val = !bank->is_input;

drivers/pinctrl/pinctrl-microchip-sgpio.c

373

if (bank->is_input)

drivers/pinctrl/pinctrl-microchip-sgpio.c

390

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

391

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

404

if (bank->is_input)

drivers/pinctrl/pinctrl-microchip-sgpio.c

456

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

458

return (input == bank->is_input) ? 0 : -EINVAL;

drivers/pinctrl/pinctrl-microchip-sgpio.c

465

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

466

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

491

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

493

return bank->pctl_desc.npins;

drivers/pinctrl/pinctrl-microchip-sgpio.c

499

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

501

return bank->pctl_desc.pins[group].name;

drivers/pinctrl/pinctrl-microchip-sgpio.c

509

struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);

drivers/pinctrl/pinctrl-microchip-sgpio.c

511

*pins = &bank->pctl_desc.pins[group].number;

drivers/pinctrl/pinctrl-microchip-sgpio.c

527

struct sgpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-microchip-sgpio.c

530

return bank->is_input ? 0 : -EINVAL;

drivers/pinctrl/pinctrl-microchip-sgpio.c

536

struct sgpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-microchip-sgpio.c

537

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

541

if (bank->is_input)

drivers/pinctrl/pinctrl-microchip-sgpio.c

551

struct sgpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-microchip-sgpio.c

553

return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;

drivers/pinctrl/pinctrl-microchip-sgpio.c

564

struct sgpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-microchip-sgpio.c

565

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

570

return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);

drivers/pinctrl/pinctrl-microchip-sgpio.c

577

struct sgpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-microchip-sgpio.c

578

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

643

struct sgpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-microchip-sgpio.c

649

sgpio_pin_to_addr(bank->priv, gpio, &addr);

drivers/pinctrl/pinctrl-microchip-sgpio.c

651

spin_lock_irqsave(&bank->priv->lock, flags);

drivers/pinctrl/pinctrl-microchip-sgpio.c

654

ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);

drivers/pinctrl/pinctrl-microchip-sgpio.c

655

sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);

drivers/pinctrl/pinctrl-microchip-sgpio.c

658

sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,

drivers/pinctrl/pinctrl-microchip-sgpio.c

660

sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,

drivers/pinctrl/pinctrl-microchip-sgpio.c

664

sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,

drivers/pinctrl/pinctrl-microchip-sgpio.c

668

sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);

drivers/pinctrl/pinctrl-microchip-sgpio.c

670

spin_unlock_irqrestore(&bank->priv->lock, flags);

drivers/pinctrl/pinctrl-microchip-sgpio.c

678

struct sgpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-microchip-sgpio.c

682

sgpio_pin_to_addr(bank->priv, gpio, &addr);

drivers/pinctrl/pinctrl-microchip-sgpio.c

685

sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);

drivers/pinctrl/pinctrl-microchip-sgpio.c

687

sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));

drivers/pinctrl/pinctrl-microchip-sgpio.c

709

struct sgpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-microchip-sgpio.c

713

sgpio_pin_to_addr(bank->priv, gpio, &addr);

drivers/pinctrl/pinctrl-microchip-sgpio.c

715

sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);

drivers/pinctrl/pinctrl-microchip-sgpio.c

762

struct sgpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-microchip-sgpio.c

763

struct sgpio_priv *priv = bank->priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

791

struct sgpio_bank *bank;

drivers/pinctrl/pinctrl-microchip-sgpio.c

797

bank = (bankno == 0) ? &priv->in : &priv->out;

drivers/pinctrl/pinctrl-microchip-sgpio.c

798

bank->priv = priv;

drivers/pinctrl/pinctrl-microchip-sgpio.c

813

pctl_desc = &bank->pctl_desc;

drivers/pinctrl/pinctrl-microchip-sgpio.c

816

bank->is_input ? "in" : "out");

drivers/pinctrl/pinctrl-microchip-sgpio.c

840

bank->is_input ? 'I' : 'O',

drivers/pinctrl/pinctrl-microchip-sgpio.c

846

pctldev = devm_pinctrl_register(dev, pctl_desc, bank);

drivers/pinctrl/pinctrl-microchip-sgpio.c

850

gc = &bank->gpio;

drivers/pinctrl/pinctrl-microchip-sgpio.c

866

gc->can_sleep = !bank->is_input;

drivers/pinctrl/pinctrl-microchip-sgpio.c

868

if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {

drivers/pinctrl/pinctrl-microchip-sgpio.c

895

ret = devm_gpiochip_add_data(dev, gc, bank);

drivers/pinctrl/pinctrl-pic32.c

1801

struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);

drivers/pinctrl/pinctrl-pic32.c

1802

u32 mask = BIT(offset - bank->gpio_chip.base);

drivers/pinctrl/pinctrl-pic32.c

1805

offset, bank->gpio_chip.base, mask);

drivers/pinctrl/pinctrl-pic32.c

1807

writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));

drivers/pinctrl/pinctrl-pic32.c

1815

struct pic32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pic32.c

1818

writel(mask, bank->reg_base + PIC32_SET(TRIS_REG));

drivers/pinctrl/pinctrl-pic32.c

1825

struct pic32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pic32.c

1827

return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));

drivers/pinctrl/pinctrl-pic32.c

1833

struct pic32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pic32.c

1837

writel(mask, bank->reg_base + PIC32_SET(PORT_REG));

drivers/pinctrl/pinctrl-pic32.c

1839

writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));

drivers/pinctrl/pinctrl-pic32.c

1847

struct pic32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pic32.c

1851

writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG));

drivers/pinctrl/pinctrl-pic32.c

1883

struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);

drivers/pinctrl/pinctrl-pic32.c

1885

u32 mask = BIT(pin - bank->gpio_chip.base);

drivers/pinctrl/pinctrl-pic32.c

1890

arg = !!(readl(bank->reg_base + CNPU_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1893

arg = !!(readl(bank->reg_base + CNPD_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1896

arg = !(readl(bank->reg_base + ANSEL_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1899

arg = !!(readl(bank->reg_base + ANSEL_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1902

arg = !!(readl(bank->reg_base + ODCU_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1905

arg = !!(readl(bank->reg_base + TRIS_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1908

arg = !(readl(bank->reg_base + TRIS_REG) & mask);

drivers/pinctrl/pinctrl-pic32.c

1924

struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);

drivers/pinctrl/pinctrl-pic32.c

1928

u32 offset = pin - bank->gpio_chip.base;

drivers/pinctrl/pinctrl-pic32.c

1932

pin, bank->gpio_chip.base, mask);

drivers/pinctrl/pinctrl-pic32.c

1941

writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));

drivers/pinctrl/pinctrl-pic32.c

1945

writel(mask, bank->reg_base + PIC32_SET(CNPD_REG));

drivers/pinctrl/pinctrl-pic32.c

1949

writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));

drivers/pinctrl/pinctrl-pic32.c

1953

writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG));

drivers/pinctrl/pinctrl-pic32.c

1957

writel(mask, bank->reg_base + PIC32_SET(ODCU_REG));

drivers/pinctrl/pinctrl-pic32.c

1960

pic32_gpio_direction_input(&bank->gpio_chip, offset);

drivers/pinctrl/pinctrl-pic32.c

1963

pic32_gpio_direction_output(&bank->gpio_chip,

drivers/pinctrl/pinctrl-pic32.c

1992

struct pic32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pic32.c

1994

if (readl(bank->reg_base + TRIS_REG) & BIT(offset))

drivers/pinctrl/pinctrl-pic32.c

2002

struct pic32_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pic32.c

2004

writel(0, bank->reg_base + CNF_REG);

drivers/pinctrl/pinctrl-pic32.c

2009

struct pic32_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pic32.c

2011

writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2012

gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data));

drivers/pinctrl/pinctrl-pic32.c

2017

struct pic32_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pic32.c

2019

gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data));

drivers/pinctrl/pinctrl-pic32.c

2020

writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2035

struct pic32_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pic32.c

2041

writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));

drivers/pinctrl/pinctrl-pic32.c

2043

writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG));

drivers/pinctrl/pinctrl-pic32.c

2045

writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2049

writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG));

drivers/pinctrl/pinctrl-pic32.c

2051

writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));

drivers/pinctrl/pinctrl-pic32.c

2053

writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2057

writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));

drivers/pinctrl/pinctrl-pic32.c

2059

writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));

drivers/pinctrl/pinctrl-pic32.c

2061

writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2074

struct pic32_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-pic32.c

2079

cnen_rise = readl(bank->reg_base + CNEN_REG);

drivers/pinctrl/pinctrl-pic32.c

2080

cnne_fall = readl(bank->reg_base + CNNE_REG);

drivers/pinctrl/pinctrl-pic32.c

2095

struct pic32_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-pic32.c

2103

stat = readl(bank->reg_base + CNF_REG);

drivers/pinctrl/pinctrl-pic32.c

2146

struct pic32_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pic32.c

2148

seq_printf(p, "GPIO%d", bank->instance);

drivers/pinctrl/pinctrl-pic32.c

2217

struct pic32_gpio_bank *bank;

drivers/pinctrl/pinctrl-pic32.c

2232

bank = &pic32_gpio_banks[id];

drivers/pinctrl/pinctrl-pic32.c

2234

bank->reg_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pinctrl/pinctrl-pic32.c

2235

if (IS_ERR(bank->reg_base))

drivers/pinctrl/pinctrl-pic32.c

2236

return PTR_ERR(bank->reg_base);

drivers/pinctrl/pinctrl-pic32.c

2242

bank->clk = devm_clk_get(&pdev->dev, NULL);

drivers/pinctrl/pinctrl-pic32.c

2243

if (IS_ERR(bank->clk)) {

drivers/pinctrl/pinctrl-pic32.c

2244

ret = PTR_ERR(bank->clk);

drivers/pinctrl/pinctrl-pic32.c

2249

ret = clk_prepare_enable(bank->clk);

drivers/pinctrl/pinctrl-pic32.c

2255

bank->gpio_chip.parent = &pdev->dev;

drivers/pinctrl/pinctrl-pic32.c

2257

girq = &bank->gpio_chip.irq;

drivers/pinctrl/pinctrl-pic32.c

2268

ret = gpiochip_add_data(&bank->gpio_chip, bank);

drivers/pinctrl/pinctrl-pic32.c

40

#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)

drivers/pinctrl/pinctrl-pistachio.c

1171

struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pistachio.c

1173

if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))

drivers/pinctrl/pinctrl-pistachio.c

1181

struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pistachio.c

1184

if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))

drivers/pinctrl/pinctrl-pistachio.c

1189

return !!(gpio_readl(bank, reg) & BIT(offset));

drivers/pinctrl/pinctrl-pistachio.c

1195

struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pistachio.c

1197

gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);

drivers/pinctrl/pinctrl-pistachio.c

1205

struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pistachio.c

1207

gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);

drivers/pinctrl/pinctrl-pistachio.c

1208

gpio_enable(bank, offset);

drivers/pinctrl/pinctrl-pistachio.c

1216

struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-pistachio.c

1219

gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);

drivers/pinctrl/pinctrl-pistachio.c

1220

gpio_enable(bank, offset);

drivers/pinctrl/pinctrl-pistachio.c

1227

struct pistachio_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pistachio.c

1229

gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);

drivers/pinctrl/pinctrl-pistachio.c

1234

struct pistachio_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pistachio.c

1236

gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);

drivers/pinctrl/pinctrl-pistachio.c

1237

gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data));

drivers/pinctrl/pinctrl-pistachio.c

1242

struct pistachio_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pistachio.c

1244

gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data));

drivers/pinctrl/pinctrl-pistachio.c

1245

gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);

drivers/pinctrl/pinctrl-pistachio.c

1260

struct pistachio_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pistachio.c

1264

gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);

drivers/pinctrl/pinctrl-pistachio.c

1265

gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1267

gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1271

gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);

drivers/pinctrl/pinctrl-pistachio.c

1272

gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1274

gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1278

gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1280

gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1284

gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);

drivers/pinctrl/pinctrl-pistachio.c

1285

gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1289

gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);

drivers/pinctrl/pinctrl-pistachio.c

1290

gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,

drivers/pinctrl/pinctrl-pistachio.c

1308

struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-pistachio.c

1314

pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &

drivers/pinctrl/pinctrl-pistachio.c

1315

gpio_readl(bank, GPIO_INTERRUPT_EN);

drivers/pinctrl/pinctrl-pistachio.c

1352

struct pistachio_gpio_bank *bank = irqd_to_bank(data);

drivers/pinctrl/pinctrl-pistachio.c

1354

seq_printf(p, "GPIO%d", bank->instance);

drivers/pinctrl/pinctrl-pistachio.c

1370

struct pistachio_gpio_bank *bank;

drivers/pinctrl/pinctrl-pistachio.c

1403

bank = &pctl->gpio_banks[i];

drivers/pinctrl/pinctrl-pistachio.c

1404

bank->pctl = pctl;

drivers/pinctrl/pinctrl-pistachio.c

1405

bank->base = pctl->base + GPIO_BANK_BASE(i);

drivers/pinctrl/pinctrl-pistachio.c

1407

bank->gpio_chip.parent = pctl->dev;

drivers/pinctrl/pinctrl-pistachio.c

1408

bank->gpio_chip.fwnode = child;

drivers/pinctrl/pinctrl-pistachio.c

1410

girq = &bank->gpio_chip.irq;

drivers/pinctrl/pinctrl-pistachio.c

1425

ret = gpiochip_add_data(&bank->gpio_chip, bank);

drivers/pinctrl/pinctrl-pistachio.c

1432

ret = gpiochip_add_pin_range(&bank->gpio_chip,

drivers/pinctrl/pinctrl-pistachio.c

1434

bank->pin_base, bank->npins);

drivers/pinctrl/pinctrl-pistachio.c

1438

gpiochip_remove(&bank->gpio_chip);

drivers/pinctrl/pinctrl-pistachio.c

1446

bank = &pctl->gpio_banks[i - 1];

drivers/pinctrl/pinctrl-pistachio.c

1447

gpiochip_remove(&bank->gpio_chip);

drivers/pinctrl/pinctrl-pistachio.c

58

#define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))

drivers/pinctrl/pinctrl-pistachio.c

847

static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)

drivers/pinctrl/pinctrl-pistachio.c

849

return readl(bank->base + reg);

drivers/pinctrl/pinctrl-pistachio.c

852

static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,

drivers/pinctrl/pinctrl-pistachio.c

855

writel(val, bank->base + reg);

drivers/pinctrl/pinctrl-pistachio.c

858

static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,

drivers/pinctrl/pinctrl-pistachio.c

865

gpio_writel(bank, (0x10000 | val) << bit, reg);

drivers/pinctrl/pinctrl-pistachio.c

868

static inline void gpio_enable(struct pistachio_gpio_bank *bank,

drivers/pinctrl/pinctrl-pistachio.c

871

gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);

drivers/pinctrl/pinctrl-pistachio.c

874

static inline void gpio_disable(struct pistachio_gpio_bank *bank,

drivers/pinctrl/pinctrl-pistachio.c

877

gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);

drivers/pinctrl/pinctrl-rockchip.c

1122

static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,

drivers/pinctrl/pinctrl-rockchip.c

1125

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1132

if ((data->bank_num == bank->bank_num) &&

drivers/pinctrl/pinctrl-rockchip.c

1147

static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)

drivers/pinctrl/pinctrl-rockchip.c

1149

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1160

if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {

drivers/pinctrl/pinctrl-rockchip.c

1165

if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)

drivers/pinctrl/pinctrl-rockchip.c

1168

if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)

drivers/pinctrl/pinctrl-rockchip.c

1170

else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)

drivers/pinctrl/pinctrl-rockchip.c

1176

if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

1178

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

1183

mux_type = bank->iomux[iomux_num].type;

drivers/pinctrl/pinctrl-rockchip.c

1184

reg = bank->iomux[iomux_num].offset;

drivers/pinctrl/pinctrl-rockchip.c

1200

if (bank->recalced_mask & BIT(pin))

drivers/pinctrl/pinctrl-rockchip.c

1201

rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);

drivers/pinctrl/pinctrl-rockchip.c

1204

if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))

drivers/pinctrl/pinctrl-rockchip.c

1209

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1224

} else if (bank->bank_num > 0) {

drivers/pinctrl/pinctrl-rockchip.c

1236

static int rockchip_verify_mux(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1239

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1246

if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {

drivers/pinctrl/pinctrl-rockchip.c

1251

if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {

drivers/pinctrl/pinctrl-rockchip.c

1274

static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)

drivers/pinctrl/pinctrl-rockchip.c

1276

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1285

ret = rockchip_verify_mux(bank, pin, mux);

drivers/pinctrl/pinctrl-rockchip.c

1289

if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)

drivers/pinctrl/pinctrl-rockchip.c

1292

dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);

drivers/pinctrl/pinctrl-rockchip.c

1294

if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)

drivers/pinctrl/pinctrl-rockchip.c

1296

else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)

drivers/pinctrl/pinctrl-rockchip.c

1302

if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

1304

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

1309

mux_type = bank->iomux[iomux_num].type;

drivers/pinctrl/pinctrl-rockchip.c

1310

reg = bank->iomux[iomux_num].offset;

drivers/pinctrl/pinctrl-rockchip.c

1326

if (bank->recalced_mask & BIT(pin))

drivers/pinctrl/pinctrl-rockchip.c

1327

rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);

drivers/pinctrl/pinctrl-rockchip.c

1330

if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))

drivers/pinctrl/pinctrl-rockchip.c

1335

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1366

} else if (bank->bank_num > 0) {

drivers/pinctrl/pinctrl-rockchip.c

1374

if (bank->route_mask & BIT(pin)) {

drivers/pinctrl/pinctrl-rockchip.c

1375

if (rockchip_get_mux_route(bank, pin, mux, &route_location,

drivers/pinctrl/pinctrl-rockchip.c

1409

static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1413

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1416

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1425

*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1441

static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1445

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1448

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1457

*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1473

static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1478

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1481

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1489

*reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1504

static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1508

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1511

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1519

*reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1535

static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1539

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1542

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1551

*reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1567

static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1572

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1575

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1583

*reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1598

static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1602

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1605

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1619

*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1635

static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1639

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1642

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1657

*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1673

static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1678

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1681

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1696

*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1708

static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1712

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1717

*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1728

static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1732

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1736

*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1746

static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1750

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1754

*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1768

static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1772

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1775

if (bank->bank_num == 0 && pin_num < 12) {

drivers/pinctrl/pinctrl-rockchip.c

1777

: bank->regmap_pull;

drivers/pinctrl/pinctrl-rockchip.c

1789

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1805

static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1809

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1812

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1825

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1841

static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1845

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1848

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1861

*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1873

static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1877

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1881

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1892

static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1896

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1900

*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1911

static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1915

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1919

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1930

static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1934

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1938

*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1950

static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1954

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1957

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

1970

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

1983

static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

1987

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

1990

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

2003

*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

2017

static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2021

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2024

if ((bank->bank_num == 0) || (bank->bank_num == 1)) {

drivers/pinctrl/pinctrl-rockchip.c

2028

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

2039

*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

2049

static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2053

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2057

if ((bank->bank_num == 0) || (bank->bank_num == 1))

drivers/pinctrl/pinctrl-rockchip.c

2062

*reg = bank->drv[drv_num].offset;

drivers/pinctrl/pinctrl-rockchip.c

2063

if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||

drivers/pinctrl/pinctrl-rockchip.c

2064

(bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))

drivers/pinctrl/pinctrl-rockchip.c

2081

static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2085

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2088

switch (bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

2145

dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);

drivers/pinctrl/pinctrl-rockchip.c

2166

static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2170

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2173

switch (bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

2230

dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);

drivers/pinctrl/pinctrl-rockchip.c

2251

static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2256

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2259

switch (bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

2316

dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);

drivers/pinctrl/pinctrl-rockchip.c

2336

static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2340

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2344

if (bank->bank_num == 0)

drivers/pinctrl/pinctrl-rockchip.c

2346

else if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

2348

else if (bank->bank_num == 2)

drivers/pinctrl/pinctrl-rockchip.c

2350

else if (bank->bank_num == 3)

drivers/pinctrl/pinctrl-rockchip.c

2352

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

2355

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2372

static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2376

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2380

if (bank->bank_num == 0)

drivers/pinctrl/pinctrl-rockchip.c

2382

else if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

2384

else if (bank->bank_num == 2)

drivers/pinctrl/pinctrl-rockchip.c

2386

else if (bank->bank_num == 3)

drivers/pinctrl/pinctrl-rockchip.c

2388

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

2391

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2408

static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2413

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2417

if (bank->bank_num == 0)

drivers/pinctrl/pinctrl-rockchip.c

2419

else if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

2421

else if (bank->bank_num == 2)

drivers/pinctrl/pinctrl-rockchip.c

2423

else if (bank->bank_num == 3)

drivers/pinctrl/pinctrl-rockchip.c

2425

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

2428

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2445

static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2449

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2452

switch (bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

2474

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2493

static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2497

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2500

switch (bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

2522

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2541

static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2546

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2549

switch (bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

2571

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2588

static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2592

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2594

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

2597

*reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

2605

*reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

2621

static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2625

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2628

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

2638

*reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

2659

static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2663

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2667

if (bank->bank_num == 0 && pin_num < 12)

drivers/pinctrl/pinctrl-rockchip.c

2669

else if (bank->bank_num == 0)

drivers/pinctrl/pinctrl-rockchip.c

2671

else if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

2673

else if (bank->bank_num == 2)

drivers/pinctrl/pinctrl-rockchip.c

2675

else if (bank->bank_num == 3)

drivers/pinctrl/pinctrl-rockchip.c

2677

else if (bank->bank_num == 4 && pin_num < 16)

drivers/pinctrl/pinctrl-rockchip.c

2679

else if (bank->bank_num == 4 && pin_num < 24)

drivers/pinctrl/pinctrl-rockchip.c

2681

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

2684

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2704

static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2708

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2712

if (bank->bank_num == 0 && pin_num < 12)

drivers/pinctrl/pinctrl-rockchip.c

2714

else if (bank->bank_num == 0)

drivers/pinctrl/pinctrl-rockchip.c

2716

else if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

2718

else if (bank->bank_num == 2)

drivers/pinctrl/pinctrl-rockchip.c

2720

else if (bank->bank_num == 3)

drivers/pinctrl/pinctrl-rockchip.c

2722

else if (bank->bank_num == 4 && pin_num < 16)

drivers/pinctrl/pinctrl-rockchip.c

2724

else if (bank->bank_num == 4 && pin_num < 24)

drivers/pinctrl/pinctrl-rockchip.c

2726

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

2729

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2749

static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2754

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2758

if (bank->bank_num == 0 && pin_num < 12)

drivers/pinctrl/pinctrl-rockchip.c

2760

else if (bank->bank_num == 0)

drivers/pinctrl/pinctrl-rockchip.c

2762

else if (bank->bank_num == 1)

drivers/pinctrl/pinctrl-rockchip.c

2764

else if (bank->bank_num == 2)

drivers/pinctrl/pinctrl-rockchip.c

2766

else if (bank->bank_num == 3)

drivers/pinctrl/pinctrl-rockchip.c

2768

else if (bank->bank_num == 4 && pin_num < 16)

drivers/pinctrl/pinctrl-rockchip.c

2770

else if (bank->bank_num == 4 && pin_num < 24)

drivers/pinctrl/pinctrl-rockchip.c

2772

else if (bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

2775

dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);

drivers/pinctrl/pinctrl-rockchip.c

2892

static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2896

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2897

u8 bank_num = bank->bank_num;

drivers/pinctrl/pinctrl-rockchip.c

2917

static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2921

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2922

u8 bank_num = bank->bank_num;

drivers/pinctrl/pinctrl-rockchip.c

2942

static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2947

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2948

u8 bank_num = bank->bank_num;

drivers/pinctrl/pinctrl-rockchip.c

2973

static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

2976

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

2983

int drv_type = bank->drv[pin_num / 8].drv_type;

drivers/pinctrl/pinctrl-rockchip.c

2985

ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);

drivers/pinctrl/pinctrl-rockchip.c

3052

static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

3055

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3062

int drv_type = bank->drv[pin_num / 8].drv_type;

drivers/pinctrl/pinctrl-rockchip.c

3065

bank->bank_num, pin_num, strength);

drivers/pinctrl/pinctrl-rockchip.c

3067

ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);

drivers/pinctrl/pinctrl-rockchip.c

3180

if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {

drivers/pinctrl/pinctrl-rockchip.c

3210

static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)

drivers/pinctrl/pinctrl-rockchip.c

3212

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3224

ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);

drivers/pinctrl/pinctrl-rockchip.c

3251

pull_type = bank->pull_type[pin_num / 8];

drivers/pinctrl/pinctrl-rockchip.c

3258

if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {

drivers/pinctrl/pinctrl-rockchip.c

3270

static int rockchip_set_pull(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

3273

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3281

dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);

drivers/pinctrl/pinctrl-rockchip.c

3287

ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);

drivers/pinctrl/pinctrl-rockchip.c

3314

pull_type = bank->pull_type[pin_num / 8];

drivers/pinctrl/pinctrl-rockchip.c

3327

if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {

drivers/pinctrl/pinctrl-rockchip.c

3357

static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

3362

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3367

*reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

3380

static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

3385

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3387

if (bank->bank_num == 0) {

drivers/pinctrl/pinctrl-rockchip.c

3393

*reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;

drivers/pinctrl/pinctrl-rockchip.c

3403

static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)

drivers/pinctrl/pinctrl-rockchip.c

3405

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3412

ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);

drivers/pinctrl/pinctrl-rockchip.c

3430

if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)

drivers/pinctrl/pinctrl-rockchip.c

3436

static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

3439

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

3448

bank->bank_num, pin_num, enable);

drivers/pinctrl/pinctrl-rockchip.c

3450

ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);

drivers/pinctrl/pinctrl-rockchip.c

3469

if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {

drivers/pinctrl/pinctrl-rockchip.c

3517

struct rockchip_pin_bank *bank;

drivers/pinctrl/pinctrl-rockchip.c

3528

bank = pin_to_bank(info, pins[cnt]);

drivers/pinctrl/pinctrl-rockchip.c

3529

ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3538

bank = pin_to_bank(info, pins[cnt]);

drivers/pinctrl/pinctrl-rockchip.c

3539

rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);

drivers/pinctrl/pinctrl-rockchip.c

3553

struct rockchip_pin_bank *bank;

drivers/pinctrl/pinctrl-rockchip.c

3555

bank = pin_to_bank(info, offset);

drivers/pinctrl/pinctrl-rockchip.c

3556

return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);

drivers/pinctrl/pinctrl-rockchip.c

3602

static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.c

3615

list_add_tail(&cfg->head, &bank->deferred_pins);

drivers/pinctrl/pinctrl-rockchip.c

3625

struct rockchip_pin_bank *bank = pin_to_bank(info, pin);

drivers/pinctrl/pinctrl-rockchip.c

3626

struct gpio_chip *gpio = &bank->gpio_chip;

drivers/pinctrl/pinctrl-rockchip.c

3642

scoped_guard(mutex, &bank->deferred_lock) {

drivers/pinctrl/pinctrl-rockchip.c

3644

return rockchip_pinconf_defer_pin(bank,

drivers/pinctrl/pinctrl-rockchip.c

3645

pin - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3652

rc = rockchip_set_pull(bank, pin - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3667

rc = rockchip_set_pull(bank, pin - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3673

rc = rockchip_set_mux(bank, pin - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3678

rc = gpio->direction_output(gpio, pin - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3684

rc = rockchip_set_mux(bank, pin - bank->pin_base,

drivers/pinctrl/pinctrl-rockchip.c

3689

rc = gpio->direction_input(gpio, pin - bank->pin_base);

drivers/pinctrl/pinctrl-rockchip.c

3698

rc = rockchip_set_drive_perpin(bank,

drivers/pinctrl/pinctrl-rockchip.c

3699

pin - bank->pin_base, arg);

drivers/pinctrl/pinctrl-rockchip.c

3707

rc = rockchip_set_schmitt(bank,

drivers/pinctrl/pinctrl-rockchip.c

3708

pin - bank->pin_base, arg);

drivers/pinctrl/pinctrl-rockchip.c

3726

struct rockchip_pin_bank *bank = pin_to_bank(info, pin);

drivers/pinctrl/pinctrl-rockchip.c

3727

struct gpio_chip *gpio = &bank->gpio_chip;

drivers/pinctrl/pinctrl-rockchip.c

3734

if (rockchip_get_pull(bank, pin - bank->pin_base) != param)

drivers/pinctrl/pinctrl-rockchip.c

3746

if (rockchip_get_pull(bank, pin - bank->pin_base) != param)

drivers/pinctrl/pinctrl-rockchip.c

3752

rc = rockchip_get_mux(bank, pin - bank->pin_base);

drivers/pinctrl/pinctrl-rockchip.c

3761

rc = gpio->get(gpio, pin - bank->pin_base);

drivers/pinctrl/pinctrl-rockchip.c

3772

rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);

drivers/pinctrl/pinctrl-rockchip.c

3782

rc = rockchip_get_schmitt(bank, pin - bank->pin_base);

drivers/pinctrl/pinctrl-rockchip.c

3830

struct rockchip_pin_bank *bank;

drivers/pinctrl/pinctrl-rockchip.c

3866

bank = bank_num_to_bank(info, num);

drivers/pinctrl/pinctrl-rockchip.c

3867

if (IS_ERR(bank))

drivers/pinctrl/pinctrl-rockchip.c

3868

return PTR_ERR(bank);

drivers/pinctrl/pinctrl-rockchip.c

3870

grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);

drivers/pinctrl/pinctrl-rockchip.c

3969

int pin, bank, ret;

drivers/pinctrl/pinctrl-rockchip.c

3986

for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {

drivers/pinctrl/pinctrl-rockchip.c

3987

pin_bank = &info->ctrl->pin_banks[bank];

drivers/pinctrl/pinctrl-rockchip.c

4025

struct rockchip_pin_bank *bank;

drivers/pinctrl/pinctrl-rockchip.c

4035

bank = ctrl->pin_banks;

drivers/pinctrl/pinctrl-rockchip.c

4036

for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {

drivers/pinctrl/pinctrl-rockchip.c

4039

raw_spin_lock_init(&bank->slock);

drivers/pinctrl/pinctrl-rockchip.c

4040

bank->drvdata = d;

drivers/pinctrl/pinctrl-rockchip.c

4041

bank->pin_base = ctrl->nr_pins;

drivers/pinctrl/pinctrl-rockchip.c

4042

ctrl->nr_pins += bank->nr_pins;

drivers/pinctrl/pinctrl-rockchip.c

4046

struct rockchip_iomux *iom = &bank->iomux[j];

drivers/pinctrl/pinctrl-rockchip.c

4047

struct rockchip_drv *drv = &bank->drv[j];

drivers/pinctrl/pinctrl-rockchip.c

4050

if (bank_pins >= bank->nr_pins)

drivers/pinctrl/pinctrl-rockchip.c

4114

if (ctrl->iomux_recalced[j].num == bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

4116

bank->recalced_mask |= BIT(pin);

drivers/pinctrl/pinctrl-rockchip.c

4124

if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {

drivers/pinctrl/pinctrl-rockchip.c

4126

bank->route_mask |= BIT(pin);

drivers/pinctrl/pinctrl-rockchip.c

4260

struct rockchip_pin_bank *bank;

drivers/pinctrl/pinctrl-rockchip.c

4267

bank = &info->ctrl->pin_banks[i];

drivers/pinctrl/pinctrl-rockchip.c

4269

mutex_lock(&bank->deferred_lock);

drivers/pinctrl/pinctrl-rockchip.c

4270

while (!list_empty(&bank->deferred_pins)) {

drivers/pinctrl/pinctrl-rockchip.c

4271

cfg = list_first_entry(&bank->deferred_pins,

drivers/pinctrl/pinctrl-rockchip.c

4276

mutex_unlock(&bank->deferred_lock);

drivers/pinctrl/pinctrl-rockchip.c

775

static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,

drivers/pinctrl/pinctrl-rockchip.c

778

struct rockchip_pinctrl *info = bank->drvdata;

drivers/pinctrl/pinctrl-rockchip.c

785

if (data->num == bank->bank_num &&

drivers/pinctrl/pinctrl-rockchip.h

407

int (*pull_calc_reg)(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.h

410

int (*drv_calc_reg)(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rockchip.h

413

int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,

drivers/pinctrl/pinctrl-rp1.c

1002

bank = &rp1_iobanks[i];

drivers/pinctrl/pinctrl-rp1.c

1003

if (data->hwirq >= bank->min_gpio &&

drivers/pinctrl/pinctrl-rp1.c

1004

data->hwirq < bank->min_gpio + bank->num_gpios) {

drivers/pinctrl/pinctrl-rp1.c

1785

const struct rp1_iobank_desc *bank = &rp1_iobanks[i];

drivers/pinctrl/pinctrl-rp1.c

1788

for (j = 0; j < bank->num_gpios; j++) {

drivers/pinctrl/pinctrl-rp1.c

1790

&pc->pins[bank->min_gpio + j];

drivers/pinctrl/pinctrl-rp1.c

1793

pin->num = bank->min_gpio + j;

drivers/pinctrl/pinctrl-rp1.c

1794

pin->bank = i;

drivers/pinctrl/pinctrl-rp1.c

1797

reg_off = bank->gpio_offset + pin->offset *

drivers/pinctrl/pinctrl-rp1.c

1812

reg_off = bank->inte_offset;

drivers/pinctrl/pinctrl-rp1.c

1826

reg_off = bank->rio_offset;

drivers/pinctrl/pinctrl-rp1.c

1840

reg_off = bank->pads_offset + pin->offset * sizeof(u32);

drivers/pinctrl/pinctrl-rp1.c

255

u8 bank;

drivers/pinctrl/pinctrl-rp1.c

866

const struct rp1_iobank_desc *bank;

drivers/pinctrl/pinctrl-rp1.c

872

bank = &rp1_iobanks[0];

drivers/pinctrl/pinctrl-rp1.c

874

bank = &rp1_iobanks[1];

drivers/pinctrl/pinctrl-rp1.c

876

bank = &rp1_iobanks[2];

drivers/pinctrl/pinctrl-rp1.c

880

ints = readl(pc->gpio_base + bank->ints_offset);

drivers/pinctrl/pinctrl-rp1.c

886

bank->gpio_offset + bit_pos));

drivers/pinctrl/pinctrl-rp1.c

964

int bank = pin->bank;

drivers/pinctrl/pinctrl-rp1.c

968

raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);

drivers/pinctrl/pinctrl-rp1.c

978

raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);

drivers/pinctrl/pinctrl-rp1.c

997

const struct rp1_iobank_desc *bank;

drivers/pinctrl/pinctrl-st.c

1047

int bank, struct st_pio_control *pc)

drivers/pinctrl/pinctrl-st.c

1053

int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;

drivers/pinctrl/pinctrl-st.c

1083

int bank, struct st_pio_control *pc)

drivers/pinctrl/pinctrl-st.c

1089

int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;

drivers/pinctrl/pinctrl-st.c

1107

int bank, struct st_pio_control *pc)

drivers/pinctrl/pinctrl-st.c

1111

return st_pctl_dt_setup_retime_packed(info, bank, pc);

drivers/pinctrl/pinctrl-st.c

1113

return st_pctl_dt_setup_retime_dedicated(info, bank, pc);

drivers/pinctrl/pinctrl-st.c

1120

struct regmap *regmap, int bank,

drivers/pinctrl/pinctrl-st.c

1123

struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);

drivers/pinctrl/pinctrl-st.c

1131

static void st_parse_syscfgs(struct st_pinctrl *info, int bank,

drivers/pinctrl/pinctrl-st.c

1140

int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;

drivers/pinctrl/pinctrl-st.c

1142

struct st_pio_control *pc = &info->banks[bank].pc;

drivers/pinctrl/pinctrl-st.c

1146

pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);

drivers/pinctrl/pinctrl-st.c

1147

pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);

drivers/pinctrl/pinctrl-st.c

1148

pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);

drivers/pinctrl/pinctrl-st.c

1149

pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);

drivers/pinctrl/pinctrl-st.c

1154

st_pctl_dt_setup_retime(info, bank, pc);

drivers/pinctrl/pinctrl-st.c

1160

phandle bank, unsigned int offset)

drivers/pinctrl/pinctrl-st.c

1167

np = of_find_node_by_phandle(bank);

drivers/pinctrl/pinctrl-st.c

1197

phandle bank;

drivers/pinctrl/pinctrl-st.c

1235

bank = be32_to_cpup(list++);

drivers/pinctrl/pinctrl-st.c

1237

conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);

drivers/pinctrl/pinctrl-st.c

1295

struct st_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-st.c

1297

writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK);

drivers/pinctrl/pinctrl-st.c

1304

struct st_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-st.c

1307

writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK);

drivers/pinctrl/pinctrl-st.c

1329

struct st_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-st.c

1351

comp = st_gpio_get(&bank->gpio_chip, pin);

drivers/pinctrl/pinctrl-st.c

1358

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/pinctrl-st.c

1359

bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (

drivers/pinctrl/pinctrl-st.c

1361

bank->irq_edge_conf |= pin_edge_conf;

drivers/pinctrl/pinctrl-st.c

1362

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/pinctrl-st.c

1364

val = readl(bank->base + REG_PIO_PCOMP);

drivers/pinctrl/pinctrl-st.c

1367

writel(val, bank->base + REG_PIO_PCOMP);

drivers/pinctrl/pinctrl-st.c

1396

static void __gpio_irq_handler(struct st_gpio_bank *bank)

drivers/pinctrl/pinctrl-st.c

1402

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/pinctrl-st.c

1403

bank_edge_mask = bank->irq_edge_conf;

drivers/pinctrl/pinctrl-st.c

1404

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/pinctrl-st.c

1407

port_in = readl(bank->base + REG_PIO_PIN);

drivers/pinctrl/pinctrl-st.c

1408

port_comp = readl(bank->base + REG_PIO_PCOMP);

drivers/pinctrl/pinctrl-st.c

1409

port_mask = readl(bank->base + REG_PIO_PMASK);

drivers/pinctrl/pinctrl-st.c

1422

val = st_gpio_get(&bank->gpio_chip, n);

drivers/pinctrl/pinctrl-st.c

1425

val ? bank->base + REG_PIO_SET_PCOMP :

drivers/pinctrl/pinctrl-st.c

1426

bank->base + REG_PIO_CLR_PCOMP);

drivers/pinctrl/pinctrl-st.c

1433

generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);

drivers/pinctrl/pinctrl-st.c

1443

struct st_gpio_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/pinctrl-st.c

1446

__gpio_irq_handler(bank);

drivers/pinctrl/pinctrl-st.c

1492

struct st_gpio_bank *bank = &info->banks[bank_nr];

drivers/pinctrl/pinctrl-st.c

1493

struct pinctrl_gpio_range *range = &bank->range;

drivers/pinctrl/pinctrl-st.c

1502

bank->base = devm_ioremap_resource(dev, &res);

drivers/pinctrl/pinctrl-st.c

1503

if (IS_ERR(bank->base))

drivers/pinctrl/pinctrl-st.c

1504

return PTR_ERR(bank->base);

drivers/pinctrl/pinctrl-st.c

1506

bank->gpio_chip = st_gpio_template;

drivers/pinctrl/pinctrl-st.c

1507

bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;

drivers/pinctrl/pinctrl-st.c

1508

bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;

drivers/pinctrl/pinctrl-st.c

1509

bank->gpio_chip.fwnode = of_fwnode_handle(np);

drivers/pinctrl/pinctrl-st.c

1510

bank->gpio_chip.parent = dev;

drivers/pinctrl/pinctrl-st.c

1511

spin_lock_init(&bank->lock);

drivers/pinctrl/pinctrl-st.c

1514

bank->gpio_chip.label = range->name;

drivers/pinctrl/pinctrl-st.c

1518

range->npins = bank->gpio_chip.ngpio;

drivers/pinctrl/pinctrl-st.c

1519

range->gc = &bank->gpio_chip;

drivers/pinctrl/pinctrl-st.c

1555

girq = &bank->gpio_chip.irq;

drivers/pinctrl/pinctrl-st.c

1569

err = gpiochip_add_data(&bank->gpio_chip, bank);

drivers/pinctrl/pinctrl-st.c

1590

int i = 0, j = 0, k = 0, bank;

drivers/pinctrl/pinctrl-st.c

1636

bank = 0;

drivers/pinctrl/pinctrl-st.c

1642

ret = st_gpiolib_register_bank(info, bank, child);

drivers/pinctrl/pinctrl-st.c

1646

k = info->banks[bank].range.pin_base;

drivers/pinctrl/pinctrl-st.c

1647

bank_name = info->banks[bank].range.name;

drivers/pinctrl/pinctrl-st.c

1658

st_parse_syscfgs(info, bank, child);

drivers/pinctrl/pinctrl-st.c

1659

bank++;

drivers/pinctrl/pinctrl-st.c

371

struct st_gpio_bank *bank = gpio_range_to_bank(range);

drivers/pinctrl/pinctrl-st.c

373

return &bank->pc;

drivers/pinctrl/pinctrl-st.c

663

static inline void __st_gpio_set(struct st_gpio_bank *bank,

drivers/pinctrl/pinctrl-st.c

667

writel(BIT(offset), bank->base + REG_PIO_SET_POUT);

drivers/pinctrl/pinctrl-st.c

669

writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);

drivers/pinctrl/pinctrl-st.c

672

static void st_gpio_direction(struct st_gpio_bank *bank,

drivers/pinctrl/pinctrl-st.c

696

writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));

drivers/pinctrl/pinctrl-st.c

698

writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));

drivers/pinctrl/pinctrl-st.c

704

struct st_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-st.c

706

return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));

drivers/pinctrl/pinctrl-st.c

711

struct st_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-st.c

712

__st_gpio_set(bank, offset, value);

drivers/pinctrl/pinctrl-st.c

720

struct st_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-st.c

722

__st_gpio_set(bank, offset, value);

drivers/pinctrl/pinctrl-st.c

729

struct st_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/pinctrl-st.c

730

struct st_pio_control pc = bank->pc;

drivers/pinctrl/pinctrl-st.c

752

value = readl(bank->base + REG_PIO_PC(i));

drivers/pinctrl/pinctrl-st.c

913

struct st_gpio_bank *bank = gpio_range_to_bank(range);

drivers/pinctrl/pinctrl-st.c

919

st_pctl_set_function(&bank->pc, gpio, 0);

drivers/pinctrl/pinctrl-st.c

920

st_gpio_direction(bank, gpio, input ?

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

129

struct pm8xxx_pin_data *pin, int bank)

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

131

unsigned int val = bank << 4;

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

136

dev_err(pctrl->dev, "failed to select bank %d\n", bank);

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

142

dev_err(pctrl->dev, "failed to read register %d\n", bank);

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

151

int bank,

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

157

val |= bank << 4;

drivers/pinctrl/renesas/pfc-sh7734.c

22

#define _GP_DATA(bank, pin, name, sfx, cfg) \

drivers/pinctrl/renesas/pfc-sh7734.c

25

#define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT

drivers/pinctrl/renesas/pfc-sh7734.c

26

#define _GP_INDT(bank, pin, name, sfx, cfg) name##_DATA

drivers/pinctrl/renesas/pfc-sh7734.c

27

#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)

drivers/pinctrl/renesas/pfc-sh7734.c

28

#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)

drivers/pinctrl/renesas/sh_pfc.h

442

#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

443

fn(bank, pin, GP_##bank##_##pin, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

444

#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

446

#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

447

PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

448

PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

449

#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

451

#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

452

PORT_GP_CFG_2(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

453

PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

454

PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

455

#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

457

#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

458

PORT_GP_CFG_4(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

459

PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

460

PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

461

#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

463

#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

464

PORT_GP_CFG_6(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

465

PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

466

#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

468

#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

469

PORT_GP_CFG_7(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

470

PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

471

#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

473

#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

474

PORT_GP_CFG_8(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

475

PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

476

#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

478

#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

479

PORT_GP_CFG_9(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

480

PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

481

#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

483

#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

484

PORT_GP_CFG_10(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

485

PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

486

#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

488

#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

489

PORT_GP_CFG_11(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

490

PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

491

#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

493

#define PORT_GP_CFG_13(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

494

PORT_GP_CFG_12(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

495

PORT_GP_CFG_1(bank, 12, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

496

#define PORT_GP_13(bank, fn, sfx) PORT_GP_CFG_13(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

498

#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

499

PORT_GP_CFG_13(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

500

PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

501

#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

503

#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

504

PORT_GP_CFG_14(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

505

PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

506

#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

508

#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

509

PORT_GP_CFG_15(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

510

PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

511

#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

513

#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

514

PORT_GP_CFG_16(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

515

PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

516

#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

518

#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

519

PORT_GP_CFG_17(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

520

PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

521

#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

523

#define PORT_GP_CFG_19(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

524

PORT_GP_CFG_18(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

525

PORT_GP_CFG_1(bank, 18, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

526

#define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

528

#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

529

PORT_GP_CFG_19(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

530

PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

531

#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

533

#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

534

PORT_GP_CFG_20(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

535

PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

536

#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

538

#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

539

PORT_GP_CFG_21(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

540

PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

541

#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

543

#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

544

PORT_GP_CFG_22(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

545

PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

546

#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

548

#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

549

PORT_GP_CFG_23(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

550

PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

551

#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

553

#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

554

PORT_GP_CFG_24(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

555

PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

556

#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

558

#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

559

PORT_GP_CFG_25(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

560

PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

561

#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

563

#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

564

PORT_GP_CFG_26(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

565

PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

566

#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

568

#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

569

PORT_GP_CFG_27(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

570

PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

571

#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

573

#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

574

PORT_GP_CFG_28(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

575

PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

576

#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

578

#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

579

PORT_GP_CFG_29(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

580

PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

581

#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

583

#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

584

PORT_GP_CFG_30(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

585

PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

586

#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

588

#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

589

PORT_GP_CFG_31(bank, fn, sfx, cfg), \

drivers/pinctrl/renesas/sh_pfc.h

590

PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)

drivers/pinctrl/renesas/sh_pfc.h

591

#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)

drivers/pinctrl/renesas/sh_pfc.h

593

#define PORT_GP_32_REV(bank, fn, sfx) \

drivers/pinctrl/renesas/sh_pfc.h

594

PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

595

PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

596

PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

597

PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

598

PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

599

PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

600

PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

601

PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

602

PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

603

PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

604

PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

605

PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

606

PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

607

PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

608

PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \

drivers/pinctrl/renesas/sh_pfc.h

609

PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)

drivers/pinctrl/renesas/sh_pfc.h

612

#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx

drivers/pinctrl/renesas/sh_pfc.h

616

#define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \

drivers/pinctrl/renesas/sh_pfc.h

617

.pin = (bank * 32) + _pin, \

drivers/pinctrl/renesas/sh_pfc.h

625

#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)

drivers/pinctrl/renesas/sh_pfc.h

637

#define _GP_ENTRY(bank, pin, name, sfx, cfg) \

drivers/pinctrl/renesas/sh_pfc.h

638

deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated

drivers/pinctrl/renesas/sh_pfc.h

761

#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))

drivers/pinctrl/samsung/pinctrl-exynos.c

1002

void exynos_pinctrl_resume(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

1004

struct exynos_eint_gpio_save *save = bank->soc_priv;

drivers/pinctrl/samsung/pinctrl-exynos.c

1005

void __iomem *regs = bank->eint_base;

drivers/pinctrl/samsung/pinctrl-exynos.c

1007

if (bank->eint_type == EINT_TYPE_GPIO) {

drivers/pinctrl/samsung/pinctrl-exynos.c

1008

pr_debug("%s: con %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

101

if (clk_enable(bank->drvdata->pclk)) {

drivers/pinctrl/samsung/pinctrl-exynos.c

1010

+ bank->eint_offset), save->eint_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

1011

pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

1013

+ 2 * bank->eint_offset), save->eint_fltcon0);

drivers/pinctrl/samsung/pinctrl-exynos.c

1014

pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

1016

+ 2 * bank->eint_offset + 4),

drivers/pinctrl/samsung/pinctrl-exynos.c

1018

pr_debug("%s: mask %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

1019

readl(regs + bank->irq_chip->eint_mask

drivers/pinctrl/samsung/pinctrl-exynos.c

102

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

1020

+ bank->eint_offset), save->eint_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

1023

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

1025

+ 2 * bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

1027

+ 2 * bank->eint_offset + 4);

drivers/pinctrl/samsung/pinctrl-exynos.c

1028

writel(save->eint_mask, regs + bank->irq_chip->eint_mask

drivers/pinctrl/samsung/pinctrl-exynos.c

1029

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

1033

void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

1035

struct exynos_eint_gpio_save *save = bank->soc_priv;

drivers/pinctrl/samsung/pinctrl-exynos.c

1036

void __iomem *regs = bank->eint_base;

drivers/pinctrl/samsung/pinctrl-exynos.c

1038

if (bank->eint_type == EINT_TYPE_GPIO) {

drivers/pinctrl/samsung/pinctrl-exynos.c

1040

if (!bank->eint_con_offset)

drivers/pinctrl/samsung/pinctrl-exynos.c

1041

exynos_pinctrl_resume(bank);

drivers/pinctrl/samsung/pinctrl-exynos.c

1043

pr_debug("%s: con %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

1044

readl(regs + bank->pctl_offset + bank->eint_con_offset),

drivers/pinctrl/samsung/pinctrl-exynos.c

1046

pr_debug("%s: mask %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

1047

readl(regs + bank->pctl_offset +

drivers/pinctrl/samsung/pinctrl-exynos.c

1048

bank->eint_mask_offset), save->eint_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

1051

regs + bank->pctl_offset + bank->eint_con_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

1053

regs + bank->pctl_offset + bank->eint_mask_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

107

writel(1 << irqd->hwirq, bank->eint_base + reg_pend);

drivers/pinctrl/samsung/pinctrl-exynos.c

109

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

116

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

132

if (bank->eint_mask_offset)

drivers/pinctrl/samsung/pinctrl-exynos.c

133

reg_mask = bank->pctl_offset + bank->eint_mask_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

135

reg_mask = our_chip->eint_mask + bank->eint_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

137

if (clk_enable(bank->drvdata->pclk)) {

drivers/pinctrl/samsung/pinctrl-exynos.c

138

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

143

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

145

mask = readl(bank->eint_base + reg_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

147

writel(mask, bank->eint_base + reg_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

149

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

151

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

158

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

190

if (bank->eint_con_offset)

drivers/pinctrl/samsung/pinctrl-exynos.c

191

reg_con = bank->pctl_offset + bank->eint_con_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

193

reg_con = our_chip->eint_con + bank->eint_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

195

ret = clk_enable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

197

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

202

con = readl(bank->eint_base + reg_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

205

writel(con, bank->eint_base + reg_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

207

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

215

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

216

struct samsung_pinctrl_drv_data *d = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-exynos.c

227

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

228

const struct samsung_pin_bank_type *bank_type = bank->type;

drivers/pinctrl/samsung/pinctrl-exynos.c

233

ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

235

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

237

bank->name, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

241

reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];

drivers/pinctrl/samsung/pinctrl-exynos.c

245

ret = clk_enable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

247

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

249

bank->name, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

253

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

255

con = readl(bank->pctl_base + reg_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

258

writel(con, bank->pctl_base + reg_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

260

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

262

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

269

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

270

const struct samsung_pin_bank_type *bank_type = bank->type;

drivers/pinctrl/samsung/pinctrl-exynos.c

274

reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];

drivers/pinctrl/samsung/pinctrl-exynos.c

278

if (clk_enable(bank->drvdata->pclk)) {

drivers/pinctrl/samsung/pinctrl-exynos.c

279

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

281

bank->name, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

285

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

287

con = readl(bank->pctl_base + reg_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

290

writel(con, bank->pctl_base + reg_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

292

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

294

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

296

gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

341

struct samsung_pin_bank *bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-exynos.c

345

if (clk_enable(bank->drvdata->pclk)) {

drivers/pinctrl/samsung/pinctrl-exynos.c

346

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

351

if (bank->eint_con_offset)

drivers/pinctrl/samsung/pinctrl-exynos.c

352

svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);

drivers/pinctrl/samsung/pinctrl-exynos.c

354

svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);

drivers/pinctrl/samsung/pinctrl-exynos.c

356

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

363

bank += (group - 1);

drivers/pinctrl/samsung/pinctrl-exynos.c

365

ret = generic_handle_domain_irq(bank->irq_domain, pin);

drivers/pinctrl/samsung/pinctrl-exynos.c

399

static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter)

drivers/pinctrl/samsung/pinctrl-exynos.c

401

unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

402

void __iomem *reg = bank->drvdata->virt_base + off;

drivers/pinctrl/samsung/pinctrl-exynos.c

405

for (int n = 0; n < bank->nr_pins; n += 4)

drivers/pinctrl/samsung/pinctrl-exynos.c

407

min(bank->nr_pins - n, 4), con);

drivers/pinctrl/samsung/pinctrl-exynos.c

416

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-exynos.c

433

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-exynos.c

434

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-exynos.c

435

if (bank->eint_type != EINT_TYPE_GPIO)

drivers/pinctrl/samsung/pinctrl-exynos.c

438

bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,

drivers/pinctrl/samsung/pinctrl-exynos.c

439

sizeof(*bank->irq_chip), GFP_KERNEL);

drivers/pinctrl/samsung/pinctrl-exynos.c

440

if (!bank->irq_chip) {

drivers/pinctrl/samsung/pinctrl-exynos.c

444

bank->irq_chip->chip.name = bank->name;

drivers/pinctrl/samsung/pinctrl-exynos.c

446

bank->irq_domain = irq_domain_create_linear(bank->fwnode,

drivers/pinctrl/samsung/pinctrl-exynos.c

447

bank->nr_pins, &exynos_eint_irqd_ops, bank);

drivers/pinctrl/samsung/pinctrl-exynos.c

448

if (!bank->irq_domain) {

drivers/pinctrl/samsung/pinctrl-exynos.c

454

bank->soc_priv = devm_kzalloc(d->dev,

drivers/pinctrl/samsung/pinctrl-exynos.c

456

if (!bank->soc_priv) {

drivers/pinctrl/samsung/pinctrl-exynos.c

457

irq_domain_remove(bank->irq_domain);

drivers/pinctrl/samsung/pinctrl-exynos.c

467

for (--i, --bank; i >= 0; --i, --bank) {

drivers/pinctrl/samsung/pinctrl-exynos.c

468

if (bank->eint_type != EINT_TYPE_GPIO)

drivers/pinctrl/samsung/pinctrl-exynos.c

470

irq_domain_remove(bank->irq_domain);

drivers/pinctrl/samsung/pinctrl-exynos.c

479

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

480

struct samsung_pinctrl_drv_data *d = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-exynos.c

483

bit = bank->eint_num + irqd->hwirq;

drivers/pinctrl/samsung/pinctrl-exynos.c

525

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

526

unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

529

irqd->irq, bank->name, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-exynos.c

62

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

67

if (bank->eint_mask_offset)

drivers/pinctrl/samsung/pinctrl-exynos.c

68

reg_mask = bank->pctl_offset + bank->eint_mask_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

699

struct samsung_pin_bank *bank = eintd->bank;

drivers/pinctrl/samsung/pinctrl-exynos.c

70

reg_mask = our_chip->eint_mask + bank->eint_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

704

generic_handle_domain_irq(bank->irq_domain, eintd->irq);

drivers/pinctrl/samsung/pinctrl-exynos.c

72

if (clk_enable(bank->drvdata->pclk)) {

drivers/pinctrl/samsung/pinctrl-exynos.c

73

dev_err(bank->gpio_chip.parent,

drivers/pinctrl/samsung/pinctrl-exynos.c

772

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-exynos.c

78

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

793

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-exynos.c

794

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-exynos.c

795

if (bank->eint_type != EINT_TYPE_WKUP)

drivers/pinctrl/samsung/pinctrl-exynos.c

798

bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),

drivers/pinctrl/samsung/pinctrl-exynos.c

80

mask = readl(bank->eint_base + reg_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

800

if (!bank->irq_chip)

drivers/pinctrl/samsung/pinctrl-exynos.c

802

bank->irq_chip->chip.name = bank->name;

drivers/pinctrl/samsung/pinctrl-exynos.c

804

bank->irq_domain = irq_domain_create_linear(bank->fwnode,

drivers/pinctrl/samsung/pinctrl-exynos.c

805

bank->nr_pins, &exynos_eint_irqd_ops, bank);

drivers/pinctrl/samsung/pinctrl-exynos.c

806

if (!bank->irq_domain) {

drivers/pinctrl/samsung/pinctrl-exynos.c

811

bank->eint_num = eint_num;

drivers/pinctrl/samsung/pinctrl-exynos.c

812

eint_num = eint_num + bank->nr_pins;

drivers/pinctrl/samsung/pinctrl-exynos.c

814

if (!fwnode_property_present(bank->fwnode, "interrupts")) {

drivers/pinctrl/samsung/pinctrl-exynos.c

815

bank->eint_type = EINT_TYPE_WKUP_MUX;

drivers/pinctrl/samsung/pinctrl-exynos.c

82

writel(mask, bank->eint_base + reg_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

821

bank->nr_pins, sizeof(*weint_data),

drivers/pinctrl/samsung/pinctrl-exynos.c

826

for (idx = 0; idx < bank->nr_pins; ++idx) {

drivers/pinctrl/samsung/pinctrl-exynos.c

827

irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);

drivers/pinctrl/samsung/pinctrl-exynos.c

830

bank->name, idx);

drivers/pinctrl/samsung/pinctrl-exynos.c

834

weint_data[idx].bank = bank;

drivers/pinctrl/samsung/pinctrl-exynos.c

84

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-exynos.c

859

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-exynos.c

86

clk_disable(bank->drvdata->pclk);

drivers/pinctrl/samsung/pinctrl-exynos.c

861

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-exynos.c

862

if (bank->eint_type != EINT_TYPE_WKUP_MUX)

drivers/pinctrl/samsung/pinctrl-exynos.c

865

muxed_data->banks[idx++] = bank;

drivers/pinctrl/samsung/pinctrl-exynos.c

871

static void exynos_set_wakeup(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

875

if (bank->irq_chip) {

drivers/pinctrl/samsung/pinctrl-exynos.c

876

irq_chip = bank->irq_chip;

drivers/pinctrl/samsung/pinctrl-exynos.c

877

irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);

drivers/pinctrl/samsung/pinctrl-exynos.c

881

void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

883

struct exynos_eint_gpio_save *save = bank->soc_priv;

drivers/pinctrl/samsung/pinctrl-exynos.c

884

const void __iomem *regs = bank->eint_base;

drivers/pinctrl/samsung/pinctrl-exynos.c

886

if (bank->eint_type == EINT_TYPE_GPIO) {

drivers/pinctrl/samsung/pinctrl-exynos.c

888

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

890

+ 2 * bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

892

+ 2 * bank->eint_offset + 4);

drivers/pinctrl/samsung/pinctrl-exynos.c

893

save->eint_mask = readl(regs + bank->irq_chip->eint_mask

drivers/pinctrl/samsung/pinctrl-exynos.c

894

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

897

bank->name, save->eint_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

899

bank->name, save->eint_fltcon0);

drivers/pinctrl/samsung/pinctrl-exynos.c

901

bank->name, save->eint_fltcon1);

drivers/pinctrl/samsung/pinctrl-exynos.c

903

bank->name, save->eint_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

904

} else if (bank->eint_type == EINT_TYPE_WKUP) {

drivers/pinctrl/samsung/pinctrl-exynos.c

905

exynos_set_wakeup(bank);

drivers/pinctrl/samsung/pinctrl-exynos.c

909

void gs101_pinctrl_suspend(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

911

struct exynos_eint_gpio_save *save = bank->soc_priv;

drivers/pinctrl/samsung/pinctrl-exynos.c

912

const void __iomem *regs = bank->eint_base;

drivers/pinctrl/samsung/pinctrl-exynos.c

914

if (bank->eint_type == EINT_TYPE_GPIO) {

drivers/pinctrl/samsung/pinctrl-exynos.c

916

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

919

+ bank->eint_fltcon_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

922

if (bank->nr_pins > 4)

drivers/pinctrl/samsung/pinctrl-exynos.c

925

+ bank->eint_fltcon_offset + 4);

drivers/pinctrl/samsung/pinctrl-exynos.c

927

save->eint_mask = readl(regs + bank->irq_chip->eint_mask

drivers/pinctrl/samsung/pinctrl-exynos.c

928

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

93

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-exynos.c

931

bank->name, save->eint_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

933

bank->name, save->eint_fltcon0);

drivers/pinctrl/samsung/pinctrl-exynos.c

934

if (bank->nr_pins > 4)

drivers/pinctrl/samsung/pinctrl-exynos.c

936

bank->name, save->eint_fltcon1);

drivers/pinctrl/samsung/pinctrl-exynos.c

938

bank->name, save->eint_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

939

} else if (bank->eint_type == EINT_TYPE_WKUP) {

drivers/pinctrl/samsung/pinctrl-exynos.c

940

exynos_set_wakeup(bank);

drivers/pinctrl/samsung/pinctrl-exynos.c

941

exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG);

drivers/pinctrl/samsung/pinctrl-exynos.c

945

void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

947

struct exynos_eint_gpio_save *save = bank->soc_priv;

drivers/pinctrl/samsung/pinctrl-exynos.c

948

const void __iomem *regs = bank->eint_base;

drivers/pinctrl/samsung/pinctrl-exynos.c

950

if (bank->eint_type == EINT_TYPE_GPIO) {

drivers/pinctrl/samsung/pinctrl-exynos.c

951

save->eint_con = readl(regs + bank->pctl_offset +

drivers/pinctrl/samsung/pinctrl-exynos.c

952

bank->eint_con_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

953

save->eint_mask = readl(regs + bank->pctl_offset +

drivers/pinctrl/samsung/pinctrl-exynos.c

954

bank->eint_mask_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

956

bank->name, save->eint_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

958

bank->name, save->eint_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

959

} else if (bank->eint_type == EINT_TYPE_WKUP) {

drivers/pinctrl/samsung/pinctrl-exynos.c

96

if (bank->eint_pend_offset)

drivers/pinctrl/samsung/pinctrl-exynos.c

960

exynos_set_wakeup(bank);

drivers/pinctrl/samsung/pinctrl-exynos.c

964

void gs101_pinctrl_resume(struct samsung_pin_bank *bank)

drivers/pinctrl/samsung/pinctrl-exynos.c

966

struct exynos_eint_gpio_save *save = bank->soc_priv;

drivers/pinctrl/samsung/pinctrl-exynos.c

968

void __iomem *regs = bank->eint_base;

drivers/pinctrl/samsung/pinctrl-exynos.c

97

reg_pend = bank->pctl_offset + bank->eint_pend_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

970

+ bank->eint_fltcon_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

972

if (bank->eint_type == EINT_TYPE_GPIO) {

drivers/pinctrl/samsung/pinctrl-exynos.c

973

pr_debug("%s: con %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

975

+ bank->eint_offset), save->eint_con);

drivers/pinctrl/samsung/pinctrl-exynos.c

977

pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

981

if (bank->nr_pins > 4)

drivers/pinctrl/samsung/pinctrl-exynos.c

982

pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

985

pr_debug("%s: mask %#010x => %#010x\n", bank->name,

drivers/pinctrl/samsung/pinctrl-exynos.c

986

readl(regs + bank->irq_chip->eint_mask

drivers/pinctrl/samsung/pinctrl-exynos.c

987

+ bank->eint_offset), save->eint_mask);

drivers/pinctrl/samsung/pinctrl-exynos.c

99

reg_pend = our_chip->eint_pend + bank->eint_offset;

drivers/pinctrl/samsung/pinctrl-exynos.c

990

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

993

if (bank->nr_pins > 4)

drivers/pinctrl/samsung/pinctrl-exynos.c

995

writel(save->eint_mask, regs + bank->irq_chip->eint_mask

drivers/pinctrl/samsung/pinctrl-exynos.c

996

+ bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-exynos.c

997

} else if (bank->eint_type == EINT_TYPE_WKUP) {

drivers/pinctrl/samsung/pinctrl-exynos.c

998

exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL);

drivers/pinctrl/samsung/pinctrl-exynos.h

257

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-exynos.h

273

void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-exynos.h

274

void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-exynos.h

275

void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-exynos.h

276

void exynos_pinctrl_resume(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-exynos.h

277

void gs101_pinctrl_suspend(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-exynos.h

278

void gs101_pinctrl_resume(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

217

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

281

struct samsung_pin_bank *bank, int pin)

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

283

const struct samsung_pin_bank_type *bank_type = bank->type;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

291

reg = d->virt_base + bank->pctl_offset;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

302

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

306

val |= bank->eint_func << shift;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

309

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

318

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

319

struct samsung_pinctrl_drv_data *d = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

320

unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

321

void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

344

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

345

struct samsung_pinctrl_drv_data *d = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

346

unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

347

void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

354

struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

355

struct samsung_pinctrl_drv_data *d = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

370

reg = d->virt_base + EINTCON_REG(bank->eint_offset);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

371

shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

379

s3c64xx_irq_set_function(d, bank, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

398

struct samsung_pin_bank *bank = h->host_data;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

400

if (!(bank->eint_mask & (1 << hw)))

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

405

irq_set_chip_data(virq, bank);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

465

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

476

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

477

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

481

if (bank->eint_type != EINT_TYPE_GPIO)

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

484

mask = bank->eint_mask;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

487

bank->irq_domain = irq_domain_create_linear(bank->fwnode,

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

488

nr_eints, &s3c64xx_gpio_irqd_ops, bank);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

489

if (!bank->irq_domain) {

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

503

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

505

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

506

if (bank->eint_type != EINT_TYPE_GPIO)

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

509

data->domains[nr_domains++] = bank->irq_domain;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

525

struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

550

struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

560

struct samsung_pin_bank *bank = ddata->bank;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

561

struct samsung_pinctrl_drv_data *d = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

589

s3c64xx_irq_set_function(d, bank, irqd->hwirq);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

668

struct samsung_pin_bank *bank = ddata->bank;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

670

if (!(bank->eint_mask & (1 << hw)))

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

703

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

739

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

740

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

747

if (bank->eint_type != EINT_TYPE_WKUP)

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

750

mask = bank->eint_mask;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

757

ddata->bank = bank;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

759

bank->irq_domain = irq_domain_create_linear(bank->fwnode,

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

761

if (!bank->irq_domain) {

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

766

irq = bank->eint_offset;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

767

mask = bank->eint_mask;

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

771

data->domains[irq] = bank->irq_domain;

drivers/pinctrl/samsung/pinctrl-samsung.c

1012

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

1013

const struct samsung_pin_bank_type *type = bank->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

1017

reg = bank->pctl_base + bank->pctl_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1032

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

1033

struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-samsung.c

1058

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

1060

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

1084

struct samsung_pin_bank *bank = drvdata->pin_banks;

drivers/pinctrl/samsung/pinctrl-samsung.c

1089

for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-samsung.c

1090

bank->gpio_chip = samsung_gpiolib_chip;

drivers/pinctrl/samsung/pinctrl-samsung.c

1092

gc = &bank->gpio_chip;

drivers/pinctrl/samsung/pinctrl-samsung.c

1094

gc->ngpio = bank->nr_pins;

drivers/pinctrl/samsung/pinctrl-samsung.c

1096

gc->fwnode = bank->fwnode;

drivers/pinctrl/samsung/pinctrl-samsung.c

1097

gc->label = bank->name;

drivers/pinctrl/samsung/pinctrl-samsung.c

1099

ret = devm_gpiochip_add_data(&pdev->dev, gc, bank);

drivers/pinctrl/samsung/pinctrl-samsung.c

1134

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

1137

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-samsung.c

1138

for (i = 0; i < d->nr_banks; ++i, ++bank)

drivers/pinctrl/samsung/pinctrl-samsung.c

1139

fwnode_handle_put(bank->fwnode);

drivers/pinctrl/samsung/pinctrl-samsung.c

1149

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

1156

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-samsung.c

1157

for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-samsung.c

1158

strscpy(node_name, bank->name, sizeof(node_name));

drivers/pinctrl/samsung/pinctrl-samsung.c

1162

bank->name);

drivers/pinctrl/samsung/pinctrl-samsung.c

1171

if (of_node_name_eq(np, bank->name))

drivers/pinctrl/samsung/pinctrl-samsung.c

1176

bank->fwnode = child;

drivers/pinctrl/samsung/pinctrl-samsung.c

1179

bank->name);

drivers/pinctrl/samsung/pinctrl-samsung.c

1191

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

1225

bank = d->pin_banks;

drivers/pinctrl/samsung/pinctrl-samsung.c

1227

for (i = 0; i < ctrl->nr_banks; ++i, ++bdata, ++bank) {

drivers/pinctrl/samsung/pinctrl-samsung.c

1228

bank->type = bdata->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

1229

bank->pctl_offset = bdata->pctl_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1230

bank->nr_pins = bdata->nr_pins;

drivers/pinctrl/samsung/pinctrl-samsung.c

1231

bank->eint_func = bdata->eint_func;

drivers/pinctrl/samsung/pinctrl-samsung.c

1232

bank->eint_type = bdata->eint_type;

drivers/pinctrl/samsung/pinctrl-samsung.c

1233

bank->eint_mask = bdata->eint_mask;

drivers/pinctrl/samsung/pinctrl-samsung.c

1234

bank->eint_offset = bdata->eint_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1235

bank->eint_con_offset = bdata->eint_con_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1236

bank->eint_mask_offset = bdata->eint_mask_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1237

bank->eint_pend_offset = bdata->eint_pend_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1238

bank->eint_fltcon_offset = bdata->eint_fltcon_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1239

bank->name = bdata->name;

drivers/pinctrl/samsung/pinctrl-samsung.c

1241

raw_spin_lock_init(&bank->slock);

drivers/pinctrl/samsung/pinctrl-samsung.c

1242

bank->drvdata = d;

drivers/pinctrl/samsung/pinctrl-samsung.c

1243

bank->pin_base = d->nr_pins;

drivers/pinctrl/samsung/pinctrl-samsung.c

1244

d->nr_pins += bank->nr_pins;

drivers/pinctrl/samsung/pinctrl-samsung.c

1246

bank->eint_base = virt_base[0];

drivers/pinctrl/samsung/pinctrl-samsung.c

1247

bank->pctl_base = virt_base[bdata->pctl_res_idx];

drivers/pinctrl/samsung/pinctrl-samsung.c

1341

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

1352

bank = &drvdata->pin_banks[i];

drivers/pinctrl/samsung/pinctrl-samsung.c

1353

const void __iomem *reg = bank->pctl_base + bank->pctl_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1354

const u8 *offs = bank->type->reg_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1355

const u8 *widths = bank->type->fld_width;

drivers/pinctrl/samsung/pinctrl-samsung.c

1364

bank->pm_save[type] = readl(reg + offs[type]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1366

if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) {

drivers/pinctrl/samsung/pinctrl-samsung.c

1368

bank->pm_save[PINCFG_TYPE_NUM] =

drivers/pinctrl/samsung/pinctrl-samsung.c

1371

bank->name, reg,

drivers/pinctrl/samsung/pinctrl-samsung.c

1372

bank->pm_save[PINCFG_TYPE_FUNC],

drivers/pinctrl/samsung/pinctrl-samsung.c

1373

bank->pm_save[PINCFG_TYPE_NUM]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1375

pr_debug("Save %s @ %p (con %#010x)\n", bank->name,

drivers/pinctrl/samsung/pinctrl-samsung.c

1376

reg, bank->pm_save[PINCFG_TYPE_FUNC]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1381

bank = &drvdata->pin_banks[i];

drivers/pinctrl/samsung/pinctrl-samsung.c

1383

drvdata->suspend(bank);

drivers/pinctrl/samsung/pinctrl-samsung.c

1405

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

1421

bank = &drvdata->pin_banks[i];

drivers/pinctrl/samsung/pinctrl-samsung.c

1423

drvdata->resume(bank);

drivers/pinctrl/samsung/pinctrl-samsung.c

1427

bank = &drvdata->pin_banks[i];

drivers/pinctrl/samsung/pinctrl-samsung.c

1428

void __iomem *reg = bank->pctl_base + bank->pctl_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1429

const u8 *offs = bank->type->reg_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1430

const u8 *widths = bank->type->fld_width;

drivers/pinctrl/samsung/pinctrl-samsung.c

1437

if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) {

drivers/pinctrl/samsung/pinctrl-samsung.c

1440

bank->name, reg,

drivers/pinctrl/samsung/pinctrl-samsung.c

1443

bank->pm_save[PINCFG_TYPE_FUNC],

drivers/pinctrl/samsung/pinctrl-samsung.c

1444

bank->pm_save[PINCFG_TYPE_NUM]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1445

writel(bank->pm_save[PINCFG_TYPE_NUM],

drivers/pinctrl/samsung/pinctrl-samsung.c

1448

pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name,

drivers/pinctrl/samsung/pinctrl-samsung.c

1450

bank->pm_save[PINCFG_TYPE_FUNC]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1454

writel(bank->pm_save[type], reg + offs[type]);

drivers/pinctrl/samsung/pinctrl-samsung.c

356

struct samsung_pin_bank **bank)

drivers/pinctrl/samsung/pinctrl-samsung.c

368

if (bank)

drivers/pinctrl/samsung/pinctrl-samsung.c

369

*bank = b;

drivers/pinctrl/samsung/pinctrl-samsung.c

378

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

390

pin_to_reg_bank(drvdata, grp->pins[0], &reg, &pin_offset, &bank);

drivers/pinctrl/samsung/pinctrl-samsung.c

391

type = bank->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

406

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

413

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

442

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

451

pin_to_reg_bank(drvdata, pin, &reg_base, &pin_offset, &bank);

drivers/pinctrl/samsung/pinctrl-samsung.c

452

type = bank->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

466

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

483

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

558

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

559

const struct samsung_pin_bank_type *type = bank->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

563

reg = bank->pctl_base + bank->pctl_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

576

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

577

struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-samsung.c

587

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

589

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

601

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

602

const struct samsung_pin_bank_type *type = bank->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

603

struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-samsung.c

606

reg = bank->pctl_base + bank->pctl_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

633

struct samsung_pin_bank *bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

637

bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

638

type = bank->type;

drivers/pinctrl/samsung/pinctrl-samsung.c

640

reg = bank->pctl_base + bank->pctl_offset

drivers/pinctrl/samsung/pinctrl-samsung.c

663

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

664

struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-samsung.c

674

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

676

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

687

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

688

struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;

drivers/pinctrl/samsung/pinctrl-samsung.c

698

raw_spin_lock_irqsave(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

701

raw_spin_unlock_irqrestore(&bank->slock, flags);

drivers/pinctrl/samsung/pinctrl-samsung.c

714

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

717

if (!bank->irq_domain)

drivers/pinctrl/samsung/pinctrl-samsung.c

720

virq = irq_create_mapping(bank->irq_domain, offset);

drivers/pinctrl/samsung/pinctrl-samsung.c

727

struct samsung_pin_bank *bank = gpiochip_get_data(gc);

drivers/pinctrl/samsung/pinctrl-samsung.c

729

bank->grange.name = bank->name;

drivers/pinctrl/samsung/pinctrl-samsung.c

730

bank->grange.id = bank->id;

drivers/pinctrl/samsung/pinctrl-samsung.c

731

bank->grange.pin_base = bank->pin_base;

drivers/pinctrl/samsung/pinctrl-samsung.c

732

bank->grange.base = gc->base;

drivers/pinctrl/samsung/pinctrl-samsung.c

733

bank->grange.npins = bank->nr_pins;

drivers/pinctrl/samsung/pinctrl-samsung.c

734

bank->grange.gc = &bank->gpio_chip;

drivers/pinctrl/samsung/pinctrl-samsung.c

735

pinctrl_add_gpio_range(bank->drvdata->pctl_dev, &bank->grange);

drivers/pinctrl/samsung/pinctrl-samsung.c

926

int pin, bank, ret;

drivers/pinctrl/samsung/pinctrl-samsung.c

958

for (bank = 0; bank < drvdata->nr_banks; bank++) {

drivers/pinctrl/samsung/pinctrl-samsung.c

959

pin_bank = &drvdata->pin_banks[bank];

drivers/pinctrl/samsung/pinctrl-samsung.c

960

pin_bank->id = bank;

drivers/pinctrl/samsung/pinctrl-samsung.c

987

struct samsung_pin_bank *bank = drvdata->pin_banks;

drivers/pinctrl/samsung/pinctrl-samsung.c

990

for (i = 0; i < drvdata->nr_banks; ++i, ++bank)

drivers/pinctrl/samsung/pinctrl-samsung.c

991

pinctrl_remove_gpio_range(drvdata->pctl_dev, &bank->grange);

drivers/pinctrl/samsung/pinctrl-samsung.h

292

void (*suspend)(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-samsung.h

293

void (*resume)(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-samsung.h

342

void (*suspend)(struct samsung_pin_bank *bank);

drivers/pinctrl/samsung/pinctrl-samsung.h

343

void (*resume)(struct samsung_pin_bank *bank);

drivers/pinctrl/stm32/pinctrl-stm32.c

1000

struct stm32_gpio_bank *bank;

drivers/pinctrl/stm32/pinctrl-stm32.c

1019

bank = gpiochip_get_data(range->gc);

drivers/pinctrl/stm32/pinctrl-stm32.c

1025

return stm32_pmx_set_mode(bank, pin, mode, alt);

drivers/pinctrl/stm32/pinctrl-stm32.c

1032

struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);

drivers/pinctrl/stm32/pinctrl-stm32.c

1035

return stm32_pmx_set_mode(bank, pin, !input, 0);

drivers/pinctrl/stm32/pinctrl-stm32.c

1043

struct stm32_gpio_bank *bank;

drivers/pinctrl/stm32/pinctrl-stm32.c

1056

bank = gpiochip_get_data(range->gc);

drivers/pinctrl/stm32/pinctrl-stm32.c

1057

if (!bank)

drivers/pinctrl/stm32/pinctrl-stm32.c

1060

if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

drivers/pinctrl/stm32/pinctrl-stm32.c

1080

static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1083

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

1088

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1099

val = readl_relaxed(bank->base + STM32_GPIO_TYPER);

drivers/pinctrl/stm32/pinctrl-stm32.c

1102

writel_relaxed(val, bank->base + STM32_GPIO_TYPER);

drivers/pinctrl/stm32/pinctrl-stm32.c

1107

stm32_gpio_backup_driving(bank, offset, drive);

drivers/pinctrl/stm32/pinctrl-stm32.c

1110

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1115

static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1120

val = readl_relaxed(bank->base + STM32_GPIO_TYPER);

drivers/pinctrl/stm32/pinctrl-stm32.c

1126

static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1129

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

1134

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1145

val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);

drivers/pinctrl/stm32/pinctrl-stm32.c

1148

writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);

drivers/pinctrl/stm32/pinctrl-stm32.c

1153

stm32_gpio_backup_speed(bank, offset, speed);

drivers/pinctrl/stm32/pinctrl-stm32.c

1156

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1161

static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1166

val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);

drivers/pinctrl/stm32/pinctrl-stm32.c

1172

static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1175

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

1180

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1191

val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);

drivers/pinctrl/stm32/pinctrl-stm32.c

1194

writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);

drivers/pinctrl/stm32/pinctrl-stm32.c

1199

stm32_gpio_backup_bias(bank, offset, bias);

drivers/pinctrl/stm32/pinctrl-stm32.c

1202

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1207

static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1212

val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);

drivers/pinctrl/stm32/pinctrl-stm32.c

1219

stm32_pconf_set_advcfgr_nolock(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)

drivers/pinctrl/stm32/pinctrl-stm32.c

1225

val = readl_relaxed(bank->base + advcfgr_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1228

writel_relaxed(val, bank->base + advcfgr_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1230

stm32_gpio_backup_advcfg(bank, offset, mask, value);

drivers/pinctrl/stm32/pinctrl-stm32.c

1233

static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)

drivers/pinctrl/stm32/pinctrl-stm32.c

1235

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

1239

if (!bank->io_sync_control)

drivers/pinctrl/stm32/pinctrl-stm32.c

1242

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1252

stm32_pconf_set_advcfgr_nolock(bank, offset, mask, value);

drivers/pinctrl/stm32/pinctrl-stm32.c

1258

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1263

static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask)

drivers/pinctrl/stm32/pinctrl-stm32.c

1269

if (!bank->io_sync_control)

drivers/pinctrl/stm32/pinctrl-stm32.c

1272

val = readl_relaxed(bank->base + advcfgr_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1278

static int stm32_pconf_set_io_sync(struct stm32_gpio_bank *bank, int offset, u32 io_sync)

drivers/pinctrl/stm32/pinctrl-stm32.c

1283

return stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,

drivers/pinctrl/stm32/pinctrl-stm32.c

1287

static const char *stm32_pconf_get_io_sync_str(struct stm32_gpio_bank *bank, int offset)

drivers/pinctrl/stm32/pinctrl-stm32.c

1289

u32 io_sync = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK);

drivers/pinctrl/stm32/pinctrl-stm32.c

1308

stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, bool is_dir_input)

drivers/pinctrl/stm32/pinctrl-stm32.c

1310

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

1317

if (!bank->io_sync_control)

drivers/pinctrl/stm32/pinctrl-stm32.c

1320

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1330

val = readl_relaxed(bank->base + delay_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1333

writel_relaxed(val, bank->base + delay_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1335

stm32_gpio_backup_skew_delay(bank, offset, delay);

drivers/pinctrl/stm32/pinctrl-stm32.c

1337

stm32_pconf_set_advcfgr_nolock(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK,

drivers/pinctrl/stm32/pinctrl-stm32.c

1344

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

1349

static u32 stm32_pconf_get_skew_delay_val(struct stm32_gpio_bank *bank, int offset)

drivers/pinctrl/stm32/pinctrl-stm32.c

1355

val = readl_relaxed(bank->base + delay_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1361

static const char *stm32_pconf_get_skew_dir_str(struct stm32_gpio_bank *bank, int offset)

drivers/pinctrl/stm32/pinctrl-stm32.c

1363

return stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK) ?

drivers/pinctrl/stm32/pinctrl-stm32.c

1367

static bool stm32_pconf_get(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1373

val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &

drivers/pinctrl/stm32/pinctrl-stm32.c

1376

val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &

drivers/pinctrl/stm32/pinctrl-stm32.c

1389

struct stm32_gpio_bank *bank;

drivers/pinctrl/stm32/pinctrl-stm32.c

1398

bank = gpiochip_get_data(range->gc);

drivers/pinctrl/stm32/pinctrl-stm32.c

1406

if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

drivers/pinctrl/stm32/pinctrl-stm32.c

1413

ret = stm32_pconf_set_driving(bank, offset, 0);

drivers/pinctrl/stm32/pinctrl-stm32.c

1416

ret = stm32_pconf_set_driving(bank, offset, 1);

drivers/pinctrl/stm32/pinctrl-stm32.c

1419

ret = stm32_pconf_set_speed(bank, offset, arg);

drivers/pinctrl/stm32/pinctrl-stm32.c

1422

ret = stm32_pconf_set_bias(bank, offset, 0);

drivers/pinctrl/stm32/pinctrl-stm32.c

1425

ret = stm32_pconf_set_bias(bank, offset, 1);

drivers/pinctrl/stm32/pinctrl-stm32.c

1428

ret = stm32_pconf_set_bias(bank, offset, 2);

drivers/pinctrl/stm32/pinctrl-stm32.c

1431

__stm32_gpio_set(bank, offset, arg);

drivers/pinctrl/stm32/pinctrl-stm32.c

1436

ret = stm32_pconf_set_skew_delay(bank, offset, arg, true);

drivers/pinctrl/stm32/pinctrl-stm32.c

1440

ret = stm32_pconf_set_skew_delay(bank, offset, arg, false);

drivers/pinctrl/stm32/pinctrl-stm32.c

1443

ret = stm32_pconf_set_io_sync(bank, offset, arg);

drivers/pinctrl/stm32/pinctrl-stm32.c

1519

struct stm32_gpio_bank *bank;

drivers/pinctrl/stm32/pinctrl-stm32.c

1534

bank = gpiochip_get_data(range->gc);

drivers/pinctrl/stm32/pinctrl-stm32.c

1542

stm32_pmx_get_mode(bank, offset, &mode, &alt);

drivers/pinctrl/stm32/pinctrl-stm32.c

1543

bias = stm32_pconf_get_bias(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1550

val = stm32_pconf_get(bank, offset, true);

drivers/pinctrl/stm32/pinctrl-stm32.c

1558

drive = stm32_pconf_get_driving(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1559

speed = stm32_pconf_get_speed(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1560

val = stm32_pconf_get(bank, offset, false);

drivers/pinctrl/stm32/pinctrl-stm32.c

1570

drive = stm32_pconf_get_driving(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1571

speed = stm32_pconf_get_speed(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1588

if (bank->io_sync_control) {

drivers/pinctrl/stm32/pinctrl-stm32.c

1592

io_sync_str = stm32_pconf_get_io_sync_str(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1593

skew_dir_str = stm32_pconf_get_skew_dir_str(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1594

skew_delay = stm32_pconf_get_skew_delay_val(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

1613

struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

1616

unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;

drivers/pinctrl/stm32/pinctrl-stm32.c

1638

struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];

drivers/pinctrl/stm32/pinctrl-stm32.c

1640

struct pinctrl_gpio_range *range = &bank->range;

drivers/pinctrl/stm32/pinctrl-stm32.c

1649

if (!IS_ERR(bank->rstc))

drivers/pinctrl/stm32/pinctrl-stm32.c

1650

reset_control_deassert(bank->rstc);

drivers/pinctrl/stm32/pinctrl-stm32.c

1655

bank->base = devm_ioremap_resource(dev, &res);

drivers/pinctrl/stm32/pinctrl-stm32.c

1656

if (IS_ERR(bank->base))

drivers/pinctrl/stm32/pinctrl-stm32.c

1657

return PTR_ERR(bank->base);

drivers/pinctrl/stm32/pinctrl-stm32.c

1659

bank->gpio_chip = stm32_gpio_template;

drivers/pinctrl/stm32/pinctrl-stm32.c

1661

fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);

drivers/pinctrl/stm32/pinctrl-stm32.c

1665

bank->gpio_chip.base = args.args[1];

drivers/pinctrl/stm32/pinctrl-stm32.c

1673

bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;

drivers/pinctrl/stm32/pinctrl-stm32.c

1674

range->name = bank->gpio_chip.label;

drivers/pinctrl/stm32/pinctrl-stm32.c

1679

range->gc = &bank->gpio_chip;

drivers/pinctrl/stm32/pinctrl-stm32.c

1687

bank->gpio_chip.base = -1;

drivers/pinctrl/stm32/pinctrl-stm32.c

1689

bank->gpio_chip.ngpio = npins;

drivers/pinctrl/stm32/pinctrl-stm32.c

1690

bank->gpio_chip.fwnode = fwnode;

drivers/pinctrl/stm32/pinctrl-stm32.c

1691

bank->gpio_chip.parent = dev;

drivers/pinctrl/stm32/pinctrl-stm32.c

1692

bank->bank_nr = bank_nr;

drivers/pinctrl/stm32/pinctrl-stm32.c

1693

bank->bank_ioport_nr = bank_ioport_nr;

drivers/pinctrl/stm32/pinctrl-stm32.c

1694

bank->secure_control = pctl->match_data->secure_control;

drivers/pinctrl/stm32/pinctrl-stm32.c

1695

bank->io_sync_control = pctl->match_data->io_sync_control;

drivers/pinctrl/stm32/pinctrl-stm32.c

1696

bank->rif_control = pctl->match_data->rif_control;

drivers/pinctrl/stm32/pinctrl-stm32.c

1697

spin_lock_init(&bank->lock);

drivers/pinctrl/stm32/pinctrl-stm32.c

1701

bank->fwnode = fwnode;

drivers/pinctrl/stm32/pinctrl-stm32.c

1703

bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,

drivers/pinctrl/stm32/pinctrl-stm32.c

1704

bank->fwnode, &stm32_gpio_domain_ops,

drivers/pinctrl/stm32/pinctrl-stm32.c

1705

bank);

drivers/pinctrl/stm32/pinctrl-stm32.c

1707

if (!bank->domain)

drivers/pinctrl/stm32/pinctrl-stm32.c

1716

stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);

drivers/pinctrl/stm32/pinctrl-stm32.c

1726

bank->gpio_chip.names = (const char * const *)names;

drivers/pinctrl/stm32/pinctrl-stm32.c

1728

err = gpiochip_add_data(&bank->gpio_chip, bank);

drivers/pinctrl/stm32/pinctrl-stm32.c

1734

dev_info(dev, "%s bank added\n", bank->gpio_chip.label);

drivers/pinctrl/stm32/pinctrl-stm32.c

184

static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);

drivers/pinctrl/stm32/pinctrl-stm32.c

1967

struct stm32_gpio_bank *bank = &pctl->banks[i];

drivers/pinctrl/stm32/pinctrl-stm32.c

1970

bank->rstc = of_reset_control_get_exclusive(np, NULL);

drivers/pinctrl/stm32/pinctrl-stm32.c

1971

if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {

drivers/pinctrl/stm32/pinctrl-stm32.c

2007

struct stm32_gpio_bank *bank = &pctl->banks[i];

drivers/pinctrl/stm32/pinctrl-stm32.c

2009

gpiochip_remove(&bank->gpio_chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

2023

struct stm32_gpio_bank *bank;

drivers/pinctrl/stm32/pinctrl-stm32.c

2031

bank = gpiochip_get_data(range->gc);

drivers/pinctrl/stm32/pinctrl-stm32.c

2036

if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

drivers/pinctrl/stm32/pinctrl-stm32.c

2046

mode = bank->pin_backup[offset].mode;

drivers/pinctrl/stm32/pinctrl-stm32.c

2047

ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt);

drivers/pinctrl/stm32/pinctrl-stm32.c

2052

__stm32_gpio_set(bank, offset, bank->pin_backup[offset].value);

drivers/pinctrl/stm32/pinctrl-stm32.c

2054

ret = stm32_pconf_set_driving(bank, offset, bank->pin_backup[offset].drive);

drivers/pinctrl/stm32/pinctrl-stm32.c

2058

ret = stm32_pconf_set_speed(bank, offset, bank->pin_backup[offset].speed);

drivers/pinctrl/stm32/pinctrl-stm32.c

2062

ret = stm32_pconf_set_bias(bank, offset, bank->pin_backup[offset].bias);

drivers/pinctrl/stm32/pinctrl-stm32.c

2066

if (bank->io_sync_control) {

drivers/pinctrl/stm32/pinctrl-stm32.c

2067

bool is_input = bank->pin_backup[offset].advcfg & STM32_GPIO_ADVCFGR_DLYPATH_MASK;

drivers/pinctrl/stm32/pinctrl-stm32.c

2069

ret = stm32_pconf_set_skew_delay(bank, offset,

drivers/pinctrl/stm32/pinctrl-stm32.c

2070

bank->pin_backup[offset].skew_delay,

drivers/pinctrl/stm32/pinctrl-stm32.c

2075

ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,

drivers/pinctrl/stm32/pinctrl-stm32.c

2076

bank->pin_backup[offset].advcfg);

drivers/pinctrl/stm32/pinctrl-stm32.c

2082

regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);

drivers/pinctrl/stm32/pinctrl-stm32.c

219

static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

222

bank->pin_backup[offset].value = value;

drivers/pinctrl/stm32/pinctrl-stm32.c

225

static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,

drivers/pinctrl/stm32/pinctrl-stm32.c

228

bank->pin_backup[offset].mode = mode;

drivers/pinctrl/stm32/pinctrl-stm32.c

229

bank->pin_backup[offset].alt = alt;

drivers/pinctrl/stm32/pinctrl-stm32.c

232

static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,

drivers/pinctrl/stm32/pinctrl-stm32.c

235

bank->pin_backup[offset].drive = drive;

drivers/pinctrl/stm32/pinctrl-stm32.c

238

static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,

drivers/pinctrl/stm32/pinctrl-stm32.c

241

bank->pin_backup[offset].speed = speed;

drivers/pinctrl/stm32/pinctrl-stm32.c

244

static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,

drivers/pinctrl/stm32/pinctrl-stm32.c

247

bank->pin_backup[offset].bias = bias;

drivers/pinctrl/stm32/pinctrl-stm32.c

250

static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 mask, u32 value)

drivers/pinctrl/stm32/pinctrl-stm32.c

254

val = bank->pin_backup[offset].advcfg;

drivers/pinctrl/stm32/pinctrl-stm32.c

257

bank->pin_backup[offset].advcfg = val;

drivers/pinctrl/stm32/pinctrl-stm32.c

260

static void stm32_gpio_backup_skew_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay)

drivers/pinctrl/stm32/pinctrl-stm32.c

262

bank->pin_backup[offset].skew_delay = delay;

drivers/pinctrl/stm32/pinctrl-stm32.c

267

static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)

drivers/pinctrl/stm32/pinctrl-stm32.c

271

cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

289

static bool stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)

drivers/pinctrl/stm32/pinctrl-stm32.c

293

cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

308

sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

316

writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

318

sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

326

static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)

drivers/pinctrl/stm32/pinctrl-stm32.c

330

cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

336

writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));

drivers/pinctrl/stm32/pinctrl-stm32.c

341

static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

344

stm32_gpio_backup_value(bank, offset, value);

drivers/pinctrl/stm32/pinctrl-stm32.c

349

writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);

drivers/pinctrl/stm32/pinctrl-stm32.c

354

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

355

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

357

int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);

drivers/pinctrl/stm32/pinctrl-stm32.c

365

if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

drivers/pinctrl/stm32/pinctrl-stm32.c

375

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

379

if (bank->rif_control)

drivers/pinctrl/stm32/pinctrl-stm32.c

380

stm32_gpio_rif_release_semaphore(bank, offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

385

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

387

return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));

drivers/pinctrl/stm32/pinctrl-stm32.c

393

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

395

__stm32_gpio_set(bank, offset, value);

drivers/pinctrl/stm32/pinctrl-stm32.c

403

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

405

__stm32_gpio_set(bank, offset, value);

drivers/pinctrl/stm32/pinctrl-stm32.c

413

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

416

fwspec.fwnode = bank->fwnode;

drivers/pinctrl/stm32/pinctrl-stm32.c

426

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

431

stm32_pmx_get_mode(bank, pin, &mode, &alt);

drivers/pinctrl/stm32/pinctrl-stm32.c

446

struct stm32_gpio_bank *bank = gpiochip_get_data(chip);

drivers/pinctrl/stm32/pinctrl-stm32.c

447

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

454

if (bank->secure_control) {

drivers/pinctrl/stm32/pinctrl-stm32.c

456

sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);

drivers/pinctrl/stm32/pinctrl-stm32.c

461

dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);

drivers/pinctrl/stm32/pinctrl-stm32.c

466

if (bank->rif_control) {

drivers/pinctrl/stm32/pinctrl-stm32.c

471

if (stm32_gpio_rif_valid(bank, i))

drivers/pinctrl/stm32/pinctrl-stm32.c

497

struct stm32_gpio_bank *bank = d->domain->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

501

if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))

drivers/pinctrl/stm32/pinctrl-stm32.c

505

level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);

drivers/pinctrl/stm32/pinctrl-stm32.c

506

if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||

drivers/pinctrl/stm32/pinctrl-stm32.c

507

(level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))

drivers/pinctrl/stm32/pinctrl-stm32.c

519

struct stm32_gpio_bank *bank = d->domain->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

538

bank->irq_type[d->hwirq] = type;

drivers/pinctrl/stm32/pinctrl-stm32.c

545

struct stm32_gpio_bank *bank = irq_data->domain->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

546

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

549

ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);

drivers/pinctrl/stm32/pinctrl-stm32.c

553

ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);

drivers/pinctrl/stm32/pinctrl-stm32.c

565

struct stm32_gpio_bank *bank = irq_data->domain->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

567

gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);

drivers/pinctrl/stm32/pinctrl-stm32.c

606

struct stm32_gpio_bank *bank = d->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

607

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

619

regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);

drivers/pinctrl/stm32/pinctrl-stm32.c

631

struct stm32_gpio_bank *bank = d->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

634

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

662

bank);

drivers/pinctrl/stm32/pinctrl-stm32.c

670

struct stm32_gpio_bank *bank = d->host_data;

drivers/pinctrl/stm32/pinctrl-stm32.c

671

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

935

static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,

drivers/pinctrl/stm32/pinctrl-stm32.c

938

struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);

drivers/pinctrl/stm32/pinctrl-stm32.c

945

spin_lock_irqsave(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

956

val = readl_relaxed(bank->base + alt_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

959

writel_relaxed(val, bank->base + alt_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

961

val = readl_relaxed(bank->base + STM32_GPIO_MODER);

drivers/pinctrl/stm32/pinctrl-stm32.c

964

writel_relaxed(val, bank->base + STM32_GPIO_MODER);

drivers/pinctrl/stm32/pinctrl-stm32.c

969

stm32_gpio_backup_mode(bank, pin, mode, alt);

drivers/pinctrl/stm32/pinctrl-stm32.c

972

spin_unlock_irqrestore(&bank->lock, flags);

drivers/pinctrl/stm32/pinctrl-stm32.c

977

static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt)

drivers/pinctrl/stm32/pinctrl-stm32.c

983

val = readl_relaxed(bank->base + alt_offset);

drivers/pinctrl/stm32/pinctrl-stm32.c

987

val = readl_relaxed(bank->base + STM32_GPIO_MODER);

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

169

int bank = (pin->pin.number - pin_base) / PINS_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

171

if (irq_bank_muxes[bank]) {

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

214

int bank = (pin->pin.number - pin_base) / PINS_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

216

int irq_mux = irq_bank_muxes[bank];

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

224

if (bank > last_bank)

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

232

if (bank > last_bank)

drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

233

last_bank = bank;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1240

u8 bank = d->hwirq / IRQ_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1242

return irq_set_irq_wake(pctl->irq[bank], on);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1311

unsigned long bank, reg, val;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1313

for (bank = 0; bank < pctl->desc->irq_banks; bank++)

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1314

if (irq == pctl->irq[bank])

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1317

WARN_ON(bank == pctl->desc->irq_banks);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1321

reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1329

bank * IRQ_PER_BANK + irqoffset);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

729

unsigned short bank;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

746

bank = pin / PINS_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

770

val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

775

reg &= ~BIT(bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

786

reg &= ~(1 << bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

787

writel(reg | val << bank,

drivers/pinctrl/sunxi/pinctrl-sunxi.c

890

unsigned short bank = offset / PINS_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

891

unsigned short bank_offset = bank - pctl->desc->pin_base /

drivers/pinctrl/sunxi/pinctrl-sunxi.c

906

snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

911

'A' + bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

916

"Couldn't enable bank P%c regulator\n", 'A' + bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

936

unsigned short bank = offset / PINS_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

937

unsigned short bank_offset = bank - pctl->desc->pin_base /

drivers/pinctrl/sunxi/pinctrl-sunxi.h

229

static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)

drivers/pinctrl/sunxi/pinctrl-sunxi.h

232

return bank;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

234

return desc->irq_bank_map[bank];

drivers/pinctrl/sunxi/pinctrl-sunxi.h

240

u8 bank = irq / IRQ_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

244

sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

253

static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)

drivers/pinctrl/sunxi/pinctrl-sunxi.h

255

return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

261

u8 bank = irq / IRQ_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

263

return sunxi_irq_ctrl_reg_from_bank(desc, bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.h

272

static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)

drivers/pinctrl/sunxi/pinctrl-sunxi.h

275

sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

278

static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)

drivers/pinctrl/sunxi/pinctrl-sunxi.h

281

sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

287

u8 bank = irq / IRQ_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

289

return sunxi_irq_status_reg_from_bank(desc, bank);

drivers/pinctrl/sunxi/pinctrl-sunxi.h

300

u8 bank = pin / PINS_PER_BANK;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

302

return GRP_CFG_REG + bank * 0x4;

drivers/pinctrl/sunxi/pinctrl-sunxi.h

37

#define SUNXI_PINCTRL_PIN(bank, pin) \

drivers/pinctrl/sunxi/pinctrl-sunxi.h

38

PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

drivers/pinctrl/tegra/pinctrl-tegra.c

30

static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)

drivers/pinctrl/tegra/pinctrl-tegra.c

32

return readl(pmx->regs[bank] + reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

35

static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)

drivers/pinctrl/tegra/pinctrl-tegra.c

37

writel_relaxed(val, pmx->regs[bank] + reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

39

pmx_readl(pmx, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

404

s8 *bank, s32 *reg, s8 *bit, s8 *width)

drivers/pinctrl/tegra/pinctrl-tegra.c

408

*bank = g->pupd_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

414

*bank = g->tri_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

420

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

426

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

432

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

438

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

444

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

451

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

454

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

462

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

465

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

472

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

478

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

484

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

490

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

496

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

503

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

506

*bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

514

*bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

572

s8 bank, bit, width;

drivers/pinctrl/tegra/pinctrl-tegra.c

578

ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,

drivers/pinctrl/tegra/pinctrl-tegra.c

583

val = pmx_readl(pmx, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

601

s8 bank, bit, width;

drivers/pinctrl/tegra/pinctrl-tegra.c

611

ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,

drivers/pinctrl/tegra/pinctrl-tegra.c

616

val = pmx_readl(pmx, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

642

pmx_writel(pmx, val, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

669

s8 bank, bit, width;

drivers/pinctrl/tegra/pinctrl-tegra.c

677

&bank, &reg, &bit, &width);

drivers/pinctrl/tegra/pinctrl-tegra.c

681

val = pmx_readl(pmx, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

739

unsigned int bank, reg;

drivers/pinctrl/tegra/pinctrl-tegra.c

742

bank = g->mux_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

745

bank = g->drv_bank;

drivers/pinctrl/tegra/pinctrl-tegra.c

749

val = pmx_readl(pmx, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra.c

751

pmx_writel(pmx, val, bank, reg);

drivers/pinctrl/tegra/pinctrl-tegra186.c

1377

slwf_w, bank) \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1379

.drv_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1405

#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1413

.mux_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1416

.pupd_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1419

.tri_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1640

#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \

drivers/pinctrl/tegra/pinctrl-tegra186.c

1652

PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1296

slwf_w, bank) \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1298

.drv_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1324

#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1332

.mux_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1335

.pupd_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1338

.tri_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1571

#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \

drivers/pinctrl/tegra/pinctrl-tegra194.c

1583

PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1397

slwf_w, bank) \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1399

.drv_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1425

#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1432

.mux_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1435

.pupd_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1438

.tri_bank = bank, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1615

#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \

drivers/pinctrl/tegra/pinctrl-tegra234.c

1627

PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \

drivers/pinctrl/vt8500/pinctrl-wmt.c

423

u32 bank = WMT_BANK_FROM_PIN(pin);

drivers/pinctrl/vt8500/pinctrl-wmt.c

425

u32 reg_pull_en = data->banks[bank].reg_pull_en;

drivers/pinctrl/vt8500/pinctrl-wmt.c

426

u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg;

drivers/pinctrl/vt8500/pinctrl-wmt.c

482

u32 bank = WMT_BANK_FROM_PIN(offset);

drivers/pinctrl/vt8500/pinctrl-wmt.c

484

u32 reg_dir = data->banks[bank].reg_dir;

drivers/pinctrl/vt8500/pinctrl-wmt.c

497

u32 bank = WMT_BANK_FROM_PIN(offset);

drivers/pinctrl/vt8500/pinctrl-wmt.c

499

u32 reg_data_in = data->banks[bank].reg_data_in;

drivers/pinctrl/vt8500/pinctrl-wmt.c

513

u32 bank = WMT_BANK_FROM_PIN(offset);

drivers/pinctrl/vt8500/pinctrl-wmt.c

515

u32 reg_data_out = data->banks[bank].reg_data_out;

drivers/pinctrl/vt8500/pinctrl-wmt.c

87

u32 bank = WMT_BANK_FROM_PIN(pin);

drivers/pinctrl/vt8500/pinctrl-wmt.c

89

u32 reg_en = data->banks[bank].reg_en;

drivers/pinctrl/vt8500/pinctrl-wmt.c

90

u32 reg_dir = data->banks[bank].reg_dir;

drivers/platform/cznic/turris-omnia-mcu-gpio.c

544

u32 bank, gpio;

drivers/platform/cznic/turris-omnia-mcu-gpio.c

552

bank = gpiospec->args[0];

drivers/platform/cznic/turris-omnia-mcu-gpio.c

555

switch (bank) {

drivers/power/supply/ab8500_charger.c

355

u8 bank;

drivers/power/supply/ab8500_charger.c

362

bank = 0x15;

drivers/power/supply/ab8500_charger.c

366

bank = AB8500_SYS_CTRL1_BLOCK;

drivers/power/supply/ab8500_charger.c

372

ret = abx500_get_register_interruptible(di->dev, bank, reg, &val);

drivers/power/supply/ab8500_charger.c

393

ret = abx500_set_register_interruptible(di->dev, bank, reg, val);

drivers/ras/amd/atl/umc.c

145

addr_hash.bank[i].xor_enable = FIELD_GET(ADDR_HASH_XOR_EN, temp);

drivers/ras/amd/atl/umc.c

146

addr_hash.bank[i].col_xor = FIELD_GET(ADDR_HASH_COL_XOR, temp);

drivers/ras/amd/atl/umc.c

147

addr_hash.bank[i].row_xor = FIELD_GET(ADDR_HASH_ROW_XOR, temp);

drivers/ras/amd/atl/umc.c

175

bit_shifts.bank[0] = 5 + FIELD_GET(ADDR_SEL_BANK0, temp);

drivers/ras/amd/atl/umc.c

176

bit_shifts.bank[1] = 5 + FIELD_GET(ADDR_SEL_BANK1, temp);

drivers/ras/amd/atl/umc.c

177

bit_shifts.bank[2] = 5 + FIELD_GET(ADDR_SEL_BANK2, temp);

drivers/ras/amd/atl/umc.c

178

bit_shifts.bank[3] = 5 + FIELD_GET(ADDR_SEL_BANK3, temp);

drivers/ras/amd/atl/umc.c

228

u16 i, col, row, bank, pc, sid;

drivers/ras/amd/atl/umc.c

232

bank = FIELD_GET(MI300_UMC_MCA_BANK, addr);

drivers/ras/amd/atl/umc.c

239

if (!addr_hash.bank[i].xor_enable)

drivers/ras/amd/atl/umc.c

242

temp = hweight16(col & addr_hash.bank[i].col_xor) & 1;

drivers/ras/amd/atl/umc.c

243

temp ^= hweight16(row & addr_hash.bank[i].row_xor) & 1;

drivers/ras/amd/atl/umc.c

244

bank ^= temp << i;

drivers/ras/amd/atl/umc.c

252

temp ^= hweight16((bank | sid << NUM_BANK_BITS) & addr_hash.bank_xor) & 1;

drivers/ras/amd/atl/umc.c

267

temp = (bank >> i) & 0x1;

drivers/ras/amd/atl/umc.c

268

addr |= temp << bit_shifts.bank[i];

drivers/ras/amd/atl/umc.c

293

pr_debug("Bank=%u Row=%u Column=%u PC=%u SID=%u", bank, row, col, pc, sid);

drivers/ras/amd/atl/umc.c

65

struct xor_bits bank[NUM_BANK_BITS];

drivers/ras/amd/atl/umc.c

75

u8 bank[NUM_BANK_BITS];

drivers/regulator/ab8500.c

1153

u8 bank;

drivers/regulator/ab8500.c

1160

.bank = _bank, \

drivers/regulator/ab8500.c

403

u8 bank, reg, mask, val;

drivers/regulator/ab8500.c

413

bank = info->mode_bank;

drivers/regulator/ab8500.c

417

bank = info->update_bank;

drivers/regulator/ab8500.c

461

bank, reg, mask, val);

drivers/regulator/ab8500.c

471

info->desc.name, bank, reg,

drivers/regulator/da9121-regulator.c

144

#define DA9121_STATUS(id, bank, name, notification, warning) \

drivers/regulator/da9121-regulator.c

145

{ id, bank, \

drivers/regulator/da9121-regulator.c

146

DA9121_MASK_SYS_STATUS_##bank##_##name, \

drivers/regulator/da9121-regulator.c

147

DA9121_MASK_SYS_EVENT_##bank##_E_##name, \

drivers/regulator/da9121-regulator.c

148

DA9121_MASK_SYS_MASK_##bank##_M_##name, \

drivers/regulator/da9121-regulator.c

152

#define DA9xxx_STATUS(id, bank, name, notification, warning) \

drivers/regulator/da9121-regulator.c

153

{ id, bank, \

drivers/regulator/da9121-regulator.c

154

DA9xxx_MASK_SYS_STATUS_##bank##_##name, \

drivers/regulator/da9121-regulator.c

155

DA9xxx_MASK_SYS_EVENT_##bank##_E_##name, \

drivers/regulator/da9121-regulator.c

156

DA9xxx_MASK_SYS_MASK_##bank##_M_##name, \

drivers/reset/hisilicon/hi6220_reset.c

48

u32 bank = idx >> 8;

drivers/reset/hisilicon/hi6220_reset.c

50

u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10;

drivers/reset/hisilicon/hi6220_reset.c

60

u32 bank = idx >> 8;

drivers/reset/hisilicon/hi6220_reset.c

62

u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10;

drivers/reset/reset-simple.c

35

int bank = id / (reg_width * BITS_PER_BYTE);

drivers/reset/reset-simple.c

42

reg = readl(data->membase + (bank * reg_width));

drivers/reset/reset-simple.c

47

writel(reg, data->membase + (bank * reg_width));

drivers/reset/reset-simple.c

89

int bank = id / (reg_width * BITS_PER_BYTE);

drivers/reset/reset-simple.c

93

reg = readl(data->membase + (bank * reg_width));

drivers/reset/reset-zynq.c

34

int bank = id / BITS_PER_LONG;

drivers/reset/reset-zynq.c

38

bank, offset);

drivers/reset/reset-zynq.c

41

priv->offset + (bank * 4),

drivers/reset/reset-zynq.c

51

int bank = id / BITS_PER_LONG;

drivers/reset/reset-zynq.c

55

bank, offset);

drivers/reset/reset-zynq.c

58

priv->offset + (bank * 4),

drivers/reset/reset-zynq.c

68

int bank = id / BITS_PER_LONG;

drivers/reset/reset-zynq.c

74

bank, offset);

drivers/reset/reset-zynq.c

76

ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);

drivers/rtc/rtc-r7301.c

129

static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)

drivers/rtc/rtc-r7301.c

133

if (bank == priv->bank)

drivers/rtc/rtc-r7301.c

136

if (bank & BIT(0))

drivers/rtc/rtc-r7301.c

138

if (bank & BIT(1))

drivers/rtc/rtc-r7301.c

145

priv->bank = bank;

drivers/rtc/rtc-r7301.c

408

priv->bank = -1;

drivers/rtc/rtc-r7301.c

56

u8 bank;

drivers/scsi/advansys.c

3606

static void AscSetBank(PortAddr iop_base, uchar bank)

drivers/scsi/advansys.c

3614

if (bank == 1) {

drivers/scsi/advansys.c

3616

} else if (bank == 2) {

drivers/scsi/qla2xxx/qla_tmpl.c

195

ulong bank = le32_to_cpu(ent->t258.bank);

drivers/scsi/qla2xxx/qla_tmpl.c

203

qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);

drivers/scsi/qla2xxx/qla_tmpl.c

215

ulong bank = le32_to_cpu(ent->t259.bank);

drivers/scsi/qla2xxx/qla_tmpl.c

222

qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);

drivers/scsi/qla2xxx/qla_tmpl.h

103

__le32 bank;

drivers/scsi/qla2xxx/qla_tmpl.h

112

__le32 bank;

drivers/soc/mediatek/mtk-mmsys.h

81

#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))

drivers/soundwire/amd_manager.c

481

unsigned int bank)

drivers/soundwire/amd_manager.c

519

enum sdw_reg_bank bank)

drivers/soundwire/amd_manager.c

596

unsigned int bank)

drivers/soundwire/cadence_master.c

1515

struct sdw_port_params *p_params, unsigned int bank)

drivers/soundwire/cadence_master.c

1531

if (bank) {

drivers/soundwire/cadence_master.c

1555

enum sdw_reg_bank bank)

drivers/soundwire/cadence_master.c

1585

if (bank) {

drivers/soundwire/cadence_master.c

1644

struct sdw_enable_ch *enable_ch, unsigned int bank)

drivers/soundwire/cadence_master.c

1649

if (bank)

drivers/soundwire/qcom.c

1020

unsigned int bank)

drivers/soundwire/qcom.c

1031

enum sdw_reg_bank bank)

drivers/soundwire/qcom.c

1039

reg = SWRM_DPn_PORT_CTRL_BANK(offset, params->port_num, bank);

drivers/soundwire/qcom.c

1054

reg = SWRM_DPn_SAMPLECTRL2_BANK(offset, params->port_num, bank);

drivers/soundwire/qcom.c

1063

reg = SWRM_DPn_PORT_CTRL_2_BANK(offset, params->port_num, bank);

drivers/soundwire/qcom.c

1074

reg = SWRM_DPn_BLOCK_CTRL2_BANK(offset, params->port_num, bank);

drivers/soundwire/qcom.c

1083

reg = SWRM_DPn_PORT_HCTRL_BANK(offset, params->port_num, bank);

drivers/soundwire/qcom.c

1098

reg = SWRM_DPn_BLOCK_CTRL3_BANK(offset, params->port_num, bank);

drivers/soundwire/qcom.c

1108

unsigned int bank)

drivers/soundwire/qcom.c

1115

reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank);

drivers/soundwire/stream.c

485

prep_ch.bank = bus->params.next_bank;

drivers/soundwire/stream.c

559

prep_ch.bank = bus->params.next_bank;

drivers/spmi/spmi-mtk-pmif.c

496

u8 bank = bit / 7;

drivers/spmi/spmi-mtk-pmif.c

497

u8 sid = ((i - SPMI_SLV_3_0_EINT) * 4) + bank;

drivers/spmi/spmi-mtk-pmif.c

499

val &= ~(PMIF_RCS_IRQ_MASK << (8 * bank));

drivers/staging/media/av7110/dvb_filter.h

203

int bank;

drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c

446

struct adapter *padapter, u8 bank

drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c

452

switch (bank) {

drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c

717

u8 bank;

drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c

740

for (bank = 1; bank < 3; bank++) { /* 8723b Max bake 0~2 */

drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c

741

if (hal_EfuseSwitchToBank(padapter, bank) == false)

drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c

802

used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1;

drivers/thermal/mediatek/auxadc_thermal.c

780

static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)

drivers/thermal/mediatek/auxadc_thermal.c

782

struct mtk_thermal *mt = bank->mt;

drivers/thermal/mediatek/auxadc_thermal.c

790

val |= bank->id;

drivers/thermal/mediatek/auxadc_thermal.c

801

static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)

drivers/thermal/mediatek/auxadc_thermal.c

803

struct mtk_thermal *mt = bank->mt;

drivers/thermal/mediatek/auxadc_thermal.c

816

static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)

drivers/thermal/mediatek/auxadc_thermal.c

818

struct mtk_thermal *mt = bank->mt;

drivers/thermal/mediatek/auxadc_thermal.c

823

for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {

drivers/thermal/mediatek/auxadc_thermal.c

827

mt, conf->bank_data[bank->id].sensors[i], raw);

drivers/thermal/mediatek/auxadc_thermal.c

855

struct mtk_thermal_bank *bank = &mt->banks[i];

drivers/thermal/mediatek/auxadc_thermal.c

857

mtk_thermal_get_bank(bank);

drivers/thermal/mediatek/auxadc_thermal.c

859

tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));

drivers/thermal/mediatek/auxadc_thermal.c

861

mtk_thermal_put_bank(bank);

drivers/thermal/mediatek/auxadc_thermal.c

877

struct mtk_thermal_bank *bank = &mt->banks[num];

drivers/thermal/mediatek/auxadc_thermal.c

884

bank->id = num;

drivers/thermal/mediatek/auxadc_thermal.c

885

bank->mt = mt;

drivers/thermal/mediatek/auxadc_thermal.c

887

mtk_thermal_get_bank(bank);

drivers/thermal/mediatek/auxadc_thermal.c

979

mtk_thermal_put_bank(bank);

drivers/tty/mxser.c

314

static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)

drivers/tty/mxser.c

316

return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,

drivers/uio/uio_fsl_elbc_gpcm.c

105

struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank];

drivers/uio/uio_fsl_elbc_gpcm.c

117

reg_br_cur = in_be32(&bank->br);

drivers/uio/uio_fsl_elbc_gpcm.c

118

reg_or_cur = in_be32(&bank->or);

drivers/uio/uio_fsl_elbc_gpcm.c

132

out_be32(&bank->br, reg_new | BR_V);

drivers/uio/uio_fsl_elbc_gpcm.c

140

out_be32(&bank->or, reg_new);

drivers/uio/uio_fsl_elbc_gpcm.c

224

if (priv->bank >= MAX_BANKS) {

drivers/uio/uio_fsl_elbc_gpcm.c

266

ret = of_property_read_u32(node, "reg", &priv->bank);

drivers/uio/uio_fsl_elbc_gpcm.c

345

reg_br_cur = in_be32(&priv->lbc->bank[priv->bank].br);

drivers/uio/uio_fsl_elbc_gpcm.c

346

reg_or_cur = in_be32(&priv->lbc->bank[priv->bank].or);

drivers/uio/uio_fsl_elbc_gpcm.c

375

out_be32(&priv->lbc->bank[priv->bank].or, reg_or_new);

drivers/uio/uio_fsl_elbc_gpcm.c

376

out_be32(&priv->lbc->bank[priv->bank].br, reg_br_new);

drivers/uio/uio_fsl_elbc_gpcm.c

424

priv->name, (unsigned long long)res.start, priv->bank,

drivers/uio/uio_fsl_elbc_gpcm.c

58

u32 bank;

drivers/uio/uio_fsl_elbc_gpcm.c

86

struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank];

drivers/uio/uio_fsl_elbc_gpcm.c

90

in_be32(&bank->br));

drivers/uio/uio_fsl_elbc_gpcm.c

94

in_be32(&bank->or));

drivers/usb/host/sl811-hcd.c

139

u8 bank,

drivers/usb/host/sl811-hcd.c

147

addr = SL811HS_PACKET_BUF(bank == 0);

drivers/usb/host/sl811-hcd.c

153

sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);

drivers/usb/host/sl811-hcd.c

159

sl811_write(sl811, bank + SL11H_HOSTCTLREG,

drivers/usb/host/sl811-hcd.c

170

u8 bank,

drivers/usb/host/sl811-hcd.c

181

sl811_write(sl811, bank + SL11H_BUFADDRREG, 0);

drivers/usb/host/sl811-hcd.c

190

sl811_write(sl811, bank + SL11H_HOSTCTLREG, control);

drivers/usb/host/sl811-hcd.c

204

u8 bank,

drivers/usb/host/sl811-hcd.c

214

addr = SL811HS_PACKET_BUF(bank == 0);

drivers/usb/host/sl811-hcd.c

221

sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);

drivers/usb/host/sl811-hcd.c

226

sl811_write(sl811, bank + SL11H_HOSTCTLREG, control);

drivers/usb/host/sl811-hcd.c

240

u8 bank,

drivers/usb/host/sl811-hcd.c

258

addr = SL811HS_PACKET_BUF(bank == 0);

drivers/usb/host/sl811-hcd.c

264

sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);

drivers/usb/host/sl811-hcd.c

269

sl811_write(sl811, bank + SL11H_HOSTCTLREG,

drivers/usb/host/sl811-hcd.c

303

static struct sl811h_ep *start(struct sl811 *sl811, u8 bank)

drivers/usb/host/sl811-hcd.c

328

if ((bank && sl811->active_b == ep) || sl811->active_a == ep)

drivers/usb/host/sl811-hcd.c

382

in_packet(sl811, ep, urb, bank, control);

drivers/usb/host/sl811-hcd.c

385

out_packet(sl811, ep, urb, bank, control);

drivers/usb/host/sl811-hcd.c

388

setup_packet(sl811, ep, urb, bank, control);

drivers/usb/host/sl811-hcd.c

391

status_packet(sl811, ep, urb, bank, control);

drivers/usb/host/sl811-hcd.c

476

done(struct sl811 *sl811, struct sl811h_ep *ep, u8 bank)

drivers/usb/host/sl811-hcd.c

485

status = sl811_read(sl811, bank + SL11H_PKTSTATREG);

drivers/usb/host/sl811-hcd.c

529

bank + SL11H_XFERCNTREG);

drivers/usb/host/sl811-hcd.c

535

sl811_read_buf(sl811, SL811HS_PACKET_BUF(bank == 0),

drivers/usb/host/sl811-hcd.c

568

PACKET("...STALL_%02x qh%p\n", bank, ep);

drivers/usb/host/sl811-hcd.c

582

bank, status, ep, urbstat);

drivers/video/backlight/lm3630a_bl.c

409

u32 bank, val;

drivers/video/backlight/lm3630a_bl.c

412

ret = fwnode_property_read_u32(node, "reg", &bank);

drivers/video/backlight/lm3630a_bl.c

416

if (bank != LM3630A_BANK_0 && bank != LM3630A_BANK_1)

drivers/video/backlight/lm3630a_bl.c

419

led_sources = lm3630a_parse_led_sources(node, BIT(bank));

drivers/video/backlight/lm3630a_bl.c

430

if (bank) {

drivers/video/backlight/lm3630a_bl.c

452

if (bank)

drivers/video/backlight/lm3630a_bl.c

461

if (bank)

drivers/video/backlight/lm3630a_bl.c

469

if (bank)

drivers/xen/mcelog.c

281

m.bank = mc_bank->mc_bank;

include/cxl/event.h

136

u8 bank;

include/cxl/event.h

72

u8 bank;

include/dt-bindings/gpio/uniphier-gpio.h

13

#define UNIPHIER_GPIO_PORT(bank, line) \

include/dt-bindings/gpio/uniphier-gpio.h

14

((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))

include/dt-bindings/pinctrl/amlogic,pinctrl.h

44

#define AML_PINMUX(bank, offset, mode) (((((bank) << 8) + (offset)) << 8) | (mode))

include/linux/amd-iommu.h

65

int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,

include/linux/amd-iommu.h

67

int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,

include/linux/cper.h

474

u16 bank;

include/linux/cper.h

494

u16 bank;

include/linux/cper.h

514

u16 bank;

include/linux/dmi.h

114

extern void dmi_memdev_name(u16 handle, const char **bank, const char **device);

include/linux/dmi.h

144

static inline void dmi_memdev_name(u16 handle, const char **bank,

include/linux/ethtool.h

670

u8 bank;

include/linux/gpio/gpio-nomadik.h

58

unsigned int bank;

include/linux/hwspinlock.h

58

int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev,

include/linux/hwspinlock.h

60

int hwspin_lock_unregister(struct hwspinlock_device *bank);

include/linux/hwspinlock.h

74

struct hwspinlock_device *bank);

include/linux/hwspinlock.h

76

struct hwspinlock_device *bank,

include/linux/jz4780-nemc.h

34

extern void jz4780_nemc_set_type(struct device *dev, unsigned int bank,

include/linux/jz4780-nemc.h

36

extern void jz4780_nemc_assert(struct device *dev, unsigned int bank,

include/linux/mfd/abx500.h

26

u8 bank;

include/linux/mfd/abx500.h

31

int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,

include/linux/mfd/abx500.h

33

int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,

include/linux/mfd/abx500.h

35

int abx500_get_register_page_interruptible(struct device *dev, u8 bank,

include/linux/mfd/abx500.h

37

int abx500_set_register_page_interruptible(struct device *dev, u8 bank,

include/linux/mfd/abx500.h

51

int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,

include/linux/scx200_gpio.h

11

#define __SCx200_GPIO_BANK unsigned bank = index>>5

include/linux/scx200_gpio.h

12

#define __SCx200_GPIO_IOADDR unsigned short ioaddr = scx200_gpio_base+0x10*bank

include/linux/scx200_gpio.h

13

#define __SCx200_GPIO_SHADOW unsigned long *shadow = scx200_gpio_shadow+bank

include/linux/scx200_gpio.h

36

return (scx200_gpio_shadow[bank] & (1<<index)) ? 1 : 0;

include/linux/soundwire/sdw.h

559

unsigned int bank;

include/linux/soundwire/sdw.h

809

unsigned int bank);

include/linux/soundwire/sdw.h

812

enum sdw_reg_bank bank);

include/linux/soundwire/sdw.h

815

struct sdw_enable_ch *enable_ch, unsigned int bank);

include/soc/mediatek/smi.h

25

unsigned char bank[32];

include/sound/opl3.h

254

unsigned char bank;

include/sound/opl3.h

363

int prog, int bank, int type,

include/sound/opl3.h

367

struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank,

include/sound/soundfont.h

105

int preset, int bank,

include/sound/soundfont.h

21

unsigned char bank; /* Midi bank for this zone */

include/sound/ump_convert.h

32

struct ump_cvt_to_ump_bank bank[16]; /* per channel */

include/sound/ump_msg.h

406

u32 bank:8;

include/sound/ump_msg.h

413

u32 bank:8;

include/trace/events/mce.h

43

__field( u8, bank )

include/trace/events/mce.h

66

__entry->bank = err->m.bank;

include/trace/events/mce.h

75

__entry->bank, __entry->status,

include/uapi/sound/asound_fm.h

113

unsigned char bank;

include/uapi/sound/sfnt_info.h

131

unsigned char bank; /* midi bank number */

include/xen/interface/xen-mca.h

353

__u8 bank; /* machine check bank */

net/ethtool/eeprom.c

123

page_data.bank = request->bank;

net/ethtool/eeprom.c

13

u8 bank;

net/ethtool/eeprom.c

192

request->bank = nla_get_u8(tb[ETHTOOL_A_MODULE_EEPROM_BANK]);

scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h

13

#define UNIPHIER_GPIO_PORT(bank, line) \

scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h

14

((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))

scripts/dtc/include-prefixes/dt-bindings/pinctrl/amlogic,pinctrl.h

44

#define AML_PINMUX(bank, offset, mode) (((((bank) << 8) + (offset)) << 8) | (mode))

sound/core/seq/seq_ump_convert.c

1015

data->rpn.bank = (event->data.control.param >> 7) & 0x7f;

sound/core/seq/seq_ump_convert.c

272

ev->data.control.param = (val->rpn.bank << 7) | val->rpn.index;

sound/core/seq/seq_ump_convert.c

816

data->rpn.bank = cc->cc_rpn_msb;

sound/core/seq/seq_ump_convert.c

820

data->rpn.bank = cc->cc_nrpn_msb;

sound/core/ump_convert.c

152

buf[2] = midi2->rpn.bank;

sound/core/ump_convert.c

311

midi2->rpn.bank = cc->cc_rpn_msb;

sound/core/ump_convert.c

315

midi2->rpn.bank = cc->cc_nrpn_msb;

sound/core/ump_convert.c

355

cc = &cvt->bank[channel];

sound/drivers/opl3/opl3_midi.c

300

unsigned char prg, bank;

sound/drivers/opl3/opl3_midi.c

319

bank = 128;

sound/drivers/opl3/opl3_midi.c

322

bank = chan->gm_bank_select;

sound/drivers/opl3/opl3_midi.c

331

bank = 127;

sound/drivers/opl3/opl3_midi.c

343

patch = snd_opl3_find_patch(opl3, prg, bank, 0);

sound/drivers/opl3/opl3_midi.c

579

bank = 128;

sound/drivers/opl3/opl3_midi.c

583

bank = 0;

sound/drivers/opl3/opl3_synth.c

201

err = snd_opl3_load_patch(opl3, inst.prog, inst.bank, type,

sound/drivers/opl3/opl3_synth.c

240

int prog, int bank, int type,

sound/drivers/opl3/opl3_synth.c

248

patch = snd_opl3_find_patch(opl3, prog, bank, 1);

sound/drivers/opl3/opl3_synth.c

302

struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank,

sound/drivers/opl3/opl3_synth.c

306

unsigned int key = (prog + bank) % OPL3_PATCH_HASH_SIZE;

sound/drivers/opl3/opl3_synth.c

310

if (patch->prog == prog && patch->bank == bank)

sound/drivers/opl3/opl3_synth.c

320

patch->bank = bank;

sound/isa/msnd/msnd.c

234

int snd_msnd_DARQ(struct snd_msnd *chip, int bank)

sound/isa/msnd/msnd.c

249

bank * DAQDS__size + DAQDS_wStart;

sound/isa/msnd/msnd.c

261

DAQD = bank * DAQDS__size + chip->mappedbase + DARQ_DATA_BUFF;

sound/isa/msnd/msnd.c

270

(char *)(chip->base + bank * DAR_BUFF_SIZE),

sound/pci/au88x0/au88x0_wt.h

21

#define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */

sound/pci/au88x0/au88x0_wt.h

22

#define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */

sound/pci/au88x0/au88x0_wt.h

23

#define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */

sound/pci/au88x0/au88x0_wt.h

24

#define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */

sound/pci/au88x0/au88x0_wt.h

25

#define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */

sound/pci/au88x0/au88x0_wt.h

26

#define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */

sound/pci/cs46xx/cs46xx_lib.c

310

unsigned int bank = offset >> 16;

sound/pci/cs46xx/cs46xx_lib.c

315

dst = chip->region.idx[bank+1].remap_addr + offset;

sound/pci/cs46xx/cs46xx_lib.c

473

unsigned int bank = offset >> 16;

sound/pci/cs46xx/cs46xx_lib.c

478

dst = chip->region.idx[bank+1].remap_addr + offset;

sound/pci/cs46xx/cs46xx_lib.h

47

unsigned int bank = reg >> 16;

sound/pci/cs46xx/cs46xx_lib.h

55

writel(val, chip->region.idx[bank+1].remap_addr + offset);

sound/pci/cs46xx/cs46xx_lib.h

60

unsigned int bank = reg >> 16;

sound/pci/cs46xx/cs46xx_lib.h

62

return readl(chip->region.idx[bank+1].remap_addr + offset);

sound/pci/ymfpci/ymfpci.h

235

struct snd_ymfpci_playback_bank *bank;

sound/pci/ymfpci/ymfpci_main.c

2052

int voice, bank, reg;

sound/pci/ymfpci/ymfpci_main.c

2085

chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;

sound/pci/ymfpci/ymfpci_main.c

2087

for (bank = 0; bank < 2; bank++) {

sound/pci/ymfpci/ymfpci_main.c

2088

chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;

sound/pci/ymfpci/ymfpci_main.c

2098

for (bank = 0; bank < 2; bank++) {

sound/pci/ymfpci/ymfpci_main.c

2099

chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;

sound/pci/ymfpci/ymfpci_main.c

2108

for (bank = 0; bank < 2; bank++) {

sound/pci/ymfpci/ymfpci_main.c

2109

chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;

sound/pci/ymfpci/ymfpci_main.c

285

pos = le32_to_cpu(voice->bank[chip->active_bank].start);

sound/pci/ymfpci/ymfpci_main.c

308

struct snd_ymfpci_playback_bank *bank;

sound/pci/ymfpci/ymfpci_main.c

311

bank = &voice->bank[next_bank];

sound/pci/ymfpci/ymfpci_main.c

313

bank->left_gain_end = volume;

sound/pci/ymfpci/ymfpci_main.c

315

bank->eff2_gain_end = volume;

sound/pci/ymfpci/ymfpci_main.c

317

bank = &ypcm->voices[1]->bank[next_bank];

sound/pci/ymfpci/ymfpci_main.c

319

bank->right_gain_end = volume;

sound/pci/ymfpci/ymfpci_main.c

321

bank->eff3_gain_end = volume;

sound/pci/ymfpci/ymfpci_main.c

468

struct snd_ymfpci_playback_bank *bank;

sound/pci/ymfpci/ymfpci_main.c

512

bank = &voice->bank[nbank];

sound/pci/ymfpci/ymfpci_main.c

513

memset(bank, 0, sizeof(*bank));

sound/pci/ymfpci/ymfpci_main.c

514

bank->format = cpu_to_le32(format);

sound/pci/ymfpci/ymfpci_main.c

515

bank->base = cpu_to_le32(runtime->dma_addr);

sound/pci/ymfpci/ymfpci_main.c

516

bank->loop_end = cpu_to_le32(ypcm->buffer_size);

sound/pci/ymfpci/ymfpci_main.c

517

bank->lpfQ = cpu_to_le32(lpfQ);

sound/pci/ymfpci/ymfpci_main.c

518

bank->delta =

sound/pci/ymfpci/ymfpci_main.c

519

bank->delta_end = cpu_to_le32(delta);

sound/pci/ymfpci/ymfpci_main.c

520

bank->lpfK =

sound/pci/ymfpci/ymfpci_main.c

521

bank->lpfK_end = cpu_to_le32(lpfK);

sound/pci/ymfpci/ymfpci_main.c

522

bank->eg_gain =

sound/pci/ymfpci/ymfpci_main.c

523

bank->eg_gain_end = cpu_to_le32(0x40000000);

sound/pci/ymfpci/ymfpci_main.c

527

bank->left_gain =

sound/pci/ymfpci/ymfpci_main.c

528

bank->left_gain_end = vol_left;

sound/pci/ymfpci/ymfpci_main.c

531

bank->right_gain =

sound/pci/ymfpci/ymfpci_main.c

532

bank->right_gain_end = vol_right;

sound/pci/ymfpci/ymfpci_main.c

538

bank->eff2_gain =

sound/pci/ymfpci/ymfpci_main.c

539

bank->eff2_gain_end = vol_left;

sound/pci/ymfpci/ymfpci_main.c

542

bank->eff3_gain =

sound/pci/ymfpci/ymfpci_main.c

543

bank->eff3_gain_end = vol_right;

sound/pci/ymfpci/ymfpci_main.c

551

bank->eff3_gain =

sound/pci/ymfpci/ymfpci_main.c

552

bank->eff3_gain_end = vol_left;

sound/pci/ymfpci/ymfpci_main.c

555

bank->eff2_gain =

sound/pci/ymfpci/ymfpci_main.c

556

bank->eff2_gain_end = vol_right;

sound/pci/ymfpci/ymfpci_main.c

672

struct snd_ymfpci_capture_bank * bank;

sound/pci/ymfpci/ymfpci_main.c

702

bank = chip->bank_capture[ypcm->capture_bank_number][nbank];

sound/pci/ymfpci/ymfpci_main.c

703

bank->base = cpu_to_le32(runtime->dma_addr);

sound/pci/ymfpci/ymfpci_main.c

704

bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);

sound/pci/ymfpci/ymfpci_main.c

705

bank->start = 0;

sound/pci/ymfpci/ymfpci_main.c

706

bank->num_of_loops = 0;

sound/pci/ymfpci/ymfpci_main.c

720

return le32_to_cpu(voice->bank[chip->active_bank].start);

sound/soc/amd/acp-pcm-dma.c

1188

u16 bank;

sound/soc/amd/acp-pcm-dma.c

1212

for (bank = 1; bank <= 4; bank++)

sound/soc/amd/acp-pcm-dma.c

1214

bank, false);

sound/soc/amd/acp-pcm-dma.c

1227

for (bank = 5; bank <= 8; bank++)

sound/soc/amd/acp-pcm-dma.c

1229

bank, false);

sound/soc/amd/acp-pcm-dma.c

1339

u16 bank;

sound/soc/amd/acp-pcm-dma.c

1357

for (bank = 1; bank <= 4; bank++)

sound/soc/amd/acp-pcm-dma.c

1358

acp_set_sram_bank_state(adata->acp_mmio, bank,

sound/soc/amd/acp-pcm-dma.c

1367

for (bank = 5; bank <= 8; bank++)

sound/soc/amd/acp-pcm-dma.c

1368

acp_set_sram_bank_state(adata->acp_mmio, bank,

sound/soc/amd/acp-pcm-dma.c

504

static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,

sound/soc/amd/acp-pcm-dma.c

510

if (bank < 32) {

sound/soc/amd/acp-pcm-dma.c

516

bank -= 32;

sound/soc/amd/acp-pcm-dma.c

523

if (val & (1 << bank)) {

sound/soc/amd/acp-pcm-dma.c

527

val &= ~(1 << bank);

sound/soc/amd/acp-pcm-dma.c

535

val |= 1 << bank;

sound/soc/amd/acp-pcm-dma.c

544

pr_err("ACP SRAM bank %d state change failed\n", bank);

sound/soc/amd/acp-pcm-dma.c

554

u16 bank;

sound/soc/amd/acp-pcm-dma.c

639

for (bank = 1; bank < 48; bank++)

sound/soc/amd/acp-pcm-dma.c

640

acp_set_sram_bank_state(acp_mmio, bank, false);

sound/soc/amd/acp-pcm-dma.c

773

u16 bank;

sound/soc/amd/acp-pcm-dma.c

829

for (bank = 1; bank <= 4; bank++)

sound/soc/amd/acp-pcm-dma.c

831

bank, true);

sound/soc/amd/acp-pcm-dma.c

835

for (bank = 5; bank <= 8; bank++)

sound/soc/amd/acp-pcm-dma.c

837

bank, true);

sound/soc/codecs/rt5677.c

4720

unsigned int bank = offset / 5;

sound/soc/codecs/rt5677.c

4722

unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2;

sound/soc/codecs/wcd938x.c

1092

int bank;

sound/soc/codecs/wcd938x.c

1095

bank = sdw_slave_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev);

sound/soc/codecs/wcd938x.c

1120

wcd938x_set_swr_clk_rate(component, rate, bank);

sound/soc/codecs/wcd938x.c

1122

wcd938x_set_swr_clk_rate(component, rate, !bank);

sound/soc/codecs/wcd938x.c

1128

wcd938x_set_swr_clk_rate(component, rate, !bank);

sound/soc/codecs/wcd938x.c

1129

wcd938x_set_swr_clk_rate(component, rate, bank);

sound/soc/codecs/wcd938x.c

313

static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)

sound/soc/codecs/wcd938x.c

315

u8 mask = (bank ? 0xF0 : 0x0F);

sound/soc/codecs/wcd938x.c

320

val = (bank ? 0x60 : 0x06);

sound/soc/codecs/wcd938x.c

323

val = (bank ? 0x50 : 0x05);

sound/soc/codecs/wcd938x.c

326

val = (bank ? 0x30 : 0x03);

sound/soc/codecs/wcd938x.c

329

val = (bank ? 0x10 : 0x01);

sound/soc/codecs/wcd939x.c

1015

int bank;

sound/soc/codecs/wcd939x.c

1018

bank = sdw_slave_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev);

sound/soc/codecs/wcd939x.c

1038

wcd939x_set_swr_clk_rate(component, rate, bank);

sound/soc/codecs/wcd939x.c

1039

wcd939x_set_swr_clk_rate(component, rate, !bank);

sound/soc/codecs/wcd939x.c

1045

wcd939x_set_swr_clk_rate(component, rate, !bank);

sound/soc/codecs/wcd939x.c

1046

wcd939x_set_swr_clk_rate(component, rate, bank);

sound/soc/codecs/wcd939x.c

332

static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)

sound/soc/codecs/wcd939x.c

334

u8 mask = (bank ? 0xF0 : 0x0F);

sound/synth/emux/emux_synth.c

874

int preset, bank, def_preset, def_bank;

sound/synth/emux/emux_synth.c

876

bank = get_bank(port, chan);

sound/synth/emux/emux_synth.c

879

if (SF_IS_DRUM_BANK(bank)) {

sound/synth/emux/emux_synth.c

881

def_bank = bank;

sound/synth/emux/emux_synth.c

887

return snd_soundfont_search_zone(emu->sflist, notep, vel, preset, bank,

sound/synth/emux/soundfont.c

1110

zone->bank = 0;

sound/synth/emux/soundfont.c

1175

zone = search_first_zone(sflist, cur->bank, cur->instr, cur->v.low);

sound/synth/emux/soundfont.c

1191

index = get_index(cur->bank, cur->instr, cur->v.low);

sound/synth/emux/soundfont.c

1208

index = get_index(zp->bank, zp->instr, zp->v.low);

sound/synth/emux/soundfont.c

1231

int preset, int bank,

sound/synth/emux/soundfont.c

1244

nvoices = search_zones(sflist, notep, vel, preset, bank,

sound/synth/emux/soundfont.c

1247

if (preset != def_preset || bank != def_bank)

sound/synth/emux/soundfont.c

1260

search_first_zone(struct snd_sf_list *sflist, int bank, int preset, int key)

sound/synth/emux/soundfont.c

1265

index = get_index(bank, preset, key);

sound/synth/emux/soundfont.c

1269

if (zp->instr == preset && zp->bank == bank)

sound/synth/emux/soundfont.c

1281

int preset, int bank, struct snd_sf_zone **table,

sound/synth/emux/soundfont.c

1287

zp = search_first_zone(sflist, bank, preset, *notep);

sound/synth/emux/soundfont.c

1296

bank = zp->v.end;

sound/synth/emux/soundfont.c

1303

preset, bank, table,

sound/synth/emux/soundfont.c

1325

get_index(int bank, int instr, int key)

sound/synth/emux/soundfont.c

1328

if (SF_IS_DRUM_BANK(bank))

sound/synth/emux/soundfont.c

157

int bank, instr;

sound/synth/emux/soundfont.c

158

bank = ((unsigned short)patch.optarg >> 8) & 0xff;

sound/synth/emux/soundfont.c

160

if (! remove_info(sflist, sflist->currsf, bank, instr))

sound/synth/emux/soundfont.c

397

zp->bank == map.map_bank &&

sound/synth/emux/soundfont.c

420

zp->bank = map.map_bank;

sound/synth/emux/soundfont.c

44

int bank, int instr);

sound/synth/emux/soundfont.c

441

int bank, int instr)

sound/synth/emux/soundfont.c

450

p->bank == bank && p->instr == instr) {

sound/synth/emux/soundfont.c

517

zone->bank == hdr.bank &&

sound/synth/emux/soundfont.c

524

remove_info(sflist, sf, hdr.bank, hdr.instr);

sound/synth/emux/soundfont.c

539

tmpzone.bank = hdr.bank;

sound/synth/emux/soundfont.c

55

int bank, int preset, int key);

sound/synth/emux/soundfont.c

552

zone->bank = tmpzone.bank;

sound/synth/emux/soundfont.c

57

int preset, int bank, struct snd_sf_zone **table,

sound/synth/emux/soundfont.c

59

static int get_index(int bank, int instr, int key);

sound/usb/caiaq/control.c

123

int bank = 0;

sound/usb/caiaq/control.c

127

bank = 0x1e;

sound/usb/caiaq/control.c

131

snd_usb_caiaq_send_command_bank(cdev, cmd, bank,

sound/usb/caiaq/device.c

214

unsigned char bank,

sound/usb/caiaq/device.c

231

cdev->ep1_out_buf[1] = bank;

sound/usb/caiaq/device.h

134

unsigned char bank,

tools/arch/x86/include/uapi/asm/kvm.h

584

__u8 bank;

tools/testing/cxl/test/mem.c

455

.bank = 2,

tools/testing/selftests/kvm/x86/ucna_injection_test.c

167

mce.bank = UCNA_BANK;