arch/m68k/lib/divsi3.S

63

#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)

arch/m68k/lib/modsi3.S

63

#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)

arch/m68k/lib/mulsi3.S

61

#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)

arch/m68k/lib/udivsi3.S

61

#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)

arch/m68k/lib/umodsi3.S

61

#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)

arch/powerpc/kernel/process.c

1525

#define REG "%016lx"

arch/powerpc/kernel/process.c

1528

#define REG "%08lx"

arch/powerpc/mm/ptdump/ptdump.c

173

#define REG "0x%016lx"

arch/powerpc/mm/ptdump/ptdump.c

175

#define REG "0x%08lx"

arch/powerpc/xmon/xmon.c

199

#define REG "%.16lx"

arch/powerpc/xmon/xmon.c

201

#define REG "%.8lx"

drivers/block/swim.c

41

#define REG(x) unsigned char x, x ## _pad[0x200 - 1];

drivers/block/swim3.c

56

#define REG(x) unsigned char x; char x ## _pad[15];

drivers/gpio/gpio-it87.c

38

#define REG 0x2e

drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c

50

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

46

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

46

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

64

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

46

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

42

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

50

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

40

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

52

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

39

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

38

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

39

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

58

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

70

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

36

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

104

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

53

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

61

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

53

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

88

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

37

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

96

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

127

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

53

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

46

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

17

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

35

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

35

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

34

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

33

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

33

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

35

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

37

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

34

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

34

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

44

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

40

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

39

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

36

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

38

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

37

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

30

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

61

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

32

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

42

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

32

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

42

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

32

#define REG(reg) reg

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

32

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c

30

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

31

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

42

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

29

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c

30

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

43

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

34

#define REG(reg) reg

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c

12

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

40

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

40

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

47

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

39

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

49

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

46

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

37

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

48

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

42

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

43

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

31

#define REG(reg) dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

42

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

43

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

52

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

50

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

27

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

45

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

60

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

51

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

41

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

41

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

57

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

51

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

59

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

54

#undef REG

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

55

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

57

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

54

#undef REG

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

55

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

66

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

59

#undef REG

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

60

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

63

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

54

#undef REG

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

55

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

59

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

52

#undef REG

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

53

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

39

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

27

#undef REG

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

28

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

43

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c

44

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

39

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c

42

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

31

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

41

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

30

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

43

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

31

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

42

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

36

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

29

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

40

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

37

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

40

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

37

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

31

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

37

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

32

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

32

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

32

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

30

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

93

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

43

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

69

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

68

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

49

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

45

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

65

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_hwseq.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

37

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

38

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

62

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

62

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

61

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

68

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

48

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c

30

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

29

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

34

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

31

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

31

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

30

#define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

32

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

30

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

31

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

33

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

35

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

37

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

14

#define REG(reg)\

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

35

#define REG(reg) \

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

417

#define REG(reg) mm ## reg

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

461

#define REG(reg) mm ## reg

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

441

#define REG(reg) mm ## reg

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

452

#define REG(reg) mm ## reg

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

458

#define REG(reg) mm ## reg

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1368

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2290

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

949

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

199

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

198

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

185

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

43

#define REG(reg) (REGS)->offset.reg

drivers/gpu/drm/bridge/tda998x_drv.c

105

#define REG(page, addr) (((page) << 8) | (addr))

drivers/gpu/drm/i915/gt/intel_lrc.c

56

#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))

drivers/gpu/drm/i915/gt/intel_lrc.c

639

#undef REG

drivers/gpu/drm/tidss/tidss_dispc_regs.h

55

#define REG(r) (dispc_common_regmap[r ## _OFF])

drivers/gpu/drm/tilcdc/tilcdc_drv.c

413

#define REG(rev, save, reg) { #reg, rev, save, reg }

drivers/gpu/drm/tilcdc/tilcdc_drv.c

434

#undef REG

drivers/gpu/drm/xe/xe_lrc.c

182

#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))

drivers/gpu/drm/xe/xe_lrc.c

606

#undef REG

drivers/hwmon/smsc47b397.c

41

#define REG 0x2e /* The register to read/write */

drivers/hwmon/smsc47m1.c

43

#define REG 0x2e /* The register to read/write */

drivers/irqchip/irq-realtek-rtl.c

26

#define REG(x) (realtek_ictl_base + x)

drivers/media/tuners/tda18250.c

504

#define REG 0

drivers/mmc/host/vub300.c

221

#define REG(c) (0x01FFFF & (c->arg>>9))

drivers/net/ethernet/apple/mace.h

9

#define REG(x) volatile unsigned char x; char x ## _pad[15]

drivers/net/ipa/reg.h

31

#define REG(__NAME, __reg_id, __offset) \

drivers/pinctrl/bcm/pinctrl-nsp-gpio.c

70

REG,

drivers/pinctrl/pinctrl-ocelot.c

1569

#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))

drivers/regulator/rn5t618-regulator.c

25

#define REG(rid, ereg, emask, vreg, vmask, min, max, step) \

drivers/scsi/ncr53c8xx.h

899

#define REG(r) REGJ (nc_, r)

drivers/scsi/sym53c8xx_2/sym_defs.h

372

#define REG(r) REGJ (nc_, r)

drivers/spi/spi-realtek-rtl.c

30

#define REG(x) (rtspi->base + x)

drivers/watchdog/it8712f_wdt.c

56

#define REG 0x2e /* The register to read/write */

drivers/watchdog/it87_wdt.c

43

#define REG 0x2e

fs/proc/base.c

178

#define REG(NAME, MODE, fops) \

include/soc/mscc/ocelot.h

105

#define REG(reg, offset) [reg & REG_MASK] = offset