sys/arm/allwinner/a10_ahci.c

340

error = clk_set_freq(sc->clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);

sys/arm/allwinner/a10_codec.c

1127

error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN);

sys/arm/allwinner/aw_i2s.c

720

error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN);

sys/arm/allwinner/aw_mmc.c

1439

CLK_SET_ROUND_DOWN);

sys/arm/allwinner/aw_mmc.c

453

CLK_SET_ROUND_DOWN);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

656

if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

717

if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

906

if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/arm/nvidia/tegra124/tegra124_cpufreq.c

340

rv = clk_set_freq(sc->clk_pll_x, point->freq, CLK_SET_ROUND_DOWN);

sys/arm/nvidia/tegra_i2c.c

683

rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN);

sys/arm/nvidia/tegra_sdhci.c

322

rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN);

sys/arm/ti/clk/ti_clk_dpll.c

197

(flags == CLK_SET_ROUND_DOWN)) {

sys/arm64/freescale/imx/clk/imx_clk_composite.c

168

if (flags & CLK_SET_ROUND_DOWN) {

sys/arm64/freescale/imx/imx8mq_ccm.c

228

COMPOSITE(IMX8MQ_CLK_USDHC1, "usdhc1", usdhc_p, 0xac00, CLK_SET_ROUND_DOWN),

sys/arm64/freescale/imx/imx8mq_ccm.c

229

COMPOSITE(IMX8MQ_CLK_USDHC2, "usdhc2", usdhc_p, 0xac80, CLK_SET_ROUND_DOWN),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

770

if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1144

if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

915

if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/arm64/nvidia/tegra210/tegra210_cpufreq.c

282

rv = clk_set_freq(sc->clk_pll_x, point->freq, CLK_SET_ROUND_DOWN);

sys/arm64/rockchip/rk_i2s.c

184

CLK_SET_ROUND_DOWN);

sys/arm64/rockchip/rk_i2s.c

578

error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN);

sys/dev/clk/allwinner/aw_clk_frac.c

253

((flags & CLK_SET_ROUND_DOWN) == 0)) {

sys/dev/clk/allwinner/aw_clk_m.c

196

((flags & CLK_SET_ROUND_DOWN) == 0)) {

sys/dev/clk/allwinner/aw_clk_nkmp.c

269

((flags & CLK_SET_ROUND_DOWN) != 0)) {

sys/dev/clk/allwinner/aw_clk_nm.c

219

((flags & CLK_SET_ROUND_DOWN) == 0)) {

sys/dev/clk/allwinner/aw_clk_nmm.c

161

((flags & CLK_SET_ROUND_DOWN) == 0)) {

sys/dev/clk/allwinner/aw_clk_np.c

153

((flags & CLK_SET_ROUND_DOWN) == 0)) {

sys/dev/clk/clk.c

1428

rv = clk_set_freq(clk, freq, CLK_SET_ROUND_DOWN | CLK_SET_ROUND_UP);

sys/dev/clk/clk.h

48

#define CLK_SET_ROUND(x) ((x) & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN))

sys/dev/clk/clk.h

53

#define CLK_SET_ROUND_ANY (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)

sys/dev/clk/clk_div.c

179

else if ((flags & CLK_SET_ROUND_DOWN) && (*fout > _fout))

sys/dev/clk/clk_div.c

217

((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&

sys/dev/clk/rockchip/rk_clk_composite.c

258

if ((best < *fout) && ((flags & CLK_SET_ROUND_DOWN) == 0))

sys/dev/clk/rockchip/rk_clk_fract.c

219

} else if ((flags & CLK_SET_ROUND_DOWN) && (_fout > *fout)) {

sys/dev/clk/rockchip/rk_clk_fract.c

243

(flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0 &&

sys/dev/cpufreq/cpufreq_dt.c

235

error = clk_set_freq(sc->clk, opp->freq, CLK_SET_ROUND_DOWN);

sys/dev/hdmi/dwc_hdmi_fdt.c

138

err = clk_set_freq(sc->clk_hdmi, freq, CLK_SET_ROUND_DOWN);

sys/dev/mmc/host/dwmmc_rockchip.c

122

CLK_SET_ROUND_DOWN);

sys/dev/mmc/host/dwmmc_starfive.c

46

err = clk_set_freq(sc->ciu, ios->clock, CLK_SET_ROUND_DOWN);

sys/dev/spibus/controller/allwinner/aw_spi.c

539

clk_set_freq(sc->clk_mod, 2 * clock, CLK_SET_ROUND_DOWN);

sys/dev/spibus/controller/rockchip/rk_spi.c

178

clk_set_freq(sc->clk_spi, 2 * freq, CLK_SET_ROUND_DOWN);