atomic_cmpset_int
if (atomic_cmpset_int(&amd64_archlevel, islevel, wantlevel))
if (atomic_cmpset_int(&pmtx->m_ps,
if (atomic_cmpset_int(&once_control->state, state,
if (atomic_cmpset_int(&once_control->state, state,
atomic_cmpset_int(&invl_max_qlen, ii, i);
#define atomic_cmpset_acq_int atomic_cmpset_int
#define atomic_cmpset_rel_int atomic_cmpset_int
#define atomic_cmpset_32 atomic_cmpset_int
while (atomic_cmpset_int(&cpu->in_pcint_handler, 1, 0))
while (atomic_cmpset_int(&cpu->in_pcint_handler, 1, 0))
if (atomic_cmpset_int(&iommu_initted, 0, 1)) {
return (atomic_cmpset_int(&dbg_capable_var, 0, 0) == 0);
atomic_cmpset_int((volatile u_int *)&(ts)->tasklet_state, old, new)
if (atomic_cmpset_int(&acpi_tasks[i].at_flag, ACPI_TASK_USED,
if (atomic_cmpset_int(&acpi_tasks[i].at_flag, ACPI_TASK_FREE,
atomic_cmpset_int(&acpi_tasks_hiwater, acpi_tasks_hiwater, i);
} while (!atomic_cmpset_int(&sc->ec_sci_pend, pending, 0));
while (!atomic_cmpset_int(&sc->sync_packet, 0xffff, command_byte))
#define test_and_clear_bit(bit, p) atomic_cmpset_int((p), ((*(p)) | (1<<bit)), ((*(p)) & ~(1<<bit)))
while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
(void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
(void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
(void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
(void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
if (atomic_cmpset_int(&q->state, IQS_IDLE,
(void) atomic_cmpset_int(&q->state,
(void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
atomic_cmpset_int(&eq->equiq, 0, 1)) {
atomic_cmpset_int(&eq->equiq, 0, 1)) {
atomic_cmpset_int(&eq->equiq, 0, 1)) {
(atomic_cmpset_int((volatile u_int *)(ptr),(old),(new)) ? (old) : (0))
if (atomic_cmpset_int(flag_cnt_ptr, old_flag_cnt, flag_cnt)) {
if (atomic_cmpset_int(&chan->ch_stflags, old_stflags,
while (atomic_cmpset_int(&sc->bypass.low, 0, 1) == 0)
while (atomic_cmpset_int(&sc->bypass.high, 0, 1) == 0)
while (atomic_cmpset_int(&sc->bypass.log, 0, 1) == 0)
while (atomic_cmpset_int(&sc->bypass.high, 1, 0) == 0)
while (atomic_cmpset_int(&sc->bypass.low, 1, 0) == 0)
while (atomic_cmpset_int(&sc->bypass.log, 1, 0) == 0)
while (atomic_cmpset_int(&sc->bypass.log, 1, 0) == 0)
while (atomic_cmpset_int(&sc->bypass.high, 0, 1) == 0)
while (atomic_cmpset_int(&sc->bypass.high, 1, 0) == 0)
if (!atomic_cmpset_int(&sc->fdir_reinit, 0, 1))
(void) atomic_cmpset_int(&txs->enqueue_is_running, 1, 0);
if (atomic_cmpset_int(&txs->enqueue_is_running, 0, 1) == 1) {
(void)atomic_cmpset_int(&arc4rand_iniseed_state, ARC4_ENTR_NONE, ARC4_ENTR_HAVE);
if (atomic_cmpset_int(&vm->suspend, 0, how) == 0)
!atomic_cmpset_int(&vd->vd_timer_armed, 0, 1))
!atomic_cmpset_int(&vd->vd_timer_armed, 1, 0))
if (atomic_cmpset_int(&sc->sc_enxio_active, 0, 1))
atomic_cmpset_int(&sc->sc_enxio_reported, 0, 1)) {
if (!atomic_cmpset_int((u_int *)pte, obits,
if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
if (!atomic_cmpset_int((u_int *)pte, oldpte,
if (!atomic_cmpset_int((u_int *)pte, oldpte,
} while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
} while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
return (atomic_cmpset_int((volatile u_int *)dst, (u_int)expect,
#define atomic_cmpset_acq_int atomic_cmpset_int
#define atomic_cmpset_rel_int atomic_cmpset_int
#define atomic_cmpset_32 atomic_cmpset_int
atomic_cmpset_int((volatile u_int *)(dst), (u_int)(old), (u_int)(new))
#define pde_cmpset(pdep, old, new) atomic_cmpset_int(pdep, old, new)
} while (!atomic_cmpset_int(&btp->curr, idx, nxt));
} while (atomic_cmpset_int(&fp->f_flag, flg, tmp) == 0);
} while (atomic_cmpset_int(&fp->f_flag, flg, tmp) == 0);
atomic_cmpset_int(&ih->ih_need, 1, 0) == 0)
if (atomic_cmpset_int(&bc->__count, _BLOCKCOUNT_WAITERS_FLAG, 0))
if (atomic_cmpset_int(counter, c, c - 1)) {
while (atomic_cmpset_int(&stopping_cpu, NOCPU,
atomic_cmpset_int(&s->s_rd_seq, s_rd_seq, rd_seq);
} while (atomic_cmpset_int(&fp->f_flag, oflag, flag) == 0);
if (__predict_false(!atomic_cmpset_int(&vp->v_holdcnt, 0, VHOLD_NO_SMR))) {
atomic_cmpset_int(&arc4rand_iniseed_state, ARC4_ENTR_HAVE, ARC4_ENTR_SEED))))
return atomic_cmpset_int(&ni->ni_refcnt, 0, 1);
if (atomic_cmpset_int(&priv->fn_sent, 0, 1) &&
if (!(atomic_cmpset_int(&SCTP_BASE_VAR(packet_log_end), value, thisend))) {
if (!(atomic_cmpset_int(&SCTP_BASE_VAR(packet_log_end), value, thisend))) {
} while (atomic_cmpset_int(&inp->sctp_flags, old_flags, new_flags) == 0);
if (!atomic_cmpset_int(&inp->store_at, store_at, new_store)) {
} while (atomic_cmpset_int(&inp->readlog_index, index, newindex) == 0);
} while (atomic_cmpset_int(&SCTP_BASE_SYSCTL(sctp_log).index, saveindex, newindex) == 0);
if (atomic_cmpset_int(&tq->adddel_scheduled, 0, 1) == 0)
if (atomic_cmpset_int(&tq->adddel_scheduled, 0, 1) == 0)
while (atomic_cmpset_int(cntr, 0, 0) == 0)
atomic_cmpset_int(&r->rule_flag, rule_flag,
while (!atomic_cmpset_int(&tlbie_lock, 0, 1));
} while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
#define atomic_cmpset_32 atomic_cmpset_int
#define atomic_cmpset_ptr atomic_cmpset_int
} while (!atomic_cmpset_int(p, value, value + v));
atomic_cmpset_int(&xprt->xp_doneddp, 0, 1)) {
if (atomic_cmpset_int(&swblk_zone_exhausted,
if (atomic_cmpset_int(&swblk_zone_exhausted,
if (atomic_cmpset_int(&swpctrie_zone_exhausted,
if (atomic_cmpset_int(&swpctrie_zone_exhausted,
if (atomic_cmpset_int(&max_kstack_used, prev_used, used))
} while (!atomic_cmpset_int(&(m)->busy_lock, _busy_lock, \
atomic_cmpset_int(&a->error, 0, error);
atomic_cmpset_int(&a->error, 0, error);
atomic_cmpset_int(&a->error, 0, error);
atomic_cmpset_int(&a->error, 0, error);
atomic_cmpset_int(&a->error, 0, error);
atomic_cmpset_int(&a->error, 0, error);