ATA_INL
uint32_t val = ATA_INL(m, off);
uint32_t val = ATA_INL(m, off);
uint32_t val = ATA_INL(m, off);
val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R);
val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R);
reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);
v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
v = ATA_INL(ctlr->r_mem, AHCI_CAP);
v = ATA_INL(ctlr->r_mem, AHCI_PI);
v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
status = ATA_INL(ch->r_mem, AHCI_P_CMD);
istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
work = ATA_INL(ch->r_mem, AHCI_P_CMD);
cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
(ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
(ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
ATA_INL(ch->r_mem, AHCI_P_IS),
ATA_INL(ch->r_mem, AHCI_P_CI),
ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
ATA_INL(ch->r_mem, AHCI_P_TFD),
ATA_INL(ch->r_mem, AHCI_P_SERR),
ATA_INL(ch->r_mem, AHCI_P_CMD));
sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
ATA_INL(ch->r_mem, AHCI_P_CMD));
uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
version = ATA_INL(ctlr->r_mem, AHCI_VS);
ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
val = ATA_INL(ch->r_mem, AHCI_P_CMD);
val = ATA_INL(ch->r_mem, AHCI_P_CMD);
ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
(ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
is = ATA_INL(ctlr->r_mem, AHCI_IS);
is = ATA_INL(ctlr->r_mem, AHCI_IS);
ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
version = ATA_INL(ctlr->r_mem, AHCI_VS);
ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC);
val = ATA_INL(ctrl->r_ecc, AHCI_FSL_REG_ECC);
vscap = ATA_INL(ctlr->r_mem, AHCI_VSCAP);
uint32_t cap = ATA_INL(ctlr->r_mem, 0x800); /* Intel's REMAP CAP */
(ATA_INL(ctlr->r_mem, 0x880 + i * 0x80) ==
caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
pi = ATA_INL(ctlr->r_mem, AHCI_PI);
ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
while ((ATA_INL(enc->r_memc, 0) & AHCI_EM_RST) &&
while (ATA_INL(enc->r_memc, 0) & (AHCI_EM_TM | AHCI_EM_RST) &&
enc->capsem = ATA_INL(enc->r_memc, 0);
ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
ATA_INL(ctlr->r_res2, 0x0C) | 0xf);
*result = ATA_INL(ctlr->r_res2, offset + reg);
ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
istatus = ATA_INL(ctlr->r_res2, offset);
u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
(ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
(ATA_INL(ctlr->r_res2,
vector = ATA_INL(ctlr->r_res2, 0x040);
status = ATA_INL(ctlr->r_res2, stat_reg);
(ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
(ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
(ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
(ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
(ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
(ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
(ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
val = ATA_INL(ctlr->r_res2, 0x14c + offset);
val = ATA_INL(ch->r_mem, EDMA_RESQIP);
val = ATA_INL(ch->r_mem, EDMA_RESQIP);
ATA_INL(ch->r_mem, EDMA_IEC),
ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE),
ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C),
ATA_INL(ch->r_mem, DMA_S), ch->rslots,
val = ATA_INL(ch->r_mem, SATA_PHYM3);
val = ATA_INL(ch->r_mem, SATA_PHYM4);
val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2);
val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1);
status = ATA_INL(ch->r_mem, SATA_SS);
status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK;
reg = ATA_INL(ch->r_mem, SATA_FISC);
reg = ATA_INL(ch->r_mem, SATA_FISIM);
while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) {
fcfg = ATA_INL(ch->r_mem, SATA_FISC);
ltm = ATA_INL(ch->r_mem, SATA_LTM);
hc = ATA_INL(ch->r_mem, EDMA_HC);
unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD);
u_int32_t status = ATA_INL(ch->r_mem, SATA_SS);
fis = ATA_INL(ch->r_mem, SATA_FISDW0);
work = ATA_INL(ch->r_mem, SATA_SC);
work = ATA_INL(ch->r_mem, SATA_SS);
work = ATA_INL(ch->r_mem, SATA_SC);
while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 &&
iec = ATA_INL(ch->r_mem, EDMA_IEC);
serr = ATA_INL(ch->r_mem, SATA_SE);
fisic = ATA_INL(ch->r_mem, SATA_FISIC);
ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S));
ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S));
uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16;
else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR)
ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0)
ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC);
__func__, ATA_INL(ch->r_mem, SIIS_P_IS),
ATA_INL(ch->r_mem, SIIS_P_SS), ch->rslots,
ATA_INL(ch->r_mem, SIIS_P_CMDERR), ATA_INL(ch->r_mem, SIIS_P_STS),
ATA_INL(ch->r_mem, SIIS_P_SERR));
ATA_INL(ch->r_mem, SIIS_P_LRAM_SLOT(slot->slot) + 4);
ATA_INL(ch->r_mem, SIIS_P_LRAM_SLOT(slot->slot) + 4);
while (((val = ATA_INL(ch->r_mem, SIIS_P_STS)) &
ctlr->gctl = ATA_INL(ctlr->r_gmem, SIIS_GCTL);
while (((val = ATA_INL(ch->r_mem, SIIS_P_STS)) &
status = ATA_INL(ch->r_mem, SIIS_P_SSTS);
status = ATA_INL(ch->r_mem, SIIS_P_SSTS) & ATA_SS_SPD_MASK;
is = ATA_INL(ctlr->r_gmem, SIIS_IS);
status = ATA_INL(ch->r_mem, SIIS_P_SNTF);
u_int32_t status = ATA_INL(ch->r_mem, SIIS_P_SSTS);
sstatus = ATA_INL(ch->r_mem, SIIS_P_SS);
istatus = ATA_INL(ch->r_mem, SIIS_P_IS) &
estatus = ATA_INL(ch->r_mem, SIIS_P_CMDERR);
ctx = ATA_INL(ch->r_mem, SIIS_P_CTX);
tmp = ATA_INL(ch->r_mem, FSL_SATA_P_SIG);
if ((ATA_INL(ch->r_mem, FSL_SATA_P_CCR) & (1 << slot->slot)) != 0)
ATA_INL(ch->r_mem, FSL_SATA_P_HSTS),
ATA_INL(ch->r_mem, FSL_SATA_P_CQR),
ATA_INL(ch->r_mem, FSL_SATA_P_CCR),
ATA_INL(ch->r_mem, FSL_SATA_P_SSTS), ch->rslots,
ATA_INL(ch->r_mem, FSL_SATA_P_CER),
ATA_INL(ch->r_mem, FSL_SATA_P_DER),
ATA_INL(ch->r_mem, FSL_SATA_P_SERR),
ATA_INL(ch->r_mem, FSL_SATA_P_CAR),
ATA_INL(ch->r_mem, FSL_SATA_P_SIG));
sstatus = ATA_INL(ch->r_mem, FSL_SATA_P_CAR);
sig = ATA_INL(ch->r_mem, FSL_SATA_P_SIG);
cmd = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL);
ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & FSL_SATA_P_HSTS_PR);
cmd = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL);
ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f);
ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) | FSL_SATA_P_HCTRL_PHYRDY);
ctrl = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f;
status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS) & ATA_SS_SPD_MASK;
istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS);
while (((rval = ATA_INL(ch->r_mem, off)) & mask) != val) {
r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL);
r = ATA_INL(ch->r_mem, FSL_SATA_P_PCC);
r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL);
r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL);
u_int32_t status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS);
istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & 0x7ffff;
work = ATA_INL(ch->r_mem, FSL_SATA_P_PCC) & ~FSL_SATA_PCC_LPB_EN;
ok = ATA_INL(ch->r_mem, FSL_SATA_P_CCR);
sntf = ATA_INL(ch->r_mem, FSL_SATA_P_SNTF);
serr = ATA_INL(ch->r_mem, FSL_SATA_P_SERR);
cer = ATA_INL(ch->r_mem, FSL_SATA_P_CER);
der = ATA_INL(ch->r_mem, FSL_SATA_P_DER);