crypto/libressl/crypto/modes/ccm128.c

179

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

201

union { u64 u[2]; u8 c[16]; } temp;

crypto/libressl/crypto/modes/ccm128.c

207

ctx->cmac.u[0] ^= ((u64*)inp)[0];

crypto/libressl/crypto/modes/ccm128.c

208

ctx->cmac.u[1] ^= ((u64*)inp)[1];

crypto/libressl/crypto/modes/ccm128.c

218

((u64*)out)[0] = scratch.u[0]^((u64*)inp)[0];

crypto/libressl/crypto/modes/ccm128.c

219

((u64*)out)[1] = scratch.u[1]^((u64*)inp)[1];

crypto/libressl/crypto/modes/ccm128.c

254

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

272

union { u64 u[2]; u8 c[16]; } temp;

crypto/libressl/crypto/modes/ccm128.c

282

ctx->cmac.u[0] ^= (((u64*)out)[0] = scratch.u[0]^((u64*)inp)[0]);

crypto/libressl/crypto/modes/ccm128.c

283

ctx->cmac.u[1] ^= (((u64*)out)[1] = scratch.u[1]^((u64*)inp)[1]);

crypto/libressl/crypto/modes/ccm128.c

333

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

390

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/gcm128.c

1075

u64 mlen = ctx->len.u[1];

crypto/libressl/crypto/modes/gcm128.c

1079

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

1081

void (*gcm_ghash_p)(u64 Xi[2],const u128 Htable[16],

crypto/libressl/crypto/modes/gcm128.c

121

static void gcm_init_8bit(u128 Htable[256], u64 H[2])

crypto/libressl/crypto/modes/gcm128.c

1264

u64 mlen = ctx->len.u[1];

crypto/libressl/crypto/modes/gcm128.c

1267

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

1269

void (*gcm_ghash_p)(u64 Xi[2],const u128 Htable[16],

crypto/libressl/crypto/modes/gcm128.c

1382

u64 mlen = ctx->len.u[1];

crypto/libressl/crypto/modes/gcm128.c

1385

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

1387

void (*gcm_ghash_p)(u64 Xi[2],const u128 Htable[16],

crypto/libressl/crypto/modes/gcm128.c

145

static void gcm_gmult_8bit(u64 Xi[2], const u128 Htable[256])

crypto/libressl/crypto/modes/gcm128.c

1504

u64 alen = ctx->len.u[0]<<3;

crypto/libressl/crypto/modes/gcm128.c

1505

u64 clen = ctx->len.u[1]<<3;

crypto/libressl/crypto/modes/gcm128.c

1507

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

1524

alen = (u64)GETU32(p) <<32|GETU32(p+4);

crypto/libressl/crypto/modes/gcm128.c

1525

clen = (u64)GETU32(p+8)<<32|GETU32(p+12);

crypto/libressl/crypto/modes/gcm128.c

230

Z.hi ^= (u64)rem_8bit[rem]<<32;

crypto/libressl/crypto/modes/gcm128.c

255

static void gcm_init_4bit(u128 Htable[16], u64 H[2])

crypto/libressl/crypto/modes/gcm128.c

333

static void gcm_gmult_4bit(u64 Xi[2], const u128 Htable[16])

crypto/libressl/crypto/modes/gcm128.c

353

Z.hi ^= (u64)rem_4bit[rem]<<32;

crypto/libressl/crypto/modes/gcm128.c

370

Z.hi ^= (u64)rem_4bit[rem]<<32;

crypto/libressl/crypto/modes/gcm128.c

402

static void gcm_ghash_4bit(u64 Xi[2],const u128 Htable[16],

crypto/libressl/crypto/modes/gcm128.c

427

Z.hi ^= (u64)rem_4bit[rem]<<32;

crypto/libressl/crypto/modes/gcm128.c

445

Z.hi ^= (u64)rem_4bit[rem]<<32;

crypto/libressl/crypto/modes/gcm128.c

523

Z.hi ^= (u64)rem_8bit[rem^Hshl4[nhi]]<<48;

crypto/libressl/crypto/modes/gcm128.c

541

Z.hi ^= ((u64)rem_8bit[rem<<4])<<48;

crypto/libressl/crypto/modes/gcm128.c

564

void gcm_gmult_4bit(u64 Xi[2],const u128 Htable[16]);

crypto/libressl/crypto/modes/gcm128.c

565

void gcm_ghash_4bit(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

579

static void gcm_gmult_1bit(u64 Xi[2],const u64 H[2])

crypto/libressl/crypto/modes/gcm128.c

596

X = (long)((u64)GETU32(p)<<32|GETU32(p+4));

crypto/libressl/crypto/modes/gcm128.c

607

u64 M = (u64)(X>>(8*sizeof(long)-1));

crypto/libressl/crypto/modes/gcm128.c

650

void gcm_init_clmul(u128 Htable[16],const u64 Xi[2]);

crypto/libressl/crypto/modes/gcm128.c

651

void gcm_gmult_clmul(u64 Xi[2],const u128 Htable[16]);

crypto/libressl/crypto/modes/gcm128.c

652

void gcm_ghash_clmul(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

656

void gcm_gmult_4bit_mmx(u64 Xi[2],const u128 Htable[16]);

crypto/libressl/crypto/modes/gcm128.c

657

void gcm_ghash_4bit_mmx(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

659

void gcm_gmult_4bit_x86(u64 Xi[2],const u128 Htable[16]);

crypto/libressl/crypto/modes/gcm128.c

660

void gcm_ghash_4bit_x86(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

667

void gcm_gmult_neon(u64 Xi[2],const u128 Htable[16]);

crypto/libressl/crypto/modes/gcm128.c

668

void gcm_ghash_neon(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

697

u64 hi,lo;

crypto/libressl/crypto/modes/gcm128.c

698

hi = (u64)GETU32(p) <<32|GETU32(p+4);

crypto/libressl/crypto/modes/gcm128.c

699

lo = (u64)GETU32(p+8)<<32|GETU32(p+12);

crypto/libressl/crypto/modes/gcm128.c

75

u64 T = U64(0xe100000000000000) & (0-(V.lo&1)); \

crypto/libressl/crypto/modes/gcm128.c

755

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

774

u64 len0 = len;

crypto/libressl/crypto/modes/gcm128.c

81

V.hi = (V.hi>>1 )^((u64)T<<32); \

crypto/libressl/crypto/modes/gcm128.c

834

u64 alen = ctx->len.u[0];

crypto/libressl/crypto/modes/gcm128.c

836

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

838

void (*gcm_ghash_p)(u64 Xi[2],const u128 Htable[16],

crypto/libressl/crypto/modes/gcm128.c

893

u64 mlen = ctx->len.u[1];

crypto/libressl/crypto/modes/gcm128.c

897

void (*gcm_gmult_p)(u64 Xi[2],const u128 Htable[16]) = ctx->gmult;

crypto/libressl/crypto/modes/gcm128.c

899

void (*gcm_ghash_p)(u64 Xi[2],const u128 Htable[16],

crypto/libressl/crypto/modes/modes_lcl.h

107

union { u64 u[2]; u8 c[16]; } nonce, cmac;

crypto/libressl/crypto/modes/modes_lcl.h

108

u64 blocks;

crypto/libressl/crypto/modes/modes_lcl.h

33

# define BSWAP8(x) ({ u64 ret=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

40

# define BSWAP8(x) ({ u32 lo=(u64)(x)>>32,hi=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

43

(u64)hi<<32|lo; })

crypto/libressl/crypto/modes/modes_lcl.h

49

# define BSWAP8(x) ({ u32 lo=(u64)(x)>>32,hi=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

52

(u64)hi<<32|lo; })

crypto/libressl/crypto/modes/modes_lcl.h

72

typedef struct { u64 hi,lo; } u128;

crypto/libressl/crypto/modes/modes_lcl.h

85

union { u64 u[2]; u32 d[4]; u8 c[16]; size_t t[16/sizeof(size_t)]; }

crypto/libressl/crypto/modes/modes_lcl.h

93

void (*gmult)(u64 Xi[2],const u128 Htable[16]);

crypto/libressl/crypto/modes/modes_lcl.h

94

void (*ghash)(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/xts128.c

135

union { u64 u[2]; u8 c[16]; } tweak1;

crypto/libressl/crypto/modes/xts128.c

160

scratch.u[0] = ((u64*)inp)[0]^tweak1.u[0];

crypto/libressl/crypto/modes/xts128.c

161

scratch.u[1] = ((u64*)inp)[1]^tweak1.u[1];

crypto/libressl/crypto/modes/xts128.c

180

((u64*)out)[0] = scratch.u[0]^tweak.u[0];

crypto/libressl/crypto/modes/xts128.c

181

((u64*)out)[1] = scratch.u[1]^tweak.u[1];

crypto/libressl/crypto/modes/xts128.c

67

union { u64 u[2]; u32 d[4]; u8 c[16]; } tweak, scratch;

crypto/libressl/crypto/modes/xts128.c

84

scratch.u[0] = ((u64*)inp)[0]^tweak.u[0];

crypto/libressl/crypto/modes/xts128.c

85

scratch.u[1] = ((u64*)inp)[1]^tweak.u[1];

crypto/libressl/crypto/modes/xts128.c

93

((u64*)out)[0] = scratch.u[0]^=tweak.u[0];

crypto/libressl/crypto/modes/xts128.c

94

((u64*)out)[1] = scratch.u[1]^=tweak.u[1];

crypto/libressl/crypto/whrlpool/wp_block.c

155

# define C0(K,i) (((u64*)(Cx.c+0))[2*K.c[(i)*8+0]])

crypto/libressl/crypto/whrlpool/wp_block.c

156

# define C1(K,i) (((u64*)(Cx.c+7))[2*K.c[(i)*8+1]])

crypto/libressl/crypto/whrlpool/wp_block.c

157

# define C2(K,i) (((u64*)(Cx.c+6))[2*K.c[(i)*8+2]])

crypto/libressl/crypto/whrlpool/wp_block.c

158

# define C3(K,i) (((u64*)(Cx.c+5))[2*K.c[(i)*8+3]])

crypto/libressl/crypto/whrlpool/wp_block.c

159

# define C4(K,i) (((u64*)(Cx.c+4))[2*K.c[(i)*8+4]])

crypto/libressl/crypto/whrlpool/wp_block.c

160

# define C5(K,i) (((u64*)(Cx.c+3))[2*K.c[(i)*8+5]])

crypto/libressl/crypto/whrlpool/wp_block.c

161

# define C6(K,i) (((u64*)(Cx.c+2))[2*K.c[(i)*8+6]])

crypto/libressl/crypto/whrlpool/wp_block.c

162

# define C7(K,i) (((u64*)(Cx.c+1))[2*K.c[(i)*8+7]])

crypto/libressl/crypto/whrlpool/wp_block.c

167

u8 c[(256*N+ROUNDS)*sizeof(u64)];

crypto/libressl/crypto/whrlpool/wp_block.c

168

u64 q[(256*N+ROUNDS)];

crypto/libressl/crypto/whrlpool/wp_block.c

445

union { u64 q[8]; u8 c[64]; } S,K,*H=(void *)ctx->H.q;

crypto/libressl/crypto/whrlpool/wp_block.c

452

u64 L[8];

crypto/libressl/crypto/whrlpool/wp_block.c

478

u64 L0,L1,L2,L3,L4,L5,L6,L7;

crypto/libressl/crypto/whrlpool/wp_block.c

496

const u64 *pa = (const u64*)p;

crypto/libressl/crypto/whrlpool/wp_block.c

616

const u64 *pa=(const u64 *)p;

crypto/libressl/crypto/whrlpool/wp_block.c

79

# define ROTATE(a,n) ({ u64 ret; asm ("rolq %1,%0" \

lib/libefivar/uefi-dplib.h

535

#define SwapBytes64(u64) bswap64(u64)

sys/dev/agp/intel-gtt.c

1634

void intel_gtt_get(u64 *gtt_total,

sys/dev/drm/amd/amdgpu/amdgpu.h

1078

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);

sys/dev/drm/amd/amdgpu/amdgpu.h

1079

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);

sys/dev/drm/amd/amdgpu/amdgpu.h

1196

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,

sys/dev/drm/amd/amdgpu/amdgpu.h

1197

u64 num_vis_bytes);

sys/dev/drm/amd/amdgpu/amdgpu.h

680

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu.h

701

u64 start_offset;

sys/dev/drm/amd/amdgpu/amdgpu.h

702

u64 size;

sys/dev/drm/amd/amdgpu/amdgpu.h

956

u64 fence_context;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.h

80

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1788

u64 start_addr;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1789

u64 size;

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

257

static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

268

static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

290

u64 *max_bytes,

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

291

u64 *max_vis_bytes)

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

294

u64 free_vram, total_vram, used_vram;

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

357

u64 total_vis_vram = adev->gmc.visible_vram_size;

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

358

u64 used_vis_vram =

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

362

u64 free_vis_vram = total_vis_vram - used_vis_vram;

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

384

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

385

u64 num_vis_bytes)

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

688

amdgpu_cs_get_threshold_for_moves(p->adev, (u64 *)&p->bytes_moved_threshold,

sys/dev/drm/amd/amdgpu/amdgpu_cs.c

689

(u64 *)&p->bytes_moved_vis_threshold);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

321

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

341

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

578

(u64 *)&adev->wb.gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_device.c

601

&adev->wb.wb_obj, (u64 *)&adev->wb.gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_device.c

669

u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);

sys/dev/drm/amd/amdgpu/amdgpu_display.c

159

u64 tiling_flags;

sys/dev/drm/amd/amdgpu/amdgpu_gart.c

224

u64 page_base;

sys/dev/drm/amd/amdgpu/amdgpu_gem.c

47

u64 flags, enum ttm_bo_type type,

sys/dev/drm/amd/amdgpu/amdgpu_gem.c

761

args->size = (u64)args->pitch * args->height;

sys/dev/drm/amd/amdgpu/amdgpu_gem.h

63

u64 flags, enum ttm_bo_type type,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

325

(u64 *)&ring->mqd_gpu_addr, &ring->mqd_ptr);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

343

(u64 *)&ring->mqd_gpu_addr, &ring->mqd_ptr);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

368

(u64 *)&ring->mqd_gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

375

(u64 *)&ring->mqd_gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

109

u64 eop_gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

96

u64 hpd_eop_gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

98

u64 mec_fw_gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

116

u64 base)

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

148

u64 size_af, size_bf;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

150

u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

192

u64 size_af, size_bf;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

109

u64 mc_vram_size;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

110

u64 visible_vram_size;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

111

u64 agp_size;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

112

u64 agp_start;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

113

u64 agp_end;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

114

u64 gart_size;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

115

u64 gart_start;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

116

u64 gart_end;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

117

u64 vram_start;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

118

u64 vram_end;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

125

u64 fb_start;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

126

u64 fb_end;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

128

u64 real_vram_size;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

130

u64 mc_mask;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

139

u64 shared_aperture_start;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

140

u64 shared_aperture_end;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

141

u64 private_aperture_start;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

142

u64 private_aperture_end;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

194

u64 base);

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

92

u64 device_id;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

93

u64 hive_id;

sys/dev/drm/amd/amdgpu/amdgpu_gmc.h

95

u64 node_segment_size;

sys/dev/drm/amd/amdgpu/amdgpu_gtt_mgr.c

290

man->size, (u64)atomic64_read(&mgr->available),

sys/dev/drm/amd/amdgpu/amdgpu_ids.c

230

u64 fence_context = adev->vm_manager.fence_context + ring->idx;

sys/dev/drm/amd/amdgpu/amdgpu_ih.c

115

amdgpu_bo_free_kernel(&ih->ring_obj, (u64*)&ih->gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_ih.c

82

&ih->ring_obj, (u64*)&ih->gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

282

int crtc_id, u64 crtc_base, bool async);

sys/dev/drm/amd/amdgpu/amdgpu_object.c

1105

int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

1125

void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

1343

u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

136

u64 flags = abo->flags;

sys/dev/drm/amd/amdgpu/amdgpu_object.c

240

u64 *gpu_addr, void **cpu_addr)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

334

u64 *gpu_addr, void **cpu_addr)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

359

void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_object.c

590

u64 flags = bp->flags;

sys/dev/drm/amd/amdgpu/amdgpu_object.c

852

u64 min_offset, u64 max_offset)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

886

u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

191

static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)

sys/dev/drm/amd/amdgpu/amdgpu_object.h

234

u64 *gpu_addr, void **cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

238

u64 *gpu_addr, void **cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

239

void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_object.h

248

u64 min_offset, u64 max_offset);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

256

int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

257

void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

269

u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

42

u64 flags;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

85

u64 flags;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

87

u64 tiling_flags;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

88

u64 metadata_flags;

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

175

&psp->tmr_bo, (u64 *)&psp->tmr_mc_addr, &psp->tmr_buf);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

232

(u64 *)&psp->asd_shared_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

353

(u64 *)&psp->fw_pri_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

361

(u64 *)&psp->fence_buf_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

368

&psp->cmd_buf_bo, (u64 *)&psp->cmd_buf_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

400

(u64 *)&psp->cmd_buf_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

404

(u64 *)&psp->fence_buf_mc_addr, &psp->fence_buf);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

407

(u64 *)&psp->fw_pri_mc_addr, &psp->fw_pri_buf);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

457

amdgpu_bo_free_kernel(&psp->tmr_bo, (u64 *)&psp->tmr_mc_addr, &psp->tmr_buf);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

459

(u64 *)&psp->fw_pri_mc_addr, &psp->fw_pri_buf);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

461

(u64 *)&psp->fence_buf_mc_addr, &psp->fence_buf);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

462

amdgpu_bo_free_kernel(&psp->asd_shared_bo, (u64 *)&psp->asd_shared_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

464

amdgpu_bo_free_kernel(&psp->cmd_buf_bo, (u64 *)&psp->cmd_buf_mc_addr,

sys/dev/drm/amd/amdgpu/amdgpu_ring.c

308

(u64 *)&ring->gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_ring.c

354

(u64 *)&ring->gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

184

u64 wptr;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

185

u64 wptr_old;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

209

u64 cond_exe_gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_sa.c

67

(u64 *)&sa_manager->gpu_addr, &sa_manager->cpu_ptr);

sys/dev/drm/amd/amdgpu/amdgpu_sa.c

98

amdgpu_bo_free_kernel(&sa_manager->bo, (u64 *)&sa_manager->gpu_addr, &sa_manager->cpu_ptr);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1098

gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1150

gtt->offset = (u64)tmp.start << PAGE_SHIFT;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1691

u64 vram_size = adev->gmc.visible_vram_size;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1692

u64 offset = adev->fw_vram_usage.start_offset;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1693

u64 size = adev->fw_vram_usage.size;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1775

u64 vis_vram_limit;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1811

vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2033

*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

737

atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

813

u64 offset;

sys/dev/drm/amd/amdgpu/amdgpu_ttm.h

76

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);

sys/dev/drm/amd/amdgpu/amdgpu_ucode.c

429

(u64*)&adev->firmware.fw_buf_mc,

sys/dev/drm/amd/amdgpu/amdgpu_ucode.c

445

(u64*)&adev->firmware.fw_buf_mc,

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

260

(u64 *)&adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

308

(u64 *)&adev->uvd.inst[j].gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

455

static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

183

(u64 *)&adev->vce.gpu_addr, &adev->vce.cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

216

amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, (u64 *)&adev->vce.gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

129

(u64 *)&adev->vcn.gpu_addr, &adev->vcn.cpu_addr);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

145

(u64 *)&adev->vcn.gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

341

(u64 *)&adev->virt.mm_table.gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

366

(u64 *)&adev->virt.mm_table.gpu_addr,

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

51

(u64 *)&adev->virt.csa_vmid0_addr, &ptr);

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

61

(u64 *)&adev->virt.csa_vmid0_addr,

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

76

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

77

(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

sys/dev/drm/amd/amdgpu/amdgpu_vm.c

1589

amdgpu_gmc_get_vm_pde(params->adev, level, (u64)&addr, (u64)&flags);

sys/dev/drm/amd/amdgpu/amdgpu_vm.c

3288

u64 fault;

sys/dev/drm/amd/amdgpu/amdgpu_vm.c

3548

int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)

sys/dev/drm/amd/amdgpu/amdgpu_vm.c

3586

void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

170

#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

171

#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

172

#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

230

DECLARE_KFIFO(faults, u64, 128);

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

259

u64 fence_context;

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

268

u64 vram_base_offset;

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

367

int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);

sys/dev/drm/amd/amdgpu/amdgpu_vm.h

369

void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);

sys/dev/drm/amd/amdgpu/amdgpu_vram_mgr.c

107

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo)

sys/dev/drm/amd/amdgpu/amdgpu_vram_mgr.c

113

u64 usage;

sys/dev/drm/amd/amdgpu/amdgpu_vram_mgr.c

86

static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/ci_dpm.c

1103

u64 tmp64;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1118

tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1220

u64 tmp64;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1234

tmp64 = (u64)duty * 100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1249

u64 tmp64;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1268

tmp64 = (u64)speed * duty100;

sys/dev/drm/amd/amdgpu/cik_ih.c

108

u64 wptr_off;

sys/dev/drm/amd/amdgpu/cik_sdma.c

618

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/cik_sdma.c

677

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/cz_ih.c

108

u64 wptr_off;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1025

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1027

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1870

amdgpu_bo_get_tiling_flags(abo, (u64 *)&tiling_flags);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

233

int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

908

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1051

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1053

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1912

amdgpu_bo_get_tiling_flags(abo, (u64 *)&tiling_flags);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

251

int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

934

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1799

amdgpu_bo_get_tiling_flags(abo, (u64 *)&tiling_flags);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

181

int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

843

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

960

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

962

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/amd/amdgpu/dce_virtual.c

58

int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2569

u64 rb_addr, rptr_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2845

u64 eop_gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2901

u64 hqd_gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2902

u64 wb_gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3045

u64 mqd_gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3314

(u64 *)&adev->gfx.rlc.save_restore_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3337

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3357

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4611

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4615

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1390

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1411

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1625

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1676

gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1702

gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1728

gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2186

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2191

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4337

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1134

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1139

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1160

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1182

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1499

(u64 *)&ngg_buf->gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1516

(u64 *)&adev->gfx.ngg.buf[i].gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1849

(u64 *)&adev->gfx.rlc.clear_state_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1853

(u64 *)&adev->gfx.rlc.cp_table_gpu_addr,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2672

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4020

u64 wptr;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4027

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

103

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

33

u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

35

return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.h

32

u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1033

adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1074

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

242

u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

382

adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

410

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1159

adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1200

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

430

u64 base = 0;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

584

adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

612

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

253

u64 addr;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

255

addr = (u64)entry->src_data[0] << 12;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

256

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

772

u64 base = 0;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

854

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

996

adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);

sys/dev/drm/amd/amdgpu/iceland_ih.c

108

u64 wptr_off;

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

121

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

38

u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

40

u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

41

u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.h

26

u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

195

(u64 *)&ring->ring_mem_mc_addr,

sys/dev/drm/amd/amdgpu/psp_v10_0.c

273

(u64 *)&ring->ring_mem_mc_addr,

sys/dev/drm/amd/amdgpu/psp_v11_0.c

263

(u64 *)&ring->ring_mem_mc_addr,

sys/dev/drm/amd/amdgpu/psp_v11_0.c

336

(u64 *)&ring->ring_mem_mc_addr,

sys/dev/drm/amd/amdgpu/psp_v3_1.c

313

(u64 *)&ring->ring_mem_mc_addr,

sys/dev/drm/amd/amdgpu/psp_v3_1.c

391

(u64 *)&ring->ring_mem_mc_addr,

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

550

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

611

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

646

u64 wptr_gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

822

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

883

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1056

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

345

u64 *rptr;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

348

rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

364

u64 wptr;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

368

wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

399

u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

692

u64 wptr_gpu_addr;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

994

u64 gpu_addr;

sys/dev/drm/amd/amdgpu/si_dpm.c

2346

u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;

sys/dev/drm/amd/amdgpu/si_dpm.c

2347

u64 prev_vddc = (u64)prev_std_vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

2348

u64 curr_vddc = (u64)curr_std_vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

2349

u64 pwr_efficiency_ratio, n, d;

sys/dev/drm/amd/amdgpu/si_dpm.c

2354

n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);

sys/dev/drm/amd/amdgpu/si_dpm.c

2358

if (pwr_efficiency_ratio > (u64)0xFFFF)

sys/dev/drm/amd/amdgpu/si_dpm.c

5256

u64 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

5269

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/drm/amd/amdgpu/si_dpm.c

6471

u64 tmp64;

sys/dev/drm/amd/amdgpu/si_dpm.c

6485

tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;

sys/dev/drm/amd/amdgpu/si_dpm.c

6564

u64 tmp64;

sys/dev/drm/amd/amdgpu/si_dpm.c

6576

tmp64 = (u64)duty * 100;

sys/dev/drm/amd/amdgpu/si_dpm.c

6593

u64 tmp64;

sys/dev/drm/amd/amdgpu/si_dpm.c

6609

tmp64 = (u64)speed * duty100;

sys/dev/drm/amd/amdgpu/tonga_ih.c

104

u64 wptr_off;

sys/dev/drm/amd/amdgpu/vega10_ih.c

104

WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vega10_ih.c

234

u64 addr, key;

sys/dev/drm/amd/amdgpu/vega10_ih.c

271

addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12);

sys/dev/drm/amd/amdgpu/vega10_ih.c

341

entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);

sys/dev/drm/amd/amdgpu/vega10_ih.c

93

u64 wptr_off;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2274

amdgpu_bo_get_tiling_flags(rbo, (u64 *)tiling_flags);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3553

chroma_addr = afb->address + (u64)awidth * new_state->fb->height;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

371

(u64 *)&compressor->gpu_addr, &compressor->cpu_addr);

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

74

res_value = div64_u64_rem(arg1_value, arg2_value, (u64 *)&remainder);

sys/dev/drm/amd/display/dc/inc/bw_fixed.h

130

div64_u64_rem(arg1.value, arg2.value, (u64 *)&res.value);

sys/dev/drm/amd/include/linux/chash.h

135

prefix.keys64 = (u64 *)&data \

sys/dev/drm/amd/include/linux/chash.h

219

int __chash_table_copy_in(struct __chash_table *table, u64 key,

sys/dev/drm/amd/include/linux/chash.h

235

int __chash_table_copy_out(struct __chash_table *table, u64 key,

sys/dev/drm/amd/include/linux/chash.h

327

static inline u64 chash_iter_key64(const struct chash_iter iter)

sys/dev/drm/amd/include/linux/chash.h

333

static inline u64 chash_iter_key(const struct chash_iter iter)

sys/dev/drm/amd/include/linux/chash.h

48

u64 *keys64;

sys/dev/drm/amd/include/linux/chash.h

53

u64 hits, hits_steps, hits_time_ns;

sys/dev/drm/amd/include/linux/chash.h

54

u64 miss, miss_steps, miss_time_ns;

sys/dev/drm/amd/include/linux/chash.h

55

u64 relocs, reloc_dist;

sys/dev/drm/amd/lib/chash.c

273

static int chash_table_find(struct chash_iter *iter, u64 key,

sys/dev/drm/amd/lib/chash.c

277

u64 ts1 = local_clock();

sys/dev/drm/amd/lib/chash.c

394

int __chash_table_copy_in(struct __chash_table *table, u64 key,

sys/dev/drm/amd/lib/chash.c

429

int __chash_table_copy_out(struct __chash_table *table, u64 key,

sys/dev/drm/amd/lib/chash.c

465

u64 iterations)

sys/dev/drm/amd/lib/chash.c

469

u64 add_count, rmv_count;

sys/dev/drm/amd/lib/chash.c

470

u64 value;

sys/dev/drm/amd/lib/chash.c

477

ret = chash_table_alloc(&table, bits, key_size, sizeof(u64),

sys/dev/drm/amd/lib/chash.c

490

u64 find_count = rmv_count;

sys/dev/drm/amd/lib/chash.c

578

u64 ts1_ns;

sys/dev/drm/amd/lib/chash.c

619

u64 ts_delta_us = local_clock() - ts1_ns;

sys/dev/drm/amd/lib/chash.c

620

u64 iters_per_second = (u64)chash_test_iters * 1000000;

sys/dev/drm/amd/lib/chash.c

74

u64 __nom = (nom); \

sys/dev/drm/amd/lib/chash.c

75

u64 __denom = (denom); \

sys/dev/drm/amd/lib/chash.c

76

u64 __quot, __frac; \

sys/dev/drm/amd/lib/chash.c

95

u64 quot1, quot2;

sys/dev/drm/amd/powerplay/amd_powerplay.c

152

(u64 *)&gpu_addr,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

196

(u64 *)&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

199

(u64 *)&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

240

(u64 *)&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

256

(u64 *)&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

270

(u64 *)&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

559

(u64 *)&smu_data->header_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

574

(u64 *)&smu_data->smu_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

579

(u64 *)&smu_data->header_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

597

(u64 *)&smu_data->header_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

602

(u64 *)&smu_data->smu_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

769

(u64 *)&smu8_smu->toc_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

779

(u64 *)&smu8_smu->smu_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

827

(u64 *)&smu8_smu->smu_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

831

(u64 *)&smu8_smu->toc_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

848

(u64 *)&smu8_smu->toc_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

851

(u64 *)&smu8_smu->smu_buffer.mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

196

(u64 *)&priv->smu_tables.entry[PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

211

(u64 *)&priv->smu_tables.entry[WMTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

227

(u64 *)&priv->smu_tables.entry[AVFSTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

244

(u64 *)&priv->smu_tables.entry[TOOLSTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

259

(u64 *)&priv->smu_tables.entry[AVFSFUSETABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

274

(u64 *)&priv->smu_tables.entry[TOOLSTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

278

(u64 *)&priv->smu_tables.entry[AVFSTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

282

(u64 *)&priv->smu_tables.entry[WMTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

286

(u64 *)&priv->smu_tables.entry[PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

300

(u64 *)&priv->smu_tables.entry[PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

303

(u64 *)&priv->smu_tables.entry[WMTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

306

(u64 *)&priv->smu_tables.entry[AVFSTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

310

(u64 *)&priv->smu_tables.entry[TOOLSTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

313

(u64 *)&priv->smu_tables.entry[AVFSFUSETABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

222

(u64 *)&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

236

(u64 *)&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

252

(u64 *)&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

267

(u64 *)&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

282

(u64 *)&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

294

(u64 *)&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

299

(u64 *)&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

303

(u64 *)&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

307

(u64 *)&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

322

(u64 *)&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

325

(u64 *)&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

329

(u64 *)&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

332

(u64 *)&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

335

(u64 *)&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

398

(u64 *)&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

412

(u64 *)&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

426

(u64 *)&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

440

(u64 *)&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

454

(u64 *)&priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

468

(u64 *)&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

480

(u64 *)&priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

484

(u64 *)&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

488

(u64 *)&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

492

(u64 *)&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

496

(u64 *)&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

511

(u64 *)&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

514

(u64 *)&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

517

(u64 *)&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

520

(u64 *)&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

523

(u64 *)&priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

526

(u64 *)&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,

sys/dev/drm/drm_crtc_internal.h

231

u32 format, u64 modifier);

sys/dev/drm/drm_dp_mst_topology.c

1393

u64 salt;

sys/dev/drm/drm_dp_mst_topology.c

1400

memcpy(&guid[0], &salt, sizeof(u64));

sys/dev/drm/drm_dp_mst_topology.c

1401

memcpy(&guid[8], &salt, sizeof(u64));

sys/dev/drm/drm_dp_mst_topology.c

2896

u64 kbps;

sys/dev/drm/drm_edid.c

3716

u64 map = 0;

sys/dev/drm/drm_edid.c

3741

map |= (u64)db[2 + count] << (8 * count);

sys/dev/drm/drm_fb_helper.c

2342

const u64 mask = BIT_ULL(fb_helper->connector_count) - 1;

sys/dev/drm/drm_fb_helper.c

2343

u64 conn_configured = 0;

sys/dev/drm/drm_gem.c

382

u32 handle, u64 *offset)

sys/dev/drm/drm_memory.c

86

u64 drm_get_max_iomem(void)

sys/dev/drm/drm_mm.c

168

u64, __subtree_last,

sys/dev/drm/drm_mm.c

172

__drm_mm_interval_first(const struct drm_mm *mm, u64 start, u64 last)

sys/dev/drm/drm_mm.c

233

u64 x = expr(node); \

sys/dev/drm/drm_mm.c

248

static u64 rb_to_hole_size(struct rb_node *rb)

sys/dev/drm/drm_mm.c

257

u64 x = node->hole_size;

sys/dev/drm/drm_mm.c

310

static inline u64 rb_hole_size(struct rb_node *rb)

sys/dev/drm/drm_mm.c

315

static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size)

sys/dev/drm/drm_mm.c

335

static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr)

sys/dev/drm/drm_mm.c

341

u64 hole_start;

sys/dev/drm/drm_mm.c

359

u64 start, u64 end, u64 size,

sys/dev/drm/drm_mm.c

418

u64 end = node->start + node->size;

sys/dev/drm/drm_mm.c

420

u64 hole_start, hole_end;

sys/dev/drm/drm_mm.c

421

u64 adj_start, adj_end;

sys/dev/drm/drm_mm.c

459

static u64 rb_to_hole_size_or_zero(struct rb_node *rb)

sys/dev/drm/drm_mm.c

482

u64 size, u64 alignment,

sys/dev/drm/drm_mm.c

484

u64 range_start, u64 range_end,

sys/dev/drm/drm_mm.c

488

u64 remainder_mask;

sys/dev/drm/drm_mm.c

509

u64 hole_start = __drm_mm_hole_node_start(hole);

sys/dev/drm/drm_mm.c

510

u64 hole_end = hole_start + hole->hole_size;

sys/dev/drm/drm_mm.c

511

u64 adj_start, adj_end;

sys/dev/drm/drm_mm.c

512

u64 col_start, col_end;

sys/dev/drm/drm_mm.c

535

u64 rem;

sys/dev/drm/drm_mm.c

702

u64 size,

sys/dev/drm/drm_mm.c

703

u64 alignment,

sys/dev/drm/drm_mm.c

705

u64 start,

sys/dev/drm/drm_mm.c

706

u64 end,

sys/dev/drm/drm_mm.c

749

u64 hole_start, hole_end;

sys/dev/drm/drm_mm.c

750

u64 col_start, col_end;

sys/dev/drm/drm_mm.c

751

u64 adj_start, adj_end;

sys/dev/drm/drm_mm.c

785

u64 rem;

sys/dev/drm/drm_mm.c

880

u64 hole_start, hole_end;

sys/dev/drm/drm_mm.c

927

void drm_mm_init(struct drm_mm *mm, u64 start, u64 size)

sys/dev/drm/drm_mm.c

965

static u64 drm_mm_dump_hole(struct drm_printer *p, const struct drm_mm_node *entry)

sys/dev/drm/drm_mm.c

967

u64 start, size;

sys/dev/drm/drm_mm.c

986

u64 total_used = 0, total_free = 0, total = 0;

sys/dev/drm/drm_modes.c

162

u64 tmp;

sys/dev/drm/drm_plane.c

564

u32 format, u64 modifier)

sys/dev/drm/drm_rect.c

55

u64 tmp = mul_u32_u32(src, dst - clip);

sys/dev/drm/drm_syncobj.c

171

u64 point,

sys/dev/drm/drm_syncobj.c

233

u32 handle, u64 point,

sys/dev/drm/drm_syncobj.c

829

u64 timeout_ns, timeout_jiffies64;

sys/dev/drm/drm_vblank.c

1069

u64 last;

sys/dev/drm/drm_vblank.c

1124

u64 seq;

sys/dev/drm/drm_vblank.c

1267

u64 diff_ns;

sys/dev/drm/drm_vblank.c

1397

static inline bool vblank_passed(u64 seq, u64 ref)

sys/dev/drm/drm_vblank.c

1403

u64 req_seq,

sys/dev/drm/drm_vblank.c

1411

u64 seq;

sys/dev/drm/drm_vblank.c

1502

static u64 widen_32_to_64(u32 narrow, u64 near)

sys/dev/drm/drm_vblank.c

1531

u64 req_seq, seq;

sys/dev/drm/drm_vblank.c

1650

u64 seq;

sys/dev/drm/drm_vblank.c

1826

u64 seq;

sys/dev/drm/drm_vblank.c

1827

u64 req_seq;

sys/dev/drm/drm_vblank.c

223

u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));

sys/dev/drm/drm_vblank.c

277

static u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

298

u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc)

sys/dev/drm/drm_vblank.c

302

u64 vblank;

sys/dev/drm/drm_vblank.c

524

linedur_ns = div_u64((u64) mode->crtc_htotal * 1000000, dotclock);

sys/dev/drm/drm_vblank.c

525

framedur_ns = div_u64((u64) frame_size * 1000000, dotclock);

sys/dev/drm/drm_vblank.c

687

(u64)ts_etime.tv_sec, ts_etime.tv_nsec / 1000,

sys/dev/drm/drm_vblank.c

688

(u64)ts_vblank_time.tv_sec, ts_vblank_time.tv_nsec / 1000,

sys/dev/drm/drm_vblank.c

752

u64 drm_crtc_vblank_count(struct drm_crtc *crtc)

sys/dev/drm/drm_vblank.c

772

static u64 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

776

u64 vblank_count;

sys/dev/drm/drm_vblank.c

804

u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,

sys/dev/drm/drm_vblank.c

814

u64 seq, ktime_t now)

sys/dev/drm/drm_vblank.c

908

u64 seq;

sys/dev/drm/i915/gvt/gvt.h

106

u64 size;

sys/dev/drm/i915/gvt/gvt.h

377

u32 fence, u64 value);

sys/dev/drm/i915/gvt/gvt.h

387

(*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

395

(*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

460

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);

sys/dev/drm/i915/gvt/gvt.h

461

int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);

sys/dev/drm/i915/gvt/gvt.h

462

int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);

sys/dev/drm/i915/gvt/gvt.h

478

static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)

sys/dev/drm/i915/gvt/gvt.h

481

return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &

sys/dev/drm/i915/gvt/gvt.h

501

int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *,

sys/dev/drm/i915/gvt/gvt.h

503

int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *,

sys/dev/drm/i915/gvt/gvt.h

81

u64 aperture_sz;

sys/dev/drm/i915/gvt/gvt.h

82

u64 hidden_sz;

sys/dev/drm/i915/gvt/hypercall.h

47

int (*set_wp_page)(unsigned long handle, u64 gfn);

sys/dev/drm/i915/gvt/hypercall.h

48

int (*unset_wp_page)(unsigned long handle, u64 gfn);

sys/dev/drm/i915/gvt/hypercall.h

56

int (*set_trap_area)(unsigned long handle, u64 start, u64 end,

sys/dev/drm/i915/gvt/mpt.h

286

struct intel_vgpu *vgpu, u64 start, u64 end, bool map)

sys/dev/drm/i915/i915_drv.c

494

u64 mchbar_addr;

sys/dev/drm/i915/i915_drv.c

500

mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

sys/dev/drm/i915/i915_drv.h

1019

u64 unordered_timeline;

sys/dev/drm/i915/i915_drv.h

1031

u64 object_memory;

sys/dev/drm/i915/i915_drv.h

2080

u64 aging_timestamp;

sys/dev/drm/i915/i915_drv.h

2963

i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);

sys/dev/drm/i915/i915_drv.h

3009

u64 size,

sys/dev/drm/i915/i915_drv.h

3010

u64 alignment,

sys/dev/drm/i915/i915_drv.h

3011

u64 flags);

sys/dev/drm/i915/i915_drv.h

3320

u64 min_size, u64 alignment,

sys/dev/drm/i915/i915_drv.h

3322

u64 start, u64 end,

sys/dev/drm/i915/i915_drv.h

3341

struct drm_mm_node *node, u64 size,

sys/dev/drm/i915/i915_drv.h

3344

struct drm_mm_node *node, u64 size,

sys/dev/drm/i915/i915_drv.h

3345

unsigned alignment, u64 start,

sys/dev/drm/i915/i915_drv.h

3346

u64 end);

sys/dev/drm/i915/i915_drv.h

3596

u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/i915_drv.h

3601

static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/i915_drv.h

3644

(u64)upper << 32 | lower; })

sys/dev/drm/i915/i915_drv.h

3728

static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)

sys/dev/drm/i915/i915_drv.h

3735

return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);

sys/dev/drm/i915/i915_drv.h

814

u64 prev_hw_residency[4];

sys/dev/drm/i915/i915_drv.h

815

u64 cur_residency[4];

sys/dev/drm/i915/i915_drv.h

838

u64 last_count1;

sys/dev/drm/i915/i915_drv.h

841

u64 last_count2;

sys/dev/drm/i915/i915_drv.h

842

u64 last_time2;

sys/dev/drm/i915/i915_drv.h

891

u64 domains;

sys/dev/drm/i915/i915_gem.c

100

u64 size)

sys/dev/drm/i915/i915_gem.c

1132

u64 remain;

sys/dev/drm/i915/i915_gem.c

1156

unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);

sys/dev/drm/i915/i915_gem.c

1206

u64 remain, offset;

sys/dev/drm/i915/i915_gem.c

1323

if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {

sys/dev/drm/i915/i915_gem.c

1392

u64 remain, offset;

sys/dev/drm/i915/i915_gem.c

1569

u64 remain;

sys/dev/drm/i915/i915_gem.c

1610

unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);

sys/dev/drm/i915/i915_gem.c

1668

if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {

sys/dev/drm/i915/i915_gem.c

259

u64 pinned;

sys/dev/drm/i915/i915_gem.c

3271

u64 remain, offset;

sys/dev/drm/i915/i915_gem.c

4683

vma->display_alignment = max_t(u64, vma->display_alignment, alignment);

sys/dev/drm/i915/i915_gem.c

4815

u64 size,

sys/dev/drm/i915/i915_gem.c

4816

u64 alignment,

sys/dev/drm/i915/i915_gem.c

4817

u64 flags)

sys/dev/drm/i915/i915_gem.c

5159

i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)

sys/dev/drm/i915/i915_gem.c

91

u64 size)

sys/dev/drm/i915/i915_gem_context.h

169

u64 lrc_desc;

sys/dev/drm/i915/i915_gem_evict.c

122

u64 min_size, u64 alignment,

sys/dev/drm/i915/i915_gem_evict.c

124

u64 start, u64 end,

sys/dev/drm/i915/i915_gem_evict.c

283

u64 start = target->start;

sys/dev/drm/i915/i915_gem_evict.c

284

u64 end = start + target->size;

sys/dev/drm/i915/i915_gem_execbuffer.c

1256

static u64

sys/dev/drm/i915/i915_gem_execbuffer.c

1262

u64 offset = reloc->offset;

sys/dev/drm/i915/i915_gem_execbuffer.c

1263

u64 target_offset = relocation_target(reloc, target);

sys/dev/drm/i915/i915_gem_execbuffer.c

1273

u64 addr;

sys/dev/drm/i915/i915_gem_execbuffer.c

1348

static u64

sys/dev/drm/i915/i915_gem_execbuffer.c

1490

u64 offset = eb_relocate_entry(eb, vma, r);

sys/dev/drm/i915/i915_gem_execbuffer.c

1543

u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);

sys/dev/drm/i915/i915_gem_execbuffer.c

1618

min_t(u64, BIT_ULL(31), size - copied);

sys/dev/drm/i915/i915_gem_execbuffer.c

2432

args->rsvd2 |= (u64)out_fence_fd << 32;

sys/dev/drm/i915/i915_gem_execbuffer.c

275

u64 invalid_flags; /** Set of execobj.flags that are invalid */

sys/dev/drm/i915/i915_gem_execbuffer.c

302

static inline u64 gen8_canonical_addr(u64 address)

sys/dev/drm/i915/i915_gem_execbuffer.c

307

static inline u64 gen8_noncanonical_addr(u64 address)

sys/dev/drm/i915/i915_gem_execbuffer.c

399

u64 pin_flags;

sys/dev/drm/i915/i915_gem_execbuffer.c

597

u64 pin_flags;

sys/dev/drm/i915/i915_gem_execbuffer.c

897

static inline u64

sys/dev/drm/i915/i915_gem_fence_reg.c

65

u64 val;

sys/dev/drm/i915/i915_gem_fence_reg.c

89

val |= (u64)((stride / 128) - 1) << fence_pitch_shift;

sys/dev/drm/i915/i915_gem_gtt.c

1027

static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)

sys/dev/drm/i915/i915_gem_gtt.c

1116

u64 start = vma->node.start;

sys/dev/drm/i915/i915_gem_gtt.c

1316

const u64 daddr = px_dma(&ppgtt->pml4);

sys/dev/drm/i915/i915_gem_gtt.c

1325

const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);

sys/dev/drm/i915/i915_gem_gtt.c

1398

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

1401

u64 from = start;

sys/dev/drm/i915/i915_gem_gtt.c

1434

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

1437

u64 from = start;

sys/dev/drm/i915/i915_gem_gtt.c

1478

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

1485

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

1490

u64 from = start;

sys/dev/drm/i915/i915_gem_gtt.c

1523

u64 start, u64 length,

sys/dev/drm/i915/i915_gem_gtt.c

1533

u64 pd_len = length;

sys/dev/drm/i915/i915_gem_gtt.c

1534

u64 pd_start = start;

sys/dev/drm/i915/i915_gem_gtt.c

1550

u64 va = (pdpe << GEN8_PDPE_SHIFT |

sys/dev/drm/i915/i915_gem_gtt.c

1581

u64 start = 0, length = ppgtt->vm.total;

sys/dev/drm/i915/i915_gem_gtt.c

1584

u64 pml4e;

sys/dev/drm/i915/i915_gem_gtt.c

1605

u64 start = 0, length = ppgtt->vm.total;

sys/dev/drm/i915/i915_gem_gtt.c

1606

u64 from = start;

sys/dev/drm/i915/i915_gem_gtt.c

1845

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

1927

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

1931

u64 from = start;

sys/dev/drm/i915/i915_gem_gtt.c

2380

u64 fault_addr;

sys/dev/drm/i915/i915_gem_gtt.c

2384

fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

sys/dev/drm/i915/i915_gem_gtt.c

2385

((u64)fault_data0 << 12);

sys/dev/drm/i915/i915_gem_gtt.c

2465

u64 offset,

sys/dev/drm/i915/i915_gem_gtt.c

2508

u64 offset,

sys/dev/drm/i915/i915_gem_gtt.c

2548

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

2553

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

2591

u64 offset;

sys/dev/drm/i915/i915_gem_gtt.c

2607

u64 offset,

sys/dev/drm/i915/i915_gem_gtt.c

2645

u64 start;

sys/dev/drm/i915/i915_gem_gtt.c

2646

u64 length;

sys/dev/drm/i915/i915_gem_gtt.c

2660

u64 start,

sys/dev/drm/i915/i915_gem_gtt.c

2661

u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

2669

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

2693

u64 offset,

sys/dev/drm/i915/i915_gem_gtt.c

2716

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

2848

u64 *start,

sys/dev/drm/i915/i915_gem_gtt.c

2849

u64 *end)

sys/dev/drm/i915/i915_gem_gtt.c

3065

static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)

sys/dev/drm/i915/i915_gem_gtt.c

3226

u64 pat = 0;

sys/dev/drm/i915/i915_gem_gtt.c

3583

ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);

sys/dev/drm/i915/i915_gem_gtt.c

3585

min_t(u64, ggtt->mappable_end, ggtt->vm.total);

sys/dev/drm/i915/i915_gem_gtt.c

3594

min_t(u64, ggtt->mappable_end, ggtt->vm.total);

sys/dev/drm/i915/i915_gem_gtt.c

3606

DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);

sys/dev/drm/i915/i915_gem_gtt.c

3608

(u64)resource_size(&intel_graphics_stolen_res) >> 20);

sys/dev/drm/i915/i915_gem_gtt.c

3946

u64 size, u64 offset, unsigned long color,

sys/dev/drm/i915/i915_gem_gtt.c

3976

static u64 random_offset(u64 start, u64 end, u64 len, u64 align)

sys/dev/drm/i915/i915_gem_gtt.c

3978

u64 range, addr;

sys/dev/drm/i915/i915_gem_gtt.c

3985

if (sizeof(unsigned long) == sizeof(u64)) {

sys/dev/drm/i915/i915_gem_gtt.c

4037

u64 size, u64 alignment, unsigned long color,

sys/dev/drm/i915/i915_gem_gtt.c

4038

u64 start, u64 end, unsigned int flags)

sys/dev/drm/i915/i915_gem_gtt.c

4041

u64 offset;

sys/dev/drm/i915/i915_gem_gtt.c

607

const u64 val)

sys/dev/drm/i915/i915_gem_gtt.c

609

u64 * const vaddr = kmap_atomic(p->page);

sys/dev/drm/i915/i915_gem_gtt.c

620

fill_page_dma(vm, p, (u64)v << 32 | v);

sys/dev/drm/i915/i915_gem_gtt.c

864

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

903

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

945

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

967

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.c

990

u64 start, u64 length)

sys/dev/drm/i915/i915_gem_gtt.h

157

#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))

sys/dev/drm/i915/i915_gem_gtt.h

177

u64 offset;

sys/dev/drm/i915/i915_gem_gtt.h

190

BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));

sys/dev/drm/i915/i915_gem_gtt.h

289

u64 total; /* size addr space maps (ex. 2GB for ggtt) */

sys/dev/drm/i915/i915_gem_gtt.h

290

u64 reserved; /* size addr space reserved */

sys/dev/drm/i915/i915_gem_gtt.h

349

u64 start, u64 length);

sys/dev/drm/i915/i915_gem_gtt.h

351

u64 start, u64 length);

sys/dev/drm/i915/i915_gem_gtt.h

354

u64 offset,

sys/dev/drm/i915/i915_gem_gtt.h

465

static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)

sys/dev/drm/i915/i915_gem_gtt.h

476

static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)

sys/dev/drm/i915/i915_gem_gtt.h

478

const u64 mask = ~((1ULL << pde_shift) - 1);

sys/dev/drm/i915/i915_gem_gtt.h

479

u64 end;

sys/dev/drm/i915/i915_gem_gtt.h

492

static inline u32 i915_pde_index(u64 addr, u32 shift)

sys/dev/drm/i915/i915_gem_gtt.h

529

({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \

sys/dev/drm/i915/i915_gem_gtt.h

537

({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \

sys/dev/drm/i915/i915_gem_gtt.h

545

({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \

sys/dev/drm/i915/i915_gem_gtt.h

549

static inline u32 gen8_pte_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

554

static inline u32 gen8_pde_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

559

static inline u32 gen8_pdpe_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

564

static inline u32 gen8_pml4e_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

569

static inline u64 gen8_pte_count(u64 address, u64 length)

sys/dev/drm/i915/i915_gem_gtt.h

659

u64 size, u64 offset, unsigned long color,

sys/dev/drm/i915/i915_gem_gtt.h

664

u64 size, u64 alignment, unsigned long color,

sys/dev/drm/i915/i915_gem_gtt.h

665

u64 start, u64 end, unsigned int flags);

sys/dev/drm/i915/i915_gem_gtt.h

70

typedef u64 gen8_pte_t;

sys/dev/drm/i915/i915_gem_gtt.h

71

typedef u64 gen8_pde_t;

sys/dev/drm/i915/i915_gem_gtt.h

72

typedef u64 gen8_ppgtt_pdpe_t;

sys/dev/drm/i915/i915_gem_gtt.h

73

typedef u64 gen8_ppgtt_pml4e_t;

sys/dev/drm/i915/i915_gem_render_state.c

97

u64 r = s + so->vma->node.start;

sys/dev/drm/i915/i915_gem_stolen.c

372

u64 reg_val = I915_READ64(GEN6_STOLEN_RESERVED);

sys/dev/drm/i915/i915_gem_stolen.c

46

struct drm_mm_node *node, u64 size,

sys/dev/drm/i915/i915_gem_stolen.c

47

unsigned alignment, u64 start, u64 end)

sys/dev/drm/i915/i915_gem_stolen.c

496

(u64)resource_size(&dev_priv->dsm) >> 10,

sys/dev/drm/i915/i915_gem_stolen.c

497

((u64)resource_size(&dev_priv->dsm) - reserved_total) >> 10);

sys/dev/drm/i915/i915_gem_stolen.c

68

struct drm_mm_node *node, u64 size,

sys/dev/drm/i915/i915_gpu_error.c

1221

ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;

sys/dev/drm/i915/i915_gpu_error.c

1222

ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;

sys/dev/drm/i915/i915_gpu_error.c

490

u64 start = ee->batchbuffer->gtt_offset;

sys/dev/drm/i915/i915_gpu_error.c

491

u64 end = start + ee->batchbuffer->gtt_size;

sys/dev/drm/i915/i915_gpu_error.c

960

const u64 slot = ggtt->error_capture.start;

sys/dev/drm/i915/i915_gpu_error.c

971

num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;

sys/dev/drm/i915/i915_gpu_error.h

115

u64 bbaddr;

sys/dev/drm/i915/i915_gpu_error.h

116

u64 acthd;

sys/dev/drm/i915/i915_gpu_error.h

118

u64 faddr;

sys/dev/drm/i915/i915_gpu_error.h

136

u64 gtt_offset;

sys/dev/drm/i915/i915_gpu_error.h

137

u64 gtt_size;

sys/dev/drm/i915/i915_gpu_error.h

172

u64 pdp[4];

sys/dev/drm/i915/i915_gpu_error.h

182

u64 gtt_offset;

sys/dev/drm/i915/i915_gpu_error.h

76

u64 fence[I915_MAX_NUM_FENCES];

sys/dev/drm/i915/i915_irq.c

1251

u64 time, c0;

sys/dev/drm/i915/i915_perf.c

2648

static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)

sys/dev/drm/i915/i915_perf.c

2670

u64 __user *uprops,

sys/dev/drm/i915/i915_perf.c

2674

u64 __user *uprop = uprops;

sys/dev/drm/i915/i915_perf.c

2696

u64 oa_period, oa_freq_hz;

sys/dev/drm/i915/i915_perf.c

2697

u64 id, value;

sys/dev/drm/i915/i915_perf.c

2765

u64 tmp = NSEC_PER_SEC;

sys/dev/drm/i915/i915_perf.c

3314

u64 *arg = data;

sys/dev/drm/i915/i915_perf.c

358

u64 single_context:1;

sys/dev/drm/i915/i915_perf.c

359

u64 ctx_handle;

sys/dev/drm/i915/i915_perf.c

459

u64 now;

sys/dev/drm/i915/i915_pmu.c

14

#define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)

sys/dev/drm/i915/i915_pmu.c

25

static u8 engine_config_sample(u64 config)

sys/dev/drm/i915/i915_pmu.c

279

static u64 count_interrupts(struct drm_i915_private *i915)

sys/dev/drm/i915/i915_pmu.c

283

u64 sum = 0;

sys/dev/drm/i915/i915_pmu.c

340

config_status(struct drm_i915_private *i915, u64 config)

sys/dev/drm/i915/i915_pmu.c

425

static u64 __get_rc6(struct drm_i915_private *i915)

sys/dev/drm/i915/i915_pmu.c

427

u64 val;

sys/dev/drm/i915/i915_pmu.c

443

static u64 get_rc6(struct drm_i915_private *i915)

sys/dev/drm/i915/i915_pmu.c

447

u64 val;

sys/dev/drm/i915/i915_pmu.c

45

static bool is_engine_config(u64 config)

sys/dev/drm/i915/i915_pmu.c

50

static unsigned int config_enabled_bit(u64 config)

sys/dev/drm/i915/i915_pmu.c

523

static u64 __i915_pmu_event_read(struct perf_event *event)

sys/dev/drm/i915/i915_pmu.c

527

u64 val = 0;

sys/dev/drm/i915/i915_pmu.c

572

u64 prev, new;

sys/dev/drm/i915/i915_pmu.c

58

static u64 config_enabled_mask(u64 config)

sys/dev/drm/i915/i915_pmu.c

75

u64 enable;

sys/dev/drm/i915/i915_pmu.c

798

add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)

sys/dev/drm/i915/i915_pmu.c

826

u64 config;

sys/dev/drm/i915/i915_pmu.h

35

u64 cur;

sys/dev/drm/i915/i915_pmu.h

67

u64 enable;

sys/dev/drm/i915/i915_pvinfo.h

60

u64 magic; /* VGT_MAGIC */

sys/dev/drm/i915/i915_syncmap.c

112

__sync_branch_idx(const struct i915_syncmap *p, u64 id)

sys/dev/drm/i915/i915_syncmap.c

118

__sync_leaf_idx(const struct i915_syncmap *p, u64 id)

sys/dev/drm/i915/i915_syncmap.c

124

static inline u64 __sync_branch_prefix(const struct i915_syncmap *p, u64 id)

sys/dev/drm/i915/i915_syncmap.c

129

static inline u64 __sync_leaf_prefix(const struct i915_syncmap *p, u64 id)

sys/dev/drm/i915/i915_syncmap.c

154

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

199

__sync_alloc_leaf(struct i915_syncmap *parent, u64 id)

sys/dev/drm/i915/i915_syncmap.c

214

static inline void __sync_set_seqno(struct i915_syncmap *p, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

230

static noinline int __sync_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

353

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

74

u64 prefix;

sys/dev/drm/i915/i915_syncmap.h

34

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/drm/i915/i915_syncmap.h

35

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/drm/i915/i915_sysfs.c

46

u64 res;

sys/dev/drm/i915/i915_timeline.h

104

u64 context, u32 seqno)

sys/dev/drm/i915/i915_timeline.h

116

u64 context, u32 seqno)

sys/dev/drm/i915/i915_timeline.h

36

u64 fence_context;

sys/dev/drm/i915/i915_utils.h

105

static inline u64 ptr_to_u64(const void *ptr)

sys/dev/drm/i915/i915_utils.h

111

typecheck(u64, x); \

sys/dev/drm/i915/i915_vgpu.c

63

u64 magic;

sys/dev/drm/i915/i915_vma.c

157

GEM_BUG_ON(range_overflows_t(u64,

sys/dev/drm/i915/i915_vma.c

430

u64 size, u64 alignment, u64 flags)

sys/dev/drm/i915/i915_vma.c

543

i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)

sys/dev/drm/i915/i915_vma.c

547

u64 start, end;

sys/dev/drm/i915/i915_vma.c

571

end = min_t(u64, end, dev_priv->ggtt.mappable_end);

sys/dev/drm/i915/i915_vma.c

573

end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);

sys/dev/drm/i915/i915_vma.c

604

u64 offset = flags & PIN_OFFSET_MASK;

sys/dev/drm/i915/i915_vma.c

633

u64 page_alignment =

sys/dev/drm/i915/i915_vma.c

70

u64 timeline;

sys/dev/drm/i915/i915_vma.c

721

u64 size, u64 alignment, u64 flags)

sys/dev/drm/i915/i915_vma.c

895

u64 vma_offset;

sys/dev/drm/i915/i915_vma.c

939

static struct i915_gem_active *active_instance(struct i915_vma *vma, u64 idx)

sys/dev/drm/i915/i915_vma.h

277

u64 size, u64 alignment, u64 flags);

sys/dev/drm/i915/i915_vma.h

287

u64 size, u64 alignment, u64 flags);

sys/dev/drm/i915/i915_vma.h

289

i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)

sys/dev/drm/i915/i915_vma.h

59

u64 size;

sys/dev/drm/i915/i915_vma.h

60

u64 display_alignment;

sys/dev/drm/i915/intel_color.c

157

const u64 *input;

sys/dev/drm/i915/intel_color.c

158

u64 temp[9];

sys/dev/drm/i915/intel_color.c

89

static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)

sys/dev/drm/i915/intel_color.c

94

u64 user_coeff = input[i];

sys/dev/drm/i915/intel_ddi.c

1457

u64 tmp;

sys/dev/drm/i915/intel_ddi.c

1498

tmp = (u64)m1 * m2_int * refclk +

sys/dev/drm/i915/intel_ddi.c

1499

(((u64)m1 * m2_frac * refclk) >> 22);

sys/dev/drm/i915/intel_ddi.c

2096

static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,

sys/dev/drm/i915/intel_ddi.c

2100

u64 domains;

sys/dev/drm/i915/intel_display.c

10008

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_display.c

12795

u64 put_domains[I915_MAX_PIPES] = {};

sys/dev/drm/i915/intel_display.c

15988

u64 get_domains;

sys/dev/drm/i915/intel_display.c

16096

u64 put_domains;

sys/dev/drm/i915/intel_display.c

2481

bool is_ccs_modifier(u64 modifier)

sys/dev/drm/i915/intel_display.c

3227

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_display.c

6052

static u64 get_crtc_power_domains(struct drm_crtc *crtc,

sys/dev/drm/i915/intel_display.c

6060

u64 mask;

sys/dev/drm/i915/intel_display.c

6087

static u64

sys/dev/drm/i915/intel_display.c

6094

u64 domains, new_domains, old_domains;

sys/dev/drm/i915/intel_display.c

6109

u64 domains)

sys/dev/drm/i915/intel_display.c

6309

u64 domains;

sys/dev/drm/i915/intel_display.c

9508

u64 *power_domain_mask)

sys/dev/drm/i915/intel_display.c

9560

u64 *power_domain_mask)

sys/dev/drm/i915/intel_display.c

9657

u64 power_domain_mask;

sys/dev/drm/i915/intel_display.c

9867

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_display.h

410

bool is_ccs_modifier(u64 modifier);

sys/dev/drm/i915/intel_dpll_mgr.c

2209

dco = div_u64((u64)dco_freq << 15, ref_freq);

sys/dev/drm/i915/intel_dpll_mgr.c

670

diff = abs_diff((u64)(freq2k * p * r2), (u64)(LC_FREQ_2K * n2));

sys/dev/drm/i915/intel_dpll_mgr.c

671

diff_best = abs_diff((u64)(freq2k * best->p * best->r2),

sys/dev/drm/i915/intel_dpll_mgr.c

672

(u64)(LC_FREQ_2K * best->n2));

sys/dev/drm/i915/intel_drv.h

101

u64 now = local_clock(); \

sys/dev/drm/i915/intel_drv.h

152

#define GBps(x) ((u64)1000 * MBps((x)))

sys/dev/drm/i915/intel_drv.h

1685

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_drv.h

1964

u64 value);

sys/dev/drm/i915/intel_drv.h

2155

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_drv.h

270

u64 (*get_power_domains)(struct intel_encoder *encoder,

sys/dev/drm/i915/intel_drv.h

93

u64 base; \

sys/dev/drm/i915/intel_drv.h

984

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_engine_cs.c

1286

u64 addr;

sys/dev/drm/i915/intel_engine_cs.c

685

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_engine_cs.c

688

u64 acthd;

sys/dev/drm/i915/intel_engine_cs.c

701

u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_engine_cs.c

704

u64 bbaddr;

sys/dev/drm/i915/intel_fbc.c

441

u64 end;

sys/dev/drm/i915/intel_fbc.c

526

GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,

sys/dev/drm/i915/intel_fbc.c

529

GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,

sys/dev/drm/i915/intel_guc.c

637

u64 flags;

sys/dev/drm/i915/intel_guc.h

143

GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));

sys/dev/drm/i915/intel_guc_fwif.h

233

u64 value_qw;

sys/dev/drm/i915/intel_guc_fwif.h

252

u64 db_base_addr;

sys/dev/drm/i915/intel_guc_fwif.h

256

u64 wq_base_addr;

sys/dev/drm/i915/intel_guc_fwif.h

298

u64 db_trigger_cpu;

sys/dev/drm/i915/intel_guc_fwif.h

300

u64 db_trigger_phy;

sys/dev/drm/i915/intel_guc_fwif.h

321

u64 reserved1[1];

sys/dev/drm/i915/intel_guc_fwif.h

323

u64 desc_private;

sys/dev/drm/i915/intel_guc_fwif.h

384

u64 host_private; /* host private data */

sys/dev/drm/i915/intel_guc_fwif.h

592

u64 execlist_ctx;

sys/dev/drm/i915/intel_guc_submission.c

523

u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);

sys/dev/drm/i915/intel_guc_submission.c

590

GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0);

sys/dev/drm/i915/intel_guc_submission.h

74

u64 submissions[I915_NUM_ENGINES];

sys/dev/drm/i915/intel_hangcheck.c

211

head_stuck(struct intel_engine_cs *engine, u64 acthd)

sys/dev/drm/i915/intel_hangcheck.c

229

engine_stuck(struct intel_engine_cs *engine, u64 acthd)

sys/dev/drm/i915/intel_hangcheck.c

37

u64 offset)

sys/dev/drm/i915/intel_hangcheck.c

64

u64 offset = 0;

sys/dev/drm/i915/intel_lrc.c

2051

u64 offset, u32 len,

sys/dev/drm/i915/intel_lrc.c

225

u64 desc;

sys/dev/drm/i915/intel_lrc.c

244

desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;

sys/dev/drm/i915/intel_lrc.c

247

desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;

sys/dev/drm/i915/intel_lrc.c

252

desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;

sys/dev/drm/i915/intel_lrc.c

256

desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */

sys/dev/drm/i915/intel_lrc.c

422

static u64 execlists_update_context(struct i915_request *rq)

sys/dev/drm/i915/intel_lrc.c

459

static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)

sys/dev/drm/i915/intel_lrc.c

495

u64 desc;

sys/dev/drm/i915/intel_lrc_reg.h

51

const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \

sys/dev/drm/i915/intel_lrc_reg.h

58

const u64 addr__ = px_dma(&ppgtt->pml4); \

sys/dev/drm/i915/intel_opregion.c

123

u64 fdss;

sys/dev/drm/i915/intel_opregion.c

126

u64 rvda; /* Physical address of raw vbt data */

sys/dev/drm/i915/intel_panel.c

393

u64 target_val;

sys/dev/drm/i915/intel_pm.c

3828

u64 total_data_bw;

sys/dev/drm/i915/intel_pm.c

3837

total_data_bw = (u64)total_data_rate * drm_mode_vrefresh(adjusted_mode);

sys/dev/drm/i915/intel_pm.c

7446

GEM_BUG_ON(range_overflows_t(u64,

sys/dev/drm/i915/intel_pm.c

7788

u64 total_count, diff, ret;

sys/dev/drm/i915/intel_pm.c

7895

u64 now, diff, diffms;

sys/dev/drm/i915/intel_pm.c

9731

static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_pm.c

9774

return lower | (u64)upper << 8;

sys/dev/drm/i915/intel_pm.c

9777

u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_pm.c

9780

u64 time_hw, prev_hw, overflow_hw;

sys/dev/drm/i915/intel_psr.c

832

u64 val)

sys/dev/drm/i915/intel_ringbuffer.c

1045

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

1939

GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));

sys/dev/drm/i915/intel_ringbuffer.c

1942

memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));

sys/dev/drm/i915/intel_ringbuffer.c

1974

memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);

sys/dev/drm/i915/intel_ringbuffer.c

2066

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

2086

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

961

u64 offset, u32 length,

sys/dev/drm/i915/intel_ringbuffer.c

984

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.h

120

u64 acthd;

sys/dev/drm/i915/intel_ringbuffer.h

475

u64 offset, u32 length,

sys/dev/drm/i915/intel_ringbuffer.h

909

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);

sys/dev/drm/i915/intel_ringbuffer.h

910

u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);

sys/dev/drm/i915/intel_runtime_pm.c

3019

u64 power_well_ids = 0;

sys/dev/drm/i915/intel_sprite.c

290

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_sprite.c

893

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_tv.c

1332

u64 tmp;

sys/dev/drm/i915/intel_uncore.c

432

static u64 gen9_edram_size(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_uncore.c

444

u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_uncore.h

152

u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

sys/dev/drm/i915/intel_uncore.h

76

u64 (*mmio_readq)(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_vbt_defs.h

746

u64 edp_vswing_preemph; /* 173 */

sys/dev/drm/include/asm/io.h

84

writeq(u64 value, volatile void __iomem *addr)

sys/dev/drm/include/asm/string_64.h

42

memset64(u64 *s, uint64_t v, size_t n)

sys/dev/drm/include/asm/string_64.h

44

u64 *dest = s;

sys/dev/drm/include/asm/string_64.h

57

return memset64((u64 *)p, (uint64_t)v, n);

sys/dev/drm/include/drm/drm_atomic.h

169

u64 last_vblank_count;

sys/dev/drm/include/drm/drm_cache.h

42

u64 drm_get_max_iomem(void);

sys/dev/drm/include/drm/drm_connector.h

205

u64 y420_cmdb_map;

sys/dev/drm/include/drm/drm_fixed.h

154

u64 a_abs = a_neg ? -a : a;

sys/dev/drm/include/drm/drm_fixed.h

155

u64 b_abs = b_neg ? -b : b;

sys/dev/drm/include/drm/drm_fixed.h

156

u64 rem;

sys/dev/drm/include/drm/drm_fixed.h

159

u64 res_abs = div64_u64_rem(a_abs, b_abs, &rem);

sys/dev/drm/include/drm/drm_fixed.h

177

u64 summand = (rem << 1) >= b_abs;

sys/dev/drm/include/drm/drm_fixed.h

192

u64 count = 1;

sys/dev/drm/include/drm/drm_fixed.h

39

#define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12)

sys/dev/drm/include/drm/drm_fixed.h

64

u64 tmp = ((u64)A.full << 13);

sys/dev/drm/include/drm/drm_gem.h

314

u32 handle, u64 *offset);

sys/dev/drm/include/drm/drm_mm.h

159

u64 start;

sys/dev/drm/include/drm/drm_mm.h

161

u64 size;

sys/dev/drm/include/drm/drm_mm.h

169

u64 __subtree_last;

sys/dev/drm/include/drm/drm_mm.h

170

u64 hole_size;

sys/dev/drm/include/drm/drm_mm.h

198

u64 *start, u64 *end);

sys/dev/drm/include/drm/drm_mm.h

227

u64 size;

sys/dev/drm/include/drm/drm_mm.h

228

u64 alignment;

sys/dev/drm/include/drm/drm_mm.h

229

u64 remainder_mask;

sys/dev/drm/include/drm/drm_mm.h

231

u64 range_start;

sys/dev/drm/include/drm/drm_mm.h

232

u64 range_end;

sys/dev/drm/include/drm/drm_mm.h

234

u64 hit_start;

sys/dev/drm/include/drm/drm_mm.h

235

u64 hit_end;

sys/dev/drm/include/drm/drm_mm.h

294

static inline u64 __drm_mm_hole_node_start(const struct drm_mm_node *hole_node)

sys/dev/drm/include/drm/drm_mm.h

310

static inline u64 drm_mm_hole_node_start(const struct drm_mm_node *hole_node)

sys/dev/drm/include/drm/drm_mm.h

316

static inline u64 __drm_mm_hole_node_end(const struct drm_mm_node *hole_node)

sys/dev/drm/include/drm/drm_mm.h

332

static inline u64 drm_mm_hole_node_end(const struct drm_mm_node *hole_node)

sys/dev/drm/include/drm/drm_mm.h

405

u64 size,

sys/dev/drm/include/drm/drm_mm.h

406

u64 alignment,

sys/dev/drm/include/drm/drm_mm.h

408

u64 start,

sys/dev/drm/include/drm/drm_mm.h

409

u64 end,

sys/dev/drm/include/drm/drm_mm.h

431

u64 size, u64 alignment,

sys/dev/drm/include/drm/drm_mm.h

456

u64 size)

sys/dev/drm/include/drm/drm_mm.h

463

void drm_mm_init(struct drm_mm *mm, u64 start, u64 size);

sys/dev/drm/include/drm/drm_mm.h

480

__drm_mm_interval_first(const struct drm_mm *mm, u64 start, u64 last);

sys/dev/drm/include/drm/drm_mm.h

506

u64 size, u64 alignment, unsigned long color,

sys/dev/drm/include/drm/drm_mm.h

507

u64 start, u64 end,

sys/dev/drm/include/drm/drm_mm.h

531

u64 size,

sys/dev/drm/include/drm/drm_mm.h

532

u64 alignment,

sys/dev/drm/include/drm/drm_syncobj.h

134

void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, u64 point,

sys/dev/drm/include/drm/drm_syncobj.h

137

u32 handle, u64 point,

sys/dev/drm/include/drm/drm_vblank.h

115

u64 count;

sys/dev/drm/include/drm/drm_vblank.h

179

u64 drm_crtc_vblank_count(struct drm_crtc *crtc);

sys/dev/drm/include/drm/drm_vblank.h

180

u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,

sys/dev/drm/include/drm/drm_vblank.h

187

u64 *seq,

sys/dev/drm/include/drm/drm_vblank.h

198

u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);

sys/dev/drm/include/drm/drm_vblank.h

53

u64 sequence;

sys/dev/drm/include/drm/intel-gtt.h

79

void intel_gtt_get(u64 *gtt_total,

sys/dev/drm/include/linux/async.h

33

typedef u64 async_cookie_t;

sys/dev/drm/include/linux/atomic.h

172

(int8_t *)&__ret, (u64)(new)) && __ret == (old)) \

sys/dev/drm/include/linux/atomic.h

177

(int16_t *)&__ret, (u64)(new)) && __ret == (old)) \

sys/dev/drm/include/linux/atomic.h

182

(int32_t *)&__ret, (u64)(new)) && __ret == (old)) \

sys/dev/drm/include/linux/atomic.h

187

(int64_t *)&__ret, (u64)(new)) && __ret == (old)) \

sys/dev/drm/include/linux/dma-fence-array.h

94

u64 context, unsigned seqno,

sys/dev/drm/include/linux/dma-fence.h

173

u64 dma_fence_context_alloc(unsigned num);

sys/dev/drm/include/linux/dma-fence.h

47

u64 context;

sys/dev/drm/include/linux/dma-fence.h

85

spinlock_t *lock, u64 context, unsigned seqno);

sys/dev/drm/include/linux/hash.h

32

static inline u64 hash_64(u64 val, unsigned int bits)

sys/dev/drm/include/linux/hash.h

34

u64 ret;

sys/dev/drm/include/linux/hrtimer.h

54

u64 timeout_us;

sys/dev/drm/include/linux/hrtimer.h

68

u64 range_ns, const enum hrtimer_mode mode);

sys/dev/drm/include/linux/jiffies.h

78

static inline u64 get_jiffies_64(void)

sys/dev/drm/include/linux/jiffies.h

80

return (u64)ticks;

sys/dev/drm/include/linux/jiffies.h

83

static inline u64 nsecs_to_jiffies(u64 n)

sys/dev/drm/include/linux/jiffies.h

88

static inline u64 nsecs_to_jiffies64(u64 n)

sys/dev/drm/include/linux/jiffies.h

99

static inline u64

sys/dev/drm/include/linux/kernel.h

166

u64_to_user_ptr(u64 address)

sys/dev/drm/include/linux/kernel.h

51

#define U64_MAX ((u64)~0ULL)

sys/dev/drm/include/linux/ktime.h

115

ns_to_ktime(u64 ns)

sys/dev/drm/include/linux/ktime.h

70

ktime_add_ms(const ktime_t kt, const u64 ms)

sys/dev/drm/include/linux/log2.h

133

fls((u32)(n)) - 1 : flsll((u64)(n)) - 1 \

sys/dev/drm/include/linux/math64.h

75

static inline u64

sys/dev/drm/include/linux/math64.h

76

div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder)

sys/dev/drm/include/linux/math64.h

82

static inline u64

sys/dev/drm/include/linux/math64.h

89

mul_u64_u32_div(u64 x, u32 y, u32 div)

sys/dev/drm/include/linux/pci.h

218

pci_set_dma_mask(struct pci_dev *dev, u64 mask)

sys/dev/drm/include/linux/pci.h

224

pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)

sys/dev/drm/include/linux/timekeeping.h

30

static inline u64 ktime_get_raw_ns(void)

sys/dev/drm/include/linux/types.h

34

typedef u64 phys_addr_t;

sys/dev/drm/linux_fence-array.c

169

u64 context, unsigned seqno,

sys/dev/drm/linux_fence.c

30

spinlock_t *lock, u64 context, unsigned seqno)

sys/dev/drm/linux_fence.c

67

u64

sys/dev/drm/linux_hrtimer.c

89

u64 range_ns, const enum hrtimer_mode mode)

sys/dev/drm/radeon/atombios_crtc.c

1183

r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, (u64 *)&fb_location);

sys/dev/drm/radeon/atombios_crtc.c

1494

r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, (u64 *)&fb_location);

sys/dev/drm/radeon/ci_dpm.c

1000

u64 tmp64;

sys/dev/drm/radeon/ci_dpm.c

1014

tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;

sys/dev/drm/radeon/ci_dpm.c

1113

u64 tmp64;

sys/dev/drm/radeon/ci_dpm.c

1124

tmp64 = (u64)duty * 100;

sys/dev/drm/radeon/ci_dpm.c

1139

u64 tmp64;

sys/dev/drm/radeon/ci_dpm.c

1156

tmp64 = (u64)speed * duty100;

sys/dev/drm/radeon/cik.c

3570

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/cik.c

3611

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/cik.c

4077

u64 rb_addr;

sys/dev/drm/radeon/cik.c

4539

u64 hqd_gpu_addr;

sys/dev/drm/radeon/cik.c

4540

u64 mqd_gpu_addr;

sys/dev/drm/radeon/cik.c

4541

u64 eop_gpu_addr;

sys/dev/drm/radeon/cik.c

4542

u64 wb_gpu_addr;

sys/dev/drm/radeon/cik.c

5647

u64 tmp = RREG32(MC_VM_FB_OFFSET);

sys/dev/drm/radeon/cik.c

9158

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/drm/radeon/cik.c

9275

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/radeon/cik.c

9277

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/radeon/cik_sdma.c

202

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/cik_sdma.c

231

u64 addr = semaphore->gpu_addr;

sys/dev/drm/radeon/cik_sdma.c

650

u64 gpu_addr;

sys/dev/drm/radeon/cik_sdma.c

707

u64 gpu_addr;

sys/dev/drm/radeon/evergreen.c

1400

void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base,

sys/dev/drm/radeon/evergreen.c

2152

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/radeon/evergreen.c

2154

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/radeon/evergreen.c

4141

u64 reg_list_mc_addr;

sys/dev/drm/radeon/evergreen_cs.c

1819

((u64)(tmp & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

1865

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

1900

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

1928

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2031

u64 size = pkt->opcode == PACKET3_DRAW_INDIRECT ? 16 : 20;

sys/dev/drm/radeon/evergreen_cs.c

2101

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2113

u64 offset, tmp;

sys/dev/drm/radeon/evergreen_cs.c

2154

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2192

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2248

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2270

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2292

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2490

u64 offset;

sys/dev/drm/radeon/evergreen_cs.c

2497

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2509

u64 offset;

sys/dev/drm/radeon/evergreen_cs.c

2516

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2529

u64 offset;

sys/dev/drm/radeon/evergreen_cs.c

2541

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/drm/radeon/evergreen_cs.c

2562

u64 offset;

sys/dev/drm/radeon/evergreen_cs.c

2570

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2589

u64 offset;

sys/dev/drm/radeon/evergreen_cs.c

2597

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2650

offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2802

u64 src_offset, dst_offset, dst2_offset;

sys/dev/drm/radeon/evergreen_cs.c

2836

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2868

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2870

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2897

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2903

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2927

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2929

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2969

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2971

dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2973

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3013

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3075

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3108

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3114

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3162

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3196

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/drm/radeon/evergreen_cs.c

948

u64 offset = (u64)track->vgt_strmout_bo_offset[i] +

sys/dev/drm/radeon/evergreen_cs.c

949

(u64)track->vgt_strmout_size[i];

sys/dev/drm/radeon/evergreen_dma.c

43

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/ni.c

1416

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/ni.c

2523

u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);

sys/dev/drm/radeon/ni_dpm.c

1395

u64 tmp, n, d;

sys/dev/drm/radeon/ni_dpm.c

1420

n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);

sys/dev/drm/radeon/ni_dpm.c

1421

d = ((u64)std_vddc_high * (u64)std_vddc_high * 100);

sys/dev/drm/radeon/ni_dpm.c

2009

u64 tmp;

sys/dev/drm/radeon/ni_dpm.c

2023

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;

sys/dev/drm/radeon/r100.c

156

void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/radeon/r100.c

2784

u64 config_aper_size;

sys/dev/drm/radeon/r100.c

2839

u64 base;

sys/dev/drm/radeon/r300.c

468

u64 base;

sys/dev/drm/radeon/r600.c

1382

u64 size_bf, size_af;

sys/dev/drm/radeon/r600.c

1413

u64 base = 0;

sys/dev/drm/radeon/r600.c

2887

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/r600.c

3511

(u64 *)&rdev->ih.gpu_addr);

sys/dev/drm/radeon/r600_cs.c

1214

track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;

sys/dev/drm/radeon/r600_cs.c

1245

track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;

sys/dev/drm/radeon/r600_cs.c

1472

u64 base_offset,

sys/dev/drm/radeon/r600_cs.c

1473

u64 mip_offset,

sys/dev/drm/radeon/r600_cs.c

1481

u64 base_align;

sys/dev/drm/radeon/r600_cs.c

1675

((u64)(tmp & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1716

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1768

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1780

u64 offset, tmp;

sys/dev/drm/radeon/r600_cs.c

1804

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1834

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1880

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1902

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

2094

u64 offset;

sys/dev/drm/radeon/r600_cs.c

2139

u64 offset;

sys/dev/drm/radeon/r600_cs.c

2146

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2158

u64 offset;

sys/dev/drm/radeon/r600_cs.c

2165

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2178

u64 offset;

sys/dev/drm/radeon/r600_cs.c

2190

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/drm/radeon/r600_cs.c

2211

u64 offset;

sys/dev/drm/radeon/r600_cs.c

2219

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2235

u64 offset;

sys/dev/drm/radeon/r600_cs.c

2243

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2385

u64 src_offset, dst_offset;

sys/dev/drm/radeon/r600_cs.c

2415

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2448

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2454

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2466

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2468

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2477

src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2479

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;

sys/dev/drm/radeon/r600_cs.c

2510

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/drm/radeon/r600_cs.c

253

u64 *base_align)

sys/dev/drm/radeon/r600_cs.c

355

u64 base_offset, base_align;

sys/dev/drm/radeon/r600_cs.c

50

u64 cb_color_bo_mc[8];

sys/dev/drm/radeon/r600_cs.c

51

u64 cb_color_bo_offset[8];

sys/dev/drm/radeon/r600_cs.c

524

u64 base_offset, base_align;

sys/dev/drm/radeon/r600_cs.c

53

u64 cb_color_frag_offset[8];

sys/dev/drm/radeon/r600_cs.c

55

u64 cb_color_tile_offset[8];

sys/dev/drm/radeon/r600_cs.c

67

u64 vgt_strmout_bo_mc[4]; /* unused */

sys/dev/drm/radeon/r600_cs.c

721

u64 offset = (u64)track->vgt_strmout_bo_offset[i] +

sys/dev/drm/radeon/r600_cs.c

722

(u64)track->vgt_strmout_size[i];

sys/dev/drm/radeon/r600_cs.c

77

u64 db_bo_mc;

sys/dev/drm/radeon/r600_cs.c

83

u64 htile_offset;

sys/dev/drm/radeon/r600_dma.c

235

u64 gpu_addr;

sys/dev/drm/radeon/r600_dma.c

289

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/r600_dma.c

316

u64 addr = semaphore->gpu_addr;

sys/dev/drm/radeon/r600_dma.c

342

u64 gpu_addr;

sys/dev/drm/radeon/r600_dpm.c

523

u64 mask)

sys/dev/drm/radeon/r600_dpm.c

531

enum r600_power_level index, u64 pins)

sys/dev/drm/radeon/r600_dpm.c

545

u64 mask)

sys/dev/drm/radeon/r600_dpm.h

190

u64 mask);

sys/dev/drm/radeon/r600_dpm.h

192

enum r600_power_level index, u64 pins);

sys/dev/drm/radeon/r600_dpm.h

194

u64 mask);

sys/dev/drm/radeon/radeon.h

1003

u64 clear_state_gpu_addr;

sys/dev/drm/radeon/radeon.h

1009

u64 cp_table_gpu_addr;

sys/dev/drm/radeon/radeon.h

1683

u64 gpu_addr;

sys/dev/drm/radeon/radeon.h

1724

u64 gpu_addr;

sys/dev/drm/radeon/radeon.h

2004

void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);

sys/dev/drm/radeon/radeon.h

2258

u64 gpu_addr;

sys/dev/drm/radeon/radeon.h

2385

u64 fence_context;

sys/dev/drm/radeon/radeon.h

2468

u64 vram_pin_size;

sys/dev/drm/radeon/radeon.h

2469

u64 gart_pin_size;

sys/dev/drm/radeon/radeon.h

2838

extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);

sys/dev/drm/radeon/radeon.h

2843

extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);

sys/dev/drm/radeon/radeon.h

557

u64 gpu_addr;

sys/dev/drm/radeon/radeon.h

691

u64 mc_vram_size;

sys/dev/drm/radeon/radeon.h

692

u64 visible_vram_size;

sys/dev/drm/radeon/radeon.h

693

u64 gtt_size;

sys/dev/drm/radeon/radeon.h

694

u64 gtt_start;

sys/dev/drm/radeon/radeon.h

695

u64 gtt_end;

sys/dev/drm/radeon/radeon.h

696

u64 vram_start;

sys/dev/drm/radeon/radeon.h

697

u64 vram_end;

sys/dev/drm/radeon/radeon.h

699

u64 real_vram_size;

sys/dev/drm/radeon/radeon.h

703

u64 gtt_base_align;

sys/dev/drm/radeon/radeon.h

704

u64 mc_mask;

sys/dev/drm/radeon/radeon.h

847

u64 next_rptr_gpu_addr;

sys/dev/drm/radeon/radeon.h

862

u64 last_semaphore_signal_addr;

sys/dev/drm/radeon/radeon.h

863

u64 last_semaphore_wait_addr;

sys/dev/drm/radeon/radeon.h

875

u64 hpd_eop_gpu_addr;

sys/dev/drm/radeon/radeon.h

961

u64 vram_base_offset;

sys/dev/drm/radeon/radeon.h

997

u64 save_restore_gpu_addr;

sys/dev/drm/radeon/radeon_asic.h

141

u64 crtc_base, bool async);

sys/dev/drm/radeon/radeon_asic.h

252

u64 crtc_base, bool async);

sys/dev/drm/radeon/radeon_asic.h

469

void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,

sys/dev/drm/radeon/radeon_asic.h

539

u64 crtc_base, bool async);

sys/dev/drm/radeon/radeon_benchmark.c

104

r = radeon_bo_pin(sobj, sdomain, (u64 *)&saddr);

sys/dev/drm/radeon/radeon_benchmark.c

116

r = radeon_bo_pin(dobj, ddomain, (u64 *)&daddr);

sys/dev/drm/radeon/radeon_cs.c

875

(u64)relocs_chunk->kdata[idx + 3] << 32;

sys/dev/drm/radeon/radeon_cursor.c

316

(u64 *)&radeon_crtc->cursor_addr);

sys/dev/drm/radeon/radeon_device.c

1779

(u64 *)&radeon_crtc->cursor_addr);

sys/dev/drm/radeon/radeon_device.c

470

(u64 *)&rdev->wb.gpu_addr);

sys/dev/drm/radeon/radeon_device.c

561

void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)

sys/dev/drm/radeon/radeon_device.c

599

u64 size_af, size_bf;

sys/dev/drm/radeon/radeon_display.c

525

ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base);

sys/dev/drm/radeon/radeon_fence.c

132

u64 seq;

sys/dev/drm/radeon/radeon_fence.c

163

u64 seq;

sys/dev/drm/radeon/radeon_fence.c

342

u64 seq, unsigned ring)

sys/dev/drm/radeon/radeon_fence.c

360

u64 seq = fence->seq;

sys/dev/drm/radeon/radeon_fence.c

459

static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)

sys/dev/drm/radeon/radeon_fence.c

488

u64 *target_seq, bool intr,

sys/dev/drm/radeon/radeon_fence.c

545

u64 seq[RADEON_NUM_RINGS] = {};

sys/dev/drm/radeon/radeon_fence.c

608

u64 seq[RADEON_NUM_RINGS];

sys/dev/drm/radeon/radeon_fence.c

646

u64 seq[RADEON_NUM_RINGS] = {};

sys/dev/drm/radeon/radeon_fence.c

673

u64 seq[RADEON_NUM_RINGS] = {};

sys/dev/drm/radeon/radeon_gart.c

154

u64 gpu_addr;

sys/dev/drm/radeon/radeon_gem.c

230

args->vram_size = (u64)man->size << PAGE_SHIFT;

sys/dev/drm/radeon/radeon_legacy_crtc.c

429

(u64 *)&base);

sys/dev/drm/radeon/radeon_object.c

324

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,

sys/dev/drm/radeon/radeon_object.c

325

u64 *gpu_addr)

sys/dev/drm/radeon/radeon_object.c

339

u64 domain_start;

sys/dev/drm/radeon/radeon_object.c

385

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)

sys/dev/drm/radeon/radeon_object.c

479

static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)

sys/dev/drm/radeon/radeon_object.c

481

u64 real_vram_size = rdev->mc.real_vram_size;

sys/dev/drm/radeon/radeon_object.c

482

u64 vram_usage = atomic64_read(&rdev->vram_usage);

sys/dev/drm/radeon/radeon_object.c

51

u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;

sys/dev/drm/radeon/radeon_object.c

523

u64 half_vram = real_vram_size >> 1;

sys/dev/drm/radeon/radeon_object.c

524

u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;

sys/dev/drm/radeon/radeon_object.c

525

u64 bytes_moved_threshold = half_free_vram >> 1;

sys/dev/drm/radeon/radeon_object.c

537

u64 bytes_moved = 0, initial_bytes_moved;

sys/dev/drm/radeon/radeon_object.c

538

u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);

sys/dev/drm/radeon/radeon_object.h

117

static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)

sys/dev/drm/radeon/radeon_object.h

135

extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);

sys/dev/drm/radeon/radeon_object.h

137

u64 max_offset, u64 *gpu_addr);

sys/dev/drm/radeon/radeon_object.h

91

static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)

sys/dev/drm/radeon/radeon_ring.c

396

(u64 *)&ring->gpu_addr);

sys/dev/drm/radeon/radeon_test.c

38

u64 gtt_addr, vram_addr;

sys/dev/drm/radeon/radeon_ttm.c

269

old_start = (u64)old_mem->start << PAGE_SHIFT;

sys/dev/drm/radeon/radeon_ttm.c

270

new_start = (u64)new_mem->start << PAGE_SHIFT;

sys/dev/drm/radeon/radeon_ttm.c

457

atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);

sys/dev/drm/radeon/radeon_ttm.c

536

u64 offset;

sys/dev/drm/radeon/radeon_ttm.c

983

void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)

sys/dev/drm/radeon/rs400.c

263

u64 base;

sys/dev/drm/radeon/rs600.c

112

void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/radeon/rs600.c

869

u64 base;

sys/dev/drm/radeon/rs690.c

150

u64 base;

sys/dev/drm/radeon/rv6xx_dpm.c

938

static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)

sys/dev/drm/radeon/rv6xx_dpm.c

941

u64 master_mask = 0;

sys/dev/drm/radeon/rv730_dpm.c

51

u64 tmp;

sys/dev/drm/radeon/rv730_dpm.c

70

tmp = (u64) engine_clock * reference_divider * post_divider * 16384;

sys/dev/drm/radeon/rv740_dpm.c

131

u64 tmp;

sys/dev/drm/radeon/rv740_dpm.c

144

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/drm/radeon/rv770.c

1601

u64 size_bf, size_af;

sys/dev/drm/radeon/rv770.c

801

void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)

sys/dev/drm/radeon/rv770_dpm.c

504

u64 tmp;

sys/dev/drm/radeon/rv770_dpm.c

522

tmp = (u64) engine_clock * reference_divider * post_divider * 16384;

sys/dev/drm/radeon/si.c

2221

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/drm/radeon/si.c

2301

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/radeon/si.c

2303

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/radeon/si.c

3364

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/drm/radeon/si_dpm.c

2257

u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;

sys/dev/drm/radeon/si_dpm.c

2258

u64 prev_vddc = (u64)prev_std_vddc;

sys/dev/drm/radeon/si_dpm.c

2259

u64 curr_vddc = (u64)curr_std_vddc;

sys/dev/drm/radeon/si_dpm.c

2260

u64 pwr_efficiency_ratio, n, d;

sys/dev/drm/radeon/si_dpm.c

2265

n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);

sys/dev/drm/radeon/si_dpm.c

2269

if (pwr_efficiency_ratio > (u64)0xFFFF)

sys/dev/drm/radeon/si_dpm.c

4797

u64 tmp;

sys/dev/drm/radeon/si_dpm.c

4810

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/drm/radeon/si_dpm.c

6039

u64 tmp64;

sys/dev/drm/radeon/si_dpm.c

6053

tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;

sys/dev/drm/radeon/si_dpm.c

6140

u64 tmp64;

sys/dev/drm/radeon/si_dpm.c

6151

tmp64 = (u64)duty * 100;

sys/dev/drm/radeon/si_dpm.c

6167

u64 tmp64;

sys/dev/drm/radeon/si_dpm.c

6183

tmp64 = (u64)speed * duty100;

sys/dev/drm/radeon/trinity_dpm.c

1643

u64 disp_clk = rdev->clock.default_dispclk / 100;

sys/dev/drm/radeon/trinity_dpm.c

1649

dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>

sys/dev/netif/ig_hal/e1000_82575.h

110

u64 l4_config;

sys/dev/netif/ig_hal/e1000_hw.h

408

#define __le64 u64

sys/dev/netif/ig_hal/e1000_hw.h

553

u64 crcerrs;

sys/dev/netif/ig_hal/e1000_hw.h

554

u64 algnerrc;

sys/dev/netif/ig_hal/e1000_hw.h

555

u64 symerrs;

sys/dev/netif/ig_hal/e1000_hw.h

556

u64 rxerrc;

sys/dev/netif/ig_hal/e1000_hw.h

557

u64 mpc;

sys/dev/netif/ig_hal/e1000_hw.h

558

u64 scc;

sys/dev/netif/ig_hal/e1000_hw.h

559

u64 ecol;

sys/dev/netif/ig_hal/e1000_hw.h

560

u64 mcc;

sys/dev/netif/ig_hal/e1000_hw.h

561

u64 latecol;

sys/dev/netif/ig_hal/e1000_hw.h

562

u64 colc;

sys/dev/netif/ig_hal/e1000_hw.h

563

u64 dc;

sys/dev/netif/ig_hal/e1000_hw.h

564

u64 tncrs;

sys/dev/netif/ig_hal/e1000_hw.h

565

u64 sec;

sys/dev/netif/ig_hal/e1000_hw.h

566

u64 cexterr;

sys/dev/netif/ig_hal/e1000_hw.h

567

u64 rlec;

sys/dev/netif/ig_hal/e1000_hw.h

568

u64 xonrxc;

sys/dev/netif/ig_hal/e1000_hw.h

569

u64 xontxc;

sys/dev/netif/ig_hal/e1000_hw.h

570

u64 xoffrxc;

sys/dev/netif/ig_hal/e1000_hw.h

571

u64 xofftxc;

sys/dev/netif/ig_hal/e1000_hw.h

572

u64 fcruc;

sys/dev/netif/ig_hal/e1000_hw.h

573

u64 prc64;

sys/dev/netif/ig_hal/e1000_hw.h

574

u64 prc127;

sys/dev/netif/ig_hal/e1000_hw.h

575

u64 prc255;

sys/dev/netif/ig_hal/e1000_hw.h

576

u64 prc511;

sys/dev/netif/ig_hal/e1000_hw.h

577

u64 prc1023;

sys/dev/netif/ig_hal/e1000_hw.h

578

u64 prc1522;

sys/dev/netif/ig_hal/e1000_hw.h

579

u64 gprc;

sys/dev/netif/ig_hal/e1000_hw.h

580

u64 bprc;

sys/dev/netif/ig_hal/e1000_hw.h

581

u64 mprc;

sys/dev/netif/ig_hal/e1000_hw.h

582

u64 gptc;

sys/dev/netif/ig_hal/e1000_hw.h

583

u64 gorc;

sys/dev/netif/ig_hal/e1000_hw.h

584

u64 gotc;

sys/dev/netif/ig_hal/e1000_hw.h

585

u64 rnbc;

sys/dev/netif/ig_hal/e1000_hw.h

586

u64 ruc;

sys/dev/netif/ig_hal/e1000_hw.h

587

u64 rfc;

sys/dev/netif/ig_hal/e1000_hw.h

588

u64 roc;

sys/dev/netif/ig_hal/e1000_hw.h

589

u64 rjc;

sys/dev/netif/ig_hal/e1000_hw.h

590

u64 mgprc;

sys/dev/netif/ig_hal/e1000_hw.h

591

u64 mgpdc;

sys/dev/netif/ig_hal/e1000_hw.h

592

u64 mgptc;

sys/dev/netif/ig_hal/e1000_hw.h

593

u64 tor;

sys/dev/netif/ig_hal/e1000_hw.h

594

u64 tot;

sys/dev/netif/ig_hal/e1000_hw.h

595

u64 tpr;

sys/dev/netif/ig_hal/e1000_hw.h

596

u64 tpt;

sys/dev/netif/ig_hal/e1000_hw.h

597

u64 ptc64;

sys/dev/netif/ig_hal/e1000_hw.h

598

u64 ptc127;

sys/dev/netif/ig_hal/e1000_hw.h

599

u64 ptc255;

sys/dev/netif/ig_hal/e1000_hw.h

600

u64 ptc511;

sys/dev/netif/ig_hal/e1000_hw.h

601

u64 ptc1023;

sys/dev/netif/ig_hal/e1000_hw.h

602

u64 ptc1522;

sys/dev/netif/ig_hal/e1000_hw.h

603

u64 mptc;

sys/dev/netif/ig_hal/e1000_hw.h

604

u64 bptc;

sys/dev/netif/ig_hal/e1000_hw.h

605

u64 tsctc;

sys/dev/netif/ig_hal/e1000_hw.h

606

u64 tsctfc;

sys/dev/netif/ig_hal/e1000_hw.h

607

u64 iac;

sys/dev/netif/ig_hal/e1000_hw.h

608

u64 icrxptc;

sys/dev/netif/ig_hal/e1000_hw.h

609

u64 icrxatc;

sys/dev/netif/ig_hal/e1000_hw.h

610

u64 ictxptc;

sys/dev/netif/ig_hal/e1000_hw.h

611

u64 ictxatc;

sys/dev/netif/ig_hal/e1000_hw.h

612

u64 ictxqec;

sys/dev/netif/ig_hal/e1000_hw.h

613

u64 ictxqmtc;

sys/dev/netif/ig_hal/e1000_hw.h

614

u64 icrxdmtc;

sys/dev/netif/ig_hal/e1000_hw.h

615

u64 icrxoc;

sys/dev/netif/ig_hal/e1000_hw.h

616

u64 cbtmpc;

sys/dev/netif/ig_hal/e1000_hw.h

617

u64 htdpmc;

sys/dev/netif/ig_hal/e1000_hw.h

618

u64 cbrdpc;

sys/dev/netif/ig_hal/e1000_hw.h

619

u64 cbrmpc;

sys/dev/netif/ig_hal/e1000_hw.h

620

u64 rpthc;

sys/dev/netif/ig_hal/e1000_hw.h

621

u64 hgptc;

sys/dev/netif/ig_hal/e1000_hw.h

622

u64 htcbdpc;

sys/dev/netif/ig_hal/e1000_hw.h

623

u64 hgorc;

sys/dev/netif/ig_hal/e1000_hw.h

624

u64 hgotc;

sys/dev/netif/ig_hal/e1000_hw.h

625

u64 lenerrs;

sys/dev/netif/ig_hal/e1000_hw.h

626

u64 scvpc;

sys/dev/netif/ig_hal/e1000_hw.h

627

u64 hrmpc;

sys/dev/netif/ig_hal/e1000_hw.h

628

u64 doosync;

sys/dev/netif/ig_hal/e1000_hw.h

629

u64 o2bgptc;

sys/dev/netif/ig_hal/e1000_hw.h

630

u64 o2bspc;

sys/dev/netif/ig_hal/e1000_hw.h

631

u64 b2ospc;

sys/dev/netif/ig_hal/e1000_hw.h

632

u64 b2ogprc;

sys/dev/netif/ig_hal/e1000_hw.h

636

u64 base_gprc;

sys/dev/netif/ig_hal/e1000_hw.h

637

u64 base_gptc;

sys/dev/netif/ig_hal/e1000_hw.h

638

u64 base_gorc;

sys/dev/netif/ig_hal/e1000_hw.h

639

u64 base_gotc;

sys/dev/netif/ig_hal/e1000_hw.h

640

u64 base_mprc;

sys/dev/netif/ig_hal/e1000_hw.h

641

u64 base_gotlbc;

sys/dev/netif/ig_hal/e1000_hw.h

642

u64 base_gptlbc;

sys/dev/netif/ig_hal/e1000_hw.h

643

u64 base_gorlbc;

sys/dev/netif/ig_hal/e1000_hw.h

644

u64 base_gprlbc;

sys/dev/netif/ig_hal/e1000_hw.h

656

u64 gprc;

sys/dev/netif/ig_hal/e1000_hw.h

657

u64 gptc;

sys/dev/netif/ig_hal/e1000_hw.h

658

u64 gorc;

sys/dev/netif/ig_hal/e1000_hw.h

659

u64 gotc;

sys/dev/netif/ig_hal/e1000_hw.h

660

u64 mprc;

sys/dev/netif/ig_hal/e1000_hw.h

661

u64 gotlbc;

sys/dev/netif/ig_hal/e1000_hw.h

662

u64 gptlbc;

sys/dev/netif/ig_hal/e1000_hw.h

663

u64 gorlbc;

sys/dev/netif/ig_hal/e1000_hw.h

664

u64 gprlbc;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1085

static u64 e1000_ltr2ns(u16 ltr)

sys/dev/netif/ig_hal/e1000_osdep.h

81

#define __le64 u64

sys/dev/netif/ig_hal/e1000_vf.h

122

u64 buffer_addr; /* Address of descriptor's data buf */

sys/dev/netif/ig_hal/e1000_vf.h

127

u64 rsvd; /* Reserved */

sys/dev/netif/ig_hal/e1000_vf.h

166

u64 base_gprc;

sys/dev/netif/ig_hal/e1000_vf.h

167

u64 base_gptc;

sys/dev/netif/ig_hal/e1000_vf.h

168

u64 base_gorc;

sys/dev/netif/ig_hal/e1000_vf.h

169

u64 base_gotc;

sys/dev/netif/ig_hal/e1000_vf.h

170

u64 base_mprc;

sys/dev/netif/ig_hal/e1000_vf.h

171

u64 base_gotlbc;

sys/dev/netif/ig_hal/e1000_vf.h

172

u64 base_gptlbc;

sys/dev/netif/ig_hal/e1000_vf.h

173

u64 base_gorlbc;

sys/dev/netif/ig_hal/e1000_vf.h

174

u64 base_gprlbc;

sys/dev/netif/ig_hal/e1000_vf.h

186

u64 gprc;

sys/dev/netif/ig_hal/e1000_vf.h

187

u64 gptc;

sys/dev/netif/ig_hal/e1000_vf.h

188

u64 gorc;

sys/dev/netif/ig_hal/e1000_vf.h

189

u64 gotc;

sys/dev/netif/ig_hal/e1000_vf.h

190

u64 mprc;

sys/dev/netif/ig_hal/e1000_vf.h

191

u64 gotlbc;

sys/dev/netif/ig_hal/e1000_vf.h

192

u64 gptlbc;

sys/dev/netif/ig_hal/e1000_vf.h

193

u64 gorlbc;

sys/dev/netif/ig_hal/e1000_vf.h

194

u64 gprlbc;

sys/dev/netif/ig_hal/e1000_vf.h

86

u64 pkt_addr; /* Packet buffer address */

sys/dev/netif/ig_hal/e1000_vf.h

87

u64 hdr_addr; /* Header buffer address */

sys/dev/netif/ix/ixgbe_82598.c

1227

u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_82598.c

1229

u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

sys/dev/netif/ix/ixgbe_82598.h

49

u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_82599.c

1544

u64 fdirhashcmd;

sys/dev/netif/ix/ixgbe_82599.c

1584

fdirhashcmd = (u64)fdircmd << 32;

sys/dev/netif/ix/ixgbe_82599.c

2187

u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_82599.c

2189

u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

sys/dev/netif/ix/ixgbe_82599.h

61

u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_api.c

1621

u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_api.h

144

u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_dcb_82599.c

66

(((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);

sys/dev/netif/ix/ixgbe_dcb_82599.c

72

(((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);

sys/dev/netif/ix/ixgbe_osdep.h

131

#define __le64 u64

sys/dev/netif/ix/ixgbe_osdep.h

134

#define __be64 u64

sys/dev/netif/ix/ixgbe_phy.c

1582

u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_phy.c

1584

u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

sys/dev/netif/ix/ixgbe_phy.h

196

u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_type.h

2928

#define __le64 u64

sys/dev/netif/ix/ixgbe_type.h

2935

#define __be64 u64

sys/dev/netif/ix/ixgbe_type.h

3247

u64 buffer_addr; /* Address of the descriptor's data buffer */

sys/dev/netif/ix/ixgbe_type.h

3412

typedef u64 ixgbe_physical_layer;

sys/dev/netif/ix/ixgbe_type.h

3800

u64 crcerrs;

sys/dev/netif/ix/ixgbe_type.h

3801

u64 illerrc;

sys/dev/netif/ix/ixgbe_type.h

3802

u64 errbc;

sys/dev/netif/ix/ixgbe_type.h

3803

u64 mspdc;

sys/dev/netif/ix/ixgbe_type.h

3804

u64 mpctotal;

sys/dev/netif/ix/ixgbe_type.h

3805

u64 mpc[8];

sys/dev/netif/ix/ixgbe_type.h

3806

u64 mlfc;

sys/dev/netif/ix/ixgbe_type.h

3807

u64 mrfc;

sys/dev/netif/ix/ixgbe_type.h

3808

u64 rlec;

sys/dev/netif/ix/ixgbe_type.h

3809

u64 lxontxc;

sys/dev/netif/ix/ixgbe_type.h

3810

u64 lxonrxc;

sys/dev/netif/ix/ixgbe_type.h

3811

u64 lxofftxc;

sys/dev/netif/ix/ixgbe_type.h

3812

u64 lxoffrxc;

sys/dev/netif/ix/ixgbe_type.h

3813

u64 pxontxc[8];

sys/dev/netif/ix/ixgbe_type.h

3814

u64 pxonrxc[8];

sys/dev/netif/ix/ixgbe_type.h

3815

u64 pxofftxc[8];

sys/dev/netif/ix/ixgbe_type.h

3816

u64 pxoffrxc[8];

sys/dev/netif/ix/ixgbe_type.h

3817

u64 prc64;

sys/dev/netif/ix/ixgbe_type.h

3818

u64 prc127;

sys/dev/netif/ix/ixgbe_type.h

3819

u64 prc255;

sys/dev/netif/ix/ixgbe_type.h

3820

u64 prc511;

sys/dev/netif/ix/ixgbe_type.h

3821

u64 prc1023;

sys/dev/netif/ix/ixgbe_type.h

3822

u64 prc1522;

sys/dev/netif/ix/ixgbe_type.h

3823

u64 gprc;

sys/dev/netif/ix/ixgbe_type.h

3824

u64 bprc;

sys/dev/netif/ix/ixgbe_type.h

3825

u64 mprc;

sys/dev/netif/ix/ixgbe_type.h

3826

u64 gptc;

sys/dev/netif/ix/ixgbe_type.h

3827

u64 gorc;

sys/dev/netif/ix/ixgbe_type.h

3828

u64 gotc;

sys/dev/netif/ix/ixgbe_type.h

3829

u64 rnbc[8];

sys/dev/netif/ix/ixgbe_type.h

3830

u64 ruc;

sys/dev/netif/ix/ixgbe_type.h

3831

u64 rfc;

sys/dev/netif/ix/ixgbe_type.h

3832

u64 roc;

sys/dev/netif/ix/ixgbe_type.h

3833

u64 rjc;

sys/dev/netif/ix/ixgbe_type.h

3834

u64 mngprc;

sys/dev/netif/ix/ixgbe_type.h

3835

u64 mngpdc;

sys/dev/netif/ix/ixgbe_type.h

3836

u64 mngptc;

sys/dev/netif/ix/ixgbe_type.h

3837

u64 tor;

sys/dev/netif/ix/ixgbe_type.h

3838

u64 tpr;

sys/dev/netif/ix/ixgbe_type.h

3839

u64 tpt;

sys/dev/netif/ix/ixgbe_type.h

3840

u64 ptc64;

sys/dev/netif/ix/ixgbe_type.h

3841

u64 ptc127;

sys/dev/netif/ix/ixgbe_type.h

3842

u64 ptc255;

sys/dev/netif/ix/ixgbe_type.h

3843

u64 ptc511;

sys/dev/netif/ix/ixgbe_type.h

3844

u64 ptc1023;

sys/dev/netif/ix/ixgbe_type.h

3845

u64 ptc1522;

sys/dev/netif/ix/ixgbe_type.h

3846

u64 mptc;

sys/dev/netif/ix/ixgbe_type.h

3847

u64 bptc;

sys/dev/netif/ix/ixgbe_type.h

3848

u64 xec;

sys/dev/netif/ix/ixgbe_type.h

3849

u64 qprc[16];

sys/dev/netif/ix/ixgbe_type.h

3850

u64 qptc[16];

sys/dev/netif/ix/ixgbe_type.h

3851

u64 qbrc[16];

sys/dev/netif/ix/ixgbe_type.h

3852

u64 qbtc[16];

sys/dev/netif/ix/ixgbe_type.h

3853

u64 qprdc[16];

sys/dev/netif/ix/ixgbe_type.h

3854

u64 pxon2offc[8];

sys/dev/netif/ix/ixgbe_type.h

3855

u64 fdirustat_add;

sys/dev/netif/ix/ixgbe_type.h

3856

u64 fdirustat_remove;

sys/dev/netif/ix/ixgbe_type.h

3857

u64 fdirfstat_fadd;

sys/dev/netif/ix/ixgbe_type.h

3858

u64 fdirfstat_fremove;

sys/dev/netif/ix/ixgbe_type.h

3859

u64 fdirmatch;

sys/dev/netif/ix/ixgbe_type.h

3860

u64 fdirmiss;

sys/dev/netif/ix/ixgbe_type.h

3861

u64 fccrc;

sys/dev/netif/ix/ixgbe_type.h

3862

u64 fclast;

sys/dev/netif/ix/ixgbe_type.h

3863

u64 fcoerpdc;

sys/dev/netif/ix/ixgbe_type.h

3864

u64 fcoeprc;

sys/dev/netif/ix/ixgbe_type.h

3865

u64 fcoeptc;

sys/dev/netif/ix/ixgbe_type.h

3866

u64 fcoedwrc;

sys/dev/netif/ix/ixgbe_type.h

3867

u64 fcoedwtc;

sys/dev/netif/ix/ixgbe_type.h

3868

u64 fcoe_noddp;

sys/dev/netif/ix/ixgbe_type.h

3869

u64 fcoe_noddp_ext_buff;

sys/dev/netif/ix/ixgbe_type.h

3870

u64 ldpcec;

sys/dev/netif/ix/ixgbe_type.h

3871

u64 pcrc8ec;

sys/dev/netif/ix/ixgbe_type.h

3872

u64 b2ospc;

sys/dev/netif/ix/ixgbe_type.h

3873

u64 b2ogprc;

sys/dev/netif/ix/ixgbe_type.h

3874

u64 o2bgptc;

sys/dev/netif/ix/ixgbe_type.h

3875

u64 o2bspc;

sys/dev/netif/ix/ixgbe_type.h

3904

u64 (*get_supported_physical_layer)(struct ixgbe_hw *);

sys/dev/netif/ix/ixgbe_x540.c

337

u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_x540.c

339

u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

sys/dev/netif/ix/ixgbe_x540.h

47

u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_x550.c

1050

u64 pfflp;

sys/dev/netif/ix/ixgbe_x550.c

1056

pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);

sys/dev/netif/ix/ixgbe_x550.c

1057

pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;

sys/dev/netif/ix/ixgbe_x550.c

3618

u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_x550.c

3620

u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

sys/dev/netif/ix/ixgbe_x550.h

92

u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);

sys/dev/raid/mpr/mpr.c

122

u64 word;

sys/dev/raid/mpr/mpr_config.c

1448

mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle, u64 *wwid)

sys/dev/raid/mpr/mpr_config.c

1456

*wwid = le64toh((u64)raid_vol_pg1.WWID.High << 32 |

sys/dev/raid/mpr/mpr_mapping.c

2218

u64 physical_id;

sys/dev/raid/mpr/mpr_mapping.c

265

_mapping_get_enc_idx_from_id(struct mpr_softc *sc, u64 enc_id,

sys/dev/raid/mpr/mpr_mapping.c

266

u64 phy_bits)

sys/dev/raid/mpr/mpr_mapping.c

2701

mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid, u16 volHandle)

sys/dev/raid/mpr/mpr_mapping.c

2998

u64 *wwid_table;

sys/dev/raid/mpr/mpr_mapping.c

3003

wwid_table = kmalloc(sizeof(u64) * event_data->NumElements, M_MPR,

sys/dev/raid/mpr/mpr_mapping.c

380

_mapping_get_ir_mt_idx_from_wwid(struct mpr_softc *sc, u64 wwid)

sys/dev/raid/mpr/mpr_mapping.c

402

_mapping_get_mt_idx_from_id(struct mpr_softc *sc, u64 dev_id)

sys/dev/raid/mpr/mpr_mapping.c

539

_mapping_get_dpm_idx_from_id(struct mpr_softc *sc, u64 id, u32 phy_bits)

sys/dev/raid/mpr/mpr_mapping.c

573

u64 physical_id;

sys/dev/raid/mpr/mpr_mapping.c

646

Mpi2EventIrConfigElement_t *element, u64 wwid)

sys/dev/raid/mpr/mpr_mapping.c

707

le64toh(((u64)dpm_entry->PhysicalIdentifier.High << 32) |

sys/dev/raid/mpr/mpr_mapping.c

708

(u64)dpm_entry->PhysicalIdentifier.Low)) && (missing_cnt ==

sys/dev/raid/mpr/mpr_mapping.h

120

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD);

sys/dev/raid/mpr/mpr_sas_lsi.c

1033

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD)

sys/dev/raid/mpr/mpr_sas_lsi.c

1114

*sas_address = (u64)hash_address.wwid[0] << 56 |

sys/dev/raid/mpr/mpr_sas_lsi.c

1115

(u64)hash_address.wwid[1] << 48 | (u64)hash_address.wwid[2] << 40 |

sys/dev/raid/mpr/mpr_sas_lsi.c

1116

(u64)hash_address.wwid[3] << 32 | (u64)hash_address.wwid[4] << 24 |

sys/dev/raid/mpr/mpr_sas_lsi.c

1117

(u64)hash_address.wwid[5] << 16 | (u64)hash_address.wwid[6] << 8 |

sys/dev/raid/mpr/mpr_sas_lsi.c

1118

(u64)hash_address.wwid[7];

sys/dev/raid/mpr/mpr_sas_lsi.c

124

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD);

sys/dev/raid/mpr/mpr_sas_lsi.c

1408

u64 wwid;

sys/dev/raid/mpr/mprvar.h

114

u64 physical_id;

sys/dev/raid/mpr/mprvar.h

142

u64 enclosure_id;

sys/dev/raid/mpr/mprvar.h

808

u64 *wwid);

sys/dev/raid/mpr/mprvar.h

833

unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid,

sys/dev/raid/mps/mps_config.c

1256

mps_config_get_volume_wwid(struct mps_softc *sc, u16 volume_handle, u64 *wwid)

sys/dev/raid/mps/mps_config.c

1264

*wwid = le64toh((u64)raid_vol_pg1.WWID.High << 32 |

sys/dev/raid/mps/mps_mapping.c

1471

u64 physical_id;

sys/dev/raid/mps/mps_mapping.c

1860

mps_mapping_get_raid_id(struct mps_softc *sc, u64 wwid, u16 handle)

sys/dev/raid/mps/mps_mapping.c

2092

u64 *wwid_table)

sys/dev/raid/mps/mps_mapping.c

2149

u64 *wwid_table;

sys/dev/raid/mps/mps_mapping.c

2155

wwid_table = kmalloc(sizeof(u64) * event_data->NumElements, M_MPT2,

sys/dev/raid/mps/mps_mapping.c

245

_mapping_get_enc_idx_from_id(struct mps_softc *sc, u64 enc_id,

sys/dev/raid/mps/mps_mapping.c

246

u64 phy_bits)

sys/dev/raid/mps/mps_mapping.c

359

_mapping_get_ir_mt_idx_from_wwid(struct mps_softc *sc, u64 wwid)

sys/dev/raid/mps/mps_mapping.c

381

_mapping_get_mt_idx_from_id(struct mps_softc *sc, u64 dev_id)

sys/dev/raid/mps/mps_mapping.c

506

_mapping_get_dpm_idx_from_id(struct mps_softc *sc, u64 id, u32 phy_bits)

sys/dev/raid/mps/mps_mapping.c

559

Mpi2EventIrConfigElement_t *element, u64 wwid)

sys/dev/raid/mps/mps_mapping.c

603

le64toh((u64)dpm_entry->PhysicalIdentifier.High |

sys/dev/raid/mps/mps_mapping.h

69

u64 *sas_address, u16 handle, u32 device_info);

sys/dev/raid/mps/mps_sas_lsi.c

119

u64 *sas_address, u16 handle, u32 device_info);

sys/dev/raid/mps/mps_sas_lsi.c

686

u64 *sas_address, u16 handle, u32 device_info)

sys/dev/raid/mps/mps_sas_lsi.c

750

*sas_address = (u64)hash_address.wwid[0] << 56 |

sys/dev/raid/mps/mps_sas_lsi.c

751

(u64)hash_address.wwid[1] << 48 | (u64)hash_address.wwid[2] << 40 |

sys/dev/raid/mps/mps_sas_lsi.c

752

(u64)hash_address.wwid[3] << 32 | (u64)hash_address.wwid[4] << 24 |

sys/dev/raid/mps/mps_sas_lsi.c

753

(u64)hash_address.wwid[5] << 16 | (u64)hash_address.wwid[6] << 8 |

sys/dev/raid/mps/mps_sas_lsi.c

754

(u64)hash_address.wwid[7];

sys/dev/raid/mps/mps_sas_lsi.c

824

u64 wwid;

sys/dev/raid/mps/mpsvar.h

136

u64 physical_id;

sys/dev/raid/mps/mpsvar.h

165

u64 enclosure_id;

sys/dev/raid/mps/mpsvar.h

725

u64 *wwid);

sys/dev/raid/mps/mpsvar.h

750

unsigned int mps_mapping_get_raid_id(struct mps_softc *sc, u64 wwid,

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

116

ena_addr->mem_addr_high = (u16)((u64)addr >> 32);

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

70

#define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

71

#define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

382

u64 addr_hi;

sys/vfs/hammer2/xxhash/xxhash.c

168

typedef union { U32 u32; U64 u64; } __attribute__((packed)) unalign;

sys/vfs/hammer2/xxhash/xxhash.c

171

static U64 XXH_read64(const void* ptr) { return ((const unalign*)ptr)->u64; }