IPL_CLOCK
if (ih->ih_level < IPL_CLOCK)
if (ih->ih_level < IPL_CLOCK)
#define splclock() splraise(IPL_CLOCK)
#define splstatclock() splraise(IPL_CLOCK)
if (tc_3000_300_intr[slot].tci_level < IPL_CLOCK) \
if (tc_3000_300_intr[slot].tci_level < IPL_CLOCK) \
if (tc_3000_500_intr[slot].tci_level < IPL_CLOCK) \
if (tc_3000_500_intr[slot].tci_level < IPL_CLOCK) \
KASSERT(level <= IPL_TTY || level >= IPL_CLOCK || flags & IPL_MPSAFE);
fake_timer_intrhand.ih_level = IPL_CLOCK;
#define splclock() splraise(IPL_CLOCK)
#define IPL_SCHED IPL_CLOCK
#define IPL_STATCLOCK IPL_CLOCK
isa_intr_establish(NULL, 0, IST_PULSE, IPL_CLOCK | IPL_MPSAFE,
arm_intr_establish_fdt_idx(sc->sc_node, 0, IPL_CLOCK,
arm_intr_establish_fdt_idx(sc->sc_node, 1, IPL_CLOCK,
ampintc_intr_establish(29, IST_EDGE_RISING, IPL_CLOCK,
IPL_CLOCK|IPL_MPSAFE, agtimer_intr, NULL, "tick");
if (ci->ci_cpl >= IPL_CLOCK) {
s = aplintc_splraise(IPL_CLOCK);
if (sc->sc_fiq_pending[ci->ci_cpuid] && new < IPL_CLOCK) {
KASSERT(level != (IPL_CLOCK | IPL_MPSAFE));
KASSERT(level == (IPL_CLOCK | IPL_MPSAFE));
KASSERT(ih->ih_ipl < IPL_CLOCK);
#define splclock() splraise(IPL_CLOCK)
#define IPL_SCHED IPL_CLOCK
#define IPL_STATCLOCK IPL_CLOCK
#define splclock() splraise(IPL_CLOCK)
#define IPL_SCHED IPL_CLOCK
#define IPL_STATCLOCK IPL_CLOCK
arm_intr_establish(sc->sc_irq, IPL_CLOCK, dmtimer_intr,
arm_intr_establish(gptimer_irq, IPL_CLOCK, gptimer_intr,
arm_intr_establish(sxitimer_irq[TICKTIMER], IPL_CLOCK,
splassert(IPL_CLOCK);
cpu_intr_establish(IPL_CLOCK, 31, itmr_intr, NULL, "clock");
sc->sc_ih = cpu_intr_establish(IPL_CLOCK, ca->ca_irq,
if (pri < IPL_CLOCK)
if (pri < IPL_CLOCK)
#define splclock() splraise(IPL_CLOCK)
#define LAPIC_TIMER_VECTOR IPL_CLOCK
#define splclock() splraise(IPL_CLOCK)
#define IPL_STATCLOCK IPL_CLOCK /* statclock */
#define IPL_SCHED IPL_CLOCK
(void)isa_intr_establish(NULL, 0, IST_PULSE, IPL_CLOCK | IPL_MPSAFE,
KASSERT(level <= IPL_TTY || level >= IPL_CLOCK || flags & IPL_MPSAFE);
#define splclock() splraise(IPL_CLOCK)
if (ci->ci_clock_deferred && newipl < IPL_CLOCK)
bonito_imask[IPL_CLOCK] |= bonito_imask[IPL_VM];
isa_intr_establish(sys_platform->isa_chipset, 7, IST_LEVEL, IPL_CLOCK,
#define IPL_STATCLOCK IPL_CLOCK
#define splclock() splraise(IPL_CLOCK)
if (ci->ci_clock_deferred && newipl < IPL_CLOCK)
imask[IPL_CLOCK] |= imask[IPL_VM];
imask[IPL_HIGH] |= imask[IPL_CLOCK];
if (ci->ci_clock_deferred && newipl < IPL_CLOCK)
if (isr->isr_ipl < IPL_CLOCK)
if (isr->isr_ipl < IPL_CLOCK)
#define splclock() splraise(IPL_CLOCK)
if (ci->ci_dec_deferred && newcpl < IPL_CLOCK) {
KASSERT(level <= IPL_TTY || level >= IPL_CLOCK || flags & IPL_MPSAFE);
if (ci->ci_dec_deferred && newcpl < IPL_CLOCK) {
KASSERT(level <= IPL_TTY || level >= IPL_CLOCK || flags & IPL_MPSAFE);
if (ci->ci_cpl >= IPL_CLOCK) {
if (tf->ipl >= IPL_CLOCK) {
if (ci->ci_clock_deferred && newipl < IPL_CLOCK)
ADD_MASK(scpu->scpu_imask[IPL_CLOCK], scpu->scpu_imask[IPL_VM]);
ADD_MASK(scpu->scpu_imask[IPL_HIGH], scpu->scpu_imask[IPL_CLOCK]);
if (ci->ci_clock_deferred && newipl < IPL_CLOCK)
#define IPL_SCHED IPL_CLOCK
#define splclock() splraise(IPL_CLOCK)
#define splclock() splraise(IPL_CLOCK)
if (ci->ci_dec_deferred && newcpl < IPL_CLOCK) {
#define IPL_STATCLOCK IPL_CLOCK
#define IPL_SCHED IPL_CLOCK
#define IPL_HIGH IPL_CLOCK
#define splclock() splraise(IPL_CLOCK)
if (ci->ci_cpl >= IPL_CLOCK) {
if (ci->ci_dec_deferred && new < IPL_CLOCK) {
if (ci->ci_timer_deferred && new < IPL_CLOCK)
sc->sc_ih = fdt_intr_establish_idx(faa->fa_node, 0, IPL_CLOCK,
#define splclock() splraise(IPL_CLOCK)
#define IPL_SCHED IPL_CLOCK
#define IPL_STATCLOCK IPL_CLOCK
if (ci->ci_cpl >= IPL_CLOCK) {
intc_intr_establish(SH_INTEVT_TMU0_TUNI0, IST_LEVEL, IPL_CLOCK,
#define splclock() _splraise(IPL_CLOCK)
sc->sc_ih = fdt_intr_establish_idx(node, 0, IPL_CLOCK,
splassert(IPL_CLOCK);
mtx_init(&cq->cq_mtx, IPL_CLOCK);
struct mutex windup_mtx = MUTEX_INITIALIZER(IPL_CLOCK);
struct mutex itimer_mtx = MUTEX_INITIALIZER(IPL_CLOCK);