DIV_ROUND_UP - OpenBSD

Symbol: DIV_ROUND_UP

sys/dev/fdt/rkdrm.c

bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

block_size * DIV_ROUND_UP(height, block_height);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

DIV_ROUND_UP(db_size, 4);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

DIV_ROUND_UP(args->bpp, 8), 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

tmp = DIV_ROUND_UP(nom_min, *nom);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

tmp = DIV_ROUND_UP(den_min, *den);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

num_loops = DIV_ROUND_UP(byte_count, max_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

slot_num = DIV_ROUND_UP(pbn, pbn_div);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

value = DIV_ROUND_UP(value * 100, golden_value);

sys/dev/pci/drm/apple/apple_drv.c

args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), 64);

sys/dev/pci/drm/clients/drm_log.c

size_t font_pitch = DIV_ROUND_UP(font->width, 8);

sys/dev/pci/drm/display/drm_dp_helper.c

return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +

sys/dev/pci/drm/display/drm_dp_helper.c

return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);

sys/dev/pci/drm/display/drm_dp_helper.c

int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);

sys/dev/pci/drm/display/drm_dp_helper.c

int slice_pixels = DIV_ROUND_UP(pixels, slice_count);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

req_slots = DIV_ROUND_UP(dfixed_const(pbn), topology_state->pbn_div.full);

sys/dev/pci/drm/display/drm_dp_tunnel.c

int request_bw = DIV_ROUND_UP(bw, tunnel->bw_granularity);

sys/dev/pci/drm/display/drm_dp_tunnel.c

DIV_ROUND_UP((__kbytes) * 8, 1000)

sys/dev/pci/drm/display/drm_dsc_helper.c

groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,

sys/dev/pci/drm/display/drm_dsc_helper.c

vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *

sys/dev/pci/drm/display/drm_dsc_helper.c

groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,

sys/dev/pci/drm/display/drm_dsc_helper.c

vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *

sys/dev/pci/drm/display/drm_dsc_helper.c

vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),

sys/dev/pci/drm/display/drm_dsc_helper.c

vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -

sys/dev/pci/drm/display/drm_dsc_helper.c

DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *

sys/dev/pci/drm/display/drm_dsc_helper.c

hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);

sys/dev/pci/drm/drm_dumb_buffers.c

cpp = DIV_ROUND_UP(args->bpp, 8);

sys/dev/pci/drm/drm_edid.c

DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);

sys/dev/pci/drm/drm_fb_helper.c

u32 y2 = DIV_ROUND_UP(end, line_length);

sys/dev/pci/drm/drm_fb_helper.c

x2 = DIV_ROUND_UP(bit_end, info->var.bits_per_pixel);

sys/dev/pci/drm/drm_fbdev_dma.c

len = DIV_ROUND_UP(len + clip->x1 % 8, 8);

sys/dev/pci/drm/drm_fbdev_dma.c

len = DIV_ROUND_UP(len + clip->x1 % 4, 4);

sys/dev/pci/drm/drm_fbdev_dma.c

len = DIV_ROUND_UP(len + clip->x1 % 2, 2);

sys/dev/pci/drm/drm_fbdev_ttm.c

len = DIV_ROUND_UP(len + clip->x1 % 8, 8);

sys/dev/pci/drm/drm_fbdev_ttm.c

len = DIV_ROUND_UP(len + clip->x1 % 4, 4);

sys/dev/pci/drm/drm_fbdev_ttm.c

len = DIV_ROUND_UP(len + clip->x1 % 2, 2);

sys/dev/pci/drm/drm_format_helper.c

dst_pitch_0 = DIV_ROUND_UP(linepixels, 8);

sys/dev/pci/drm/drm_format_helper.c

dst_pitch_0 = DIV_ROUND_UP(linepixels, 4);

sys/dev/pci/drm/drm_format_helper.c

unsigned int cpp_i = DIV_ROUND_UP(bpp_i, 8);

sys/dev/pci/drm/drm_format_helper.c

size_t len_i = DIV_ROUND_UP(drm_rect_width(clip) * bpp_i, 8);

sys/dev/pci/drm/drm_format_helper.c

u8 cpp = DIV_ROUND_UP(drm_format_info_bpp(format, 0), 8);

sys/dev/pci/drm/drm_modes.c

hslen = DIV_ROUND_UP(params->hslen_ns.typ, pixel_duration_ns);

sys/dev/pci/drm/drm_modes.c

unsigned int hfp_min = DIV_ROUND_UP(params->hfp_ns.min,

sys/dev/pci/drm/drm_modes.c

unsigned int hbp_min = DIV_ROUND_UP(params->hbp_ns.min,

sys/dev/pci/drm/drm_modes.c

hfp = hfp_min + DIV_ROUND_UP(porches_rem, 2);

sys/dev/pci/drm/drm_panic.c

size_mul(DIV_ROUND_UP(logo->width, BITS_PER_BYTE), logo->height),

sys/dev/pci/drm/drm_panic.c

size_t font_pitch = DIV_ROUND_UP(font->width, 8);

sys/dev/pci/drm/drm_panic.c

DIV_ROUND_UP(drm_rect_width(rect), 8), 1, fg_color);

sys/dev/pci/drm/drm_panic.c

qr_pitch = DIV_ROUND_UP(qr_width, 8);

sys/dev/pci/drm/drm_rect.c

return DIV_ROUND_UP(src, dst);

sys/dev/pci/drm/i915/display/hsw_ips.c

return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);

sys/dev/pci/drm/i915/display/i9xx_plane.c

return DIV_ROUND_UP(pixel_rate * num, den);

sys/dev/pci/drm/i915/display/i9xx_wm.c

wm = DIV_ROUND_UP(wm, 64) + 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

ret = DIV_ROUND_UP(ret, 64);

sys/dev/pci/drm/i915/display/i9xx_wm.c

fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);

sys/dev/pci/drm/i915/display/i9xx_wm.c

entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);

sys/dev/pci/drm/i915/display/i9xx_wm.c

entries = DIV_ROUND_UP(entries,

sys/dev/pci/drm/i915/display/i9xx_wm.c

entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);

sys/dev/pci/drm/i915/display/i9xx_wm.c

ret = DIV_ROUND_UP(ret, 64) + 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

ret = DIV_ROUND_UP(ret, 64) + 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));

sys/dev/pci/drm/i915/display/i9xx_wm.c

entries = DIV_ROUND_UP(entries, wm->cacheline_size) +

sys/dev/pci/drm/i915/display/icl_dsi.c

hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,

sys/dev/pci/drm/i915/display/icl_dsi.c

lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);

sys/dev/pci/drm/i915/display/icl_dsi.c

ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);

sys/dev/pci/drm/i915/display/icl_dsi.c

DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns);

sys/dev/pci/drm/i915/display/icl_dsi.c

tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -

sys/dev/pci/drm/i915/display/icl_dsi.c

tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);

sys/dev/pci/drm/i915/display/icl_dsi.c

ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns);

sys/dev/pci/drm/i915/display/icl_dsi.c

ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -

sys/dev/pci/drm/i915/display/icl_dsi.c

ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);

sys/dev/pci/drm/i915/display/icl_dsi.c

theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);

sys/dev/pci/drm/i915/display/icl_dsi.c

esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);

sys/dev/pci/drm/i915/display/icl_dsi.c

htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

htotal = DIV_ROUND_UP((hactive + 160) * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

vtotal = vactive + DIV_ROUND_UP(400, line_time_us);

sys/dev/pci/drm/i915/display/intel_alpm.c

int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;

sys/dev/pci/drm/i915/display/intel_alpm.c

return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +

sys/dev/pci/drm/i915/display/intel_audio.c

link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);

sys/dev/pci/drm/i915/display/intel_audio.c

hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;

sys/dev/pci/drm/i915/display/intel_bios.c

DIV_ROUND_UP(backlight_data->hdr_dpcd_refresh_timeout[panel_type], 100);

sys/dev/pci/drm/i915/display/intel_bw.c

data_rate = DIV_ROUND_UP(data_rate, 1000);

sys/dev/pci/drm/i915/display/intel_bw.c

sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0),

sys/dev/pci/drm/i915/display/intel_bw.c

return DIV_ROUND_UP(total_max_bw, 64);

sys/dev/pci/drm/i915/display/intel_bw.c

qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);

sys/dev/pci/drm/i915/display/intel_bw.c

bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);

sys/dev/pci/drm/i915/display/intel_bw.c

qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);

sys/dev/pci/drm/i915/display/intel_bw.c

qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);

sys/dev/pci/drm/i915/display/intel_bw.c

peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;

sys/dev/pci/drm/i915/display/intel_bw.c

clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;

sys/dev/pci/drm/i915/display/intel_bw.c

bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);

sys/dev/pci/drm/i915/display/intel_bw.c

data_rate = DIV_ROUND_UP(data_rate * 105, 100);

sys/dev/pci/drm/i915/display/intel_bw.c

sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);

sys/dev/pci/drm/i915/display/intel_cdclk.c

return DIV_ROUND_UP(cdclk, 25000);

sys/dev/pci/drm/i915/display/intel_cdclk.c

return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);

sys/dev/pci/drm/i915/display/intel_cdclk.c

DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));

sys/dev/pci/drm/i915/display/intel_ddi.c

return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);

sys/dev/pci/drm/i915/display/intel_display.c

return DIV_ROUND_UP(bps, link_bw * 8);

sys/dev/pci/drm/i915/display/intel_display.c

linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,

sys/dev/pci/drm/i915/display/intel_dp.c

min_slice_count = DIV_ROUND_UP(mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

min_slice_count = DIV_ROUND_UP(mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

DIV_ROUND_UP(mode_hdisplay,

sys/dev/pci/drm/i915/display/intel_dp.c

slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,

sys/dev/pci/drm/i915/display/intel_dp.c

return DIV_ROUND_UP(pixel_clock * bpp, 8);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

return DIV_ROUND_UP(kbytes * 8, 1000);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, bitrate);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);

sys/dev/pci/drm/i915/display/intel_fb.c

return DIV_ROUND_UP(fb->base.pitches[color_plane],

sys/dev/pci/drm/i915/display/intel_fb.c

return DIV_ROUND_UP(x + dims->width, dims->tile_width);

sys/dev/pci/drm/i915/display/intel_fb.c

return DIV_ROUND_UP(y + dims->height, dims->tile_height);

sys/dev/pci/drm/i915/display/intel_fb.c

return DIV_ROUND_UP(size, intel_tile_size(display));

sys/dev/pci/drm/i915/display/intel_fb.c

max_size = max(max_size, DIV_ROUND_UP(end, tile_size));

sys/dev/pci/drm/i915/display/intel_fb.c

vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile));

sys/dev/pci/drm/i915/display/intel_fb.c

return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;

sys/dev/pci/drm/i915/display/intel_fb.c

*w = DIV_ROUND_UP(main_width, main_hsub * hsub);

sys/dev/pci/drm/i915/display/intel_fb.c

*h = DIV_ROUND_UP(main_height, main_vsub * vsub);

sys/dev/pci/drm/i915/display/intel_fbdev.c

mode_cmd->pitches[0] = ALIGN(mode_cmd->width * DIV_ROUND_UP(sizes->surface_bpp, 8), 64);

sys/dev/pci/drm/i915/display/intel_fixed.h

return DIV_ROUND_UP(fp.val, 1 << 16);

sys/dev/pci/drm/i915/display/intel_fixed.h

return DIV_ROUND_UP(val.val, d.val);

sys/dev/pci/drm/i915/display/intel_flipq.c

DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) +

sys/dev/pci/drm/i915/display/intel_flipq.c

return DIV_ROUND_UP(intel_flipq_exec_time_us(display), 1000);

sys/dev/pci/drm/i915/display/intel_hdmi.c

adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);

sys/dev/pci/drm/i915/display/intel_hdmi.c

min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);

sys/dev/pci/drm/i915/display/intel_hdmi.c

slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);

sys/dev/pci/drm/i915/display/intel_hdmi.c

bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);

sys/dev/pci/drm/i915/display/intel_hdmi.c

bpp = DIV_ROUND_UP(bpp_target_x16, 16);

sys/dev/pci/drm/i915/display/intel_hdmi.c

target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);

sys/dev/pci/drm/i915/display/intel_lvds.c

DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

DIV_ROUND_UP(crtc_state->pixel_rate, 2);

sys/dev/pci/drm/i915/display/intel_opregion.c

asle->cblv = DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID;

sys/dev/pci/drm/i915/display/intel_plane.c

unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);

sys/dev/pci/drm/i915/display/intel_plane.c

unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

pmdemand_state->params.ddiclk_max = DIV_ROUND_UP(max_ddiclk, 1000);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

DIV_ROUND_UP(intel_cdclk_actual(new_cdclk_state), 1000);

sys/dev/pci/drm/i915/display/intel_pps.c

return DIV_ROUND_UP(val, 10);

sys/dev/pci/drm/i915/display/intel_pps.c

DIV_ROUND_UP(seq->power_cycle, 1000) + 1));

sys/dev/pci/drm/i915/display/intel_pps.c

DIV_ROUND_UP(seq->power_cycle, 1000) + 1));

sys/dev/pci/drm/i915/display/intel_psr.c

return DIV_ROUND_UP(1000 * 1000,

sys/dev/pci/drm/i915/display/intel_sprite.c

return DIV_ROUND_UP(pixel_rate * num, den);

sys/dev/pci/drm/i915/display/intel_sprite.c

return DIV_ROUND_UP(pixel_rate * num, den);

sys/dev/pci/drm/i915/display/intel_sprite.c

return DIV_ROUND_UP(pixel_rate * num, den);

sys/dev/pci/drm/i915/display/intel_vblank.c

vdisplay = DIV_ROUND_UP(vdisplay, 2);

sys/dev/pci/drm/i915/display/intel_vblank.c

vblank_start = DIV_ROUND_UP(vblank_start, 2);

sys/dev/pci/drm/i915/display/intel_vdsc.c

min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);

sys/dev/pci/drm/i915/display/intel_vdsc.c

vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,

sys/dev/pci/drm/i915/display/intel_vdsc.c

vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);

sys/dev/pci/drm/i915/display/intel_vdsc.c

vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);

sys/dev/pci/drm/i915/display/intel_vdsc.c

vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,

sys/dev/pci/drm/i915/display/intel_vdsc.c

return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

return DIV_ROUND_UP(pixel_rate, 2);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

return DIV_ROUND_UP(pixel_rate * num, 2 * den);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

return DIV_ROUND_UP(pixel_rate * num, den);

sys/dev/pci/drm/i915/display/skl_watermark.c

wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,

sys/dev/pci/drm/i915/display/skl_watermark.c

interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *

sys/dev/pci/drm/i915/display/skl_watermark.c

interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,

sys/dev/pci/drm/i915/display/skl_watermark.c

min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);

sys/dev/pci/drm/i915/display/skl_watermark.c

return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,

sys/dev/pci/drm/i915/display/skl_watermark.c

int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,

sys/dev/pci/drm/i915/display/skl_watermark.c

dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);

sys/dev/pci/drm/i915/display/skl_watermark.c

int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,

sys/dev/pci/drm/i915/display/skl_watermark.c

display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);

sys/dev/pci/drm/i915/display/vlv_dsi.c

intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);

sys/dev/pci/drm/i915/display/vlv_dsi.c

prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);

sys/dev/pci/drm/i915/display/vlv_dsi.c

exit_zero_cnt = DIV_ROUND_UP(

sys/dev/pci/drm/i915/display/vlv_dsi.c

clk_zero_cnt = DIV_ROUND_UP(

sys/dev/pci/drm/i915/display/vlv_dsi.c

trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);

sys/dev/pci/drm/i915/display/vlv_dsi.c

tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);

sys/dev/pci/drm/i915/display/vlv_dsi.c

lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +

sys/dev/pci/drm/i915/display/vlv_dsi.c

hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);

sys/dev/pci/drm/i915/display/vlv_dsi.c

DIV_ROUND_UP(

sys/dev/pci/drm/i915/display/vlv_dsi.c

DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,

sys/dev/pci/drm/i915/display/vlv_dsi.c

return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,

sys/dev/pci/drm/i915/display/vlv_dsi.c

return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

txesc1_div = DIV_ROUND_UP(div1_value, 2);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

txesc1_div = DIV_ROUND_UP(div1_value, 4);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

txesc1_div = DIV_ROUND_UP(div1_value, 6);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

txesc1_div = DIV_ROUND_UP(div1_value, 8);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

div2_value = DIV_ROUND_UP(div1_value, txesc1_div);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);

sys/dev/pci/drm/i915/gem/i915_gem_create.c

int cpp = DIV_ROUND_UP(args->bpp, 8);

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

*cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;

sys/dev/pci/drm/i915/gt/intel_migrate.c

DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0)

sys/dev/pci/drm/i915/gt/intel_migrate.c

num_ccs_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),

sys/dev/pci/drm/i915/gt/intel_sseu.c

DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :

sys/dev/pci/drm/i915/gt/intel_sseu.c

DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :

sys/dev/pci/drm/i915/gt/intel_sseu.c

WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >

sys/dev/pci/drm/i915/gt/intel_sseu.h

#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

for (i = 0; !err && i < DIV_ROUND_UP(ccs_bytes, PAGE_SIZE); i++) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

timeout = DIV_ROUND_UP(timeout, 1000);

sys/dev/pci/drm/i915/gt/selftest_rps.c

timeout = DIV_ROUND_UP(timeout, 1000);

sys/dev/pci/drm/i915/gvt/kvmgt.c

DIV_ROUND_UP(size, PAGE_SIZE));

sys/dev/pci/drm/i915/gvt/kvmgt.c

int total_pages = DIV_ROUND_UP(size, PAGE_SIZE);

sys/dev/pci/drm/i915/i915_cmd_parser.c

jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)),

sys/dev/pci/drm/i915/i915_memcpy.c

__memcpy_ntdqu(dst, src, DIV_ROUND_UP(len, 16));

sys/dev/pci/drm/i915/i915_perf.c

count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);

sys/dev/pci/drm/i915/i915_perf_types.h

#define FORMAT_MASK_SIZE DIV_ROUND_UP(I915_OA_FORMAT_MAX - 1, BITS_PER_LONG)

sys/dev/pci/drm/i915/selftests/i915_request.c

max_t(int, 2, DIV_ROUND_UP(num_online_cpus(), nengines));

sys/dev/pci/drm/include/drm/drm_fourcc.h

return DIV_ROUND_UP(width, info->hsub);

sys/dev/pci/drm/include/drm/drm_fourcc.h

return DIV_ROUND_UP(height, info->vsub);

sys/dev/pci/drm/include/linux/math.h

#define DIV_ROUND_UP_ULL(x, y) DIV_ROUND_UP(x, y)

sys/dev/pci/drm/radeon/cik.c

num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);

sys/dev/pci/drm/radeon/cik.c

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/radeon/cik_sdma.c

num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);

sys/dev/pci/drm/radeon/evergreen.c

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/radeon/evergreen_dma.c

num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);

sys/dev/pci/drm/radeon/r100.c

crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,

sys/dev/pci/drm/radeon/r100.c

rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);

sys/dev/pci/drm/radeon/r100.c

rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);

sys/dev/pci/drm/radeon/r100.c

num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);

sys/dev/pci/drm/radeon/r200.c

num_loops = DIV_ROUND_UP(size, 0x1FFFFF);

sys/dev/pci/drm/radeon/r600.c

num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);

sys/dev/pci/drm/radeon/r600_cs.c

return DIV_ROUND_UP(w, bw);

sys/dev/pci/drm/radeon/r600_cs.c

return DIV_ROUND_UP(h, bh);

sys/dev/pci/drm/radeon/r600_dma.c

num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);

sys/dev/pci/drm/radeon/radeon_display.c

unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);

sys/dev/pci/drm/radeon/radeon_display.c

tmp = DIV_ROUND_UP(nom_min, *nom);

sys/dev/pci/drm/radeon/radeon_display.c

tmp = DIV_ROUND_UP(den_min, *den);

sys/dev/pci/drm/radeon/radeon_gem.c

DIV_ROUND_UP(args->bpp, 8), 0);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8,

sys/dev/pci/drm/radeon/rs690.c

rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);

sys/dev/pci/drm/radeon/rs690.c

rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);

sys/dev/pci/drm/radeon/rv770_dma.c

num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);

sys/dev/pci/drm/radeon/si.c

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/pci/drm/radeon/si_dma.c

num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);

sys/dev/pci/drm/ttm/ttm_pool.c

num_pages = DIV_ROUND_UP(num_pages, 2);

sys/dev/pv/viogpu.c

bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);

sys/dev/usb/dwc2/dwc2_core.h

DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];

sys/dev/usb/dwc2/dwc2_core.h

(DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \

sys/dev/usb/dwc2/dwc2_hcd.c

DIV_ROUND_UP(interval * us, us_per_frame);

sys/dev/usb/dwc2/dwc2_hcd.h

#define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \

sys/dev/usb/dwc2/dwc2_hcdqueue.c

int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);

sys/dev/usb/dwc2/dwc2_hcdqueue.c

int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);

sys/dev/usb/dwc2/dwc2_hcdqueue.c

DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %

sys/dev/usb/dwc2/dwc2_hcdqueue.c

qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);

sys/dev/usb/dwc2/dwc2var.h

#define NS_TO_US(ns) DIV_ROUND_UP(ns, 1000L)