sc_status
u_char sc_status[7]; /* copy of registers */
fdc->sc_status[0], NE7_ST0BITS,
fdc->sc_status[1]);
fdc->sc_status[0], NE7_ST0BITS,
fdc->sc_status[1], NE7_ST1BITS,
fdc->sc_status[2], NE7_ST2BITS,
fdc->sc_status[3], fdc->sc_status[4], fdc->sc_status[5]);
#define st0 fdc->sc_status[0]
#define st1 fdc->sc_status[1]
#define cyl fdc->sc_status[1]
(fdc->sc_status[0] & 0xd8) == 0x40 &&
(fdc->sc_status[1] & 0x2) == 0x2) {
fdc->sc_status[0] == 0 &&
fdc->sc_status[1] == 0 &&
fdc->sc_status[2] == 0) {
printf(" 0x%x", fdc->sc_status[i]);
printf(" 0x%x", fdc->sc_status[i]);
if ((vroom = fdc->sc_status[7]) == 0)
fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) {
if (fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x80)
printf(" 0x%x", fdc->sc_status[i]);
ok = (n == 2 && (fdc->sc_status[0] & 0xf8) == 0x20) ? 1 : 0;
if (n >= sizeof(fdc->sc_status)) {
fdc->sc_status[n++] =
if ((CARDSLOT_CARDTYPE(sc->sc_status) ==
(CARDSLOT_CARDTYPE(sc->sc_status) ==
if (CARDSLOT_WORK(sc->sc_status) ==
CARDSLOT_SET_CARDTYPE(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
if ((CARDSLOT_CARDTYPE(sc->sc_status) ==
(CARDSLOT_CARDTYPE(sc->sc_status) ==
if (CARDSLOT_WORK(sc->sc_status) ==
CARDSLOT_SET_CARDTYPE(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
if (CARDSLOT_CARDTYPE(sc->sc_status) ==
if (CARDSLOT_WORK(sc->sc_status) ==
CARDSLOT_SET_WORK(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
CARDSLOT_SET_CARDTYPE(sc->sc_status,
} else if (CARDSLOT_CARDTYPE(sc->sc_status) !=
CARDSLOT_SET_CARDTYPE(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
if (CARDSLOT_CARDTYPE(sc->sc_status) !=
(CARDSLOT_WORK(sc->sc_status) ==
CARDSLOT_SET_CARDTYPE(sc->sc_status,
CARDSLOT_SET_WORK(sc->sc_status,
int sc_status; /* the status of slot */
uint32_t sc_status;
sc->sc_status = status & SD_EMMC_STATUS_MASK;
KASSERT(sc->sc_status == 0);
while (sc->sc_status == 0) {
status = sc->sc_status;
sc->sc_status = 0;
tipd_read_4(sc, TPS_STATUS, &sc->sc_status);
tipd_read_4(sc, TPS_STATUS, &sc->sc_status);
if ((status ^ sc->sc_status) & TPS_STATUS_PLUG_PRESENT) {
sc->sc_status = status;
uint32_t sc_status;
sc->sc_status = HIL_STATUS_BUSY;
sc->sc_status = HIL_STATUS_READY;
if (sc->sc_status != HIL_STATUS_BUSY)
int sc_status; /* initialization status */
rate = sc->sc_buf.sc_status.an_current_tx_rate;
an_swap16((u_int16_t *)&sc->sc_buf.sc_status.an_cur_bssid, 3);
an_swap16((u_int16_t *)&sc->sc_buf.sc_status.an_ssid, 16);
sc->sc_buf.sc_status.an_cur_bssid);
sc->sc_buf.sc_status.an_cur_channel];
ni->ni_esslen = sc->sc_buf.sc_status.an_ssidlen;
memcpy(ni->ni_essid, sc->sc_buf.sc_status.an_ssid,
sc->sc_buf.sc_status.an_cur_channel,
sc->sc_buf.sc_status.an_current_tx_rate/2);
struct an_rid_status sc_status;
sc->sc_status = GDT_S_NO_STATUS;
sc->sc_status = ctx.cmd_status;
if (sc->sc_status != GDT_S_BSY || --retries == 0)
return (sc->sc_status == GDT_S_OK);
sc->sc_status);
sc->sc_status);
"error %d\n", sc->sc_status);
printf("cannot get cache info, error %d\n", sc->sc_status);
sc->sc_status);
switch (sc->sc_status) {
sc->sc_status));
u_int16_t sc_status;
printf(" %x", fdc->sc_status[i]);
if (!(fa->fa_flags & 0x20) && (n != 2 || (fdc->sc_status[0] & 0xf8) != 0x20))
#define st0 fdc->sc_status[0]
#define cyl fdc->sc_status[1]
fdc->sc_status[0], NE7_ST0BITS,
fdc->sc_status[1], NE7_ST1BITS,
fdc->sc_status[2], NE7_ST2BITS,
fdc->sc_status[3], fdc->sc_status[4], fdc->sc_status[5]);
if (n >= sizeof(fdc->sc_status)) {
fdc->sc_status[n++] =
fdc->sc_status[0], NE7_ST0BITS,
fdc->sc_status[1]);
fdc->sc_status[0], NE7_ST0BITS,
fdc->sc_status[1], NE7_ST1BITS,
fdc->sc_status[2], NE7_ST2BITS,
fdc->sc_status[3], fdc->sc_status[4], fdc->sc_status[5]);
u_char sc_status[7]; /* copy of registers */
*operation_result = adev->dm.dmub_notify->sc_status;
notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
enum set_config_status sc_status;
notify->sc_status = cmd.set_config_reply.set_config_reply_control.status;
if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) {
} else if (sc->sc_csc->sc_status &
bio_status_init(&sc->sc_status, &sc->sc_dev);
bio_status_init(&sc->sc_status, &sc->sc_dev);
bio_status(&sc->sc_status, 0, BIO_MSG_INFO, fmt, &ap);
bio_status(&sc->sc_status, 1, BIO_MSG_WARN, fmt, &ap);
bio_status(&sc->sc_status, 1, BIO_MSG_ERROR, fmt, &ap);
bio_status_init(&sc->sc_status, &sc->sc_dev);
sc->sc_status.bs_status = (rv ? BIO_STATUS_ERROR : BIO_STATUS_SUCCESS);
if (sc->sc_status.bs_msg_count > 0)
memcpy(&bio->bio_status, &sc->sc_status, sizeof(struct bio_status));
bio_status_init(&sc->sc_status, &sc->sc_dev);
struct bio_status sc_status; /* Status and messages. */
uint32_t sc_status;
sc->sc_status = 0;
if (sc->sc_status & UBCMTP_ENABLED)
sc->sc_status |= UBCMTP_ENABLED;
if (usbd_is_dying(sc->sc_udev) || !(sc->sc_status & UBCMTP_ENABLED))
sc->sc_status &= ~UBCMTP_ENABLED;
if (usbd_is_dying(sc->sc_udev) || !(sc->sc_status & UBCMTP_ENABLED))
if (usbd_is_dying(sc->sc_udev) || !(sc->sc_status & UBCMTP_ENABLED))
sc->sc_status |= (1 << port);
if ((sc->sc_status & (1 << port)) || up->reattach) {
sc->sc_status &= ~(1 << port);
sc->sc_status |= stats;
uint32_t sc_status; /* status from last interrupt */
sc->sc_status = 0; /* clear status bit */
u_char sc_status;
u_char sc_status;
sc->sc_status = 0; /* clear status bit */
uint32_t sc_status; /* Status flags. */
sc->sc_status = 0;
if (sc->sc_status & usbd_is_dying(sc->sc_hdev.sc_udev))
if (sc->sc_status & UTPMS_ENABLED)
sc->sc_status |= UTPMS_ENABLED;
sc->sc_status &= ~UTPMS_VALID;
if (!(sc->sc_status & UTPMS_ENABLED))
sc->sc_status &= ~UTPMS_ENABLED;
if (!(sc->sc_status & UTPMS_VALID)) {
sc->sc_status |= UTPMS_VALID;
KASSERT(vmm_softc->sc_status == VMM_SUSPENDED);
vmm_softc->sc_status = VMM_ACTIVE;
wakeup(&vmm_softc->sc_status);
while (vmm_softc->sc_status != VMM_ACTIVE) {
ret = rwsleep_nsec(&vmm_softc->sc_status, &vmm_softc->sc_slock,
sc->sc_status = VMM_ACTIVE;
KASSERT(vmm_softc->sc_status == VMM_ACTIVE);
vmm_softc->sc_status = VMM_SUSPENDED;
volatile unsigned int sc_status; /* [a] */