sys/arch/armv7/exynos/exehci.c

236

val = regmap_read_4(sysrm, USB20PHY_CFG);

sys/arch/armv7/exynos/exehci.c

251

val = regmap_read_4(pmurm, offset);

sys/arch/armv7/imx/imxahci.c

154

reg = regmap_read_4(rm, IOMUXC_GPR13);

sys/arch/armv7/imx/imxahci.c

164

reg = regmap_read_4(rm, IOMUXC_GPR13);

sys/arch/armv7/imx/imxtemp.c

139

calibration = regmap_read_4(rm, OCOTP_ANA1);

sys/arch/armv7/imx/imxtemp.c

62

regmap_read_4((sc)->sc_rm, (reg))

sys/arch/armv7/xilinx/zqreset.c

101

return regmap_read_4(rm, reg);

sys/arch/riscv64/dev/smtcomphy.c

177

val = regmap_read_4(sc->sc_apmu, APMU_PCIE_CLK_RES_CTRL_PORTA);

sys/arch/riscv64/dev/smtcomphy.c

286

val = oval = regmap_read_4(sc->sc_apmu, APMU_PMUA_USB_PHY_CTRL0);

sys/arch/riscv64/dev/stfclock.c

675

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF);

sys/arch/riscv64/dev/stfclock.c

679

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF);

sys/arch/riscv64/dev/stfclock.c

682

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF);

sys/arch/riscv64/dev/stfclock.c

686

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PREDIV_OFF);

sys/arch/riscv64/dev/stfclock.c

692

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_PD_OFF);

sys/arch/riscv64/dev/stfclock.c

697

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_FRAC_OFF);

sys/arch/riscv64/dev/stfclock.c

701

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_PREDIV_OFF);

sys/arch/riscv64/dev/stfclock.c

761

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF);

sys/arch/riscv64/dev/stfclock.c

767

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PREDIV_OFF);

sys/arch/riscv64/dev/stfclock.c

772

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF);

sys/arch/riscv64/dev/stfclock.c

777

reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF);

sys/arch/riscv64/dev/stfpcie.c

301

reg = regmap_read_4(rm, stg_base + STG_RP_NEP);

sys/arch/riscv64/dev/stfpcie.c

305

reg = regmap_read_4(rm, stg_base + STG_AWFUN);

sys/arch/riscv64/dev/stfpcie.c

310

reg = regmap_read_4(rm, stg_base + STG_AWFUN);

sys/arch/riscv64/dev/stfpcie.c

395

reg = regmap_read_4(rm, stg_base + STG_ARFUN);

sys/arch/riscv64/dev/stfpcie.c

399

reg = regmap_read_4(rm, stg_base + STG_AWFUN);

sys/arch/riscv64/dev/stfpcie.c

408

reg = regmap_read_4(rm, stg_base + STG_ARFUN);

sys/arch/riscv64/dev/stfpcie.c

411

reg = regmap_read_4(rm, stg_base + STG_AWFUN);

sys/arch/riscv64/dev/stfpcie.c

472

reg = regmap_read_4(rm, stg_base + STG_LNKSTA);

sys/dev/fdt/amlclock.c

107

(regmap_read_4((sc)->sc_rm, (reg) << 2))

sys/dev/fdt/amlpwrc.c

123

val = regmap_read_4(rm, reg << 2);

sys/dev/fdt/amlpwrc.c

48

(regmap_read_4((sc)->sc_rm, (reg) << 2))

sys/dev/fdt/amltemp.c

146

sc->sc_calib = regmap_read_4(rm, offset);

sys/dev/fdt/dwpcie.c

1194

reg = regmap_read_4(gpr, IOMUXC_GPR12);

sys/dev/fdt/dwpcie.c

1209

reg = regmap_read_4(gpr, off);

sys/dev/fdt/dwpcie.c

1218

reg = regmap_read_4(gpr, off);

sys/dev/fdt/dwpcie.c

1223

reg = regmap_read_4(gpr, off);

sys/dev/fdt/dwpcie.c

1236

reg = regmap_read_4(gpr, off);

sys/dev/fdt/dwpcie.c

1248

reg = regmap_read_4(gpr, off);

sys/dev/fdt/dwpcie.c

1252

reg = regmap_read_4(gpr, off);

sys/dev/fdt/dwpcie.c

1282

if (regmap_read_4(phy, IMX8MM_PCIE_PHY_CMN_REG75) ==

sys/dev/fdt/dwpcie.c

1416

val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);

sys/dev/fdt/dwpcie.c

1422

val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC);

sys/dev/fdt/dwpcie.c

1425

regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC);

sys/dev/fdt/dwpcie.c

1441

val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);

sys/dev/fdt/dwpcie.c

1444

regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);

sys/dev/fdt/dwpcie.c

1448

val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);

sys/dev/fdt/dwpcie.c

1455

val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);

sys/dev/fdt/dwpcie.c

1472

val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);

sys/dev/fdt/if_dwqe_fdt.c

457

reg = regmap_read_4(rm, offset);

sys/dev/fdt/if_dwxe.c

528

syscon = regmap_read_4(rm, SYSCON_EMAC);

sys/dev/fdt/if_dwxe.c

575

syscon = regmap_read_4(rm, SYSCON_GMAC);

sys/dev/fdt/if_mvpp.c

2767

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0);

sys/dev/fdt/if_mvpp.c

2770

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_CTRL0);

sys/dev/fdt/if_mvpp.c

2780

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0);

sys/dev/fdt/if_mvpp.c

2785

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_CTRL0);

sys/dev/fdt/if_mvpp.c

2810

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL1);

sys/dev/fdt/if_mvpp.c

2815

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0);

sys/dev/fdt/if_mvpp.c

2819

reg = regmap_read_4(sc->sc->sc_rm, GENCONF_SOFT_RESET1);

sys/dev/fdt/imxccm.c

1163

pllout_div = regmap_read_4(sc->sc_anatop, CCM_FRAC_IMX8M_PLLOUT_DIV_CFG);

sys/dev/fdt/imxccm.c

1167

pll0 = regmap_read_4(sc->sc_anatop, CCM_FRAC_IMX8M_ARM_PLL0);

sys/dev/fdt/imxccm.c

1168

pll1 = regmap_read_4(sc->sc_anatop, CCM_FRAC_IMX8M_ARM_PLL1);

sys/dev/fdt/imxccm.c

1223

pllout_div = regmap_read_4(sc->sc_anatop, CCM_FRAC_IMX8M_PLLOUT_DIV_CFG);

sys/dev/fdt/imxccm.c

1240

reg = regmap_read_4(sc->sc_anatop, pll0);

sys/dev/fdt/imxccm.c

1266

reg = regmap_read_4(sc->sc_anatop, pll1);

sys/dev/fdt/imxccm.c

1273

reg = regmap_read_4(sc->sc_anatop, pll0);

sys/dev/fdt/imxccm.c

1279

reg = regmap_read_4(sc->sc_anatop, pll0);

sys/dev/fdt/imxccm.c

1284

reg = regmap_read_4(sc->sc_anatop, pll0);

sys/dev/fdt/imxccm.c

1296

reg = regmap_read_4(sc->sc_anatop, pll0);

sys/dev/fdt/imxccm.c

519

while ((regmap_read_4(sc->sc_anatop,

sys/dev/fdt/imxccm.c

536

while ((regmap_read_4(sc->sc_anatop,

sys/dev/fdt/imxccm.c

553

while ((regmap_read_4(sc->sc_anatop,

sys/dev/fdt/imxccm.c

660

pll0 = regmap_read_4(sc->sc_anatop,

sys/dev/fdt/imxccm.c

662

pll1 = regmap_read_4(sc->sc_anatop,

sys/dev/fdt/imxccm.c

743

regmap_read_4(sc->sc_anatop, pll0) |

sys/dev/fdt/imxccm.c

746

regmap_read_4(sc->sc_anatop, pll0) &

sys/dev/fdt/imxccm.c

754

regmap_read_4(sc->sc_anatop, pll0) |

sys/dev/fdt/imxccm.c

757

reg = regmap_read_4(sc->sc_anatop, pll0);

sys/dev/fdt/imxccm.c

765

regmap_read_4(sc->sc_anatop, pll0) &

sys/dev/fdt/imxrtc.c

40

(regmap_read_4((sc)->sc_rm, (reg)))

sys/dev/fdt/mvclock.c

241

reg = regmap_read_4(rm, CP110_PM_CLOCK_GATING_CTRL);

sys/dev/fdt/mvgpio.c

38

(regmap_read_4((sc)->sc_rm, (sc)->sc_offset + (reg)))

sys/dev/fdt/mvpinctrl.c

342

if (regmap_read_4(sc->sc_rm, XTAL) & XTAL_MODE)

sys/dev/fdt/mvpinctrl.c

41

(regmap_read_4((sc)->sc_rm, (reg)))

sys/dev/fdt/mvtemp.c

193

return regmap_read_4(sc->sc_rm, sc->sc_offs[reg]);

sys/dev/fdt/rkclock.c

2161

reg = regmap_read_4(sc->sc_grf, RK3328_GRF_MAC_CON1);

sys/dev/fdt/rkcomphy.c

396

stat = regmap_read_4(phy_rm,

sys/dev/fdt/rkemmcphy.c

63

(regmap_read_4((sc)->sc_rm, (sc)->sc_off + (reg)))

sys/dev/fdt/rkpcie.c

724

status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1);

sys/dev/fdt/rkpcie.c

740

status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1);

sys/dev/fdt/rkpcie.c

756

status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1);

sys/dev/fdt/rkpciephy.c

147

stat = regmap_read_4(rm, GRF_PCIE30PHY_STATUS0);

sys/dev/fdt/rkpciephy.c

221

stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY0_STATUS1);

sys/dev/fdt/rkpciephy.c

227

stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY1_STATUS1);

sys/dev/fdt/rktcphy.c

215

reg = regmap_read_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id));

sys/dev/fdt/rktcphy.c

225

reg = regmap_read_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id));

sys/dev/fdt/rkusbphy.c

380

v = regmap_read_4(rm, r->r_offs);

sys/dev/fdt/syscon.c

152

value = regmap_read_4(rm, sc->sc_offset);

sys/dev/fdt/syscon.c

170

value = regmap_read_4(rm, sc->sc_offset);

sys/dev/fdt/xhci_fdt.c

551

val = regmap_read_4(pmurm, offset);

sys/dev/ofw/ofw_misc.h

30

uint32_t regmap_read_4(struct regmap *, bus_size_t);