sys/arch/armv7/omap/if_cpsw.c

697

cpsw_mii_readreg(struct device *dev, int phy, int reg)

sys/arch/armv7/omap/if_cpsw.c

706

((reg & 0x1F) << 21) | ((phy & 0x1F) << 16));

sys/arch/armv7/omap/if_cpsw.c

719

cpsw_mii_writereg(struct device *dev, int phy, int reg, int val)

sys/arch/armv7/omap/if_cpsw.c

730

((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val);

sys/arch/armv7/sunxi/sxie.c

211

int phy, node, phy_supply, phyloc = MII_PHY_ANY;

sys/arch/armv7/sunxi/sxie.c

231

phy = OF_getpropint(faa->fa_node, "phy", 0);

sys/arch/armv7/sunxi/sxie.c

232

if (phy == 0)

sys/arch/armv7/sunxi/sxie.c

233

phy = OF_getpropint(faa->fa_node, "phy-handle", 0);

sys/arch/armv7/sunxi/sxie.c

234

node = OF_getnodebyphandle(phy);

sys/arch/armv7/sunxi/sxie.c

690

sxie_miibus_readreg(struct device *dev, int phy, int reg)

sys/arch/armv7/sunxi/sxie.c

695

SXIWRITE4(sc, SXIE_MACMADR, phy << 8 | reg);

sys/arch/armv7/sunxi/sxie.c

712

sxie_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/arch/armv7/sunxi/sxie.c

717

SXIWRITE4(sc, SXIE_MACMADR, phy << 8 | reg);

sys/arch/macppc/dev/if_bm.c

885

bmac_mii_readreg(struct device *dev, int phy, int reg)

sys/arch/macppc/dev/if_bm.c

887

return mii_bitbang_readreg(dev, &bmac_mbo, phy, reg);

sys/arch/macppc/dev/if_bm.c

891

bmac_mii_writereg(struct device *dev, int phy, int reg, int val)

sys/arch/macppc/dev/if_bm.c

893

mii_bitbang_writereg(dev, &bmac_mbo, phy, reg, val);

sys/dev/fdt/dwpcie.c

1146

struct regmap *anatop, *gpr, *phy;

sys/dev/fdt/dwpcie.c

1153

phy = regmap_bycompatible("fsl,imx7d-pcie-phy");

sys/dev/fdt/dwpcie.c

1154

KASSERT(phy != NULL);

sys/dev/fdt/dwpcie.c

1232

regmap_write_4(phy, IMX8MM_PCIE_PHY_CMN_REG62,

sys/dev/fdt/dwpcie.c

1234

regmap_write_4(phy, IMX8MM_PCIE_PHY_CMN_REG64,

sys/dev/fdt/dwpcie.c

1240

regmap_write_4(phy, IMX8MM_PCIE_PHY_TRSV_REG5,

sys/dev/fdt/dwpcie.c

1242

regmap_write_4(phy, IMX8MM_PCIE_PHY_TRSV_REG6,

sys/dev/fdt/dwpcie.c

1282

if (regmap_read_4(phy, IMX8MM_PCIE_PHY_CMN_REG75) ==

sys/dev/fdt/ehci_fdt.c

256

uint32_t *phy;

sys/dev/fdt/ehci_fdt.c

269

phy = phys;

sys/dev/fdt/ehci_fdt.c

270

while (phy && phy < phys + (len / sizeof(uint32_t))) {

sys/dev/fdt/ehci_fdt.c

271

ehci_init_phy(sc, phy);

sys/dev/fdt/ehci_fdt.c

272

phy = ehci_next_phy(phy);

sys/dev/fdt/if_bse_fdt.c

58

uint32_t phy;

sys/dev/fdt/if_bse_fdt.c

97

phy = OF_getpropint(faa->fa_node, "phy-handle", 0);

sys/dev/fdt/if_bse_fdt.c

98

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_cad.c

399

int node, phy;

sys/dev/fdt/if_cad.c

449

phy = OF_getpropint(faa->fa_node, "phy-handle", 0);

sys/dev/fdt/if_cad.c

450

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_dwge.c

394

uint32_t phy, phy_supply;

sys/dev/fdt/if_dwge.c

411

phy = OF_getpropint(faa->fa_node, "phy", 0);

sys/dev/fdt/if_dwge.c

412

if (phy == 0)

sys/dev/fdt/if_dwge.c

413

phy = OF_getpropint(faa->fa_node, "phy-handle", 0);

sys/dev/fdt/if_dwge.c

414

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_dwge.c

860

dwge_mii_readreg(struct device *self, int phy, int reg)

sys/dev/fdt/if_dwge.c

867

phy << GMAC_GMII_ADDR_PA_SHIFT |

sys/dev/fdt/if_dwge.c

881

dwge_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/fdt/if_dwge.c

889

phy << GMAC_GMII_ADDR_PA_SHIFT |

sys/dev/fdt/if_dwqe_fdt.c

105

uint32_t phy, phy_supply;

sys/dev/fdt/if_dwqe_fdt.c

157

phy = OF_getpropint(faa->fa_node, "phy", 0);

sys/dev/fdt/if_dwqe_fdt.c

158

if (phy == 0)

sys/dev/fdt/if_dwqe_fdt.c

159

phy = OF_getpropint(faa->fa_node, "phy-handle", 0);

sys/dev/fdt/if_dwqe_fdt.c

160

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_dwqe_fdt.c

212

dwqe_reset_phy(sc, phy);

sys/dev/fdt/if_dwqe_fdt.c

303

dwqe_reset_phy(struct dwqe_softc *sc, uint32_t phy)

sys/dev/fdt/if_dwqe_fdt.c

310

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_dwxe.c

379

uint32_t phy;

sys/dev/fdt/if_dwxe.c

403

phy = OF_getpropint(faa->fa_node, "phy-handle", 0);

sys/dev/fdt/if_dwxe.c

404

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_dwxe.c

770

dwxe_mii_readreg(struct device *self, int phy, int reg)

sys/dev/fdt/if_dwxe.c

777

phy << DWXE_MDIO_CMD_PHY_ADDR_SHIFT |

sys/dev/fdt/if_dwxe.c

792

dwxe_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/fdt/if_dwxe.c

800

phy << DWXE_MDIO_CMD_PHY_ADDR_SHIFT |

sys/dev/fdt/if_fec.c

1168

fec_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/fdt/if_fec.c

1177

phy << ENET_MMFR_PA_SHIFT | reg << ENET_MMFR_RA_SHIFT);

sys/dev/fdt/if_fec.c

1187

fec_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/fdt/if_fec.c

1195

phy << ENET_MMFR_PA_SHIFT | reg << ENET_MMFR_RA_SHIFT |

sys/dev/fdt/if_fec.c

480

int phy = child->mii_phy;

sys/dev/fdt/if_fec.c

486

fec_miibus_writereg(dev, phy, 0x0d, 0x0003);

sys/dev/fdt/if_fec.c

487

fec_miibus_writereg(dev, phy, 0x0e, 0x805d);

sys/dev/fdt/if_fec.c

488

fec_miibus_writereg(dev, phy, 0x0d, 0x4003);

sys/dev/fdt/if_fec.c

489

reg = fec_miibus_readreg(dev, phy, 0x0e);

sys/dev/fdt/if_fec.c

490

fec_miibus_writereg(dev, phy, 0x0e, reg & ~0x0100);

sys/dev/fdt/if_fec.c

493

fec_miibus_writereg(dev, phy, 0x0d, 0x0007);

sys/dev/fdt/if_fec.c

494

fec_miibus_writereg(dev, phy, 0x0e, 0x8016);

sys/dev/fdt/if_fec.c

495

fec_miibus_writereg(dev, phy, 0x0d, 0x4007);

sys/dev/fdt/if_fec.c

497

reg = fec_miibus_readreg(dev, phy, 0x0e) & 0xffe3;

sys/dev/fdt/if_fec.c

498

fec_miibus_writereg(dev, phy, 0x0e, reg | 0x18);

sys/dev/fdt/if_fec.c

501

fec_miibus_writereg(dev, phy, 0x1d, 0x0005);

sys/dev/fdt/if_fec.c

502

reg = fec_miibus_readreg(dev, phy, 0x1e);

sys/dev/fdt/if_fec.c

503

fec_miibus_writereg(dev, phy, 0x1e, reg | 0x0100);

sys/dev/fdt/if_fec.c

513

uint32_t val, phy;

sys/dev/fdt/if_fec.c

517

phy = OF_getpropint(sc->sc_node, "phy-handle", 0);

sys/dev/fdt/if_fec.c

518

if (phy)

sys/dev/fdt/if_fec.c

519

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_fec.c

535

fec_miibus_writereg(dev, phy, 0x0b, 0x8104);

sys/dev/fdt/if_fec.c

536

fec_miibus_writereg(dev, phy, 0x0c, val);

sys/dev/fdt/if_fec.c

540

fec_miibus_writereg(dev, phy, 0x0b, 0x8105);

sys/dev/fdt/if_fec.c

541

fec_miibus_writereg(dev, phy, 0x0c, val);

sys/dev/fdt/if_fec.c

545

fec_miibus_writereg(dev, phy, 0x0b, 0x8106);

sys/dev/fdt/if_fec.c

546

fec_miibus_writereg(dev, phy, 0x0c, val);

sys/dev/fdt/if_fec.c

554

uint32_t val, phy;

sys/dev/fdt/if_fec.c

558

phy = OF_getpropint(sc->sc_node, "phy-handle", 0);

sys/dev/fdt/if_fec.c

559

if (phy)

sys/dev/fdt/if_fec.c

560

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_fec.c

575

fec_miibus_writereg(dev, phy, 0x0d, 0x0002);

sys/dev/fdt/if_fec.c

576

fec_miibus_writereg(dev, phy, 0x0e, 0x0004);

sys/dev/fdt/if_fec.c

577

fec_miibus_writereg(dev, phy, 0x0d, 0x4002);

sys/dev/fdt/if_fec.c

578

fec_miibus_writereg(dev, phy, 0x0e, val);

sys/dev/fdt/if_fec.c

582

fec_miibus_writereg(dev, phy, 0x0d, 0x0002);

sys/dev/fdt/if_fec.c

583

fec_miibus_writereg(dev, phy, 0x0e, 0x0005);

sys/dev/fdt/if_fec.c

584

fec_miibus_writereg(dev, phy, 0x0d, 0x4002);

sys/dev/fdt/if_fec.c

585

fec_miibus_writereg(dev, phy, 0x0e, val);

sys/dev/fdt/if_fec.c

589

fec_miibus_writereg(dev, phy, 0x0d, 0x0002);

sys/dev/fdt/if_fec.c

590

fec_miibus_writereg(dev, phy, 0x0e, 0x0006);

sys/dev/fdt/if_fec.c

591

fec_miibus_writereg(dev, phy, 0x0d, 0x4002);

sys/dev/fdt/if_fec.c

592

fec_miibus_writereg(dev, phy, 0x0e, val);

sys/dev/fdt/if_fec.c

595

fec_miibus_writereg(dev, phy, 0x0d, 0x0002);

sys/dev/fdt/if_fec.c

596

fec_miibus_writereg(dev, phy, 0x0e, 0x0008);

sys/dev/fdt/if_fec.c

597

fec_miibus_writereg(dev, phy, 0x0d, 0x4002);

sys/dev/fdt/if_fec.c

598

fec_miibus_writereg(dev, phy, 0x0e, val);

sys/dev/fdt/if_mvneta.c

237

mvneta_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/fdt/if_mvneta.c

240

return sc->sc_mdio->md_readreg(sc->sc_mdio->md_cookie, phy, reg);

sys/dev/fdt/if_mvneta.c

244

mvneta_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/fdt/if_mvneta.c

247

return sc->sc_mdio->md_writereg(sc->sc_mdio->md_cookie, phy, reg, val);

sys/dev/fdt/if_mvnetareg.h

214

#define MVNETA_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5))

sys/dev/fdt/if_mvnetareg.h

218

#define MVNETA_SMI_PHYAD(phy) (((phy) & 0x1f) << 16)

sys/dev/fdt/if_mvpp.c

1326

uint32_t phy, reg;

sys/dev/fdt/if_mvpp.c

1374

phy = OF_getpropint(sc->sc_node, "phy", 0);

sys/dev/fdt/if_mvpp.c

1375

if (phy) {

sys/dev/fdt/if_mvpp.c

1376

node = OF_getnodebyphandle(phy);

sys/dev/fdt/if_mvpp.c

1381

sc->sc_mdio = mii_byphandle(phy);

sys/dev/fdt/if_mvpp.c

1918

mvpp2_mii_readreg(struct device *self, int phy, int reg)

sys/dev/fdt/if_mvpp.c

1921

return sc->sc_mdio->md_readreg(sc->sc_mdio->md_cookie, phy, reg);

sys/dev/fdt/if_mvpp.c

1925

mvpp2_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/fdt/if_mvpp.c

1928

return sc->sc_mdio->md_writereg(sc->sc_mdio->md_cookie, phy, reg, val);

sys/dev/fdt/imxehci.c

124

uint32_t phy[1], misc[2];

sys/dev/fdt/imxehci.c

134

phy, sizeof(phy)) != sizeof(phy)) {

sys/dev/fdt/imxehci.c

136

phy, sizeof(phy)) != sizeof(phy))

sys/dev/fdt/imxehci.c

235

imxehci_init_phy(sc, phy);

sys/dev/fdt/mvmdio.c

120

mvmdio_smi_readreg(struct device *dev, int phy, int reg)

sys/dev/fdt/mvmdio.c

139

smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg)

sys/dev/fdt/mvmdio.c

158

mvmdio_smi_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/fdt/mvmdio.c

177

smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) |

sys/dev/fdt/mvsw.c

116

uint32_t phy;

sys/dev/fdt/mvsw.c

152

phy = OF_getpropint(port, "phy-handle", 0);

sys/dev/fdt/mvsw.c

153

node = OF_getnodebyphandle(phy);

sys/dev/fdt/mvsw.c

193

mvsw_smi_read(struct mvsw_softc *sc, int phy, int reg)

sys/dev/fdt/mvsw.c

199

MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |

sys/dev/fdt/mvsw.c

209

mvsw_smi_write(struct mvsw_softc *sc, int phy, int reg, int val)

sys/dev/fdt/mvsw.c

216

MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |

sys/dev/fdt/mvsw.c

239

mvsw_phy_read(struct mvsw_softc *sc, int phy, int reg)

sys/dev/fdt/mvsw.c

245

MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |

sys/dev/fdt/mvsw.c

255

mvsw_phy_write(struct mvsw_softc *sc, int phy, int reg, int val)

sys/dev/fdt/mvsw.c

262

MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |

sys/dev/fdt/mvsw.c

331

int phy;

sys/dev/fdt/mvsw.c

333

phy = OF_getpropint(node, "reg", -1);

sys/dev/fdt/mvsw.c

334

if (phy == -1)

sys/dev/fdt/mvsw.c

338

val = mvsw_phy_read(sc, phy, MII_BMCR);

sys/dev/fdt/mvsw.c

340

mvsw_phy_write(sc, phy, MII_BMCR, val);

sys/dev/fdt/rkpciephy.c

164

struct regmap *phy, *pipe;

sys/dev/fdt/rkpciephy.c

171

phy = regmap_byphandle(grf);

sys/dev/fdt/rkpciephy.c

172

if (phy == NULL)

sys/dev/fdt/rkpciephy.c

179

regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0),

sys/dev/fdt/rkpciephy.c

203

regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0), reg);

sys/dev/fdt/rkpciephy.c

221

stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY0_STATUS1);

sys/dev/fdt/rkpciephy.c

227

stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY1_STATUS1);

sys/dev/fdt/xhci_fdt.c

418

uint32_t *phy;

sys/dev/fdt/xhci_fdt.c

432

phy = phys;

sys/dev/fdt/xhci_fdt.c

433

while (phy && phy < phys + (len / sizeof(uint32_t))) {

sys/dev/fdt/xhci_fdt.c

435

xhci_init_phy(sc, phy);

sys/dev/fdt/xhci_fdt.c

440

phy = xhci_next_phy(phy);

sys/dev/ic/aic6915.c

1361

sf_mii_read(struct device *self, int phy, int reg)

sys/dev/ic/aic6915.c

1368

v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));

sys/dev/ic/aic6915.c

1389

sf_mii_write(struct device *self, int phy, int reg, int val)

sys/dev/ic/aic6915.c

1394

sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);

sys/dev/ic/aic6915.c

1397

if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &

sys/dev/ic/ar5008.c

1585

if (athn_rates[ridx[0]].phy == IEEE80211_T_DS &&

sys/dev/ic/ar5008.c

1678

athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) ||

sys/dev/ic/ar5008.c

1698

if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&

sys/dev/ic/ar5008.c

1889

uint32_t phy;

sys/dev/ic/ar5008.c

1892

phy = AR_READ(sc, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO;

sys/dev/ic/ar5008.c

1894

phy = 0;

sys/dev/ic/ar5008.c

1895

phy |= AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |

sys/dev/ic/ar5008.c

1898

phy |= AR_PHY_FC_DYN2040_EN;

sys/dev/ic/ar5008.c

1900

phy |= AR_PHY_FC_DYN2040_PRI_CH;

sys/dev/ic/ar5008.c

1902

AR_WRITE(sc, AR_PHY_TURBO, phy);

sys/dev/ic/ar5416.c

186

uint32_t phy, reg;

sys/dev/ic/ar5416.c

190

phy = 0;

sys/dev/ic/ar5416.c

196

phy |= AR5416_BMODE_SYNTH;

sys/dev/ic/ar5416.c

215

phy |= SM(AR5416_AMODE_REFSEL, 2);

sys/dev/ic/ar5416.c

220

phy |= SM(AR5416_AMODE_REFSEL, 1);

sys/dev/ic/ar5416.c

222

phy |= SM(AR5416_AMODE_REFSEL, 2);

sys/dev/ic/ar5416.c

225

phy |= SM(AR5416_AMODE_REFSEL, 2);

sys/dev/ic/ar5416.c

230

phy |= chansel << 8 | 1 << 5 | 1;

sys/dev/ic/ar5416.c

231

DPRINTFN(4, ("AR_PHY(0x37)=0x%08x\n", phy));

sys/dev/ic/ar5416.c

232

AR_WRITE(sc, AR_PHY(0x37), phy);

sys/dev/ic/ar5xxx.c

315

switch (rate->phy) {

sys/dev/ic/ar5xxx.h

333

u_int8_t phy;

sys/dev/ic/ar5xxx.h

341

#define r_phy phy

sys/dev/ic/ar9003.c

1486

if (athn_rates[ridx[0]].phy == IEEE80211_T_DS &&

sys/dev/ic/ar9003.c

1606

athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) {

sys/dev/ic/ar9003.c

1624

if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&

sys/dev/ic/ar9003.c

1828

uint32_t phy;

sys/dev/ic/ar9003.c

1830

phy = AR_READ(sc, AR_PHY_GEN_CTRL);

sys/dev/ic/ar9003.c

1831

phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 |

sys/dev/ic/ar9003.c

1834

phy |= AR_PHY_GC_DYN2040_EN;

sys/dev/ic/ar9003.c

1836

phy |= AR_PHY_GC_DYN2040_PRI_CH;

sys/dev/ic/ar9003.c

1839

phy &= ~AR_PHY_GC_GF_DETECT_EN;

sys/dev/ic/ar9003.c

1840

AR_WRITE(sc, AR_PHY_GEN_CTRL, phy);

sys/dev/ic/ar9280.c

179

uint32_t phy, reg, ndiv = 0;

sys/dev/ic/ar9280.c

182

phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;

sys/dev/ic/ar9280.c

185

phy |= (freq << 16) / 15;

sys/dev/ic/ar9280.c

186

phy |= AR9280_BMODE | AR9280_FRACMODE;

sys/dev/ic/ar9280.c

214

phy |= SM(AR9280_AMODE_REFSEL, 3);

sys/dev/ic/ar9280.c

217

phy |= SM(AR9280_AMODE_REFSEL, 2);

sys/dev/ic/ar9280.c

221

phy |= (ndiv & 0x1ff) << 17;

sys/dev/ic/ar9280.c

222

phy |= (ndiv & ~0x1ff) * 2;

sys/dev/ic/ar9280.c

224

phy |= (freq << 15) / 15;

sys/dev/ic/ar9280.c

225

phy |= AR9280_FRACMODE;

sys/dev/ic/ar9280.c

233

DPRINTFN(4, ("AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy));

sys/dev/ic/ar9280.c

234

AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);

sys/dev/ic/ar9380.c

264

uint32_t chansel, phy;

sys/dev/ic/ar9380.c

284

phy = (chansel << 2) | AR9380_FRACMODE;

sys/dev/ic/ar9380.c

285

DPRINTFN(4, ("AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy));

sys/dev/ic/ar9380.c

286

AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);

sys/dev/ic/ar9380.c

289

AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);

sys/dev/ic/athn.c

1948

} else if (athn_rates[ridx].phy == IEEE80211_T_OFDM) {

sys/dev/ic/athn.c

2507

if (athn_rates[an->ridx[j]].phy ==

sys/dev/ic/athn.c

2508

athn_rates[an->ridx[i]].phy) {

sys/dev/ic/athnvar.h

134

enum ieee80211_phytype phy;

sys/dev/ic/ax88190.c

153

ax88190_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/ax88190.c

155

return (mii_bitbang_readreg(self, &ax88190_mii_bitbang_ops, phy, reg));

sys/dev/ic/ax88190.c

159

ax88190_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/ax88190.c

161

mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);

sys/dev/ic/bcmgenet.c

112

genet_mii_readreg(struct device *dev, int phy, int reg)

sys/dev/ic/bcmgenet.c

119

__SHIFTIN(phy, GENET_MDIO_PMD) |

sys/dev/ic/bcmgenet.c

128

sc->sc_dev.dv_xname, phy, reg);

sys/dev/ic/bcmgenet.c

133

genet_mii_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/ic/bcmgenet.c

140

__SHIFTIN(phy, GENET_MDIO_PMD) |

sys/dev/ic/bcmgenet.c

149

sc->sc_dev.dv_xname, phy, reg);

sys/dev/ic/bwi.c

1391

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

1417

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/ic/bwi.c

1443

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

1456

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

1555

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

1560

KASSERT(phy->phy_mode != IEEE80211_MODE_11A);

sys/dev/ic/bwi.c

1568

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

1569

if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)

sys/dev/ic/bwi.c

1576

if (phy->phy_mode == IEEE80211_MODE_11B && phy->phy_rev >= 2 &&

sys/dev/ic/bwi.c

2150

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2154

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/ic/bwi.c

2160

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

2161

if (phy->phy_rev == 1)

sys/dev/ic/bwi.c

2165

} else if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/ic/bwi.c

2166

if (phy->phy_rev >= 2 && rf->rf_type == BWI_RF_T_BCM2050)

sys/dev/ic/bwi.c

2169

panic("unknown PHY mode %u", phy->phy_mode);

sys/dev/ic/bwi.c

2179

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2207

bwi_mac_set_ackrates(mac, &sc->sc_ic.ic_sup_rates[phy->phy_mode]);

sys/dev/ic/bwi.c

2212

if (phy->phy_mode == IEEE80211_MODE_11B)

sys/dev/ic/bwi.c

2831

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2855

phy->phy_init = bwi_phy_init_11a;

sys/dev/ic/bwi.c

2856

phy->phy_mode = IEEE80211_MODE_11A;

sys/dev/ic/bwi.c

2857

phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11A;

sys/dev/ic/bwi.c

2858

phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11A;

sys/dev/ic/bwi.c

2859

phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11A;

sys/dev/ic/bwi.c

2864

phy->phy_init = bwi_sup_bphy[i].init;

sys/dev/ic/bwi.c

2873

phy->phy_mode = IEEE80211_MODE_11B;

sys/dev/ic/bwi.c

2881

phy->phy_init = bwi_phy_init_11g;

sys/dev/ic/bwi.c

2882

phy->phy_mode = IEEE80211_MODE_11G;

sys/dev/ic/bwi.c

2883

phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11G;

sys/dev/ic/bwi.c

2884

phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11G;

sys/dev/ic/bwi.c

2885

phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11G;

sys/dev/ic/bwi.c

2892

phy->phy_rev = phyrev;

sys/dev/ic/bwi.c

2893

phy->phy_version = phyver;

sys/dev/ic/bwi.c

2901

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2904

if (phy->phy_version == 0) {

sys/dev/ic/bwi.c

2908

if (phy->phy_version > 1)

sys/dev/ic/bwi.c

2920

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2926

if (phy->phy_flags & BWI_PHY_F_CALIBRATED)

sys/dev/ic/bwi.c

2929

if (phy->phy_mode == IEEE80211_MODE_11G && phy->phy_rev == 1) {

sys/dev/ic/bwi.c

2935

phy->phy_flags |= BWI_PHY_F_CALIBRATED;

sys/dev/ic/bwi.c

2943

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2945

KASSERT(phy->phy_tbl_ctrl != 0 && phy->phy_tbl_data_lo != 0);

sys/dev/ic/bwi.c

2946

PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);

sys/dev/ic/bwi.c

2947

PHY_WRITE(mac, phy->phy_tbl_data_lo, data);

sys/dev/ic/bwi.c

2953

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2955

KASSERT(phy->phy_tbl_data_lo != 0 && phy->phy_tbl_data_hi != 0 &&

sys/dev/ic/bwi.c

2956

phy->phy_tbl_ctrl != 0);

sys/dev/ic/bwi.c

2958

PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);

sys/dev/ic/bwi.c

2959

PHY_WRITE(mac, phy->phy_tbl_data_hi, data >> 16);

sys/dev/ic/bwi.c

2960

PHY_WRITE(mac, phy->phy_tbl_data_lo, data & 0xffff);

sys/dev/ic/bwi.c

2987

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

2991

if (phy->phy_rev == 1)

sys/dev/ic/bwi.c

2996

if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED))

sys/dev/ic/bwi.c

2999

if (phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

3003

if (phy->phy_rev == 2) {

sys/dev/ic/bwi.c

3006

} else if (phy->phy_rev > 5) {

sys/dev/ic/bwi.c

3012

if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED)) {

sys/dev/ic/bwi.c

3026

if ((phy->phy_rev <= 2 && (phy->phy_flags & BWI_PHY_F_LINKED)) ||

sys/dev/ic/bwi.c

3027

phy->phy_rev >= 2)

sys/dev/ic/bwi.c

3035

if (phy->phy_rev >= 2 && (phy->phy_flags & BWI_PHY_F_LINKED))

sys/dev/ic/bwi.c

3051

if (phy->phy_rev >= 6) {

sys/dev/ic/bwi.c

3061

if (phy->phy_rev < 2)

sys/dev/ic/bwi.c

3067

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

3075

} else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

3182

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3185

if (phy->phy_version == 1)

sys/dev/ic/bwi.c

3204

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

3223

if (phy->phy_version == 1) {

sys/dev/ic/bwi.c

3235

if (phy->phy_version == 1)

sys/dev/ic/bwi.c

3240

if (phy->phy_version == 0)

sys/dev/ic/bwi.c

3283

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3343

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

3394

if (phy->phy_version == 4) {

sys/dev/ic/bwi.c

3401

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/ic/bwi.c

3422

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3427

if (phy->phy_rev == 1) {

sys/dev/ic/bwi.c

3454

if (phy->phy_rev == 2) {

sys/dev/ic/bwi.c

3457

} else if (phy->phy_rev > 2) {

sys/dev/ic/bwi.c

3478

if (phy->phy_rev <= 2) {

sys/dev/ic/bwi.c

3481

} else if (phy->phy_rev >= 7 && (PHY_READ(mac, 0x449) & 0x200)) {

sys/dev/ic/bwi.c

3494

if (phy->phy_rev == 2) {

sys/dev/ic/bwi.c

3497

} else if (phy->phy_rev > 2 && phy->phy_rev <= 8) {

sys/dev/ic/bwi.c

3507

if (phy->phy_rev == 1) {

sys/dev/ic/bwi.c

3555

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3558

ofs = phy->phy_rev == 1 ? 0x4c00 : 0;

sys/dev/ic/bwi.c

3565

if (phy->phy_rev == 1) {

sys/dev/ic/bwi.c

3585

if (phy->phy_rev == 1)

sys/dev/ic/bwi.c

3598

if (phy->phy_rev == 1) {

sys/dev/ic/bwi.c

3606

if (phy->phy_rev >= 6) {

sys/dev/ic/bwi.c

3615

if (phy->phy_rev == 1) {

sys/dev/ic/bwi.c

3627

if (phy->phy_rev >= 6) {

sys/dev/ic/bwi.c

3636

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3640

if (phy->phy_rev <= 1) {

sys/dev/ic/bwi.c

3687

bwi_phy_clear_state(struct bwi_phy *phy)

sys/dev/ic/bwi.c

3689

phy->phy_flags &= ~BWI_CLEAR_PHY_FLAGS;

sys/dev/ic/bwi.c

3763

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3805

switch (phy->phy_mode) {

sys/dev/ic/bwi.c

3835

if (phy->phy_rev == 6)

sys/dev/ic/bwi.c

3908

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

3975

if (phy->phy_rev >= 3)

sys/dev/ic/bwi.c

3987

phy->phy_rev >= 7) {

sys/dev/ic/bwi.c

4211

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

4215

if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)

sys/dev/ic/bwi.c

4244

if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {

sys/dev/ic/bwi.c

4295

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

4314

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/ic/bwi.c

4320

} else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4334

if (phy->phy_rev >= 3)

sys/dev/ic/bwi.c

4342

if (phy->phy_rev < 7 ||

sys/dev/ic/bwi.c

4356

if (phy->phy_version == 0) {

sys/dev/ic/bwi.c

4359

if (phy->phy_version >= 2)

sys/dev/ic/bwi.c

4366

if (phy->phy_mode == IEEE80211_MODE_11B)

sys/dev/ic/bwi.c

4369

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4377

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4399

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4406

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4413

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4423

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4449

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/ic/bwi.c

4450

phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4457

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/ic/bwi.c

4458

phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4465

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/ic/bwi.c

4466

phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4476

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/ic/bwi.c

4477

phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4514

if (phy->phy_version != 0)

sys/dev/ic/bwi.c

4520

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/ic/bwi.c

4523

} else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

4620

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

4629

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/ic/bwi.c

4637

phy->phy_mode == IEEE80211_MODE_11G)

sys/dev/ic/bwi.c

4654

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/ic/bwi.c

4695

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/ic/bwi.c

4710

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/ic/bwi.c

4716

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

4741

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/ic/bwi.c

4782

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

4797

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

4816

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

4826

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

4844

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

4863

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

4878

if (phy->phy_flags & BWI_PHY_F_LINKED)

sys/dev/ic/bwi.c

4899

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

4914

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

4918

if (phy->phy_flags & BWI_PHY_F_LINKED)

sys/dev/ic/bwi.c

4922

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/ic/bwi.c

5165

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

5192

if (phy->phy_rev >= 5)

sys/dev/ic/bwi.c

5211

if (phy->phy_version >= 2)

sys/dev/ic/bwi.c

5213

else if (phy->phy_version == 0)

sys/dev/ic/bwi.c

5245

if (phy->phy_version != 0)

sys/dev/ic/bwi.c

5276

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

5306

if (phy->phy_rev >= 6) {

sys/dev/ic/bwi.c

5350

if (phy->phy_version == 0)

sys/dev/ic/bwi.c

5388

if (phy->phy_rev >= 6) {

sys/dev/ic/bwi.c

5407

if (phy->phy_rev >= 6) {

sys/dev/ic/bwi.c

5430

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

5471

if (phy->phy_rev >= 3) {

sys/dev/ic/bwi.c

5478

if (phy->phy_rev == 4 || phy->phy_rev == 6 ||

sys/dev/ic/bwi.c

5479

phy->phy_rev == 7) {

sys/dev/ic/bwi.c

5482

} else if (phy->phy_rev == 3 || phy->phy_rev == 5)

sys/dev/ic/bwi.c

5501

if (phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

5514

if (phy->phy_version >= 2)

sys/dev/ic/bwi.c

5520

if (phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

5559

if (phy->phy_rev >= 3) {

sys/dev/ic/bwi.c

5565

if (phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

5585

if (phy->phy_rev >= 3) {

sys/dev/ic/bwi.c

5795

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

5799

if (phy->phy_flags & BWI_PHY_F_LINKED)

sys/dev/ic/bwi.c

5811

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/ic/bwi.c

5820

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/ic/bwi.c

5836

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/ic/bwi.c

5844

if (phy->phy_rev >= 2) {

sys/dev/ic/bwi.c

5847

if (phy->phy_rev == 2) {

sys/dev/ic/bwi.c

5854

if (phy->phy_rev >= 6)

sys/dev/ic/bwi.c

5873

if (phy->phy_mode == IEEE80211_MODE_11B)

sys/dev/ic/bwi.c

706

struct bwi_phy *phy;

sys/dev/ic/bwi.c

777

phy = &mac->mac_phy;

sys/dev/ic/bwi.c

802

if (phy->phy_mode == IEEE80211_MODE_11B ||

sys/dev/ic/bwi.c

803

phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/ic/bwi.c

809

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/ic/bwi.c

838

} else if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/ic/bwi.c

843

panic("unknown phymode %d", phy->phy_mode);

sys/dev/ic/dc.c

627

dc_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/ic/dc.c

642

if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)

sys/dev/ic/dc.c

650

if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)

sys/dev/ic/dc.c

654

if (phy == (MII_NPHY - 1)) {

sys/dev/ic/dc.c

683

(phy << 23) | (reg << 18));

sys/dev/ic/dc.c

734

frame.mii_phyaddr = phy;

sys/dev/ic/dc.c

748

dc_miibus_writereg(struct device *self, int phy, int reg, int data)

sys/dev/ic/dc.c

756

if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)

sys/dev/ic/dc.c

758

if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)

sys/dev/ic/dc.c

763

(phy << 23) | (reg << 10) | data);

sys/dev/ic/dc.c

804

frame.mii_phyaddr = phy;

sys/dev/ic/dl10019.c

197

dl10019_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/dl10019.c

205

return (mii_bitbang_readreg(self, ops, phy, reg));

sys/dev/ic/dl10019.c

209

dl10019_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/dl10019.c

217

mii_bitbang_writereg(self, ops, phy, reg, val);

sys/dev/ic/dwqe.c

507

dwqe_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/dwqe.c

514

(phy << GMAC_MAC_MDIO_ADDR_PA_SHIFT) |

sys/dev/ic/dwqe.c

530

dwqe_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/dwqe.c

538

(phy << GMAC_MAC_MDIO_ADDR_PA_SHIFT) |

sys/dev/ic/elink3.c

1703

ep_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/elink3.c

1719

ep_mii_sendbits(sc, phy, 5);

sys/dev/ic/elink3.c

1747

ep_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/elink3.c

1760

ep_mii_sendbits(sc, phy, 5);

sys/dev/ic/fxp.c

1570

fxp_mdi_read(struct device *self, int phy, int reg)

sys/dev/ic/fxp.c

1577

(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));

sys/dev/ic/fxp.c

1596

fxp_mdi_write(struct device *self, int phy, int reg, int value)

sys/dev/ic/fxp.c

1602

(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |

sys/dev/ic/gem.c

1286

gem_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/gem.c

1296

printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);

sys/dev/ic/gem.c

1300

v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |

sys/dev/ic/gem.c

1316

gem_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/gem.c

1327

phy, reg, val);

sys/dev/ic/gem.c

1332

(phy << GEM_MIF_PHY_SHIFT) |

sys/dev/ic/gem.c

1408

gem_pcs_readreg(struct device *self, int phy, int reg)

sys/dev/ic/gem.c

1416

printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg);

sys/dev/ic/gem.c

1419

if (phy != GEM_PHYAD_EXTERNAL)

sys/dev/ic/gem.c

1445

gem_pcs_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/gem.c

1455

phy, reg, val);

sys/dev/ic/gem.c

1458

if (phy != GEM_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

1020

hme_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/hme.c

1030

if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)

sys/dev/ic/hme.c

1036

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

1042

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

1052

(phy << HME_MIF_FO_PHYAD_SHIFT) |

sys/dev/ic/hme.c

1082

printf("hme_mii_statchg: status change\n", phy);

sys/dev/ic/hme.c

1107

int phy = sc->sc_phys[instance];

sys/dev/ic/hme.c

1112

printf("hme_mediachange: phy = %d\n", phy);

sys/dev/ic/hme.c

1120

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

1127

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

934

int phy;

sys/dev/ic/hme.c

938

phy = HME_PHYAD_EXTERNAL;

sys/dev/ic/hme.c

940

phy = sc->sc_tcvr = HME_PHYAD_EXTERNAL;

sys/dev/ic/hme.c

942

phy = sc->sc_tcvr = HME_PHYAD_INTERNAL;

sys/dev/ic/hme.c

948

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

955

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

964

hme_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/hme.c

973

if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)

sys/dev/ic/hme.c

979

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

985

if (phy == HME_PHYAD_EXTERNAL)

sys/dev/ic/hme.c

995

(phy << HME_MIF_FO_PHYAD_SHIFT) |

sys/dev/ic/mtd8xx.c

214

mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg)

sys/dev/ic/mtd8xx.c

229

data = opcode | (phy << 7) | (reg << 2);

sys/dev/ic/mtd8xx.c

249

mtd_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/ic/mtd8xx.c

254

return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1)));

sys/dev/ic/mtd8xx.c

258

miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg);

sys/dev/ic/mtd8xx.c

278

mtd_miibus_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/mtd8xx.c

283

if (!phy)

sys/dev/ic/mtd8xx.c

288

miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg);

sys/dev/ic/mtwreg.h

791

uint16_t phy;

sys/dev/ic/mtwreg.h

870

uint16_t phy;

sys/dev/ic/mtwreg.h

961

enum ieee80211_phytype phy;

sys/dev/ic/re.c

363

re_gmii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/re.c

369

if (phy != 7)

sys/dev/ic/re.c

399

re_gmii_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/ic/re.c

422

re_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/ic/re.c

432

rval = re_gmii_readreg(dev, phy, reg);

sys/dev/ic/re.c

438

if (phy) {

sys/dev/ic/re.c

487

re_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/ic/re.c

496

re_gmii_writereg(dev, phy, reg, data);

sys/dev/ic/re.c

502

if (phy) {

sys/dev/ic/rt2860.c

1275

uint16_t phy;

sys/dev/ic/rt2860.c

1382

phy = letoh16(rxwi->phy);

sys/dev/ic/rt2860.c

1383

switch (phy & RT2860_PHY_MODE) {

sys/dev/ic/rt2860.c

1385

switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {

sys/dev/ic/rt2860.c

1391

if (phy & RT2860_PHY_SHPRE)

sys/dev/ic/rt2860.c

1395

switch (phy & RT2860_PHY_MCS) {

sys/dev/ic/rt2860.c

1590

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/ic/rt2860.c

1591

txwi->phy = htole16(RT2860_PHY_CCK);

sys/dev/ic/rt2860.c

1596

txwi->phy = htole16(RT2860_PHY_OFDM);

sys/dev/ic/rt2860.c

1597

txwi->phy |= htole16(mcs);

sys/dev/ic/rt2860.c

1613

rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))

sys/dev/ic/rt2860.c

4167

txwi.phy = htole16(rt2860_rates[ridx].mcs);

sys/dev/ic/rt2860.c

4168

if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)

sys/dev/ic/rt2860.c

4169

txwi.phy |= htole16(RT2860_PHY_OFDM);

sys/dev/ic/rt2860.c

874

rt2860_rates[rn->ridx[i]].phy ==

sys/dev/ic/rt2860.c

875

rt2860_rates[rn->ridx[j]].phy)

sys/dev/ic/rt2860reg.h

1077

enum ieee80211_phytype phy;

sys/dev/ic/rt2860reg.h

874

uint16_t phy;

sys/dev/ic/rt2860reg.h

944

uint16_t phy;

sys/dev/ic/rtl81x9.c

1240

rl_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/ic/rtl81x9.c

1251

if (phy != 0)

sys/dev/ic/rtl81x9.c

1282

frame.mii_phyaddr = phy;

sys/dev/ic/rtl81x9.c

1290

rl_miibus_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/rtl81x9.c

1297

if (phy)

sys/dev/ic/rtl81x9.c

1325

frame.mii_phyaddr = phy;

sys/dev/ic/rtwn.c

1457

struct r92c_rx_phystat *phy;

sys/dev/ic/rtwn.c

1478

phy = (struct r92c_rx_phystat *)physt;

sys/dev/ic/rtwn.c

1479

rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 110;

sys/dev/ic/rtwn.c

1488

struct r88e_rx_phystat *phy;

sys/dev/ic/rtwn.c

1492

phy = (struct r88e_rx_phystat *)physt;

sys/dev/ic/rtwn.c

1495

rpt = (phy->agc_rpt >> 5) & 0x7;

sys/dev/ic/rtwn.c

1496

rssi = (phy->agc_rpt & 0x1f) << 1;

sys/dev/ic/rtwn.c

1501

rssi = (phy->agc_rpt & 0x1f) > 27 ? -94 : cckoff[rpt] - rssi;

sys/dev/ic/rtwn.c

1503

rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110;

sys/dev/ic/rtwn.c

1511

struct r88e_rx_phystat *phy;

sys/dev/ic/rtwn.c

1515

phy = (struct r88e_rx_phystat *)physt;

sys/dev/ic/rtwn.c

1516

lna_idx = (phy->agc_rpt & 0xe0) >> 5;

sys/dev/ic/rtwn.c

1517

vga_idx = (phy->agc_rpt & 0x1f);

sys/dev/ic/rtwn.c

1542

rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110;

sys/dev/ic/smc83c170.c

1317

epic_mii_read(struct device *self, int phy, int reg)

sys/dev/ic/smc83c170.c

1325

MMCTL_ARG(phy, reg, MMCTL_READ));

sys/dev/ic/smc83c170.c

1338

epic_mii_write(struct device *self, int phy, int reg, int val)

sys/dev/ic/smc83c170.c

1347

MMCTL_ARG(phy, reg, MMCTL_WRITE));

sys/dev/ic/smc83c170reg.h

274

#define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))

sys/dev/ic/smc91cxx.c

1161

smc91cxx_mii_readreg(struct device *self, int phy, int reg)

sys/dev/ic/smc91cxx.c

1168

val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);

sys/dev/ic/smc91cxx.c

1176

smc91cxx_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/ic/smc91cxx.c

1182

mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);

sys/dev/ic/xl.c

429

xl_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/ic/xl.c

434

if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)

sys/dev/ic/xl.c

439

frame.mii_phyaddr = phy;

sys/dev/ic/xl.c

447

xl_miibus_writereg(struct device *self, int phy, int reg, int data)

sys/dev/ic/xl.c

452

if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)

sys/dev/ic/xl.c

457

frame.mii_phyaddr = phy;

sys/dev/isa/if_ef_isapnp.c

787

ef_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/isa/if_ef_isapnp.c

813

ef_mii_writeb(sc, (phy & i) ? 1 : 0);

sys/dev/isa/if_ef_isapnp.c

858

ef_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/isa/if_ef_isapnp.c

879

ef_mii_writeb(sc, (phy & i) ? 1 : 0);

sys/dev/mii/mii_bitbang.c

114

mii_bitbang_readreg(struct device *sc, mii_bitbang_ops_t ops, int phy,

sys/dev/mii/mii_bitbang.c

123

mii_bitbang_sendbits(sc, ops, phy, 5);

sys/dev/mii/mii_bitbang.c

163

int phy, int reg, int val)

sys/dev/mii/mii_bitbang.c

170

mii_bitbang_sendbits(sc, ops, phy, 5);

sys/dev/mii/ukphy_subr.c

118

mii->mii_media_active |= mii_phy_flowstatus(phy);

sys/dev/mii/ukphy_subr.c

55

ukphy_status(struct mii_softc *phy)

sys/dev/mii/ukphy_subr.c

57

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/ukphy_subr.c

64

bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);

sys/dev/mii/ukphy_subr.c

68

bmcr = PHY_READ(phy, MII_BMCR);

sys/dev/mii/ukphy_subr.c

90

anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);

sys/dev/mii/ukphy_subr.c

91

if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&

sys/dev/mii/ukphy_subr.c

92

(phy->mii_extcapabilities &

sys/dev/mii/ukphy_subr.c

94

gtcr = PHY_READ(phy, MII_100T2CR);

sys/dev/mii/ukphy_subr.c

95

gtsr = PHY_READ(phy, MII_100T2SR);

sys/dev/ofw/ofw_misc.c

256

uint32_t *phy;

sys/dev/ofw/ofw_misc.c

267

phy = phys;

sys/dev/ofw/ofw_misc.c

268

while (phy && phy < phys + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_misc.c

270

rv = phy_enable_cells(phy);

sys/dev/ofw/ofw_misc.c

273

phy = phy_next_phy(phy);

sys/dev/pci/drm/apple/dcp-internal.h

231

struct phy *phy;

sys/dev/pci/drm/apple/dcp.c

265

if (!dcp->phy) {

sys/dev/pci/drm/apple/dcp.c

282

dcp->dptxport[port].atcphy = dcp->phy;

sys/dev/pci/drm/apple/dcp.c

361

if (dcp->phy && dcp->fw_compat >= DCP_FIRMWARE_V_13_5) {

sys/dev/pci/drm/apple/dcp.c

387

} else if (dcp->phy)

sys/dev/pci/drm/apple/dcp.c

962

dcp->phy = devm_phy_optional_get(dev, "dp-phy");

sys/dev/pci/drm/apple/dcp.c

963

if (IS_ERR(dcp->phy)) {

sys/dev/pci/drm/apple/dcp.c

964

dev_err(dev, "Failed to get dp-phy: %ld\n", PTR_ERR(dcp->phy));

sys/dev/pci/drm/apple/dcp.c

965

return PTR_ERR(dcp->phy);

sys/dev/pci/drm/apple/dcp.c

967

if (dcp->phy) {

sys/dev/pci/drm/apple/dptxep.h

56

struct phy *atcphy;

sys/dev/pci/drm/drm_linux.c

3754

struct phy *

sys/dev/pci/drm/drm_linux.c

3758

struct phy *phy;

sys/dev/pci/drm/drm_linux.c

3765

phy = malloc(sizeof(*phy), M_DEVBUF, M_WAITOK);

sys/dev/pci/drm/drm_linux.c

3766

phy->node = pdev->node;

sys/dev/pci/drm/drm_linux.c

3767

phy->name = name;

sys/dev/pci/drm/drm_linux.c

3769

return phy;

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

106

#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

112

#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

118

#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

125

#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

130

#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

137

#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

144

#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

15

#define BXT_PHY_BASE(phy) \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

156

#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

16

_PICK_EVEN_2RANGES(phy, 1, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

162

#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

171

#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

174

#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

192

#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

195

#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

198

#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

20

#define _BXT_PHY(phy, reg) \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

209

#define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

21

_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

212

#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

226

#define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

229

#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

23

#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

24

(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

241

#define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

244

#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

256

#define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

259

#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

26

#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

269

#define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

27

_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

30

#define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

31

_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

51

#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

60

#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

95

#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

98

#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \

sys/dev/pci/drm/i915/display/icl_dsi.c

254

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

258

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

266

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

269

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

270

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

276

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

279

intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

280

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

286

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

290

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

433

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

435

for_each_dsi_phy(phy, intel_dsi->phys)

sys/dev/pci/drm/i915/display/icl_dsi.c

436

intel_combo_phy_power_up_lanes(display, phy, true,

sys/dev/pci/drm/i915/display/icl_dsi.c

444

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

449

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

450

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

453

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

458

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

459

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

461

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

464

intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

469

intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

473

ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

476

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

488

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

491

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

492

tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

494

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

495

intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

503

for_each_dsi_phy(phy, intel_dsi->phys)

sys/dev/pci/drm/i915/display/icl_dsi.c

504

intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,

sys/dev/pci/drm/i915/display/icl_dsi.c

508

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

509

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

511

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

512

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

519

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

520

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

522

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

523

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);

sys/dev/pci/drm/i915/display/icl_dsi.c

553

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

581

for_each_dsi_phy(phy, intel_dsi->phys)

sys/dev/pci/drm/i915/display/icl_dsi.c

582

intel_de_rmw(display, ICL_DPHY_CHKN(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

627

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

631

for_each_dsi_phy(phy, intel_dsi->phys)

sys/dev/pci/drm/i915/display/icl_dsi.c

632

tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

sys/dev/pci/drm/i915/display/icl_dsi.c

643

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

647

for_each_dsi_phy(phy, intel_dsi->phys)

sys/dev/pci/drm/i915/display/icl_dsi.c

648

tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

sys/dev/pci/drm/i915/display/icl_dsi.c

659

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

664

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

665

if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))

sys/dev/pci/drm/i915/display/icl_dsi.c

678

enum phy phy;

sys/dev/pci/drm/i915/display/icl_dsi.c

684

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

685

val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

sys/dev/pci/drm/i915/display/icl_dsi.c

686

val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);

sys/dev/pci/drm/i915/display/icl_dsi.c

690

for_each_dsi_phy(phy, intel_dsi->phys) {

sys/dev/pci/drm/i915/display/icl_dsi.c

691

val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

sys/dev/pci/drm/i915/display/intel_bios.c

2945

enum phy phy = intel_port_to_phy(display, port);

sys/dev/pci/drm/i915/display/intel_bios.c

2951

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

104

phy_name(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

113

enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

118

procmon = icl_get_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

120

ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

122

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

124

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

130

static bool has_phy_misc(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

142

return phy == PHY_A;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

146

return phy < PHY_C;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

152

enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

155

if (!has_phy_misc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

156

return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

158

return !(intel_de_read(display, ICL_PHY_MISC(phy)) &

sys/dev/pci/drm/i915/display/intel_combo_phy.c

160

(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

190

static bool phy_is_master(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

208

if (phy == PHY_A)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

211

return phy == PHY_D;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

213

return phy == PHY_C;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

219

enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

224

if (!icl_combo_phy_enabled(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

228

ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

234

ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

238

ret &= icl_verify_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

240

if (phy_is_master(display, phy)) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

241

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

248

ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

254

ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

261

enum phy phy, bool is_dsi,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

305

intel_de_rmw(display, ICL_PORT_CL_DW10(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

311

enum phy phy;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

313

for_each_combo_phy(display, phy) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

317

if (icl_combo_phy_verify_state(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

320

procmon = icl_get_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

324

phy_name(phy), procmon->name);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

326

if (!has_phy_misc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

337

val = intel_de_read(display, ICL_PHY_MISC(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

339

phy == PHY_A) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

347

intel_de_write(display, ICL_PHY_MISC(phy), val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

351

val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

355

intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

357

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

360

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

363

icl_set_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

365

if (phy_is_master(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

366

intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

369

intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

370

intel_de_rmw(display, ICL_PORT_CL_DW5(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

377

enum phy phy;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

379

for_each_combo_phy_reverse(display, phy) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

380

if (phy == PHY_A &&

sys/dev/pci/drm/i915/display/intel_combo_phy.c

381

!icl_combo_phy_verify_state(display, phy)) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

390

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

394

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

398

if (!has_phy_misc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

401

intel_de_rmw(display, ICL_PHY_MISC(phy), 0,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

405

intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

58

icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

62

val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

81

enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

85

procmon = icl_get_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

87

intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

90

intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

91

intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

95

enum phy phy, i915_reg_t reg, u32 mask,

sys/dev/pci/drm/i915/display/intel_combo_phy.h

11

enum phy;

sys/dev/pci/drm/i915/display/intel_combo_phy.h

17

enum phy phy, bool is_dsi,

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

100

#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

102

#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

104

#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

107

#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

108

#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

109

#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

119

#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

120

#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

121

#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

130

#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

131

#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

132

#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

143

#define ICL_PORT_TX_DW6_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(6, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

144

#define ICL_PORT_TX_DW6_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(6, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

145

#define ICL_PORT_TX_DW6_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(6, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

150

#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

151

#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

152

#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

156

#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

157

#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

158

#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

17

#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

24

#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

27

#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

31

#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

46

#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

51

#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

54

#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

57

#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

59

#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

69

#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

72

#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

74

#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

80

#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

82

#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

84

#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

86

#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

87

#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

88

#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

145

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

155

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

167

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

177

phy_name(phy), *val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

183

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

192

phy_name(phy),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

201

phy_name(phy),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

215

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

223

"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

254

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

269

phy_name(phy), addr, i);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2824

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2839

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2853

phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

287

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2898

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2915

phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2925

phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2937

phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

295

"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2950

phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3024

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3090

phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

311

"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3175

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3215

encoder->base.base.id, encoder->base.name, phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

323

"PHY %c Error occurred during write command.\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3298

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3330

phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3359

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3377

encoder->base.base.id, encoder->base.name, phy_name(phy));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

345

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

359

"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

40

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

44

return phy <= PHY_B;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

46

return phy == PHY_A;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

49

if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)

sys/dev/pci/drm/i915/display/intel_ddi.c

1042

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1049

val = TGL_TRANS_CLK_SEL_PORT(phy);

sys/dev/pci/drm/i915/display/intel_ddi.c

1171

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1184

intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val,

sys/dev/pci/drm/i915/display/intel_ddi.c

1189

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1196

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1202

intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1214

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1225

intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1235

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1244

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1249

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1259

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1265

intel_de_rmw(display, ICL_PORT_CL_DW5(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1269

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1271

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1277

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1279

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1600

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1605

_icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1606

ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1607

pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1608

ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1614

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1616

_icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1617

ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1623

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1625

return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1626

ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1632

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1634

return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1635

ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1636

ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1644

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1650

RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1651

RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1652

RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1658

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1661

RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1667

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1670

RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1676

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1679

RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1680

RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1688

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1698

(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||

sys/dev/pci/drm/i915/display/intel_ddi.c

1699

(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))

sys/dev/pci/drm/i915/display/intel_ddi.c

1702

_icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1703

DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1704

DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1705

DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1711

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1713

_icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1714

DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1720

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1722

return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1723

DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1729

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1733

val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1734

val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

sys/dev/pci/drm/i915/display/intel_ddi.c

1735

val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);

sys/dev/pci/drm/i915/display/intel_ddi.c

1743

if (phy >= PHY_C)

sys/dev/pci/drm/i915/display/intel_ddi.c

1754

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1760

ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1761

ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1762

ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1768

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1771

ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1777

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1780

ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1786

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1789

ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1790

ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

2466

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2468

intel_combo_phy_power_up_lanes(display, phy, false,

sys/dev/pci/drm/i915/display/intel_ddi.c

5073

enum port port, enum phy phy,

sys/dev/pci/drm/i915/display/intel_ddi.c

5079

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

5087

tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

5095

tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

5097

seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

5113

enum phy phy;

sys/dev/pci/drm/i915/display/intel_ddi.c

5144

phy = intel_port_to_phy(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5152

if (intel_hti_uses_phy(display, phy)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5154

port_name(port), phy_name(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

5181

if (intel_phy_is_snps(display, phy) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

5182

display->snps.phy_failed_calibration & BIT(phy)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5185

phy_name(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

5197

intel_ddi_encoder_name(display, port, phy, &encoder_name));

sys/dev/pci/drm/i915/display/intel_display.c

1819

bool intel_phy_is_combo(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_display.c

1821

if (phy == PHY_NONE)

sys/dev/pci/drm/i915/display/intel_display.c

1824

return phy <= PHY_E;

sys/dev/pci/drm/i915/display/intel_display.c

1826

return phy <= PHY_D;

sys/dev/pci/drm/i915/display/intel_display.c

1828

return phy <= PHY_C;

sys/dev/pci/drm/i915/display/intel_display.c

1830

return phy <= PHY_B;

sys/dev/pci/drm/i915/display/intel_display.c

1841

bool intel_phy_is_tc(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_display.c

1851

return phy >= PHY_F && phy <= PHY_I;

sys/dev/pci/drm/i915/display/intel_display.c

1853

return phy >= PHY_D && phy <= PHY_I;

sys/dev/pci/drm/i915/display/intel_display.c

1855

return phy >= PHY_C && phy <= PHY_F;

sys/dev/pci/drm/i915/display/intel_display.c

1861

bool intel_phy_is_snps(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_display.c

1867

return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;

sys/dev/pci/drm/i915/display/intel_display.c

1871

enum phy intel_port_to_phy(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display.c

1900

enum phy intel_encoder_to_phy(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_display.h

412

enum phy intel_port_to_phy(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_display.h

449

bool intel_phy_is_combo(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_display.h

450

bool intel_phy_is_tc(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_display.h

451

bool intel_phy_is_snps(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_display.h

454

enum phy intel_encoder_to_phy(struct intel_encoder *encoder);

sys/dev/pci/drm/i915/display/intel_display_power_map.c

478

.bxt.phy = DPIO_PHY1,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

481

.bxt.phy = DPIO_PHY0,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

581

.bxt.phy = DPIO_PHY1,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

584

.bxt.phy = DPIO_PHY0,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

587

.bxt.phy = DPIO_PHY2,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1464

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1472

phy = DPIO_PHY0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1474

phy = DPIO_PHY1;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1482

PHY_POWERGOOD(phy), 1))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1484

phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1489

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1492

vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1495

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1497

vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1504

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1506

vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1511

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1517

phy, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1526

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1533

phy = DPIO_PHY0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1537

phy = DPIO_PHY1;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1541

display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1549

phy, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1552

display->power.chv_phy_assert[phy] = true;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1557

static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1569

if (!display->power.chv_phy_assert[phy])

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1578

val = vlv_dpio_read(display->drm, phy, reg);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1621

bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1629

was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1635

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1637

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1644

phy, ch, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1659

enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1664

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1665

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1668

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1670

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1677

phy, ch, mask, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1681

assert_chv_phy_powergate(display, phy, ch, override, mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1855

enum phy phy = icl_aux_pw_to_phy(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1857

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

259

static enum phy icl_aux_pw_to_phy(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

571

enum phy phy = icl_aux_pw_to_phy(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

573

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

586

enum phy phy = icl_aux_pw_to_phy(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

588

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

948

bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

954

bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

960

return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

969

bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

973

bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

980

i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

154

bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

75

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

23

#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

30

#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))

sys/dev/pci/drm/i915/display/intel_display_regs.h

167

#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))

sys/dev/pci/drm/i915/display/intel_display_regs.h

171

#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))

sys/dev/pci/drm/i915/display/intel_display_regs.h

172

#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))

sys/dev/pci/drm/i915/display/intel_display_regs.h

175

#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))

sys/dev/pci/drm/i915/display/intel_display_regs.h

176

#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

178

#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))

sys/dev/pci/drm/i915/display/intel_display_regs.h

179

#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))

sys/dev/pci/drm/i915/display/intel_display_regs.h

180

#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2595

#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2596

#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2600

#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2601

#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2602

#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2603

#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2604

#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2605

(3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2606

#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2607

((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2617

#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2619

#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2622

#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2623

#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2624

#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2625

#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2630

#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2633

#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2641

#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

35

#define BXT_PHY_CTL_FAMILY(phy) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

36

_MMIO(_PICK_EVEN_2RANGES(phy, 1, \

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1001

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1004

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1012

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1041

enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1049

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1051

vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1053

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1055

vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1080

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1084

vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1085

vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1086

vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1088

vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1091

vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1093

vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1094

vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1095

vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1106

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1111

vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1114

vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1121

vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1122

vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1123

vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1136

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1147

vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1150

vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1151

vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1162

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1165

vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1166

vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

237

bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

243

return &phy_list[phy];

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

247

enum dpio_phy *phy, enum dpio_channel *ch)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

258

*phy = i;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

265

*phy = i;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

273

*phy = DPIO_PHY0;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

301

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

308

bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

314

bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

315

BXT_PORT_PCS_DW10_GRP(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

321

intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

331

intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

336

val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

345

intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

350

bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

351

BXT_PORT_PCS_DW10_GRP(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

356

enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

360

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

365

if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

368

"DDI PHY %d powered, but power hasn't settled\n", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

373

if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

375

"DDI PHY %d powered, but still in reset\n", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

383

static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

385

u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

391

enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

393

if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

394

drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

397

static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

402

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

404

if (bxt_dpio_phy_is_enabled(display, phy)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

407

display->state.bxt_phy_grc = bxt_get_grc(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

409

if (bxt_dpio_phy_verify_state(display, phy)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

411

"won't reprogram it\n", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

417

"force reprogramming it\n", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

430

if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

433

phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

436

intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

439

intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

443

intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

447

intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

466

intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

467

intel_de_rmw(display, BXT_PORT_REF_DW8(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

474

intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

477

void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

481

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

483

intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

488

void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

490

const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

507

_bxt_dpio_phy_init(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

514

__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

532

phy, &vaf, reg.reg, val, (val & ~mask) | expected,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

541

enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

547

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

550

__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

553

if (!bxt_dpio_phy_is_enabled(display, phy))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

559

ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

561

"BXT_PORT_CL1CM_DW9(%d)", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

562

ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

564

"BXT_PORT_CL1CM_DW10(%d)", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

568

ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

569

"BXT_PORT_CL1CM_DW28(%d)", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

572

ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

574

"BXT_PORT_CL2CM_DW6(%d)", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

584

ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

585

"BXT_PORT_REF_DW6(%d)", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

588

ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

589

"BXT_PORT_REF_DW8(%d)", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

618

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

622

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

629

intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

640

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

645

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

650

BXT_PORT_TX_DW14_LN(phy, ch, lane));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

723

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

730

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

734

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

737

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

741

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

744

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

747

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

750

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

753

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

758

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

761

vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

766

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

779

vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

789

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

794

vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

798

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

800

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

803

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

805

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

818

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

821

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

826

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

829

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

834

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

837

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

843

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

846

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

852

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

874

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

897

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

903

vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

905

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

911

vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

915

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

921

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

924

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

930

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

938

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

943

vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

955

enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

962

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

964

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

967

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

969

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

979

vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

994

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

996

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

999

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

31

enum dpio_phy *phy, enum dpio_channel *ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

34

void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

35

void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

37

enum dpio_phy phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

39

enum dpio_phy phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

79

enum dpio_phy *phy, enum dpio_channel *ch)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

86

static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

89

static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

93

enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

98

enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpll.c

1873

enum dpio_phy phy, enum dpio_channel ch)

sys/dev/pci/drm/i915/display/intel_dpll.c

1881

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1884

vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1886

tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);

sys/dev/pci/drm/i915/display/intel_dpll.c

1889

vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1891

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1893

vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1895

tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);

sys/dev/pci/drm/i915/display/intel_dpll.c

1898

vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1907

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1917

vlv_pllb_recal_opamp(display, phy, ch);

sys/dev/pci/drm/i915/display/intel_dpll.c

1920

vlv_dpio_write(display->drm, phy, VLV_PCS_DW17_BCAST, 0x0100000f);

sys/dev/pci/drm/i915/display/intel_dpll.c

1923

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW16(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1925

vlv_dpio_write(display->drm, phy, VLV_PLL_DW16(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1928

vlv_dpio_write(display->drm, phy, VLV_CMN_DW0, 0x610);

sys/dev/pci/drm/i915/display/intel_dpll.c

1944

vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1947

vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1953

vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x009f0003);

sys/dev/pci/drm/i915/display/intel_dpll.c

1955

vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x00d0000f);

sys/dev/pci/drm/i915/display/intel_dpll.c

1960

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1962

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1966

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1968

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1971

coreclk = vlv_dpio_read(display->drm, phy, VLV_PLL_DW7(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1975

vlv_dpio_write(display->drm, phy, VLV_PLL_DW7(ch), coreclk);

sys/dev/pci/drm/i915/display/intel_dpll.c

1977

vlv_dpio_write(display->drm, phy, VLV_PLL_DW19(ch), 0x87871000);

sys/dev/pci/drm/i915/display/intel_dpll.c

2028

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2037

vlv_dpio_write(display->drm, phy, CHV_CMN_DW13(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2044

vlv_dpio_write(display->drm, phy, CHV_PLL_DW0(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2048

vlv_dpio_write(display->drm, phy, CHV_PLL_DW1(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2053

vlv_dpio_write(display->drm, phy, CHV_PLL_DW2(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2057

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2062

vlv_dpio_write(display->drm, phy, CHV_PLL_DW3(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2065

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW9(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2071

vlv_dpio_write(display->drm, phy, CHV_PLL_DW9(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2096

vlv_dpio_write(display->drm, phy, CHV_PLL_DW6(ch), loopfilter);

sys/dev/pci/drm/i915/display/intel_dpll.c

2098

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW8(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2101

vlv_dpio_write(display->drm, phy, CHV_PLL_DW8(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2104

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2105

vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)) |

sys/dev/pci/drm/i915/display/intel_dpll.c

2117

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2124

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2126

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2248

enum dpio_phy phy = vlv_pipe_to_phy(pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2265

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2267

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), val);

sys/dev/pci/drm/i915/display/intel_dpll.c

520

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

531

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW3(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

548

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

559

cmn_dw13 = vlv_dpio_read(display->drm, phy, CHV_CMN_DW13(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

560

pll_dw0 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW0(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

561

pll_dw1 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW1(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

562

pll_dw2 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW2(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

563

pll_dw3 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2046

enum dpio_phy phy = DPIO_PHY0;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2051

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2069

intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2073

intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2077

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2081

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2085

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2089

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2093

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2098

intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2101

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2104

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2107

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2111

intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2114

temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2116

intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2119

intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2132

temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2134

intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2141

temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2145

intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2177

enum dpio_phy phy;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2182

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2195

hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2198

hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2201

hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2204

hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2207

hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2210

hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2213

hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2218

hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2221

hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2224

hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2234

BXT_PORT_PCS_DW12_LN01(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2235

if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2240

BXT_PORT_PCS_DW12_LN23(phy, ch)));

sys/dev/pci/drm/i915/display/intel_hdmi.c

2809

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2812

switch (phy) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

2823

MISSING_CASE(phy);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2833

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2843

if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2844

return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2846

return GMBUS_PIN_1_BXT + phy;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2852

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2862

if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2863

return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2865

return GMBUS_PIN_1_BXT + phy;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2875

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2883

if (phy == PHY_A)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2886

return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;

sys/dev/pci/drm/i915/display/intel_hti.c

24

bool intel_hti_uses_phy(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_hti.c

26

if (drm_WARN_ON(display->drm, phy == PHY_NONE))

sys/dev/pci/drm/i915/display/intel_hti.c

30

display->hti.state & HDPORT_DDI_USED(phy);

sys/dev/pci/drm/i915/display/intel_hti.h

12

enum phy;

sys/dev/pci/drm/i915/display/intel_hti.h

15

bool intel_hti_uses_phy(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_hti_regs.h

13

#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

150

enum phy phy;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

161

phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

164

pmdemand_state->active_combo_phys_mask |= BIT(phy);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

166

pmdemand_state->active_combo_phys_mask &= ~BIT(phy);

sys/dev/pci/drm/i915/display/intel_pps.c

101

enum dpio_phy phy = vlv_pipe_to_phy(pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

138

!chv_phy_powergate_ch(display, phy, ch, true);

sys/dev/pci/drm/i915/display/intel_pps.c

167

chv_phy_powergate_ch(display, phy, ch, false);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1824

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1825

i915_reg_t enable_reg = (phy <= PHY_D ?

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1826

DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1832

intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1833

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1834

intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1835

intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1836

intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1837

intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1838

intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1858

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1867

drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1881

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1882

i915_reg_t enable_reg = (phy <= PHY_D ?

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1883

DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1900

intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1907

drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1953

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1955

pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1956

pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1957

pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1958

pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1959

pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1960

pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1961

pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1969

pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &

sys/dev/pci/drm/i915/display/intel_snps_phy.c

34

enum phy phy;

sys/dev/pci/drm/i915/display/intel_snps_phy.c

36

for_each_phy_masked(phy, ~0) {

sys/dev/pci/drm/i915/display/intel_snps_phy.c

37

if (!intel_phy_is_snps(display, phy))

sys/dev/pci/drm/i915/display/intel_snps_phy.c

45

if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

47

display->snps.phy_failed_calibration |= BIT(phy);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

55

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

63

intel_de_rmw(display, SNPS_PHY_TX_REQ(phy),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

72

enum phy phy = intel_encoder_to_phy(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

87

intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val);

sys/dev/pci/drm/i915/display/intel_snps_phy.h

11

enum phy;

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

13

#define _SNPS_PHY(phy) _PHY(phy, \

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

16

#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

18

#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

19

#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

22

#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

28

#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

41

#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

46

#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

50

#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

55

#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

58

#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

64

#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

67

#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

70

#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)

sys/dev/pci/drm/i915/display/vlv_sideband.c

12

enum dpio_phy phy)

sys/dev/pci/drm/i915/display/vlv_sideband.c

19

return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO;

sys/dev/pci/drm/i915/display/vlv_sideband.c

24

u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg)

sys/dev/pci/drm/i915/display/vlv_sideband.c

27

enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);

sys/dev/pci/drm/i915/display/vlv_sideband.c

38

phy, reg, val);

sys/dev/pci/drm/i915/display/vlv_sideband.c

44

enum dpio_phy phy, int reg, u32 val)

sys/dev/pci/drm/i915/display/vlv_sideband.c

47

enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);

sys/dev/pci/drm/i915/display/vlv_sideband.h

82

u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg);

sys/dev/pci/drm/i915/display/vlv_sideband.h

84

enum dpio_phy phy, int reg, u32 val);

sys/dev/pci/drm/i915/display/vlv_sideband.h

86

static inline u32 vlv_dpio_read(struct drm_device *drm, int phy, int reg)

sys/dev/pci/drm/i915/display/vlv_sideband.h

91

int phy, int reg, u32 val)

sys/dev/pci/drm/i915/gvt/handlers.c

553

enum dpio_phy phy = DPIO_PHY0;

sys/dev/pci/drm/i915/gvt/handlers.c

561

phy = DPIO_PHY1;

sys/dev/pci/drm/i915/gvt/handlers.c

565

phy = DPIO_PHY0;

sys/dev/pci/drm/i915/gvt/handlers.c

569

phy = DPIO_PHY0;

sys/dev/pci/drm/i915/gvt/handlers.c

586

vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;

sys/dev/pci/drm/i915/gvt/handlers.c

587

if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)

sys/dev/pci/drm/i915/gvt/handlers.c

589

vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));

sys/dev/pci/drm/i915/gvt/handlers.c

591

vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));

sys/dev/pci/drm/i915/gvt/handlers.c

593

vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));

sys/dev/pci/drm/i915/gvt/handlers.c

595

vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));

sys/dev/pci/drm/include/linux/phy/phy.h

23

struct phy;

sys/dev/pci/drm/include/linux/phy/phy.h

25

struct phy *devm_phy_optional_get(struct device *, const char *);

sys/dev/pci/drm/include/linux/phy/phy.h

28

phy_configure(struct phy *phy, union phy_configure_opts *opts)

sys/dev/pci/drm/include/linux/phy/phy.h

34

phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)

sys/dev/pci/if_age.c

303

age_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_age.c

309

if (phy != sc->age_phyaddr)

sys/dev/pci/if_age.c

323

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_age.c

334

age_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_age.c

340

if (phy != sc->age_phyaddr)

sys/dev/pci/if_age.c

356

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_alc.c

165

alc_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_alc.c

170

if (phy != sc->alc_phyaddr)

sys/dev/pci/if_alc.c

174

v = alc_mii_readreg_816x(dev, phy, reg);

sys/dev/pci/if_alc.c

176

v = alc_mii_readreg_813x(dev, phy, reg);

sys/dev/pci/if_alc.c

182

alc_mii_readreg_813x(struct device *dev, int phy, int reg)

sys/dev/pci/if_alc.c

209

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_alc.c

217

alc_mii_readreg_816x(struct device *dev, int phy, int reg)

sys/dev/pci/if_alc.c

238

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_alc.c

246

alc_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_alc.c

250

if (phy != sc->alc_phyaddr)

sys/dev/pci/if_alc.c

254

alc_mii_writereg_816x(dev, phy, reg, val);

sys/dev/pci/if_alc.c

256

alc_mii_writereg_813x(dev, phy, reg, val);

sys/dev/pci/if_alc.c

260

alc_mii_writereg_813x(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_alc.c

278

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_alc.c

282

alc_mii_writereg_816x(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_alc.c

304

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_ale.c

129

ale_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_ale.c

135

if (phy != sc->ale_phyaddr)

sys/dev/pci/if_ale.c

153

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_ale.c

161

ale_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_ale.c

167

if (phy != sc->ale_phyaddr)

sys/dev/pci/if_ale.c

182

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_bce.c

1201

bce_mii_read(struct device *self, int phy, int reg)

sys/dev/pci/if_bce.c

1214

(MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */

sys/dev/pci/if_bce.c

1226

"0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);

sys/dev/pci/if_bce.c

1234

bce_mii_write(struct device *self, int phy, int reg, int val)

sys/dev/pci/if_bce.c

1248

BCE_MIPHY(phy) | BCE_MIREG(reg));

sys/dev/pci/if_bce.c

1261

"= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);

sys/dev/pci/if_bge.c

1004

bge_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_bge.c

1022

BGE_MIPHY(phy)|BGE_MIREG(reg));

sys/dev/pci/if_bge.c

1057

bge_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_bge.c

1080

BGE_MIPHY(phy)|BGE_MIREG(reg)|val);

sys/dev/pci/if_bnx.c

1090

bnx_miibus_read_reg(struct device *dev, int phy, int reg)

sys/dev/pci/if_bnx.c

1116

val = BNX_MIPHY(phy) | BNX_MIREG(reg) |

sys/dev/pci/if_bnx.c

1137

"reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);

sys/dev/pci/if_bnx.c

1143

"%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __FUNCTION__, phy,

sys/dev/pci/if_bnx.c

1168

bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_bnx.c

1176

phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);

sys/dev/pci/if_bnx.c

1198

val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |

sys/dev/pci/if_cas.c

1430

cas_mii_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_cas.c

1440

printf("cas_mii_readreg: phy %d reg %d\n", phy, reg);

sys/dev/pci/if_cas.c

1444

v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) |

sys/dev/pci/if_cas.c

1460

cas_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/pci/if_cas.c

1471

phy, reg, val);

sys/dev/pci/if_cas.c

1476

(phy << CAS_MIF_PHY_SHIFT) |

sys/dev/pci/if_cas.c

1542

cas_pcs_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_cas.c

1550

printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg);

sys/dev/pci/if_cas.c

1553

if (phy != CAS_PHYAD_EXTERNAL)

sys/dev/pci/if_cas.c

1579

cas_pcs_writereg(struct device *self, int phy, int reg, int val)

sys/dev/pci/if_cas.c

1589

phy, reg, val);

sys/dev/pci/if_cas.c

1592

if (phy != CAS_PHYAD_EXTERNAL)

sys/dev/pci/if_em_soc.c

111

data |= (phy << MDIO_COMMAND_PHY_ADDR_OFFSET);

sys/dev/pci/if_em_soc.c

128

DEVNAME(sc), phy, reg);

sys/dev/pci/if_em_soc.c

49

gcu_miibus_readreg(struct em_hw *hw, int phy, int reg)

sys/dev/pci/if_em_soc.c

63

data |= (phy << MDIO_COMMAND_PHY_ADDR_OFFSET);

sys/dev/pci/if_em_soc.c

80

DEVNAME(sc), phy, reg);

sys/dev/pci/if_em_soc.c

90

DEVNAME(sc), phy, reg);

sys/dev/pci/if_em_soc.c

97

gcu_miibus_writereg(struct em_hw *hw, int phy, int reg, int val)

sys/dev/pci/if_et.c

306

et_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_et.c

315

val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |

sys/dev/pci/if_et.c

332

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_et.c

349

et_miibus_writereg(struct device *dev, int phy, int reg, int val0)

sys/dev/pci/if_et.c

358

val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |

sys/dev/pci/if_et.c

375

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_et.c

376

et_miibus_readreg(dev, phy, reg);

sys/dev/pci/if_ice.c

12342

link_speeds = pi->phy.curr_user_speed_req;

sys/dev/pci/if_ice.c

12426

pi->phy.curr_user_speed_req = phy_data.user_speeds_intr;

sys/dev/pci/if_ice.c

12712

status = ice_cfg_phy_fec(pi, cfg, pi->phy.curr_user_fec_req);

sys/dev/pci/if_ice.c

12735

switch (pi->phy.curr_user_fc_req) {

sys/dev/pci/if_ice.c

12859

pi->phy.curr_user_phy_cfg = *cfg;

sys/dev/pci/if_ice.c

12920

pi->phy.curr_user_speed_req = dflt_user_speed;

sys/dev/pci/if_ice.c

12926

pi->phy.curr_user_fec_req = dflt_fec_mode;

sys/dev/pci/if_ice.c

12992

pi->phy.curr_user_phy_cfg.caps |= ICE_AQC_PHY_EN_LINK;

sys/dev/pci/if_ice.c

12994

pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK;

sys/dev/pci/if_ice.c

13694

struct ice_link_status *li = &pi->phy.link_info;

sys/dev/pci/if_ice.c

14393

struct ice_link_status *li = &sc->hw.port_info->phy.link_info;

sys/dev/pci/if_ice.c

18265

vsi->max_frame_size = hw->port_info->phy.link_info.max_frame_size;

sys/dev/pci/if_ice.c

23409

li = &pi->phy.link_info;

sys/dev/pci/if_ice.c

23456

phy_info = &pi->phy;

sys/dev/pci/if_ice.c

24067

switch (pi->phy.link_info.link_speed) {

sys/dev/pci/if_ice.c

24123

if (!(hw->port_info->phy.link_info_old.link_info &

sys/dev/pci/if_ice.c

26561

sc->hw.port_info->phy.get_link_info = true;

sys/dev/pci/if_ice.c

26933

pi->phy.get_link_info = true;

sys/dev/pci/if_ice.c

26936

if (pi->phy.link_info.topo_media_conflict &

sys/dev/pci/if_ice.c

26943

if ((pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) &&

sys/dev/pci/if_ice.c

26944

!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) {

sys/dev/pci/if_ice.c

26945

if (!(pi->phy.link_info.an_info & ICE_AQ_QUALIFIED_MODULE))

sys/dev/pci/if_ice.c

26950

if (pi->phy.link_info.link_cfg_err &

sys/dev/pci/if_ice.c

26955

if (pi->phy.link_info.link_cfg_err &

sys/dev/pci/if_ice.c

26962

if (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE)) {

sys/dev/pci/if_ice.c

28577

pi->phy.get_link_info = true;

sys/dev/pci/if_ice.c

28580

if (pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {

sys/dev/pci/if_ice.c

29782

return hw->port_info->phy.link_info.max_frame_size -

sys/dev/pci/if_ice.c

30344

pi->phy.curr_user_speed_req =

sys/dev/pci/if_ice.c

30346

pi->phy.curr_user_fec_req = ice_caps_to_fec_mode(pcaps.caps,

sys/dev/pci/if_ice.c

30348

pi->phy.curr_user_fc_req = ice_caps_to_fc_mode(pcaps.caps);

sys/dev/pci/if_ice.c

30450

pi->phy.get_link_info = true;

sys/dev/pci/if_ice.c

30459

if (pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {

sys/dev/pci/if_ice.c

6644

phy_type_high = pi->phy.phy_type_high;

sys/dev/pci/if_ice.c

6645

phy_type_low = pi->phy.phy_type_low;

sys/dev/pci/if_ice.c

6646

media_type = &pi->phy.media_type;

sys/dev/pci/if_ice.c

6649

if (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE))

sys/dev/pci/if_ice.c

6773

pi->phy.phy_type_low = le64toh(pcaps->phy_type_low);

sys/dev/pci/if_ice.c

6774

pi->phy.phy_type_high = le64toh(pcaps->phy_type_high);

sys/dev/pci/if_ice.c

6775

memcpy(pi->phy.link_info.module_type, &pcaps->module_type,

sys/dev/pci/if_ice.c

6776

sizeof(pi->phy.link_info.module_type));

sys/dev/pci/if_ice.c

6779

pi->phy.media_type);

sys/dev/pci/if_ice.c

6812

li_old = &pi->phy.link_info_old;

sys/dev/pci/if_ice.c

6813

li = &pi->phy.link_info;

sys/dev/pci/if_ice.c

6879

pi->phy.get_link_info = false;

sys/dev/pci/if_icevar.h

2449

struct ice_phy_info phy;

sys/dev/pci/if_igc.c

1553

sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;

sys/dev/pci/if_igc.c

1556

sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;

sys/dev/pci/if_igc.c

1559

sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;

sys/dev/pci/if_igc.c

1563

sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;

sys/dev/pci/if_igc.c

1565

sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;

sys/dev/pci/if_igc.c

1569

sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;

sys/dev/pci/if_igc.c

1571

sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;

sys/dev/pci/if_igc.c

225

hw->phy.autoneg_wait_to_complete = false;

sys/dev/pci/if_igc.c

226

hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;

sys/dev/pci/if_igc.c

229

if (hw->phy.media_type == igc_media_type_copper)

sys/dev/pci/if_igc.c

230

hw->phy.mdix = AUTO_ALL_MODES;

sys/dev/pci/if_iwm.c

6078

cmd.phy = htole32(IWM_FW_CMD_ID_AND_COLOR(phyctxt->id, phyctxt->color));

sys/dev/pci/if_iwmreg.h

2951

uint32_t phy;

sys/dev/pci/if_iwmreg.h

2969

uint32_t phy;

sys/dev/pci/if_iwn.c

4289

struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;

sys/dev/pci/if_iwn.c

4293

mask = (letoh16(phy->antenna) >> 4) & IWN_ANT_ABC;

sys/dev/pci/if_iwn.c

4294

agc = (letoh16(phy->agc) >> 7) & 0x7f;

sys/dev/pci/if_iwn.c

4298

rssi = MAX(rssi, phy->rssi[0]);

sys/dev/pci/if_iwn.c

4300

rssi = MAX(rssi, phy->rssi[2]);

sys/dev/pci/if_iwn.c

4302

rssi = MAX(rssi, phy->rssi[4]);

sys/dev/pci/if_iwn.c

4310

struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;

sys/dev/pci/if_iwn.c

4314

agc = (letoh32(phy->agc) >> 9) & 0x7f;

sys/dev/pci/if_iwn.c

4316

rssi = MAX(letoh16(phy->rssi[0]) & 0xff,

sys/dev/pci/if_iwn.c

4317

letoh16(phy->rssi[1]) & 0xff);

sys/dev/pci/if_iwn.c

4318

rssi = MAX(letoh16(phy->rssi[2]) & 0xff, rssi);

sys/dev/pci/if_iwx.c

5585

cmd.phy = htole32(IWX_FW_CMD_ID_AND_COLOR(phyctxt->id, phyctxt->color));

sys/dev/pci/if_iwxreg.h

3343

uint32_t phy;

sys/dev/pci/if_ix.c

1208

} else if ((hw->phy.media_type != ixgbe_media_type_copper) &&

sys/dev/pci/if_ix.c

1387

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/pci/if_ix.c

1720

sc->hw.phy.smart_speed = ixgbe_smart_speed;

sys/dev/pci/if_ix.c

2014

if (hw->phy.multispeed_fiber)

sys/dev/pci/if_ix.c

2020

if (hw->phy.multispeed_fiber)

sys/dev/pci/if_ix.c

2052

if (sc->hw.phy.multispeed_fiber) {

sys/dev/pci/if_ix.c

2065

autoneg = sc->hw.phy.autoneg_advertised;

sys/dev/pci/if_ix.c

327

if (hw->phy.ops.set_phy_power)

sys/dev/pci/if_ix.c

328

hw->phy.ops.set_phy_power(&sc->hw, TRUE);

sys/dev/pci/if_ix.c

3638

err = hw->phy.ops.identify_sfp(hw);

sys/dev/pci/if_ix.c

3665

autoneg = hw->phy.autoneg_advertised;

sys/dev/pci/if_ix.c

3687

error = hw->phy.ops.handle_lasi(hw);

sys/dev/pci/if_ix.c

420

if (hw->phy.ops.set_phy_power)

sys/dev/pci/if_ix.c

421

hw->phy.ops.set_phy_power(&sc->hw, TRUE);

sys/dev/pci/if_ix.c

609

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/if_ix.c

614

if (hw->phy.type == ixgbe_phy_fw)

sys/dev/pci/if_ix.c

621

if (hw->phy.ops.read_i2c_byte_unlocked(hw, 127,

sys/dev/pci/if_ix.c

625

hw->phy.ops.write_i2c_byte_unlocked(hw, 127,

sys/dev/pci/if_ix.c

631

if (hw->phy.ops.read_i2c_byte_unlocked(hw, i,

sys/dev/pci/if_ix.c

638

hw->phy.ops.write_i2c_byte_unlocked(hw, 127,

sys/dev/pci/if_ix.c

880

if (sc->hw.phy.type == ixgbe_phy_none) {

sys/dev/pci/if_ix.c

881

err = sc->hw.phy.ops.identify(&sc->hw);

sys/dev/pci/if_ix.c

902

if (sc->hw.phy.ops.set_phy_power)

sys/dev/pci/if_ix.c

903

sc->hw.phy.ops.set_phy_power(&sc->hw, TRUE);

sys/dev/pci/if_ixl.c

391

uint8_t phy;

sys/dev/pci/if_ixl.c

4066

struct ixl_aq_phy_abilities *phy;

sys/dev/pci/if_ixl.c

4092

phy = IXL_DMA_KVA(&idm);

sys/dev/pci/if_ixl.c

4094

phy_types = lemtoh32(&phy->phy_type);

sys/dev/pci/if_ixl.c

4095

phy_types |= (uint64_t)phy->phy_type_ext << 32;

sys/dev/pci/if_ixl.c

4116

struct ixl_aq_phy_abilities *phy;

sys/dev/pci/if_ixl.c

4128

phy = IXL_DMA_KVA(&idm);

sys/dev/pci/if_ixl.c

4130

rv = phy->module_type[0];

sys/dev/pci/if_jme.c

140

jme_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_jme.c

147

if ((sc->jme_caps & JME_CAP_FPGA) && phy == 0)

sys/dev/pci/if_jme.c

151

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/pci/if_jme.c

160

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_jme.c

171

jme_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_jme.c

177

if ((sc->jme_caps & JME_CAP_FPGA) && phy == 0)

sys/dev/pci/if_jme.c

182

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/pci/if_jme.c

191

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_lge.c

223

lge_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_lge.c

233

if (sc->lge_pcs == 0 && phy == 0)

sys/dev/pci/if_lge.c

236

CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);

sys/dev/pci/if_lge.c

251

lge_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_lge.c

257

(data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);

sys/dev/pci/if_lii.c

506

lii_mii_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_lii.c

529

printf("%s: timeout reading PHY %d reg %d\n", DEVNAME(sc), phy,

sys/dev/pci/if_lii.c

537

lii_mii_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_lii.c

561

printf("%s: timeout writing PHY %d reg %d\n", DEVNAME(sc), phy,

sys/dev/pci/if_msk.c

381

msk_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_msk.c

387

SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |

sys/dev/pci/if_msk.c

409

phy, reg, val));

sys/dev/pci/if_msk.c

415

msk_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_msk.c

421

phy, reg, val));

sys/dev/pci/if_msk.c

424

SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |

sys/dev/pci/if_mwx.c

3900

if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))

sys/dev/pci/if_mwx.c

4374

if (phy->rx_ampdu_ts != status->timestamp) {

sys/dev/pci/if_mwx.c

4375

if (!++phy->ampdu_ref)

sys/dev/pci/if_mwx.c

4376

phy->ampdu_ref++;

sys/dev/pci/if_mwx.c

4378

phy->rx_ampdu_ts = status->timestamp;

sys/dev/pci/if_mwx.c

4380

status->ampdu_ref = phy->ampdu_ref;

sys/dev/pci/if_mwx.c

4962

struct sta_rec_phy *phy;

sys/dev/pci/if_mwx.c

5011

phy = mt7921_append_tlv(m, tlvnum, STA_REC_PHY, sizeof(*phy));

sys/dev/pci/if_mwx.c

5016

phy->basic_rate = htole16(0x0150); /* XXX */

sys/dev/pci/if_mwx.c

5017

phy->phy_type = mt7921_get_phy_mode_v2(sc, ni);

sys/dev/pci/if_mwx.c

5019

phy->ampdu = FIELD_PREP(IEEE80211_HT_AMPDU_PARM_FACTOR,

sys/dev/pci/if_mwx.c

5025

phy->rcpi = 0xdc; /* XXX STOLEN FROM LINUX DUMP */

sys/dev/pci/if_nep.c

803

nep_mii_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_nep.c

810

frame |= (reg << MIF_FRAME_REG_SHIFT) | (phy << MIF_FRAME_PHY_SHIFT);

sys/dev/pci/if_nep.c

824

nep_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/pci/if_nep.c

831

frame |= (reg << MIF_FRAME_REG_SHIFT) | (phy << MIF_FRAME_PHY_SHIFT);

sys/dev/pci/if_nfe.c

364

uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;

sys/dev/pci/if_nfe.c

366

phy = NFE_READ(sc, NFE_PHY_IFACE);

sys/dev/pci/if_nfe.c

367

phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);

sys/dev/pci/if_nfe.c

373

phy |= NFE_PHY_HDX; /* half-duplex */

sys/dev/pci/if_nfe.c

381

phy |= NFE_PHY_1000T;

sys/dev/pci/if_nfe.c

386

phy |= NFE_PHY_100TX;

sys/dev/pci/if_nfe.c

396

NFE_WRITE(sc, NFE_PHY_IFACE, phy);

sys/dev/pci/if_nfe.c

402

nfe_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_nfe.c

415

NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);

sys/dev/pci/if_nfe.c

436

sc->mii_phyaddr = phy;

sys/dev/pci/if_nfe.c

439

sc->sc_dev.dv_xname, phy, reg, val));

sys/dev/pci/if_nfe.c

445

nfe_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_nfe.c

459

ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;

sys/dev/pci/if_ngbe.c

1841

struct ngbe_phy_info *phy = &hw->phy;

sys/dev/pci/if_ngbe.c

1844

phy->ops.reset = ngbe_phy_reset;

sys/dev/pci/if_ngbe.c

1845

phy->ops.read_reg = ngbe_phy_read_reg;

sys/dev/pci/if_ngbe.c

1846

phy->ops.write_reg = ngbe_phy_write_reg;

sys/dev/pci/if_ngbe.c

1847

phy->ops.setup_link = ngbe_phy_setup_link;

sys/dev/pci/if_ngbe.c

1848

phy->ops.phy_led_ctrl = ngbe_phy_led_ctrl;

sys/dev/pci/if_ngbe.c

1849

phy->ops.check_overtemp = ngbe_phy_check_overtemp;

sys/dev/pci/if_ngbe.c

1850

phy->ops.identify = ngbe_phy_identify;

sys/dev/pci/if_ngbe.c

1851

phy->ops.init = ngbe_phy_init;

sys/dev/pci/if_ngbe.c

1852

phy->ops.check_event = ngbe_phy_check_event;

sys/dev/pci/if_ngbe.c

1853

phy->ops.get_adv_pause = ngbe_phy_get_advertised_pause;

sys/dev/pci/if_ngbe.c

1854

phy->ops.get_lp_adv_pause = ngbe_phy_get_lp_advertised_pause;

sys/dev/pci/if_ngbe.c

1855

phy->ops.set_adv_pause = ngbe_phy_set_pause_advertisement;

sys/dev/pci/if_ngbe.c

1856

phy->ops.setup_once = ngbe_phy_setup;

sys/dev/pci/if_ngbe.c

1957

hw->phy.type = ngbe_phy_internal;

sys/dev/pci/if_ngbe.c

2018

switch (hw->phy.media_type) {

sys/dev/pci/if_ngbe.c

2046

hw->phy.ops.get_adv_pause(hw, &technology_ability_reg);

sys/dev/pci/if_ngbe.c

2047

hw->phy.ops.get_lp_adv_pause(hw, &lp_technology_ability_reg);

sys/dev/pci/if_ngbe.c

2261

hw->phy.id = (uint32_t)phy_id;

sys/dev/pci/if_ngbe.c

2282

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/if_ngbe.c

2293

status = hw->phy.ops.read_reg(hw, NGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/pci/if_ngbe.c

268

hw->phy.autoneg_advertised = NGBE_LINK_SPEED_AUTONEG;

sys/dev/pci/if_ngbe.c

269

hw->phy.force_speed = NGBE_LINK_SPEED_UNKNOWN;

sys/dev/pci/if_ngbe.c

284

hw->phy.reset_if_overtemp = 1;

sys/dev/pci/if_ngbe.c

286

hw->phy.reset_if_overtemp = 0;

sys/dev/pci/if_ngbe.c

2869

hw->phy.ops.write_reg(hw, 0x11, 0xa4b, 0x1110);

sys/dev/pci/if_ngbe.c

2870

hw->phy.ops.write_reg(hw, MII_MMDACR, 0x0, MMDACR_FN_ADDRESS | 0x07);

sys/dev/pci/if_ngbe.c

2871

hw->phy.ops.write_reg(hw, MII_MMDAADR, 0x0, 0x003c);

sys/dev/pci/if_ngbe.c

2872

hw->phy.ops.write_reg(hw, MII_MMDACR, 0x0, MMDACR_FN_DATANPI | 0x07);

sys/dev/pci/if_ngbe.c

2873

hw->phy.ops.write_reg(hw, MII_MMDAADR, 0x0, 0);

sys/dev/pci/if_ngbe.c

2877

hw->phy.ops.read_reg(hw, MII_ANAR, 0, &val);

sys/dev/pci/if_ngbe.c

2879

hw->phy.ops.write_reg(hw, MII_ANAR, 0x0, val);

sys/dev/pci/if_ngbe.c

2937

hw->phy.ops.check_event(sc);

sys/dev/pci/if_ngbe.c

3183

speed = hw->phy.autoneg_advertised;

sys/dev/pci/if_ngbe.c

3185

speed = hw->phy.force_speed;

sys/dev/pci/if_ngbe.c

3188

if (hw->phy.type == ngbe_phy_internal) {

sys/dev/pci/if_ngbe.c

3189

error = hw->phy.ops.setup_once(sc);

sys/dev/pci/if_ngbe.c

3217

hw->phy.ops.read_reg(hw, NGBE_MDIO_AUTO_NEG_LSC,

sys/dev/pci/if_ngbe.c

3241

hw->phy.ops.read_reg(hw, 4, 0, &value);

sys/dev/pci/if_ngbe.c

3250

hw->phy.ops.read_reg(hw, NGBE_MDIO_AUTO_NEG_LSC,

sys/dev/pci/if_ngbe.c

3252

hw->phy.ops.read_reg(hw, MII_BMSR, 0, &value);

sys/dev/pci/if_ngbe.c

3256

hw->phy.ops.read_reg(hw, MII_ANLPAR, 0, &value);

sys/dev/pci/if_ngbe.c

3266

switch(hw->phy.type) {

sys/dev/pci/if_ngbe.c

3286

if (!hw->phy.phy_semaphore_mask)

sys/dev/pci/if_ngbe.c

3287

hw->phy.phy_semaphore_mask = NGBE_MNG_SWFW_SYNC_SW_PHY;

sys/dev/pci/if_ngbe.c

3290

hw->phy.addr = 0;

sys/dev/pci/if_ngbe.c

3293

error = hw->phy.ops.identify(sc);

sys/dev/pci/if_ngbe.c

3298

if (hw->phy.type == ngbe_phy_internal) {

sys/dev/pci/if_ngbe.c

3300

hw->phy.ops.write_reg(hw, 0x12, 0xa42, value);

sys/dev/pci/if_ngbe.c

3320

hw->phy.ops.write_reg(hw, 16, 0xd04, value);

sys/dev/pci/if_ngbe.c

3321

hw->phy.ops.write_reg(hw, 17, 0xd04, 0);

sys/dev/pci/if_ngbe.c

3323

hw->phy.ops.read_reg(hw, 18, 0xd04, &value);

sys/dev/pci/if_ngbe.c

3332

hw->phy.ops.write_reg(hw, 18, 0xd04, value);

sys/dev/pci/if_ngbe.c

3419

if (hw->phy.type != ngbe_phy_internal) {

sys/dev/pci/if_ngbe.c

3425

if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw) != 0) {

sys/dev/pci/if_ngbe.c

3436

status = hw->phy.ops.write_reg(hw, 0, 0, value);

sys/dev/pci/if_ngbe.c

3438

status = hw->phy.ops.read_reg(hw, 0, 0, &value);

sys/dev/pci/if_ngbe.c

3458

status = hw->phy.ops.read_reg(hw, MII_ANAR, 0, &value);

sys/dev/pci/if_ngbe.c

3461

status = hw->phy.ops.write_reg(hw, MII_ANAR, 0, value);

sys/dev/pci/if_ngbe.c

3484

hw->phy.ops.write_reg(hw, 20, 0xa46, 2);

sys/dev/pci/if_ngbe.c

3488

hw->phy.ops.read_reg(hw, 16, 0xa42, &value);

sys/dev/pci/if_ngbe.c

3509

status = hw->phy.ops.reset(sc);

sys/dev/pci/if_ngbe.c

3534

hw->phy.ops.write_reg(hw, 0, 0, value);

sys/dev/pci/if_ngbe.c

3540

hw->phy.ops.read_reg(hw, 4, 0, &value);

sys/dev/pci/if_ngbe.c

3542

hw->phy.ops.write_reg(hw, 4, 0, value);

sys/dev/pci/if_ngbe.c

3545

hw->phy.ops.read_reg(hw, 9, 0, &value);

sys/dev/pci/if_ngbe.c

3550

hw->phy.ops.write_reg(hw, 9, 0, value);

sys/dev/pci/if_ngbe.c

3552

hw->phy.ops.read_reg(hw, 4, 0, &value);

sys/dev/pci/if_ngbe.c

3557

hw->phy.ops.write_reg(hw, 4, 0, value);

sys/dev/pci/if_ngbe.c

3559

hw->phy.ops.read_reg(hw, 4, 0, &value);

sys/dev/pci/if_ngbe.c

3564

hw->phy.ops.write_reg(hw, 4, 0, value);

sys/dev/pci/if_ngbe.c

3568

hw->phy.ops.write_reg(hw, 0, 0, value);

sys/dev/pci/if_ngbe.c

3571

hw->phy.ops.phy_led_ctrl(sc);

sys/dev/pci/if_ngbe.c

3572

hw->phy.ops.check_event(sc);

sys/dev/pci/if_ngbe.c

3690

status = hw->phy.ops.init(sc);

sys/dev/pci/if_ngbe.c

4056

status = hw->phy.ops.setup_link(sc, speed, need_restart);

sys/dev/pci/if_ngbe.c

4126

if ((hw->phy.media_type == ngbe_media_type_copper) &&

sys/dev/pci/if_ngbe.c

4128

error = hw->phy.ops.set_adv_pause(hw, pcap_backplane);

sys/dev/pci/if_ngbe.c

4190

hw->phy.media_type = hw->mac.ops.get_media_type(hw);

sys/dev/pci/if_ngbereg.h

886

struct ngbe_phy_info phy;

sys/dev/pci/if_nge.c

495

nge_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_nge.c

504

frame.mii_phyaddr = phy;

sys/dev/pci/if_nge.c

512

nge_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_nge.c

522

frame.mii_phyaddr = phy;

sys/dev/pci/if_pcn.c

1972

pcn_mii_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_pcn.c

1977

pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));

sys/dev/pci/if_pcn.c

1991

pcn_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/pci/if_pcn.c

1995

pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));

sys/dev/pci/if_rtwn.c

819

struct r92c_rx_phystat *phy = NULL;

sys/dev/pci/if_rtwn.c

876

phy = mtod(rx_data->m, struct r92c_rx_phystat *);

sys/dev/pci/if_rtwn.c

877

rssi = rtwn_get_rssi(&sc->sc_sc, rate, phy);

sys/dev/pci/if_se.c

334

se_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_se.c

339

ctrl = (phy << GMI_PHY_SHIFT) | (reg << GMI_REG_SHIFT) |

sys/dev/pci/if_se.c

351

se_miibus_writereg(struct device *self, int phy, int reg, int data)

sys/dev/pci/if_se.c

356

ctrl = (phy << GMI_PHY_SHIFT) | (reg << GMI_REG_SHIFT) |

sys/dev/pci/if_sis.c

546

sis_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_sis.c

552

if (phy != 0)

sys/dev/pci/if_sis.c

578

if (phy != 0)

sys/dev/pci/if_sis.c

582

(phy << 11) | (reg << 6) | SIS_PHYOP_READ);

sys/dev/pci/if_sis.c

605

frame.mii_phyaddr = phy;

sys/dev/pci/if_sis.c

614

sis_miibus_writereg(struct device *self, int phy, int reg, int data)

sys/dev/pci/if_sis.c

620

if (phy != 0)

sys/dev/pci/if_sis.c

635

if (phy != 0)

sys/dev/pci/if_sis.c

638

CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |

sys/dev/pci/if_sis.c

653

frame.mii_phyaddr = phy;

sys/dev/pci/if_sk.c

2085

u_int32_t phy, v;

sys/dev/pci/if_sk.c

2127

phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |

sys/dev/pci/if_sk.c

2131

phy |= SK_GPHY_COPPER;

sys/dev/pci/if_sk.c

2133

phy |= SK_GPHY_FIBER;

sys/dev/pci/if_sk.c

2135

DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));

sys/dev/pci/if_sk.c

2137

SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);

sys/dev/pci/if_sk.c

2139

SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);

sys/dev/pci/if_sk.c

239

sk_xmac_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_sk.c

246

if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)

sys/dev/pci/if_sk.c

249

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/pci/if_sk.c

270

sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_sk.c

277

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/pci/if_sk.c

321

sk_marv_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_sk.c

327

if (phy != 0 ||

sys/dev/pci/if_sk.c

331

phy, reg));

sys/dev/pci/if_sk.c

335

SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |

sys/dev/pci/if_sk.c

357

phy, reg, val));

sys/dev/pci/if_sk.c

363

sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_sk.c

369

phy, reg, val));

sys/dev/pci/if_sk.c

372

SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |

sys/dev/pci/if_ste.c

327

ste_miibus_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_ste.c

332

if (sc->ste_one_phy && phy != 0)

sys/dev/pci/if_ste.c

337

frame.mii_phyaddr = phy;

sys/dev/pci/if_ste.c

345

ste_miibus_writereg(struct device *self, int phy, int reg, int data)

sys/dev/pci/if_ste.c

352

frame.mii_phyaddr = phy;

sys/dev/pci/if_stge.c

1526

stge_mii_readreg(struct device *self, int phy, int reg)

sys/dev/pci/if_stge.c

1529

return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));

sys/dev/pci/if_stge.c

1538

stge_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/pci/if_stge.c

1541

mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);

sys/dev/pci/if_tl.c

677

tl_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_tl.c

684

frame.mii_phyaddr = phy;

sys/dev/pci/if_tl.c

692

tl_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_tl.c

699

frame.mii_phyaddr = phy;

sys/dev/pci/if_vge.c

299

vge_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_vge.c

305

if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))

sys/dev/pci/if_vge.c

337

vge_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_vge.c

342

if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))

sys/dev/pci/if_vr.c

272

vr_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_vr.c

280

if (phy != 1)

sys/dev/pci/if_vr.c

288

frame.mii_phyaddr = phy;

sys/dev/pci/if_vr.c

296

vr_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_vr.c

304

if (phy != 1)

sys/dev/pci/if_vr.c

312

frame.mii_phyaddr = phy;

sys/dev/pci/if_vte.c

114

vte_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_vte.c

120

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/pci/if_vte.c

129

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_vte.c

137

vte_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/pci/if_vte.c

144

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/pci/if_vte.c

153

sc->sc_dev.dv_xname, phy, reg);

sys/dev/pci/if_wb.c

452

wb_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/pci/if_wb.c

459

frame.mii_phyaddr = phy;

sys/dev/pci/if_wb.c

467

wb_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/pci/if_wb.c

474

frame.mii_phyaddr = phy;

sys/dev/pci/igc_api.c

321

if (hw->phy.ops.check_reset_block)

sys/dev/pci/igc_api.c

322

return hw->phy.ops.check_reset_block(hw);

sys/dev/pci/igc_api.c

338

if (hw->phy.ops.get_info)

sys/dev/pci/igc_api.c

339

return hw->phy.ops.get_info(hw);

sys/dev/pci/igc_api.c

354

if (hw->phy.ops.reset)

sys/dev/pci/igc_api.c

355

return hw->phy.ops.reset(hw);

sys/dev/pci/igc_api.c

75

if (hw->phy.ops.init_params) {

sys/dev/pci/igc_api.c

76

ret_val = hw->phy.ops.init_params(hw);

sys/dev/pci/igc_base.c

102

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_base.c

104

if (!(phy->ops.check_reset_block))

sys/dev/pci/igc_base.c

108

if (phy->ops.check_reset_block(hw))

sys/dev/pci/igc_hw.h

360

struct igc_phy_info phy;

sys/dev/pci/igc_i225.c

1081

hw->phy.ops.init_params = igc_init_phy_params_i225;

sys/dev/pci/igc_i225.c

1119

hw->phy.media_type != igc_media_type_copper)

sys/dev/pci/igc_i225.c

135

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_i225.c

140

if (hw->phy.media_type != igc_media_type_copper) {

sys/dev/pci/igc_i225.c

141

phy->type = igc_phy_none;

sys/dev/pci/igc_i225.c

145

phy->ops.power_up = igc_power_up_phy_copper;

sys/dev/pci/igc_i225.c

146

phy->ops.power_down = igc_power_down_phy_copper_base;

sys/dev/pci/igc_i225.c

147

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;

sys/dev/pci/igc_i225.c

148

phy->reset_delay_us = 100;

sys/dev/pci/igc_i225.c

149

phy->ops.acquire = igc_acquire_phy_base;

sys/dev/pci/igc_i225.c

150

phy->ops.check_reset_block = igc_check_reset_block_generic;

sys/dev/pci/igc_i225.c

151

phy->ops.release = igc_release_phy_base;

sys/dev/pci/igc_i225.c

152

phy->ops.reset = igc_phy_hw_reset_generic;

sys/dev/pci/igc_i225.c

153

phy->ops.read_reg = igc_read_phy_reg_gpy;

sys/dev/pci/igc_i225.c

154

phy->ops.write_reg = igc_write_phy_reg_gpy;

sys/dev/pci/igc_i225.c

161

ret_val = hw->phy.ops.reset(hw);

sys/dev/pci/igc_i225.c

166

phy->type = igc_phy_i225;

sys/dev/pci/igc_i225.c

907

if ((hw->phy.media_type == igc_media_type_copper) &&

sys/dev/pci/igc_i225.c

92

hw->phy.media_type = igc_media_type_copper;

sys/dev/pci/igc_mac.c

373

if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))

sys/dev/pci/igc_mac.c

569

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/pci/igc_mac.c

572

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/pci/igc_mac.c

585

ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,

sys/dev/pci/igc_mac.c

589

ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,

sys/dev/pci/igc_phy.c

137

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

143

if (!phy->ops.read_reg)

sys/dev/pci/igc_phy.c

146

ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);

sys/dev/pci/igc_phy.c

150

phy->id = (uint32_t)(phy_id << 16);

sys/dev/pci/igc_phy.c

152

ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);

sys/dev/pci/igc_phy.c

156

phy->id |= (uint32_t)(phy_id & PHY_REVISION_MASK);

sys/dev/pci/igc_phy.c

157

phy->revision = (uint32_t)(phy_id & ~PHY_REVISION_MASK);

sys/dev/pci/igc_phy.c

174

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

189

(phy->addr << IGC_MDIC_PHY_SHIFT) | (IGC_MDIC_OP_READ));

sys/dev/pci/igc_phy.c

19

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

23

phy->ops.init_params = igc_null_ops_generic;

sys/dev/pci/igc_phy.c

232

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

24

phy->ops.acquire = igc_null_ops_generic;

sys/dev/pci/igc_phy.c

247

(phy->addr << IGC_MDIC_PHY_SHIFT) | (IGC_MDIC_OP_WRITE));

sys/dev/pci/igc_phy.c

25

phy->ops.check_reset_block = igc_null_ops_generic;

sys/dev/pci/igc_phy.c

26

phy->ops.force_speed_duplex = igc_null_ops_generic;

sys/dev/pci/igc_phy.c

27

phy->ops.get_info = igc_null_ops_generic;

sys/dev/pci/igc_phy.c

28

phy->ops.set_page = igc_null_set_page;

sys/dev/pci/igc_phy.c

287

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

29

phy->ops.read_reg = igc_null_read_reg;

sys/dev/pci/igc_phy.c

295

phy->autoneg_advertised &= phy->autoneg_mask;

sys/dev/pci/igc_phy.c

298

ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);

sys/dev/pci/igc_phy.c

30

phy->ops.read_reg_locked = igc_null_read_reg;

sys/dev/pci/igc_phy.c

302

if (phy->autoneg_mask & ADVERTISE_1000_FULL) {

sys/dev/pci/igc_phy.c

304

ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,

sys/dev/pci/igc_phy.c

31

phy->ops.read_reg_page = igc_null_read_reg;

sys/dev/pci/igc_phy.c

310

if (phy->autoneg_mask & ADVERTISE_2500_FULL) {

sys/dev/pci/igc_phy.c

312

ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<

sys/dev/pci/igc_phy.c

32

phy->ops.release = igc_null_phy_generic;

sys/dev/pci/igc_phy.c

33

phy->ops.reset = igc_null_ops_generic;

sys/dev/pci/igc_phy.c

334

DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);

sys/dev/pci/igc_phy.c

337

if (phy->autoneg_advertised & ADVERTISE_10_HALF) {

sys/dev/pci/igc_phy.c

34

phy->ops.set_d0_lplu_state = igc_null_lplu_state;

sys/dev/pci/igc_phy.c

343

if (phy->autoneg_advertised & ADVERTISE_10_FULL) {

sys/dev/pci/igc_phy.c

349

if (phy->autoneg_advertised & ADVERTISE_100_HALF) {

sys/dev/pci/igc_phy.c

35

phy->ops.set_d3_lplu_state = igc_null_lplu_state;

sys/dev/pci/igc_phy.c

355

if (phy->autoneg_advertised & ADVERTISE_100_FULL) {

sys/dev/pci/igc_phy.c

36

phy->ops.write_reg = igc_null_write_reg;

sys/dev/pci/igc_phy.c

361

if (phy->autoneg_advertised & ADVERTISE_1000_HALF)

sys/dev/pci/igc_phy.c

365

if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {

sys/dev/pci/igc_phy.c

37

phy->ops.write_reg_locked = igc_null_write_reg;

sys/dev/pci/igc_phy.c

371

if (phy->autoneg_advertised & ADVERTISE_2500_HALF)

sys/dev/pci/igc_phy.c

375

if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {

sys/dev/pci/igc_phy.c

38

phy->ops.write_reg_page = igc_null_write_reg;

sys/dev/pci/igc_phy.c

39

phy->ops.power_up = igc_null_phy_generic;

sys/dev/pci/igc_phy.c

40

phy->ops.power_down = igc_null_phy_generic;

sys/dev/pci/igc_phy.c

435

ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);

sys/dev/pci/igc_phy.c

441

if (phy->autoneg_mask & ADVERTISE_1000_FULL)

sys/dev/pci/igc_phy.c

442

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,

sys/dev/pci/igc_phy.c

445

if (phy->autoneg_mask & ADVERTISE_2500_FULL)

sys/dev/pci/igc_phy.c

446

ret_val = phy->ops.write_reg(hw,

sys/dev/pci/igc_phy.c

465

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

474

phy->autoneg_advertised &= phy->autoneg_mask;

sys/dev/pci/igc_phy.c

479

if (!phy->autoneg_advertised)

sys/dev/pci/igc_phy.c

480

phy->autoneg_advertised = phy->autoneg_mask;

sys/dev/pci/igc_phy.c

493

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);

sys/dev/pci/igc_phy.c

498

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

sys/dev/pci/igc_phy.c

505

if (phy->autoneg_wait_to_complete) {

sys/dev/pci/igc_phy.c

545

ret_val = hw->phy.ops.force_speed_duplex(hw);

sys/dev/pci/igc_phy.c

581

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

586

switch (phy->type) {

sys/dev/pci/igc_phy.c

590

phy->speed_downgraded = false;

sys/dev/pci/igc_phy.c

612

if (!hw->phy.ops.read_reg)

sys/dev/pci/igc_phy.c

617

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/pci/igc_phy.c

620

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/pci/igc_phy.c

652

if (!hw->phy.ops.read_reg)

sys/dev/pci/igc_phy.c

660

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/pci/igc_phy.c

671

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/pci/igc_phy.c

699

struct igc_phy_info *phy = &hw->phy;

sys/dev/pci/igc_phy.c

705

if (phy->ops.check_reset_block) {

sys/dev/pci/igc_phy.c

706

ret_val = phy->ops.check_reset_block(hw);

sys/dev/pci/igc_phy.c

711

ret_val = phy->ops.acquire(hw);

sys/dev/pci/igc_phy.c

721

DELAY(phy->reset_delay_us);

sys/dev/pci/igc_phy.c

737

phy->ops.release(hw);

sys/dev/pci/igc_phy.c

756

hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

sys/dev/pci/igc_phy.c

758

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/pci/igc_phy.c

776

hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

sys/dev/pci/igc_phy.c

778

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/pci/igc_phy.c

802

ret_val = hw->phy.ops.acquire(hw);

sys/dev/pci/igc_phy.c

808

hw->phy.ops.release(hw);

sys/dev/pci/igc_phy.c

838

ret_val = hw->phy.ops.acquire(hw);

sys/dev/pci/igc_phy.c

844

hw->phy.ops.release(hw);

sys/dev/pci/igc_phy.c

869

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);

sys/dev/pci/igc_phy.c

873

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);

sys/dev/pci/igc_phy.c

877

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |

sys/dev/pci/igc_phy.c

883

ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);

sys/dev/pci/igc_phy.c

885

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);

sys/dev/pci/igc_phy.c

890

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);

sys/dev/pci/ixgbe.c

206

switch (hw->phy.media_type) {

sys/dev/pci/ixgbe.c

2539

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/pci/ixgbe.c

2542

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,

sys/dev/pci/ixgbe.c

2585

switch (hw->phy.media_type) {

sys/dev/pci/ixgbe.c

301

switch (hw->phy.media_type) {

sys/dev/pci/ixgbe.c

316

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/pci/ixgbe.c

337

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/pci/ixgbe.c

340

else if (hw->phy.media_type == ixgbe_media_type_copper)

sys/dev/pci/ixgbe.c

350

if (hw->phy.media_type == ixgbe_media_type_backplane) {

sys/dev/pci/ixgbe.c

353

} else if (hw->phy.media_type == ixgbe_media_type_copper) {

sys/dev/pci/ixgbe.c

371

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/pci/ixgbe.c

374

else if (hw->phy.media_type == ixgbe_media_type_copper)

sys/dev/pci/ixgbe.c

3965

switch (hw->phy.media_type) {

sys/dev/pci/ixgbe.c

4019

switch (hw->phy.media_type) {

sys/dev/pci/ixgbe.c

406

if (hw->phy.media_type == ixgbe_media_type_backplane) {

sys/dev/pci/ixgbe.c

4071

hw->phy.autoneg_advertised = 0;

sys/dev/pci/ixgbe.c

4074

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/pci/ixgbe.c

4077

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/pci/ixgbe.c

4109

status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,

sys/dev/pci/ixgbe.c

411

} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&

sys/dev/pci/ixgbe.c

4119

status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,

sys/dev/pci/ixgbe.c

4128

status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,

sys/dev/pci/ixgbe.c

413

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/pci/ixgbe.c

4138

status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,

sys/dev/pci/ixgbe.c

4342

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/pci/ixgbe.c

4343

if (hw->phy.ops.identify)

sys/dev/pci/ixgbe.c

4344

status = hw->phy.ops.identify(hw);

sys/dev/pci/ixgbe.c

440

hw->phy.media_type = hw->mac.ops.get_media_type(hw);

sys/dev/pci/ixgbe.c

655

if (hw->phy.id == 0)

sys/dev/pci/ixgbe.c

657

hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,

sys/dev/pci/ixgbe.c

659

hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,

sys/dev/pci/ixgbe.c

661

hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,

sys/dev/pci/ixgbe.c

663

hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,

sys/dev/pci/ixgbe_82598.c

1150

if (hw->phy.type == ixgbe_phy_nl) {

sys/dev/pci/ixgbe_82598.c

1158

hw->phy.ops.write_reg_mdi(hw,

sys/dev/pci/ixgbe_82598.c

1165

hw->phy.ops.read_reg_mdi(hw,

sys/dev/pci/ixgbe_82598.c

1182

hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,

sys/dev/pci/ixgbe_82598.c

1226

hw->phy.ops.identify(hw);

sys/dev/pci/ixgbe_82598.c

1230

switch (hw->phy.type) {

sys/dev/pci/ixgbe_82598.c

1233

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/pci/ixgbe_82598.c

1273

if (hw->phy.type == ixgbe_phy_nl) {

sys/dev/pci/ixgbe_82598.c

1274

hw->phy.ops.identify_sfp(hw);

sys/dev/pci/ixgbe_82598.c

1276

switch (hw->phy.sfp_type) {

sys/dev/pci/ixgbe_82598.c

138

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_82598.c

147

phy->ops.init = ixgbe_init_phy_ops_82598;

sys/dev/pci/ixgbe_82598.c

179

phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;

sys/dev/pci/ixgbe_82598.c

202

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_82598.c

209

phy->ops.identify(hw);

sys/dev/pci/ixgbe_82598.c

218

switch (hw->phy.type) {

sys/dev/pci/ixgbe_82598.c

220

phy->ops.setup_link = ixgbe_setup_phy_link_tnx;

sys/dev/pci/ixgbe_82598.c

221

phy->ops.check_link = ixgbe_check_phy_link_tnx;

sys/dev/pci/ixgbe_82598.c

222

phy->ops.get_firmware_version =

sys/dev/pci/ixgbe_82598.c

226

phy->ops.reset = ixgbe_reset_phy_nl;

sys/dev/pci/ixgbe_82598.c

229

ret_val = phy->ops.identify_sfp(hw);

sys/dev/pci/ixgbe_82598.c

232

else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {

sys/dev/pci/ixgbe_82598.c

370

switch (hw->phy.type) {

sys/dev/pci/ixgbe_82598.c

623

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/pci/ixgbe_82598.c

666

if (hw->phy.type == ixgbe_phy_nl) {

sys/dev/pci/ixgbe_82598.c

667

hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);

sys/dev/pci/ixgbe_82598.c

668

hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);

sys/dev/pci/ixgbe_82598.c

669

hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,

sys/dev/pci/ixgbe_82598.c

681

hw->phy.ops.read_reg(hw, 0xC79F,

sys/dev/pci/ixgbe_82598.c

684

hw->phy.ops.read_reg(hw, 0xC00C,

sys/dev/pci/ixgbe_82598.c

802

status = hw->phy.ops.setup_link_speed(hw, speed,

sys/dev/pci/ixgbe_82598.c

869

if (hw->phy.reset_disable == FALSE) {

sys/dev/pci/ixgbe_82598.c

873

phy_status = hw->phy.ops.init(hw);

sys/dev/pci/ixgbe_82598.c

879

hw->phy.ops.reset(hw);

sys/dev/pci/ixgbe_82599.c

1038

status = hw->phy.ops.setup_link_speed(hw, speed,

sys/dev/pci/ixgbe_82599.c

1076

status = hw->phy.ops.init(hw);

sys/dev/pci/ixgbe_82599.c

1082

if (hw->phy.sfp_setup_needed) {

sys/dev/pci/ixgbe_82599.c

1084

hw->phy.sfp_setup_needed = FALSE;

sys/dev/pci/ixgbe_82599.c

1091

if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)

sys/dev/pci/ixgbe_82599.c

1092

hw->phy.ops.reset(hw);

sys/dev/pci/ixgbe_82599.c

1167

if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||

sys/dev/pci/ixgbe_82599.c

121

if (hw->phy.multispeed_fiber) {

sys/dev/pci/ixgbe_82599.c

1309

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/pci/ixgbe_82599.c

1310

hw->phy.type = ixgbe_phy_none;

sys/dev/pci/ixgbe_82599.c

1315

if (hw->phy.type == ixgbe_phy_sfp_unsupported)

sys/dev/pci/ixgbe_82599.c

132

(hw->phy.smart_speed == ixgbe_smart_speed_auto ||

sys/dev/pci/ixgbe_82599.c

133

hw->phy.smart_speed == ixgbe_smart_speed_on) &&

sys/dev/pci/ixgbe_82599.c

1339

hw->phy.ops.identify(hw);

sys/dev/pci/ixgbe_82599.c

1341

switch (hw->phy.type) {

sys/dev/pci/ixgbe_82599.c

1344

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/pci/ixgbe_82599.c

1458

if (hw->phy.media_type != ixgbe_media_type_fiber) {

sys/dev/pci/ixgbe_82599.c

154

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_82599.c

162

hw->phy.qsfp_shared_i2c_bus = TRUE;

sys/dev/pci/ixgbe_82599.c

1648

if (hw->phy.qsfp_shared_i2c_bus == TRUE) {

sys/dev/pci/ixgbe_82599.c

1676

if (hw->phy.qsfp_shared_i2c_bus == TRUE) {

sys/dev/pci/ixgbe_82599.c

1706

if (hw->phy.qsfp_shared_i2c_bus == TRUE) {

sys/dev/pci/ixgbe_82599.c

1734

if (hw->phy.qsfp_shared_i2c_bus == TRUE) {

sys/dev/pci/ixgbe_82599.c

174

phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;

sys/dev/pci/ixgbe_82599.c

175

phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;

sys/dev/pci/ixgbe_82599.c

178

ret_val = phy->ops.identify(hw);

sys/dev/pci/ixgbe_82599.c

184

if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)

sys/dev/pci/ixgbe_82599.c

185

hw->phy.ops.reset = NULL;

sys/dev/pci/ixgbe_82599.c

195

switch (hw->phy.type) {

sys/dev/pci/ixgbe_82599.c

197

phy->ops.setup_link = ixgbe_setup_phy_link_tnx;

sys/dev/pci/ixgbe_82599.c

198

phy->ops.check_link = ixgbe_check_phy_link_tnx;

sys/dev/pci/ixgbe_82599.c

199

phy->ops.get_firmware_version =

sys/dev/pci/ixgbe_82599.c

216

if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {

sys/dev/pci/ixgbe_82599.c

219

hw->phy.ops.reset = NULL;

sys/dev/pci/ixgbe_82599.c

361

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_82599.c

371

phy->ops.identify = ixgbe_identify_phy_82599;

sys/dev/pci/ixgbe_82599.c

372

phy->ops.init = ixgbe_init_phy_ops_82599;

sys/dev/pci/ixgbe_82599.c

443

if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||

sys/dev/pci/ixgbe_82599.c

444

hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||

sys/dev/pci/ixgbe_82599.c

445

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/pci/ixgbe_82599.c

446

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||

sys/dev/pci/ixgbe_82599.c

447

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/pci/ixgbe_82599.c

448

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {

sys/dev/pci/ixgbe_82599.c

519

if (hw->phy.multispeed_fiber) {

sys/dev/pci/ixgbe_82599.c

526

if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)

sys/dev/pci/ixgbe_82599.c

549

switch (hw->phy.type) {

sys/dev/pci/ixgbe_82599.c

587

hw->phy.multispeed_fiber = TRUE;

sys/dev/pci/ixgbe_82599.c

808

hw->phy.autoneg_advertised = 0;

sys/dev/pci/ixgbe_82599.c

811

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/pci/ixgbe_82599.c

814

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/pci/ixgbe_82599.c

817

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/pci/ixgbe_82599.c

827

hw->phy.smart_speed_active = FALSE;

sys/dev/pci/ixgbe_82599.c

863

hw->phy.smart_speed_active = TRUE;

sys/dev/pci/ixgbe_82599.c

888

hw->phy.smart_speed_active = FALSE;

sys/dev/pci/ixgbe_82599.c

959

(hw->phy.smart_speed_active == FALSE))

sys/dev/pci/ixgbe_82599.c

979

if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)

sys/dev/pci/ixgbe_phy.c

1005

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/pci/ixgbe_phy.c

1007

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/pci/ixgbe_phy.c

1009

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/pci/ixgbe_phy.c

1013

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;

sys/dev/pci/ixgbe_phy.c

1014

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;

sys/dev/pci/ixgbe_phy.c

1018

hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;

sys/dev/pci/ixgbe_phy.c

1042

if (!hw->phy.speeds_supported)

sys/dev/pci/ixgbe_phy.c

1045

*speed = hw->phy.speeds_supported;

sys/dev/pci/ixgbe_phy.c

1081

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_phy.c

1119

hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe_phy.c

1124

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)

sys/dev/pci/ixgbe_phy.c

1127

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe_phy.c

1134

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,

sys/dev/pci/ixgbe_phy.c

1139

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)

sys/dev/pci/ixgbe_phy.c

1142

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,

sys/dev/pci/ixgbe_phy.c

1149

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/pci/ixgbe_phy.c

1154

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)

sys/dev/pci/ixgbe_phy.c

1157

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/pci/ixgbe_phy.c

1167

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe_phy.c

117

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

1172

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe_phy.c

1190

status = hw->phy.ops.read_reg(hw, TNX_FW_REV,

sys/dev/pci/ixgbe_phy.c

1209

status = hw->phy.ops.read_reg(hw, AQ_FW_REV,

sys/dev/pci/ixgbe_phy.c

1235

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/pci/ixgbe_phy.c

1239

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/pci/ixgbe_phy.c

1244

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/pci/ixgbe_phy.c

1294

hw->phy.ops.write_reg(hw, phy_offset,

sys/dev/pci/ixgbe_phy.c

1335

switch (hw->phy.type) {

sys/dev/pci/ixgbe_phy.c

1374

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/pci/ixgbe_phy.c

1392

enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;

sys/dev/pci/ixgbe_phy.c

1403

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/pci/ixgbe_phy.c

1411

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1419

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/pci/ixgbe_phy.c

1422

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1429

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1435

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1460

hw->phy.sfp_type = ixgbe_sfp_type_da_cu;

sys/dev/pci/ixgbe_phy.c

1462

hw->phy.sfp_type = ixgbe_sfp_type_sr;

sys/dev/pci/ixgbe_phy.c

1464

hw->phy.sfp_type = ixgbe_sfp_type_lr;

sys/dev/pci/ixgbe_phy.c

1466

hw->phy.sfp_type = ixgbe_sfp_type_da_cu;

sys/dev/pci/ixgbe_phy.c

1468

hw->phy.sfp_type = ixgbe_sfp_type_unknown;

sys/dev/pci/ixgbe_phy.c

1472

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1475

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1478

hw->phy.ops.read_i2c_eeprom(

sys/dev/pci/ixgbe_phy.c

1484

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1487

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1490

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1497

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1500

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1504

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1507

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1511

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1514

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1518

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1521

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1524

hw->phy.sfp_type = ixgbe_sfp_type_unknown;

sys/dev/pci/ixgbe_phy.c

1528

if (hw->phy.sfp_type != stored_sfp_type)

sys/dev/pci/ixgbe_phy.c

1529

hw->phy.sfp_setup_needed = TRUE;

sys/dev/pci/ixgbe_phy.c

1532

hw->phy.multispeed_fiber = FALSE;

sys/dev/pci/ixgbe_phy.c

1537

hw->phy.multispeed_fiber = TRUE;

sys/dev/pci/ixgbe_phy.c

1540

if (hw->phy.type != ixgbe_phy_nl) {

sys/dev/pci/ixgbe_phy.c

1541

hw->phy.id = identifier;

sys/dev/pci/ixgbe_phy.c

1542

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1549

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1556

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1571

hw->phy.type =

sys/dev/pci/ixgbe_phy.c

1576

hw->phy.type = ixgbe_phy_sfp_ftl_active;

sys/dev/pci/ixgbe_phy.c

1578

hw->phy.type = ixgbe_phy_sfp_ftl;

sys/dev/pci/ixgbe_phy.c

1581

hw->phy.type = ixgbe_phy_sfp_avago;

sys/dev/pci/ixgbe_phy.c

1584

hw->phy.type = ixgbe_phy_sfp_intel;

sys/dev/pci/ixgbe_phy.c

1587

hw->phy.type = ixgbe_phy_sfp_unknown;

sys/dev/pci/ixgbe_phy.c

1596

hw->phy.type = ixgbe_phy_sfp_passive_unknown;

sys/dev/pci/ixgbe_phy.c

1598

hw->phy.type = ixgbe_phy_sfp_active_unknown;

sys/dev/pci/ixgbe_phy.c

1605

!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||

sys/dev/pci/ixgbe_phy.c

1606

hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||

sys/dev/pci/ixgbe_phy.c

1607

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/pci/ixgbe_phy.c

1608

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||

sys/dev/pci/ixgbe_phy.c

1609

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/pci/ixgbe_phy.c

1610

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {

sys/dev/pci/ixgbe_phy.c

1611

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/pci/ixgbe_phy.c

1627

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/pci/ixgbe_phy.c

1628

if (hw->phy.type != ixgbe_phy_nl) {

sys/dev/pci/ixgbe_phy.c

1629

hw->phy.id = 0;

sys/dev/pci/ixgbe_phy.c

1630

hw->phy.type = ixgbe_phy_unknown;

sys/dev/pci/ixgbe_phy.c

1649

hw->phy.ops.identify_sfp(hw);

sys/dev/pci/ixgbe_phy.c

1650

if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)

sys/dev/pci/ixgbe_phy.c

1653

switch (hw->phy.type) {

sys/dev/pci/ixgbe_phy.c

1668

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1670

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1690

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1714

enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;

sys/dev/pci/ixgbe_phy.c

1727

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/pci/ixgbe_phy.c

1735

status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,

sys/dev/pci/ixgbe_phy.c

1742

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/pci/ixgbe_phy.c

1747

hw->phy.id = identifier;

sys/dev/pci/ixgbe_phy.c

1749

status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,

sys/dev/pci/ixgbe_phy.c

1755

status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,

sys/dev/pci/ixgbe_phy.c

1762

hw->phy.type = ixgbe_phy_qsfp_passive_unknown;

sys/dev/pci/ixgbe_phy.c

1764

hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;

sys/dev/pci/ixgbe_phy.c

1766

hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;

sys/dev/pci/ixgbe_phy.c

1770

hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;

sys/dev/pci/ixgbe_phy.c

1772

hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;

sys/dev/pci/ixgbe_phy.c

1780

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1784

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1788

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1801

hw->phy.type = ixgbe_phy_qsfp_active_unknown;

sys/dev/pci/ixgbe_phy.c

1803

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1806

hw->phy.sfp_type =

sys/dev/pci/ixgbe_phy.c

1810

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/pci/ixgbe_phy.c

1816

if (hw->phy.sfp_type != stored_sfp_type)

sys/dev/pci/ixgbe_phy.c

1817

hw->phy.sfp_setup_needed = TRUE;

sys/dev/pci/ixgbe_phy.c

1820

hw->phy.multispeed_fiber = FALSE;

sys/dev/pci/ixgbe_phy.c

1825

hw->phy.multispeed_fiber = TRUE;

sys/dev/pci/ixgbe_phy.c

1830

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1837

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1844

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/pci/ixgbe_phy.c

1857

hw->phy.type = ixgbe_phy_qsfp_intel;

sys/dev/pci/ixgbe_phy.c

1859

hw->phy.type = ixgbe_phy_qsfp_unknown;

sys/dev/pci/ixgbe_phy.c

1872

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/pci/ixgbe_phy.c

1873

hw->phy.id = 0;

sys/dev/pci/ixgbe_phy.c

1874

hw->phy.type = ixgbe_phy_unknown;

sys/dev/pci/ixgbe_phy.c

1894

uint16_t sfp_type = hw->phy.sfp_type;

sys/dev/pci/ixgbe_phy.c

1898

if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)

sys/dev/pci/ixgbe_phy.c

1901

if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)

sys/dev/pci/ixgbe_phy.c

1905

(hw->phy.sfp_type == ixgbe_sfp_type_da_cu))

sys/dev/pci/ixgbe_phy.c

1999

return hw->phy.ops.read_i2c_byte(hw, byte_offset,

sys/dev/pci/ixgbe_phy.c

2017

return hw->phy.ops.write_i2c_byte(hw, byte_offset,

sys/dev/pci/ixgbe_phy.c

2032

hw->phy.sfp_type == ixgbe_sfp_type_not_present)

sys/dev/pci/ixgbe_phy.c

2054

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

2180

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

226

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

2711

hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,

sys/dev/pci/ixgbe_phy.c

2736

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,

sys/dev/pci/ixgbe_phy.c

2750

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,

sys/dev/pci/ixgbe_phy.c

317

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_phy.c

322

phy->ops.identify = ixgbe_identify_phy_generic;

sys/dev/pci/ixgbe_phy.c

323

phy->ops.reset = ixgbe_reset_phy_generic;

sys/dev/pci/ixgbe_phy.c

324

phy->ops.read_reg = ixgbe_read_phy_reg_generic;

sys/dev/pci/ixgbe_phy.c

325

phy->ops.write_reg = ixgbe_write_phy_reg_generic;

sys/dev/pci/ixgbe_phy.c

326

phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;

sys/dev/pci/ixgbe_phy.c

327

phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;

sys/dev/pci/ixgbe_phy.c

328

phy->ops.setup_link = ixgbe_setup_phy_link_generic;

sys/dev/pci/ixgbe_phy.c

329

phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;

sys/dev/pci/ixgbe_phy.c

330

phy->ops.check_link = NULL;

sys/dev/pci/ixgbe_phy.c

331

phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;

sys/dev/pci/ixgbe_phy.c

332

phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;

sys/dev/pci/ixgbe_phy.c

333

phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;

sys/dev/pci/ixgbe_phy.c

334

phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;

sys/dev/pci/ixgbe_phy.c

335

phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;

sys/dev/pci/ixgbe_phy.c

336

phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;

sys/dev/pci/ixgbe_phy.c

337

phy->ops.identify_sfp = ixgbe_identify_module_generic;

sys/dev/pci/ixgbe_phy.c

338

phy->sfp_type = ixgbe_sfp_type_unknown;

sys/dev/pci/ixgbe_phy.c

339

phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;

sys/dev/pci/ixgbe_phy.c

340

phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;

sys/dev/pci/ixgbe_phy.c

341

phy->ops.read_i2c_combined_unlocked =

sys/dev/pci/ixgbe_phy.c

343

phy->ops.write_i2c_combined_unlocked =

sys/dev/pci/ixgbe_phy.c

345

phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;

sys/dev/pci/ixgbe_phy.c

346

phy->ops.write_i2c_byte_unlocked =

sys/dev/pci/ixgbe_phy.c

348

phy->ops.check_overtemp = ixgbe_tn_check_overtemp;

sys/dev/pci/ixgbe_phy.c

372

hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);

sys/dev/pci/ixgbe_phy.c

374

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/pci/ixgbe_phy.c

375

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/pci/ixgbe_phy.c

380

hw->phy.type = ixgbe_phy_cu_unknown;

sys/dev/pci/ixgbe_phy.c

382

hw->phy.type = ixgbe_phy_generic;

sys/dev/pci/ixgbe_phy.c

401

if (!hw->phy.phy_semaphore_mask) {

sys/dev/pci/ixgbe_phy.c

403

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;

sys/dev/pci/ixgbe_phy.c

405

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_phy.c

408

if (hw->phy.type != ixgbe_phy_unknown)

sys/dev/pci/ixgbe_phy.c

411

if (hw->phy.nw_mng_if_sel) {

sys/dev/pci/ixgbe_phy.c

412

phy_addr = (hw->phy.nw_mng_if_sel &

sys/dev/pci/ixgbe_phy.c

433

hw->phy.addr = 0;

sys/dev/pci/ixgbe_phy.c

480

hw->phy.addr = phy_addr;

sys/dev/pci/ixgbe_phy.c

481

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,

sys/dev/pci/ixgbe_phy.c

505

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,

sys/dev/pci/ixgbe_phy.c

510

hw->phy.id = (uint32_t)(phy_id_high << 16);

sys/dev/pci/ixgbe_phy.c

511

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,

sys/dev/pci/ixgbe_phy.c

514

hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK);

sys/dev/pci/ixgbe_phy.c

515

hw->phy.revision =

sys/dev/pci/ixgbe_phy.c

577

if (hw->phy.type == ixgbe_phy_unknown)

sys/dev/pci/ixgbe_phy.c

580

if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)

sys/dev/pci/ixgbe_phy.c

584

if (!hw->phy.reset_if_overtemp &&

sys/dev/pci/ixgbe_phy.c

585

(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))

sys/dev/pci/ixgbe_phy.c

596

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/pci/ixgbe_phy.c

607

if (hw->phy.type == ixgbe_phy_x550em_ext_t) {

sys/dev/pci/ixgbe_phy.c

608

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_phy.c

620

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_phy.c

660

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/pci/ixgbe_phy.c

691

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/pci/ixgbe_phy.c

738

uint32_t gssr = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

745

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

sys/dev/pci/ixgbe_phy.c

771

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/pci/ixgbe_phy.c

800

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/pci/ixgbe_phy.c

838

uint32_t gssr = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

843

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

sys/dev/pci/ixgbe_phy.c

871

hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe_phy.c

876

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&

sys/dev/pci/ixgbe_phy.c

880

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe_phy.c

884

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,

sys/dev/pci/ixgbe_phy.c

891

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&

sys/dev/pci/ixgbe_phy.c

897

if ((hw->phy.autoneg_advertised &

sys/dev/pci/ixgbe_phy.c

905

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&

sys/dev/pci/ixgbe_phy.c

909

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,

sys/dev/pci/ixgbe_phy.c

914

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/pci/ixgbe_phy.c

920

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&

sys/dev/pci/ixgbe_phy.c

924

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/pci/ixgbe_phy.c

933

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe_phy.c

938

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe_phy.c

960

hw->phy.autoneg_advertised = 0;

sys/dev/pci/ixgbe_phy.c

963

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/pci/ixgbe_phy.c

966

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;

sys/dev/pci/ixgbe_phy.c

969

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;

sys/dev/pci/ixgbe_phy.c

972

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/pci/ixgbe_phy.c

975

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/pci/ixgbe_phy.c

978

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;

sys/dev/pci/ixgbe_phy.c

981

hw->phy.ops.setup_link(hw);

sys/dev/pci/ixgbe_phy.c

998

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,

sys/dev/pci/ixgbe_type.h

4313

struct ixgbe_phy_info phy;

sys/dev/pci/ixgbe_x540.c

104

phy->ops.init = ixgbe_init_phy_ops_generic;

sys/dev/pci/ixgbe_x540.c

105

phy->ops.reset = NULL;

sys/dev/pci/ixgbe_x540.c

106

phy->ops.set_phy_power = ixgbe_set_copper_phy_power;

sys/dev/pci/ixgbe_x540.c

203

return hw->phy.ops.setup_link_speed(hw, speed,

sys/dev/pci/ixgbe_x540.c

218

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_x540.c

323

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/pci/ixgbe_x540.c

86

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_x550.c

1352

hw->phy.type = ixgbe_phy_sgmii;

sys/dev/pci/ixgbe_x550.c

1374

switch (hw->phy.sfp_type) {

sys/dev/pci/ixgbe_x550.c

1443

hw->phy.ops.reset = NULL;

sys/dev/pci/ixgbe_x550.c

1561

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);

sys/dev/pci/ixgbe_x550.c

1634

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);

sys/dev/pci/ixgbe_x550.c

1708

if (hw->phy.type == ixgbe_phy_fw) {

sys/dev/pci/ixgbe_x550.c

1710

*speed = hw->phy.speeds_supported;

sys/dev/pci/ixgbe_x550.c

1715

if (hw->phy.media_type == ixgbe_media_type_fiber) {

sys/dev/pci/ixgbe_x550.c

1721

if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/pci/ixgbe_x550.c

1722

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1

sys/dev/pci/ixgbe_x550.c

1723

|| hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/pci/ixgbe_x550.c

1724

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {

sys/dev/pci/ixgbe_x550.c

1730

if (hw->phy.multispeed_fiber)

sys/dev/pci/ixgbe_x550.c

1736

switch (hw->phy.type) {

sys/dev/pci/ixgbe_x550.c

1744

if (hw->phy.nw_mng_if_sel &

sys/dev/pci/ixgbe_x550.c

1786

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,

sys/dev/pci/ixgbe_x550.c

1795

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,

sys/dev/pci/ixgbe_x550.c

1805

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,

sys/dev/pci/ixgbe_x550.c

1819

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,

sys/dev/pci/ixgbe_x550.c

1835

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,

sys/dev/pci/ixgbe_x550.c

1843

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,

sys/dev/pci/ixgbe_x550.c

1885

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_x550.c

1894

status = hw->phy.ops.write_reg(hw,

sys/dev/pci/ixgbe_x550.c

1903

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,

sys/dev/pci/ixgbe_x550.c

1913

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,

sys/dev/pci/ixgbe_x550.c

1921

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,

sys/dev/pci/ixgbe_x550.c

1931

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,

sys/dev/pci/ixgbe_x550.c

1939

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,

sys/dev/pci/ixgbe_x550.c

1948

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,

sys/dev/pci/ixgbe_x550.c

2022

if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))

sys/dev/pci/ixgbe_x550.c

2069

hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);

sys/dev/pci/ixgbe_x550.c

2075

hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {

sys/dev/pci/ixgbe_x550.c

2076

hw->phy.addr = (hw->phy.nw_mng_if_sel &

sys/dev/pci/ixgbe_x550.c

2094

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_x550.c

2103

phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;

sys/dev/pci/ixgbe_x550.c

2105

phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;

sys/dev/pci/ixgbe_x550.c

2111

phy->ops.read_reg_mdi = NULL;

sys/dev/pci/ixgbe_x550.c

2112

phy->ops.write_reg_mdi = NULL;

sys/dev/pci/ixgbe_x550.c

2113

hw->phy.ops.read_reg = NULL;

sys/dev/pci/ixgbe_x550.c

2114

hw->phy.ops.write_reg = NULL;

sys/dev/pci/ixgbe_x550.c

2115

phy->ops.check_overtemp = ixgbe_check_overtemp_fw;

sys/dev/pci/ixgbe_x550.c

2117

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;

sys/dev/pci/ixgbe_x550.c

2119

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_x550.c

2124

hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;

sys/dev/pci/ixgbe_x550.c

2125

hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;

sys/dev/pci/ixgbe_x550.c

2127

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;

sys/dev/pci/ixgbe_x550.c

2129

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_x550.c

2133

hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;

sys/dev/pci/ixgbe_x550.c

2136

phy->ops.read_reg_mdi = NULL;

sys/dev/pci/ixgbe_x550.c

2137

phy->ops.write_reg_mdi = NULL;

sys/dev/pci/ixgbe_x550.c

2143

ret_val = phy->ops.identify(hw);

sys/dev/pci/ixgbe_x550.c

215

if (hw->phy.ops.read_i2c_byte_unlocked)

sys/dev/pci/ixgbe_x550.c

2150

if (phy->sfp_type != ixgbe_sfp_type_unknown)

sys/dev/pci/ixgbe_x550.c

2151

phy->ops.reset = NULL;

sys/dev/pci/ixgbe_x550.c

2154

switch (hw->phy.type) {

sys/dev/pci/ixgbe_x550.c

2156

phy->ops.setup_link = NULL;

sys/dev/pci/ixgbe_x550.c

2157

phy->ops.read_reg = ixgbe_read_phy_reg_x550em;

sys/dev/pci/ixgbe_x550.c

2158

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/pci/ixgbe_x550.c

216

status = hw->phy.ops.read_i2c_byte_unlocked(hw, reg, IXGBE_PE,

sys/dev/pci/ixgbe_x550.c

2161

phy->ops.setup_link = ixgbe_setup_kr_x550em;

sys/dev/pci/ixgbe_x550.c

2162

phy->ops.read_reg = ixgbe_read_phy_reg_x550em;

sys/dev/pci/ixgbe_x550.c

2163

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/pci/ixgbe_x550.c

2167

phy->ops.setup_link = NULL;

sys/dev/pci/ixgbe_x550.c

2168

phy->ops.reset = NULL;

sys/dev/pci/ixgbe_x550.c

2172

phy->ops.setup_link = NULL;

sys/dev/pci/ixgbe_x550.c

2173

phy->ops.read_reg = ixgbe_read_phy_reg_x550em;

sys/dev/pci/ixgbe_x550.c

2174

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/pci/ixgbe_x550.c

2180

phy->ops.setup_internal_link =

sys/dev/pci/ixgbe_x550.c

2187

phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;

sys/dev/pci/ixgbe_x550.c

2189

phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;

sys/dev/pci/ixgbe_x550.c

2190

phy->ops.reset = ixgbe_reset_phy_t_X550em;

sys/dev/pci/ixgbe_x550.c

2193

phy->ops.setup_link = NULL;

sys/dev/pci/ixgbe_x550.c

2196

phy->ops.setup_link = ixgbe_setup_fw_link;

sys/dev/pci/ixgbe_x550.c

2197

phy->ops.reset = ixgbe_reset_phy_fw;

sys/dev/pci/ixgbe_x550.c

2252

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_x550.c

2268

status = hw->phy.ops.init(hw);

sys/dev/pci/ixgbe_x550.c

2281

if (hw->phy.type == ixgbe_phy_x550em_ext_t) {

sys/dev/pci/ixgbe_x550.c

2291

if (hw->phy.sfp_setup_needed) {

sys/dev/pci/ixgbe_x550.c

2293

hw->phy.sfp_setup_needed = FALSE;

sys/dev/pci/ixgbe_x550.c

2300

if (!hw->phy.reset_disable && hw->phy.ops.reset) {

sys/dev/pci/ixgbe_x550.c

2301

if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)

sys/dev/pci/ixgbe_x550.c

236

if (hw->phy.ops.write_i2c_byte_unlocked)

sys/dev/pci/ixgbe_x550.c

237

status = hw->phy.ops.write_i2c_byte_unlocked(hw, reg, IXGBE_PE,

sys/dev/pci/ixgbe_x550.c

2383

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_x550.c

2395

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_x550.c

2405

status = hw->phy.ops.write_reg(hw,

sys/dev/pci/ixgbe_x550.c

2424

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)

sys/dev/pci/ixgbe_x550.c

2430

return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);

sys/dev/pci/ixgbe_x550.c

2581

if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {

sys/dev/pci/ixgbe_x550.c

2588

ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,

sys/dev/pci/ixgbe_x550.c

2606

ret_val = hw->phy.ops.read_reg(hw, reg_slice,

sys/dev/pci/ixgbe_x550.c

2619

ret_val = hw->phy.ops.write_reg(hw, reg_slice,

sys/dev/pci/ixgbe_x550.c

2623

ret_val = hw->phy.ops.read_reg(hw, reg_slice,

sys/dev/pci/ixgbe_x550.c

2773

ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/pci/ixgbe_x550.c

2779

ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/pci/ixgbe_x550.c

2813

!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {

sys/dev/pci/ixgbe_x550.c

2822

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_x550.c

328

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_x550.c

3404

hw->phy.ops.identify(hw);

sys/dev/pci/ixgbe_x550.c

3406

switch (hw->phy.type) {

sys/dev/pci/ixgbe_x550.c

3409

if (hw->phy.nw_mng_if_sel &

sys/dev/pci/ixgbe_x550.c

3431

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/pci/ixgbe_x550.c

3440

if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)

sys/dev/pci/ixgbe_x550.c

3442

if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)

sys/dev/pci/ixgbe_x550.c

3444

if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)

sys/dev/pci/ixgbe_x550.c

3579

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,

sys/dev/pci/ixgbe_x550.c

3602

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,

sys/dev/pci/ixgbe_x550.c

3609

status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe_x550.c

3616

status = hw->phy.ops.read_reg(hw,

sys/dev/pci/ixgbe_x550.c

3624

save_autoneg = hw->phy.autoneg_advertised;

sys/dev/pci/ixgbe_x550.c

3630

hw->phy.autoneg_advertised = save_autoneg;

sys/dev/pci/ixgbe_x550.c

3650

status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,

sys/dev/pci/ixgbe_x550.c

4101

hw->phy.id);

sys/dev/pci/ixgbe_x550.c

4140

uint32_t mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4147

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

sys/dev/pci/ixgbe_x550.c

4168

uint32_t mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4173

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

sys/dev/pci/ixgbe_x550.c

4205

return hw->phy.ops.setup_internal_link(hw);

sys/dev/pci/ixgbe_x550.c

4241

!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {

sys/dev/pci/ixgbe_x550.c

4248

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);

sys/dev/pci/ixgbe_x550.c

4282

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/pci/ixgbe_x550.c

4328

if (hw->phy.id == 0)

sys/dev/pci/ixgbe_x550.c

4332

hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,

sys/dev/pci/ixgbe_x550.c

4335

hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,

sys/dev/pci/ixgbe_x550.c

4356

if (hw->phy.id == 0)

sys/dev/pci/ixgbe_x550.c

4360

hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,

sys/dev/pci/ixgbe_x550.c

4363

hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,

sys/dev/pci/ixgbe_x550.c

440

hw->phy.type = ixgbe_phy_x550em_kx4;

sys/dev/pci/ixgbe_x550.c

443

hw->phy.type = ixgbe_phy_x550em_xfi;

sys/dev/pci/ixgbe_x550.c

448

hw->phy.type = ixgbe_phy_x550em_kr;

sys/dev/pci/ixgbe_x550.c

454

hw->phy.type = ixgbe_phy_ext_1g_t;

sys/dev/pci/ixgbe_x550.c

458

hw->phy.type = ixgbe_phy_fw;

sys/dev/pci/ixgbe_x550.c

460

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;

sys/dev/pci/ixgbe_x550.c

462

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_x550.c

546

hw->phy.speeds_supported = 0;

sys/dev/pci/ixgbe_x550.c

550

hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;

sys/dev/pci/ixgbe_x550.c

552

if (!hw->phy.autoneg_advertised)

sys/dev/pci/ixgbe_x550.c

553

hw->phy.autoneg_advertised = hw->phy.speeds_supported;

sys/dev/pci/ixgbe_x550.c

555

hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;

sys/dev/pci/ixgbe_x550.c

557

hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;

sys/dev/pci/ixgbe_x550.c

558

hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;

sys/dev/pci/ixgbe_x550.c

559

if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)

sys/dev/pci/ixgbe_x550.c

573

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;

sys/dev/pci/ixgbe_x550.c

575

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_x550.c

577

hw->phy.type = ixgbe_phy_fw;

sys/dev/pci/ixgbe_x550.c

578

hw->phy.ops.read_reg = NULL;

sys/dev/pci/ixgbe_x550.c

579

hw->phy.ops.write_reg = NULL;

sys/dev/pci/ixgbe_x550.c

620

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/pci/ixgbe_x550.c

660

phy->ops.init = ixgbe_init_phy_ops_X550em;

sys/dev/pci/ixgbe_x550.c

665

phy->ops.identify = ixgbe_identify_phy_fw;

sys/dev/pci/ixgbe_x550.c

666

phy->ops.set_phy_power = NULL;

sys/dev/pci/ixgbe_x550.c

667

phy->ops.get_firmware_version = NULL;

sys/dev/pci/ixgbe_x550.c

671

phy->ops.identify = ixgbe_identify_phy_x550em;

sys/dev/pci/ixgbe_x550.c

672

phy->ops.set_phy_power = NULL;

sys/dev/pci/ixgbe_x550.c

675

phy->ops.identify = ixgbe_identify_phy_x550em;

sys/dev/pci/ixgbe_x550.c

679

phy->ops.set_phy_power = NULL;

sys/dev/pci/ixgbe_x550.c

703

if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))

sys/dev/pci/ixgbe_x550.c

730

if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)

sys/dev/pci/ixgbe_x550.c

735

if (hw->phy.eee_speeds_advertised)

sys/dev/pci/ixgbe_x550.c

770

if (!!hw->phy.eee_speeds_advertised == enable_eee)

sys/dev/pci/ixgbe_x550.c

773

hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;

sys/dev/pci/ixgbe_x550.c

775

hw->phy.eee_speeds_advertised = 0;

sys/dev/pci/ixgbe_x550.c

776

return hw->phy.ops.setup_link(hw);

sys/dev/pci/ixgbe_x550.c

826

hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |

sys/dev/pci/ixgbe_x550.c

828

hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;

sys/dev/pcmcia/if_xe.c

891

xe_mdi_read(struct device *self, int phy, int reg)

sys/dev/pcmcia/if_xe.c

902

xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */

sys/dev/pcmcia/if_xe.c

913

("xe_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));

sys/dev/pcmcia/if_xe.c

919

xe_mdi_write(struct device *self, int phy, int reg, int value)

sys/dev/pcmcia/if_xe.c

928

xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */

sys/dev/pcmcia/if_xe.c

935

("xe_mdi_write: phy %d reg %d val %x\n", phy, reg, value));

sys/dev/sbus/be.c

1158

be_pal_gate(struct be_softc *sc, int phy)

sys/dev/sbus/be.c

1167

if (phy == BE_PHY_INTERNAL)

sys/dev/sbus/be.c

1175

be_tcvr_read_bit(struct be_softc *sc, int phy)

sys/dev/sbus/be.c

1181

if (phy == BE_PHY_INTERNAL) {

sys/dev/sbus/be.c

1203

be_tcvr_write_bit(struct be_softc *sc, int phy, int bit)

sys/dev/sbus/be.c

1209

if (phy == BE_PHY_INTERNAL) {

sys/dev/sbus/be.c

1223

be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits)

sys/dev/sbus/be.c

1228

be_tcvr_write_bit(sc, phy, (data & i) != 0);

sys/dev/sbus/be.c

1232

be_mii_readreg(struct device *self, int phy, int reg)

sys/dev/sbus/be.c

1241

be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);

sys/dev/sbus/be.c

1242

be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);

sys/dev/sbus/be.c

1243

be_mii_sendbits(sc, phy, phy, 5);

sys/dev/sbus/be.c

1244

be_mii_sendbits(sc, phy, reg, 5);

sys/dev/sbus/be.c

1246

(void) be_tcvr_read_bit(sc, phy);

sys/dev/sbus/be.c

1247

(void) be_tcvr_read_bit(sc, phy);

sys/dev/sbus/be.c

1250

val |= (be_tcvr_read_bit(sc, phy) << i);

sys/dev/sbus/be.c

1252

(void) be_tcvr_read_bit(sc, phy);

sys/dev/sbus/be.c

1253

(void) be_tcvr_read_bit(sc, phy);

sys/dev/sbus/be.c

1254

(void) be_tcvr_read_bit(sc, phy);

sys/dev/sbus/be.c

1260

be_mii_writereg(struct device *self, int phy, int reg, int val)

sys/dev/sbus/be.c

1269

be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);

sys/dev/sbus/be.c

1270

be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);

sys/dev/sbus/be.c

1271

be_mii_sendbits(sc, phy, phy, 5);

sys/dev/sbus/be.c

1272

be_mii_sendbits(sc, phy, reg, 5);

sys/dev/sbus/be.c

1274

be_tcvr_write_bit(sc, phy, 1);

sys/dev/sbus/be.c

1275

be_tcvr_write_bit(sc, phy, 0);

sys/dev/sbus/be.c

1278

be_tcvr_write_bit(sc, phy, (val >> i) & 1);

sys/dev/sbus/be.c

1282

be_mii_reset(struct be_softc *sc, int phy)

sys/dev/sbus/be.c

1286

be_mii_writereg((struct device *)sc, phy, MII_BMCR,

sys/dev/sbus/be.c

1288

be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);

sys/dev/sbus/be.c

1291

int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);

sys/dev/usb/dwc2/dwc2_core.h

1120

struct phy *phy;

sys/dev/usb/dwc2/dwc2_hcd.c

4369

ret = phy_reset(hsotg->phy);

sys/dev/usb/dwc2/dwc2_params.c

424

if (hsotg->phy) {

sys/dev/usb/dwc2/dwc2_params.c

429

if (phy_get_bus_width(hsotg->phy) == 8)

sys/dev/usb/if_aue.c

429

aue_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_aue.c

455

if (phy == 3)

sys/dev/usb/if_aue.c

461

aue_csr_write_1(sc, AUE_PHY_ADDR, phy);

sys/dev/usb/if_aue.c

476

sc->aue_dev.dv_xname, __func__, phy, reg, val));

sys/dev/usb/if_aue.c

483

aue_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/usb/if_aue.c

491

if (phy == 3)

sys/dev/usb/if_aue.c

497

sc->aue_dev.dv_xname, __func__, phy, reg, data));

sys/dev/usb/if_aue.c

501

aue_csr_write_1(sc, AUE_PHY_ADDR, phy);

sys/dev/usb/if_axe.c

259

axe_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_axe.c

277

DPRINTF(("axe_miibus_readreg: phy 0x%x reg 0x%x\n", phy, reg));

sys/dev/usb/if_axe.c

279

if (sc->axe_phyaddrs[0] != AXE_NOPHY && phy != sc->axe_phyaddrs[0])

sys/dev/usb/if_axe.c

282

if (sc->axe_phyaddrs[1] != AXE_NOPHY && phy != sc->axe_phyaddrs[1])

sys/dev/usb/if_axe.c

285

if (sc->axe_phyno != phy)

sys/dev/usb/if_axe.c

292

err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, val);

sys/dev/usb/if_axe.c

301

phy, reg, UGETW(val)));

sys/dev/usb/if_axe.c

318

axe_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/usb/if_axe.c

326

if (sc->axe_phyno != phy)

sys/dev/usb/if_axe.c

333

err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, uval);

sys/dev/usb/if_axen.c

169

axen_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_axen.c

181

if (sc->axen_phyno != phy)

sys/dev/usb/if_axen.c

185

err = axen_cmd(sc, AXEN_CMD_MII_READ_REG, reg, phy, &val);

sys/dev/usb/if_axen.c

195

phy, reg, ival));

sys/dev/usb/if_axen.c

205

axen_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/usb/if_axen.c

214

if (sc->axen_phyno != phy)

sys/dev/usb/if_axen.c

219

err = axen_cmd(sc, AXEN_CMD_MII_WRITE_REG, reg, phy, &uval);

sys/dev/usb/if_axen.c

222

phy, reg, val));

sys/dev/usb/if_mos.c

373

mos_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_mos.c

386

mos_reg_write_1(sc, MOS_PHY_CTL, (phy & MOS_PHYCTL_PHYADDR) |

sys/dev/usb/if_mos.c

407

mos_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/usb/if_mos.c

418

mos_reg_write_1(sc, MOS_PHY_CTL, (phy & MOS_PHYCTL_PHYADDR) |

sys/dev/usb/if_mtw.c

2007

rt2860_rates[mn->ridx[i]].phy ==

sys/dev/usb/if_mtw.c

2008

rt2860_rates[mn->ridx[j]].phy)

sys/dev/usb/if_mtw.c

2051

uint16_t phy;

sys/dev/usb/if_mtw.c

2131

phy = letoh16(rxwi->phy);

sys/dev/usb/if_mtw.c

2132

switch (phy >> MT7601_PHY_SHIFT) {

sys/dev/usb/if_mtw.c

2134

switch ((phy & MTW_PHY_MCS) & ~MTW_PHY_SHPRE) {

sys/dev/usb/if_mtw.c

2140

if (phy & MTW_PHY_SHPRE)

sys/dev/usb/if_mtw.c

2144

switch (phy & MTW_PHY_MCS) {

sys/dev/usb/if_mtw.c

2341

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/usb/if_mtw.c

2342

txwi->phy = htole16(MTW_PHY_CCK << MT7601_PHY_SHIFT);

sys/dev/usb/if_mtw.c

2346

} else if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)

sys/dev/usb/if_mtw.c

2347

txwi->phy = htole16(MTW_PHY_OFDM << MT7601_PHY_SHIFT);

sys/dev/usb/if_mtw.c

2348

txwi->phy |= htole16(mcs);

sys/dev/usb/if_mue.c

264

mue_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_mue.c

272

if (sc->mue_phyno != phy)

sys/dev/usb/if_mue.c

281

MUE_MII_ACCESS_PHYADDR(phy));

sys/dev/usb/if_mue.c

292

mue_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/usb/if_mue.c

299

if (sc->mue_phyno != phy)

sys/dev/usb/if_mue.c

309

MUE_MII_ACCESS_PHYADDR(phy));

sys/dev/usb/if_otus.c

1034

letoh32(tx->phy)));

sys/dev/usb/if_otusreg.h

291

uint32_t phy;

sys/dev/usb/if_rsu.c

1255

struct r92s_rx_phystat *phy;

sys/dev/usb/if_rsu.c

1266

phy = (struct r92s_rx_phystat *)physt;

sys/dev/usb/if_rsu.c

1267

rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 106;

sys/dev/usb/if_run.c

2138

rt2860_rates[rn->ridx[i]].phy ==

sys/dev/usb/if_run.c

2139

rt2860_rates[rn->ridx[j]].phy)

sys/dev/usb/if_run.c

2186

uint16_t phy;

sys/dev/usb/if_run.c

2271

phy = letoh16(rxwi->phy);

sys/dev/usb/if_run.c

2272

switch (phy & RT2860_PHY_MODE) {

sys/dev/usb/if_run.c

2274

switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {

sys/dev/usb/if_run.c

2280

if (phy & RT2860_PHY_SHPRE)

sys/dev/usb/if_run.c

2284

switch (phy & RT2860_PHY_MCS) {

sys/dev/usb/if_run.c

2469

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/usb/if_run.c

2470

txwi->phy = htole16(RT2860_PHY_CCK);

sys/dev/usb/if_run.c

2475

txwi->phy = htole16(RT2860_PHY_OFDM);

sys/dev/usb/if_run.c

2476

txwi->phy |= htole16(mcs);

sys/dev/usb/if_smsc.c

281

smsc_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_smsc.c

293

addr = (phy << 11) | (reg << 6) | SMSC_MII_READ;

sys/dev/usb/if_smsc.c

307

smsc_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/usb/if_smsc.c

312

if (sc->sc_phyno != phy)

sys/dev/usb/if_smsc.c

324

addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE;

sys/dev/usb/if_udav.c

1424

udav_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_udav.c

1436

sc->sc_dev.dv_xname, __func__, phy, reg));

sys/dev/usb/if_udav.c

1447

if (phy != 0) {

sys/dev/usb/if_udav.c

1449

sc->sc_dev.dv_xname, __func__, phy));

sys/dev/usb/if_udav.c

1475

sc->sc_dev.dv_xname, __func__, phy, reg, data16));

sys/dev/usb/if_udav.c

1481

udav_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/usb/if_udav.c

1492

sc->sc_dev.dv_xname, __func__, phy, reg, data));

sys/dev/usb/if_udav.c

1503

if (phy != 0) {

sys/dev/usb/if_udav.c

1505

sc->sc_dev.dv_xname, __func__, phy));

sys/dev/usb/if_ure.c

523

ure_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_ure.c

543

ure_miibus_writereg(struct device *dev, int phy, int reg, int val)

sys/dev/usb/if_url.c

1268

url_int_miibus_readreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_url.c

1279

sc->sc_dev.dv_xname, __func__, phy, reg));

sys/dev/usb/if_url.c

1290

if (phy != 0) {

sys/dev/usb/if_url.c

1292

sc->sc_dev.dv_xname, __func__, phy));

sys/dev/usb/if_url.c

1334

sc->sc_dev.dv_xname, __func__, phy, reg, val));

sys/dev/usb/if_url.c

1341

url_int_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/usb/if_url.c

1351

sc->sc_dev.dv_xname, __func__, phy, reg, data));

sys/dev/usb/if_url.c

1362

if (phy != 0) {

sys/dev/usb/if_url.c

1364

sc->sc_dev.dv_xname, __func__, phy));

sys/dev/usb/if_url.c

1427

url_ext_miibus_redreg(struct device *dev, int phy, int reg)

sys/dev/usb/if_url.c

1433

sc->sc_dev.dv_xname, __func__, phy, reg));

sys/dev/usb/if_url.c

1445

url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);

sys/dev/usb/if_url.c

1464

sc->sc_dev.dv_xname, __func__, phy, reg, val));

sys/dev/usb/if_url.c

1471

url_ext_miibus_writereg(struct device *dev, int phy, int reg, int data)

sys/dev/usb/if_url.c

1476

sc->sc_dev.dv_xname, __func__, phy, reg, data));

sys/dev/usb/if_url.c

1489

url_csr_write_1(sc, URL_PHYADD, phy);

sys/dev/usb/if_zyd.c

2159

desc->phy = zyd_plcp_signal(rate);

sys/dev/usb/if_zyd.c

2161

desc->phy |= ZYD_TX_PHY_OFDM;

sys/dev/usb/if_zyd.c

2163

desc->phy |= ZYD_TX_PHY_5GHZ;

sys/dev/usb/if_zyd.c

2165

desc->phy |= ZYD_TX_PHY_SHPREAMBLE;

sys/dev/usb/if_zydreg.h

974

uint8_t phy;