lib/libcrypto/lhash/lhash.h

157

#define LHM_lh_insert(type, lh, inst) \

lib/libcrypto/lhash/lhash.h

159

CHECKED_PTR_OF(type, inst)))

lib/libcrypto/lhash/lhash.h

160

#define LHM_lh_retrieve(type, lh, inst) \

lib/libcrypto/lhash/lhash.h

162

CHECKED_PTR_OF(type, inst)))

lib/libcrypto/lhash/lhash.h

163

#define LHM_lh_delete(type, lh, inst) \

lib/libcrypto/lhash/lhash.h

165

CHECKED_PTR_OF(type, inst)))

lib/libcrypto/stack/safestack.h

1641

#define lh_ADDED_OBJ_insert(lh,inst) LHM_lh_insert(ADDED_OBJ,lh,inst)

lib/libcrypto/stack/safestack.h

1642

#define lh_ADDED_OBJ_retrieve(lh,inst) LHM_lh_retrieve(ADDED_OBJ,lh,inst)

lib/libcrypto/stack/safestack.h

1643

#define lh_ADDED_OBJ_delete(lh,inst) LHM_lh_delete(ADDED_OBJ,lh,inst)

lib/libcrypto/stack/safestack.h

1652

#define lh_CONF_VALUE_insert(lh,inst) LHM_lh_insert(CONF_VALUE,lh,inst)

lib/libcrypto/stack/safestack.h

1653

#define lh_CONF_VALUE_retrieve(lh,inst) LHM_lh_retrieve(CONF_VALUE,lh,inst)

lib/libcrypto/stack/safestack.h

1654

#define lh_CONF_VALUE_delete(lh,inst) LHM_lh_delete(CONF_VALUE,lh,inst)

lib/libcrypto/stack/safestack.h

1663

#define lh_ERR_STATE_insert(lh,inst) LHM_lh_insert(ERR_STATE,lh,inst)

lib/libcrypto/stack/safestack.h

1664

#define lh_ERR_STATE_retrieve(lh,inst) LHM_lh_retrieve(ERR_STATE,lh,inst)

lib/libcrypto/stack/safestack.h

1665

#define lh_ERR_STATE_delete(lh,inst) LHM_lh_delete(ERR_STATE,lh,inst)

lib/libcrypto/stack/safestack.h

1674

#define lh_ERR_STRING_DATA_insert(lh,inst) LHM_lh_insert(ERR_STRING_DATA,lh,inst)

lib/libcrypto/stack/safestack.h

1675

#define lh_ERR_STRING_DATA_retrieve(lh,inst) LHM_lh_retrieve(ERR_STRING_DATA,lh,inst)

lib/libcrypto/stack/safestack.h

1676

#define lh_ERR_STRING_DATA_delete(lh,inst) LHM_lh_delete(ERR_STRING_DATA,lh,inst)

lib/libcrypto/stack/safestack.h

1685

#define lh_EX_CLASS_ITEM_insert(lh,inst) LHM_lh_insert(EX_CLASS_ITEM,lh,inst)

lib/libcrypto/stack/safestack.h

1686

#define lh_EX_CLASS_ITEM_retrieve(lh,inst) LHM_lh_retrieve(EX_CLASS_ITEM,lh,inst)

lib/libcrypto/stack/safestack.h

1687

#define lh_EX_CLASS_ITEM_delete(lh,inst) LHM_lh_delete(EX_CLASS_ITEM,lh,inst)

lib/libcrypto/stack/safestack.h

1696

#define lh_FUNCTION_insert(lh,inst) LHM_lh_insert(FUNCTION,lh,inst)

lib/libcrypto/stack/safestack.h

1697

#define lh_FUNCTION_retrieve(lh,inst) LHM_lh_retrieve(FUNCTION,lh,inst)

lib/libcrypto/stack/safestack.h

1698

#define lh_FUNCTION_delete(lh,inst) LHM_lh_delete(FUNCTION,lh,inst)

lib/libcrypto/stack/safestack.h

1707

#define lh_OBJ_NAME_insert(lh,inst) LHM_lh_insert(OBJ_NAME,lh,inst)

lib/libcrypto/stack/safestack.h

1708

#define lh_OBJ_NAME_retrieve(lh,inst) LHM_lh_retrieve(OBJ_NAME,lh,inst)

lib/libcrypto/stack/safestack.h

1709

#define lh_OBJ_NAME_delete(lh,inst) LHM_lh_delete(OBJ_NAME,lh,inst)

lib/libcrypto/stack/safestack.h

1718

#define lh_OPENSSL_STRING_insert(lh,inst) LHM_lh_insert(OPENSSL_STRING,lh,inst)

lib/libcrypto/stack/safestack.h

1719

#define lh_OPENSSL_STRING_retrieve(lh,inst) LHM_lh_retrieve(OPENSSL_STRING,lh,inst)

lib/libcrypto/stack/safestack.h

1720

#define lh_OPENSSL_STRING_delete(lh,inst) LHM_lh_delete(OPENSSL_STRING,lh,inst)

lib/libcrypto/stack/safestack.h

1729

#define lh_SSL_SESSION_insert(lh,inst) LHM_lh_insert(SSL_SESSION,lh,inst)

lib/libcrypto/stack/safestack.h

1730

#define lh_SSL_SESSION_retrieve(lh,inst) LHM_lh_retrieve(SSL_SESSION,lh,inst)

lib/libcrypto/stack/safestack.h

1731

#define lh_SSL_SESSION_delete(lh,inst) LHM_lh_delete(SSL_SESSION,lh,inst)

sbin/ifconfig/ifconfig.c

2928

uint64_t type, subtype, inst;

sbin/ifconfig/ifconfig.c

2957

inst = IFM_INST(media_current);

sbin/ifconfig/ifconfig.c

2963

media_current = IFM_MAKEWORD(type, subtype, 0, inst);

sbin/ifconfig/ifconfig.c

2971

uint64_t type, subtype, options, inst, mode;

sbin/ifconfig/ifconfig.c

2982

inst = IFM_INST(media_current);

sbin/ifconfig/ifconfig.c

2986

media_current = IFM_MAKEWORD(type, subtype, options, inst) | mode;

sbin/ifconfig/ifconfig.c

2993

uint64_t type, subtype, options, inst;

sbin/ifconfig/ifconfig.c

3004

inst = IFM_INST(media_current);

sbin/ifconfig/ifconfig.c

3006

media_current = IFM_MAKEWORD(type, subtype, options, inst) |

sbin/ifconfig/ifconfig.c

3057

uint64_t type, subtype, options, inst;

sbin/ifconfig/ifconfig.c

3074

inst = strtonum(val, 0, IFM_INST_MAX, &errmsg);

sbin/ifconfig/ifconfig.c

3078

media_current = IFM_MAKEWORD(type, subtype, options, inst);

sbin/iked/proc.c

147

unsigned int src, dst, inst;

sbin/iked/proc.c

163

for (inst = 0; inst < ps->ps_instances[dst]; inst++) {

sbin/iked/proc.c

164

iev = &ps->ps_ievs[dst][inst];

sbin/iked/proc.c

166

ps->ps_pp->pp_pipes[dst][inst]) == -1)

sbin/iked/proc.c

194

for (inst = 0; inst < ps->ps_instances[dst]; inst++) {

sbin/iked/proc.c

195

if (proc_compose_imsg(ps, dst, inst, IMSG_CTL_PROCREADY,

sbin/iked/proc.c

200

ps->ps_connecting, ps->ps_title[dst], inst + 1);

sys/arch/alpha/alpha/db_disasm.c

820

alpha_instruction inst;

sys/arch/alpha/alpha/db_disasm.c

822

inst.bits = db_get_value(loc, 4, 0);

sys/arch/alpha/alpha/db_disasm.c

824

loc += alpha_print_instruction(loc, inst, altfmt);

sys/arch/alpha/alpha/db_trace.c

174

u_int inst;

sys/arch/alpha/alpha/db_trace.c

211

inst = *(u_int *)(pc - i);

sys/arch/alpha/alpha/db_trace.c

218

if (name[0] == '?' && inst_return(inst))

sys/arch/alpha/alpha/db_trace.c

224

if ((inst & 0xffff0000) == 0x23de0000)

sys/arch/alpha/alpha/db_trace.c

226

framesize -= disp(inst) / sizeof (u_long);

sys/arch/alpha/alpha/db_trace.c

227

else if ((inst & 0xfc1f0000) == 0xb41e0000)

sys/arch/alpha/alpha/db_trace.c

229

slot[rega(inst)] =

sys/arch/alpha/alpha/db_trace.c

230

frame + disp(inst) / sizeof (u_long);

sys/arch/alpha/alpha/db_trace.c

231

else if ((inst & 0xfc000fe0) == 0x44000400 &&

sys/arch/alpha/alpha/db_trace.c

232

rega(inst) == regb(inst)) {

sys/arch/alpha/alpha/db_trace.c

235

if (rega(inst) != 31)

sys/arch/alpha/alpha/db_trace.c

236

slot[rega(inst)] = slot[regc(inst)];

sys/arch/alpha/alpha/db_trace.c

237

slot[regc(inst)] = 0;

sys/arch/alpha/alpha/db_trace.c

242

} else if (db_inst_load(inst))

sys/arch/alpha/alpha/db_trace.c

244

slot[rega(inst)] = 0;

sys/arch/alpha/alpha/db_trace.c

245

else if (opcode[inst >> 26].opc_fmt == OPC_OP)

sys/arch/alpha/alpha/db_trace.c

247

slot[regc(inst)] = 0;

sys/arch/alpha/alpha/fp_complete.c

146

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

149

inst.bits = bits;

sys/arch/alpha/alpha/fp_complete.c

152

alpha_shadow.uop |= 1UL << inst.generic_format.opcode;

sys/arch/alpha/alpha/fp_complete.c

237

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

239

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

247

switch(inst.float_format.function) {

sys/arch/alpha/alpha/fp_complete.c

250

sts(inst.float_detail.fb, &sfb, p);

sys/arch/alpha/alpha/fp_complete.c

252

ldt(inst.float_detail.fc, &tfc, p);

sys/arch/alpha/alpha/fp_complete.c

255

if(inst.float_detail.src == 2) {

sys/arch/alpha/alpha/fp_complete.c

256

stt(inst.float_detail.fb, &tfb, p);

sys/arch/alpha/alpha/fp_complete.c

258

lds(inst.float_detail.fc, &sfc, p);

sys/arch/alpha/alpha/fp_complete.c

264

this_cannot_happen(5, inst.generic_format.opcode);

sys/arch/alpha/alpha/fp_complete.c

266

ldt(inst.float_detail.fc, &tfc, p);

sys/arch/alpha/alpha/fp_complete.c

274

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

276

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

277

stt(inst.float_detail.fb, &tfb, p);

sys/arch/alpha/alpha/fp_complete.c

281

ldt(inst.float_detail.fc, &tfc, p);

sys/arch/alpha/alpha/fp_complete.c

288

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

290

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

291

switch(inst.float_detail.src) {

sys/arch/alpha/alpha/fp_complete.c

293

this_cannot_happen(3, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

301

this_cannot_happen(4, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

305

stt(inst.float_detail.fb, &tfb, p);

sys/arch/alpha/alpha/fp_complete.c

309

alpha_ldt(inst.float_detail.fc, &tfc);

sys/arch/alpha/alpha/fp_complete.c

325

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

327

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

328

stt(inst.float_detail.fb, &tfb, p);

sys/arch/alpha/alpha/fp_complete.c

330

alpha_ldt(inst.float_detail.fc, &tfc); /* yes, ldt */

sys/arch/alpha/alpha/fp_complete.c

504

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

506

inst.bits = bits;

sys/arch/alpha/alpha/fp_complete.c

507

switch(inst.generic_format.opcode) {

sys/arch/alpha/alpha/fp_complete.c

510

this_cannot_happen(2, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

513

if (inst.float_format.function == op_cvtql_sv ||

sys/arch/alpha/alpha/fp_complete.c

514

inst.float_format.function == op_cvtql_v) {

sys/arch/alpha/alpha/fp_complete.c

515

alpha_stt(inst.float_detail.fb, &tfb);

sys/arch/alpha/alpha/fp_complete.c

517

alpha_lds(inst.float_detail.fc, &sfc);

sys/arch/alpha/alpha/fp_complete.c

521

this_cannot_happen(3, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

528

switch(inst.float_detail.src) {

sys/arch/alpha/alpha/fp_complete.c

530

sts(inst.float_detail.fb, &sfb, p);

sys/arch/alpha/alpha/fp_complete.c

531

if (inst.float_detail.opclass == 10)

sys/arch/alpha/alpha/fp_complete.c

533

else if (inst.float_detail.opclass & ~3) {

sys/arch/alpha/alpha/fp_complete.c

534

this_cannot_happen(1, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

537

sts(inst.float_detail.fa, &sfa, p);

sys/arch/alpha/alpha/fp_complete.c

538

sfc.i = (*swfp_s[inst.float_detail.opclass])(

sys/arch/alpha/alpha/fp_complete.c

541

lds(inst.float_detail.fc, &sfc, p);

sys/arch/alpha/alpha/fp_complete.c

545

if (inst.float_detail.opclass >= 12)

sys/arch/alpha/alpha/fp_complete.c

546

(*swfp_cvt[inst.float_detail.opclass - 12])(

sys/arch/alpha/alpha/fp_complete.c

547

inst.bits, p);

sys/arch/alpha/alpha/fp_complete.c

549

stt(inst.float_detail.fb, &tfb, p);

sys/arch/alpha/alpha/fp_complete.c

550

if (inst.float_detail.opclass == 10)

sys/arch/alpha/alpha/fp_complete.c

553

stt(inst.float_detail.fa, &tfa, p);

sys/arch/alpha/alpha/fp_complete.c

554

tfc.i = (*swfp_t[inst.float_detail

sys/arch/alpha/alpha/fp_complete.c

557

ldt(inst.float_detail.fc, &tfc, p);

sys/arch/alpha/alpha/fp_complete.c

571

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

576

(u_int32_t *)&inst))) {

sys/arch/alpha/alpha/fp_complete.c

589

rm = inst.float_detail.rnd;

sys/arch/alpha/alpha/fp_complete.c

596

alpha_fp_interpret(p, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

619

alpha_instruction inst;

sys/arch/alpha/alpha/fp_complete.c

662

inst = tsw[pc - win_begin];

sys/arch/alpha/alpha/fp_complete.c

663

op_class = 1UL << inst.generic_format.opcode;

sys/arch/alpha/alpha/fp_complete.c

665

a1 &= ~(1UL << (inst.operate_generic_format.rc + 32));

sys/arch/alpha/alpha/fp_complete.c

668

a1 &= ~(1UL << inst.operate_generic_format.rc);

sys/arch/alpha/alpha/fp_complete.c

672

if (inst.mem_format.displacement == op_trapb ||

sys/arch/alpha/alpha/fp_complete.c

673

inst.mem_format.displacement == op_excb)

sys/arch/alpha/alpha/trap.c

696

alpha_instruction inst;

sys/arch/alpha/alpha/trap.c

709

if (copyinsn(p, (u_int32_t *)inst_pc, (u_int32_t *)&inst) != 0) {

sys/arch/alpha/alpha/trap.c

718

switch (inst.generic_format.opcode) {

sys/arch/alpha/alpha/trap.c

723

regptr = irp(p, inst.mem_format.rb);

sys/arch/alpha/alpha/trap.c

728

memaddr += inst.mem_format.displacement;

sys/arch/alpha/alpha/trap.c

730

regptr = irp(p, inst.mem_format.ra);

sys/arch/alpha/alpha/trap.c

732

if (inst.mem_format.opcode == op_ldwu ||

sys/arch/alpha/alpha/trap.c

733

inst.mem_format.opcode == op_stw) {

sys/arch/alpha/alpha/trap.c

740

if (inst.mem_format.opcode == op_ldbu) {

sys/arch/alpha/alpha/trap.c

748

} else if (inst.mem_format.opcode == op_ldwu) {

sys/arch/alpha/alpha/trap.c

756

} else if (inst.mem_format.opcode == op_stw) {

sys/arch/alpha/alpha/trap.c

763

} else if (inst.mem_format.opcode == op_stb) {

sys/arch/alpha/alpha/trap.c

774

if (inst.operate_generic_format.function == op_sextb &&

sys/arch/alpha/alpha/trap.c

775

inst.operate_generic_format.ra == 31) {

sys/arch/alpha/alpha/trap.c

778

if (inst.operate_generic_format.is_lit) {

sys/arch/alpha/alpha/trap.c

779

b = inst.operate_lit_format.literal;

sys/arch/alpha/alpha/trap.c

781

if (inst.operate_reg_format.sbz != 0)

sys/arch/alpha/alpha/trap.c

783

regptr = irp(p, inst.operate_reg_format.rb);

sys/arch/alpha/alpha/trap.c

787

regptr = irp(p, inst.operate_generic_format.rc);

sys/arch/alpha/alpha/trap.c

792

if (inst.operate_generic_format.function == op_sextw &&

sys/arch/alpha/alpha/trap.c

793

inst.operate_generic_format.ra == 31) {

sys/arch/alpha/alpha/trap.c

796

if (inst.operate_generic_format.is_lit) {

sys/arch/alpha/alpha/trap.c

797

w = inst.operate_lit_format.literal;

sys/arch/alpha/alpha/trap.c

799

if (inst.operate_reg_format.sbz != 0)

sys/arch/alpha/alpha/trap.c

801

regptr = irp(p, inst.operate_reg_format.rb);

sys/arch/alpha/alpha/trap.c

805

regptr = irp(p, inst.operate_generic_format.rc);

sys/arch/alpha/include/db_machdep.h

51

#define BKPT_SET(inst) BKPT_INST

sys/arch/amd64/amd64/db_disasm.c

1031

db_disasm_esc(vaddr_t loc, int inst, int short_addr, int size, int rex,

sys/arch/amd64/amd64/db_disasm.c

1041

fp = &db_Esc_inst[inst - 0xd8][f_reg(regmodrm, 0)];

sys/arch/amd64/amd64/db_disasm.c

1125

int inst;

sys/arch/amd64/amd64/db_disasm.c

1129

struct inst * ip;

sys/arch/amd64/amd64/db_disasm.c

1147

get_value_inc(inst, loc, 1, 0);

sys/arch/amd64/amd64/db_disasm.c

1160

switch (inst) {

sys/arch/amd64/amd64/db_disasm.c

1205

get_value_inc(inst, loc, 1, 0);

sys/arch/amd64/amd64/db_disasm.c

1211

if ((repe || repne) && inst == 0x0f)

sys/arch/amd64/amd64/db_disasm.c

1221

if (inst >= 0x40 && inst <= 0x4f) {

sys/arch/amd64/amd64/db_disasm.c

1223

rex = inst;

sys/arch/amd64/amd64/db_disasm.c

1226

get_value_inc(inst, loc, 1, 0);

sys/arch/amd64/amd64/db_disasm.c

1229

if (inst >= 0xd8 && inst <= 0xdf) {

sys/arch/amd64/amd64/db_disasm.c

123

struct inst db_Grp7[] = {

sys/arch/amd64/amd64/db_disasm.c

1230

loc = db_disasm_esc(loc, inst, short_addr, size, rex, seg);

sys/arch/amd64/amd64/db_disasm.c

1234

if (inst == 0x0f) {

sys/arch/amd64/amd64/db_disasm.c

1235

get_value_inc(inst, loc, 1, 0);

sys/arch/amd64/amd64/db_disasm.c

1236

if (inst == 0x0f) {

sys/arch/amd64/amd64/db_disasm.c

1240

ip = db_inst_0f[inst>>4];

sys/arch/amd64/amd64/db_disasm.c

1244

ip = &ip[inst&0xf];

sys/arch/amd64/amd64/db_disasm.c

1246

ip = &db_inst_table[inst];

sys/arch/amd64/amd64/db_disasm.c

1260

ip = (struct inst *)ip->i_extra;

sys/arch/amd64/amd64/db_disasm.c

1268

ip = (struct inst *)ip->i_extra;

sys/arch/amd64/amd64/db_disasm.c

1354

db_printf("%s", db_reg[size][f_rm(inst, rex)]);

sys/arch/amd64/amd64/db_disasm.c

1357

db_printf("%s", db_reg[LONG][f_rm(inst, rex)]);

sys/arch/amd64/amd64/db_disasm.c

1363

db_printf("%s", db_seg_reg[f_reg(inst, 0)]);

sys/arch/amd64/amd64/db_disasm.c

139

struct inst db_Grp9[] = {

sys/arch/amd64/amd64/db_disasm.c

1480

if (altfmt == 0 && (inst == 0xe9 || inst == 0xeb)) {

sys/arch/amd64/amd64/db_disasm.c

165

struct inst db_Grp0f1e[] = {

sys/arch/amd64/amd64/db_disasm.c

176

struct inst db_inst_0f0x[] = {

sys/arch/amd64/amd64/db_disasm.c

196

struct inst db_inst_0f1x[] = {

sys/arch/amd64/amd64/db_disasm.c

216

struct inst db_inst_0f2x[] = {

sys/arch/amd64/amd64/db_disasm.c

236

struct inst db_inst_0f3x[] = {

sys/arch/amd64/amd64/db_disasm.c

256

struct inst db_inst_0f8x[] = {

sys/arch/amd64/amd64/db_disasm.c

276

struct inst db_inst_0f9x[] = {

sys/arch/amd64/amd64/db_disasm.c

296

struct inst db_inst_0fax[] = {

sys/arch/amd64/amd64/db_disasm.c

316

struct inst db_inst_0fbx[] = {

sys/arch/amd64/amd64/db_disasm.c

336

struct inst db_inst_0fcx[] = {

sys/arch/amd64/amd64/db_disasm.c

356

struct inst *db_inst_0f[] = {

sys/arch/amd64/amd64/db_disasm.c

531

struct inst db_Grp3[] = {

sys/arch/amd64/amd64/db_disasm.c

542

struct inst db_Grp4[] = {

sys/arch/amd64/amd64/db_disasm.c

553

struct inst db_Grp5[] = {

sys/arch/amd64/amd64/db_disasm.c

564

struct inst db_inst_table[256] = {

sys/arch/amd64/amd64/db_disasm.c

855

struct inst db_bad_inst =

sys/arch/amd64/include/db_machdep.h

54

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/arm/arm/db_interface.c

349

db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code,

sys/arch/arm/arm/db_interface.c

354

if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) {

sys/arch/arm/include/db_machdep.h

57

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/arm/include/db_machdep.h

95

vaddr_t db_branch_taken(u_int inst, vaddr_t pc, db_regs_t *regs);

sys/arch/arm64/include/db_machdep.h

58

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/hppa/hppa/db_disasm.c

1138

static const struct inst illeg = { 0, 0, 0, 0, 0, "???", 0 };

sys/arch/hppa/hppa/db_disasm.c

1139

static const struct inst *so_sysop[0xd0];

sys/arch/hppa/hppa/db_disasm.c

1140

static const struct inst *so_mmuop[0x50];

sys/arch/hppa/hppa/db_disasm.c

1141

static const struct inst *so_arith[0x80];

sys/arch/hppa/hppa/db_disasm.c

1142

static const struct inst *so_loads[0x50];

sys/arch/hppa/hppa/db_disasm.c

1143

static const struct inst *so_cldw [0x0A];

sys/arch/hppa/hppa/db_disasm.c

1144

static const struct inst *so_cldd [0x0A];

sys/arch/hppa/hppa/db_disasm.c

1145

static const struct inst *so_float[0x04];

sys/arch/hppa/hppa/db_disasm.c

1146

static const struct inst *so_fstq [0x0A];

sys/arch/hppa/hppa/db_disasm.c

1147

static const struct inst *so_ebran[0x08];

sys/arch/hppa/hppa/db_disasm.c

1148

static const struct inst *so_addit[0x02];

sys/arch/hppa/hppa/db_disasm.c

1149

static const struct inst *so_addi [0x02];

sys/arch/hppa/hppa/db_disasm.c

1150

static const struct inst *so_subi [0x02];

sys/arch/hppa/hppa/db_disasm.c

1151

static const struct inst *so_shext[0x08];

sys/arch/hppa/hppa/db_disasm.c

1152

static const struct inst *so_deps [0x08];

sys/arch/hppa/hppa/db_disasm.c

1154

#define ILLEG (const struct inst **)&illeg

sys/arch/hppa/hppa/db_disasm.c

1235

register const struct inst *i;

sys/arch/hppa/hppa/db_disasm.c

1275

m->subops = (const struct inst **)i;

sys/arch/hppa/hppa/db_disasm.c

1294

addDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1303

unitDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1315

iaDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1328

shdDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1341

extrDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1351

vextrDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1361

depDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1371

vdepDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1381

depiDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1390

vdepiDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1504

ldDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1530

stDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1555

ldxDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1588

stsDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1610

stbysDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1632

limmDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1641

blDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1662

brDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1670

bvDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1678

beDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1699

cbDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1716

cbiDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1733

bbDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1750

ariDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1765

scDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1795

mmgtDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1851

brkDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

1858

floatDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

2037

coprDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

2123

lpkDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

2156

diagDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

2173

fmpysubDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

2187

fmpyaddDasm(const struct inst *i, OFS ofs, int w)

sys/arch/hppa/hppa/db_disasm.c

2209

register const struct inst *i;

sys/arch/hppa/hppa/db_disasm.c

2232

i = (const struct inst *)m->subops;

sys/arch/hppa/hppa/db_disasm.c

759

int (*dasmfcn)(const struct inst *, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

766

const struct inst **subops; /* pointer to table of subops indexed by

sys/arch/hppa/hppa/db_disasm.c

897

int blDasm(const struct inst *i, OFS ofs, int w);

sys/arch/hppa/hppa/db_disasm.c

898

int ldDasm(const struct inst *, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

899

int stDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

900

int addDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

901

int unitDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

902

int iaDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

903

int shdDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

904

int extrDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

905

int vextrDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

906

int depDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

907

int vdepDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

908

int depiDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

909

int vdepiDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

910

int limmDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

911

int brkDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

912

int lpkDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

913

int fmpyaddDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

914

int fmpysubDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

915

int floatDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

916

int coprDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

917

int diagDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

918

int scDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

919

int mmgtDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

920

int ldxDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

921

int stsDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

922

int stbysDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

923

int brDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

924

int bvDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

925

int beDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

926

int cbDasm(const struct inst *i,OFS ofs, int);

sys/arch/hppa/hppa/db_disasm.c

927

int cbiDasm(const struct inst *i,OFS ofs, int);

sys/arch/hppa/hppa/db_disasm.c

928

int bbDasm(const struct inst *i,OFS ofs, int);

sys/arch/hppa/hppa/db_disasm.c

929

int ariDasm(const struct inst *i, OFS, int);

sys/arch/hppa/hppa/db_disasm.c

989

static const struct inst instrs[] = {

sys/arch/hppa/include/db_machdep.h

41

#define BKPT_SET(inst) BKPT_INST

sys/arch/i386/i386/db_disasm.c

1007

fp = &db_Esc_inst[inst - 0xd8][f_reg(regmodrm)];

sys/arch/i386/i386/db_disasm.c

1091

int inst;

sys/arch/i386/i386/db_disasm.c

1095

struct inst * ip;

sys/arch/i386/i386/db_disasm.c

1109

get_value_inc(inst, loc, 1, 0);

sys/arch/i386/i386/db_disasm.c

1119

switch (inst) {

sys/arch/i386/i386/db_disasm.c

1158

get_value_inc(inst, loc, 1, 0);

sys/arch/i386/i386/db_disasm.c

1161

if (inst >= 0xd8 && inst <= 0xdf) {

sys/arch/i386/i386/db_disasm.c

1162

loc = db_disasm_esc(loc, inst, short_addr, size, seg);

sys/arch/i386/i386/db_disasm.c

1167

if (inst == 0x0f) {

sys/arch/i386/i386/db_disasm.c

1168

get_value_inc(inst, loc, 1, 0);

sys/arch/i386/i386/db_disasm.c

1169

ip = db_inst_0f[inst>>4];

sys/arch/i386/i386/db_disasm.c

1173

ip = &ip[inst&0xf];

sys/arch/i386/i386/db_disasm.c

1175

ip = &db_inst_table[inst];

sys/arch/i386/i386/db_disasm.c

1189

ip = (struct inst *)ip->i_extra;

sys/arch/i386/i386/db_disasm.c

1197

ip = (struct inst *)ip->i_extra;

sys/arch/i386/i386/db_disasm.c

124

struct inst db_Grp7[] = {

sys/arch/i386/i386/db_disasm.c

1275

db_printf("%s", db_reg[size][f_rm(inst)]);

sys/arch/i386/i386/db_disasm.c

1278

db_printf("%s", db_reg[LONG][f_rm(inst)]);

sys/arch/i386/i386/db_disasm.c

1284

db_printf("%s", db_seg_reg[f_reg(inst)]);

sys/arch/i386/i386/db_disasm.c

1397

if (altfmt == 0 && (inst == 0xe9 || inst == 0xeb)) {

sys/arch/i386/i386/db_disasm.c

140

struct inst db_Grp9[] = {

sys/arch/i386/i386/db_disasm.c

166

struct inst db_inst_0f0x[] = {

sys/arch/i386/i386/db_disasm.c

186

struct inst db_inst_0f2x[] = {

sys/arch/i386/i386/db_disasm.c

206

struct inst db_inst_0f3x[] = {

sys/arch/i386/i386/db_disasm.c

226

struct inst db_inst_0f8x[] = {

sys/arch/i386/i386/db_disasm.c

246

struct inst db_inst_0f9x[] = {

sys/arch/i386/i386/db_disasm.c

266

struct inst db_inst_0fax[] = {

sys/arch/i386/i386/db_disasm.c

286

struct inst db_inst_0fbx[] = {

sys/arch/i386/i386/db_disasm.c

306

struct inst db_inst_0fcx[] = {

sys/arch/i386/i386/db_disasm.c

326

struct inst *db_inst_0f[] = {

sys/arch/i386/i386/db_disasm.c

501

struct inst db_Grp3[] = {

sys/arch/i386/i386/db_disasm.c

512

struct inst db_Grp4[] = {

sys/arch/i386/i386/db_disasm.c

523

struct inst db_Grp5[] = {

sys/arch/i386/i386/db_disasm.c

534

struct inst db_inst_table[256] = {

sys/arch/i386/i386/db_disasm.c

825

struct inst db_bad_inst =

sys/arch/i386/i386/db_disasm.c

998

db_disasm_esc(vaddr_t loc, int inst, int short_addr, int size, char *seg)

sys/arch/i386/i386/db_trace.c

80

int inst;

sys/arch/i386/i386/db_trace.c

88

inst = db_get_value((int)argp, 4, 0);

sys/arch/i386/i386/db_trace.c

89

if ((inst & 0xff) == 0x59) /* popl %ecx */

sys/arch/i386/i386/db_trace.c

91

else if ((inst & 0xffff) == 0xc483) /* addl %n, %esp */

sys/arch/i386/i386/db_trace.c

92

args = ((inst >> 16) & 0xff) / 4;

sys/arch/i386/include/db_machdep.h

51

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/m88k/include/db_machdep.h

54

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/m88k/m88k/db_disasm.c

1045

m88k_print_instruction(int cpu, u_int iadr, u_int32_t inst)

sys/arch/m88k/m88k/db_disasm.c

1053

if (inst == 0) {

sys/arch/m88k/m88k/db_disasm.c

1058

if ((inst & p->mask) == p->match) {

sys/arch/m88k/m88k/db_disasm.c

1059

if ((*p->opfun)(cpu, inst, p->opcode, iadr)) {

sys/arch/m88k/m88k/db_disasm.c

1067

db_printf("\t.word\t0x%x\n", inst);

sys/arch/m88k/m88k/db_disasm.c

323

oimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

325

int32_t Linst = inst & 0xffff;

sys/arch/m88k/m88k/db_disasm.c

326

u_int32_t H6inst = inst >> 26;

sys/arch/m88k/m88k/db_disasm.c

327

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

328

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

348

ctrlregs(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

350

u_int32_t dir = (inst >> 14) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

351

u_int32_t sfu = (inst >> 11) & 0x07;

sys/arch/m88k/m88k/db_disasm.c

352

u_int32_t creg = (inst >> 5) & 0x3f;

sys/arch/m88k/m88k/db_disasm.c

353

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

354

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

355

u_int32_t rs2 = (inst >> 0) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

382

sindou(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

384

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

385

u_int32_t td = (inst >> 5) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

386

u_int32_t t2 = (inst >> 7) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

387

u_int32_t t1 = (inst >> 9) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

388

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

389

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

390

u_int32_t checkbits = (inst >> 11) & 0x0f;

sys/arch/m88k/m88k/db_disasm.c

391

u_int32_t rf = (inst >> 15) & 0x01;

sys/arch/m88k/m88k/db_disasm.c

426

if ((inst & 0x200) != 0) /* does not use the RF bit... */

sys/arch/m88k/m88k/db_disasm.c

467

jump(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

469

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

472

if ((inst & (1 << 10)) != 0)

sys/arch/m88k/m88k/db_disasm.c

483

instset(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

485

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

486

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

487

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

488

u_int32_t checkbits = (inst >> 10) & 0x3f;

sys/arch/m88k/m88k/db_disasm.c

489

u_int32_t H6inst = (inst >> 26) & 0x3f;

sys/arch/m88k/m88k/db_disasm.c

493

db_printf("\t\tr%d, 0x%04x", rs1, inst & 0xffff);

sys/arch/m88k/m88k/db_disasm.c

515

obranch(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

517

u_int32_t disp = inst & 0x3ffffff;

sys/arch/m88k/m88k/db_disasm.c

520

if ((inst & (1 << 26)) != 0)

sys/arch/m88k/m88k/db_disasm.c

532

brcond(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

534

u_int32_t match = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

535

u_int32_t rs = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

536

u_int32_t disp = inst & 0xffff;

sys/arch/m88k/m88k/db_disasm.c

537

int bcnd = ((inst >> 27) & 0x03) == 1;

sys/arch/m88k/m88k/db_disasm.c

544

if ((inst & (1 << 26)) != 0)

sys/arch/m88k/m88k/db_disasm.c

563

otrap(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

565

u_int32_t vecno = inst & 0x1ff;

sys/arch/m88k/m88k/db_disasm.c

566

u_int32_t match = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

567

u_int32_t rs = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

568

int tcnd = ((inst >> 12) & 0x0f) == 0xe;

sys/arch/m88k/m88k/db_disasm.c

586

obit(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

588

u_int32_t rs = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

589

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

590

u_int32_t width = (inst >> 5) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

591

u_int32_t offset = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

594

if (((inst >> 10) & 0x3f) != 0x2a) /* rot */

sys/arch/m88k/m88k/db_disasm.c

603

bitman(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

605

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

606

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

607

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

616

immem(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

618

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

619

u_int32_t rs = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

620

u_int32_t st_lda = (inst >> 28) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

621

u_int32_t aryno = (inst >> 26) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

664

db_printf("0x%x", inst & 0xffff);

sys/arch/m88k/m88k/db_disasm.c

671

nimmem(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

673

u_int32_t scaled = (inst >> 9) & 0x01;

sys/arch/m88k/m88k/db_disasm.c

674

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

675

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

676

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

677

u_int32_t st_lda = (inst >> 12) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

678

u_int32_t aryno = (inst >> 10) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

703

if ((inst & (1 << 26)) == 0)

sys/arch/m88k/m88k/db_disasm.c

709

if ((inst & (1 << 26)) == 0)

sys/arch/m88k/m88k/db_disasm.c

711

if ((inst & (1 << 7)) != 0)

sys/arch/m88k/m88k/db_disasm.c

724

if (st_lda != 0x03 && (inst & (1 << 8)) != 0)

sys/arch/m88k/m88k/db_disasm.c

745

lognim(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

747

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

748

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

749

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

752

if ((inst & (1 << 10)) != 0)

sys/arch/m88k/m88k/db_disasm.c

762

onimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

764

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

765

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

766

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

767

u_int32_t carry = (inst >> 8) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

771

if ((inst & (1 << 11)) == 0) {

sys/arch/m88k/m88k/db_disasm.c

795

pinst(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)

sys/arch/m88k/m88k/db_disasm.c

797

u_int32_t rd = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

798

u_int32_t rs1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

799

u_int32_t rs2 = inst & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

800

u_int32_t tfield = (inst >> 5) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

801

u_int32_t pfunc = (inst >> 11) & 0x1f;

sys/arch/m88k/m88k/db_disasm.c

808

db_printf(".%d", (inst >> 5) & 0x3c);

sys/arch/m88k/m88k/db_disasm.c

814

u_int32_t sfield = (inst >> 7) & 0x03;

sys/arch/m88k/m88k/db_disasm.c

832

db_printf("\tr%d, r%d, %d", rd, rs1, (inst >> 5) & 0x3f);

sys/arch/m88k/m88k/db_sstep.c

100

switch (inst >> (32 - 5)) {

sys/arch/m88k/m88k/db_sstep.c

104

inst = (inst & 0x03ffffff) << 2;

sys/arch/m88k/m88k/db_sstep.c

106

if (inst & 0x08000000)

sys/arch/m88k/m88k/db_sstep.c

107

inst |= 0xf0000000;

sys/arch/m88k/m88k/db_sstep.c

108

return (pc + inst);

sys/arch/m88k/m88k/db_sstep.c

114

inst = (inst & 0x0000ffff) << 2;

sys/arch/m88k/m88k/db_sstep.c

116

if (inst & 0x00020000)

sys/arch/m88k/m88k/db_sstep.c

117

inst |= 0xfffc0000;

sys/arch/m88k/m88k/db_sstep.c

118

return (pc + inst);

sys/arch/m88k/m88k/db_sstep.c

121

regno = inst & 0x1f;

sys/arch/m88k/m88k/db_sstep.c

146

u_int inst;

sys/arch/m88k/m88k/db_sstep.c

152

db_read_bytes(pc, sizeof(inst), (caddr_t)&inst);

sys/arch/m88k/m88k/db_sstep.c

158

if (inst_branch_or_call(inst)) {

sys/arch/m88k/m88k/db_sstep.c

159

brpc = branch_taken(inst, pc, regs);

sys/arch/m88k/m88k/db_sstep.c

91

branch_taken(u_int inst, vaddr_t pc, db_regs_t *regs)

sys/arch/m88k/m88k/db_trace.c

467

uint32_t inst;

sys/arch/m88k/m88k/db_trace.c

49

br_dest(vaddr_t addr, u_int inst)

sys/arch/m88k/m88k/db_trace.c

504

if (!db_trace_get_val(check_addr, &inst))

sys/arch/m88k/m88k/db_trace.c

507

if (ST_R30_R31_IMM(inst)) {

sys/arch/m88k/m88k/db_trace.c

51

inst = (inst & 0x03ffffff) << 2;

sys/arch/m88k/m88k/db_trace.c

511

} else if (SUBU_R31_R31_IMM(inst)) {

sys/arch/m88k/m88k/db_trace.c

528

if (JMP_R1(inst) || JMPN_R1(inst)) {

sys/arch/m88k/m88k/db_trace.c

53

if (inst & 0x08000000)

sys/arch/m88k/m88k/db_trace.c

54

inst |= 0xf0000000;

sys/arch/m88k/m88k/db_trace.c

55

return (addr + inst);

sys/arch/m88k/m88k/db_trace.c

550

if (!db_trace_get_val(function_addr, &inst))

sys/arch/m88k/m88k/db_trace.c

552

if (!SUBU_R31_R31_IMM(inst))

sys/arch/m88k/m88k/db_trace.c

569

*stack += IMM16VAL(inst);

sys/arch/m88k/m88k/db_trace.c

575

if (!db_trace_get_val(check_addr, &inst))

sys/arch/m88k/m88k/db_trace.c

577

if (SUBU_R31_R31_IMM(inst)) {

sys/arch/m88k/m88k/db_trace.c

580

*stack += IMM16VAL(inst);

sys/arch/m88k/m88k/db_trace.c

603

if (!db_trace_get_val(check_addr, &inst))

sys/arch/m88k/m88k/db_trace.c

606

if (SUBU_R31_R31_IMM(inst)) {

sys/arch/m88k/m88k/db_trace.c

607

r31 -= IMM16VAL(inst);

sys/arch/m88k/m88k/db_trace.c

613

flags = m88k_instruction_info(inst);

sys/arch/m88k/m88k/db_trace.c

616

s1 = (inst >> 16) & 0x1f;

sys/arch/m88k/m88k/db_trace.c

617

d = (inst >> 21) & 0x1f;

sys/arch/m88k/m88k/db_trace.c

624

tried_to_save_r1 = r31 + IMM16VAL(inst);

sys/arch/m88k/m88k/db_trace.c

626

d, check_addr, r31 + IMM16VAL(inst)));

sys/arch/m88k/m88k/db_trace.c

627

if (db_trace_get_val(r31 + IMM16VAL(inst),

sys/arch/m88k/m88k/db_trace.c

634

IMM16VAL(inst) + 4;

sys/arch/m88k/m88k/db_trace.c

636

d + 1, check_addr, r31 + IMM16VAL(inst)));

sys/arch/m88k/m88k/db_trace.c

637

if (db_trace_get_val(r31 + IMM16VAL(inst) + 4,

sys/arch/m88k/m88k/trap.c

1426

ss_branch_taken(u_int inst, vaddr_t pc, struct reg *regs)

sys/arch/m88k/m88k/trap.c

1435

switch (inst >> (32 - 5)) {

sys/arch/m88k/m88k/trap.c

1439

inst = (inst & 0x03ffffff) << 2;

sys/arch/m88k/m88k/trap.c

1441

if (inst & 0x08000000)

sys/arch/m88k/m88k/trap.c

1442

inst |= 0xf0000000;

sys/arch/m88k/m88k/trap.c

1443

return (pc + inst);

sys/arch/m88k/m88k/trap.c

1449

inst = (inst & 0x0000ffff) << 2;

sys/arch/m88k/m88k/trap.c

1451

if (inst & 0x00020000)

sys/arch/m88k/m88k/trap.c

1452

inst |= 0xfffc0000;

sys/arch/m88k/m88k/trap.c

1453

return (pc + inst);

sys/arch/m88k/m88k/trap.c

1456

regno = inst & 0x1f; /* get the register value */

sys/arch/mips64/mips64/fp_emulate.c

1550

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

1553

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

1555

switch (inst.RType.rs) {

sys/arch/mips64/mips64/fp_emulate.c

1557

if (inst.FRType.fd != 0 || inst.FRType.func != 0)

sys/arch/mips64/mips64/fp_emulate.c

1559

if (inst.FRType.ft != ZERO)

sys/arch/mips64/mips64/fp_emulate.c

1560

regs[inst.FRType.ft] = (int32_t)

sys/arch/mips64/mips64/fp_emulate.c

1562

[FPBASE + inst.FRType.fs];

sys/arch/mips64/mips64/fp_emulate.c

1565

if (inst.FRType.fd != 0 || inst.FRType.func != 0)

sys/arch/mips64/mips64/fp_emulate.c

1567

if ((tf->sr & SR_FR_32) != 0 || (inst.FRType.fs & 1) == 0) {

sys/arch/mips64/mips64/fp_emulate.c

1568

if (inst.FRType.ft != ZERO)

sys/arch/mips64/mips64/fp_emulate.c

1569

regs[inst.FRType.ft] =

sys/arch/mips64/mips64/fp_emulate.c

1570

fpu_load(p, tf, FMT_L, inst.FRType.fs);

sys/arch/mips64/mips64/fp_emulate.c

1574

if (inst.FRType.fd != 0 || inst.FRType.func != 0)

sys/arch/mips64/mips64/fp_emulate.c

1576

if (inst.FRType.ft != ZERO) {

sys/arch/mips64/mips64/fp_emulate.c

1577

switch (inst.FRType.fs) {

sys/arch/mips64/mips64/fp_emulate.c

1588

regs[inst.FRType.ft] = (int64_t)cval;

sys/arch/mips64/mips64/fp_emulate.c

1592

if (inst.FRType.fd != 0 || inst.FRType.func != 0)

sys/arch/mips64/mips64/fp_emulate.c

1594

((uint64_t *)p->p_md.md_regs)[FPBASE + inst.FRType.fs] =

sys/arch/mips64/mips64/fp_emulate.c

1595

(int32_t)regs[inst.FRType.ft];

sys/arch/mips64/mips64/fp_emulate.c

1598

if (inst.FRType.fd != 0 || inst.FRType.func != 0)

sys/arch/mips64/mips64/fp_emulate.c

1600

if ((tf->sr & SR_FR_32) != 0 || (inst.FRType.fs & 1) == 0) {

sys/arch/mips64/mips64/fp_emulate.c

1601

fpu_store(p, tf, FMT_L, inst.FRType.fs,

sys/arch/mips64/mips64/fp_emulate.c

1602

regs[inst.FRType.ft]);

sys/arch/mips64/mips64/fp_emulate.c

1606

if (inst.FRType.fd != 0 || inst.FRType.func != 0)

sys/arch/mips64/mips64/fp_emulate.c

1608

cval = (int32_t)regs[inst.FRType.ft];

sys/arch/mips64/mips64/fp_emulate.c

1609

switch (inst.FRType.fs) {

sys/arch/mips64/mips64/fp_emulate.c

1626

cc = (inst.RType.rt & COPz_BC_CC_MASK) >> COPz_BC_CC_SHIFT;

sys/arch/mips64/mips64/fp_emulate.c

1627

nd = inst.RType.rt & COPz_BCL_TF_MASK;

sys/arch/mips64/mips64/fp_emulate.c

1628

istf = inst.RType.rt & COPz_BC_TF_MASK;

sys/arch/mips64/mips64/fp_emulate.c

1641

dest = tf->pc + 4 + ((short)inst.IType.imm << 2);

sys/arch/mips64/mips64/fp_emulate.c

166

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

1679

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

1684

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

1685

switch (inst.FRType.func) {

sys/arch/mips64/mips64/fp_emulate.c

1687

if (inst.FQType.fs != 0)

sys/arch/mips64/mips64/fp_emulate.c

1689

va = (vaddr_t)regs[inst.FQType.fr] +

sys/arch/mips64/mips64/fp_emulate.c

1690

(vaddr_t)regs[inst.FQType.ft];

sys/arch/mips64/mips64/fp_emulate.c

1699

if ((tf->sr & SR_FR_32) != 0 || (inst.FQType.fd & 1) == 0)

sys/arch/mips64/mips64/fp_emulate.c

1700

fpu_store(p, tf, FMT_L, inst.FQType.fd, ddata);

sys/arch/mips64/mips64/fp_emulate.c

1703

if (inst.FQType.fs != 0)

sys/arch/mips64/mips64/fp_emulate.c

1705

va = (vaddr_t)regs[inst.FQType.fr] +

sys/arch/mips64/mips64/fp_emulate.c

1706

(vaddr_t)regs[inst.FQType.ft];

sys/arch/mips64/mips64/fp_emulate.c

1715

((uint64_t *)p->p_md.md_regs)[FPBASE + inst.FQType.fd] = wdata;

sys/arch/mips64/mips64/fp_emulate.c

1718

if (inst.FQType.fd != 0)

sys/arch/mips64/mips64/fp_emulate.c

1720

va = (vaddr_t)regs[inst.FQType.fr] +

sys/arch/mips64/mips64/fp_emulate.c

1721

(vaddr_t)regs[inst.FQType.ft];

sys/arch/mips64/mips64/fp_emulate.c

1726

if ((tf->sr & SR_FR_32) != 0 || (inst.FQType.fs & 1) == 0)

sys/arch/mips64/mips64/fp_emulate.c

1727

ddata = fpu_load(p, tf, FMT_L, inst.FQType.fs);

sys/arch/mips64/mips64/fp_emulate.c

1738

if (inst.FQType.fd != 0)

sys/arch/mips64/mips64/fp_emulate.c

1740

va = (vaddr_t)regs[inst.FQType.fr] +

sys/arch/mips64/mips64/fp_emulate.c

1741

(vaddr_t)regs[inst.FQType.ft];

sys/arch/mips64/mips64/fp_emulate.c

1746

wdata = ((uint64_t *)p->p_md.md_regs)[FPBASE + inst.FQType.fs];

sys/arch/mips64/mips64/fp_emulate.c

1768

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

1773

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

1774

switch (inst.IType.op) {

sys/arch/mips64/mips64/fp_emulate.c

1776

va = (vaddr_t)regs[inst.IType.rs] + (int16_t)inst.IType.imm;

sys/arch/mips64/mips64/fp_emulate.c

1785

if ((tf->sr & SR_FR_32) != 0 || (inst.IType.rt & 1) == 0)

sys/arch/mips64/mips64/fp_emulate.c

1786

fpu_store(p, tf, FMT_L, inst.IType.rt, ddata);

sys/arch/mips64/mips64/fp_emulate.c

1789

va = (vaddr_t)regs[inst.IType.rs] + (int16_t)inst.IType.imm;

sys/arch/mips64/mips64/fp_emulate.c

1798

((uint64_t *)p->p_md.md_regs)[FPBASE + inst.IType.rt] = wdata;

sys/arch/mips64/mips64/fp_emulate.c

1801

va = (vaddr_t)regs[inst.IType.rs] + (int16_t)inst.IType.imm;

sys/arch/mips64/mips64/fp_emulate.c

1806

if ((tf->sr & SR_FR_32) != 0 || (inst.IType.rt & 1) == 0)

sys/arch/mips64/mips64/fp_emulate.c

1807

ddata = fpu_load(p, tf, FMT_L, inst.IType.rt);

sys/arch/mips64/mips64/fp_emulate.c

1818

va = (vaddr_t)regs[inst.IType.rs] + (int16_t)inst.IType.imm;

sys/arch/mips64/mips64/fp_emulate.c

1823

wdata = ((uint64_t *)p->p_md.md_regs)[FPBASE + inst.IType.rt];

sys/arch/mips64/mips64/fp_emulate.c

1841

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

1845

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

1846

if ((inst.RType.rt & 0x02) != 0 || inst.RType.shamt != 0)

sys/arch/mips64/mips64/fp_emulate.c

1849

cc = inst.RType.rt >> 2;

sys/arch/mips64/mips64/fp_emulate.c

1850

istf = inst.RType.rt & COPz_BC_TF_MASK;

sys/arch/mips64/mips64/fp_emulate.c

1853

if (inst.RType.rd != ZERO)

sys/arch/mips64/mips64/fp_emulate.c

1854

regs[inst.RType.rd] = regs[inst.RType.rs];

sys/arch/mips64/mips64/fp_emulate.c

219

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

245

switch (inst.FRType.op) {

sys/arch/mips64/mips64/fp_emulate.c

253

switch (inst.FRType.func) {

sys/arch/mips64/mips64/fp_emulate.c

282

switch (inst.RType.rs) {

sys/arch/mips64/mips64/fp_emulate.c

305

switch (inst.FQType.op4) {

sys/arch/mips64/mips64/fp_emulate.c

307

switch (inst.FRType.func) {

sys/arch/mips64/mips64/fp_emulate.c

446

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

450

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

453

switch (inst.FRType.op) {

sys/arch/mips64/mips64/fp_emulate.c

466

switch (inst.FRType.op) {

sys/arch/mips64/mips64/fp_emulate.c

477

switch (inst.RType.rs) {

sys/arch/mips64/mips64/fp_emulate.c

491

switch (inst.FQType.op4) {

sys/arch/mips64/mips64/fp_emulate.c

493

switch (inst.FRType.func) {

sys/arch/mips64/mips64/fp_emulate.c

522

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

592

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

598

fpu_op = fpu_ops1[inst.FRType.func];

sys/arch/mips64/mips64/fp_emulate.c

609

switch (inst.FRType.fmt) {

sys/arch/mips64/mips64/fp_emulate.c

629

ft = inst.FRType.ft;

sys/arch/mips64/mips64/fp_emulate.c

630

fs = inst.FRType.fs;

sys/arch/mips64/mips64/fp_emulate.c

631

fd = inst.FRType.fd;

sys/arch/mips64/mips64/fp_emulate.c

643

fpu_c(p, tf, inst.FRType.fmt, ft, fs, fd, inst.FRType.func);

sys/arch/mips64/mips64/fp_emulate.c

645

return (*fpu_op)(p, tf, inst.FRType.fmt, ft, fs, fd);

sys/arch/mips64/mips64/fp_emulate.c

654

InstFmt inst;

sys/arch/mips64/mips64/fp_emulate.c

668

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/fp_emulate.c

674

fpu_op = fpu_ops1x[inst.FQType.op4];

sys/arch/mips64/mips64/fp_emulate.c

682

switch (inst.FQType.fmt3) {

sys/arch/mips64/mips64/fp_emulate.c

698

fr = inst.FQType.fr;

sys/arch/mips64/mips64/fp_emulate.c

699

ft = inst.FQType.ft;

sys/arch/mips64/mips64/fp_emulate.c

700

fs = inst.FQType.fs;

sys/arch/mips64/mips64/fp_emulate.c

701

fd = inst.FQType.fd;

sys/arch/mips64/mips64/fp_emulate.c

711

return (*fpu_op)(p, tf, inst.FRType.fmt, fr, ft, fs, fd);

sys/arch/mips64/mips64/mips64_machdep.c

352

InstFmt inst;

sys/arch/mips64/mips64/mips64_machdep.c

354

inst.word = insn;

sys/arch/mips64/mips64/mips64_machdep.c

355

switch (inst.JType.op) {

sys/arch/mips64/mips64/mips64_machdep.c

357

switch (inst.RType.func) {

sys/arch/mips64/mips64/mips64_machdep.c

366

switch (inst.IType.rt) {

sys/arch/mips64/mips64/mips64_machdep.c

395

switch (inst.RType.rs) {

sys/arch/mips64/mips64/trap.c

1347

InstFmt inst;

sys/arch/mips64/mips64/trap.c

1398

inst.word = *(uint32_t *)va;

sys/arch/mips64/mips64/trap.c

1399

if (inst_call(inst.word) || inst_return(inst.word)) {

sys/arch/mips64/mips64/trap.c

1402

inst.word = *(uint32_t *)va;

sys/arch/mips64/mips64/trap.c

1405

switch (inst.JType.op) {

sys/arch/mips64/mips64/trap.c

1407

switch (inst.RType.func) {

sys/arch/mips64/mips64/trap.c

1414

if (inst.IType.rs == SP &&

sys/arch/mips64/mips64/trap.c

1415

inst.IType.rt == RA && ra == 0)

sys/arch/mips64/mips64/trap.c

1417

(int16_t)inst.IType.imm);

sys/arch/mips64/mips64/trap.c

1421

if (inst.IType.rs == SP &&

sys/arch/mips64/mips64/trap.c

1422

inst.IType.rt == SP &&

sys/arch/mips64/mips64/trap.c

1423

(int16_t)inst.IType.imm < 0 &&

sys/arch/mips64/mips64/trap.c

1425

framesize = -(int16_t)inst.IType.imm;

sys/arch/mips64/mips64/trap.c

1493

InstFmt inst;

sys/arch/mips64/mips64/trap.c

1502

inst = *(InstFmt *)&insn;

sys/arch/mips64/mips64/trap.c

1504

switch ((int)inst.JType.op) {

sys/arch/mips64/mips64/trap.c

1506

switch ((int)inst.RType.func) {

sys/arch/mips64/mips64/trap.c

1514

switch ((int)inst.IType.rt) {

sys/arch/mips64/mips64/trap.c

1540

if (inst.RType.rs == OP_BC) /* oh the irony */

sys/arch/mips64/mips64/trap.c

659

InstFmt inst;

sys/arch/mips64/mips64/trap.c

675

if (copyinsn(p, va, &inst.word) != 0) {

sys/arch/mips64/mips64/trap.c

682

if (inst.RType.op == OP_SPECIAL3 &&

sys/arch/mips64/mips64/trap.c

683

inst.RType.rs == 0 &&

sys/arch/mips64/mips64/trap.c

684

inst.RType.rd == 29 &&

sys/arch/mips64/mips64/trap.c

685

inst.RType.shamt == 0 &&

sys/arch/mips64/mips64/trap.c

686

inst.RType.func == OP_RDHWR) {

sys/arch/mips64/mips64/trap.c

687

regs[inst.RType.rt] = (register_t)TCB_GET(p);

sys/arch/mips64/mips64/trap.c

871

InstFmt inst;

sys/arch/mips64/mips64/trap.c

876

#define GetBranchDest(InstPtr, inst) \

sys/arch/mips64/mips64/trap.c

877

(InstPtr + 4 + ((short)inst.IType.imm << 2))

sys/arch/mips64/mips64/trap.c

879

inst.word = curinst;

sys/arch/mips64/mips64/trap.c

883

switch ((int)inst.JType.op) {

sys/arch/mips64/mips64/trap.c

885

switch ((int)inst.RType.func) {

sys/arch/mips64/mips64/trap.c

888

retAddr = (vaddr_t)regsPtr[inst.RType.rs];

sys/arch/mips64/mips64/trap.c

896

switch ((int)inst.IType.rt) {

sys/arch/mips64/mips64/trap.c

901

if ((int64_t)(regsPtr[inst.RType.rs]) < 0)

sys/arch/mips64/mips64/trap.c

902

retAddr = GetBranchDest(instPC, inst);

sys/arch/mips64/mips64/trap.c

910

if ((int64_t)(regsPtr[inst.RType.rs]) >= 0)

sys/arch/mips64/mips64/trap.c

911

retAddr = GetBranchDest(instPC, inst);

sys/arch/mips64/mips64/trap.c

922

retAddr = (inst.JType.target << 2) | (instPC & ~0x0fffffffUL);

sys/arch/mips64/mips64/trap.c

926

if (regsPtr[inst.RType.rs] == regsPtr[inst.RType.rt])

sys/arch/mips64/mips64/trap.c

927

retAddr = GetBranchDest(instPC, inst);

sys/arch/mips64/mips64/trap.c

933

if (regsPtr[inst.RType.rs] != regsPtr[inst.RType.rt])

sys/arch/mips64/mips64/trap.c

934

retAddr = GetBranchDest(instPC, inst);

sys/arch/mips64/mips64/trap.c

940

if ((int64_t)(regsPtr[inst.RType.rs]) <= 0)

sys/arch/mips64/mips64/trap.c

941

retAddr = GetBranchDest(instPC, inst);

sys/arch/mips64/mips64/trap.c

947

if ((int64_t)(regsPtr[inst.RType.rs]) > 0)

sys/arch/mips64/mips64/trap.c

948

retAddr = GetBranchDest(instPC, inst);

sys/arch/mips64/mips64/trap.c

953

switch (inst.RType.rs) {

sys/arch/mips64/mips64/trap.c

955

cc = (inst.RType.rt & COPz_BC_CC_MASK) >>

sys/arch/mips64/mips64/trap.c

957

if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)

sys/arch/mips64/mips64/trap.c

962

retAddr = GetBranchDest(instPC, inst);

sys/arch/powerpc/include/db_machdep.h

51

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/powerpc/powerpc/cpu_subr.c

40

uint32_t *inst;

sys/arch/powerpc/powerpc/cpu_subr.c

53

for (inst = p->s; inst < p->e; inst++)

sys/arch/powerpc/powerpc/cpu_subr.c

54

*inst = rfid_inst;

sys/arch/powerpc/powerpc/cpu_subr.c

79

for (inst = p->s; inst < p->e; inst++)

sys/arch/powerpc/powerpc/cpu_subr.c

80

*inst = nop_inst;

sys/arch/powerpc/powerpc/cpu_subr.c

87

for (inst = p->s; inst < p->e; inst++)

sys/arch/powerpc/powerpc/cpu_subr.c

88

*inst = nop_inst;

sys/arch/powerpc64/include/db_machdep.h

51

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/riscv64/include/db_machdep.h

64

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/riscv64/include/db_machdep.h

83

vaddr_t db_branch_taken(u_int inst, vaddr_t pc, db_regs_t *regs);

sys/arch/riscv64/riscv64/db_interface.c

425

db_trapper(vaddr_t addr, u_int inst, trapframe_t *frame, int fault_code)

sys/arch/sh/include/db_machdep.h

51

#define BKPT_SET(inst) BKPT_INST

sys/arch/sh/sh/db_interface.c

163

inst_call(int inst)

sys/arch/sh/sh/db_interface.c

166

inst >>= 16;

sys/arch/sh/sh/db_interface.c

168

return (inst & M_BSR) == I_BSR || (inst & M_BSRF) == I_BSRF ||

sys/arch/sh/sh/db_interface.c

169

(inst & M_JSR) == I_JSR;

sys/arch/sh/sh/db_interface.c

173

inst_return(int inst)

sys/arch/sh/sh/db_interface.c

176

inst >>= 16;

sys/arch/sh/sh/db_interface.c

178

return (inst & M_RTS) == I_RTS;

sys/arch/sh/sh/db_interface.c

182

inst_trap_return(int inst)

sys/arch/sh/sh/db_interface.c

185

inst >>= 16;

sys/arch/sh/sh/db_interface.c

187

return (inst & M_RTE) == I_RTE;

sys/arch/sh/sh/db_trace.c

188

int i, inst;

sys/arch/sh/sh/db_trace.c

198

inst = db_get_value(pc, 2, 0);

sys/arch/sh/sh/db_trace.c

201

if (inst == 0x6ef3) /* mov r15,r14 -- end of prologue */

sys/arch/sh/sh/db_trace.c

204

if (inst == 0x4f22) { /* sts.l pr,@-r15 */

sys/arch/sh/sh/db_trace.c

209

if (inst == 0x2fe6) { /* mov.l r14,@-r15 */

sys/arch/sh/sh/db_trace.c

214

if ((inst & 0xff0f) == 0x2f06) { /* mov.l r?,@-r15 */

sys/arch/sh/sh/db_trace.c

218

if ((inst & 0xff00) == 0x7f00) { /* add #n,r15 */

sys/arch/sh/sh/db_trace.c

219

int8_t n = inst & 0xff;

sys/arch/sh/sh/db_trace.c

229

if ((inst & 0xf000) == 0x9000) {

sys/arch/sh/sh/db_trace.c

232

unsigned int disp = (int)(inst & 0xff);

sys/arch/sparc64/include/db_machdep.h

109

int db_inst_trap_return(int inst);

sys/arch/sparc64/include/db_machdep.h

110

int db_inst_return(int inst);

sys/arch/sparc64/include/db_machdep.h

111

int db_inst_call(int inst);

sys/arch/sparc64/include/db_machdep.h

112

int db_inst_branch(int inst);

sys/arch/sparc64/include/db_machdep.h

113

int db_inst_unconditional_flow_transfer(int inst);

sys/arch/sparc64/include/db_machdep.h

114

vaddr_t db_branch_taken(int inst, vaddr_t pc, db_regs_t *regs);

sys/arch/sparc64/include/db_machdep.h

97

#define BKPT_SET(inst) (BKPT_INST)

sys/arch/sparc64/sparc64/db_interface.c

1165

db_branch_taken(int inst, vaddr_t pc, db_regs_t *regs)

sys/arch/sparc64/sparc64/db_interface.c

1170

insn.i_int = inst;

sys/arch/sparc64/sparc64/db_interface.c

1173

switch(inst & 0xffc00000) {

sys/arch/sparc64/sparc64/db_interface.c

1175

return pc + ((inst<<(32-19))>>((32-19)-2));

sys/arch/sparc64/sparc64/db_interface.c

1177

return pc + ((inst<<(32-22))>>((32-22)-2));

sys/arch/sparc64/sparc64/db_interface.c

1197

return pc + ((inst << 10) >> 8);

sys/arch/sparc64/sparc64/db_interface.c

1214

db_inst_branch(int inst)

sys/arch/sparc64/sparc64/db_interface.c

1218

insn.i_int = inst;

sys/arch/sparc64/sparc64/db_interface.c

1221

switch(inst & 0xffc00000) {

sys/arch/sparc64/sparc64/db_interface.c

1247

db_inst_call(int inst)

sys/arch/sparc64/sparc64/db_interface.c

1251

insn.i_int = inst;

sys/arch/sparc64/sparc64/db_interface.c

1258

return (insn.i_op3.i_op3 == IOP3_JMPL) && !db_inst_return(inst);

sys/arch/sparc64/sparc64/db_interface.c

1267

db_inst_unconditional_flow_transfer(int inst)

sys/arch/sparc64/sparc64/db_interface.c

1271

insn.i_int = inst;

sys/arch/sparc64/sparc64/db_interface.c

1273

if (db_inst_call(inst))

sys/arch/sparc64/sparc64/db_interface.c

1295

db_inst_return(int inst)

sys/arch/sparc64/sparc64/db_interface.c

1297

return (inst == I_JMPLri(I_G0, I_O7, 8) || /* ret */

sys/arch/sparc64/sparc64/db_interface.c

1298

inst == I_JMPLri(I_G0, I_I7, 8)); /* retl */

sys/arch/sparc64/sparc64/db_interface.c

1302

db_inst_trap_return(int inst)

sys/arch/sparc64/sparc64/db_interface.c

1306

insn.i_int = inst;

sys/ddb/db_run.c

333

u_int inst;

sys/ddb/db_run.c

339

inst = db_get_value(pc, sizeof(int), 0);

sys/ddb/db_run.c

340

if (inst_branch(inst) || inst_call(inst) || inst_return(inst)) {

sys/ddb/db_run.c

341

brpc = branch_taken(inst, pc, getreg_val, regs);

sys/dev/dt/dt_prov_kprobe.c

102

uint8_t *inst = (uint8_t *)symp->st_value;

sys/dev/dt/dt_prov_kprobe.c

109

if (inst[0] != 0xf3 || inst[1] != 0x0f ||

sys/dev/dt/dt_prov_kprobe.c

110

inst[2] != 0x1e || inst[3] != 0xfa)

sys/dev/dt/dt_prov_kprobe.c

115

if (inst[off] != 0x4c || inst[off + 1] != 0x8b || inst[off + 2] != 0x1d)

sys/dev/dt/dt_prov_kprobe.c

120

if (inst[off] != 0x4c || inst[off + 1] != 0x33 || inst[off + 2] != 0x1c)

sys/dev/dt/dt_prov_kprobe.c

125

if (inst[off] != SSF_INST)

sys/dev/dt/dt_prov_kprobe.c

129

if (inst[off + 1] != 0x48 || inst[off + 2] != 0x89 ||

sys/dev/dt/dt_prov_kprobe.c

130

inst[off + 3] != 0xe5)

sys/dev/dt/dt_prov_kprobe.c

163

uint8_t *inst = (uint8_t *)symp->st_value;

sys/dev/dt/dt_prov_kprobe.c

167

if (inst[off - 1] == 0xcc && inst[off] == RET_INST)

sys/dev/dt/dt_prov_kprobe.c

203

uint8_t *inst = (uint8_t *)symp->st_value;

sys/dev/dt/dt_prov_kprobe.c

206

if (*inst != SSF_INST)

sys/dev/dt/dt_prov_kprobe.c

245

while(*((uint8_t *)inst) == 0xcc)

sys/dev/dt/dt_prov_kprobe.c

246

(*(uint8_t *)inst) -= 1;

sys/dev/dt/dt_prov_kprobe.c

283

vaddr_t inst;

sys/dev/dt/dt_prov_kprobe.c

308

inst = symp->st_value;

sys/dev/dt/dt_prov_kprobe.c

312

if (inst < KERNBASE || inst >= (vaddr_t)&__kutext_end)

sys/dev/dt/dt_prov_kprobe.c

329

dtp->dtp_addr = inst + off;

sys/dev/dt/dt_prov_kprobe.c

345

dtp->dtp_addr = inst + off;

sys/dev/dt/dt_prov_kprobe.c

83

#define INSTTOIDX(inst) (ptr_hash(inst) & PPTMASK)

sys/dev/pci/bktr/bktr_core.c

2852

volatile unsigned int inst;

sys/dev/pci/bktr/bktr_core.c

2874

inst = OP_WRITE | OP_SOL | (cols);

sys/dev/pci/bktr/bktr_core.c

2893

*dma_prog++ = htole32(inst);

sys/dev/pci/bktr/bktr_core.c

2937

*dma_prog++ = htole32(inst);

sys/dev/pci/bktr/bktr_core.c

2964

u_int inst;

sys/dev/pci/bktr/bktr_core.c

2993

inst = OP_WRITE123 | OP_SOL | OP_EOL | (cols);

sys/dev/pci/bktr/bktr_core.c

3009

*dma_prog++ = htole32(inst);

sys/dev/pci/bktr/bktr_core.c

3054

*dma_prog++ = htole32(inst);

sys/dev/pci/bktr/bktr_core.c

3081

u_int inst;

sys/dev/pci/bktr/bktr_core.c

3097

inst = OP_WRITE123 | OP_SOL | OP_EOL | (cols);

sys/dev/pci/bktr/bktr_core.c

3112

*dma_prog++ = htole32(inst);

sys/dev/pci/bktr/bktr_core.c

3161

*dma_prog++ = htole32(inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1359

uint8_t ip, uint8_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1364

return adev->ip_versions[ip][inst] & ~0xFFU;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1368

uint8_t ip, uint8_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1371

return adev->ip_versions[ip][inst];

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1409

uint32_t inst, uint32_t reg_addr, char reg_name[],

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1481

#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1482

#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

153

u32 inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1840

enum amdgpu_uid_type type, uint8_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1843

enum amdgpu_uid_type type, uint8_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

823

int8_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

819

u32 inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

821

struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

265

u32 inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

130

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

287

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

295

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

299

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

300

hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

303

WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

309

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

338

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

340

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

342

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

344

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

346

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

351

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

355

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

357

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

468

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

493

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

496

watch_address_high, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

498

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

501

watch_address_low, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1018

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1049

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1075

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1082

uint32_t inst, unsigned int utimeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

141

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

211

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

292

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

344

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

475

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

516

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

679

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

84

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

891

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

96

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

48

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

53

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

63

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

67

uint32_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

110

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

182

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

278

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

330

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

461

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

503

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

591

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

634

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

84

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

97

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

106

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

167

struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

263

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

315

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

450

uint32_t pipe_id, uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

491

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

576

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

747

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

791

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

798

uint32_t inst, unsigned int utimeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

82

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

93

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

107

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

165

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

322

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

57

static int init_interrupts_v12(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

118

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

162

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

206

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

322

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

362

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

498

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

81

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

94

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

113

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

157

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

230

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

354

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

394

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

544

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

75

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

88

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

102

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1024

int *max_waves_per_cu, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1034

soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1046

amdgpu_gfx_select_se_sh(adev, se_idx, 0, 0xffffffff, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1067

inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1071

amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1072

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1104

uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1106

kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1111

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1113

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1119

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1121

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1124

kgd_gfx_v9_unlock_srbm(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1129

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1134

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1135

amdgpu_gfx_rlc_enter_safe_mode(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1137

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1140

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1141

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1150

amdgpu_gfx_rlc_exit_safe_mode(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1151

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1157

static int kgd_gfx_v9_hqd_dequeue_wait(struct amdgpu_device *adev, uint32_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1177

uint32_t inst, unsigned int utimeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1182

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1183

amdgpu_gfx_rlc_enter_safe_mode(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1185

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1188

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1189

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1198

inst, pipe_id, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1201

WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1203

if (!kgd_gfx_v9_hqd_dequeue_wait(adev, inst, utimeout))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1206

pr_debug("Attempting pipe reset on XCC %i pipe id %i\n", inst, pipe_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1211

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1212

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1214

if (kgd_gfx_v9_hqd_dequeue_wait(adev, inst, utimeout))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1219

inst, pipe_id, queue_id, !!queue_addr ? "succeeded!" : "failed!");

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1220

amdgpu_gfx_rlc_exit_safe_mode(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1221

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

161

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

169

kgd_gfx_v9_lock_srbm(adev, mec, pipe, 0, 0, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

171

WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

175

kgd_gfx_v9_unlock_srbm(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

226

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

234

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

238

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

241

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

242

WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

248

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

277

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

279

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

281

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

283

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

290

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

294

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

296

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

303

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

305

struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

312

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

320

spin_lock(&adev->gfx.kiq[inst].ring_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

347

spin_unlock(&adev->gfx.kiq[inst].ring_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

348

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

355

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

370

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

372

for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

373

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

376

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

486

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

492

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

493

act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

498

if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

499

high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

502

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

51

uint32_t queue, uint32_t vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

527

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

537

kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

54

soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

540

WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

557

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

561

temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

566

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

57

static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

572

kgd_gfx_v9_release_queue(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

59

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

629

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

635

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

636

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

64

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

645

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

69

kgd_gfx_v9_lock_srbm(adev, mec, pipe, queue_id, 0, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

81

void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

824

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

83

kgd_gfx_v9_unlock_srbm(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

90

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

906

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

909

*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

92

kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

94

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

95

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

951

struct kfd_cu_occupancy *queue_cnt, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

964

soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

965

reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

98

kgd_gfx_v9_unlock_srbm(adev, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

109

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

113

uint32_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

26

uint32_t sh_mem_bases, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

28

unsigned int vmid, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

30

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

34

struct mm_struct *mm, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

37

uint32_t doorbell_off, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

40

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

43

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

47

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

50

uint32_t sq_cmd, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

57

int *max_waves_per_cu, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

60

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

62

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

65

void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

94

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

99

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

2092

amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7800

uint32_t inst, uint32_t reg_addr, char reg_name[],

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7820

inst, reg_name, (uint32_t)expected_value,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7874

enum amdgpu_uid_type type, uint8_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7886

if (inst >= AMDGPU_UID_INST_MAX) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7888

inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7892

if (uid_info->uid[type][inst] != 0) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7896

uid_info->uid[type][inst], type, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7899

uid_info->uid[type][inst] = uid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7903

enum amdgpu_uid_type type, uint8_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7914

if (inst >= AMDGPU_UID_INST_MAX) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7916

inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7920

return uid_info->uid[type][inst];

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1035

uint16_t hw_id, uint8_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1044

harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1054

harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1057

harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1073

uint8_t inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1089

inst = ip->instance_number;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1091

if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1352

uint8_t inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1391

inst = ip->instance_number;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1393

if (amdgpu_discovery_validate_ip(adev, inst, hw_id))

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1414

adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1793

adev->vcn.inst[v].vcn_codec_disable_mask =

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

659

uint8_t inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

677

inst = ip->number_instance;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

679

if (amdgpu_discovery_validate_ip(adev, inst, hw_id))

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

686

if (inst == 0) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

454

ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

455

ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

727

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

729

struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

730

struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

752

inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

757

inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

761

inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

773

spin_lock(&adev->gfx.kiq[inst].ring_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

776

spin_unlock(&adev->gfx.kiq[inst].ring_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

789

spin_unlock(&adev->gfx.kiq[inst].ring_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

794

spin_unlock(&adev->gfx.kiq[inst].ring_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

148

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

432

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

50

#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

51

{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

29

int8_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

38

dev_inst = adev->ip_map.dev_inst[block][inst];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

43

dev_inst = inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

121

fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

167

WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

169

RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

176

tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

253

tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

299

!adev->jpeg.inst[i].ras_poison_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

302

r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

346

.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

347

.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

348

(uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

374

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

397

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

58

&adev->jpeg.inst[i].dpg_sram_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

59

&adev->jpeg.inst[i].dpg_sram_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

60

&adev->jpeg.inst[i].dpg_sram_cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

81

&adev->jpeg.inst[i].dpg_sram_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

82

&adev->jpeg.inst[i].dpg_sram_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

83

(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

86

amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

133

struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

55

*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

57

*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

98

*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

99

*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

463

if (adev->uvd.inst[i].ring.sched.ready &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

464

!adev->uvd.inst[i].ring.no_user_submission)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

486

if (adev->uvd.inst[i].ring_enc[j].sched.ready &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

487

!adev->uvd.inst[i].ring_enc[j].no_user_submission)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

499

if (adev->vcn.inst[i].ring_dec.sched.ready &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

500

!adev->vcn.inst[i].ring_dec.no_user_submission)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

512

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

513

if (adev->vcn.inst[i].ring_enc[j].sched.ready &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

514

!adev->vcn.inst[i].ring_enc[j].no_user_submission)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

529

if (adev->jpeg.inst[i].ring_dec[j].sched.ready &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

530

!adev->jpeg.inst[i].ring_dec[j].no_user_submission)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

383

#define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

384

ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1271

fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1273

fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

328

&adev->uvd.inst[j].vcpu_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

329

&adev->uvd.inst[j].gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

330

&adev->uvd.inst[j].cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

380

kvfree(adev->uvd.inst[j].saved_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

382

amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

383

&adev->uvd.inst[j].gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

384

(void **)&adev->uvd.inst[j].cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

386

amdgpu_ring_fini(&adev->uvd.inst[j].ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

389

amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

407

if (ring == &adev->uvd.inst[0].ring) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

443

if (adev->uvd.inst[j].vcpu_bo == NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

446

size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

447

ptr = adev->uvd.inst[j].cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

449

adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

450

if (!adev->uvd.inst[j].saved_bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

456

memset(adev->uvd.inst[j].saved_bo, 0, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

458

memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

484

if (adev->uvd.inst[i].vcpu_bo == NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

487

size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

488

ptr = adev->uvd.inst[i].cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

490

if (adev->uvd.inst[i].saved_bo != NULL) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

492

memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

495

kvfree(adev->uvd.inst[i].saved_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

496

adev->uvd.inst[i].saved_bo = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

505

memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

514

amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

522

struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

967

(start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h

62

struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1001

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1015

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

102

adev->vcn.inst[i].adev = adev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

103

adev->vcn.inst[i].inst = i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1037

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

107

r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

111

amdgpu_ucode_release(&adev->vcn.inst[i].fw);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

113

if (!adev->vcn.inst[0].fw) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1137

hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

114

r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1145

adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

118

amdgpu_ucode_release(&adev->vcn.inst[0].fw);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

122

adev->vcn.inst[i].fw = adev->vcn.inst[0].fw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1297

!adev->vcn.inst[i].ras_poison_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1300

r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1346

.mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1347

.ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1348

(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

136

rw_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround, "vcnwa");

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

137

rw_init(&adev->vcn.inst[i].vcn_pg_lock, "vcnpg");

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

138

rw_init(&adev->vcn.inst[i].engine_reset_mutex, "vcner");

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

139

atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

140

INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

141

atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1412

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1433

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

144

adev->vcn.inst[i].indirect_sram = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1453

if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1476

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1494

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1553

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

158

adev->vcn.inst[i].indirect_sram = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

165

adev->vcn.inst[i].using_unified_queue =

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

168

hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

169

adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

223

&adev->vcn.inst[i].vcpu_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

224

&adev->vcn.inst[i].gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

225

&adev->vcn.inst[i].cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

231

adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

233

adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

236

adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

239

adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

240

adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

241

adev->vcn.inst[i].fw_shared.log_offset = log_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

244

if (adev->vcn.inst[i].indirect_sram) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

248

&adev->vcn.inst[i].dpg_sram_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

249

&adev->vcn.inst[i].dpg_sram_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

250

&adev->vcn.inst[i].dpg_sram_cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

268

&adev->vcn.inst[i].dpg_sram_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

269

&adev->vcn.inst[i].dpg_sram_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

270

(void **)&adev->vcn.inst[i].dpg_sram_cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

272

kvfree(adev->vcn.inst[i].saved_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

274

amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

275

&adev->vcn.inst[i].gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

276

(void **)&adev->vcn.inst[i].cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

278

amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

280

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

281

amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

284

amdgpu_ucode_release(&adev->vcn.inst[i].fw);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

286

amdgpu_ucode_release(&adev->vcn.inst[0].fw);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

287

adev->vcn.inst[i].fw = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

293

mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

294

mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

300

int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

320

if (adev->vcn.inst[i].vcpu_bo == NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

323

size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

324

ptr = adev->vcn.inst[i].cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

326

adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

327

if (!adev->vcn.inst[i].saved_bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

331

memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

374

if (adev->vcn.inst[i].vcpu_bo == NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

377

size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

378

ptr = adev->vcn.inst[i].cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

380

if (adev->vcn.inst[i].saved_bo != NULL) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

382

memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

385

kvfree(adev->vcn.inst[i].saved_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

386

adev->vcn.inst[i].saved_bo = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

391

hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

395

memcpy_toio(adev->vcn.inst[i].cpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

396

adev->vcn.inst[i].fw->data + offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

436

if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

463

unsigned int i = vcn_inst->inst, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

468

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

473

!adev->vcn.inst[i].using_unified_queue) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

482

adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

502

struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

545

!adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

546

atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

548

atomic_dec(&ring->adev->vcn.inst[ring->me].total_submission_cnt);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

550

schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

565

WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

569

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

573

tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

634

ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

636

ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

638

ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

641

ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

804

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

817

if (adev->vcn.inst[ring->me].using_unified_queue) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

836

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

934

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

948

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

970

if (adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

156

*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

158

*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

209

*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

211

*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

302

int inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

348

struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

35

uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

98

#define vpe_get_reg_offset(vpe, inst, offset) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

99

((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

713

int inst = 0, i, j, r, n;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

733

xgmi_regs->inst_header.instance = inst++;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

787

int inst = 0, i, j, r, n;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

807

wafl_regs->inst_header.instance = inst++;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

900

int inst = 0, i, n, r, arr_size;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

932

usr_regs->inst_header.instance = inst++;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4715

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4727

inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4730

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4740

inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4743

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1541

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1553

inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1556

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1566

inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1569

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1353

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1365

inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1368

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1378

inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1381

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2188

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2200

inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2203

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6954

gfx_v9_0_ras_fields[i].inst != reg->inst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

838

gfx_v9_4_ras_fields[i].inst != reg->inst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1474

gfx_v9_4_2_ras_fields[i].inst != reg->inst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1012

uint32_t *ptr, num_xcc, inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1026

inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1029

ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1700

int i, inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1710

inst = adev->ip_map.logical_to_dev_inst ?

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1714

reg = adev->reg_offset[entry->hwip][inst][entry->segment] +

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

349

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

341

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

361

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

436

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

627

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

844

u32 j, inv_req, tmp, sem, req, ack, inst;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

857

inst = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

859

inst = vmhub;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

864

if (adev->gfx.kiq[inst].ring.sched.ready &&

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

870

1 << vmid, inst);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

889

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

891

tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

902

WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

904

WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

917

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

919

tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

932

WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

934

WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

958

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

447

amdgpu_fence_process(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

491

r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

495

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

498

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

503

adev->jpeg.internal.jpeg_pitch[0] = adev->jpeg.inst->external.jpeg_pitch[0] =

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

520

amdgpu_ring_fini(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

533

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

591

adev->jpeg.inst->ring_dec->funcs = &jpeg_v1_0_decode_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

601

adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

607

bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

610

mutex_lock(&adev->vcn.inst[0].vcn1_jpeg1_workaround);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

612

if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_dec))

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

615

for (cnt = 0; cnt < adev->vcn.inst[0].num_enc_rings; cnt++) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

616

if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_enc[cnt]))

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

103

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

108

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

114

adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

121

amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

161

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

337

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

758

amdgpu_fence_process(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

836

adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

846

adev->jpeg.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

847

adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

91

VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

116

VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

122

VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

128

VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

145

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

153

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

159

adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

171

amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

218

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

253

amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

299

static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

303

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

311

WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

313

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

318

WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

320

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

325

WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

328

static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

332

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

338

WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

343

struct amdgpu_ring *ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

638

amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

765

adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

767

adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

768

adev->jpeg.inst[i].ring_dec->me = i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

790

adev->jpeg.inst[i].irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

791

adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

793

adev->jpeg.inst[i].ras_poison_irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

794

adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

841

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

843

for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

846

jpeg_v2_6_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

106

VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

118

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

123

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

129

adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

136

amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

176

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

353

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

550

amdgpu_fence_process(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

628

adev->jpeg.inst->ring_dec->funcs = &jpeg_v3_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

638

adev->jpeg.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

639

adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

100

VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

106

VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

112

VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

124

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

130

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

136

adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

147

amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

186

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

231

amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

390

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

472

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

715

amdgpu_fence_process(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

793

adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

807

adev->jpeg.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

808

adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

810

adev->jpeg.inst->ras_poison_irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

811

adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

849

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

851

for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

854

jpeg_v4_0_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1109

uint32_t i, inst;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1114

for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1115

if (adev->jpeg.inst[inst].aid_id == i)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1118

if (inst >= adev->jpeg.num_jpeg_inst) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1127

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1130

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1133

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1136

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1139

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1142

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1145

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1148

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1253

adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1254

adev->jpeg.inst[i].ring_dec[j].me = i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1255

adev->jpeg.inst[i].ring_dec[j].pipe = j;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1258

adev->jpeg.inst[i].aid_id =

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1278

adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1280

adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1282

adev->jpeg.inst->ras_poison_irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1283

adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1407

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1409

for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1412

jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

147

amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1498

adev->jpeg.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1499

r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

154

VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

160

VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

176

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

178

ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

193

snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

194

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

201

adev->jpeg.inst[i].external.jpeg_pitch[j] =

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

220

amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

288

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

383

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

399

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

406

adev->jpeg.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

409

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

448

amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

543

static void jpeg_v4_0_3_start_inst(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

545

int jpeg_inst = GET_INST(JPEG, inst);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

559

jpeg_v4_0_3_disable_clock_gating(adev, inst);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

627

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

635

static void jpeg_v4_0_3_stop_inst(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

637

int jpeg_inst = GET_INST(JPEG, inst);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

643

jpeg_v4_0_3_enable_clock_gating(adev, inst);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

130

VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

136

VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

142

VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

159

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

164

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

170

adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

178

amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

231

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

307

static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

311

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

321

WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

323

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

328

WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

331

static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

335

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

345

WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

347

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

352

WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

374

static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

377

WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

379

SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

384

WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

388

WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

394

static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

397

WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

402

WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

404

SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

423

struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

445

adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

446

(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

513

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

756

amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

844

adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

845

adev->jpeg.inst[i].ring_dec->me = i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

861

adev->jpeg.inst[i].irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

862

adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

105

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

111

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

117

adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

124

amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

163

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

343

struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

354

adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

355

(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

427

struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

636

amdgpu_fence_process(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

714

adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

724

adev->jpeg.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

725

adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

93

VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1078

adev->jpeg.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1079

r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

145

amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

151

VCN_5_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

157

VCN_5_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

173

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

175

ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

185

snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

186

r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

193

adev->jpeg.inst[i].external.jpeg_pitch[j] =

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

212

amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

262

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

276

ring = adev->jpeg.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

280

adev->jpeg.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

283

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

319

amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

486

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

577

ring = &adev->jpeg.inst[i].ring_dec[j];

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

762

u32 i, inst;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

767

for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

768

if (adev->jpeg.inst[inst].aid_id == i)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

771

if (inst >= adev->jpeg.num_jpeg_inst) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

780

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

783

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

786

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

789

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

792

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

795

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

798

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

801

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

804

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

807

amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

914

adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_1_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

915

adev->jpeg.inst[i].ring_dec[j].me = i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

916

adev->jpeg.inst[i].ring_dec[j].pipe = j;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

919

adev->jpeg.inst[i].aid_id =

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

939

adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

941

adev->jpeg.inst->irq.funcs = &jpeg_v5_0_1_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

943

adev->jpeg.inst->ras_poison_irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

944

adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v5_0_1_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

983

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

985

for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

988

jpeg_v5_0_1_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

52

struct mmsch_v3_0_table_info inst[MMSCH_V3_0_VCN_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

63

struct mmsch_v4_0_table_info inst[MMSCH_V4_0_VCN_INSTANCES];

sys/dev/pci/drm/amd/amdgpu/nv.c

396

if (!adev->reg_offset[en->hwip][en->inst])

sys/dev/pci/drm/amd/amdgpu/nv.c

398

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

sys/dev/pci/drm/amd/amdgpu/soc15.c

445

if (!adev->reg_offset[en->hwip][en->inst])

sys/dev/pci/drm/amd/amdgpu/soc15.c

447

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

sys/dev/pci/drm/amd/amdgpu/soc15.h

100

#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \

sys/dev/pci/drm/amd/amdgpu/soc15.h

101

{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }

sys/dev/pci/drm/amd/amdgpu/soc15.h

55

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

62

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

72

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

81

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

90

#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg

sys/dev/pci/drm/amd/amdgpu/soc15.h

91

#define SOC15_REG_ENTRY_STR(ip, inst, reg) \

sys/dev/pci/drm/amd/amdgpu/soc15.h

92

{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }

sys/dev/pci/drm/amd/amdgpu/soc15.h

94

#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc15.h

97

#define SOC15_REG_ENTRY_OFFSET_INST(entry, inst) \

sys/dev/pci/drm/amd/amdgpu/soc15.h

98

(adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

100

#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

101

amdgpu_device_wait_on_rreg(adev, inst, \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

102

(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

105

#define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

106

amdgpu_device_wait_on_rreg(adev, inst, \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

107

(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

113

#define WREG32_RLC_EX(prefix, reg, value, inst) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

118

uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

119

uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

120

uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

138

#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

139

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

151

#define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

153

uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

155

uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

156

uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

157

uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

158

uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

169

#define RREG32_SOC15_RLC(ip, inst, reg) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

170

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

172

#define WREG32_SOC15_RLC(ip, inst, reg, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

174

uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

175

__WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP, inst); \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

178

#define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

180

uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

181

WREG32_RLC_EX(prefix, target_reg, value, inst); \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

191

#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

192

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

194

#define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

195

__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

198

#define RREG32_SOC15_EXT(ip, inst, reg, ext) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

199

RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

202

#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

203

WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

28

#define GET_INST(ip, inst) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

30

adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

36

#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

37

#define SOC15_REG_OFFSET1(ip, inst, reg, offset) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

38

(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

40

#define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

42

amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

45

#define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

47

amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

66

#define RREG32_SOC15(ip, inst, reg) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

67

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

68

0, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

72

#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

74

#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

75

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

76

AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

78

#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

79

__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

80

(offset), 0, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

82

#define WREG32_SOC15(ip, inst, reg, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

83

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

84

value, 0, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

89

#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

90

__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

92

#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

93

__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

94

value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

96

#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

97

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

98

value, 0, ip##_HWIP, inst)

sys/dev/pci/drm/amd/amdgpu/soc21.c

317

if (!adev->reg_offset[en->hwip][en->inst])

sys/dev/pci/drm/amd/amdgpu/soc21.c

319

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

sys/dev/pci/drm/amd/amdgpu/soc24.c

177

if (!adev->reg_offset[en->hwip][en->inst])

sys/dev/pci/drm/amd/amdgpu/soc24.c

179

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

203

adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

250

addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

267

addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

271

addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

332

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

527

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

539

adev->uvd.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

540

adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

564

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

572

ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

574

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

584

ptr = adev->uvd.inst[0].cpu_addr;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

656

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

116

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

124

ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

126

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

162

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

289

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

585

addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

602

addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

606

addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

713

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

802

adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

812

adev->uvd.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

813

adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

109

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

117

ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

119

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

153

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

287

lower_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

289

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

321

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

629

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

904

adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

914

adev->uvd.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

915

adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1180

adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1183

adev->uvd.inst->srbm_soft_reset = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1192

if (!adev->uvd.inst->srbm_soft_reset)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1204

if (!adev->uvd.inst->srbm_soft_reset)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1206

srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1234

if (!adev->uvd.inst->srbm_soft_reset)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

125

if (ring == &adev->uvd.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1260

amdgpu_fence_process(&adev->uvd.inst->ring);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1264

amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1270

amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

156

if (ring == &adev->uvd.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1635

adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1638

adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1648

adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1661

adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1663

adev->uvd.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1665

adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

387

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

394

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

406

adev->uvd.inst->ring_enc[i].funcs = NULL;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

408

adev->uvd.inst->irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

414

ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

416

r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

427

ring = &adev->uvd.inst->ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

430

&adev->uvd.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

451

amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

467

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

508

ring = &adev->uvd.inst->ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

613

lower_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

615

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

728

struct amdgpu_ring *ring = &adev->uvd.inst->ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

868

ring = &adev->uvd.inst->ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

875

ring = &adev->uvd.inst->ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

95

if (ring == &adev->uvd.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1117

ring = &adev->uvd.inst[k].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1124

ring = &adev->uvd.inst[k].ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

123

if (ring == &adev->uvd.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1498

amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1501

amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1505

amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1607

adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1608

adev->uvd.inst[i].ring.me = i;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

161

if (ring == &adev->uvd.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1621

adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1622

adev->uvd.inst[j].ring_enc[i].me = j;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1641

adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1642

adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

411

r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

417

r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

448

ring = &adev->uvd.inst[j].ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

452

&adev->uvd.inst[j].irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

459

ring = &adev->uvd.inst[j].ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

474

&adev->uvd.inst[j].irq, 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

507

amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

536

ring = &adev->uvd.inst[j].ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

577

ring = &adev->uvd.inst[j].ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

696

lower_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

698

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

707

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

709

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

714

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

716

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

762

WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

763

*adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

764

adev->uvd.inst[i].ring_enc[0].wptr = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

765

adev->uvd.inst[i].ring_enc[0].wptr_old = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

820

ring = &adev->uvd.inst[i].ring;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

838

lower_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

840

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

850

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

852

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

857

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

859

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

89

if (ring == &adev->uvd.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

923

ring = &adev->uvd.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

979

ring = &adev->uvd.inst[k].ring;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1002

ring = &adev->vcn.inst->ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1009

ring = &adev->vcn.inst->ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1029

struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

108

adev->vcn.inst[0].num_enc_rings = 2;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

109

adev->vcn.inst[0].set_pg_state = vcn_v1_0_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1300

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1307

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1309

adev->vcn.inst[inst_idx].pause_state.fw_based,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1310

adev->vcn.inst[inst_idx].pause_state.jpeg,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1333

ring = &adev->vcn.inst->ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1340

ring = &adev->vcn.inst->ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1358

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1362

if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1364

adev->vcn.inst[inst_idx].pause_state.fw_based,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1365

adev->vcn.inst[inst_idx].pause_state.jpeg,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

137

VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1393

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1418

adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

142

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

144

&adev->vcn.inst->irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1446

struct amdgpu_vcn_inst *vinst = adev->vcn.inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

155

adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

157

task_set(&adev->vcn.inst[0].idle_work.work.task,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

159

&adev->vcn.inst[0].idle_work.work);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1678

if (ring == &adev->vcn.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

168

ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1695

if (ring == &adev->vcn.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

171

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1712

if (ring == &adev->vcn.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

176

adev->vcn.inst[0].internal.scratch9 = adev->vcn.inst->external.scratch9 =

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

178

adev->vcn.inst[0].internal.data0 = adev->vcn.inst->external.data0 =

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

180

adev->vcn.inst[0].internal.data1 = adev->vcn.inst->external.data1 =

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1818

amdgpu_fence_process(&adev->vcn.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

182

adev->vcn.inst[0].internal.cmd = adev->vcn.inst->external.cmd =

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1821

amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1824

amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

184

adev->vcn.inst[0].internal.nop = adev->vcn.inst->external.nop =

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

187

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1881

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1882

fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1892

if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1897

adev->vcn.inst->pause_dpg_mode(vcn_inst, &new_state);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

190

ring = &adev->vcn.inst->ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1900

fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1901

fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1911

schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1918

bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1920

mutex_lock(&adev->vcn.inst[0].vcn1_jpeg1_workaround);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1922

if (amdgpu_fence_wait_empty(ring->adev->jpeg.inst->ring_dec))

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

193

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1946

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1947

fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1954

if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1964

adev->vcn.inst->pause_dpg_mode(adev->vcn.inst, &new_state);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1970

schedule_delayed_work(&ring->adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1971

mutex_unlock(&ring->adev->vcn.inst[0].vcn1_jpeg1_workaround);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

199

adev->vcn.inst[0].pause_dpg_mode = vcn_v1_0_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

202

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

205

amdgpu_vcn_fwlog_init(adev->vcn.inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2105

if (reg == PACKET0(p->adev->vcn.inst[0].internal.data0, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2107

} else if (reg == PACKET0(p->adev->vcn.inst[0].internal.data1, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2109

} else if (reg == PACKET0(p->adev->vcn.inst[0].internal.cmd, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2187

adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2194

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2195

adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2205

adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 2;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2206

adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

256

struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

263

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

264

ring = &adev->vcn.inst->ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

270

ring = adev->jpeg.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

286

struct amdgpu_vcn_inst *vinst = adev->vcn.inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

312

idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

357

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

370

lower_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

372

upper_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

382

lower_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

384

upper_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

390

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

392

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

425

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

441

lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

443

upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

453

lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

455

upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

463

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

466

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

849

struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1004

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1005

struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1014

return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1155

ring = &adev->vcn.inst->ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

116

adev->vcn.inst[0].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1164

ring = &adev->vcn.inst->ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

118

adev->vcn.inst[0].num_enc_rings = 2;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

120

adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1294

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1300

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1302

adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1311

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1327

ring = &adev->vcn.inst->ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1337

ring = &adev->vcn.inst->ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1363

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1410

vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1413

vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

145

&adev->vcn.inst->irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1483

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1485

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

150

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1500

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1520

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

153

&adev->vcn.inst->irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1541

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1544

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1547

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1550

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1553

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1556

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1559

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1582

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1585

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1587

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1589

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1598

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1601

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1604

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1607

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1632

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1635

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1638

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1654

if (ring == &adev->vcn.inst->ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1671

if (ring == &adev->vcn.inst->ring_enc[0]) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

168

ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1695

if (ring == &adev->vcn.inst->ring_enc[0]) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

175

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

180

adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1808

amdgpu_fence_process(&adev->vcn.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

181

adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1811

amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1814

amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

182

adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

183

adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1835

WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1839

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

184

adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1841

amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1845

tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

185

adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

187

adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

188

adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

189

adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

190

adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

191

adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

192

adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1921

adev->vcn.inst->ring_dec.wptr = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1922

adev->vcn.inst->ring_dec.wptr_old = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1923

vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1925

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1926

adev->vcn.inst->ring_enc[i].wptr = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1927

adev->vcn.inst->ring_enc[i].wptr_old = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1928

vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

193

adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

194

adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

195

adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

196

adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

198

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1984

size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2005

lower_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2009

upper_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

201

ring = &adev->vcn.inst->ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2023

lower_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2027

upper_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2038

lower_32_bits(adev->vcn.inst->gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2043

upper_32_bits(adev->vcn.inst->gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2052

for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2053

ring = &adev->vcn.inst->ring_enc[r];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2066

ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

209

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

215

adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

216

adev->vcn.inst[0].reset = vcn_v2_0_reset;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2178

adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2185

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2186

adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

219

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2196

adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2197

adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

227

fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

231

amdgpu_vcn_fwlog_init(adev->vcn.inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

255

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

285

struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

302

for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

303

ring = &adev->vcn.inst->ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

322

struct amdgpu_vcn_inst *vinst = adev->vcn.inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

384

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

400

lower_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

402

upper_32_bits(adev->vcn.inst->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

412

lower_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

414

upper_32_bits(adev->vcn.inst->gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

420

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

422

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

428

lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

430

upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

442

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

468

lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

471

upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

489

lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

492

upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

509

lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

512

upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

521

lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

524

upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

856

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

857

struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

870

adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1008

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1009

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1024

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1111

ring = &adev->vcn.inst[inst_idx].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1165

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1167

adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1179

return vcn_v2_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

121

struct amdgpu_vcn_inst *v = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1301

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1327

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1336

ring = &adev->vcn.inst[i].ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1438

size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1456

lower_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1460

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1473

lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1477

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

148

if (!fences && !atomic_read(&adev->vcn.inst[0].total_submission_cnt)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1487

lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1492

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1501

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1514

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

153

schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1551

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1586

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

160

struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

162

atomic_inc(&adev->vcn.inst[0].total_submission_cnt);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

164

cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1661

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1667

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1669

adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1678

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1696

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

170

mutex_lock(&adev->vcn.inst[0].vcn_pg_lock);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1706

ring = &adev->vcn.inst[inst_idx].ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1728

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1827

if (ring == &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1844

if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1868

if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1923

adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1924

adev->vcn.inst[i].ring_dec.me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1935

for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1936

adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1937

adev->vcn.inst[j].ring_enc[i].me = j;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

196

mutex_unlock(&adev->vcn.inst[0].vcn_pg_lock);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1995

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

207

!adev->vcn.inst[ring->me].using_unified_queue)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2070

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2073

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2076

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

208

atomic_dec(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

210

atomic_dec(&adev->vcn.inst[0].total_submission_cnt);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2104

adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2105

adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2107

adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2108

adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

212

schedule_delayed_work(&adev->vcn.inst[0].idle_work,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2187

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2190

for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2193

vcn_v2_6_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

233

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

242

adev->vcn.inst[i].num_enc_rings = 2;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

256

adev->vcn.inst[i].set_pg_state = vcn_v2_5_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

286

VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

291

for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

293

i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

300

VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

310

adev->vcn.inst[j].idle_work.work.func = vcn_v2_5_idle_work_handler;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

312

task_set(&adev->vcn.inst[j].idle_work.work.task,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

314

&adev->vcn.inst[j].idle_work.work);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

323

adev->vcn.inst[j].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

324

adev->vcn.inst[j].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

325

adev->vcn.inst[j].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

326

adev->vcn.inst[j].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

327

adev->vcn.inst[j].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

328

adev->vcn.inst[j].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

330

adev->vcn.inst[j].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

331

adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

332

adev->vcn.inst[j].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

333

adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

334

adev->vcn.inst[j].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

335

adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

336

adev->vcn.inst[j].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

337

adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

338

adev->vcn.inst[j].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

339

adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

341

ring = &adev->vcn.inst[j].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

353

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

358

for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

361

ring = &adev->vcn.inst[j].ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

375

&adev->vcn.inst[j].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

381

fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

385

amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

388

adev->vcn.inst[j].pause_dpg_mode = vcn_v2_5_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

389

adev->vcn.inst[j].reset = vcn_v2_5_reset;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

393

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

435

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

478

adev->vcn.inst[j].ring_enc[0].sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

479

adev->vcn.inst[j].ring_enc[1].sched.ready = false;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

480

adev->vcn.inst[j].ring_enc[2].sched.ready = false;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

481

adev->vcn.inst[j].ring_dec.sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

484

ring = &adev->vcn.inst[j].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

493

for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

494

ring = &adev->vcn.inst[j].ring_enc[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

518

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

597

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

604

size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

615

lower_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

617

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

626

lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

628

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

634

lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

636

upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

642

lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

644

upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

654

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

655

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

681

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

684

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

702

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

705

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

722

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

725

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

734

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

737

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

759

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

869

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

925

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

980

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1003

WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1005

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1025

WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1031

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1032

struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1047

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1136

ring = &adev->vcn.inst[inst_idx].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1196

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1327

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1337

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

135

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1359

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1368

ring = &adev->vcn.inst[i].ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1418

header.inst[i].init_status = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1419

header.inst[i].table_offset = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1420

header.inst[i].table_size = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1435

cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1451

lower_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1454

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

146

adev->vcn.inst[i].num_enc_rings = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1465

cache_addr = adev->vcn.inst[i].gpu_addr + offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1479

cache_addr = adev->vcn.inst[i].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

148

adev->vcn.inst[i].num_enc_rings = 2;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1494

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1495

ring = &adev->vcn.inst[i].ring_enc[j];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1509

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1533

header.inst[i].init_status = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1534

header.inst[i].table_offset = header.total_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1535

header.inst[i].table_size = table_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

157

adev->vcn.inst[i].set_pg_state = vcn_v3_0_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1597

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1635

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1717

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1724

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1726

adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1752

fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1754

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1764

ring = &adev->vcn.inst[inst_idx].ring_enc[1];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1790

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1841

fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2023

if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data0, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2025

} else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data1, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2027

} else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) &&

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2082

if (ring == &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

209

adev->vcn.inst[i].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2099

if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

210

adev->vcn.inst[i].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

211

adev->vcn.inst[i].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

212

adev->vcn.inst[i].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2123

if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

213

adev->vcn.inst[i].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

214

adev->vcn.inst[i].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

216

adev->vcn.inst[i].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

217

adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

218

adev->vcn.inst[i].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2180

adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2182

adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2183

adev->vcn.inst[i].ring_dec.me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

219

adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2195

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2196

adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2197

adev->vcn.inst[i].ring_enc[j].me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

220

adev->vcn.inst[i].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

221

adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

222

adev->vcn.inst[i].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

223

adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

224

adev->vcn.inst[i].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

225

adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2255

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

229

VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

233

atomic_set(&adev->vcn.inst[i].sched_score, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2330

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2333

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2336

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

235

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2360

adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2361

adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

238

ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

244

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

246

&adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

250

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

255

j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

259

ring = &adev->vcn.inst[i].ring_enc[j];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

262

ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1) + 1 + j;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

268

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

269

hw_prio, &adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

274

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

287

amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

290

adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

291

adev->vcn.inst[i].reset = vcn_v3_0_reset;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

295

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

334

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

381

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

393

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

394

ring = &adev->vcn.inst[i].ring_enc[j];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

412

ring = &adev->vcn.inst[i].ring_dec;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

421

for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

422

ring = &adev->vcn.inst[i].ring_enc[j];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

446

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

523

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

524

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

529

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

530

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

531

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

532

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

533

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

536

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

537

lower_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

538

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

539

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

541

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

544

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

547

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

548

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

549

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

550

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

551

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

552

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

555

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

556

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

557

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

558

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

559

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

560

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

563

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

564

lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

565

WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

566

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

567

WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

568

WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

576

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

577

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

603

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

606

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

624

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

627

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

644

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

647

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

656

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

659

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

674

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

693

WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

694

SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

711

WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

712

SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

715

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

721

WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

727

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

732

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

735

WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

751

WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

767

SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

781

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

785

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

792

WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

794

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

816

WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

818

SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

820

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

841

WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

843

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

875

WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

877

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

883

WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

885

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

905

WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

913

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

969

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

973

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

980

WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

982

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1000

struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1015

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1094

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1139

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1151

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1154

return vcn_v4_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1281

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

132

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1370

header.inst[i].init_status = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1371

header.inst[i].table_offset = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1372

header.inst[i].table_size = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

139

adev->vcn.inst[i].set_pg_state = vcn_v4_0_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1390

cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1406

lower_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1409

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1420

cache_addr = adev->vcn.inst[i].gpu_addr + offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1434

cache_addr = adev->vcn.inst[i].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1449

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1452

ring_enc = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1464

rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1465

rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1466

rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1469

rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1470

rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1471

rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1483

lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1486

upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1495

header.inst[i].init_status = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1496

header.inst[i].table_offset = header.total_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1497

header.inst[i].table_size = table_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

153

fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1553

init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1572

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1608

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1616

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

169

amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1702

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1707

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1709

adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1735

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1752

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1769

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1789

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1981

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

203

atomic_set(&adev->vcn.inst[i].sched_score, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2045

adev->vcn.inst[i].ring_enc[0].funcs =

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2047

adev->vcn.inst[i].ring_enc[0].me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

205

atomic_set(&adev->vcn.inst[i].sched_score, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

209

VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2114

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

215

VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

219

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2212

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

223

(adev->vcn.inst[i].num_enc_rings + 1) + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2247

adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2248

adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2250

adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2251

adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

229

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

230

AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2303

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2306

for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2309

vcn_v4_0_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

237

adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

241

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

286

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

333

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

344

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

371

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

450

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

454

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

459

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

460

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

461

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

462

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

463

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

466

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

467

lower_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

468

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

469

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

471

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

473

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

476

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

477

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

478

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

479

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

480

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

481

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

484

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

485

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

486

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

487

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

488

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

489

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

492

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

493

lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

494

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

495

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

496

WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

497

WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

513

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

516

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

542

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

545

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

563

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

566

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

583

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

586

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

595

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

598

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

621

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

640

WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

641

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

646

value = (inst) ? 0x2200800 : 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

662

WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

663

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

666

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

672

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

687

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

692

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

695

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

711

WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

727

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

743

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

750

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

754

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

756

data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

778

WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

779

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

781

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

802

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

804

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

829

WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

831

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

842

WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

859

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

914

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

921

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

925

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

927

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

948

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

950

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

961

WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

968

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

999

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1041

cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1058

lower_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1061

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1072

cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1082

cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1097

fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1100

ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1112

lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1115

upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1189

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1196

return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

120

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

127

adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1318

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1319

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1360

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1399

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1406

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

142

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1504

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1521

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

154

fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1587

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

159

amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1606

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1622

vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1671

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1672

adev->vcn.inst[i].ring_enc[0].me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1674

adev->vcn.inst[i].aid_id =

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1736

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

179

VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1810

uint32_t i, inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1816

for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1817

if (adev->vcn.inst[inst].aid_id == i)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1820

if (inst >= adev->vcn.num_vcn_inst) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1829

amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

185

VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1870

adev->vcn.inst->irq.num_types++;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1872

adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1874

adev->vcn.inst->ras_poison_irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1875

adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1985

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1988

for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1991

vcn_v4_0_3_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

201

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2076

adev->vcn.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2077

r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

213

ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

214

snprintf(ring->name, sizeof(ring->name), "vcn_unified_%d", adev->vcn.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

219

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

221

&adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

228

adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

268

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

297

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

300

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

304

adev->vcn.inst[inst_idx].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

337

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

352

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

353

vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

357

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

383

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

392

amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

455

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

459

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

477

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

480

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

489

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

491

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

498

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

501

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

510

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

513

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

532

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

536

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

564

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

567

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

585

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

588

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

605

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

609

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

619

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

622

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

646

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

744

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

793

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

847

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

849

adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

866

inst_idx, adev->vcn.inst[inst_idx].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

867

adev->vcn.inst[inst_idx].dpg_sram_curr_addr =

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

868

(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

871

adev->vcn.inst[inst_idx].aid_id, 0, true);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

952

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1007

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1051

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1063

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1066

return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1194

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

123

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1236

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1270

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1278

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

128

adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1365

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1370

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1372

adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1399

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1416

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1433

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1453

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1469

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1531

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1532

adev->vcn.inst[i].ring_enc[0].me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1599

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1665

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

167

atomic_set(&adev->vcn.inst[i].sched_score, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1698

adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1699

adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

171

VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

177

VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

181

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

185

i * (adev->vcn.inst[i].num_enc_rings + 1) + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

192

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

193

AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

197

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

213

amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

216

adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

219

adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

257

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

298

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

324

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

401

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

405

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

410

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

411

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

412

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

413

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

414

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

417

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

418

lower_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

419

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

420

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

422

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

424

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

427

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

428

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

429

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

430

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

431

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

432

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

435

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

436

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

437

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

438

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

439

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

440

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

443

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

444

lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

445

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

446

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

447

WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

448

WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

464

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

468

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

496

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

499

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

517

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

520

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

538

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

542

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

552

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

555

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

578

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

582

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

584

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

586

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

588

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

591

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

593

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

596

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

598

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

602

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

604

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

606

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

608

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

610

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

612

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

614

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

616

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

620

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

625

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

638

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

643

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

646

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

648

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

650

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

653

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

655

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

658

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

660

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

663

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

665

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

681

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

688

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

692

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

694

data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

716

WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

717

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

719

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

740

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

742

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

767

WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

769

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

780

WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

797

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

852

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

859

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

863

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

865

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

886

WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

888

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

899

WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

914

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

915

struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

930

adev->vcn.inst[inst_idx].dpg_sram_curr_addr =

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

931

(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1001

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1009

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

102

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

108

adev->vcn.inst[i].set_pg_state = vcn_v5_0_0_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1093

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1098

if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1100

adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1123

adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1140

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1157

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1177

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1193

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1252

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1253

adev->vcn.inst[i].ring_enc[0].me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1320

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1386

amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1419

adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1420

adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

147

atomic_set(&adev->vcn.inst[i].sched_score, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

151

VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

157

VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

161

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

168

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

169

AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

173

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

182

amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

185

adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

189

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

223

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

262

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

288

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

365

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

369

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

374

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

375

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

376

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

377

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

378

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

381

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

382

lower_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

383

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

384

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

386

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

388

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

391

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

392

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

393

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

394

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

395

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

396

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

399

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

400

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

401

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

402

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

403

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

404

WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

407

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

408

lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

409

WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

410

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

411

WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

412

WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

428

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

432

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

458

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

461

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

479

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

482

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

499

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

502

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

511

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

514

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

539

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

544

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

545

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

549

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

550

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

555

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

556

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

561

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

562

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

567

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

568

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

572

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

573

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

577

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

578

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

582

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

583

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

587

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

593

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

607

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

612

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

615

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

618

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

619

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

624

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

625

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

630

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

631

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

636

WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

637

SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

698

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

699

struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

715

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

764

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

808

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

820

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

823

return vcn_v5_0_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

922

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

965

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

106

adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1088

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1135

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1173

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1180

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

121

amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1255

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1272

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1292

if (ring != &adev->vcn.inst[ring->me].ring_enc[0])

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1311

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1373

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1374

adev->vcn.inst[i].ring_enc[0].me = i;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1376

adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

141

fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1436

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1491

uint32_t i, inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1497

for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1498

if (adev->vcn.inst[inst].aid_id == i)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

150

amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1500

if (inst >= adev->vcn.num_vcn_inst) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1509

amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1550

adev->vcn.inst->irq.num_types++;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1552

adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1554

adev->vcn.inst->ras_poison_irq.num_types = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1555

adev->vcn.inst->ras_poison_irq.funcs = &vcn_v5_0_1_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1612

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1615

for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1618

vcn_v5_0_1_query_poison_by_instance(adev, inst, sub);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

168

VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1706

adev->vcn.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1707

r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

174

VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

189

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

200

ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

201

snprintf(ring->name, sizeof(ring->name), "vcn_unified_%d", adev->vcn.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

203

r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

204

AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

248

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

279

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

285

adev->vcn.inst[i].aid_id);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

309

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

319

ring = &adev->vcn.inst[i].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

347

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

349

cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

355

amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

398

struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

423

int inst = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

427

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

430

vcn_inst = GET_INST(VCN, inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

434

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

436

(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

441

lower_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

443

upper_32_bits(adev->vcn.inst[inst].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

452

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

454

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

460

lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

462

upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

468

lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

470

upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

488

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

492

hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

520

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

523

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

541

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

544

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

561

lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

565

upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

575

lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

578

upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

627

vcn_inst = GET_INST(VCN, vinst->inst);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

670

int inst_idx = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

672

adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

690

adev->vcn.inst[inst_idx].dpg_sram_curr_addr =

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

691

(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

694

adev->vcn.inst[inst_idx].aid_id, 0, true);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

750

ring = &adev->vcn.inst[inst_idx].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

833

cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

850

lower_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

853

upper_32_bits(adev->vcn.inst[i].gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

864

cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

874

cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

889

fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

892

ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

904

lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

907

upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

981

int i = vinst->inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

987

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

99

adev->vcn.inst[i].num_enc_rings = 1;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

990

return vcn_v5_0_1_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

64

static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

68

base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

100

uint32_t *se_mask, uint32_t inst)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

110

int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

192

i = inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

297

uint32_t inst)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

304

inst, doorbell_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

166

uint32_t *se_mask, uint32_t inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

202

uint32_t inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

599

int xcc_id, err, inst = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

604

xcc_mqd = mqd + hiq_mqd_size * inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

609

pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

612

++inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

623

int xcc_id, err, inst = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

629

m = get_mqd(mqd + hiq_mqd_size * inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

63

struct mqd_update_info *minfo, uint32_t inst)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

636

pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

639

++inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

649

int inst = 0, xcc_id;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

654

m = get_mqd(mqd + hiq_mqd_size * inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

656

m->queue_doorbell_id0, inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

658

++inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

72

minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

821

int xcc_id, err, inst = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

830

xcc_mqd = mqd + mqd_offset * inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

835

pr_debug("Destroy MQD failed for xcc: %d\n", inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

838

++inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

851

int xcc_id, err, inst = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

856

xcc_mqd = mqd + mqd_stride_size * inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

862

pr_debug("Load MQD failed for xcc: %d\n", inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

865

++inst;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

99

inst, m->compute_static_thread_mgmt_se0,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10097

int i, inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10125

inst = aconnector->audio_inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10129

amdgpu_dm_audio_eld_notify(adev, inst);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10160

inst = status->audio_inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10161

aconnector->audio_inst = inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10164

amdgpu_dm_audio_eld_notify(adev, inst);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1208

adev->dm.dc->res_pool->audios[i]->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

154

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

174

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

202

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

119

dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

64

#define CLK_SRI(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

115

#define CLK_SR_DCN321(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

280

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

281

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

283

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

393

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

444

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

268

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

269

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

271

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

319

if (old_dpp && !dppclk_active[old_dpp->inst])

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

320

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

57

#define CLK_SR_DCN401(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/core/dc.c

2484

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4157

inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4249

pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4427

inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

602

mux_mapping.otg_output_num = pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6170

pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6375

dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

668

mux_mapping.otg_output_num = pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

897

pipes->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1244

mpcc_inst = hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

850

block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

856

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

863

block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

870

block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2315

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2316

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2317

pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2323

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2324

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2325

pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2331

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2332

pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2337

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2338

pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2343

pipe->plane_res.dpp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2348

pipe->plane_res.dpp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2546

split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3640

unsigned int i, inst, tg_inst = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3648

inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3650

if (inst == ENGINE_ID_UNKNOWN)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3654

if (pool->stream_enc[i]->id == inst) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3699

pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3843

pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3969

pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3974

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3977

pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5465

sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5474

dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

946

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

77

pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

427

fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

432

fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

801

pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

845

pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

847

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

849

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

45

int inst;

sys/dev/pci/drm/amd/display/dc/dc_trace.h

43

#define TRACE_OPTC_LOCK_UNLOCK_STATE(optc, inst, lock) \

sys/dev/pci/drm/amd/display/dc/dc_trace.h

44

trace_dcn_optc_lock_unlock_state(optc, inst, lock, __func__, __LINE__)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

54

#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

55

.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

57

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

58

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

354

void dccg31_disable_dscclk(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

361

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

398

void dccg31_enable_dscclk(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

405

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

235

void dccg31_disable_dscclk(struct dccg *dccg, int inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

237

void dccg31_enable_dscclk(struct dccg *dccg, int inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

32

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

33

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

31

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

32

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1003

if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1008

dccg35_set_symclk32_le_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1012

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1015

dccg35_set_physymclk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1016

dccg35_set_physymclk_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1020

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1022

dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1023

dccg35_set_physymclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1028

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1033

if (inst < 0) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1037

dccg35_set_dppclk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1038

dcn35_set_dppclk_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1040

REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1048

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1052

if (inst < 0) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1056

dcn35_set_dppclk_src_new(dccg, inst, DPP_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1057

REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1060

dccg35_set_dppclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1064

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1066

dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1067

dccg35_set_dsc_clk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1071

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1074

dccg35_set_dsc_clk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1075

dccg35_set_dsc_clk_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1080

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1082

dccg35_set_dtbclk_p_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1083

dccg35_set_dtbclk_p_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1087

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1089

dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1090

dccg35_set_dtbclk_p_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1094

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1096

dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1097

dccg35_set_dpstreamclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1102

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1104

dccg35_set_dpstreamclk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1105

dccg35_set_dpstreamclk_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

137

static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

144

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

169

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

179

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1801

static void dccg35_enable_dscclk(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1806

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1849

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1853

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

208

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

216

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2200

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2203

dccg35_enable_symclk32_se_new(dccg, inst, (enum symclk32_se_clk_source)phyd32clk);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2206

static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2208

dccg35_disable_symclk32_se_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2213

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2216

dccg35_enable_symclk32_le_new(dccg, inst, (enum symclk32_le_clk_source) src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2219

static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2221

dccg35_disable_symclk32_le_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2226

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2235

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2237

dccg35_disable_symclk32_le_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2242

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2248

dccg35_enable_physymclk_new(dccg, inst, (enum physymclk_source)clk_src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2250

dccg35_disable_physymclk_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2255

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2262

dccg35_enable_physymclk_new(dccg, inst, PHYSYMCLK_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2264

dccg35_disable_physymclk_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2269

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2278

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2280

dccg35_disable_symclk32_le_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2286

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2289

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2291

dccg35_disable_dtbclk_p_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2346

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2348

dccg35_disable_dscclk_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

235

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2351

static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2353

dccg35_enable_dscclk_new(dccg, inst, DSC_DTO_TUNED_CK_GPU_DISCLK_3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

243

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

272

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

280

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

319

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

329

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

366

static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

374

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

393

static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

400

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

425

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

433

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

462

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

470

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

497

static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

503

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

524

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

530

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

576

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

581

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

599

int inst, enum dppclk_clock_source src)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

603

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

625

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

633

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

663

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

667

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

703

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

707

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

747

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

751

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

814

static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

818

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

847

static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

852

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

880

static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

886

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

918

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

921

dccg35_set_symclk_fe_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

922

dccg35_set_symclk_fe_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

927

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

929

dccg35_set_symclk_fe_src_new(dccg, SYMCLK_FE_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

930

dccg35_set_symclk_fe_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

935

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

938

dccg35_set_symclk_be_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

939

dccg35_set_symclk_be_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

944

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

949

dccg35_set_symclk_be_src_new(dccg, inst, SYMCLK_BE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

955

if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

960

dccg35_set_symclk_be_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

965

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

968

dccg35_set_symclk32_se_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

969

dccg35_set_symclk32_se_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

974

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

976

dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

977

dccg35_set_symclk32_se_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

982

int inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

985

dccg35_set_symclk32_le_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

986

dccg35_set_symclk32_le_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

991

int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

996

dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

30

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

31

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

730

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

734

switch (inst) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

212

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

31

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

32

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1268

if (audio->inst != 0)

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1327

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1341

audio->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1353

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1367

audio->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

630

audio->inst, value);

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

660

audio->inst, value);

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

901

audio->inst, value, audio_info->display_name);

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

149

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

157

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

509

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

520

aux_engine110->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

242

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

289

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

524

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1003

REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1007

REG_UPDATE(PIXEL_RATE_CNTL[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1012

REG_UPDATE(PIXEL_RATE_CNTL[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1074

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1081

dto_params.otg_inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1194

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1203

clock_hz = REG_READ(PHASE[inst]);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1210

modulo_hz = REG_READ(MODULO[inst]);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1288

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1298

REG_WRITE(MODULO[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1306

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1312

REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1313

REG_WRITE(PHASE[inst], pixel_clk);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1314

REG_WRITE(MODULO[inst], ref_clk);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1315

REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1334

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1343

REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1344

REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1347

REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1348

REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1352

REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1356

REG_UPDATE(PIXEL_RATE_CNTL[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

972

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

989

REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

990

REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

993

REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

994

REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

999

REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

274

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

280

ipp_dce->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

292

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

298

ipp_dce->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

271

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

279

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

1004

dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

955

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

962

dce_mi->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

974

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

979

dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

987

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

992

dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

999

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

436

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

445

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

454

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

462

int inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

726

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

735

opp110->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

745

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

754

opp110->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

316

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

324

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

292

dce_panel_cntl->base.inst = init_data->inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1644

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1651

xfm_dce->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1673

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1680

xfm_dce->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

660

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

668

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

103

unsigned int inst)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

107

feature_support = abm_feature_support(abm, inst);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

110

dmub_abm_init_config(abm, src, bytes, inst);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

162

unsigned int inst)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

166

uint8_t panel_mask = 0x01 << inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h

40

unsigned int inst);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

348

copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

352

copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

158

copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

203

params->inst,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

212

compressor->attached_inst = params->inst + CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

267

uint32_t *inst)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

274

if (inst != NULL)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

275

*inst = compressor->attached_inst;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

284

if (inst != NULL)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

285

*inst =

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

304

cp110->offsets = reg_offsets[params->inst];

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1235

gsl_params->gsl_master == tg->inst,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2347

tg110->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

395

params->inst,

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

401

compressor->attached_inst = params->inst;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

402

cp110->offsets = reg_offsets[params->inst];

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

441

uint32_t *inst)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

448

if (inst != NULL)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

449

*inst = compressor->attached_inst;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

458

if (inst != NULL)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

459

*inst =

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1262

tg110->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

266

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

252

tg110->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

234

tg110->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

119

int inst)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

123

dwbc10->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

265

int inst);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

51

#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

52

SRI(WB_ENABLE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

53

SRI(WB_EC_CONFIG, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

54

SRI(CNV_MODE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

55

SRI(WB_SOFT_RESET, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

56

SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

57

SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

58

SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

59

SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

60

SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

61

SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

62

SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

63

SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

64

SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

65

SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

66

SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

67

SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

68

SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

69

SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

70

SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

71

SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

72

SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

73

SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

74

SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

75

SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

76

SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

77

SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

78

SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

79

SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

80

SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

81

SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

82

SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

145

hubp->inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

164

hubp->inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

213

pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

261

pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

312

pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

353

dpp->inst, s.igam_input_format,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

442

tg->inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c

61

int inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c

67

ippn10->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c

78

int inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c

84

ippn10->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

211

int inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

218

int inst,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

107

DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

110

DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

138

DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

166

DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

169

DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

215

dwbc20->base.inst, stereo_params->stereo_enabled);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

230

DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

239

DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

253

DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

332

int inst)

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

336

dwbc20->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

64

DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

67

DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

75

DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

30

#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

31

SRI2_DWB(WB_ENABLE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

32

SRI2_DWB(WB_EC_CONFIG, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

33

SRI2_DWB(CNV_MODE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

34

SRI2_DWB(CNV_WINDOW_START, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

35

SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

36

SRI2_DWB(CNV_UPDATE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

37

SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

38

SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

39

SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

40

SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

400

int inst);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

41

SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

42

SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

43

SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

44

SRI2_DWB(WBSCL_MODE, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

45

SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

46

SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

47

SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

48

SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

49

SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

50

SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

51

SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

52

SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

53

SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

54

SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

55

SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

56

SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

57

SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

58

SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

59

SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

60

SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

61

SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

62

SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

63

SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

64

SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

65

SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

66

SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

67

SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

68

SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

69

SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

70

SRI2_DWB(WB_DBG_MODE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

71

SRI2_DWB(WB_HW_DEBUG, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

72

SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

73

SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

74

SRI2_DWB(WB_SOFT_RESET, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

75

SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

76

SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst)

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h

33

#define MPC_REG_LIST_DCN201(inst) \

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h

34

MPC_REG_LIST_DCN2_0(inst)

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h

36

#define MPC_OUT_MUX_REG_LIST_DCN201(inst) \

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h

37

MPC_OUT_MUX_REG_LIST_DCN2_0(inst)

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.c

62

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.c

68

oppn201->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h

68

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

202

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

209

afmt3->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

135

int inst;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

165

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

229

int inst)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

233

mcif_wb30->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

100

SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

101

SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

102

SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

103

SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

104

SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

105

SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

106

SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

107

SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

108

SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

109

SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

110

SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

111

SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

112

SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

113

SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

114

SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

115

SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

116

SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

117

SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

118

SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

119

SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

120

SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

121

SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

122

SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

123

SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

124

SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

125

SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

126

SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

127

SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

128

SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

129

SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

130

SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

131

SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

132

SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

133

SRI2(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB, inst)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

34

#define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

35

SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

36

SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

37

SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

38

SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

39

SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

40

SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

41

SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

42

SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

43

SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

44

SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

446

int inst);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

45

SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

46

SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

47

SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

48

SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

49

SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

50

SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

51

SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

52

SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

53

SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

54

SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

55

SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

56

SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

57

SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

58

SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

59

SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

60

SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

61

SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

62

SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

63

SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

64

SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

65

SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

66

SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

67

SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

68

SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

69

SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

70

SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

71

SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

72

SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

73

SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

74

SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

75

SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

76

SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

77

SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

78

SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

79

SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

80

SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

81

SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

82

SRI2(MMHUBBUB_WARMUP_P_VMID, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

83

SRI(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB, inst)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

85

#define MCIF_WB_COMMON_REG_LIST_DCN30(inst) \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

86

SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

87

SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

88

SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

89

SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

90

SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

91

SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

92

SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

93

SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

94

SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

95

SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

96

SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

97

SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

98

SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

99

SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

251

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

258

vpg3->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

151

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

217

dcn301_panel_cntl->base.inst = init_data->inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

79

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

86

afmt31->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

121

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c

106

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c

113

apg31->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

105

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

74

int inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

174

dcn31_panel_cntl->base.inst = init_data->inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

198

dcn31_panel_cntl->base.pwrseq_inst = dcn31_panel_cntl->base.inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

79

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

86

vpg31->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

158

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

897

enc1->base.stream_enc_inst = vpg->inst;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

504

enc1->base.stream_enc_inst = vpg->inst;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

491

enc1->base.stream_enc_inst = vpg->inst;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

518

enc1->base.stream_enc_inst = vpg->inst;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

792

enc1->base.stream_enc_inst = vpg->inst;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

541

secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1408

pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1892

sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1284

dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1285

current_pipe_context->link_res.hpo_dp_link_enc->inst;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

258

pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

575

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

582

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1521

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

409

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

416

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

777

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

300

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

307

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

78

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1506

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1513

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

582

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

149

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

156

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h

33

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

130

uint32_t inst, const struct dcn3_dpp_registers *tf_regs,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

134

bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

58

uint32_t inst, const struct dcn3_dpp_registers *tf_regs,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

264

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

271

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

688

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

188

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

226

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

231

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

249

DC_LOG_DSC("disable DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

253

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

274

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

64

int inst,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

70

dsc->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

596

int inst,

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

61

int inst,

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

67

dsc->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

84

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

97

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h

52

int inst,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

129

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

145

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

150

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

168

DC_LOG_DSC("disable DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

172

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

193

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

49

int inst,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

55

dsc->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

330

int inst,

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

129

DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

151

DC_LOG_DWB("%s dwb3_fc_disabled at inst = %d", __func__, dwbc->inst);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

167

DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

262

int inst)

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

266

dwbc30->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

94

DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

30

#define DWBC_COMMON_REG_LIST_DCN30(inst) \

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

882

int inst);

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

47

int inst)

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

51

(const struct dcn30_dwbc_mask *)dwbc_mask, inst);

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h

57

int inst);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

533

cntl.hpo_engine_id = enc->inst + ENGINE_ID_HPO_DP_0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

613

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

620

enc31->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

185

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

710

switch (enc->inst) {

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

762

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

772

enc3->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

236

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

74

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

81

enc31->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h

60

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1405

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1415

hubp1->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

803

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1703

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1713

hubp2->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

310

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

141

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

151

hubp201->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

127

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

688

cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

849

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

859

hubp21->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

117

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

568

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

578

hubp2->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

252

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

121

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

131

hubp2->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

239

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

217

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

227

hubp2->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

65

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

229

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

239

hubp2->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

54

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1082

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1092

hubp2->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

320

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

36

#define HUBP_3DLUT_FL_REG_LIST_DCN401(inst)\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

37

SRI_ARR_US(_3DLUT_FL_CONFIG, HUBP, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

38

SRI_ARR_US(_3DLUT_FL_BIAS_SCALE, HUBP, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

39

SRI_ARR(HUBP_3DLUT_ADDRESS_HIGH, CURSOR0_, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

40

SRI_ARR(HUBP_3DLUT_ADDRESS_LOW, CURSOR0_, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

41

SRI_ARR(HUBP_3DLUT_CONTROL, CURSOR0_, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

42

SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, inst)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

60

val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

71

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

76

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

83

REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1280

unsigned int inst, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

61

#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

62

SRII(PIXEL_RATE_CNTL, blk, inst), \

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

63

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1184

dto_params.otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1186

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1189

dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1464

pipe_ctx->stream_res.tg->inst + 1);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1606

pipe_ctx->stream_res.audio->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1682

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1891

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1896

pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1969

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2278

params.inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2615

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2739

gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2931

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3076

pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3198

uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3214

link->panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3226

pipe_ctx->stream->link->panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3236

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3239

abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

128

params.inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

200

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

286

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1233

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1346

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1446

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1499

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1502

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1510

"Power gated front end %d\n", hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1514

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1621

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1623

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1674

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1675

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1679

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1754

hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2253

inst_flags.opp_inst = pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2261

pipe->stream_res.opp->inst, lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2420

grouped_pipes[i]->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2455

grouped_pipes[i]->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2459

grouped_pipes[i]->stream_res.tg->inst, &pclk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2587

grouped_pipes[0]->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2744

pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2931

mpcc_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2956

hubp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2961

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3037

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3050

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

310

hubp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3108

pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

344

pool->hubps[i]->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3548

if (res_pool->hubps[i]->inst == mpcc_inst)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

380

pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

408

pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

438

pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

476

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

654

tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

691

dsc->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

792

hpo_dp_link_enc->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1009

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

102

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1032

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1195

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1200

opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1298

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1301

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1308

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1465

inst_flags.otg_inst = pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1696

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1704

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1965

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1969

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2137

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2140

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2227

is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2239

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2620

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2633

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2635

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2741

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2782

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2880

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2898

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2982

mpcc_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3008

hubp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3013

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3042

dto_params.otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3048

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3049

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3074

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3128

hubp->inst, mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3188

res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3205

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3206

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

856

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

871

opp_inst[i] = opp_heads[i]->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

901

dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

903

dto_params.otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

298

res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

315

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

381

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

481

dpp_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

521

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

182

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

200

panel_cntl->inst, panel_cntl->pwrseq_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

205

panel_cntl->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

223

otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

234

panel_cntl->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

239

panel_cntl->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

258

otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

269

panel_cntl->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

275

panel_cntl->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

281

frame_ramp, 0, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

283

dmub_abm_set_backlight(dc, backlight_pwm_u16_16, frame_ramp, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

102

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1242

out_data->otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

257

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

359

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

395

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

906

hubp->inst, mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

610

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

641

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

644

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

719

otg_inst = tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

724

panel_cntl->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

727

dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

113

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

119

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

127

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

160

opp_instances[0] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

165

opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

390

&& pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

434

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

441

opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

90

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

97

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1044

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1051

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1068

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1070

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1078

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1080

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1084

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1119

opp_instances[0] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1124

opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1279

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1286

opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1326

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1522

bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1526

hws->funcs.dsc_pg_control(hws, dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1530

hws->funcs.dsc_pg_control(hws, dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1662

if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1676

if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

443

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

480

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

566

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1048

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1051

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1057

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1060

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1063

update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1066

update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1075

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1080

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1085

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1090

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1095

update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1100

update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1128

update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1129

update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1130

update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1134

new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

347

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

354

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

369

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

375

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

383

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

416

opp_instances[0] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

421

opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

673

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

675

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

726

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

727

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

731

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

809

pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

956

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

959

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

965

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

967

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

968

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

972

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

982

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

985

update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1581

opp_inst[i] = opp_heads[i]->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1630

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1693

hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1697

hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1887

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1901

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2025

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2028

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2199

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2202

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2671

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2674

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2684

"Power gated front end %d\n", hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2687

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

385

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

417

int mpcc_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

591

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

620

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

673

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

742

opp_inst[i] = opp_heads[i]->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

790

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

808

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

929

*dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

975

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

990

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

175

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

179

unsigned int inst,

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

50

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h

58

unsigned int inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/audio.h

62

unsigned int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

91

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

81

#define CLK_BASE(inst) \

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

82

CLK_BASE_INNER(inst)

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

84

#define CLK_SRI(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

85

.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

86

mm ## block ## _ ## inst ## _ ## reg_name

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

168

int inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

172

int inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

78

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h

159

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

122

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/ipp.h

39

unsigned int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

237

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/mcif_wb.h

71

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

87

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

237

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

59

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

66

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

295

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

188

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h

41

int inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/vpg.h

50

int inst;

sys/dev/pci/drm/amd/display/dc/inc/resource.h

82

struct dc_context *ctx, unsigned int inst);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

90

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

118

pipes[i]->stream_res.audio->inst);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

885

inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

933

inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

121

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

121

link_res->hpo_dp_link_enc->inst,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

145

link_res->hpo_dp_link_enc->inst,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

42

hpo_dp_stream_encoder->inst,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

80

stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

679

config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

696

config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

846

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

848

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

853

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

855

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

876

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

932

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

648

panel_cntl_init_data.inst = panel_cntl_init_data.ctx->dc_edp_id_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1037

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1255

link_enc_index = link_res->hpo_dp_link_enc->inst;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

807

pipe_ctx[i].stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

314

int inst)

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

318

mcif_wb20->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

32

#define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

33

SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

34

SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

35

SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

36

SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

37

SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

38

SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

39

SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

40

SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

41

SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

42

SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

43

SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

44

SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

45

SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

46

SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

47

SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

48

SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

49

SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

50

SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

51

SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

515

int inst);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

52

SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

53

SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

54

SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

55

SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

56

SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

57

SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

58

SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

59

SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

60

SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

61

SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

62

SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

63

SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

64

SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

65

SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

66

SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

67

SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

68

SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

69

SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

70

SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

71

SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

72

SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

73

SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

74

SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

75

SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

76

SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

77

SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

78

SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

79

SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

80

SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

81

SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

82

SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

83

SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

84

SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

85

SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

86

SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

87

SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

88

SRI(SMU_WM_CONTROL, WBIF, inst)

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

229

int inst)

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

233

mcif_wb30->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

209

int inst);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

32

#define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

33

SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

34

SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

35

SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

36

SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

37

SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

38

SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

39

SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

40

SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

41

SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

42

SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

43

SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

44

SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

45

SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

46

SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

47

SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

48

SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

49

SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

50

SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

51

SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

52

SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

53

SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

54

SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

55

SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

56

SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

57

SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

58

SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

59

SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

60

SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

61

SRI2(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

62

SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

63

SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

64

SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

65

SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

66

SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

67

SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

68

SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

69

SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

70

SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

71

SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

72

SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

73

SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

74

SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

75

SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

76

SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

77

SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

78

SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

79

SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

80

SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c

47

const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst)

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c

53

(const struct dcn30_mmhubbub_mask *)(mcif_wb_mask), inst);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h

71

const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

33

#define MPC_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

34

SRII(MPCC_TOP_SEL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

35

SRII(MPCC_BOT_SEL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

36

SRII(MPCC_CONTROL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

37

SRII(MPCC_STATUS, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

38

SRII(MPCC_OPP_ID, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

39

SRII(MPCC_BG_G_Y, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

40

SRII(MPCC_BG_R_CR, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

41

SRII(MPCC_BG_B_CB, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

42

SRII(MPCC_SM_CONTROL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

43

SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

45

#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

46

SRII(MUX, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

47

VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

33

#define MPC_REG_LIST_DCN2_0(inst)\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

34

MPC_COMMON_REG_LIST_DCN1_0(inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

35

SRII(MPCC_TOP_GAIN, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

36

SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

37

SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

38

SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

39

SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

40

SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

41

SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

42

SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

43

SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

44

SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

45

SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

46

SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

47

SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

48

SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

49

SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

50

SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

51

SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

52

SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

53

SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

54

SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

55

SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

56

SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

57

SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

58

SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

59

SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

60

SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

61

SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

62

SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

63

SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

64

SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

65

SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

66

SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

67

SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

68

SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

69

SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

70

SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

72

#define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

73

MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

74

SRII(CSC_MODE, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

75

SRII(CSC_C11_C12_A, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

76

SRII(CSC_C33_C34_A, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

77

SRII(CSC_C11_C12_B, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

78

SRII(CSC_C33_C34_B, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

79

SRII(DENORM_CONTROL, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

80

SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

81

SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

100

SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

102

#define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

103

MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

104

SRII(CSC_MODE, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

105

SRII(CSC_C11_C12_A, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

106

SRII(CSC_C33_C34_A, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

107

SRII(CSC_C11_C12_B, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

108

SRII(CSC_C33_C34_B, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

109

SRII(DENORM_CONTROL, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

110

SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

111

SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

118

#define MPC_RMU_REG_LIST_DCN3AG(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

119

SRII(SHAPER_CONTROL, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

120

SRII(SHAPER_OFFSET_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

121

SRII(SHAPER_OFFSET_G, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

122

SRII(SHAPER_OFFSET_B, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

123

SRII(SHAPER_SCALE_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

124

SRII(SHAPER_SCALE_G_B, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

125

SRII(SHAPER_LUT_INDEX, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

126

SRII(SHAPER_LUT_DATA, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

127

SRII(SHAPER_LUT_WRITE_EN_MASK, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

128

SRII(SHAPER_RAMA_START_CNTL_B, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

129

SRII(SHAPER_RAMA_START_CNTL_G, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

130

SRII(SHAPER_RAMA_START_CNTL_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

131

SRII(SHAPER_RAMA_END_CNTL_B, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

132

SRII(SHAPER_RAMA_END_CNTL_G, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

133

SRII(SHAPER_RAMA_END_CNTL_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

134

SRII(SHAPER_RAMA_REGION_0_1, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

135

SRII(SHAPER_RAMA_REGION_2_3, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

136

SRII(SHAPER_RAMA_REGION_4_5, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

137

SRII(SHAPER_RAMA_REGION_6_7, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

138

SRII(SHAPER_RAMA_REGION_8_9, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

139

SRII(SHAPER_RAMA_REGION_10_11, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

140

SRII(SHAPER_RAMA_REGION_12_13, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

141

SRII(SHAPER_RAMA_REGION_14_15, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

142

SRII(SHAPER_RAMA_REGION_16_17, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

143

SRII(SHAPER_RAMA_REGION_18_19, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

144

SRII(SHAPER_RAMA_REGION_20_21, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

145

SRII(SHAPER_RAMA_REGION_22_23, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

146

SRII(SHAPER_RAMA_REGION_24_25, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

147

SRII(SHAPER_RAMA_REGION_26_27, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

148

SRII(SHAPER_RAMA_REGION_28_29, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

149

SRII(SHAPER_RAMA_REGION_30_31, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

150

SRII(SHAPER_RAMA_REGION_32_33, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

151

SRII(SHAPER_RAMB_START_CNTL_B, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

152

SRII(SHAPER_RAMB_START_CNTL_G, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

153

SRII(SHAPER_RAMB_START_CNTL_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

154

SRII(SHAPER_RAMB_END_CNTL_B, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

155

SRII(SHAPER_RAMB_END_CNTL_G, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

156

SRII(SHAPER_RAMB_END_CNTL_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

157

SRII(SHAPER_RAMB_REGION_0_1, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

158

SRII(SHAPER_RAMB_REGION_2_3, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

159

SRII(SHAPER_RAMB_REGION_4_5, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

160

SRII(SHAPER_RAMB_REGION_6_7, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

161

SRII(SHAPER_RAMB_REGION_8_9, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

162

SRII(SHAPER_RAMB_REGION_10_11, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

163

SRII(SHAPER_RAMB_REGION_12_13, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

164

SRII(SHAPER_RAMB_REGION_14_15, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

165

SRII(SHAPER_RAMB_REGION_16_17, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

166

SRII(SHAPER_RAMB_REGION_18_19, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

167

SRII(SHAPER_RAMB_REGION_20_21, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

168

SRII(SHAPER_RAMB_REGION_22_23, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

169

SRII(SHAPER_RAMB_REGION_24_25, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

170

SRII(SHAPER_RAMB_REGION_26_27, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

171

SRII(SHAPER_RAMB_REGION_28_29, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

172

SRII(SHAPER_RAMB_REGION_30_31, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

173

SRII(SHAPER_RAMB_REGION_32_33, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

174

SRII_MPC_RMU(3DLUT_MODE, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

175

SRII_MPC_RMU(3DLUT_INDEX, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

176

SRII_MPC_RMU(3DLUT_DATA, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

177

SRII_MPC_RMU(3DLUT_DATA_30BIT, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

178

SRII_MPC_RMU(3DLUT_READ_WRITE_CONTROL, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

179

SRII_MPC_RMU(3DLUT_OUT_NORM_FACTOR, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

180

SRII_MPC_RMU(3DLUT_OUT_OFFSET_R, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

181

SRII_MPC_RMU(3DLUT_OUT_OFFSET_G, MPC_RMU, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

182

SRII_MPC_RMU(3DLUT_OUT_OFFSET_B, MPC_RMU, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

185

#define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

186

SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

45

#define MPC_REG_LIST_DCN3_0(inst)\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

46

MPC_COMMON_REG_LIST_DCN1_0(inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

47

SRII(MPCC_TOP_GAIN, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

48

SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

49

SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

50

SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

51

SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

52

SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

53

SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

54

SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

55

SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

56

SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

57

SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

58

SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

59

SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

60

SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

61

SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

62

SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

63

SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

64

SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

65

SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

66

SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

67

SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

68

SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

69

SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

70

SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

71

SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

72

SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

73

SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

74

SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

75

SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

76

SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

77

SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

78

SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

79

SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

80

SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

81

SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

82

SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

83

SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

84

SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

85

SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

86

SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

87

SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

88

SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

89

SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

90

SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

91

SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

92

SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

93

SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

94

SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

95

SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

96

SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

97

SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

98

SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

99

SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

100

SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

101

SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

102

SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

103

SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

104

SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

105

SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

106

SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

107

SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

108

SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

109

SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

110

SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

111

SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

112

SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

113

SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

114

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

115

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

116

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

117

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

118

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

119

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

120

SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

121

SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

122

SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

123

SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

124

SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

125

SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

126

SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

127

SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

128

SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

129

SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

130

SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

131

SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

132

SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

133

SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

134

SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

135

SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

136

SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

137

SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

138

SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

139

SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

140

SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

141

SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

142

SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

143

SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

144

SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

145

SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

146

SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

147

SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

148

SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

149

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

150

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

151

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

152

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

153

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

154

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

155

SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

156

SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

157

SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

158

SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

159

SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

160

SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

161

SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

162

SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

163

SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

164

SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

165

SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

166

SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

167

SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

168

SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

169

SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

170

SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

171

SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

172

SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

173

SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

174

SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

175

SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

34

#define MPC_REG_LIST_DCN3_2(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

35

MPC_REG_LIST_DCN3_0(inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

36

SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

37

SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

38

SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

39

SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

40

SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

41

SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

42

SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

43

SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

44

SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

45

SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

46

SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

47

SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

48

SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

49

SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

50

SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

51

SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

52

SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

53

SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

54

SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

55

SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

56

SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

57

SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

58

SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

59

SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

60

SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

61

SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

62

SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

63

SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

64

SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

65

SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

66

SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

67

SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

68

SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

69

SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

70

SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

71

SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

72

SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

73

SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

74

SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

75

SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

76

SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

77

SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

78

SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

79

SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

80

SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

81

SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

82

SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

83

SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

84

SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

85

SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

86

SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

87

SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

88

SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

89

SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

90

SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

91

SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

92

SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

93

SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

94

SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

95

SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

96

SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

97

SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

98

SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

99

SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

106

#define MPC_REG_LIST_DCN4_01_RI(inst) \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

107

MPC_REG_LIST_DCN3_2_RI(inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

108

SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

109

SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

110

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

111

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

112

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

113

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

114

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

115

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

116

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

117

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

118

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

119

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

120

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

121

SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

122

SRII(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

123

SRII(MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

124

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

125

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

126

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

127

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

128

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

129

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

130

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

131

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

132

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

133

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

134

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

135

SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

136

SRII(MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

137

SRII(MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM, inst)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

400

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

407

oppn10->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

162

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

402

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

408

oppn20->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

141

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

40

uint32_t inst, const struct dcn35_opp_registers *regs,

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

44

dcn20_opp_construct(oppn20, ctx, inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

60

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

535

OPTC_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

676

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

684

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

694

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

893

MANUAL_FLOW_CONTROL_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

897

OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

100

TG_COMMON_REG_LIST_DCN(inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

101

SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

102

SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

103

SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

104

SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

34

#define TG_COMMON_REG_LIST_DCN(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

35

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

36

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

37

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

38

SRI(OTG_BLANK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

39

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

40

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

41

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

42

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

43

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

44

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

45

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

46

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

47

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

48

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

49

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

50

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

51

SRI(OTG_INTERLACE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

52

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

53

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

54

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

55

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

56

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

57

SRI(OTG_V_TOTAL_MID, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

58

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

59

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

60

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

61

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

62

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

63

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

64

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

65

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

66

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

67

SRI(OTG_BLACK_COLOR, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

68

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

73

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

74

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

75

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

76

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

77

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

78

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

79

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

80

SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

81

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

82

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

83

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

84

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

85

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

86

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

87

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

88

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

89

SRI(OTG_CRC1_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

90

SRI(OTG_CRC1_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

91

SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

92

SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

93

SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

94

SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

96

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

97

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

99

#define TG_COMMON_REG_LIST_DCN1_0(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

169

OPTC_SEG0_SRC_SEL, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

250

OPTC_DWB0_SOURCE_SELECT, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

253

OPTC_DWB1_SOURCE_SELECT, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

285

OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

375

OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

384

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

468

OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

60

OPTC_SEG0_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

31

#define TG_COMMON_REG_LIST_DCN2_0(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

32

TG_COMMON_REG_LIST_DCN(inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

33

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

34

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

35

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

36

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

37

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

38

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

39

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

40

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

41

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

42

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

43

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

45

SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

46

SRI(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

47

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

46

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

31

#define TG_COMMON_REG_LIST_DCN201(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

32

TG_COMMON_REG_LIST_DCN(inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

33

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

34

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

35

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

36

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

37

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

38

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

39

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

40

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

41

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

116

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

124

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

132

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

203

OPTC_SEG0_SRC_SEL, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

349

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

50

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

62

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

99

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

100

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

101

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

102

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

103

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

104

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

105

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

106

SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

107

SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

108

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

109

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

110

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

111

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

113

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

31

#define V_TOTAL_REGS_DCN30_SRI(inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

33

#define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

34

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

35

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

36

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

37

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

38

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

39

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

40

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

41

SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

42

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

43

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

44

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

45

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

46

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

47

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

48

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

49

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

50

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

51

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

52

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

53

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

54

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

55

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

56

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

57

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

58

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

59

V_TOTAL_REGS_DCN30_SRI(inst)\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

60

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

61

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

62

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

63

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

64

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

65

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

66

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

67

SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

68

SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

69

SRI(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

70

SRI(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

71

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

73

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

74

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

75

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

76

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

77

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

78

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

79

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

80

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

81

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

82

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

83

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

84

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

85

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

86

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

87

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

88

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

89

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

90

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

91

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

93

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

94

SRI(OTG_DRR_CONTROL, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

97

#define OPTC_COMMON_REG_LIST_DCN3_0(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

98

OPTC_COMMON_REG_LIST_DCN3_BASE(inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

99

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

103

OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

101

OPTC_SEG0_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

234

OPTC_SEG0_SRC_SEL, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

100

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

102

SRI(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

103

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

104

SRI(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

31

#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

32

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

33

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

34

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

35

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

36

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

37

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

38

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

39

SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

40

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

41

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

42

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

43

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

44

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

45

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

46

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

47

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

48

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

49

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

50

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

51

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

52

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

53

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

54

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

55

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

56

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

57

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

58

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

59

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

60

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

61

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

62

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

63

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

64

SRI(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

65

SRI(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

66

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

67

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

68

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

73

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

74

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

75

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

76

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

77

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

78

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

79

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

80

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

81

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

82

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

83

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

84

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

85

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

87

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

88

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

89

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

90

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

91

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

92

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

93

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

94

SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

95

SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

96

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

97

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

98

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

99

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

111

OPTC_SEG0_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

171

OPTC_SEG0_SRC_SEL, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

100

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

101

SRI(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

102

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

103

SRI(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

32

#define OPTC_COMMON_REG_LIST_DCN3_14(inst) \

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

33

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

34

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

35

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

36

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

37

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

38

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

39

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

40

SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

41

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

42

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

43

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

44

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

45

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

46

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

47

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

48

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

49

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

50

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

51

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

52

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

53

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

54

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

55

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

56

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

57

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

58

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

59

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

60

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

61

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

62

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

63

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

64

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

65

SRI(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

66

SRI(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

67

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

68

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

73

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

74

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

75

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

76

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

77

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

78

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

79

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

80

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

81

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

82

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

83

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

84

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

85

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

86

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

88

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

89

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

90

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

91

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

92

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

93

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

94

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

95

SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

96

SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

97

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

98

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

99

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

151

OPTC_SEG0_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

235

OPTC_SEG0_SRC_SEL, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

256

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

118

OPTC_SEG0_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

281

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

186

OPTC_SEG0_SRC_SEL, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

275

OPTC_SEG0_SRC_SEL, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

298

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

336

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

390

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

398

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

456

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

458

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

459

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

561

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

571

dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

584

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

592

dce_transform_construct(transform, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

593

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

598

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

607

dce_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

608

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

653

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

662

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

671

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

677

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

685

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

687

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

715

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

723

dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

724

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1153

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

503

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

505

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

506

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

605

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

615

dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

628

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

636

dce_transform_construct(transform, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

637

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

642

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

651

dce_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

652

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

697

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

706

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

715

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

721

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

729

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

731

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

759

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

767

dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

768

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

896

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

483

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

485

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

486

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

577

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

587

dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

599

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

607

dce_transform_construct(transform, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

608

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

658

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

666

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

675

dce_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

676

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

682

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

691

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

697

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

705

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

707

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

735

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

743

dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

744

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

428

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

437

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

442

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

450

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

452

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

480

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

488

dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

489

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

691

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

693

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

694

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

743

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

751

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

760

dce_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

761

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

873

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

883

dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

889

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

897

dce_transform_construct(transform, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

898

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

489

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

491

return dce60_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

492

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

512

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

521

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

527

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

535

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

537

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

565

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

573

dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

574

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

669

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

679

dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

692

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

700

dce60_transform_construct(transform, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

701

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

748

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

786

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

795

dce60_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

796

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

495

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

497

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

498

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

518

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

527

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

533

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

541

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

543

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

571

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

579

dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

580

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

675

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

685

dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

698

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

706

dce_transform_construct(transform, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

707

&xfm_regs[inst], &xfm_shift, &xfm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

754

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

792

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

801

dce_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

802

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1002

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1105

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

571

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

579

dpp1_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

580

&tf_regs[inst], &tf_shift, &tf_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

585

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

595

dcn10_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

596

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

602

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

612

dcn10_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

613

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

618

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

626

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

628

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

655

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

663

dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

664

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

711

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

770

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

810

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

812

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

813

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

981

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

989

dcn10_hubp_construct(hubp1, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

990

&hubp_regs[inst], &hubp_shift, &hubp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1061

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1071

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1198

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1206

if (hubp2_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1207

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1238

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1345

if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1347

res_ctx->is_dsc_acquired[dsc_old->inst] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1495

next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1551

secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1919

if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1923

if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2167

sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

733

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

741

if (dpp2_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

742

&tf_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

751

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

761

dcn20_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

762

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

768

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

778

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

779

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

785

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

793

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

795

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

823

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

831

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

832

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

890

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

950

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

990

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

992

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

993

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

102

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

107

uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

84

uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

87

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

90

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

93

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

97

uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1024

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

629

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

637

if (dpp201_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

638

&tf_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

646

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

655

dcn20_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

656

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

662

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

671

dcn201_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

672

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

677

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

685

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

687

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

710

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

718

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

719

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

767

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

848

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

850

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

851

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

983

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

991

if (dcn201_hubp_construct(hubp201, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

992

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1026

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1036

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1037

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1050

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1090

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1100

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1129

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1131

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1132

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1328

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

484

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

494

dcn20_ipp_construct(ipp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

495

&ipp_regs[inst], &ipp_shift, &ipp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

501

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

509

if (dpp2_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

510

&tf_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

520

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

528

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

530

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

557

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

565

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

566

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

979

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

987

if (hubp21_construct(hubp21, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

988

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1003

afmt3_construct(afmt3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1004

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1198

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1206

if (hubp3_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1207

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1266

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1276

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1538

sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

185

#define CLK_SRI(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

186

.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

187

mm ## block ## _ ## inst ## _ ## reg_name

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

750

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

758

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

759

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

768

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

778

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

779

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

785

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

793

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

795

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

824

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

832

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

833

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

898

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

954

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

971

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

973

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

974

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

979

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

986

vpg3_construct(vpg3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

987

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

996

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1158

static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1166

if (hubp3_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1167

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1226

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1236

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

189

#define CLK_SRI(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

190

.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

191

mm ## block ## _ ## inst ## _ ## reg_name

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

714

static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

722

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

723

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

731

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

741

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

742

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

746

static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

754

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

756

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

780

static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

788

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

789

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

854

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

910

&panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

942

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

944

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

945

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

950

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

957

vpg3_construct(vpg3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

958

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

967

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

974

afmt3_construct(afmt3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

975

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

297

static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

304

vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

329

static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

336

afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

367

static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

369

return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

504

static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

511

if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

538

static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

545

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

572

static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

581

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

611

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

680

static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

689

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

787

static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

794

dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

795

&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

818

static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

825

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

925

dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

290

static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

297

vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

319

static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

326

afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

357

static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

359

return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

485

static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

492

if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

516

static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

523

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

547

static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

556

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

583

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

641

static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

650

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

745

static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

752

dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

753

&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

773

static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

780

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

870

dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1064

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1159

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1161

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1162

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1167

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1174

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1175

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1184

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1191

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1192

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1203

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1210

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1211

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1305

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1315

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1316

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1496

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1504

if (hubp31_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1505

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1564

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1574

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

196

#define CLK_SRI(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

197

.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

198

reg ## block ## _ ## inst ## _ ## reg_name

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

916

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

924

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

925

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

934

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

944

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

945

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

951

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

959

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

961

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

988

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

996

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

997

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1046

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1054

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1055

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1122

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1217

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1219

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1220

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1225

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1232

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1233

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1242

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1249

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1250

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1261

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1268

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1269

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1364

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1374

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1375

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1554

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1562

if (hubp31_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1563

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1622

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1632

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

213

#define CLK_SRI(reg_name, block, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

214

.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

215

reg ## block ## _ ## inst ## _ ## reg_name

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

952

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

960

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

961

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

970

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

980

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

981

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

987

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

995

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

997

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1062

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1157

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1159

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1160

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1165

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1172

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1173

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1182

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1189

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1190

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1201

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1208

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1209

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1305

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1315

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1316

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1496

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1504

if (hubp31_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1505

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1564

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1574

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

914

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

922

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

923

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

932

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

942

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

943

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

949

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

957

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

959

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

986

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

994

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

995

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1056

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1151

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1153

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1154

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1159

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1166

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1167

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1176

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1183

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1184

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1196

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1203

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1204

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1300

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1310

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1311

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1489

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1497

if (hubp31_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1498

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1557

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1567

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

908

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

916

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

917

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

926

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

936

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

937

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

943

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

951

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

953

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

980

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

988

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

989

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1012

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1105

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1116

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1117

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1122

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1142

vpg3_construct(vpg3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1143

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1152

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1168

afmt3_construct(afmt3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1169

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1178

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1192

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1193

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1302

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1317

hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1318

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1563

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1580

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

160

#define SRII_ARR_2(reg_name, block, id, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

161

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2766

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2826

pool->dpps[free_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2858

free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

747

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

763

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

765

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

787

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

803

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

804

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

890

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

905

if (hubp32_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

906

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

922

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

937

if (dpp32_construct(dpp3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

938

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

972

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

989

dcn20_opp_construct(opp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

990

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1000

SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1001

SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1002

SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1003

SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1004

SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1005

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1006

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1007

SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1008

SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1009

SRI_ARR(OTG_H_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1010

SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1011

SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1012

SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1013

SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1014

SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1015

SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1016

SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1017

SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1018

SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1019

SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1020

SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1021

SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1022

SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1023

SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1024

SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1025

SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1026

SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1027

SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1028

SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1029

SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1030

SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1031

SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1032

SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1033

SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1034

SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1035

SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1036

SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1037

SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1038

SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1039

SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1040

SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1041

SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1042

SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1043

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1044

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1045

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1046

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1047

SR_ARR(GSL_SOURCE_SELECT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1048

SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1049

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1050

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1051

SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1052

SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1053

SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1054

SRI_ARR(OTG_DSC_START_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1055

SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1056

SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1057

SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1058

SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1059

SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1060

SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1061

SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1062

SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1063

SRI_ARR(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

672

#define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

673

SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

674

SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

675

SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

676

SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

677

SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

678

SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

679

SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

680

SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

681

SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

682

SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

683

SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

684

SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

685

SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

686

SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

687

SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

688

SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

689

SRI2_ARR(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

690

SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

691

SRI2_ARR(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

692

SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

693

SRI2_ARR(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

694

SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

695

SRI2_ARR(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

696

SRI2_ARR(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

697

SRI2_ARR(MCIF_WB_WATERMARK, MMHUBBUB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

698

SRI2_ARR(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

699

SRI2_ARR(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

700

SRI2_ARR(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

701

SRI2_ARR(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

702

SRI2_ARR(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

703

SRI2_ARR(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

704

SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

705

SRI2_ARR(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

706

SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

707

SRI2_ARR(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

708

SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

709

SRI2_ARR(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

710

SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

711

SRI2_ARR(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

712

SRI2_ARR(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

713

SRI2_ARR(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

714

SRI2_ARR(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

715

SRI2_ARR(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

716

SRI2_ARR(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

717

SRI2_ARR(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

718

SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

719

SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

720

SRI2_ARR(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

777

#define MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

778

SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

780

#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

781

SRII(MUX, MPC_OUT, inst), VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

783

#define MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

784

MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(CSC_MODE, MPC_OUT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

785

SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

786

SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

787

SRII(DENORM_CONTROL, MPC_OUT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

788

SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

789

SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

791

#define MPC_COMMON_REG_LIST_DCN1_0_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

792

SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

793

SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

794

SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

795

SRII(MPCC_BG_R_CR, MPCC, inst), SRII(MPCC_BG_B_CB, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

796

SRII(MPCC_SM_CONTROL, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

797

SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

799

#define MPC_REG_LIST_DCN3_0_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

800

MPC_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(MPCC_TOP_GAIN, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

801

SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

802

SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

803

SRII(MPCC_MEM_PWR_CTRL, MPCC, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

804

SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

805

SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

806

SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

807

SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

808

SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

809

SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

810

SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

811

SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

812

SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

813

SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

814

SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

815

SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

816

SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

817

SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

818

SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

819

SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

820

SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

821

SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

822

SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

823

SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

824

SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

825

SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

826

SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

827

SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

828

SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

829

SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

830

SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

831

SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

832

SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

833

SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

834

SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

835

SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

836

SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

837

SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

838

SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

839

SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

840

SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

841

SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

842

SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

843

SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

844

SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

845

SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

846

SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

847

SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

848

SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

849

SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

850

SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

851

SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

852

SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

853

SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

855

#define MPC_REG_LIST_DCN3_2_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

856

MPC_REG_LIST_DCN3_0_RI(inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

857

SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

858

SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

859

SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

860

SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

861

SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

862

SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

863

SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

864

SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

865

SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

866

SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

867

SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

868

SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

869

SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

870

SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

871

SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

872

SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

873

SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

874

SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

875

SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

876

SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

877

SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

878

SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

879

SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

880

SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

881

SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

882

SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

883

SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

884

SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

885

SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

886

SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

887

SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

888

SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

889

SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

890

SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

891

SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

892

SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

893

SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

894

SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

895

SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

896

SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

897

SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

898

SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

899

SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

900

SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

901

SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

902

SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

903

SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

904

SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

905

SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

906

SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

907

SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

908

SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

909

SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

910

SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

911

SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

912

SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

913

SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

914

SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

915

SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

916

SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

917

SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

918

SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

919

SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

920

SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

921

SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

922

SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

923

SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

924

SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

925

SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

926

SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

927

SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

928

SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

929

SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

930

SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

931

SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

932

SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

933

SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

934

SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

935

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

936

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

937

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

938

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

939

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

940

SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

941

SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

942

SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

943

SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

944

SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

945

SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

946

SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

947

SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

948

SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

949

SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

950

SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

951

SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

952

SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

953

SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

954

SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

955

SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

956

SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

957

SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

958

SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

959

SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

960

SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

961

SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

962

SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

963

SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

964

SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

965

SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

966

SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

967

SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

968

SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

969

SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

970

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

971

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

972

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

973

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

974

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

975

SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

976

SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

977

SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

978

SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

979

SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

980

SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

981

SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

982

SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

983

SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

984

SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

985

SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

986

SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

987

SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

988

SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

989

SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

990

SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

991

SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

992

SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

993

SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

994

SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

995

SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

996

SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

999

#define OPTC_COMMON_REG_LIST_DCN3_2_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1006

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1086

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1097

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1098

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1103

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1123

vpg3_construct(vpg3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1124

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1133

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1149

afmt3_construct(afmt3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1150

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1159

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1173

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1174

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1283

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1298

hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1299

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1543

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1560

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

160

#define SRII_ARR_2(reg_name, block, id, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

161

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

741

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

757

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

759

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

781

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

797

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

798

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

884

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

899

if (hubp32_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

900

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

916

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

931

if (dpp32_construct(dpp3, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

932

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

966

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

983

dcn20_opp_construct(opp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

984

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1045

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1164

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1177

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1178

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1183

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1203

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1204

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1213

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1229

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1230

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1241

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1255

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1256

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1365

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1380

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1381

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1568

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1583

if (hubp35_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1584

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1669

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1686

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

176

#define SRII_ARR_2(reg_name, block, id, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

177

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

808

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

823

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

838

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

855

dcn35_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

856

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

865

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

881

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

883

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

928

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

944

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

945

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

158

#define MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

159

MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

160

SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

218

#define OPTC_COMMON_REG_LIST_DCN3_5_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

219

SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

220

SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

221

SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

222

SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

223

SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

224

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

225

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

226

SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

227

SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

228

SRI_ARR(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

229

SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

230

SRI_ARR(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

231

SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

232

SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

233

SRI_ARR(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

234

SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

235

SRI_ARR(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

236

SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

237

SRI_ARR(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

238

SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

239

SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

240

SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

241

SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

242

SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

243

SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

244

SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

245

SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

246

SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

247

SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

248

SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

249

SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

250

SRI_ARR(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

251

SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

252

SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

253

SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

254

SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

255

SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

256

SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

257

SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

258

SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

259

SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

260

SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

261

SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

262

SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

263

SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

264

SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

265

SRI_ARR(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

266

SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

267

SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

268

SRI_ARR(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

269

SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

270

SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

271

SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

272

SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

273

SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

274

SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

275

SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

276

SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

277

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

278

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

279

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

280

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

281

SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

282

SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

283

SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

284

SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

285

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

286

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

287

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

288

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

289

SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

290

SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

291

SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

292

SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

293

SR_ARR(GSL_SOURCE_SELECT, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

294

SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

295

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

296

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

297

SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

298

SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

299

SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

300

SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

301

SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

302

SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

303

SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

304

SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

305

SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

306

SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

307

SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

308

SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

309

SRI_ARR(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1025

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1144

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1157

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1158

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1163

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1183

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1184

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1193

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1209

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1210

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1221

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1235

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1236

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1345

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1360

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1361

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1548

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

156

#define SRII_ARR_2(reg_name, block, id, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1563

if (hubp35_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1564

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

157

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1649

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1666

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

788

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

803

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

818

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

835

dcn35_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

836

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

845

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

861

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

863

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

908

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

924

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

925

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1026

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1145

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1158

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1159

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1164

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1184

vpg31_construct(vpg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1185

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1194

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1210

afmt31_construct(afmt31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1211

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1222

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1236

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1237

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1346

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1361

hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1362

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1549

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1564

if (hubp35_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1565

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

161

#define SRII_ARR_2(reg_name, block, id, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1650

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1667

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

789

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

804

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

819

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

836

dcn35_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

837

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

846

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

862

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

864

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

909

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

925

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

926

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1004

tgn10->base.inst = instance;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1079

struct dc_context *ctx, unsigned int inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1090

return dce_audio_create(ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1091

&audio_regs[inst], &audio_shift, &audio_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1096

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1116

vpg31_construct(vpg4, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1117

&vpg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1126

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1141

afmt3_construct(afmt401, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1142

&afmt_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1151

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1165

apg31_construct(apg31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1166

&apg_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1273

uint8_t inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1290

hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1291

&hpo_dp_link_enc_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

147

#define SRII_ARR_2(reg_name, block, id, inst)\

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

148

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1568

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1585

dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1711

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

742

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

757

dce110_aux_engine_construct(aux_engine, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

759

&aux_engine_regs[inst],

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

781

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

796

dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

797

&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

883

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

898

if (hubp401_construct(hubp2, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

899

&hubp_regs[inst], &hubp_shift, &hubp_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

915

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

930

if (dpp401_construct(dpp401, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

931

&dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

965

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

982

dcn20_opp_construct(opp4, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

983

&opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

468

#define MPC_DWB_MUX_REG_LIST_DCN4_01_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

469

MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

471

#define MPC_OUT_MUX_COMMON_REG_LIST_DCN4_01_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

472

MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

474

#define MPC_OUT_MUX_REG_LIST_DCN4_01_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

475

MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

478

#define OPTC_COMMON_REG_LIST_DCN401_RI(inst) \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

479

SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

480

SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

481

SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

482

SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

483

SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

484

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

485

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

486

SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

487

SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

488

SRI_ARR(OTG_H_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

489

SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

490

SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

491

SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

492

SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

493

SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

494

SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

495

SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

496

SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

497

SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

498

SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

499

SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

500

SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

501

SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

502

SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

503

SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

504

SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

505

SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

506

SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

507

SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

508

SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

509

SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

510

SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

511

SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

512

SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

513

SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

514

SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

515

SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

516

SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

517

SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

518

SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

519

SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

520

SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

521

SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

522

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

523

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

524

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

525

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

526

SR_ARR(GSL_SOURCE_SELECT, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

527

SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

528

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

529

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

530

SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

531

SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

532

SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

533

SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

534

SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

535

SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

536

SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

537

SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

538

SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

539

SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

540

SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

541

SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

542

SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

543

SRI_ARR(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2608

uint8_t inst : 6; /**< DOMAIN instance to control */

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

694

unsigned int inst)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

702

if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

756

if (res_pool->multiple_abms[inst]) {

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

757

result = res_pool->multiple_abms[inst]->funcs->init_abm_config(

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

758

res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.h

54

unsigned int inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

225

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

228

unsigned int vmid, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

231

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

237

struct mm_struct *mm, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

242

uint32_t doorbell_off, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

251

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

259

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

264

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

273

uint32_t sq_cmd, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

314

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

319

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

328

int *max_waves_per_cu, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

331

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

334

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

337

uint32_t inst, unsigned int utimeout);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

455

int inst);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

109

(adev)->powerplay.pp_handle, block_type, gate, inst));

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

615

void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

619

ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

76

int inst)

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

397

uint32_t block_type, bool gate, int inst);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

448

void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3296

int inst)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1237

int inst)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

112

reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

48

uint32_t inst;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2158

adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

251

int inst)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

266

if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

269

ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

271

atomic_set(&power_gate->vcn_gated[inst], !enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

392

int inst)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

411

ret = smu_dpm_set_vcn_enable(smu, !gate, inst);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

414

gate ? "gate" : "ungate", inst);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

802

int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

252

int inst);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

215

int inst);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1605

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1140

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1157

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1162

if (adev->vcn.harvest_config & (1 << inst))

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1168

0x10000 * inst, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

474

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

645

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2001

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2006

if (adev->vcn.harvest_config & (1 << inst))

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2011

inst << 16U, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

726

int inst, j, k, idx;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

736

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

740

JpegBusy[(inst * num_jpeg_rings) + j]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

743

SMUQ10_ROUND(metrics->VcnBusy[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

745

metrics->VclkFrequency[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

747

metrics->DclkFrequency[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

749

metrics->SocclkFrequency[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

760

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

761

xcp_metrics->current_gfxclk[idx] = SMUQ10_ROUND(metrics->GfxclkFrequency[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

762

xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

763

xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

765

xcp_metrics->gfx_below_host_limit_ppt_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

766

xcp_metrics->gfx_below_host_limit_thm_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

767

xcp_metrics->gfx_low_utilization_acc[idx] = SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

768

xcp_metrics->gfx_below_host_limit_total_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

781

int ret = 0, xcc_id, inst, i, j, k, idx;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

823

inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

824

if (inst >= 0) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

826

SMUQ10_ROUND(metrics->VclkFrequency[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

828

SMUQ10_ROUND(metrics->DclkFrequency[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

889

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

895

[(inst * NUM_JPEG_RINGS_FW) + j]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

898

SMUQ10_ROUND(metrics->VcnBusy[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

905

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

907

SMUQ10_ROUND(metrics->GfxBusy[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

909

SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

912

SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

914

SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

916

SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

918

SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

198

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2635

int ret, inst, i, j, k, idx;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2678

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2684

version)[(inst * num_jpeg_rings) + j]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2687

SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2690

GET_METRIC_FIELD(VclkFrequency, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2692

GET_METRIC_FIELD(DclkFrequency, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2694

GET_METRIC_FIELD(SocclkFrequency, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2706

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2709

version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2712

GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2715

version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2721

[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2725

[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2729

->GfxclkLowUtilizationAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2733

[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2749

int ret = 0, xcc_id, inst, i, j, k, idx;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2805

inst = GET_INST(VCN, i);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2806

if (inst >= 0) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2809

version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2812

version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2904

inst = GET_INST(VCN, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2910

[(inst * num_jpeg_rings) + j]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2913

SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2922

inst = GET_INST(GC, k);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2924

SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2927

version)[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2931

(metrics_v0->GfxclkBelowHostLimitPptAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2934

(metrics_v0->GfxclkBelowHostLimitThmAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2937

(metrics_v0->GfxclkLowUtilizationAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2940

(metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

225

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1571

int inst)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1576

if (adev->vcn.harvest_config & (1 << inst))

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1580

if (inst == 0)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1583

inst << 16U, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1584

else if (inst == 1)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1587

inst << 16U, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1591

inst << 16U, NULL);

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1773

static void init_power_well_domains(const struct i915_power_well_instance *inst,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1778

if (!inst->domain_list)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1781

if (inst->domain_list->count == 0) {

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1787

for (j = 0; j < inst->domain_list->count; j++)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1788

set_bit(inst->domain_list->list[j], power_well->domains.bits);

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1815

const struct i915_power_well_instance *inst;

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1819

for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1830

for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1832

enum i915_power_well_id id = inst->id;

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1836

overflows_type(inst - desc->instances->list, pw->instance_idx));

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1837

pw->instance_idx = inst - desc->instances->list;

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1839

init_power_well_domains(inst, pw);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

707

int inst = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

722

inst++);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1245

int inst = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1267

inst++);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

310

int class, inst;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

314

for (inst = 0; inst < i915->engine_uabi_class_count[class]; inst++) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

316

class, inst);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

319

class, inst);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

325

engine->uabi_instance != inst) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

330

class, inst);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3844

unsigned int inst;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3846

for (inst = 0; inst <= MAX_ENGINE_INSTANCE; inst++) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3847

if (!gt->engine_class[class][inst])

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3850

if (filter && !filter(gt->engine_class[class][inst]))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3853

siblings[n++] = gt->engine_class[class][inst];

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

365

u8 group, inst;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

375

intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

376

flags |= GUC_REGSET_STEERING(group, inst);

sys/dev/pci/if_bnx.c

2865

REG_WR_IND(sc, cpu_reg->inst, 0);

sys/dev/pci/if_bnx.c

2914

cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

2961

cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3008

cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3055

cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;

sys/dev/pci/if_bnxreg.h

4660

u_int32_t inst;

sys/net/if_media.c

422

ifmedia_delete_instance(struct ifmedia *ifm, uint64_t inst)

sys/net/if_media.c

431

if (inst == IFM_INST_ANY ||

sys/net/if_media.c

432

inst == IFM_INST(ife->ifm_media)) {

usr.bin/openssl/ocsp.c

1308

ASN1_OBJECT *inst = NULL;

usr.bin/openssl/ocsp.c

1314

unpack_revinfo(&revtm, &reason, &inst, &invtm,

usr.bin/openssl/ocsp.c

1323

else if (inst)

usr.bin/openssl/ocsp.c

1325

NID_hold_instruction_code, inst, 0, 0);

usr.bin/openssl/ocsp.c

1326

ASN1_OBJECT_free(inst);

usr.bin/ssh/sshconnect2.c

1947

char *name = NULL, *inst = NULL, *lang = NULL, *prompt = NULL;

usr.bin/ssh/sshconnect2.c

1962

(r = sshpkt_get_cstring(ssh, &inst, NULL)) != 0 ||

usr.bin/ssh/sshconnect2.c

1969

if ((len = strlen(inst)) > 0) {

usr.bin/ssh/sshconnect2.c

1970

addnl = inst[len] != '\n';

usr.bin/ssh/sshconnect2.c

1971

fmprintf(stderr, "%s%s", inst, addnl ? "\n" : "");

usr.bin/ssh/sshconnect2.c

2014

free(inst);

usr.sbin/httpd/proc.c

146

unsigned int src, dst, inst;

usr.sbin/httpd/proc.c

157

for (inst = 0; inst < ps->ps_instances[dst]; inst++) {

usr.sbin/httpd/proc.c

158

iev = &ps->ps_ievs[dst][inst];

usr.sbin/httpd/proc.c

160

ps->ps_pp->pp_pipes[dst][inst]) == -1)

usr.sbin/relayd/proc.c

146

unsigned int src, dst, inst;

usr.sbin/relayd/proc.c

157

for (inst = 0; inst < ps->ps_instances[dst]; inst++) {

usr.sbin/relayd/proc.c

158

iev = &ps->ps_ievs[dst][inst];

usr.sbin/relayd/proc.c

160

ps->ps_pp->pp_pipes[dst][inst]) == -1)

usr.sbin/snmpd/proc.c

148

unsigned int src, dst, inst;

usr.sbin/snmpd/proc.c

163

for (inst = 0; inst < ps->ps_instances[dst]; inst++) {

usr.sbin/snmpd/proc.c

164

iev = &ps->ps_ievs[dst][inst];

usr.sbin/snmpd/proc.c

166

ps->ps_pp->pp_pipes[dst][inst]) == -1)

usr.sbin/snmpd/proc.c

194

for (inst = 0; inst < ps->ps_instances[dst]; inst++) {

usr.sbin/snmpd/proc.c

195

if (proc_compose_imsg(ps, dst, inst, IMSG_CTL_PROCREADY,

usr.sbin/snmpd/proc.c

200

ps->ps_connecting, ps->ps_title[dst], inst + 1);