games/battlestar/fly.c

100

dc = -5;

games/battlestar/fly.c

105

dc = 1;

games/battlestar/fly.c

110

dc = 5;

games/battlestar/fly.c

257

if (column + dc < COLS - 1 && column + dc > 0)

games/battlestar/fly.c

258

column += dc;

games/battlestar/fly.c

48

static int dr = 0, dc = 0;

games/battlestar/fly.c

94

dc = -1;

games/fortune/strfile/strfile.c

130

char *sp, dc;

games/fortune/strfile/strfile.c

143

dc = Delimch;

games/fortune/strfile/strfile.c

162

Tbl.str_delim = dc;

games/fortune/strfile/strfile.c

169

if (sp == NULL || (sp[0] == dc && sp[1] == '\n')) {

games/sail/dr_2.c

204

*col -= dc[*dir] * dist;

games/sail/dr_2.c

213

*col -= dc[winddir];

games/sail/dr_3.c

239

sp->file->col -= dc[sp->file->dir] * dist;

games/sail/dr_3.c

250

sp->file->col -= dc[winddir];

games/sail/extern.h

289

extern const char dr[], dc[];

games/sail/extern.h

82

#define sterncol(sp) ((sp)->file->col + dc[(sp)->file->dir])

games/sail/globals.c

537

const char dc[] = { 0, 0, -1, -1, -1, 0, 1, 1, 1 };

games/sail/misc.c

104

angle(int dr, int dc)

games/sail/misc.c

108

if (dc >= 0 && dr > 0)

games/sail/misc.c

110

else if (dr <= 0 && dc > 0)

games/sail/misc.c

112

else if (dc <= 0 && dr < 0)

games/sail/misc.c

117

dc = abs(dc);

games/sail/misc.c

118

if ((i == 0 || i == 4) && dc * 2.4 > dr) {

games/sail/misc.c

120

if (dc > dr * 2.4)

games/sail/misc.c

122

} else if ((i == 2 || i == 6) && dr * 2.4 > dc) {

games/sail/misc.c

124

if (dr > dc * 2.4)

games/sail/misc.c

147

Dc += dc[to->file->dir];

games/sail/misc.c

163

Dc += dc[on->file->dir];

games/sail/misc.c

65

stern2c += dc[to->file->dir];

games/sail/misc.c

67

stern1c += dc[from->file->dir];

games/sail/pl_7.c

396

(void) wmove(slot_w, Y - dr[winddir], 1 - dc[winddir]);

games/sail/pl_7.c

415

(void) mvwaddch(slot_w, Y + dr[winddir], 1 + dc[winddir], '+');

lib/libc/gen/glob.c

729

Char *dc;

lib/libc/gen/glob.c

743

dc = pathend;

lib/libc/gen/glob.c

745

while (dc < pathend_last && (*dc++ = *sc++) != EOS)

lib/libc/gen/glob.c

747

if (dc >= pathend_last) {

lib/libc/gen/glob.c

748

*dc = EOS;

lib/libc/gen/glob.c

757

err = glob2(pathbuf, pathbuf_last, --dc, pathend_last,

lib/libkeynote/auxil.c

136

struct keynote_deckey dc;

lib/libkeynote/auxil.c

152

if (kn_decode_key(&dc, key, KEYNOTE_PUBLIC_KEY) != 0)

lib/libkeynote/auxil.c

158

kl->key_key = dc.dec_key;

lib/libkeynote/auxil.c

159

kl->key_alg = dc.dec_algorithm;

lib/libkeynote/auxil.c

291

kn_free_key(struct keynote_deckey *dc)

lib/libkeynote/auxil.c

293

if (dc)

lib/libkeynote/auxil.c

294

keynote_free_key(dc->dec_key, dc->dec_algorithm);

lib/libkeynote/keynote-keygen.c

103

struct keynote_deckey dc;

lib/libkeynote/keynote-keygen.c

200

dc.dec_algorithm = KEYNOTE_ALGORITHM_DSA;

lib/libkeynote/keynote-keygen.c

201

dc.dec_key = (void *) dsa;

lib/libkeynote/keynote-keygen.c

203

foo = kn_encode_key(&dc, ienc, enc, KEYNOTE_PUBLIC_KEY);

lib/libkeynote/keynote-keygen.c

228

foo = kn_encode_key(&dc, ienc, enc, KEYNOTE_PRIVATE_KEY);

lib/libkeynote/keynote-keygen.c

281

dc.dec_algorithm = KEYNOTE_ALGORITHM_RSA;

lib/libkeynote/keynote-keygen.c

282

dc.dec_key = (void *) rsa;

lib/libkeynote/keynote-keygen.c

284

foo = kn_encode_key(&dc, ienc, enc, KEYNOTE_PUBLIC_KEY);

lib/libkeynote/keynote-keygen.c

309

foo = kn_encode_key(&dc, ienc, enc, KEYNOTE_PRIVATE_KEY);

lib/libkeynote/signature.c

1057

struct keynote_deckey dc;

lib/libkeynote/signature.c

1087

i = kn_decode_key(&dc, s, KEYNOTE_PRIVATE_KEY);

lib/libkeynote/signature.c

1096

dc.dec_key = key;

lib/libkeynote/signature.c

1097

dc.dec_algorithm = alg;

lib/libkeynote/signature.c

1105

keynote_free_key(dc.dec_key, dc.dec_algorithm);

lib/libkeynote/signature.c

1111

sig = keynote_sign_assertion(as, sigalg, dc.dec_key, dc.dec_algorithm,

lib/libkeynote/signature.c

1114

keynote_free_key(dc.dec_key, dc.dec_algorithm);

lib/libkeynote/signature.c

1125

kn_encode_key(struct keynote_deckey *dc, int iencoding,

lib/libkeynote/signature.c

1136

if (dc == NULL || dc->dec_key == NULL)

lib/libkeynote/signature.c

1143

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_DSA) &&

lib/libkeynote/signature.c

1147

dsa = (DSA *) dc->dec_key;

lib/libkeynote/signature.c

1206

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_RSA) &&

lib/libkeynote/signature.c

1210

rsa = (RSA *) dc->dec_key;

lib/libkeynote/signature.c

1269

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_BINARY) &&

lib/libkeynote/signature.c

1273

bn = (struct keynote_binary *) dc->dec_key;

lib/libkeynote/signature.c

352

kn_decode_key(struct keynote_deckey *dc, char *key, int keytype)

lib/libkeynote/signature.c

362

dc->dec_algorithm = keynote_get_private_key_algorithm(key, &encoding,

lib/libkeynote/signature.c

365

dc->dec_algorithm = keynote_get_key_algorithm(key, &encoding,

lib/libkeynote/signature.c

367

if (dc->dec_algorithm == KEYNOTE_ALGORITHM_NONE)

lib/libkeynote/signature.c

369

if ((dc->dec_key = strdup(key)) == NULL) {

lib/libkeynote/signature.c

430

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_DSA) &&

lib/libkeynote/signature.c

435

if ((dc->dec_key =

lib/libkeynote/signature.c

446

if ((dc->dec_key =

lib/libkeynote/signature.c

462

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_RSA) &&

lib/libkeynote/signature.c

467

if ((dc->dec_key =

lib/libkeynote/signature.c

475

if (RSA_blinding_on(dc->dec_key, NULL) != 1) {

lib/libkeynote/signature.c

477

RSA_free(dc->dec_key);

lib/libkeynote/signature.c

484

if ((dc->dec_key =

lib/libkeynote/signature.c

500

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_X509) &&

lib/libkeynote/signature.c

520

dc->dec_key = EVP_PKEY_get0_RSA(pPublicKey);

lib/libkeynote/signature.c

521

RSA_up_ref(dc->dec_key);

lib/libkeynote/signature.c

529

if ((dc->dec_algorithm == KEYNOTE_ALGORITHM_BINARY) &&

lib/libkeynote/signature.c

532

dc->dec_key = calloc(1, sizeof(struct keynote_binary));

lib/libkeynote/signature.c

533

if (dc->dec_key == NULL)

lib/libkeynote/signature.c

539

((struct keynote_binary *) dc->dec_key)->bn_key = decoded;

lib/libkeynote/signature.c

540

((struct keynote_binary *) dc->dec_key)->bn_len = len;

sbin/isakmpd/ike_auth.c

187

struct keynote_deckey dc;

sbin/isakmpd/ike_auth.c

235

if (!buf2 || kn_decode_key(&dc, buf2,

sbin/isakmpd/ike_auth.c

245

if (dc.dec_algorithm != KEYNOTE_ALGORITHM_RSA) {

sbin/isakmpd/ike_auth.c

247

"type %d in \"%s\"", dc.dec_algorithm,

sbin/isakmpd/ike_auth.c

250

kn_free_key(&dc);

sbin/isakmpd/ike_auth.c

254

return dc.dec_key;

sbin/isakmpd/ike_auth.c

715

struct keynote_deckey dc;

sbin/isakmpd/ike_auth.c

718

dc.dec_algorithm = KEYNOTE_ALGORITHM_RSA;

sbin/isakmpd/ike_auth.c

719

dc.dec_key = key;

sbin/isakmpd/ike_auth.c

721

pp = kn_encode_key(&dc, INTERNAL_ENC_PKCS1,

sbin/isakmpd/ike_auth.c

724

kn_free_key(&dc);

sbin/isakmpd/ike_auth.c

732

kn_free_key(&dc);

sbin/isakmpd/ike_quick_mode.c

237

dc.dec_algorithm = KEYNOTE_ALGORITHM_RSA;

sbin/isakmpd/ike_quick_mode.c

245

dc.dec_key = isakmp_sa->recv_key;

sbin/isakmpd/ike_quick_mode.c

246

principal[0] = kn_encode_key(&dc, INTERNAL_ENC_PKCS1,

sbin/isakmpd/ike_quick_mode.c

98

struct keynote_deckey dc;

sbin/isakmpd/policy.c

2079

struct keynote_deckey dc;

sbin/isakmpd/policy.c

2091

if (kn_decode_key(&dc, dat, KEYNOTE_PUBLIC_KEY) != 0)

sbin/isakmpd/policy.c

2094

kn_free_key(&dc);

sbin/isakmpd/x509.c

111

struct keynote_deckey dc;

sbin/isakmpd/x509.c

138

dc.dec_algorithm = KEYNOTE_ALGORITHM_RSA;

sbin/isakmpd/x509.c

139

dc.dec_key = key;

sbin/isakmpd/x509.c

140

ikey = kn_encode_key(&dc, INTERNAL_ENC_PKCS1, ENCODING_HEX,

sbin/isakmpd/x509.c

203

dc.dec_algorithm = KEYNOTE_ALGORITHM_RSA;

sbin/isakmpd/x509.c

204

dc.dec_key = key;

sbin/isakmpd/x509.c

205

skey = kn_encode_key(&dc, INTERNAL_ENC_PKCS1, ENCODING_HEX,

sbin/unwind/libunbound/validator/autotrust.c

333

uint16_t dc)

sbin/unwind/libunbound/validator/autotrust.c

345

tp->dclass = dc;

sys/arch/amd64/stand/libsa/diskprobe.c

123

const char *dc = (const char *)((0x40 << 4) + 0x75);

sys/arch/amd64/stand/libsa/diskprobe.c

126

for (i = 0x80; i < (0x80 + *dc); i++) {

sys/arch/i386/stand/libsa/diskprobe.c

127

const char *dc = (const char *)((0x40 << 4) + 0x75);

sys/arch/i386/stand/libsa/diskprobe.c

130

for (i = 0x80; i < (0x80 + *dc); i++) {

sys/arch/luna88k/dev/lunafb.c

219

struct om_hwdevconfig *dc = &omfb_console_dc;

sys/arch/luna88k/dev/lunafb.c

220

struct rasops_info *ri = &dc->dc_ri;

sys/arch/luna88k/dev/lunafb.c

223

omfb_getdevconfig(OMFB_FB_WADDR, dc);

sys/arch/luna88k/dev/lunafb.c

234

struct om_hwdevconfig *dc = sc->sc_dc;

sys/arch/luna88k/dev/lunafb.c

243

wsd_fbip->height = dc->dc_ht;

sys/arch/luna88k/dev/lunafb.c

244

wsd_fbip->width = dc->dc_wid;

sys/arch/luna88k/dev/lunafb.c

245

wsd_fbip->depth = dc->dc_depth;

sys/arch/luna88k/dev/lunafb.c

246

wsd_fbip->stride = dc->dc_rowbytes;

sys/arch/luna88k/dev/lunafb.c

248

wsd_fbip->cmsize = dc->dc_cmsize;

sys/arch/luna88k/dev/lunafb.c

253

*(u_int *)data = dc->dc_rowbytes;

sys/arch/luna88k/dev/lunafb.c

263

if (dc->dc_depth == 8)

sys/arch/luna88k/dev/lunafb.c

298

struct om_hwdevconfig *dc = sc->sc_dc;

sys/arch/luna88k/dev/lunafb.c

306

cookie = (paddr_t)(trunc_page(dc->dc_videobase) + offset);

sys/arch/luna88k/dev/lunafb.c

309

offset < dc->dc_rowbytes * dc->dc_ht * hwplanebits + PAGE_SIZE)

sys/arch/luna88k/dev/lunafb.c

397

omfb_getdevconfig(paddr_t paddr, struct om_hwdevconfig *dc)

sys/arch/luna88k/dev/lunafb.c

410

if ((hwplanebits > 0) && (dc->dc_depth_checked == 0)) {

sys/arch/luna88k/dev/lunafb.c

425

dc->dc_depth_checked = 1;

sys/arch/luna88k/dev/lunafb.c

428

dc->dc_wid = 1280;

sys/arch/luna88k/dev/lunafb.c

429

dc->dc_ht = 1024;

sys/arch/luna88k/dev/lunafb.c

430

dc->dc_depth = hwplanebits;

sys/arch/luna88k/dev/lunafb.c

431

dc->dc_rowbytes = 2048 / 8;

sys/arch/luna88k/dev/lunafb.c

432

dc->dc_cmsize = (hwplanebits == 1) ? 0 : 1 << hwplanebits;

sys/arch/luna88k/dev/lunafb.c

433

dc->dc_videobase = paddr;

sys/arch/luna88k/dev/lunafb.c

436

omfb_set_default_cmap(dc);

sys/arch/luna88k/dev/lunafb.c

445

omfb_clear_framebuffer(dc);

sys/arch/luna88k/dev/lunafb.c

448

ri = &dc->dc_ri;

sys/arch/luna88k/dev/lunafb.c

449

ri->ri_width = dc->dc_wid;

sys/arch/luna88k/dev/lunafb.c

450

ri->ri_height = dc->dc_ht;

sys/arch/luna88k/dev/lunafb.c

452

ri->ri_stride = dc->dc_rowbytes;

sys/arch/luna88k/dev/lunafb.c

453

ri->ri_bits = (void *)dc->dc_videobase;

sys/arch/luna88k/dev/lunafb.c

455

ri->ri_hw = dc;

sys/arch/luna88k/dev/lunafb.c

581

omfb_clear_framebuffer(struct om_hwdevconfig *dc)

sys/arch/luna88k/dev/lunafb.c

587

for (i = 0; i < dc->dc_ht * dc->dc_rowbytes / sizeof(u_int32_t); i++)

sys/arch/luna88k/dev/lunafb.c

588

*((volatile u_int32_t *)dc->dc_videobase + i) = 0;

sys/arch/luna88k/dev/lunafb.c

608

omfb_set_default_cmap(struct om_hwdevconfig *dc)

sys/arch/luna88k/dev/lunafb.c

621

odac->bt_cmap = dc->dc_cmap.r[i] = 0;

sys/arch/luna88k/dev/lunafb.c

622

odac->bt_cmap = dc->dc_cmap.g[i] = 0;

sys/arch/luna88k/dev/lunafb.c

623

odac->bt_cmap = dc->dc_cmap.b[i] = 0;

sys/arch/luna88k/dev/lunafb.c

629

odac->bt_cmap = dc->dc_cmap.r[15] = 0;

sys/arch/luna88k/dev/lunafb.c

630

odac->bt_cmap = dc->dc_cmap.g[15] = 255;

sys/arch/luna88k/dev/lunafb.c

631

odac->bt_cmap = dc->dc_cmap.b[15] = 0;

sys/arch/luna88k/dev/lunafb.c

636

if (dc->dc_depth == 1) {

sys/arch/luna88k/dev/lunafb.c

641

odac->bt_cmap = dc->dc_cmap.r[i] = val;

sys/arch/luna88k/dev/lunafb.c

642

odac->bt_cmap = dc->dc_cmap.g[i] = val;

sys/arch/luna88k/dev/lunafb.c

643

odac->bt_cmap = dc->dc_cmap.b[i] = val;

sys/arch/luna88k/dev/lunafb.c

648

odac->bt_cmap = dc->dc_cmap.r[i]

sys/arch/luna88k/dev/lunafb.c

650

odac->bt_cmap = dc->dc_cmap.g[i]

sys/arch/luna88k/dev/lunafb.c

652

odac->bt_cmap = dc->dc_cmap.b[i]

sys/arch/luna88k/dev/lunafb.c

674

if (dc->dc_depth == 1) {

sys/arch/luna88k/dev/lunafb.c

679

ndac->bt_cmap = dc->dc_cmap.r[i] = val;

sys/arch/luna88k/dev/lunafb.c

680

ndac->bt_cmap = dc->dc_cmap.g[i] = val;

sys/arch/luna88k/dev/lunafb.c

681

ndac->bt_cmap = dc->dc_cmap.b[i] = val;

sys/arch/luna88k/dev/lunafb.c

690

ndac->bt_cmap = dc->dc_cmap.r[i]

sys/arch/luna88k/dev/lunafb.c

692

ndac->bt_cmap = dc->dc_cmap.g[i]

sys/arch/luna88k/dev/lunafb.c

694

ndac->bt_cmap = dc->dc_cmap.b[i]

sys/dev/dt/dt_dev.c

249

struct dt_cpubuf *dc;

sys/dev/dt/dt_dev.c

272

dc = &sc->ds_cpu[(sc->ds_lastcpu + i) % ncpusfound];

sys/dev/dt/dt_dev.c

273

error = dt_ring_copy(dc, uio, max, &count);

sys/dev/dt/dt_dev.c

502

struct dt_cpubuf *dc;

sys/dev/dt/dt_dev.c

508

dc = &sc->ds_cpu[i];

sys/dev/dt/dt_dev.c

511

dropevt += dc->dc_dropevt;

sys/dev/dt/dt_dev.c

512

skiptick = dc->dc_skiptick;

sys/dev/dt/dt_dev.c

513

recurevt = dc->dc_recurevt;

sys/dev/dt/dt_dev.c

514

readevt += dc->dc_readevt;

sys/dev/dt/dt_dev.c

801

struct dt_cpubuf *dc = &dp->dp_sc->ds_cpu[cpu_number()];

sys/dev/dt/dt_dev.c

803

dc->dc_skiptick += skip;

sys/dev/dt/dt_dev.c

816

struct dt_cpubuf *dc = &dp->dp_sc->ds_cpu[cpu_number()];

sys/dev/dt/dt_dev.c

818

if (dc->dc_inevt == 1) {

sys/dev/dt/dt_dev.c

819

dc->dc_recurevt++;

sys/dev/dt/dt_dev.c

824

dc->dc_inevt = 1;

sys/dev/dt/dt_dev.c

827

prod = dc->dc_prod;

sys/dev/dt/dt_dev.c

828

cons = dc->dc_cons;

sys/dev/dt/dt_dev.c

832

dc->dc_dropevt++;

sys/dev/dt/dt_dev.c

835

dc->dc_inevt = 0;

sys/dev/dt/dt_dev.c

842

dtev = &dc->dc_ring[cons];

sys/dev/dt/dt_dev.c

869

struct dt_cpubuf *dc = &dp->dp_sc->ds_cpu[cpu_number()];

sys/dev/dt/dt_dev.c

871

KASSERT(dtev == &dc->dc_ring[dc->dc_cons]);

sys/dev/dt/dt_dev.c

873

dc->dc_cons = (dc->dc_cons + 1) % DT_EVTRING_SIZE;

sys/dev/dt/dt_dev.c

877

dc->dc_inevt = 0;

sys/dev/dt/dt_dev.c

887

dt_ring_copy(struct dt_cpubuf *dc, struct uio *uio, size_t max, size_t *rcvd)

sys/dev/dt/dt_dev.c

896

cons = dc->dc_cons;

sys/dev/dt/dt_dev.c

897

prod = dc->dc_prod;

sys/dev/dt/dt_dev.c

908

error = uiomove(&dc->dc_ring[prod], count * sizeof(struct dt_evt), uio);

sys/dev/dt/dt_dev.c

921

error = uiomove(&dc->dc_ring[0], count * sizeof(struct dt_evt), uio);

sys/dev/dt/dt_dev.c

929

dc->dc_readevt += copied;

sys/dev/dt/dt_dev.c

930

dc->dc_prod = prod;

sys/dev/ic/mfi.c

1428

mfi_ioctl_cache(struct scsi_link *link, u_long cmd, struct dk_cache *dc)

sys/dev/ic/mfi.c

1463

dc->wrcache = wrenable;

sys/dev/ic/mfi.c

1464

dc->rdcache = rdenable;

sys/dev/ic/mfi.c

1468

if (((dc->wrcache) ? 1 : 0) == wrenable &&

sys/dev/ic/mfi.c

1469

((dc->rdcache) ? 1 : 0) == rdenable)

sys/dev/ic/mfi.c

1478

if (dc->rdcache)

sys/dev/ic/mfi.c

1484

if (dc->wrcache)

sys/dev/ic/mfi.c

1491

if (dc->rdcache) {

sys/dev/ic/mfi.c

1495

if (dc->wrcache)

sys/dev/ic/mpi.c

2984

mpi_ioctl_cache(struct scsi_link *link, u_long cmd, struct dk_cache *dc)

sys/dev/ic/mpi.c

3019

dc->wrcache = enabled;

sys/dev/ic/mpi.c

3020

dc->rdcache = 0;

sys/dev/ic/mpi.c

3024

if (dc->rdcache) {

sys/dev/ic/mpi.c

3029

if (((dc->wrcache) ? 1 : 0) == enabled)

sys/dev/ic/mpi.c

3033

if (dc->wrcache) {

sys/dev/ic/qwxreg.h

4026

uint32_t dc;

sys/dev/ic/qwxreg.h

4035

uint32_t dc;

sys/dev/ic/qwzreg.h

4081

uint32_t dc;

sys/dev/ic/qwzreg.h

4090

uint32_t dc;

sys/dev/isa/pcdisplay.c

171

pcdisplay_init(struct pcdisplay_config *dc, bus_space_tag_t iot,

sys/dev/isa/pcdisplay.c

174

struct pcdisplay_handle *ph = &dc->dc_ph;

sys/dev/isa/pcdisplay.c

179

dc->mono = mono;

sys/dev/isa/pcdisplay.c

191

dc->pcs.hdl = ph;

sys/dev/isa/pcdisplay.c

192

dc->pcs.type = &pcdisplay_scr;

sys/dev/isa/pcdisplay.c

193

dc->pcs.active = 1;

sys/dev/isa/pcdisplay.c

194

dc->pcs.mem = NULL;

sys/dev/isa/pcdisplay.c

203

dc->pcs.dispoffset = 0;

sys/dev/isa/pcdisplay.c

204

dc->pcs.visibleoffset = 0;

sys/dev/isa/pcdisplay.c

206

dc->pcs.vc_crow = cpos / pcdisplay_scr.ncols;

sys/dev/isa/pcdisplay.c

207

dc->pcs.vc_ccol = cpos % pcdisplay_scr.ncols;

sys/dev/isa/pcdisplay.c

208

pcdisplay_cursor_init(&dc->pcs, 1);

sys/dev/isa/pcdisplay.c

253

struct pcdisplay_config *dc;

sys/dev/isa/pcdisplay.c

261

dc = &pcdisplay_console_dc;

sys/dev/isa/pcdisplay.c

265

dc = malloc(sizeof(struct pcdisplay_config),

sys/dev/isa/pcdisplay.c

269

pcdisplay_init(dc, ia->ia_iot, ia->ia_memt, 0);

sys/dev/isa/pcdisplay.c

272

pcdisplay_init(dc, ia->ia_iot, ia->ia_memt, 1);

sys/dev/isa/pcdisplay.c

276

sc->sc_dc = dc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

483

MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

484

module_param_named(dc, amdgpu_dc, int, 0444);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10039

dm->dc, acrtc_state->stream,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10044

update_planes_and_stream_adapter(dm->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1005

if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10185

dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1021

if (dc_enable_dmub_notifications(adev->dm.dc) &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1025

dc_stat_get_dmub_notification(adev->dm.dc, &notify);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10270

dc_exit_ips_for_hw_access(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10346

dc_exit_ips_for_hw_access(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10347

WARN_ON(!dc_commit_streams(dm->dc, &params));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10351

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10425

if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10426

pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10483

dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10770

dc_exit_ips_for_hw_access(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10771

dc_update_planes_and_stream(dm->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1082

if (adev->dm.dc->fbc_compressor == NULL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1105

adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11362

dm->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11405

dm->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11757

static int dm_update_plane_state(struct dc *dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11821

dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11860

dc_new_plane_state = dc_create_plane_state(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11893

dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1198

adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1208

adev->dm.dc->res_pool->audios[i]->inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12262

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12307

if (dc_resource_is_dsc_encoding_supported(dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12441

ret = dm_update_plane_state(dc, state, plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12481

ret = dm_update_plane_state(dc, state, plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12494

if (dc_resource_is_dsc_encoding_supported(dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1257

struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1258

struct abm *abm = adev->dm.dc->res_pool->abm;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1259

struct dc_context *ctx = adev->dm.dc->ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12650

if (dc_resource_is_dsc_encoding_supported(dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12677

status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12798

res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12840

if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12847

res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12861

res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13139

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13143

if (dc->current_state) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13144

for (i = 0; i < dc->current_state->stream_count; ++i)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13145

dc->current_state->streams[i]

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13149

dm_enable_per_frame_crtc_master_sync(dc->current_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13150

dc_trigger_sync(dc, dc->current_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13155

static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13157

if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13158

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13172

amdgpu_dm_exit_ips_for_hw_access(ctx->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13196

amdgpu_dm_exit_ips_for_hw_access(ctx->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13216

if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13344

is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1371

hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1405

if (!adev->dm.dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1406

adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1407

if (!adev->dm.dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1426

adev->dm.dc->debug.sanity_checks = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1432

adev->dm.dc->debug.sanity_checks = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1658

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1659

int max_caps = dc->caps.max_links;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2025

adev->dm.dc = dc_create(&init_data);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2027

if (adev->dm.dc) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2029

dce_version_to_string(adev->dm.dc->ctx->dce_version));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2036

adev->dm.dc->debug.force_single_disp_pipe_split = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2037

adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2041

adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2043

adev->dm.dc->debug.disable_stutter = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2046

adev->dm.dc->debug.disable_stutter = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2049

adev->dm.dc->debug.disable_dsc = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2052

adev->dm.dc->debug.disable_clock_gate = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2055

adev->dm.dc->debug.force_subvp_mclk_switch = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2058

adev->dm.dc->debug.force_disable_subvp = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2059

adev->dm.dc->debug.fams2_config.bits.enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2063

adev->dm.dc->debug.using_dml2 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2064

adev->dm.dc->debug.using_dml21 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2068

adev->dm.dc->debug.hdcp_lc_force_fw_enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2071

adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2074

adev->dm.dc->debug.skip_detection_link_training = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2076

adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2079

adev->dm.dc->debug.ignore_cable_id = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2081

if (adev->dm.dc->caps.dp_hdmi21_pcon_support)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2090

dc_hardware_init(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2104

dc_setup_system_context(adev->dm.dc, &pa_config);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2107

adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2117

if (adev->dm.dc->caps.max_links > 0) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2124

if (adev->dm.dc->caps.ips_support &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2125

adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2128

if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2129

adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2136

dc_init_callbacks(adev->dm.dc, &init_params);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2138

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2173

dc_enable_dmub_outbox(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2177

dc_dmub_srv_enable_dpia_trace(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2192

adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2193

adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2271

if (adev->dm.dc) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2272

dc_deinit_callbacks(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2273

dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2274

if (dc_enable_dmub_notifications(adev->dm.dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2287

if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2288

for (i = 0; i < adev->dm.dc->caps.max_links; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2300

if (adev->dm.dc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2301

dc_destroy(&adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2434

return dm_read_reg(adev->dm.dc->ctx, address);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2442

return dm_write_reg(adev->dm.dc->ctx, address, value);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2722

dmcu = adev->dm.dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2745

} else if (adev->dm.dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2749

dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2751

if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

288

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2952

oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

301

if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

302

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3044

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3049

if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3068

if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3077

static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3087

context = dc_state_create_current_copy(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3102

if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3105

res = dc_state_remove_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3113

return dc_commit_streams(dc, &params);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3121

for (i = 0; i < dm->dc->caps.max_links; i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3200

dc_allow_idle_optimizations(adev->dm.dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3202

dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3207

res = amdgpu_dm_commit_zero_streams(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3235

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3237

if (dm->dc->caps.ips_support && adev->in_s0ix)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3238

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3240

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3376

update_planes_and_stream_adapter(dm->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3417

if (dm->dc->caps.ips_support) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3424

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3425

dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3449

link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3457

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3458

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3460

dc_resume(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3472

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3474

dc_enable_dmub_outbox(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3479

dc_exit_ips_for_hw_access(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3480

WARN_ON(!dc_commit_streams(dm->dc, &commit_params));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3503

dm_state->context = dc_state_create(dm->dc, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3510

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3512

dc_enable_dmub_outbox(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3516

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3517

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3520

dc_resume(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3561

dc_exit_ips_for_hw_access(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3921

struct dc *dc = aconnector->dc_link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3929

if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3930

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3967

if (reallow_idle && dc->caps.ips_support)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3968

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3979

struct dc *dc = aconnector->dc_link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4050

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

408

static inline bool update_planes_and_stream_adapter(struct dc *dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4111

struct dc *dc = aconnector->dc_link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4201

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

421

dc_post_update_surfaces_to_stream(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

423

return dc_update_planes_and_stream(dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4241

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4311

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4343

dc_interrupt_to_irq_source(dc, i + 1, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4373

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4409

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4444

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4473

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4503

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4538

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4582

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4614

dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4653

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4674

i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4684

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4718

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4733

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4737

dc_interrupt_to_irq_source(dc, i, 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4862

state->context = dc_state_create_current_copy(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5113

if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5114

dc_allow_idle_optimizations(dm->dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5142

if (dm->dc->caps.ips_support && reallow_idle)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5143

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5307

if (plane_id >= dm->dc->caps.max_streams)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5372

int max_overlay = dm->dc->caps.max_slave_planes;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5374

dm->display_indexes_num = dm->dc->caps.max_streams;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5380

link_cnt = dm->dc->caps.max_links;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5387

primary_planes = dm->dc->caps.max_streams;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5398

plane = &dm->dc->caps.planes[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5416

for (i = 0; i < dm->dc->caps.max_planes; ++i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5417

struct dc_plane_cap *plane = &dm->dc->caps.planes[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

542

dc_stream_adjust_vmin_vmax(adev->dm.dc, stream, adjust);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5439

for (i = 0; i < dm->dc->caps.max_streams; i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5530

link = dc_get_link_at_index(dm->dc, i);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5587

dc_exit_ips_for_hw_access(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

686

dc_stream_fc_disable_writeback(adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7019

dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7034

struct dc *dc = sink->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7039

dc_dsc_get_default_config_option(dc, &dsc_options);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7053

if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7054

dc->debug.dsc_min_slice_height_override,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7062

if (dc_dsc_compute_config(dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7077

if (dc_dsc_compute_config(dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7095

struct dc *dc = sink->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7102

dc_dsc_get_default_config_option(dc, &dsc_options);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7114

dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7120

if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7140

if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7826

static enum dc_status dm_validate_stream_and_context(struct dc *dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7836

dc_plane_state = dc_create_plane_state(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7840

dc_state = dc_state_create(dc, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7862

dc_result = dc_validate_stream(dc, stream);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7864

dc_result = dc_validate_plane(dc, dc_plane_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7867

dc_result = dc_state_add_stream(dc, dc_state, stream);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7870

dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7877

dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7924

dc_result = dc_validate_stream(adev->dm.dc, stream);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7933

dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

853

if (notify->link_index > adev->dm.dc->link_count) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

865

link = adev->dm.dc->links[link_index];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8705

const struct dc *dc = amdgpu_dm_connector->dc_link->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8712

if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8893

ddc_service->ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8898

ddc_service->ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8977

struct dc *dc = dm->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8978

struct dc_link *link = dc_get_link_at_index(dc, link_index);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9409

dc_stream_adjust_vmin_vmax(dm->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9622

adev->dm.dc->caps.color.dpp.gamma_corr)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

342

struct dc *dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

84

struct dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1260

if (dc_plane_state->ctx && dc_plane_state->ctx->dc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1261

color_caps = &dc_plane_state->ctx->dc->caps.color;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

823

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

518

if (!dc_stream_configure_crc(stream_state->ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

528

dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

533

dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

761

if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 0,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

858

dc_stream_configure_crc(stream_state->ctx->dc, stream_state,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

873

if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, i,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

882

dc_stream_configure_crc(stream_state->ctx->dc, stream_state,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

159

(dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

160

dm->dc->idle_optimizations_allowed &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

205

if (!idle_work->dm->dc->idle_optimizations_allowed) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

209

dc_allow_idle_optimizations(idle_work->dm->dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

222

dc_post_update_surfaces_to_stream(idle_work->dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

223

dc_allow_idle_optimizations(idle_work->dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

260

dc_allow_idle_optimizations(dm->dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

279

dc_post_update_surfaces_to_stream(dm->dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

280

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

310

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

324

if (dc->caps.ips_support &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

325

dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

330

if (dc_supports_vrr(dm->dc->ctx->dce_version)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

521

if (adev->dm.dc->caps.color.mpc.ogam_ram)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

658

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

708

if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

758

acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

759

acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

770

is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

779

dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01) ?

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

89

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1026

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1029

if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1031

(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1296

pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1572

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1674

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1758

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1858

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1942

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2042

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2122

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2219

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2297

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2351

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2420

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2489

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

262

struct dc *dc = (struct dc *)link->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2676

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2679

seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2680

seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2687

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3120

link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3133

link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3164

link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3179

*val = adev->dm.dc->config.allow_edp_hotplug_detection;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3192

adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

322

dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3247

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3275

if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3291

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3303

if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3333

dc_dmub_trace_event_control(adev->dm.dc, val);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

336

dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3435

struct dc *dc = (struct dc *)link->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3483

dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3498

dc_link_set_preferred_training_settings(dc, &prefer_link_settings,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3795

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3802

if (!dc->hwss.log_hw_state)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3805

dc->hwss.log_hw_state(dc, &log_ctx);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3834

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3840

if (dc->hwss.log_hw_state)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3841

dc->hwss.log_hw_state(dc, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

393

struct dc *dc = (struct dc *)link->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4017

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4018

bool mall_supported = dc->caps.mall_size_total;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4019

bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4023

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4028

if (dc->cap_funcs.get_subvp_en)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4029

subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4049

adev->dm.dc->debug.set_mst_en_for_sst = val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4058

*val = adev->dm.dc->debug.set_mst_en_for_sst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4073

adev->dm.dc->debug.ignore_cable_id = val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4082

*val = adev->dm.dc->debug.ignore_cable_id;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4097

adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4110

*val = adev->dm.dc->debug.visual_confirm;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4129

adev->dm.dc->debug.skip_detection_link_training = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4131

adev->dm.dc->debug.skip_detection_link_training = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4144

*val = adev->dm.dc->debug.skip_detection_link_training;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4164

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4169

int num_pipes = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4177

if (!dc->hwss.get_dcc_en_bits) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4182

dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4273

if (adev->dm.dc->caps.ips_support)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

456

dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

471

dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

613

struct dc *dc = (struct dc *)link->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

687

dc_link_set_drive_settings(dc, &link_lane_settings, link);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

47

link->dc->caps.i2c_speed_in_khz};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

60

link->dc->caps.i2c_speed_in_khz};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

736

struct cp_psp *cp_psp, struct dc *dc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

738

int max_caps = dc->caps.max_links;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

773

if (dc->ctx->dce_version == DCN_VERSION_3_1 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

774

dc->ctx->dce_version == DCN_VERSION_3_14 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

775

dc->ctx->dce_version == DCN_VERSION_3_15 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

776

dc->ctx->dce_version == DCN_VERSION_3_16 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

777

dc->ctx->dce_version == DCN_VERSION_3_2 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

778

dc->ctx->dce_version == DCN_VERSION_3_21 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

779

dc->ctx->dce_version == DCN_VERSION_3_5 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

780

dc->ctx->dce_version == DCN_VERSION_3_51 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

781

dc->ctx->dce_version == DCN_VERSION_3_6 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

782

dc->ctx->dce_version == DCN_VERSION_4_01)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

785

config->ddc.handle = dc_get_link_at_index(dc, i);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

792

config->debug.lc_enable_sw_fallback = dc->debug.hdcp_lc_enable_sw_fallback;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

793

if (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

88

struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1179

ret = dc_interrupt_set(ctx->dc, irq_source, enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1222

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1226

struct dc_state *dc_state = ctx->dc->current_state;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1227

struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1333

ctx->dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1334

ctx->dc->clk_mgr,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

498

dc_interrupt_set(adev->dm.dc, src, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

532

dc_interrupt_set(adev->dm.dc, src, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

556

dc_interrupt_set(adev->dm.dc, src, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

656

adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

660

dc_interrupt_ack(adev->dm.dc, src);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

698

dc_interrupt_set(adev->dm.dc, src, st);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

711

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

729

if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

730

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

732

dc_interrupt_set(adev->dm.dc, irq_source, st);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

786

dc_interrupt_set(adev->dm.dc, irq_source, st);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

812

dc_interrupt_set(adev->dm.dc, irq_source, st);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

876

dc_interrupt_set(adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

899

if (!dc_interrupt_set(adev->dm.dc, i, false))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

937

dc_interrupt_set(adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

944

dc_interrupt_set(adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

987

dc_interrupt_set(adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

994

dc_interrupt_set(adev->dm.dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1248

stream->sink->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1249

stream->sink->ctx->dc->debug.dsc_min_slice_height_override,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1361

const struct dc *dc = dc_link->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1443

__func__, dc->current_state->stream_count);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1448

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1449

stream = dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1500

res_pool = stream->ctx->dc->res_pool;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1520

res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1542

if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1787

is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1788

stream->sink->ctx->dc->debug.dsc_min_slice_height_override,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1946

dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1948

if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

305

if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

921

dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

926

params[i].sink->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

974

dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

979

param.sink->ctx->dc->res_pool->dscs[0],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1050

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1052

struct dc_plane_cap *plane_cap = &dc->caps.planes[0];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1235

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1262

if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1390

adev->dm.dc->caps.color.dpp.gamma_corr)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1615

struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1637

if (dm->dc->caps.color.mpc.gamut_remap)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1641

if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1816

unsigned int primary_zpos = dm->dc->caps.max_slave_planes;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

270

struct dc *dc = adev->dm.dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

284

if (!dc->cap_funcs.get_dcc_compression_cap)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

297

if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

103

struct dc *dc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

110

dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

118

mod_power_only_edp(dc->current_state, stream);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

123

if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

175

dc_stream_set_static_screen_params(link->ctx->dc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

189

if (link->ctx->dc->caps.ips_support)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

190

dc_allow_idle_optimizations(link->ctx->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

217

return dc_set_psr_allow_active(dm->dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

232

for (i = 0; i < dm->dc->current_state->stream_count ; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

234

struct dc_stream_state *stream = dm->dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

35

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

37

if (!dc->caps.dmcub_support)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

40

if (dc->ctx->dce_version < DCN_VERSION_3_1)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

108

link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

164

link->dc->link_srv->edp_setup_replay(link, stream);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

165

link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

167

link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

192

link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

208

return dc_set_replay_allow_active(dm->dc, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

83

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

98

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

99

!dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

193

struct dc *dc = dm->dc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

194

struct dc_link *link = dc_get_link_at_index(dc, link_index);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3055

if (ctx->dc->config.multi_mon_pp_mclk_switch)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3074

if (ctx->dc->debug.bandwidth_calcs_trace) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3124

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3154

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3182

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3210

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3245

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3275

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3303

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3331

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3365

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3394

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3421

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3448

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3496

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3524

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3552

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3580

if (ctx->dc->caps.max_slave_planes) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1424

if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3104

else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3115

if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3116

info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

1059

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

1060

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

180

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

181

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

196

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

197

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

230

if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) && (bp->base.ctx->dc->ctx->dce_version <= DCN_VERSION_2_0))

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

296

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

297

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

327

static struct dc_link *get_link_by_phy_id(struct dc *p_dc, uint32_t phy_id)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

378

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

379

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

381

struct dc_link *link = get_link_by_phy_id(bp->base.ctx->dc, dig_v1_7.phyid);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

425

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

426

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

553

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

554

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

569

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

570

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

862

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

863

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

880

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

881

bp->base.ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

103

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

104

if (dc->hwss.exit_optimized_pwr_state)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

105

dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

115

dc->link_srv->edp_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

116

dc->link_srv->edp_set_replay_allow_active(edp_link, &allow_active, false, false, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

122

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

129

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

135

dc->link_srv->edp_set_psr_allow_active(edp_link,

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

137

dc->link_srv->edp_set_replay_allow_active(edp_link,

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

142

if (dc->hwss.optimize_pwr_state)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

143

dc->hwss.optimize_pwr_state(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

54

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

70

if (!stream->dpms_off || dc->is_switch_in_progress_dest || (stream_status && stream_status->plane_count))

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

78

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

96

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

237

struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

279

struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

382

if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

389

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

396

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

397

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

422

dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

123

struct dc *dc = context->clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

128

pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

130

pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

196

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

202

if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

221

if (dc->bw_vbios && (dc->ctx->asic_id.chip_family == FAMILY_AI) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

222

ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

225

div64_s64(dc->bw_vbios->high_yclk.value,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

233

dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

251

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

252

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

279

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

67

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

76

if (dc->sclk_lvls.num_levels == 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

79

for (i = 0; i < dc->sclk_lvls.num_levels; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

80

if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

81

return dc->sclk_lvls.clocks_in_khz[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

89

return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

39

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

128

struct dc *dc = clk_mgr->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

129

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

215

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

75

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

76

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

119

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

149

if (dce121_xgmi_enabled(ctx->dc->hwseq))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

105

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

106

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

131

dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

98

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

163

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

164

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

192

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

193

struct dc_debug_options *debug = &dc->debug;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

204

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

209

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

274

ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

318

struct dc_debug_options *debug = &ctx->dc->debug;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

87

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

128

struct dc *dc = clk_mgr->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

129

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

110

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

152

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

155

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

183

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

185

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

222

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

229

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

234

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

238

dc->debug.force_clock_mode & 0x1) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

246

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

247

if (dc->res_pool->pp_smu)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

248

pp_smu = &dc->res_pool->pp_smu->nv_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

258

if (dc->debug.force_min_dcfclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

259

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

260

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

281

total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

321

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

102

dc->debug.force_clock_mode & 0x1) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

119

if (dc->debug.force_min_dcfclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

120

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

121

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

133

total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

157

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

184

struct dc_debug_options *debug = &ctx->dc->debug;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

90

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

98

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

113

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

119

dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

137

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

143

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

145

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

152

if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

156

display_count = rn_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

514

struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

55

static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

70

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

706

struct dc_debug_options *debug = &ctx->dc->debug;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

71

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

756

if (ctx->dc->config.is_single_rank_dimm)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

778

if (ctx->dc->config.is_asymmetric_memory)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

90

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

91

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

95

display_count = rn_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

146

struct dc *dc = clk_mgr->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

147

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

199

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

206

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

211

if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

215

(dc->debug.force_clock_mode & 0x1)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

223

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

231

if (dc->debug.force_min_dcfclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

232

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

233

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

253

if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

254

if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) !=

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

255

(clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

265

if (dc->clk_mgr->dc_mode_softmax_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

266

new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

268

dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

301

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

425

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

426

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

101

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

107

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

118

display_count = vg_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

142

if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

148

new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

63

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

79

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

80

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

116

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

119

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

120

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

127

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

141

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

147

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

168

display_count = dcn31_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

243

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

257

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

637

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

638

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

641

display_count = dcn31_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

745

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

77

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

98

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

99

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

193

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

211

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

242

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

327

if (!clk_mgr->base.ctx->dc->debug.enable_z9_disable_interface &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

1031

if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

174

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

195

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

196

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

214

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

217

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

220

: &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

229

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

280

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

286

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

289

display_count = dcn314_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

372

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

373

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

392

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

406

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

987

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

212

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

230

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

261

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

102

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

105

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

106

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

117

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

132

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

138

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

141

display_count = dcn315_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

211

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

212

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

230

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

244

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

58

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

672

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

74

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

75

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

206

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

224

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

255

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

105

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

108

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

111

: &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

121

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

142

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

148

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

163

display_count = dcn316_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

219

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

220

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

238

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

252

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

657

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

70

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

86

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

87

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

181

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

199

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

230

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1064

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1065

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1177

if (ctx->dc->debug.disable_dtb_ref_clk_switch) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1195

if (ctx->dc->debug.disable_dtb_ref_clk_switch &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

203

if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

236

if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

239

< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

241

= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

247

if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

250

< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

252

= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

274

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

320

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

357

struct dc *dc = clk_mgr->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

371

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

374

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

414

if (dc->debug.override_dispclk_programming) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

425

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

427

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

461

if (dc->debug.override_dispclk_programming) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

627

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

633

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

640

(dc->debug.force_clock_mode & 0x1)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

652

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

666

!dc->work_arounds.clock_update_disable_mask.fclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

676

if (dc->debug.force_min_dcfclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

677

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

678

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

681

!dc->work_arounds.clock_update_disable_mask.dcfclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

687

!dc->work_arounds.clock_update_disable_mask.dcfclk_ds) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

707

!dc->work_arounds.clock_update_disable_mask.uclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

712

if (dc->clk_mgr->dc_mode_softmax_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

717

if (dc->debug.disable_dc_mode_overwrite) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

718

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

719

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

722

dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

724

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

740

!dc->work_arounds.clock_update_disable_mask.fclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

747

!dc->work_arounds.clock_update_disable_mask.uclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

755

!dc->work_arounds.clock_update_disable_mask.uclk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

756

if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

758

max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

802

if (!dc->debug.disable_dtb_ref_clk_switch &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

811

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

843

if (dc->config.enable_auto_dpm_test_logs) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1195

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1196

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1199

display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1457

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1512

if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1528

if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1534

ctx->dc->debug.ignore_pg = false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1535

ctx->dc->debug.disable_dpp_power_gate = false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1536

ctx->dc->debug.disable_hubp_power_gate = false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1537

ctx->dc->debug.disable_dsc_power_gate = false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1540

if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1543

ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1546

ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

157

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

173

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

174

const struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

192

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

195

if (dc->ctx->dce_environment == DCE_ENV_DIAG)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

198

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

199

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

205

: &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

214

if (!dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

233

has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

234

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

240

!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

246

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

262

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

288

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

316

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

317

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

326

const struct dc *dc_struct = link->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

384

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

391

if (dc->work_arounds.skip_clock_update)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

394

display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

413

if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

455

if (dc->debug.force_min_dcfclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

456

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

457

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

488

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

489

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

500

if (!dc->debug.disable_dtb_ref_clk_switch &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

519

if (dc->debug.notify_dpia_hr_bw)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

532

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

650

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

129

if (clk_mgr->base.ctx->dc->debug.disable_timeout)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

280

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1085

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1086

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1097

(dc->debug.force_clock_mode & 0x1)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1118

if (!dc->debug.disable_dtb_ref_clk_switch &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1157

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1222

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1244

if (dc->config.enable_auto_dpm_test_logs)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1330

const struct dc *dc = clk_mgr->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1331

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1364

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1371

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1424

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1425

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

150

is_df_throttle_opt_enabled = !clk_mgr->base.ctx->dc->debug.force_subvp_df_throttle;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1588

if (ctx->dc->debug.disable_dtb_ref_clk_switch &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

201

if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

262

if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

291

if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

294

< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

296

= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

299

if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

302

< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

304

= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

542

use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

550

dccg->ctx->dc->link_srv->dp_get_encoding_format(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

562

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

620

struct dc *dc = clk_mgr->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

630

if (dc->debug.override_dispclk_programming) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

772

struct dc *dc = clk_mgr_base->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

787

int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

802

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

841

if (dc->debug.force_min_dcfclk_mhz > 0)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

842

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

843

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

918

if (dc->clk_mgr->dc_mode_softmax_enabled) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1002

dc_ctx->dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1020

dc->dml.logger = dc_ctx->logger;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1031

dc->ctx = dc_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1033

dc->link_srv = link_create_link_service();

sys/dev/pci/drm/amd/display/dc/core/dc.c

1034

if (!dc->link_srv)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1040

static bool dc_construct(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1049

dc->config = init_params->flags;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1052

dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1053

if (!dc->vm_helper) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1058

memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1066

dc->bw_dceip = dc_dceip;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1074

dc->bw_vbios = dc_vbios;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1081

dc->dcn_soc = dcn_soc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1089

dc->dcn_ip = dcn_ip;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1092

dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1094

dc->dml2_options.bb_from_dmub = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1096

if (!dc_construct_ctx(dc, init_params)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1101

dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1126

dc->vendor_signature = init_params->vendor_signature;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1139

dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1140

if (!dc->res_pool)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1144

if (dc->caps.i2c_speed_in_khz_hdcp == 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1145

dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1146

if (dc->caps.max_optimizable_video_width == 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1147

dc->caps.max_optimizable_video_width = 5120;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1148

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1149

if (!dc->clk_mgr)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1152

dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1154

if (dc->res_pool->funcs->update_bw_bounding_box) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1156

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1159

dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1160

if (!dc->soc_and_ip_translator)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1164

if (!create_links(dc, init_params->num_virtual_links))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1170

if (!create_link_encoders(dc))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1177

dc->current_state = dc_state_create(dc, NULL);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1179

if (!dc->current_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1191

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1201

static void apply_ctx_interdependent_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1209

if (dc->hwss.interdependent_update_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1210

dc->hwss.interdependent_update_lock(dc, context, lock);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1212

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1214

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1220

dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1226

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1228

if (dc->debug.visual_confirm & VISUAL_CONFIRM_EXPLICIT) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1234

if (dc->ctx->dce_version >= DCN_VERSION_1_0) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1237

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1239

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1241

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1243

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1245

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_DCC)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1246

get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1248

if (dc->ctx->dce_version < DCN_VERSION_2_0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1250

dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1252

if (dc->ctx->dce_version >= DCN_VERSION_2_0) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1253

if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1255

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1257

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1259

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1260

get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1261

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_VABC)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1268

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1280

switch (dc->debug.visual_confirm) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1288

dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1289

memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1302

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1312

static void disable_dangling_plane(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1315

struct dc_state *dangling_context = dc_state_create_current_copy(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1323

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1325

dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1330

(dc->current_state->res_ctx.pipe_ctx[i].top_pipe))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1332

dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1335

dc->current_state->res_ctx.pipe_ctx[i].top_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1344

dc->current_state->stream_count != context->stream_count)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1347

if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1348

!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1351

old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1359

bool is_phantom = dc_state_get_stream_subvp_type(dc->current_state, old_stream) == SUBVP_PHANTOM;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1360

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1370

if (dc->hwseq->funcs.blank_pixel_data)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1371

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1377

dc_state_rem_all_phantom_planes_for_stream(dc, old_stream, dangling_context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1379

dc_state_rem_all_planes_for_stream(dc, old_stream, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1380

disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1383

if (!dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1384

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1385

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1388

if (dc->hwss.apply_ctx_for_surface) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1389

apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1390

dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1391

apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1392

dc->hwss.post_unlock_program_front_end(dc, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1395

if (dc->res_pool->funcs->prepare_mcache_programming)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1396

dc->res_pool->funcs->prepare_mcache_programming(dc, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1397

if (dc->hwss.program_front_end_for_ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1398

dc->hwss.interdependent_update_lock(dc, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1399

dc->hwss.program_front_end_for_ctx(dc, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1400

dc->hwss.interdependent_update_lock(dc, dc->current_state, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1401

dc->hwss.post_unlock_program_front_end(dc, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1415

current_ctx = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1416

dc->current_state = dangling_context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1421

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1427

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1455

for (j = 0; j < dc->res_pool->stream_enc_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1456

if (dc->res_pool->stream_enc[j]->id == enc_inst) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1457

tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1458

dc->res_pool->stream_enc[j]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1463

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1464

dc->res_pool->dp_clock_source,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1472

dc->link_srv->set_dpms_off(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1483

struct dc *dc_create(const struct dc_init_data *init_params)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1485

struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1488

if (!dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1492

dc->caps.linear_pitch_alignment = 64;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1493

if (!dc_construct_ctx(dc, init_params))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1496

if (!dc_construct(dc, init_params))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1499

full_pipe_count = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1500

if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1502

dc->caps.max_streams = min(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1504

dc->res_pool->stream_enc_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1506

dc->caps.max_links = dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1507

dc->caps.max_audios = dc->res_pool->audio_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1508

dc->caps.linear_pitch_alignment = 64;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1510

dc->caps.max_dp_protocol_version = DP_VERSION_1_4;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1512

dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1514

if (dc->res_pool->dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1515

dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1518

dc->dcn_reg_offsets = init_params->dcn_reg_offsets;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1519

dc->nbio_reg_offsets = init_params->nbio_reg_offsets;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1520

dc->clk_reg_offsets = init_params->clk_reg_offsets;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1523

dc->versions.dc_ver = DC_VER;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1525

dc->build_id = DC_BUILD_ID;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1529

return dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1532

dc_destruct(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1533

kfree(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1537

static void detect_edp_presence(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1545

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1551

if (dc->config.edp_not_connected) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1560

void dc_hardware_init(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1563

detect_edp_presence(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1564

if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1565

dc->hwss.init_hw(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1566

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1569

void dc_init_callbacks(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

157

static void destroy_links(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1572

dc->ctx->cp_psp = init_params->cp_psp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1575

void dc_deinit_callbacks(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1577

memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1580

void dc_destroy(struct dc **dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1582

dc_destruct(*dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1583

kfree(*dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1584

*dc = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1588

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1592

int pipe_count = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1606

dc->hwss.enable_per_frame_crtc_position_reset(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1607

dc, multisync_count, multisync_pipes);

sys/dev/pci/drm/amd/display/dc/core/dc.c

161

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1612

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1618

int pipe_count = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

162

if (NULL != dc->links[i])

sys/dev/pci/drm/amd/display/dc/core/dc.c

163

dc->link_srv->destroy_link(&dc->links[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1648

dc->hwss.enable_vblanks_synchronization &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1704

if (dc->config.use_pipe_ctx_sync_logic) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1736

dc->hwss.enable_timing_synchronization(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1737

dc, ctx, group_index, group_size, pipe_set);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1740

dc->hwss.enable_vblanks_synchronization(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1741

dc, group_index, group_size, pipe_set);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1749

static bool streams_changed(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1755

if (stream_count != dc->current_state->stream_count)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1758

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1759

if (dc->current_state->streams[i] != streams[i])

sys/dev/pci/drm/amd/display/dc/core/dc.c

1768

bool dc_validate_boot_timing(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1785

if (dc->debug.force_odm_combine) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1803

for (i = 0; i < dc->res_pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1804

if (dc->res_pool->stream_enc[i]->id == enc_inst) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1806

se = dc->res_pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1808

tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1809

dc->res_pool->stream_enc[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1815

if (i == dc->res_pool->stream_enc_count) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1820

if (tg_inst >= dc->res_pool->timing_generator_count) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1830

tg = dc->res_pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1913

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1914

dc->res_pool->dp_clock_source,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1928

if (pixels_per_cycle != 1 && !dc->debug.enable_dp_dig_pixel_rate_div_policy) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

194

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1978

if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

199

struct dc_bios *bios = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2003

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

201

dc->link_count = 0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2011

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2017

context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2018

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2023

dc->hwss.setup_stereo)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2024

dc->hwss.setup_stereo(pipe, dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2029

void dc_trigger_sync(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2031

if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2032

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2034

enable_timing_multisync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2035

program_timing_sync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2039

static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2044

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2052

void dc_z10_restore(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2054

if (dc->hwss.z10_restore)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2055

dc->hwss.z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2058

void dc_z10_save_init(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2060

if (dc->hwss.z10_save_init)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2061

dc->hwss.z10_save_init(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2072

static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2078

if (!dc->config.set_pipe_unlock_order)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2081

memset(dc->scratch.pipes_to_unlock_first, 0, sizeof(dc->scratch.pipes_to_unlock_first));

sys/dev/pci/drm/amd/display/dc/core/dc.c

2082

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2093

resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2094

dc->scratch.pipes_to_unlock_first[i] = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2110

static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2112

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2120

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2121

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2123

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2124

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2127

subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2136

disable_vbios_mode_if_required(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2137

dc->hwss.enable_accelerated_mode(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2140

if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2141

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2146

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2154

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2159

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2160

dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2161

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2162

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2164

if (dc->hwss.update_dsc_pg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2165

dc->hwss.update_dsc_pg(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2167

disable_dangling_plane(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2171

if (dc->hwss.apply_ctx_for_surface) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2175

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2176

dc->hwss.apply_ctx_for_surface(

sys/dev/pci/drm/amd/display/dc/core/dc.c

2177

dc, context->streams[i],

sys/dev/pci/drm/amd/display/dc/core/dc.c

2180

apply_ctx_interdependent_lock(dc, context, context->streams[i], false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2181

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2186

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2188

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2191

result = dc->hwss.apply_ctx_to_hw(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2195

dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2199

dc_trigger_sync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2209

determine_pipe_unlock_order(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2211

if (dc->res_pool->funcs->prepare_mcache_programming)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2212

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2213

if (dc->hwss.program_front_end_for_ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2214

dc->hwss.interdependent_update_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2215

dc->hwss.program_front_end_for_ctx(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2217

if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2218

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2220

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2224

dc->hwss.interdependent_update_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2225

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2228

if (dc->hwss.commit_subvp_config)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2229

dc->hwss.commit_subvp_config(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2230

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2231

dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2232

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2233

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2241

if (dc->hwss.apply_ctx_for_surface) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2242

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2243

dc->hwss.apply_ctx_for_surface(

sys/dev/pci/drm/amd/display/dc/core/dc.c

2244

dc, context->streams[i],

sys/dev/pci/drm/amd/display/dc/core/dc.c

2247

apply_ctx_interdependent_lock(dc, context, context->streams[i], false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2248

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2261

dc->hwss.setup_stereo)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2262

dc->hwss.setup_stereo(pipe, dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2274

dc_enable_stereo(dc, context, dc_streams, context->stream_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2279

hwss_wait_for_no_pipes_pending(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2284

hwss_wait_for_odm_update_pending_complete(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2286

dc->hwss.optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2290

dc_trigger_sync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2293

if (dc->hwss.update_dsc_pg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2294

dc->hwss.update_dsc_pg(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2296

if (dc->ctx->dce_version >= DCE_VERSION_MAX)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2301

context->stream_mask = get_stream_mask(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2303

if (context->stream_mask != dc->current_state->stream_mask)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2304

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);

sys/dev/pci/drm/amd/display/dc/core/dc.c

231

for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2314

old_state = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2315

dc->current_state = context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2319

dc_state_retain(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2324

static bool commit_minimal_transition_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2339

enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2351

if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2354

if (!streams_changed(dc, params->streams, params->stream_count) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2355

dc->current_state->power_source == params->power_source)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2358

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2369

res = dc_validate_stream(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2375

dc_stream_log(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

239

DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2390

if (params->stream_count > dc->current_state->stream_count &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2391

dc->current_state->stream_count == 1) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2392

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2393

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2400

res = commit_minimal_transition_state(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2402

context = dc_state_create_current_copy(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2408

res = dc_validate_with_context(dc, set, params->stream_count, context, DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/core/dc.c

241

link_init_params.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2413

if (res == DC_OK && dc->res_pool->funcs->link_encs_assign && !dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2414

dc->res_pool->funcs->link_encs_assign(

sys/dev/pci/drm/amd/display/dc/core/dc.c

2415

dc, context, context->streams, context->stream_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2425

if (dc->hwss.is_pipe_topology_transition_seamless &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2426

!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2427

res = commit_minimal_transition_state(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2434

res = dc_commit_state_no_check(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

244

link_init_params.link_index = dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2447

if (dc->hwss.is_abm_supported)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2448

status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, params->streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

245

link_init_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

246

link = dc->link_srv->create_link(&link_init_params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2466

struct dc *dc, bool acquire,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2474

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2475

struct resource_context *res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

249

dc->links[dc->link_count] = link;

sys/dev/pci/drm/amd/display/dc/core/dc.c

250

link->dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2501

static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

251

++dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2515

dc->hwss.update_pending_status(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2529

static void process_deferred_updates(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2533

if (dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2534

ASSERT(dc->dcn_ip->max_num_dpp);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2535

for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2536

if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2537

dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2541

void dc_post_update_surfaces_to_stream(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2544

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2546

if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2549

post_surface_trace(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2556

if (dc->ctx->dce_version < DCE_VERSION_MAX)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2561

if (is_flip_pending_in_pipes(dc, context))

sys/dev/pci/drm/amd/display/dc/core/dc.c

2564

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2568

dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2571

process_deferred_updates(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2573

dc->hwss.optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2575

if (dc->hwss.update_dsc_pg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2576

dc->hwss.update_dsc_pg(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2579

dc->optimized_required = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

258

dc->lowest_dpia_link_index = MAX_LINKS;

sys/dev/pci/drm/amd/display/dc/core/dc.c

259

for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

263

link_init_params.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2648

static enum surface_update_type get_plane_info_update_type(const struct dc *dc, const struct dc_surface_update *u)

sys/dev/pci/drm/amd/display/dc/core/dc.c

265

link_init_params.link_index = dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

266

link_init_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

269

link = dc->link_srv->create_link(&link_init_params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

271

if (dc->lowest_dpia_link_index > dc->link_count)

sys/dev/pci/drm/amd/display/dc/core/dc.c

272

dc->lowest_dpia_link_index = dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2727

if (!dc->debug.skip_full_updated_if_possible) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

274

dc->links[dc->link_count] = link;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2741

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

275

link->dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

276

++dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2771

if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2798

static enum surface_update_type det_surface_update(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2801

const struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2813

type = get_plane_info_update_type(dc, u);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2816

type = get_scaling_info_update_type(dc, u);

sys/dev/pci/drm/amd/display/dc/core/dc.c

289

link->link_index = dc->link_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2893

if (dc->debug.enable_legacy_fast_update &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

290

dc->links[dc->link_count] = link;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2907

static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count)

sys/dev/pci/drm/amd/display/dc/core/dc.c

291

dc->link_count++;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2928

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

293

link->ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2937

if (dc->idle_optimizations_allowed || dc_can_clear_cursor_limit(dc))

sys/dev/pci/drm/amd/display/dc/core/dc.c

294

link->dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2960

if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3004

if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3010

det_surface_update(dc, &updates[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3024

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3038

type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3051

if (dc->clk_mgr->funcs->are_clock_states_equal) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3052

if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3053

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3055

} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3056

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

309

enc_init.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

320

dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3222

static void copy_stream_update_to_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3227

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

332

static bool create_link_encoders(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3338

struct dc_state *dsc_validate_context = dc_state_create_copy(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3343

if (dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

335

unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;

sys/dev/pci/drm/amd/display/dc/core/dc.c

336

unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3408

static void update_seamless_boot_flags(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3424

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3451

static bool update_planes_and_stream_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3462

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3473

context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3475

dc, srf_updates, surface_count, stream_update, stream_status);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3480

force_immediate_gsl_plane_flip(dc, srf_updates, surface_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3482

backup_planes_and_stream_state(&dc->scratch.current_state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3485

copy_stream_update_to_stream(dc, context, stream, stream_update);

sys/dev/pci/drm/amd/display/dc/core/dc.c

349

if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3508

update_surface_trace(dc, srf_updates, surface_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

351

struct link_encoder *link_enc = dc->res_pool->link_encoders[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3520

context = dc_state_create_copy(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3529

dc_state_remove_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

353

if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3530

dc_state_release_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3533

if (!dc_state_rem_all_planes_for_stream(dc, stream, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

354

link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3540

if (!dc_state_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3554

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3566

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

357

dc->res_pool->link_encoders[i] = link_enc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3571

update_seamless_boot_flags(dc, context, surface_count, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3576

backup_planes_and_stream_state(&dc->scratch.new_state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

358

dc->res_pool->dig_link_enc_count++;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3587

static void commit_planes_do_stream_update(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3596

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3601

if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3602

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3613

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3616

dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/core/dc.c

3623

dc->hwss.set_dmdata_attributes &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

3625

dc->hwss.set_dmdata_attributes(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3628

dc_stream_set_gamut_remap(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3631

dc_stream_program_csc_matrix(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3649

program_cursor_attributes(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3652

program_cursor_position(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3659

dc->link_srv->update_dsc_config(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3663

dc->link_srv->increase_mst_payload(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3666

dc->link_srv->reduce_mst_payload(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3684

dc->link_srv->dp_set_test_pattern(stream->link,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3695

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3697

if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3700

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3704

dc->hwss.prepare_bandwidth(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3705

dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3713

dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3726

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

373

static void destroy_link_encoders(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3737

static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3753

void dc_dmub_update_dirty_rect(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3764

if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3767

if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/core/dc.c

379

if (!dc->res_pool)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3791

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3801

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3807

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

382

num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3820

if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3823

if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/core/dc.c

383

num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3846

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3889

static void build_dmub_cmd_list(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3899

build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3902

static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3911

dc_dmub_update_dirty_rect(dc, surface_count, stream,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3918

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3929

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

393

struct link_encoder *link_enc = dc->res_pool->link_encoders[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3934

dc_dmub_srv_fams2_passthrough_flip(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3941

static void commit_planes_for_stream_fast(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3956

determine_pipe_unlock_order(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3958

if (dc->debug.fams2_config.bits.enable &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

3959

dc->debug.fams2_config.bits.enable_offload_flip &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

3960

dc_state_is_fams2_in_use(dc, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

397

dc->res_pool->link_encoders[i] = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3978

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

398

dc->res_pool->dig_link_enc_count--;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3980

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3989

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3993

if (!dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3994

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3996

if (dc->debug.visual_confirm)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3997

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4004

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4014

dc->hwss.program_triplebuffer != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4015

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4025

commit_plane_for_stream_offload_fams2_flip(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4031

build_dmub_cmd_list(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4038

hwss_build_fast_sequence(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4046

hwss_execute_sequence(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4060

static void commit_planes_for_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4076

determine_pipe_unlock_order(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4081

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4083

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4084

if (update_type == UPDATE_TYPE_FULL && dc->optimized_required)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4085

hwss_process_outstanding_hw_updates(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4087

if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4088

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4090

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4094

if (!dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4095

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4097

if (dc->debug.visual_confirm)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4098

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4103

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4106

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4108

if (dc->hwss.update_dsc_pg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4109

dc->hwss.update_dsc_pg(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4111

context_clock_trace(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4115

hwss_wait_for_outstanding_hw_updates(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4122

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4123

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4126

subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4131

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

414

static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4159

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

416

if (!dc || !stream || !adjust)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4168

if (dc->hwss.wait_for_dcc_meta_propagation) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4169

dc->hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4172

if (dc->hwseq->funcs.wait_for_pipe_update_if_needed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4173

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4175

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4176

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4177

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4179

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4180

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4182

dc->hwss.interdependent_update_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4184

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4185

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4187

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4188

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

419

if (!dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4194

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4197

dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4201

commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4208

if (dc->hwss.apply_ctx_for_surface)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4209

dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4210

if (dc->hwss.program_front_end_for_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4211

dc->hwss.program_front_end_for_ctx(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4213

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4214

dc->hwss.interdependent_update_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4216

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4218

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4221

if (dc->hwss.commit_subvp_config)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4222

dc->hwss.commit_subvp_config(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4227

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4228

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4231

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4232

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4238

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4241

if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

4242

dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4248

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

425

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4258

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4266

dc->hwss.program_triplebuffer != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4267

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

428

if (dc->hwss.set_long_vtotal)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4280

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

429

dc->hwss.set_long_vtotal(&pipe, 1, adjust->v_total_min, adjust->v_total_max);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4298

if (dc->hwss.apply_ctx_for_surface && stream_status)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4299

dc->hwss.apply_ctx_for_surface(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4300

dc, pipe_ctx->stream, stream_status->plane_count, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4304

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4315

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4317

dc->hwss.program_triplebuffer(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4318

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4322

if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4323

dc->hwss.program_front_end_for_ctx(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4326

if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe && update_type == UPDATE_TYPE_FULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4327

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4330

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4334

if (dc->debug.validate_dml_output) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4335

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4341

cur_pipe->plane_res.hubp, dc->ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4351

if (dc->hwss.set_flip_control_gsl)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4355

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4365

dc->hwss.set_flip_control_gsl(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4374

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4388

dc->hwss.trigger_3dlut_dma_load)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4389

dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4392

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4394

dc->hwss.program_triplebuffer(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4395

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4398

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4403

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4404

dc->hwss.interdependent_update_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4406

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4429

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4443

if (dc->hwss.enable_phantom_streams)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4444

dc->hwss.enable_phantom_streams(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4449

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4457

if (dc->hwss.disable_phantom_streams)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4458

dc->hwss.disable_phantom_streams(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4462

if (dc->hwss.commit_subvp_config)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4463

dc->hwss.commit_subvp_config(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4467

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4468

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4469

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4470

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4471

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4473

if (dc->hwss.subvp_pipe_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4474

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4475

if (dc->hwss.fams2_global_control_lock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4476

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4480

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4496

current_stream_mask = get_stream_mask(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4499

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);

sys/dev/pci/drm/amd/display/dc/core/dc.c

452

bool dc_stream_adjust_vmin_vmax(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4523

static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4530

struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4538

dc->current_state->stream_count > 0 &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4539

dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4552

dc->current_state->stream_count == 1 &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4553

dc->debug.enable_single_display_2to1_odm_policy) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4565

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4566

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4568

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4603

static void backup_and_set_minimal_pipe_split_policy(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4609

if (!dc->config.is_vmin_only_asic) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4610

policy->mpc_policy = dc->debug.pipe_split_policy;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4611

dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4613

policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4614

dc->debug.enable_single_display_2to1_odm_policy = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4615

policy->subvp_policy = dc->debug.force_disable_subvp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4616

dc->debug.force_disable_subvp = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

462

if (dc->ctx->dce_version > DCE_VERSION_MAX) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4624

static void restore_minimal_pipe_split_policy(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

463

if (dc->optimized_required &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4630

if (!dc->config.is_vmin_only_asic)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4631

dc->debug.pipe_split_policy = policy->mpc_policy;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4632

dc->debug.enable_single_display_2to1_odm_policy =

sys/dev/pci/drm/amd/display/dc/core/dc.c

4634

dc->debug.force_disable_subvp = policy->subvp_policy;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4639

static void release_minimal_transition_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4644

restore_minimal_pipe_split_policy(dc, base_context, policy);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4662

static struct dc_state *create_minimal_transition_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4671

backup_and_set_minimal_pipe_split_policy(dc, base_context, policy);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4673

if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4682

release_minimal_transition_state(dc, minimal_transition_context, base_context, policy);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4690

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4695

return dc->hwss.is_pipe_topology_transition_seamless(dc, initial_state,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4697

dc->hwss.is_pipe_topology_transition_seamless(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4701

static void swap_and_release_current_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4706

struct dc_state *old = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

471

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4716

dc->current_state = new_context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4720

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4744

static bool commit_minimal_transition_based_on_new_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4753

create_minimal_transition_state(dc, new_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4758

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4759

dc->current_state,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4763

commit_planes_for_stream(dc, srf_updates,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4767

dc, intermediate_context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4768

dc_state_retain(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4772

dc, intermediate_context, new_context, &policy);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4777

static bool commit_minimal_transition_based_on_current_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4783

struct dc_state *old_current_state = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

479

if (dc->caps.max_v_total != 0 &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4798

restore_planes_and_stream_state(&dc->scratch.current_state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

480

(adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4800

intermediate_context = create_minimal_transition_state(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4805

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4806

dc->current_state,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4812

commit_planes_for_stream(dc, srf_updates,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4816

dc, intermediate_context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4817

dc_state_retain(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4820

release_minimal_transition_state(dc, intermediate_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4828

restore_planes_and_stream_state(&dc->scratch.new_state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

483

return set_long_vtotal(dc, stream, adjust);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4851

static bool commit_minimal_transition_state_in_dc_update(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4858

dc, new_context, stream, srf_updates,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4861

success = commit_minimal_transition_based_on_current_context(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4886

static bool commit_minimal_transition_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

489

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4898

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4908

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4909

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4911

if (pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

492

dc->hwss.set_drr(&pipe,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4920

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4937

if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4941

dc->current_state == transition_base_context ? "current" : "new",

sys/dev/pci/drm/amd/display/dc/core/dc.c

4944

dc->debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC in Use" :

sys/dev/pci/drm/amd/display/dc/core/dc.c

4948

transition_context = create_minimal_transition_state(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4951

ret = dc_commit_state_no_check(dc, transition_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4952

release_minimal_transition_state(dc, transition_context, transition_base_context, &policy);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4963

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4964

for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4965

dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5038

static bool full_update_required(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5047

const struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5107

if (dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5110

if (dc_can_clear_cursor_limit(dc))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5116

static bool fast_update_only(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5124

&& !full_update_required(dc, srf_updates, surface_count, stream_update, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5127

static bool update_planes_and_stream_v2(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5145

is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5148

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

515

bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5156

!commit_minimal_transition_state(dc, dc->current_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5160

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5171

if (!commit_minimal_transition_state(dc, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5178

if (dc->hwss.is_pipe_topology_transition_seamless &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5179

!dc->hwss.is_pipe_topology_transition_seamless(

sys/dev/pci/drm/amd/display/dc/core/dc.c

5180

dc, dc->current_state, context))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5181

commit_minimal_transition_state_in_dc_update(dc, context, stream,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5184

if (is_fast_update_only && !dc->debug.enable_legacy_fast_update) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5185

commit_planes_for_stream_fast(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5194

dc->hwss.is_pipe_topology_transition_seamless &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5195

!dc->hwss.is_pipe_topology_transition_seamless(

sys/dev/pci/drm/amd/display/dc/core/dc.c

5196

dc, dc->current_state, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5201

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5209

if (dc->current_state != context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5210

swap_and_release_current_context(dc, context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5214

static void commit_planes_and_stream_update_on_current_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5225

if (fast_update_only(dc, fast_update, srf_updates, surface_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5227

!dc->debug.enable_legacy_fast_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5228

commit_planes_for_stream_fast(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

523

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5234

dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5237

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5243

dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5246

static void commit_planes_and_stream_update_with_new_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5254

if (!dc->hwss.is_pipe_topology_transition_seamless(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5255

dc->current_state, new_context))

sys/dev/pci/drm/amd/display/dc/core/dc.c

526

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5268

commit_minimal_transition_state_in_dc_update(dc, new_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5272

dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5281

static bool update_planes_and_stream_v3(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5299

if (!update_planes_and_stream_state(dc, srf_updates, surface_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5304

if (new_context == dc->current_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5305

commit_planes_and_stream_update_on_current_context(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5309

commit_planes_and_stream_update_with_new_context(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5312

swap_and_release_current_context(dc, new_context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5331

bool dc_update_planes_and_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5338

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5353

if (dc->ctx->dce_version >= DCN_VERSION_4_01)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5354

ret = update_planes_and_stream_v3(dc, srf_updates,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5357

ret = update_planes_and_stream_v2(dc, srf_updates,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5359

if (ret && (dc->ctx->dce_version >= DCN_VERSION_3_2 ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

5360

dc->ctx->dce_version == DCN_VERSION_3_01))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5366

void dc_commit_updates_for_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5375

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5381

if (dc->ctx->dce_version >= DCN_VERSION_4_01) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5382

ret = update_planes_and_stream_v3(dc, srf_updates, surface_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5385

ret = update_planes_and_stream_v2(dc, srf_updates, surface_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5389

if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5393

uint8_t dc_get_current_stream_count(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5395

return dc->current_state->stream_count;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5398

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5400

if (i < dc->current_state->stream_count)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5401

return dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5406

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5410

return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5416

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5419

if (dc == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5422

return dal_irq_service_set(dc->res_pool->irqs, src, enable);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5425

void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5427

dal_irq_service_ack(dc->res_pool->irqs, src);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5430

void dc_power_down_on_boot(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5432

if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5433

dc->hwss.power_down_on_boot) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5434

if (dc->caps.ips_support)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5435

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5436

dc->hwss.power_down_on_boot(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5440

void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5442

if (!dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5447

dc_state_construct(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5449

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5451

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5453

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5455

dc->hwss.init_hw(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5457

if (dc->hwss.init_sys_ctx != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5458

dc->vm_pa_config.valid) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5459

dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5463

if (dc->caps.ips_support)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5464

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5466

if (dc->caps.ips_v2_support) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5467

if (dc->clk_mgr->funcs->set_low_power_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5468

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5472

ASSERT(dc->current_state->stream_count == 0);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5473

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5475

dc_state_destruct(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5481

void dc_resume(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5485

for (i = 0; i < dc->link_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5486

dc->link_srv->resume(dc->links[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5489

bool dc_is_dmcu_initialized(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5491

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5498

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5500

if (dc->hwss.set_clock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5501

return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5504

void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5506

if (dc->hwss.get_clock)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5507

dc->hwss.get_clock(dc, clock_type, clock_cfg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5511

bool dc_set_psr_allow_active(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5516

for (i = 0; i < dc->current_state->stream_count ; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5518

struct dc_stream_state *stream = dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5541

bool dc_set_replay_allow_active(struct dc *dc, bool active)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5546

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5548

struct dc_stream_state *stream = dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5573

bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5575

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5577

dc->config.disable_ips = disable_ips;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5582

void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5587

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5589

if (dc->debug.disable_idle_power_optimizations) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5594

if (allow != dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5596

dc->idle_optimizations_allowed, allow, caller_name);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5598

if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5601

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5602

if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5605

if (allow == dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5608

if (dc->hwss.apply_idle_power_optimizations && dc->clk_mgr != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5609

dc->hwss.apply_idle_power_optimizations(dc, allow)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5610

dc->idle_optimizations_allowed = allow;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5615

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_fclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5616

idle_fclk_khz = dc->clk_mgr->funcs->get_hard_min_fclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5618

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5619

idle_dramclk_khz = dc->clk_mgr->funcs->get_hard_min_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5621

if (dc->res_pool && context) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5622

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5627

if (!dc->caps.is_apu)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5634

void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5636

if (dc->caps.ips_support)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5637

dc_allow_idle_optimizations_internal(dc, false, caller_name);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5640

bool dc_dmub_is_ips_idle_state(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5642

if (dc->debug.disable_idle_power_optimizations)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5645

if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5648

if (!dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5651

return dc->ctx->dmub_srv->idle_allowed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5655

void dc_unlock_memory_clock_frequency(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5657

if (dc->clk_mgr->funcs->set_hard_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5658

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5660

if (dc->clk_mgr->funcs->set_hard_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5661

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5665

void dc_lock_memory_clock_frequency(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5667

if (dc->clk_mgr->funcs->get_memclk_states_from_smu)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5668

dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5670

if (dc->clk_mgr->funcs->set_hard_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5671

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5673

if (dc->clk_mgr->funcs->set_hard_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5674

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5677

static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5679

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5684

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5688

dc->hwss.disable_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5699

if (dc->clk_mgr->funcs->set_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5700

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5701

if (dc->clk_mgr->funcs->set_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5702

dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5704

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5708

dc->hwss.disable_pixel_data(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5733

void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5738

if (!dc->config.dc_mode_clk_limit_support)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5741

softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5742

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5743

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5744

maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5746

funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5747

p_state_change_support = dc->clk_mgr->clks.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5749

if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5751

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5752

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5756

blank_and_force_memclk(dc, true, softMax);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5759

} else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5761

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5762

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5766

blank_and_force_memclk(dc, true, maxDPM);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5770

dc->clk_mgr->dc_mode_softmax_enabled = enable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5772

bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5778

if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, pitch, height, format, cursor_attr))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5784

void dc_hardware_release(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5786

dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5788

if (dc->hwss.hardware_release)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5789

dc->hwss.hardware_release(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5792

void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5794

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5795

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5810

bool dc_is_dmub_outbox_supported(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5812

if (!dc->caps.dmcub_support)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5815

switch (dc->ctx->asic_id.chip_family) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5819

if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5820

!dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5826

if (!dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5835

return dc->debug.enable_dmub_aux_for_legacy_ddc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5851

bool dc_enable_dmub_notifications(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5853

return dc_is_dmub_outbox_supported(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5863

void dc_enable_dmub_outbox(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5865

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5880

bool dc_process_dmub_aux_transfer_async(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

589

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5892

if (!dc->links[link_index]->ddc->ddc_pin)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5897

cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

592

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5933

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5938

uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5943

for (index = 0; index < dc->link_count; index++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5947

if (!dc->links[index]->ddc->ddc_pin) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5948

if (dc->links[index]->ddc_hw_inst == dpia_port_index) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5971

bool dc_process_dmub_set_config_async(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5983

cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5987

if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6016

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6027

cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6030

if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

sys/dev/pci/drm/amd/display/dc/core/dc.c

604

dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/core/dc.c

605

dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6061

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6067

cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6070

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6081

void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6089

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6101

void dc_print_dmub_diagnostic_data(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6103

dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6110

void dc_disable_accelerated_mode(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6112

bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6125

void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6142

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6153

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6178

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6193

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6204

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6223

void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6226

unsigned int max_cursor_size = dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6229

if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6230

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6231

stream_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6232

dc->current_state,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6233

dc->current_state->streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6256

void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6265

edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6282

if (!context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6284

struct dc *dc = context->clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6286

if (dc->res_pool->funcs->get_power_profile)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6287

profile.power_level = dc->res_pool->funcs->get_power_profile(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6302

struct dc *dc = context->clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6304

if (dc->res_pool->funcs->get_det_buffer_size)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6305

return dc->res_pool->funcs->get_det_buffer_size(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6323

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6328

dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6330

if (link->link_index < dc->lowest_dpia_link_index)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6333

*host_router_index = (link->link_index - dc->lowest_dpia_link_index) / dc->caps.num_of_dpias_per_host_router;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6334

if (*host_router_index < dc->caps.num_of_host_routers)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6340

bool dc_is_cursor_limit_pending(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6344

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6345

if (dc_stream_is_cursor_limit_pending(dc, dc->current_state->streams[i]))

sys/dev/pci/drm/amd/display/dc/core/dc.c

6352

bool dc_can_clear_cursor_limit(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6356

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6357

if (dc_state_can_clear_stream_cursor_subvp_limit(dc->current_state->streams[i], dc->current_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

6364

void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6370

if (dc->res_pool->timing_generators[i] &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

6371

dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6372

tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6377

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6378

if (dc->hwss.get_underflow_debug_data)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6379

dc->hwss.get_underflow_debug_data(dc, tg, out_data);

sys/dev/pci/drm/amd/display/dc/core/dc.c

655

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

658

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

670

dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

698

bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,

sys/dev/pci/drm/amd/display/dc/core/dc.c

707

&dc->current_state->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

713

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

771

bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

778

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

781

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

797

void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,

sys/dev/pci/drm/amd/display/dc/core/dc.c

804

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

807

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

809

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

829

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

sys/dev/pci/drm/amd/display/dc/core/dc.c

831

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

841

dc_exit_ips_for_hw_access(stream->ctx->dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

861

bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

867

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

870

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

871

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

872

dc->hwss.program_gamut_remap(pipes);

sys/dev/pci/drm/amd/display/dc/core/dc.c

880

bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

886

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

889

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

892

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

893

dc->hwss.program_output_csc(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

905

void dc_stream_set_static_screen_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

914

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

920

if (dc->current_state->res_ctx.pipe_ctx[j].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

923

&dc->current_state->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

928

dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

93

dc->ctx

sys/dev/pci/drm/amd/display/dc/core/dc.c

931

static void dc_destruct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

934

if (dc->res_pool && dc->res_pool->funcs->link_encs_assign &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

935

!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc.c

936

link_enc_cfg_init(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

938

if (dc->current_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

939

dc_state_release(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

940

dc->current_state = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

943

destroy_links(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

945

destroy_link_encoders(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

947

if (dc->clk_mgr) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

948

dc_destroy_clk_mgr(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

949

dc->clk_mgr = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

952

dc_destroy_resource_pool(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

954

dc_destroy_soc_and_ip_translator(&dc->soc_and_ip_translator);

sys/dev/pci/drm/amd/display/dc/core/dc.c

956

if (dc->link_srv)

sys/dev/pci/drm/amd/display/dc/core/dc.c

957

link_destroy_link_service(&dc->link_srv);

sys/dev/pci/drm/amd/display/dc/core/dc.c

959

if (dc->ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

96

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/core/dc.c

960

if (dc->ctx->gpio_service)

sys/dev/pci/drm/amd/display/dc/core/dc.c

961

dal_gpio_service_destroy(&dc->ctx->gpio_service);

sys/dev/pci/drm/amd/display/dc/core/dc.c

963

if (dc->ctx->created_bios)

sys/dev/pci/drm/amd/display/dc/core/dc.c

964

dal_bios_parser_destroy(&dc->ctx->dc_bios);

sys/dev/pci/drm/amd/display/dc/core/dc.c

965

kfree(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc.c

966

dc_perf_trace_destroy(&dc->ctx->perf_trace);

sys/dev/pci/drm/amd/display/dc/core/dc.c

968

kfree(dc->ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

969

dc->ctx = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

972

kfree(dc->bw_vbios);

sys/dev/pci/drm/amd/display/dc/core/dc.c

973

dc->bw_vbios = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

975

kfree(dc->bw_dceip);

sys/dev/pci/drm/amd/display/dc/core/dc.c

976

dc->bw_dceip = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

978

kfree(dc->dcn_soc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

979

dc->dcn_soc = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

981

kfree(dc->dcn_ip);

sys/dev/pci/drm/amd/display/dc/core/dc.c

982

dc->dcn_ip = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

984

kfree(dc->vm_helper);

sys/dev/pci/drm/amd/display/dc/core/dc.c

985

dc->vm_helper = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

989

static bool dc_construct_ctx(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

998

dc_stream_init_rmcm_3dlut(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

176

void post_surface_trace(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

178

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

185

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

188

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

40

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

45

if (dc->debug.surface_trace) \

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

50

if (dc->debug.clock_trace) \

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

55

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

60

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1000

dc->hwss.wait_for_dcc_meta_propagation(

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1001

params->wait_for_dcc_meta_propagation_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1005

dc->hwss.fams2_global_control_lock_fast(params);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1145

void hwss_wait_for_all_blank_complete(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1149

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1166

void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1185

hwss_wait_for_all_blank_complete(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1188

void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1202

dc->hwss.update_pending_status(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1212

void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1221

int opp_count = dc->res_pool->res_cap->num_opp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1226

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1236

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1237

dc->hwss.wait_for_all_pending_updates(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1247

if ((dc->res_pool->opps[opp_inst] != NULL) &&

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1248

(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1249

dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1250

dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1255

hwss_wait_for_odm_update_pending_complete(dc, dc_context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1258

void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1261

hwss_wait_for_outstanding_hw_updates(dc, dc_context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1264

if (dc->hwss.program_outstanding_updates)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1265

dc->hwss.program_outstanding_updates(dc, dc_context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

241

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

432

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

445

if (dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

447

*color = sm_ver_colors[dc->config.smart_mux_version];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

584

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

597

if (dc->ctx->dce_version < DCN_VERSION_4_01) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

631

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

638

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

661

for (int i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

704

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

711

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

715

if (!dc_state_is_fams2_in_use(dc, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

723

void hwss_build_fast_sequence(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

734

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

744

if (dc->hwss.wait_for_dcc_meta_propagation) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

745

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

750

if (dc->hwss.subvp_pipe_control_lock_fast) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

751

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

758

if (dc->hwss.fams2_global_control_lock_fast) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

759

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

761

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

765

if (dc->hwss.pipe_control_lock) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

766

block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

774

block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

786

if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

792

if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

793

block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

799

if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

802

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

809

block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

816

block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

823

if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

840

block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

846

if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE &&

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

847

dc->hwss.update_visual_confirm_color) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

848

block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

855

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

862

block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

869

block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

882

if (dc->hwss.pipe_control_lock) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

883

block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

889

if (dc->hwss.subvp_pipe_control_lock_fast) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

890

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

897

if (dc->hwss.fams2_global_control_lock_fast) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

898

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

900

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

924

void hwss_execute_sequence(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

930

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

937

dc->hwss.subvp_pipe_control_lock_fast(params);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

940

dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

945

dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

949

dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

954

dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

958

hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

963

dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

975

hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

980

dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

147

stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

168

for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

177

for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

243

link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

249

static void clear_enc_assignments(const struct dc *dc, struct dc_state *state)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

262

for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

263

if (dc->res_pool->link_encoders[i])

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

271

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

274

clear_enc_assignments(dc, state);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

287

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

29

#define DC_LOGGER dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

297

ASSERT(dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_STEADY);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

300

for (i = 0; i < dc->current_state->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

301

dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

326

if (state != dc->current_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

327

struct dc_state *prev_state = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

396

link_enc_cfg_validate(dc, state);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

40

for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

400

dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i] =

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

407

dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

41

link_enc = stream->ctx->dc->res_pool->link_encoders[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

449

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

454

struct dc_stream_state *stream = link_enc_cfg_get_stream_using_link_enc(dc, eng_id);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

463

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

470

struct link_enc_assignment assignment = get_assignment(dc, i);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

482

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

488

stream = link_enc_cfg_get_stream_using_link_enc(dc, eng_id);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

497

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

509

struct link_enc_assignment assignment = get_assignment(dc, i);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

514

link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

522

struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

533

struct link_enc_assignment assignment = get_assignment(dc, i);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

539

for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

541

dc->res_pool->link_encoders[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

542

link_enc = dc->res_pool->link_encoders[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

55

static struct link_enc_assignment get_assignment(struct dc *dc, int i)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

559

link->dc->res_pool->funcs->link_encs_assign) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

560

link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

563

link->ctx->dc);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

571

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

584

dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

59

if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

590

link_enc = stream->link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

598

bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

60

assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

605

struct link_enc_assignment assignment = get_assignment(dc, i);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

619

bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

62

assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

695

for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

730

void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

104

return link->dc->link_srv->is_hdcp1x_supported(link, signal);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

109

return link->dc->link_srv->is_hdcp2x_supported(link, signal);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

114

link->dc->link_srv->clear_dprx_states(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

119

return link->dc->link_srv->reset_cur_dp_mst_topology(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

126

return link->dc->link_srv->dp_link_bandwidth_kbps(link, link_settings);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

133

return link->dc->link_srv->dp_required_hblank_size_bytes(link,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

137

void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

139

dc->link_srv->get_cur_res_map(dc, map);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

142

void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

144

dc->link_srv->restore_res_map(dc, map);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

151

return link->dc->link_srv->update_dsc_config(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

155

dc_get_oem_i2c_device(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

157

return dc->res_pool->oem_device;

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

161

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

164

if (dc->res_pool->oem_device)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

166

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

167

dc->res_pool->oem_device,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

174

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

179

struct dc_link *link = dc->links[link_index];

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

183

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

189

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

192

struct ddc_service *ddc = dc->res_pool->oem_device;

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

196

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

205

link->dc->link_srv->dp_handle_automated_test(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

216

return link->dc->link_srv->dp_set_test_pattern(link, test_pattern,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

221

void dc_link_set_drive_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

227

dc->link_srv->get_cur_link_res(link, &link_res);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

228

dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

231

void dc_link_set_preferred_link_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

235

dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

238

void dc_link_set_preferred_training_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

244

dc->link_srv->dp_set_preferred_training_settings(dc, link_setting,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

250

return link->dc->link_srv->dp_trace_is_initialized(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

257

link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

262

return link->dc->link_srv->dp_trace_is_logged(link, in_detection);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

268

return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

274

return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

279

return link->dc->link_srv->dp_trace_get_link_loss_count(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

288

return link->dc->link_srv->add_remote_sink(link, edid, len, init_data);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

293

link->dc->link_srv->remove_remote_sink(link, sink);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

300

const struct dc *dc = ddc->link->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

302

return dc->link_srv->aux_transfer_raw(

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

306

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

308

return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

314

return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

321

return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

327

return link->dc->link_srv->mst_decide_link_encoding_format(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

332

return link->dc->link_srv->dp_get_verified_link_cap(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

341

else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

344

else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

355

return link->dc->link_srv->dp_is_sink_present(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

360

return link->dc->link_srv->dp_is_fec_supported(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

366

link->dc->link_srv->dp_overwrite_extended_receiver_cap(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

371

return link->dc->link_srv->dp_should_enable_fec(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

377

link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

384

return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

389

return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

39

struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

394

link->dc->link_srv->dp_handle_link_loss(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

401

return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

408

return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

414

link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

420

return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

425

link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

430

return link->dc->link_srv->edp_get_backlight_level(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

437

return link->dc->link_srv->edp_get_backlight_level_nits(link,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

44

return dc->links[link_index];

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

445

return link->dc->link_srv->edp_set_backlight_level(link,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

454

return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

460

return link->dc->link_srv->edp_get_target_backlight_pwm(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

465

return link->dc->link_srv->edp_get_psr_state(link, state);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

47

void dc_get_edp_links(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

471

return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

479

return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

485

return link->dc->link_srv->edp_set_replay_allow_active(link, allow_active, wait,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

491

return link->dc->link_srv->edp_get_replay_state(link, state);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

496

return link->dc->link_srv->edp_wait_for_t12(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

501

return link->dc->link_srv->get_hpd_state(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

506

link->dc->link_srv->enable_hpd(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

511

link->dc->link_srv->disable_hpd(link);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

516

link->dc->link_srv->enable_hpd_filter(link, enable);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

519

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

521

return dc->link_srv->validate_dp_tunnel_bandwidth(dc, new_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

528

link->dc->link_srv->edp_get_alpm_support(link, auxless_support, auxwake_support);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

54

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

56

if (!dc->links[i])

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

58

if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

59

edp_links[*edp_num] = dc->links[i];

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

66

bool dc_get_edp_link_panel_inst(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

76

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

87

return link->dc->link_srv->detect_link(link, reason);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

93

return link->dc->link_srv->detect_connection_type(link, type);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

98

return link->dc->link_srv->get_status(link);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1478

if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1699

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1971

struct dc *dc = otg_master->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1974

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

228

struct resource_pool *dc_create_resource_pool(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2304

static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2308

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2352

static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2360

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2376

resource_log_pipe(dc, dpp_pipes[dpp_idx],

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

238

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2382

resource_log_pipe(dc, opp_heads[slice_idx],

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2410

void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2414

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

242

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2428

resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2443

resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

246

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

251

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

255

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

259

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

263

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

267

init_data->num_virtual_links, dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

273

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2734

const struct dc *dc = link->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2735

const struct resource_context *res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2769

static bool add_dio_link_enc_to_ctx(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

278

init_data->num_virtual_links, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2794

int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

284

res_pool = dcn10_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2843

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2845

return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2867

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

287

res_pool = dcn20_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2876

if (stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2892

stream->ctx->dc, context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

290

res_pool = dcn21_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

293

res_pool = dcn201_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

296

res_pool = dcn30_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

299

res_pool = dcn301_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

302

res_pool = dcn302_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

305

res_pool = dcn303_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

308

res_pool = dcn31_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

311

res_pool = dcn314_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

314

res_pool = dcn315_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

317

res_pool = dcn316_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

320

res_pool = dcn32_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

323

res_pool = dcn321_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

326

res_pool = dcn35_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

329

res_pool = dcn351_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

332

res_pool = dcn36_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

335

res_pool = dcn401_create_resource_pool(init_data, dc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

343

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

345

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

363

void dc_destroy_resource_pool(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

365

if (dc) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

366

if (dc->res_pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

367

dc->res_pool->funcs->destroy(&dc->res_pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

369

kfree(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3745

static void mark_seamless_boot_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3748

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3750

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3754

if (!dc->config.allow_seamless_boot_optimization)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3758

if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3861

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3865

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3867

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3875

mark_seamless_boot_stream(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3891

acquired = acquire_otg_master_pipe_for_stream(dc->current_state,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3900

dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3916

if (!dc->link_srv->dp_decide_link_settings(stream,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3920

dc->link_srv->dp_decide_tunnel_settings(stream,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3923

if (dc->link_srv->dp_get_encoding_format(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3941

if (dc->config.unify_link_enc_assignment && is_dio_encoder)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3942

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3986

bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3988

if (dc->res_pool == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3991

return dc->res_pool->res_cap->num_dsc > 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

402

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4032

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4050

if (!dc_state_add_plane(dc, stream, set[i].plane_states[j], state))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

406

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4074

enum dc_status dc_validate_with_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4091

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

413

create_funcs->read_dce_straps(dc->ctx, &straps);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4162

if (!dc_state_rem_all_planes_for_stream(dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4186

if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4191

res = dc_state_remove_phantom_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4192

dc_state_release_phantom_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4194

if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4199

res = dc_state_remove_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4211

mark_seamless_boot_stream(dc, add_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4224

res = dc_state_add_stream(dc, context, add_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4228

if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4240

if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4252

res = dc_validate_global_state(dc, context, validate_mode);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4255

if ((dc->hwss.calculate_pix_rate_divider) && (res == DC_OK)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4257

dc->hwss.calculate_pix_rate_divider(dc, context, add_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4311

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4321

if (dc->res_pool->funcs->validate_global) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4322

result = dc->res_pool->funcs->validate_global(dc, new_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4330

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4337

if (dc->debug.enable_hblank_borrow)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4340

if (dc->res_pool->funcs->patch_unknown_plane_state &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4343

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4357

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4360

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4363

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4369

result = resource_build_scaling_params_for_context(dc, new_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4372

result = dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, validate_mode);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4803

if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4804

vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

481

dc->caps.dynamic_audio = false;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

483

dc->caps.dynamic_audio = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4834

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4839

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4852

if (!dc->config.disable_disp_pll_sharing)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4921

if (pipe_ctx_old->stream->ctx->dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4924

} else if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4926

struct dc *dc = pipe_ctx_old->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4928

link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

496

dc->hwseq = create_funcs->create_hwseq(ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5067

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5069

if (dc == NULL || stream == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5073

struct timing_generator *tg = dc->res_pool->timing_generators[0];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5091

res = dc->link_srv->validate_mode_timing(stream,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5098

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5108

if (dc->res_pool->funcs->validate_plane)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5109

return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5235

const struct dc *dc = link->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5236

const struct resource_context *res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5240

if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5241

link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx, dc->res_pool, link);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5244

} else if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5245

dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5247

dc->res_pool, link);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5255

void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5262

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5263

pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5273

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5283

void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5296

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5317

void reset_sync_context_for_pipe(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5325

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5334

uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5339

if (dc->ctx->dce_version == DCN_VERSION_3_1 &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5340

dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5434

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5442

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5474

dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5481

dcn20_build_mapped_resource(dc, state, sec_pipe->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5488

enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5492

if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5496

&context->res_ctx, dc->res_pool, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5502

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5508

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5514

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5523

if (pipe_ctx->link_res.dio_link_enc == NULL && dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5524

if (!add_dio_link_enc_to_ctx(dc, context, dc->res_pool, pipe_ctx, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5537

if (context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5538

context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config(context, mcache_params);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5543

void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5545

dml2_options->callbacks.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5564

dml2_options->svp_pstate.callbacks.dc = dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

567

if (stream1->ctx->dc->config.vblank_alignment_dto_params &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

568

stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

594

if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

647

if (stream1->ctx->dc->caps.disable_dp_clk_share)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

938

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

942

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

948

if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

949

dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

950

*base_offset = dc->debug.visual_confirm_rect_height;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

96

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

48

void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify)

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

55

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

68

get_link_index_from_dpia_port_index(dc, notify->instance);

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

83

void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout)

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

85

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

184

static void init_state(struct dc *dc, struct dc_state *state)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

190

memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

194

struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

203

init_state(dc, state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

204

dc_state_construct(dc, state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

208

if (dc->debug.using_dml2) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

209

if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

214

if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

283

void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

285

dc_state_copy(dst_state, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

288

struct dc_state *dc_state_create_current_copy(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

290

return dc_state_create_copy(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

293

void dc_state_construct(struct dc *dc, struct dc_state *state)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

295

state->clk_mgr = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

298

if (dc->res_pool)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

299

link_enc_cfg_init(dc, state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

374

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

380

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

382

if (state->stream_count >= dc->res_pool->timing_generator_count) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

392

state, dc->res_pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

403

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

417

dc->current_state, dc->res_pool, stream, 1);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

419

state, dc->res_pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

43

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

430

dc_stream_release_3dlut_for_stream(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

450

static void remove_mpc_combine_for_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

459

new_ctx, cur_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

464

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

469

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

491

dc->current_state, pool, otg_master_pipe, plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

496

remove_mpc_combine_for_stream(dc, state,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

497

dc->current_state,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

500

dc->current_state, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

509

dc->current_state, dc->res_pool, stream,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

513

dc->current_state, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

532

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

539

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

593

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

618

if (!dc_state_remove_plane(dc, stream, del_planes[i], state))

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

625

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

635

if (!dc_state_add_plane(dc, stream, plane_states[i], state)) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

710

struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

716

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

735

void dc_state_release_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

739

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

749

struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

753

struct dc_plane_state *phantom_plane = dc_create_plane_state(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

755

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

770

void dc_state_release_phantom_plane(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

774

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

785

enum dc_status dc_state_add_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

792

enum dc_status res = dc_state_add_stream(dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

820

enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

841

return dc_state_remove_stream(dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

845

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

850

bool res = dc_state_add_plane(dc, phantom_stream, phantom_plane, state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

862

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

867

return dc_state_remove_plane(dc, phantom_stream, phantom_plane, state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

871

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

897

if (!dc_state_remove_plane(dc, phantom_stream, del_planes[i], state))

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

900

dc_state_release_phantom_plane(dc, state, del_planes[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

907

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

913

return dc_state_add_all_planes_for_stream(dc, phantom_stream, phantom_planes, plane_count, state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

917

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

924

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

930

dc_state_rem_all_phantom_planes_for_stream(dc, phantom_stream, state, false);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

931

dc_state_remove_phantom_stream(dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

939

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

950

dc_state_release_phantom_stream(dc, state, phantom_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

955

dc_state_release_phantom_plane(dc, state, phantom_planes[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

974

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

982

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

983

is_fams2_in_use |= dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1216

bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1220

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1221

is_limit_pending = dc_state_get_stream_cursor_subvp_limit(stream, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1226

bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1230

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1231

can_clear_limit = dc_state_get_stream_cursor_subvp_limit(stream, dc->current_state) &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1234

dc_stream_check_cursor_attributes(stream, dc->current_state, &stream->cursor_attributes));

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

204

if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

205

!new_stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

223

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

224

return dc_state_get_stream_status(dc->current_state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

228

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

238

res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

248

dc->hwss.cursor_lock(dc, pipe_to_program, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

250

dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

253

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

254

if (dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

256

if (dc->hwss.set_cursor_sdr_white_level)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

257

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

261

dc->hwss.cursor_lock(dc, pipe_to_program, false);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

263

dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

275

const struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

293

dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

298

if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

299

max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

322

if (dc_stream_check_cursor_attributes(stream, stream->ctx->dc->current_state, attributes)) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

334

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

340

dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

343

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

345

if (dc->idle_optimizations_allowed) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

346

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

350

program_cursor_attributes(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

353

if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

354

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

363

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

37

#define DC_LOGGER dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

373

res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

387

dc->hwss.cursor_lock(dc, pipe_to_program, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

390

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

391

if (dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

396

dc->hwss.cursor_lock(dc, pipe_to_program, false);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

423

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

431

dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

434

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

437

if (dc->idle_optimizations_allowed &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

438

(!old_position->enable || dc->debug.exit_idle_opt_for_cursor_updates) &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

440

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

444

program_cursor_position(dc, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

446

if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

447

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

450

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

454

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

455

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

463

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

475

bool dc_stream_add_writeback(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

498

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

502

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

521

if (dc->hwss.enable_writeback) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

523

struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

528

if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

534

if (dc->hwss.enable_writeback) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

535

struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

539

dc->hwss.update_writeback(dc, wb_info, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

542

dc->hwss.enable_writeback(dc, wb_info, dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

549

bool dc_stream_fc_disable_writeback(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

553

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

56

if (stream->ctx->dc->caps.dual_link_dvi &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

570

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

586

bool dc_stream_remove_writeback(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

624

if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

629

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

632

if (dc->hwss.disable_writeback) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

633

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

636

dc->hwss.disable_writeback(dc, dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

645

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

647

&dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

649

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

668

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

676

dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

677

res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

679

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

687

if (dc->hwss.send_immediate_sdp_message != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

688

dc->hwss.send_immediate_sdp_message(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

708

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

714

dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

715

res_ctx = &dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

717

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

738

bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

743

if (!dc->hwss.dmdata_status_done)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

747

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

755

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

757

return dc->hwss.dmdata_status_done(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

760

bool dc_stream_set_dynamic_metadata(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

773

if (!dc->hwss.program_dmdata_engine)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

777

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

791

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

793

dc->hwss.program_dmdata_engine(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

803

enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

807

if (dc->res_pool->funcs->add_dsc_to_stream_resource) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

808

return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

819

struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

828

void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

880

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

884

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

888

if (dc->res_pool->rmcm_3dlut[i].isInUse &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

889

dc->res_pool->rmcm_3dlut[i].stream == stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

890

return &dc->res_pool->rmcm_3dlut[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

899

if (!dc->res_pool->rmcm_3dlut[i].isInUse) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

900

dc->res_pool->rmcm_3dlut[i].isInUse = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

901

dc->res_pool->rmcm_3dlut[i].stream = stream;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

902

return &dc->res_pool->rmcm_3dlut[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

912

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

916

dc_stream_get_3dlut_for_stream(dc, stream, false);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

926

void dc_stream_init_rmcm_3dlut(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

928

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

931

dc->res_pool->rmcm_3dlut[i].isInUse = false;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

932

dc->res_pool->rmcm_3dlut[i].stream = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

933

dc->res_pool->rmcm_3dlut[i].protection_bits = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

116

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

121

!plane_state->ctx->dc) {

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

127

dc = plane_state->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

129

if (dc->current_state == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

133

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

135

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

146

dc_exit_ips_for_hw_access(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

148

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

150

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

156

dc->hwss.update_pending_status(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

278

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

284

dc = plane_state->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

286

if (!dc || !dc->current_state)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

289

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

290

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

295

if (dc->hwss.clear_surface_dcc_and_tiling)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

296

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

73

for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

86

struct dc_plane_state *dc_create_plane_state(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

95

dc_plane_construct(dc->ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

37

int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

42

if (dc->hwss.init_sys_ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

43

num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config);

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

48

memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

49

dc->vm_pa_config.valid = true;

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

50

dc->dml2_options.gpuvm_enable = true;

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

51

dc_z10_save_init(dc);

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

57

void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid)

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

59

dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid);

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

62

int dc_get_vmid_use_vector(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

68

in_use |= dc->vm_helper->hubp_vmid_usage[i].vmid_usage[0]

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

69

| dc->vm_helper->hubp_vmid_usage[i].vmid_usage[1];

sys/dev/pci/drm/amd/display/dc/dc.h

1233

struct dc *dc_create(const struct dc_init_data *init_params);

sys/dev/pci/drm/amd/display/dc/dc.h

1234

void dc_hardware_init(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

1236

int dc_get_vmid_use_vector(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

1237

void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);

sys/dev/pci/drm/amd/display/dc/dc.h

1239

int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);

sys/dev/pci/drm/amd/display/dc/dc.h

1240

void dc_init_callbacks(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1242

void dc_deinit_callbacks(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

1243

void dc_destroy(struct dc **dc);

sys/dev/pci/drm/amd/display/dc/dc.h

1631

const struct dc *dc;

sys/dev/pci/drm/amd/display/dc/dc.h

1865

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

1887

bool dc_validate_boot_timing(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1891

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

sys/dev/pci/drm/amd/display/dc/dc.h

1893

enum dc_status dc_validate_with_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1903

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1908

struct dc *dc, bool acquire,

sys/dev/pci/drm/amd/display/dc/dc.h

1913

bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

1930

enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);

sys/dev/pci/drm/amd/display/dc/dc.h

1933

struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1938

uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);

sys/dev/pci/drm/amd/display/dc/dc.h

1955

struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);

sys/dev/pci/drm/amd/display/dc/dc.h

1958

bool dc_get_edp_link_panel_inst(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1963

void dc_get_edp_links(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

1967

void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,

sys/dev/pci/drm/amd/display/dc/dc.h

2068

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2078

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2092

dc_get_oem_i2c_device(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2095

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2206

void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/dc.h

2223

void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/dc.h

2231

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);

sys/dev/pci/drm/amd/display/dc/dc.h

2292

void dc_link_set_drive_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2323

void dc_link_set_preferred_link_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2339

void dc_link_set_preferred_training_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2506

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);

sys/dev/pci/drm/amd/display/dc/dc.h

2609

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2612

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2613

void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);

sys/dev/pci/drm/amd/display/dc/dc.h

2615

struct dc *dc, uint32_t link_index);

sys/dev/pci/drm/amd/display/dc/dc.h

2617

void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2622

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2624

void dc_resume(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2626

void dc_power_down_on_boot(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2635

bool dc_is_dmcu_initialized(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2637

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);

sys/dev/pci/drm/amd/display/dc/dc.h

2638

void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);

sys/dev/pci/drm/amd/display/dc/dc.h

2640

bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2646

#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)

sys/dev/pci/drm/amd/display/dc/dc.h

2647

#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)

sys/dev/pci/drm/amd/display/dc/dc.h

2649

void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);

sys/dev/pci/drm/amd/display/dc/dc.h

2650

void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);

sys/dev/pci/drm/amd/display/dc/dc.h

2651

bool dc_dmub_is_ips_idle_state(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2654

void dc_unlock_memory_clock_frequency(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2657

void dc_lock_memory_clock_frequency(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2660

void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2663

void dc_hardware_release(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2666

void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2668

bool dc_set_psr_allow_active(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2670

bool dc_set_replay_allow_active(struct dc *dc, bool active);

sys/dev/pci/drm/amd/display/dc/dc.h

2672

bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);

sys/dev/pci/drm/amd/display/dc/dc.h

2674

void dc_z10_restore(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2675

void dc_z10_save_init(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2677

bool dc_is_dmub_outbox_supported(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2678

bool dc_enable_dmub_notifications(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2681

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2685

void dc_enable_dmub_outbox(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2687

bool dc_process_dmub_aux_transfer_async(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2692

uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2695

bool dc_process_dmub_set_config_async(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2700

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2705

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);

sys/dev/pci/drm/amd/display/dc/dc.h

2707

void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2710

void dc_print_dmub_diagnostic_data(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2712

void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);

sys/dev/pci/drm/amd/display/dc/dc.h

2728

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

2733

void dc_disable_accelerated_mode(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2738

bool dc_is_cursor_limit_pending(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2739

bool dc_can_clear_cursor_limit(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc.h

2752

void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);

sys/dev/pci/drm/amd/display/dc/dc.h

459

struct dc;

sys/dev/pci/drm/amd/display/dc/dc.h

464

bool (*get_dcc_compression_cap)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc.h

467

bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc.h

727

unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \

sys/dev/pci/drm/amd/display/dc/dc.h

728

dm_get_timestamp(dc->ctx) : 0

sys/dev/pci/drm/amd/display/dc/dc.h

731

if (dc->debug.bw_val_profile.enable) \

sys/dev/pci/drm/amd/display/dc/dc.h

732

dc->debug.bw_val_profile.total_count++

sys/dev/pci/drm/amd/display/dc/dc.h

735

if (dc->debug.bw_val_profile.enable) { \

sys/dev/pci/drm/amd/display/dc/dc.h

737

voltage_level_tick = dm_get_timestamp(dc->ctx); \

sys/dev/pci/drm/amd/display/dc/dc.h

738

dc->debug.bw_val_profile.skip_ ## status ## _count++; \

sys/dev/pci/drm/amd/display/dc/dc.h

742

if (dc->debug.bw_val_profile.enable) \

sys/dev/pci/drm/amd/display/dc/dc.h

743

voltage_level_tick = dm_get_timestamp(dc->ctx)

sys/dev/pci/drm/amd/display/dc/dc.h

746

if (dc->debug.bw_val_profile.enable) \

sys/dev/pci/drm/amd/display/dc/dc.h

747

watermark_tick = dm_get_timestamp(dc->ctx)

sys/dev/pci/drm/amd/display/dc/dc.h

750

if (dc->debug.bw_val_profile.enable) { \

sys/dev/pci/drm/amd/display/dc/dc.h

751

end_tick = dm_get_timestamp(dc->ctx); \

sys/dev/pci/drm/amd/display/dc/dc.h

752

dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \

sys/dev/pci/drm/amd/display/dc/dc.h

753

dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \

sys/dev/pci/drm/amd/display/dc/dc.h

755

dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \

sys/dev/pci/drm/amd/display/dc/dc.h

756

dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1033

if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1148

void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1150

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1157

if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1163

if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1185

if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1191

if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1208

static int count_active_streams(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1212

for (i = 0; i < dc->current_state->stream_count; ++i) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1213

struct dc_stream_state *stream = dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1215

if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1222

static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1228

if (dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1231

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1234

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1246

if (dc->work_arounds.skip_psr_ips_crtc_disable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1260

dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1266

if (dc->config.disable_ips == DMUB_IPS_ENABLE ||

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1267

dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1274

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1276

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1280

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1285

} else if (dc->config.disable_ips == DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1287

if (count_active_streams(dc) == 0) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1302

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_Z8_RETENTION) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1309

if (dc->config.disable_ips_rcg == DMUB_IPS_RCG_ENABLE) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1312

} else if (dc->config.disable_ips_rcg == DMUB_IPS0_RCG_DISABLE) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1314

} else if (dc->config.disable_ips_rcg == DMUB_IPS1_RCG_DISABLE) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1318

if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1320

} else if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_ALL) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1337

dm_execute_dmub_cmd(dc->ctx, &cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1344

static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1349

if (dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1352

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1355

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1357

if (dc->clk_mgr->funcs->exit_low_power_state) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1390

if (!dc->caps.ips_v2_support && ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1391

(!dc->debug.optimize_ips_handshake ||

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1398

if (!dc->debug.optimize_ips_handshake || !ips_fw->signals.bits.ips2_commit)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1399

udelay(dc->debug.ips2_eval_delay_us);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1407

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1417

udelay(dc->debug.ips2_entry_delay_us);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1424

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1439

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1447

dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1451

dc_dmub_srv_notify_idle(dc, false);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1470

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1538

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1546

!dc_dmub_srv->ctx->dc->debug.disable_dmub_reallow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1547

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1552

void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1554

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1559

allow_idle &= (!dc->debug.ips_disallow_entry);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

157

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1576

dc_dmub_srv_exit_low_power_state(dc);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1598

dc_dmub_srv_notify_idle(dc, allow_idle);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1621

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1635

!ctx->dc->debug.disable_dmub_reallow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1636

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1678

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1685

!ctx->dc->debug.disable_dmub_reallow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1686

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1691

static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1712

global_cmd->config.global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1713

global_cmd->config.global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1714

global_cmd->config.global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1744

global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1754

dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1757

static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1761

struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1771

cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1776

config->global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1777

config->global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1778

config->global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1798

config->global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1801

dm_execute_dmub_cmd_list(dc->ctx, 1, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1804

void dc_dmub_srv_fams2_update_config(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1808

if (dc->debug.fams_version.major == 2)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1809

dc_dmub_srv_rb_based_fams2_update_config(dc, context, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1810

if (dc->debug.fams_version.major == 3)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1811

dc_dmub_srv_ib_based_fams2_update_config(dc, context, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1814

void dc_dmub_srv_fams2_drr_update(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1836

dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1840

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1935

dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

212

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2234

void dc_dmub_srv_release_hw(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2236

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2249

dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

275

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

365

bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

367

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

371

void dc_dmub_trace_event_control(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

373

dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

376

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

389

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

392

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

403

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

406

static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

412

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

420

static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

428

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

438

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

44

static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

448

if (dc == NULL)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

451

visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

460

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

472

cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

479

for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

48

dc_srv->ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

493

config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

494

dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

502

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

51

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

511

if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

531

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

536

if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

537

dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

550

if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

552

memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

575

static void populate_subvp_cmd_drr_info(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

61

dc_dmub_srv_construct(dc_srv, dc, dmub);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

616

(((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

622

dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

623

max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

633

max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

637

pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

654

static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

666

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

693

populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

710

static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

737

(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

740

(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

748

div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

756

div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

775

static void populate_subvp_cmd_pipe_info(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

827

div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

830

div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

842

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

870

void dc_dmub_setup_subvp_dmub_command(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

88

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

889

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

902

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

916

populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

922

populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

928

update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

930

cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

931

cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

936

(dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

941

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

105

void dc_dmub_srv_enable_dpia_trace(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

110

void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

196

void dc_dmub_srv_fams2_update_config(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

199

void dc_dmub_srv_fams2_drr_update(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

207

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

33

struct dc;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

333

void dc_dmub_srv_release_hw(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

82

bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

84

void dc_dmub_trace_event_control(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

86

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

88

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

89

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

92

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

99

void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

118

void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_options *options);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

65

bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

29

bool dc_edid_parser_send_cea(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

35

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

50

bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset)

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

52

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

63

bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

68

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.h

31

bool dc_edid_parser_send_cea(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.h

37

bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset);

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.h

39

bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

633

if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {

sys/dev/pci/drm/amd/display/dc/dc_helper.c

683

ctx->dc->debug.dmub_offload_enabled &&

sys/dev/pci/drm/amd/display/dc/dc_helper.c

684

!ctx->dc->debug.dmcub_emulation) {

sys/dev/pci/drm/amd/display/dc/dc_plane.h

38

struct dc_plane_state *dc_create_plane_state(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

136

pipe_ctx->stream->ctx->dc->debug.max_downscale_src_width;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

137

spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

144

spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

146

if (pipe_ctx->stream->ctx->dc->debug.force_easf == 1)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

148

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

151

unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

152

unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

184

if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

185

spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

189

if (pipe_ctx->stream->ctx->dc->debug.force_cositing)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

190

spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

202

(enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy;

sys/dev/pci/drm/amd/display/dc/dc_stat.h

40

void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify);

sys/dev/pci/drm/amd/display/dc/dc_stat.h

41

void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout);

sys/dev/pci/drm/amd/display/dc/dc_state.h

31

struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params);

sys/dev/pci/drm/amd/display/dc/dc_state.h

34

void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state);

sys/dev/pci/drm/amd/display/dc/dc_state.h

35

struct dc_state *dc_state_create_current_copy(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc_state.h

36

void dc_state_construct(struct dc *dc, struct dc_state *state);

sys/dev/pci/drm/amd/display/dc/dc_state.h

41

enum dc_status dc_state_add_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state.h

46

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state.h

51

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state.h

57

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state.h

63

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state.h

68

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

101

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

105

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

47

struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

50

struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

55

void dc_state_release_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

58

void dc_state_release_phantom_plane(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

63

enum dc_status dc_state_add_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

67

enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

72

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

78

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

84

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

90

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

97

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

388

bool dc_update_planes_and_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

403

void dc_commit_updates_for_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

412

void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

414

uint8_t dc_get_current_stream_count(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

415

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

439

bool dc_stream_add_writeback(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

443

bool dc_stream_fc_disable_writeback(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

447

bool dc_stream_remove_writeback(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

451

enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

455

bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

457

bool dc_stream_set_dynamic_metadata(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

461

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

468

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

474

void dc_trigger_sync(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

477

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

504

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

508

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

533

bool dc_stream_adjust_vmin_vmax(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

537

bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

553

bool dc_stream_configure_crc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

561

bool dc_stream_get_crc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

568

void dc_stream_set_static_screen_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

573

void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

579

bool dc_stream_set_gamut_remap(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

582

bool dc_stream_program_csc_matrix(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

586

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

591

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

594

void dc_stream_init_rmcm_3dlut(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

598

void dc_dmub_update_dirty_rect(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

604

bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

605

bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_trace.h

28

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \

sys/dev/pci/drm/amd/display/dc/dc_types.h

796

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

123

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

133

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

185

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

194

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

203

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

212

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

238

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

247

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

256

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

265

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

334

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

358

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

402

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

457

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

464

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

474

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

481

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

491

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

498

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

508

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

515

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

525

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

532

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

678

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

685

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

299

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

303

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

308

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1188

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

141

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1460

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1466

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1472

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1478

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1499

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1505

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1511

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1517

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1539

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1704

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1715

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1726

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1737

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

174

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1766

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1779

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1859

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1867

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1875

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1883

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1902

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1908

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1914

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1920

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1926

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1936

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1943

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1950

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1957

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1964

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

213

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

240

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

277

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

326

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

371

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

397

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

430

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

467

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

282

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

289

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

299

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

306

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

316

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

323

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

333

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

340

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

391

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

400

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

409

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

418

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

444

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

453

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

462

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

471

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

489

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

498

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

507

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

516

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

528

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

542

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

550

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

558

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

566

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

708

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

715

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

722

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

810

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

817

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

824

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

831

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

443

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

577

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

623

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

716

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

744

if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

254

struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

293

struct dc *core_dc = clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

345

struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

453

if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

573

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

582

if (dc->sclk_lvls.num_levels == 0)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

585

for (i = 0; i < dc->sclk_lvls.num_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

586

if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

587

return dc->sclk_lvls.clocks_in_khz[i];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

595

return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

599

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

608

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

609

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

613

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

633

dc,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

654

pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

668

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

669

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

696

dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

723

dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

750

dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

788

dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1088

dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1104

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1105

clock_source->ctx->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1113

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1114

clock_source->ctx->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1200

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1205

if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1206

clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1292

if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1293

clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1299

clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1335

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

973

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

980

if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

983

dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

382

const struct dc_config *config = &dmcu->ctx->dc->config;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

398

for (i = 0; i < ctx->dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

399

if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

400

if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A &&

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

401

ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

402

tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

34

struct dc *dc = ddc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

35

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

39

if (!dc->ctx->dc_bios->fw_info.oem_i2c_present)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

42

id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

327

if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

342

set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

431

set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

436

if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

754

if (ctx->dc->debug.scl_reset_length10)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1812

if (enc110->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

302

if (ctx->dc->caps.psp_setup_panel_mode)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

788

enc110->base.ctx->dc->debug.hdmi20_disable) &&

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

791

if (enc110->base.ctx->dc->debug.hdmi20_disable &&

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

910

if (enc110->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

321

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

348

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

374

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

407

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

188

if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

144

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

149

ret = dmub_abm_save_restore(dc, panel_inst, pData);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

224

if (ctx->dc->caps.dmcub_support) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

42

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

48

dc_get_edp_links(dc->dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

69

dc_allow_idle_optimizations(abm->ctx->dc, false);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

76

dc_allow_idle_optimizations(abm->ctx->dc, false);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

144

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

154

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

165

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

169

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

172

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

178

cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

185

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

192

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

202

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

220

struct dc_context *dc,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

229

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

232

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)pData, bytes);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

238

cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

246

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

249

memcpy((void *)pData, dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

261

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

274

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

285

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

296

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

305

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

315

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

56

static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

59

uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

60

uint32_t edp_id_count = dc->dc_edp_id_count;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

75

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h

44

struct dc_context *dc,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

81

dc_get_edp_links(link->dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

143

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

171

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

182

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

199

dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

234

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

248

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

258

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

267

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

276

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

286

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

298

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

302

struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

357

copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

365

copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

368

copy_settings_data->debug.bitfields.enable_ips_visual_confirm = dc->dc->debug.enable_ips_visual_confirm;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

379

copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

397

!link->dc->debug.disable_fec) &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

400

link->dc->caps.edp_dsc_support)) &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

427

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

438

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

448

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

100

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

109

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

121

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

125

struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

174

copy_settings_data->debug.bitfields.enable_ips_visual_confirm = dc->dc->debug.enable_ips_visual_confirm;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

181

!link->dc->debug.disable_fec) &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

184

link->dc->caps.edp_dsc_support)) &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

196

copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

197

copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

198

copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

200

dc->dc->debug.auxless_alpm_lfps_t1t2_us;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

202

dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

203

copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

206

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

219

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

231

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

289

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

305

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

50

struct dc_context *dc = dmub->ctx;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

66

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

757

if (ctx->dc->debug.disable_stutter) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

237

if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

110

static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned int bufSize, bool invarOnly)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

112

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

113

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

119

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

189

static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

191

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

231

static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

233

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

288

static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

290

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

328

static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

330

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

383

static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

385

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

414

static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

416

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

435

pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

470

static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

478

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

479

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

480

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

481

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

482

dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

483

dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

491

static void dcn10_clear_otpc_underflow(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

493

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

508

static void dcn10_clear_hubp_underflow(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

510

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

524

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

539

dcn10_clear_hubp_underflow(dc);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

542

dcn10_clear_otpc_underflow(dc);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

545

void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

570

chars_printed = dcn10_get_hubbub_state(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

576

chars_printed = dcn10_get_hubp_states(dc, pBuf, remaining_buf_size, mask & DC_HW_STATE_INVAR_ONLY);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

582

chars_printed = dcn10_get_rq_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

588

chars_printed = dcn10_get_dlg_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

594

chars_printed = dcn10_get_ttu_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

600

chars_printed = dcn10_get_cm_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

606

chars_printed = dcn10_get_mpcc_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

612

chars_printed = dcn10_get_otg_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

618

chars_printed = dcn10_get_clock_states(dc, pBuf, remaining_buf_size);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

72

static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned int bufSize)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

74

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

81

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

85

dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

33

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

35

void dcn10_log_hw_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

38

void dcn10_get_hw_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

205

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

265

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

440

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

61

if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

71

if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

101

uint32_t xtal = panel_cntl->ctx->dc->res_pool->ref_clocks.dccg_ref_clock_inKhz;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

176

if (dcn31_panel_cntl->base.ctx->dc->config.support_edp0_on_dp1) {

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

73

uint32_t freq_to_set = panel_cntl->ctx->dc->debug.pwm_freq;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

56

if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

70

if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false &&

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

646

enc10->base.ctx->dc->debug.hdmi20_disable) &&

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

649

if (enc10->base.ctx->dc->debug.hdmi20_disable &&

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

776

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1027

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

935

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

954

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

254

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

499

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

549

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

203

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

535

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

582

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

188

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

392

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

458

if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

468

link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

485

dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

505

if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

515

link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

532

dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

551

if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

564

link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

112

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

153

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

293

if (enc->ctx->dc->debug.dig_fifo_off_in_blank)

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

384

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

147

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

334

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

111

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

346

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

70

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

188

if (enc10->base.ctx->dc->debug.hdmi20_disable)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

123

dcn35_link_encoder_set_fgcg(enc, enc->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dio);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

267

if (enc10->base.ctx->dc->debug.hdmi20_disable)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

307

if (!enc->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

322

if (!enc->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

336

if (!enc->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

364

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

58

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

98

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

117

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

319

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

111

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

373

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

70

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

sys/dev/pci/drm/amd/display/dc/dm_services.h

127

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1003

v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1057

hack_bounding_box(v, &dc->debug, context);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1064

&& dc->debug.force_single_disp_pipe_split) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1070

(dc->debug.sr_exit_time_dpm0_ns

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1071

|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1073

if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1075

dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1076

if (dc->debug.sr_exit_time_dpm0_ns)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1077

v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1135

if (dc->debug.voltage_align_fclk)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1166

if (dc->debug.max_disp_clk == true)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1167

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1170

dc->debug.min_disp_clk_khz) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1172

dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1181

(int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1185

(int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1189

(int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1193

(int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1266

dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1282

dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1295

dc->dcn_soc->sr_enter_plus_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1296

context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1303

bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1309

if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1316

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1328

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1330

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1331

dc->dcn_soc->number_of_channels *

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1334

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1335

dc->dcn_soc->number_of_channels *

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1338

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1339

dc->dcn_soc->number_of_channels *

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1345

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1349

dc->dcn_soc->dcfclkv_min0p65 = dcfclks->data[0].clocks_in_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1350

dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1351

dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1352

dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1357

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1362

*min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1363

*min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1364

*socclk_khz = dc->dcn_soc->socclk * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1368

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1377

if (dc->res_pool->pp_smu)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1378

pp = &dc->res_pool->pp_smu->rv_funcs;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1403

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1429

void dcn_bw_sync_calcs_and_dml(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1465

dc->dcn_soc->sr_exit_time * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1466

dc->dcn_soc->sr_enter_plus_exit_time * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1467

dc->dcn_soc->urgent_latency * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1468

dc->dcn_soc->write_back_latency * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1469

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1470

dc->dcn_soc->max_request_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1471

dc->dcn_soc->dcfclkv_max0p9 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1472

dc->dcn_soc->dcfclkv_nom0p8 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1473

dc->dcn_soc->dcfclkv_mid0p72 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1474

dc->dcn_soc->dcfclkv_min0p65 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1475

dc->dcn_soc->max_dispclk_vmax0p9 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1476

dc->dcn_soc->max_dispclk_vnom0p8 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1477

dc->dcn_soc->max_dispclk_vmid0p72 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1478

dc->dcn_soc->max_dispclk_vmin0p65 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1479

dc->dcn_soc->max_dppclk_vmax0p9 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1480

dc->dcn_soc->max_dppclk_vnom0p8 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1481

dc->dcn_soc->max_dppclk_vmid0p72 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1482

dc->dcn_soc->max_dppclk_vmin0p65 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1483

dc->dcn_soc->socclk * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1484

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1485

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1486

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1487

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1488

dc->dcn_soc->phyclkv_max0p9 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1489

dc->dcn_soc->phyclkv_nom0p8 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1490

dc->dcn_soc->phyclkv_mid0p72 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1491

dc->dcn_soc->phyclkv_min0p65 * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1492

dc->dcn_soc->downspreading * 100,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1493

dc->dcn_soc->round_trip_ping_latency_cycles,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1494

dc->dcn_soc->urgent_out_of_order_return_per_channel,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1495

dc->dcn_soc->number_of_channels,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1496

dc->dcn_soc->vmm_page_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1497

dc->dcn_soc->dram_clock_change_latency * 1000,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1498

dc->dcn_soc->return_bus_width);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1533

dc->dcn_ip->rob_buffer_size_in_kbyte,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1534

dc->dcn_ip->det_buffer_size_in_kbyte,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1535

dc->dcn_ip->dpp_output_buffer_pixels,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1536

dc->dcn_ip->opp_output_buffer_lines,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1537

dc->dcn_ip->pixel_chunk_size_in_kbyte,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1538

dc->dcn_ip->pte_enable,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1539

dc->dcn_ip->pte_chunk_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1540

dc->dcn_ip->meta_chunk_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1541

dc->dcn_ip->writeback_chunk_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1542

dc->dcn_ip->odm_capability,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1543

dc->dcn_ip->dsc_capability,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1544

dc->dcn_ip->line_buffer_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1545

dc->dcn_ip->max_line_buffer_lines,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1546

dc->dcn_ip->is_line_buffer_bpp_fixed,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1547

dc->dcn_ip->line_buffer_fixed_bpp,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1548

dc->dcn_ip->writeback_luma_buffer_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1549

dc->dcn_ip->writeback_chroma_buffer_size,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1550

dc->dcn_ip->max_num_dpp,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1551

dc->dcn_ip->max_num_writeback,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1552

dc->dcn_ip->max_dchub_topscl_throughput,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1553

dc->dcn_ip->max_pscl_tolb_throughput,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1554

dc->dcn_ip->max_lb_tovscl_throughput,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1555

dc->dcn_ip->max_vscl_tohscl_throughput,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1556

dc->dcn_ip->max_hscl_ratio,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1557

dc->dcn_ip->max_vscl_ratio,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1558

dc->dcn_ip->max_hscl_taps,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1559

dc->dcn_ip->max_vscl_taps,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1560

dc->dcn_ip->pte_buffer_size_in_requests,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1561

dc->dcn_ip->dispclk_ramping_margin,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1562

dc->dcn_ip->under_scan_factor * 100,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1563

dc->dcn_ip->max_inter_dcn_tile_repeaters,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1564

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1565

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1566

dc->dcn_ip->dcfclk_cstate_latency);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1568

dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1569

dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1570

dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1571

dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1572

dc->dml.soc.ideal_dram_bw_after_urgent_percent =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1573

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1574

dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1575

dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1576

dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1577

dc->dcn_soc->round_trip_ping_latency_cycles;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1578

dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1579

dc->dcn_soc->urgent_out_of_order_return_per_channel;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1580

dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1581

dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1582

dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1583

dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1585

dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1586

dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1587

dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1588

dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1589

dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1590

dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1591

dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1592

dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1593

dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1594

dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1595

dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1596

dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1597

dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1598

dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1599

dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1600

dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1601

dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1602

dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1603

dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1604

dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1605

dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1606

dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1607

dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1608

dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1609

dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1611

dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1612

dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1613

dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1614

dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1615

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1616

dc->dml.ip.bug_forcing_LC_req_same_size_fixed =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1617

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1618

dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

318

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

40

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

453

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

458

struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

497

input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

638

static bool dcn_bw_apply_registry_override(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

642

if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

643

&& dc->debug.sr_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

645

dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

648

if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

649

!= dc->debug.sr_enter_plus_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

650

&& dc->debug.sr_enter_plus_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

652

dc->dcn_soc->sr_enter_plus_exit_time =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

653

dc->debug.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

656

if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

657

&& dc->debug.urgent_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

659

dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

662

if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

663

!= dc->debug.percent_of_ideal_drambw

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

664

&& dc->debug.percent_of_ideal_drambw) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

666

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

667

dc->debug.percent_of_ideal_drambw;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

670

if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

671

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

672

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

674

dc->dcn_soc->dram_clock_change_latency =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

675

dc->debug.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

749

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

759

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

770

if (dcn_bw_apply_registry_override(dc))

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

771

dcn_bw_sync_calcs_and_dml(dc);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

775

v->sr_exit_time = dc->dcn_soc->sr_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

776

v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

777

v->urgent_latency = dc->dcn_soc->urgent_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

778

v->write_back_latency = dc->dcn_soc->write_back_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

780

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

782

v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

783

v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

784

v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

785

v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

787

v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

788

v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

789

v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

790

v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

792

v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

793

v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

794

v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

795

v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

797

v->socclk = dc->dcn_soc->socclk;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

799

v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

800

v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

801

v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

802

v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

804

v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

805

v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

806

v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

807

v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

809

v->downspreading = dc->dcn_soc->downspreading;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

810

v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

811

v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

812

v->number_of_channels = dc->dcn_soc->number_of_channels;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

813

v->vmm_page_size = dc->dcn_soc->vmm_page_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

814

v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

815

v->return_bus_width = dc->dcn_soc->return_bus_width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

817

v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

818

v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

819

v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

820

v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

821

v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

822

v->pte_enable = dc->dcn_ip->pte_enable;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

823

v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

824

v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

825

v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

826

v->odm_capability = dc->dcn_ip->odm_capability;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

827

v->dsc_capability = dc->dcn_ip->dsc_capability;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

828

v->line_buffer_size = dc->dcn_ip->line_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

829

v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

830

v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

831

v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

832

v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

833

v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

834

v->max_num_dpp = dc->dcn_ip->max_num_dpp;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

835

v->max_num_writeback = dc->dcn_ip->max_num_writeback;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

836

v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

837

v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

838

v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

839

v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

840

v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

841

v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

842

v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

843

v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

844

v->under_scan_factor = dc->dcn_ip->under_scan_factor;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

845

v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

846

v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

847

v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

849

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

851

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

988

if (dc->debug.optimized_watermark) {

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

127

void dcn10_resource_construct_fp(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

130

if (dc->ctx->dce_version == DCN_VERSION_1_01) {

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

131

struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

132

struct dcn_ip_params *dcn_ip = dc->dcn_ip;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

133

struct display_mode_lib *dml = &dc->dml;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

140

if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

141

dc->dcn_soc->urgent_latency = 3;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

142

dc->debug.disable_dmcu = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

143

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

146

dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

147

ASSERT(dc->dcn_soc->number_of_channels < 3);

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

148

if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

149

dc->dcn_soc->number_of_channels = 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

151

if (dc->dcn_soc->number_of_channels == 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

152

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

153

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

154

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

155

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

156

if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev))

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

157

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h

30

void dcn10_resource_construct_fp(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1045

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1048

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1051

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1057

static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1063

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1084

int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1140

void dcn20_calculate_dlg_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1151

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1158

if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1159

context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1174

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1176

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1177

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1179

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1203

if (dc->ctx->dce_version < DCN_VERSION_3_1 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1224

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1231

if (dc->ctx->dce_version == DCN_VERSION_2_01)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1249

context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1314

int dcn20_populate_dml_pipes_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1325

for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1337

if (dc->debug.disable_timing_sync ||

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1349

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1367

pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1369

pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1454

if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1542

pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1679

|| dc->debug.always_scale; /*support always scale*/

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1725

dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1730

void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1741

for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1745

pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1767

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1771

if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1772

pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1773

if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1774

pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1780

if (dc->res_pool->funcs->populate_dml_pipes)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1781

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1784

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1847

void dcn20_update_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1864

if (dc->bb_overrides.min_dcfclk_mhz > 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1865

min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1867

if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1981

void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1985

if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1986

&& dc->bb_overrides.sr_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1987

bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1991

!= dc->bb_overrides.sr_enter_plus_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1992

&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1994

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1998

!= dc->bb_overrides.sr_exit_z8_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1999

&& dc->bb_overrides.sr_exit_z8_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2000

bb->sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2004

!= dc->bb_overrides.sr_enter_plus_exit_z8_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2005

&& dc->bb_overrides.sr_enter_plus_exit_z8_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2006

bb->sr_enter_plus_exit_z8_time_us = dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2008

if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2009

&& dc->bb_overrides.urgent_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2010

bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2014

!= dc->bb_overrides.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2015

&& dc->bb_overrides.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2017

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2021

!= dc->bb_overrides.dummy_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2022

&& dc->bb_overrides.dummy_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2024

dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2028

static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2038

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2042

out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2057

dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2058

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2078

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2090

dc->debug.disable_dram_clock_change_vactive_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2092

dc->debug.enable_dram_clock_change_one_display_vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2095

ASSERT(context != dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2098

return dcn20_validate_bandwidth_internal(dc, context, validate_mode, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2101

voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2113

memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2114

voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2154

int dcn21_populate_dml_pipes_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2164

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2168

pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2175

static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2179

if (dc->bb_overrides.sr_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2181

dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2182

dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2186

if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2188

dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2189

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2193

if (dc->bb_overrides.urgent_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2194

bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2197

if (dc->bb_overrides.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2199

dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2200

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2235

static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2245

struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2249

patch_bounding_box(dc, &context->bw_ctx.dml.soc);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2251

for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2255

pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2280

if (dc->res_pool->funcs->populate_dml_pipes)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2281

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2284

pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2319

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2329

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2336

ASSERT(context != dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2338

out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2353

dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2354

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2401

void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2403

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2404

struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2461

dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2474

void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2485

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

38

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

989

void dcn20_populate_dml_writeback_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

997

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

31

void dcn20_populate_dml_writeback_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

39

void dcn20_calculate_dlg_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

44

int dcn20_populate_dml_pipes_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

48

void dcn20_calculate_wm(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

57

void dcn20_update_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

62

void dcn20_patch_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

64

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

75

int dcn21_populate_dml_pipes_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

79

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

81

void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

85

void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

182

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

191

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

218

if (dc->dml.ip.writeback_max_hscl_taps > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

258

dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

289

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

294

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

297

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

298

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

299

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

304

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

330

dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

333

dummy_latency_index = dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

341

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

342

dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

361

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

366

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

367

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

368

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

408

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

413

dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

417

int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

420

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

429

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

434

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

436

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

437

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

462

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

478

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

485

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

489

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

490

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

491

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

492

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

499

dc->dml.soc.num_chans <= 4 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

503

for (i = 0; i < dc->dml.soc.num_states; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

504

if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

505

context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

511

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

516

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

519

dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

522

void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

526

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

527

dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

568

void dcn30_fpu_update_bw_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

578

dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

579

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

599

dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

600

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

601

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

620

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

633

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

634

dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

661

double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

662

double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

663

double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

721

void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

725

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

728

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

33

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

41

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

44

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

49

void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

57

void dcn30_fpu_update_bw_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

63

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

71

void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

323

void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

325

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

326

struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

391

dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

392

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

395

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

396

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

397

dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

399

dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

426

void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

435

struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

467

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

474

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

478

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

479

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

480

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

481

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

485

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h

30

void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h

36

void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

195

void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

211

if (dc->ctx->dc_bios->vram_info.num_chans)

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

212

dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

214

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

215

dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

217

dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

218

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

343

dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

344

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

345

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.h

30

void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

191

void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

207

if (dc->ctx->dc_bios->vram_info.num_chans)

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

208

dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

210

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

211

dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

213

dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

214

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

362

dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

363

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

364

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.h

29

void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

454

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

458

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

459

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

460

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

461

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

465

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

469

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

474

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

476

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

478

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

483

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

513

if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time &&

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

514

cstate_enter_plus_exit_z8_ns < dc->debug.minimum_z8_residency_time * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

515

cstate_enter_plus_exit_z8_ns = dc->debug.minimum_z8_residency_time * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

522

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

537

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

547

if (dc->config.forced_clocks || dc->debug.max_disp_clk) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

551

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

552

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

553

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

554

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

559

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

572

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

576

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

590

void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

592

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

603

dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

604

dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

656

dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

657

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

660

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

661

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

662

dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

665

dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

668

void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

675

dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

676

dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

721

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

722

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

723

dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

726

dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN315);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

729

void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

731

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

742

dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

743

dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

798

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

801

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

802

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

803

dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

806

dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

38

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

39

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

42

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

47

void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

48

void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

49

void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

55

int dcn31x_populate_dml_pipes_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

182

void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

194

if (dc->config.use_default_clock_table == false) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

195

dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

196

dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

265

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

268

dcn20_patch_bounding_box(dc, &dcn3_14_soc);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

269

dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

307

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

319

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

321

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

356

if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

357

pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

394

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

396

&& pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

399

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

405

} else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

406

&& dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

407

context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

412

if (dc->debug.force_odm_combine_4to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

415

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

421

if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

35

void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

36

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1037

static bool subvp_validate_static_schedulability(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1048

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1074

schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1079

if (dcn32_subvp_drr_admissable(dc, context))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1080

schedulable = subvp_drr_schedulable(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1081

else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1082

schedulable = subvp_vblank_schedulable(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1093

static void assign_subvp_index(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1098

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1200

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1231

dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1267

static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1274

dc->current_state, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1280

dc->current_state, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1285

static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1294

&slice_table, dc, context, vba,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1296

update_pipes_with_slice_table(dc, context, &slice_table);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1300

static bool should_apply_odm_power_optimization(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1312

if (!dc->debug.enable_single_display_2to1_odm_policy)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1347

if (dc->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1361

&slice_table, dc, context, v,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1394

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1416

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1437

static bool dcn32_full_validate_bw_helper(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1460

if (dc->debug.dml_disallow_alternate_prefetch_modes)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1470

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1475

if (!dcn32_apply_merge_split_flags_helper(dc, context, repopulate_pipes, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1487

if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1488

!dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && !is_test_pattern_enabled(context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1492

dc->debug.force_subvp_mclk_switch)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1496

while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1497

dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1518

dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1520

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1538

&& subvp_validate_static_schedulability(dc, context, *vlevel))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1542

if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1561

dc_state_remove_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1562

dc_state_release_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1564

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1570

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1575

dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1585

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1589

assign_subvp_index(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1593

if (should_apply_odm_power_optimization(dc, context, vba, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1595

dc, context, pipes, split, merge, vlevel, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1600

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1604

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1607

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1645

static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1657

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1675

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1685

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1686

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1700

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1785

context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1789

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1794

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1810

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1823

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1824

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1825

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

183

static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1840

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1852

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1859

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1861

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

189

double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

190

double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

191

double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1917

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

192

double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1938

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1948

if (dc->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1950

dc, context, vba, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1958

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

197

uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2006

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2032

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2034

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2062

hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2068

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2085

pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2090

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2104

pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2109

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2115

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2118

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2138

bool dcn32_internal_validate_bw(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2160

dc_state_remove_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2161

dc_state_release_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2163

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2166

resource_update_pipes_for_stream_with_slice_count(context, dc->current_state, dc->res_pool, context->streams[i], 1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2167

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2175

context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2178

if (!dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2184

(dc->debug.dml_disallow_alternate_prefetch_modes &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2208

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2219

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2227

&& !dc->config.enable_windowed_mpo_odm

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2238

if (!dcn32_apply_merge_split_flags_helper(dc, context, &repopulate_pipes, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2242

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2252

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2253

if (!dc->config.enable_windowed_mpo_odm)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2254

dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2302

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2317

bool subvp_in_use = dcn32_subvp_in_use(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2335

dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2341

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2344

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2347

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2348

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

235

if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2364

if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2367

fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2376

dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2385

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2389

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2392

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2394

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2415

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2416

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2439

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2440

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2441

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2442

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2443

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2508

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2513

dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2517

int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2520

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2529

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2534

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2536

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2537

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2538

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2556

if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2576

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2577

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2578

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2595

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2602

if (dc->config.forced_clocks) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2606

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2607

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2608

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2609

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2619

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2621

dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2626

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2631

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

275

int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

292

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

293

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

297

dcn32_subvp_in_use(dc, context))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3051

void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3056

dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3059

if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3060

&& dc->bb_overrides.sr_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3061

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3062

dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3066

!= dc->bb_overrides.sr_enter_plus_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3067

&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3068

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3070

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3073

if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3074

&& dc->bb_overrides.urgent_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3075

dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3076

dc->dml2_options.bbox_overrides.urgent_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3077

dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3081

!= dc->bb_overrides.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3082

&& dc->bb_overrides.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3083

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3085

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3089

!= dc->bb_overrides.fclk_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3090

&& dc->bb_overrides.fclk_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3091

dc->dml2_options.bbox_overrides.fclk_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3093

dc->bb_overrides.fclk_clock_change_latency_ns / 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3097

!= dc->bb_overrides.dummy_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3098

&& dc->bb_overrides.dummy_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3100

dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3104

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3107

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3109

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3114

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3119

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3126

if (dc->ctx->dc_bios->vram_info.num_chans) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3127

dc->dml2_options.bbox_overrides.dram_num_chan =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3128

dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3129

dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3130

dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3133

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3134

dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3135

dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3138

dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3140

dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3143

dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3144

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3145

dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3146

dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3147

dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3148

dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3152

if (dc->debug.use_legacy_soc_bb_mechanism) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3305

build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3310

dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3311

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3312

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3315

if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3318

dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3320

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3321

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3323

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3324

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3326

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3327

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3329

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

333

void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3330

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3332

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3333

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3335

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3336

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3338

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3339

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3341

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3342

if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3343

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3344

dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3347

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3348

if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3349

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3350

dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3353

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3354

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3355

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3356

dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3359

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3360

if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3361

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3362

dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3365

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3366

if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3367

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3368

dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3371

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3372

if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3373

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3374

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3375

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3376

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

342

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3433

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3446

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3459

if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3489

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3523

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3528

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3560

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3567

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3585

pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed || blank_us >= dc->debug.fpo_vactive_max_blank_us) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3600

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3603

if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3604

dc->dml.soc.num_chans <= 8) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3605

int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3607

if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3609

context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

466

void dcn32_set_phantom_stream_timing(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

487

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

500

pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

501

dc->caps.subvp_pstate_allow_width_us) / 1000000) *

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

516

pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

524

phantom_vactive += dc->debug.subvp_extra_lines;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

558

static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

564

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

575

free_pipes = dc->res_pool->pipe_count - num_pipes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

599

static bool dcn32_assign_subvp_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

606

unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

609

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

632

(!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

634

(refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

680

static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

683

unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

686

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

703

free_pipes = dcn32_get_num_free_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

707

if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

726

static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

736

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

752

dc->caps.subvp_prefetch_end_to_mall_start_us +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

753

dc->caps.subvp_fw_processing_delay_us + 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

797

static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

818

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

835

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

857

dc->caps.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

898

static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

924

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

952

dc->caps.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

985

static bool subvp_subvp_admissable(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

994

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

34

void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

39

void dcn32_set_phantom_stream_timing(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

47

bool dcn32_internal_validate_bw(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

54

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

59

void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

61

int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

72

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

74

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

76

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

610

void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

614

dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

617

if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

618

&& dc->bb_overrides.sr_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

619

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

620

dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

624

!= dc->bb_overrides.sr_enter_plus_exit_time_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

625

&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

626

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

628

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

631

if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

632

&& dc->bb_overrides.urgent_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

633

dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

634

dc->dml2_options.bbox_overrides.urgent_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

635

dcn3_21_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

639

!= dc->bb_overrides.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

640

&& dc->bb_overrides.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

641

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

643

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

647

!= dc->bb_overrides.fclk_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

648

&& dc->bb_overrides.fclk_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

649

dc->dml2_options.bbox_overrides.fclk_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

651

dc->bb_overrides.fclk_clock_change_latency_ns / 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

655

!= dc->bb_overrides.dummy_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

656

&& dc->bb_overrides.dummy_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

658

dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

662

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

665

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

667

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

672

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

677

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

684

if (dc->ctx->dc_bios->vram_info.num_chans) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

685

dc->dml2_options.bbox_overrides.dram_num_chan =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

686

dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

687

dcn3_21_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

688

dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

691

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

692

dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

693

dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

696

dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

698

dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

701

dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

702

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

703

dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

704

dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

705

dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

706

dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

709

if (dc->debug.use_legacy_soc_bb_mechanism) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

855

build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

860

dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

861

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

862

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

864

if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

867

dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

869

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

870

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

872

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

873

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

875

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

876

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

878

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

879

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

881

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

882

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

884

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

885

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

887

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

888

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

891

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

892

if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

893

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

894

dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

897

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

898

if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

899

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

900

dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

903

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

904

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

905

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

906

dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

909

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

910

if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

911

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

912

dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

915

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

916

if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

917

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

918

dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

921

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

922

if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

923

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

924

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

925

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

926

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.h

32

void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

227

void dcn35_update_bw_bounding_box_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

234

dc->scratch.update_bw_bounding_box.clock_limits;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

240

dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

241

dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

321

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

324

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

325

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

327

dc->debug.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

330

if (dc->bb_overrides.dram_clock_change_latency_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

332

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

334

if (dc->bb_overrides.sr_exit_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

335

dcn3_5_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

337

if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

339

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

341

if (dc->bb_overrides.sr_exit_z8_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

342

dcn3_5_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

344

if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

346

dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

349

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

356

dc->dml2_options.bbox_overrides.clks_table.num_states =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

358

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

360

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

362

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

364

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

366

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

368

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

371

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

372

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

374

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

376

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

378

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

380

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

382

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

384

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

386

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

392

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

394

dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

395

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

397

dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

398

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

437

int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

450

dcn31_populate_dml_pipes_from_context(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

453

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

531

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

533

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

537

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

548

dc->debug.crb_alloc_policy_min_disp_count &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

549

dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

551

dc->debug.crb_alloc_policy * 64;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

556

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

563

dc->debug.seamless_boot_odm_combine &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

578

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

582

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

586

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

600

dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

603

dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

34

void dcn35_update_bw_bounding_box_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

37

int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

42

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

261

void dcn351_update_bw_bounding_box_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

268

dc->scratch.update_bw_bounding_box.clock_limits;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

274

dc->res_pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

275

dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

355

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

358

!= dc->debug.dram_clock_change_latency_ns

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

359

&& dc->debug.dram_clock_change_latency_ns) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

361

dc->debug.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

364

if (dc->bb_overrides.dram_clock_change_latency_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

366

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

368

if (dc->bb_overrides.sr_exit_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

369

dcn3_51_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

371

if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

373

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

375

if (dc->bb_overrides.sr_exit_z8_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

376

dcn3_51_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

378

if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

380

dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

383

dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

390

dc->dml2_options.bbox_overrides.clks_table.num_states =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

392

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

394

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

396

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

398

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

400

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

402

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

404

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

405

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

407

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

409

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

411

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

413

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

415

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

417

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

419

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

425

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_51_soc.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

427

dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_51_soc.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

428

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_51_soc.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

430

dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_51_soc.sr_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

431

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_51_soc.sr_enter_plus_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

470

int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

483

dcn31_populate_dml_pipes_from_context(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

486

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

564

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

566

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

570

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

581

dc->debug.crb_alloc_policy_min_disp_count &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

582

dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

584

dc->debug.crb_alloc_policy * 64;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

589

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

596

dc->debug.seamless_boot_odm_combine &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

611

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

616

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

631

dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

12

int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

17

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

9

void dcn351_update_bw_bounding_box_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

127

if (stream->ctx->dc->caps.max_v_total != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

14

const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

140

stream->ctx->dc->config.enable_fpo_flicker_detection == 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

277

if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

280

stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

432

const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

556

} else if ((plane_state->ctx->dc->config.use_spl == true) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

568

if (plane_state->ctx->dc->debug.always_scale == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

59

const struct dc *in_dc)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

727

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

76

unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

78

if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

851

void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

20

void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

21

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

23

void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

9

struct dc;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

196

static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

200

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

236

bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

242

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

250

phantom_stream = dml_ctx->config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

273

dml_ctx->config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

279

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

287

phantom_plane = dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

315

dml_ctx->config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

320

void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

344

dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

361

dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

374

dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

377

void dml21_build_fams2_programming(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

419

if (dc->debug.fams_version.major == 3) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

429

switch (dc->debug.fams_version.minor) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

440

for (k = 0; k < dc->res_pool->pipe_count; k++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

470

switch (dc->debug.fams_version.minor) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

477

for (k = 0; k < dc->res_pool->pipe_count; k++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

481

switch (dc->debug.fams_version.minor) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

84

int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

33

int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

44

void dml21_handle_phantom_streams_planes(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

46

void dml21_build_fams2_programming(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

125

num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

168

if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

169

context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

204

static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

266

static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

297

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

311

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

38

static void dml21_populate_configuration_options(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

466

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

54

static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

70

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

87

static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

13

struct dc;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

31

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

37

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

61

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

65

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1006

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

749

ctx->config.callbacks.acquire_secondary_pipe_for_mpc_odm(ctx->config.callbacks.dc, state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

783

ctx->config.callbacks.acquire_secondary_pipe_for_mpc_odm(ctx->config.callbacks.dc, state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

970

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

977

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

999

ctx->config.callbacks.dc->res_pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

125

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

717

ctx->config.svp_pstate.callbacks.dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

727

ctx->config.svp_pstate.callbacks.add_phantom_stream(ctx->config.svp_pstate.callbacks.dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

748

ctx->config.svp_pstate.callbacks.dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

775

ctx->config.svp_pstate.callbacks.add_phantom_plane(ctx->config.svp_pstate.callbacks.dc, phantom_stream, phantom_plane, state);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

832

if (!ctx->config.svp_pstate.callbacks.remove_phantom_plane(ctx->config.svp_pstate.callbacks.dc, stream, del_planes[i], context))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

834

ctx->config.svp_pstate.callbacks.release_phantom_plane(ctx->config.svp_pstate.callbacks.dc, context, del_planes[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

853

ctx->config.svp_pstate.callbacks.remove_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

854

ctx->config.svp_pstate.callbacks.release_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

245

void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

327

void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

34

void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

610

void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

679

void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

713

void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

719

out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

720

out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

721

out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

722

out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

723

out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

724

out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

725

out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

726

out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

727

out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

728

out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

729

out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

730

out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

731

out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

732

out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

733

out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

734

out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

735

out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

739

out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

740

out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

744

out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

745

out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

746

out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

747

out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

748

out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

30

void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

31

void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

32

void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

34

void dml2_translate_ip_params(const struct dc *in_dc, struct ip_params_st *out);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

35

void dml2_translate_socbb_params(const struct dc *in_dc, struct soc_bounding_box_st *out);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

36

void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

169

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

173

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

279

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

293

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

294

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

369

if (dc->config.forced_clocks || dc->debug.max_disp_clk) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

122

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

45

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

96

enum dc_status dml2_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

36

static void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

369

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

381

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

389

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

398

static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

44

static void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

487

if (context->streams[0]->sink->link->dc->caps.is_apu)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

53

const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

541

static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

543

if (dc->debug.override_odm_optimization) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

544

dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

548

bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

581

static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

626

bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

660

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

694

void dml2_reinit(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

115

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

117

struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

120

struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

123

enum dc_status (*add_phantom_stream)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

127

bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

128

bool (*remove_phantom_plane)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

132

enum dc_status (*remove_phantom_stream)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

135

void (*release_phantom_plane)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

138

void (*release_phantom_stream)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

146

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

149

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

152

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

258

bool dml2_create(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

267

void dml2_reinit(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

295

bool dml2_validate(const struct dc *in_dc,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

308

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

36

struct dc;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

73

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

76

bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

77

bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

137

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

138

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

174

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

168

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

169

dpp->base.ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

468

if (dpp->base.ctx->dc->debug.use_max_lb) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

619

dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

630

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

659

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

57

if (dpp_base->ctx->dc->debug.cm_in_bypass)

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

203

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

204

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

251

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1207

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1401

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

467

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

468

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

506

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

573

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

578

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

590

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

595

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

607

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

612

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

132

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

137

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

227

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

51

if (dpp_base->ctx->dc->debug.cm_in_bypass)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1065

dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1094

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1104

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1133

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1143

if (dpp->base.ctx->dc->config.prefer_easf)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1183

if (dpp->base.ctx->dc->config.prefer_easf)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

160

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

161

dpp->base.ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

288

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

474

if (dpp->base.ctx->dc->debug.use_max_lb) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

521

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1452

void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_options *options)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1454

options->dsc_min_slice_height_override = dc->debug.dsc_min_slice_height_override;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1455

options->dsc_force_odm_hslice_override = dc->debug.force_odm_combine;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

331

bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

399

if (dc->debug.dsc_bpp_increment_div) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

404

if (dc->debug.dsc_bpp_increment_div >= 1)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

406

if (dc->debug.dsc_bpp_increment_div >= 2)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

408

if (dc->debug.dsc_bpp_increment_div >= 4)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

410

if (dc->debug.dsc_bpp_increment_div >= 8)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

412

if (dc->debug.dsc_bpp_increment_div >= 16)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

594

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

596

if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

599

dc = dsc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

601

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool || dc->debug.disable_dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

605

max_dscclk_khz = dc->clk_mgr->funcs->get_max_clock_khz(dc->clk_mgr, CLK_TYPE_DSCCLK);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

619

max_odm_combine_factor = dc->caps.max_odm_combine_factor;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

620

num_dsc = dc->res_pool->res_cap->num_dsc;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

644

if (dsc && dsc->ctx->dc) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

645

if (dsc->ctx->dc->clk_mgr &&

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

646

dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

648

max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

674

if (!dsc || !dsc->ctx || !dsc->ctx->dc || dsc->ctx->dc->debug.disable_dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

684

if (dsc->ctx->dc->debug.native422_support)

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

178

i2c_command.speed = link->ddc->ctx->dc->caps.i2c_speed_in_khz;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

609

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

830

struct dc *dc = hubbub1->base.ctx->dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

840

if (dc->debug.disable_dcc == DCC_DISABLE)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

883

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

462

struct dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

221

struct dc *dc = hubbub->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

230

if (dc->debug.disable_dcc == DCC_DISABLE)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

279

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

615

if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

616

hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

626

hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

73

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

135

if (!hubbub1->base.ctx->dc->config.skip_riommu_prefetch_wa) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

613

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

132

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

133

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

280

struct dc *dc = hubbub->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

289

if (dc->debug.disable_dcc == DCC_DISABLE)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

338

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

382

uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1043

if (hubbub->ctx->dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

753

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

754

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

808

struct dc *dc = hubbub->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

816

if (dc->debug.disable_dcc == DCC_DISABLE)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

865

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

766

struct dc *dc = hubbub->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

769

if (!safe_to_lower && dc->debug.disable_stutter_for_wm_program &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

770

(ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) ||

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

771

ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

810

hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

812

if (dc->debug.disable_stutter_for_wm_program &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

813

(ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) ||

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

814

ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

817

} else if (dc->debug.disable_stutter) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

818

hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

821

hubbub32_force_usr_retraining_allow(hubbub, dc->debug.force_usr_allow);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

970

uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

994

if (hubbub->ctx->dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

329

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

330

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

332

hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

521

if (hubbub->ctx->dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

530

hubbub->ctx->dc->debug.enable_fine_grain_clock_gating

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

489

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

491

hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

831

struct dc *dc = hubbub->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

832

const unsigned int max_dcc_plane_width = dc->caps.dcc_plane_width_limit;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

844

if (dc->debug.disable_dcc == DCC_DISABLE)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

971

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

796

if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

52

hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

47

void dce_pipe_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

53

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

89

void dce60_pipe_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1282

void dce_pipe_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1290

void dce60_pipe_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

109

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

112

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

114

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

115

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

121

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

124

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

126

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

127

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

134

void dce100_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

136

dce110_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

138

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

139

dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

140

dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

141

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

73

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

80

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

35

void dce100_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

38

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

42

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

45

bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1012

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1020

ctx->dc->link_srv->edp_receiver_ready_T7(link);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1029

if (ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1030

ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1044

!link->dc->config.edp_no_power_sequencing &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1053

ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1057

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1065

ctx->dc->link_srv->edp_add_delay_for_T9(link);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1081

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1089

dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1090

clk_mgr = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1099

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1118

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1125

dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1126

clk_mgr = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1153

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1155

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1162

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1172

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1179

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1183

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1190

if (!(dc->ctx->dce_version >= DCN_VERSION_3_5)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1207

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1225

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1233

link->dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1236

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1253

!link->dc->config.edp_no_power_sequencing) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1261

link->dc->link_srv->edp_receiver_ready_T9(link);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1301

dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1314

link->dc->link_srv->dp_is_fec_supported(link)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1477

static void program_scaler(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1486

if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1489

color_space_to_black_color(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1519

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1522

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1529

color_space_to_black_color(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1544

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1584

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1591

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1597

hws->funcs.disable_stream_gating(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1615

if (dc->config.disable_hbr_audio_dp2)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1617

dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1622

if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1623

check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1655

if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1659

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1662

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1685

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1693

((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1697

dc->link_srv->set_dsc_enable(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1701

dc->link_srv->set_dpms_on(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1708

if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1710

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1728

static void power_down_encoders(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1732

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1733

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1737

dc->link_srv->blank_dp_stream(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1755

static void power_down_controllers(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1759

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1760

dc->res_pool->timing_generators[i]->funcs->disable_crtc(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1761

dc->res_pool->timing_generators[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1765

static void power_down_clock_sources(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1769

if (dc->res_pool->dp_clock_source->funcs->cs_power_down(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1770

dc->res_pool->dp_clock_source) == false)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1773

for (i = 0; i < dc->res_pool->clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1774

if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1775

dc->res_pool->clock_sources[i]) == false)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1780

static void power_down_all_hw_blocks(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1782

power_down_encoders(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1784

power_down_controllers(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1786

power_down_clock_sources(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1788

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1789

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1793

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1797

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1799

if (dc->caps.ips_support)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1802

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1803

tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1808

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1814

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1815

dc->hwss.disable_plane(dc, dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1816

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1838

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1846

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1847

if (dc->links[i]->local_sink &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1848

dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1849

edp_links_with_sink[*edp_with_sink_num] = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1856

static void clean_up_dsc_blocks(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1861

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1862

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1865

if (!dc->caps.is_apu ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1866

dc->ctx->dce_version < DCN_VERSION_3_15)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1869

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1872

dsc = dc->res_pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1876

if (i < dc->res_pool->timing_generator_count) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1877

tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1882

if (i < dc->res_pool->stream_enc_count) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1883

se = dc->res_pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1908

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1916

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1924

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1928

get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1929

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1932

hws->funcs.init_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1937

if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1948

can_apply_edp_fast_boot = dc_validate_boot_timing(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1954

if (dc->is_switch_in_progress_dest && edp_link->is_dds)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1967

dc->res_pool->dccg->funcs->get_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1968

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2002

keep_edp_vdd_on |= dc->is_switch_in_progress_dest;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2011

clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2013

power_down_all_hw_blocks(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2019

clean_up_dsc_blocks(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2021

disable_vga_and_power_gate_all_controllers(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2023

dc->hwss.edp_power_control(edp_link_with_sink, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2025

clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2027

bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2048

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2052

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2062

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

208

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

215

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

216

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2184

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2186

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2199

static bool should_enable_fbc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2206

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2209

ASSERT(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2212

if (!dc->ctx->fbc_gpu_addr)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2219

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2232

if (i == dc->res_pool->pipe_count)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2265

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2270

if (should_enable_fbc(dc, context, &pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2273

struct compressor *compr = dc->fbc_compressor;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2279

compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2289

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2298

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2318

dc->link_srv->set_dpms_off(pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2327

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2330

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2346

pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2349

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2353

dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2361

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2385

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2400

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2403

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2404

dc->res_pool->dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2422

if (i == dc->res_pool->pipe_count) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2423

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2452

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2455

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2456

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2459

bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2463

if (dc->config.use_pipe_ctx_sync_logic)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2464

reset_syncd_pipes_from_disabled_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2468

hws->funcs.reset_hw_ctx_wrap(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2478

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2480

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2488

dce_crtc_switch_to_clk_src(dc->hwseq,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2494

dc, i, dc->ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2498

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2499

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2501

dce110_setup_audio_dto(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2503

if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2504

dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2507

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2509

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2529

dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2536

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2540

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2541

enable_fbc(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2592

static void program_surface_visibility(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2615

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2638

static void update_plane_addr(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2676

void dce110_power_down(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2678

power_down_all_hw_blocks(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2679

disable_vga_and_power_gate_all_controllers(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2722

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2728

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2770

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2774

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2803

static void dce110_init_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2808

static void dce110_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2815

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2819

bp = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2820

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2821

xfm = dc->res_pool->transforms[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2825

dc, i, bp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2828

dc, i, bp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2831

dc->ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2835

dce_clock_gating_power_up(dc->hwseq, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2838

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

284

dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2843

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2848

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2849

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2859

for (i = 0; i < dc->res_pool->audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2860

struct audio *audio = dc->res_pool->audios[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2864

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2865

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2873

abm = dc->res_pool->abm;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2877

dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2881

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2882

dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2888

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2891

struct clk_mgr *dccg = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2893

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2902

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2905

struct clk_mgr *dccg = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2907

dce110_set_displaymarks(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2917

struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2924

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2931

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2959

program_scaler(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2972

if (dc->config.gpu_vm_support)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2983

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2986

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3027

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3037

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3038

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3040

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3054

dce110_program_front_end_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3056

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3058

program_surface_visibility(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3062

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3063

enable_fbc(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3067

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3072

static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3074

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3079

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3083

dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3085

dc->res_pool->transforms[fe_idx]->funcs->transform_reset(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3086

dc->res_pool->transforms[fe_idx]);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3090

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3097

static void program_output_csc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3126

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3190

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3193

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3277

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3278

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3280

link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3282

link->dc->res_pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3292

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3311

dc->link_srv->dp_get_encoding_format(link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3317

if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3318

if (dc->clk_mgr->funcs->notify_link_rate_change)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3319

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3334

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3341

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3343

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3346

link->dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3348

link->dc->hwss.edp_backlight_control(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3361

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3424

void dce110_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3426

dc->hwss = dce110_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3427

dc->hwseq->funcs = dce110_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

607

dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

669

const struct dc *dc = link->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

677

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

741

hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

808

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

813

ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

819

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

820

ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

835

if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

874

if (ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

875

ctx->dc->debug.dmub_command_table) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

895

ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

900

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

901

ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

91

struct dc_context *ctx = dc->ctx

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

929

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

936

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

122

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

36

void dce110_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

39

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

45

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

62

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

64

void dce110_power_down(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

71

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

75

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

114

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

121

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

152

void dce112_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

157

dce110_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

158

dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.h

34

void dce112_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

152

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

161

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

260

void dce120_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

265

dce110_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

266

dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

267

dc->hwss.update_dchub = dce120_update_dchub;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

268

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h

35

void dce120_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

115

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

120

if (dce60_should_enable_fbc(dc, context, &pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

123

struct compressor *compr = dc->fbc_compressor;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

129

compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

181

static void dce60_program_surface_visibility(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

232

static void dce60_program_scaler(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

239

if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

242

color_space_to_black_color(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

271

struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

278

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

286

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

314

dce60_program_scaler(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

327

if (dc->config.gpu_vm_support)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

341

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

382

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

392

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

393

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

395

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

409

dce60_program_front_end_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

411

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

413

dce60_program_surface_visibility(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

417

if (dc->fbc_compressor)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

418

dce60_enable_fbc(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

421

void dce60_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

423

dce110_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

425

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

426

dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

427

dc->hwss.cursor_lock = dce60_pipe_control_lock;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

428

dc->hwss.pipe_control_lock = dce60_pipe_control_lock;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

429

dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

430

dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

431

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

50

static bool dce60_should_enable_fbc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

57

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

60

ASSERT(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

63

if (!dc->ctx->fbc_gpu_addr)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

70

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

86

if (i == dc->res_pool->pipe_count)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h

34

void dce60_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

45

void dce80_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

47

dce110_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

49

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

50

dc->hwss.pipe_control_lock = dce_pipe_control_lock;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

51

dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

52

dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

53

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.h

34

void dce80_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

101

void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1033

static void undo_DEGVIDCN10_253_wa(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1035

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1036

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1053

static void apply_DEGVIDCN10_253_wa(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1055

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1056

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1059

if (dc->debug.disable_stutter)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1065

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1066

if (!dc->res_pool->hubps[i]->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1083

void dcn10_bios_golden_init(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1085

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1086

struct dc_bios *bp = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1090

if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1093

if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1095

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1109

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1115

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1117

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1118

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1119

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1124

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1131

if (!dc->hwseq->wa.false_optc_underflow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1136

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1137

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1142

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1181

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1204

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1242

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1261

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

127

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1282

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1288

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

130

dc->hwss.get_position(&pipe_ctx, 1, &position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1302

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1304

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1311

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1314

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1327

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1337

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1338

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1341

if (i == dc->res_pool->pipe_count)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1349

static bool dcn10_hw_wa_force_recovery(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1354

if (!dc->debug.recovery_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1366

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1368

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1377

hubbub1_soft_reset(dc->res_pool->hubbub, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1379

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1381

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1389

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1391

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1400

hubbub1_soft_reset(dc->res_pool->hubbub, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1401

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1403

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1415

void dcn10_verify_allow_pstate_change_high(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1417

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1427

dcn10_log_hw_state(dc, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1431

if (dcn10_hw_wa_force_recovery(dc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1440

void dcn10_plane_atomic_disconnect(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1444

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1447

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1465

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1470

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1471

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1487

void dcn10_plane_atomic_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1491

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1492

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1520

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1522

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1527

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1539

dc->optimized_required = false; /* We're powering off, no need to optimize */

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1541

hws->funcs.plane_atomic_power_down(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1553

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1555

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1556

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1561

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1563

apply_DEGVIDCN10_253_wa(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1569

void dcn10_init_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1572

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1573

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1584

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1585

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1600

hws->funcs.init_blank(dc, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1611

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1613

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1628

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1635

dc->res_pool->mpc->funcs->mpc_init_single_inst(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1636

dc->res_pool->mpc, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1639

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1640

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1641

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1642

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1664

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1679

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1680

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1681

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1682

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1684

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1689

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1703

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1705

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1706

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1707

int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1710

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1728

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1730

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1745

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1748

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1754

hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1759

void dcn10_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1762

struct abm *abm = dc->res_pool->abm;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1763

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1764

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1765

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1766

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

177

void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1771

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1772

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1775

if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1776

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1777

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1781

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1782

dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1785

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1787

if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1788

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1791

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1793

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1798

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1814

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1819

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1835

dc->link_srv->blank_all_dp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1838

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1846

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1848

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1849

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1850

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1851

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1863

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1864

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

188

dc->hwss.get_position(&pipe_ctx, 1, &position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1886

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1895

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1896

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1904

void dcn10_power_down_on_boot(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

191

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1911

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1917

dc->hwseq->funcs.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1918

dc->hwseq->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1919

dc->hwss.edp_power_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1920

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1921

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1922

dc->hwss.edp_power_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1924

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1925

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1929

dc->hwseq->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1930

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1942

if (dc->clk_mgr->funcs->set_low_power_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1943

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1947

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1951

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1954

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1956

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1969

dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1971

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2006

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2031

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2043

if (!dpp_base->ctx->dc->debug.always_use_regamma

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2109

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2129

else if (cm_helper_translate_curve_to_hw_format(dc->ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2148

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2152

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2160

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2161

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2168

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2169

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

219

void dcn10_lock_all_pipes(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2190

static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2198

if (!dc->hwss.calc_vupdate_position || !dc->hwss.get_position)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2204

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2207

dc->hwss.get_position(&pipe_ctx, 1, &position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2238

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2246

delay_cursor_until_vupdate(dc, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2255

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2260

dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

228

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

229

old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2383

static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2386

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2397

dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2405

if (dc->config.vblank_alignment_dto_params &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2406

dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2408

(dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2410

(dc->config.vblank_alignment_dto_params >> 48) & 0x7FFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2412

dc->config.vblank_alignment_dto_params & 0xFFFFFFFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2418

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2419

dc->res_pool->dp_clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

245

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2453

dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2454

dc->res_pool->dp_clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2457

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2458

dc->res_pool->dp_clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

247

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2474

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2479

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2509

master = dcn10_align_pixel_clocks(dc, group_size, grouped_pipes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

251

static void log_mpc_crc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2539

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

254

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2545

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

255

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2622

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2626

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

265

static void dcn10_log_hubbub_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

268

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

273

dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2731

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2735

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2737

if (dc->debug.sanity_checks) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2738

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2741

undo_DEGVIDCN10_253_wa(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2743

power_on_plane_resources(dc->hwseq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2754

if (dc->config.gpu_vm_support)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2757

if (dc->debug.sanity_checks) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2758

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2826

void dcn10_program_output_csc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2876

void dcn10_update_visual_confirm_color(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2880

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2887

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2894

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2936

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

294

static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2946

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2948

dc->res_pool->mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2951

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2958

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

296

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

297

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2978

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2982

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3022

dc->clk_mgr->clks.dispclk_khz)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3027

dc->clk_mgr->clks.dispclk_khz / 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3034

if (dc->res_pool->dccg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3035

dc->res_pool->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3036

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3040

dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3041

dc->clk_mgr->clks.dispclk_khz / 2 :

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3042

dc->clk_mgr->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3073

hws->funcs.update_mpcc(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3093

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3094

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3096

if (dc->hwss.set_cursor_sdr_white_level)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3097

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3102

dc->hwss.program_gamut_remap(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3104

dc->hwss.program_output_csc(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3133

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3140

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3151

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3171

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3175

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3202

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3206

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3223

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3225

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3229

dcn10_enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3231

dcn10_update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3247

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3250

void dcn10_wait_for_pending_cleared(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3257

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3283

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3288

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3297

false_optc_underflow_wa(dc, pipe_ctx->stream, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3301

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3303

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3305

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3307

dc->hwss.optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3311

if (dc->hwseq->wa.DEGVIDCN10_254)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3312

hubbub1_wm_change_req_wa(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3315

static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3325

hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3332

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3335

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3336

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3339

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3340

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3345

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3346

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3350

dc->optimized_required = hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3352

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3354

dcn10_stereo_hw_frame_pack_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3356

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3359

dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3362

dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3365

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3366

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3370

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3373

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3374

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3377

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3378

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3383

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3384

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3390

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3393

dcn10_stereo_hw_frame_pack_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3395

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3398

dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3401

dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3404

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3405

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3516

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3524

if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3525

dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3527

dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3556

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3560

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3563

if (dc->debug.sanity_checks) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3564

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3582

if (dc->debug.sanity_checks) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3583

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3589

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3602

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3621

if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3622

struct dce_hwseq *hwseq = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3623

struct timing_generator *tg = dc->res_pool->timing_generators[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3627

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3629

hubbub->funcs->allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3637

struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3650

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3945

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3951

int vupdate_pos = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3961

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3975

vline_pos += dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3990

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3997

dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4002

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4005

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4022

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4051

enum dc_status dcn10_set_clock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4056

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4060

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_clock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4063

dc->clk_mgr->funcs->get_clock(dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4083

if (dc->clk_mgr->funcs->update_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4084

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4090

void dcn10_get_clock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4094

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4096

if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4097

dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4101

void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4103

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

449

static void dcn10_log_color_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

452

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

453

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

522

dc->caps.color.dpp.input_lut_shared,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

523

dc->caps.color.dpp.icsc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

524

dc->caps.color.dpp.dgam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

525

dc->caps.color.dpp.dgam_rom_caps.srgb,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

526

dc->caps.color.dpp.dgam_rom_caps.bt2020,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

527

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

528

dc->caps.color.dpp.dgam_rom_caps.pq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

529

dc->caps.color.dpp.dgam_rom_caps.hlg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

530

dc->caps.color.dpp.post_csc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

531

dc->caps.color.dpp.gamma_corr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

532

dc->caps.color.dpp.dgam_rom_for_yuv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

533

dc->caps.color.dpp.hw_3d_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

534

dc->caps.color.dpp.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

535

dc->caps.color.dpp.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

550

dc->caps.color.mpc.gamut_remap,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

551

dc->caps.color.mpc.num_3dluts,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

552

dc->caps.color.mpc.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

553

dc->caps.color.mpc.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

610

void dcn10_log_hw_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

613

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

614

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

619

dcn10_log_hubbub_state(dc, log_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

621

dcn10_log_hubp_states(dc, log_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

623

if (dc->hwss.log_color_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

624

dc->hwss.log_color_state(dc, log_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

626

dcn10_log_color_state(dc, log_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

721

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

722

struct link_encoder *lenc = dc->links[i]->link_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

741

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

742

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

743

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

744

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

745

dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

746

dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

747

dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

749

log_mpc_crc(dc, log_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

813

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

88

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

902

if (hws->ctx->dc->debug.disable_dpp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

963

if (hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

104

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

108

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

112

void dcn10_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

113

void dcn10_init_pipes(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

114

void dcn10_power_down_on_boot(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

116

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

118

void dcn10_plane_atomic_disconnect(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

123

void dce110_power_down(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

124

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

126

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

132

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

137

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

148

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

159

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

161

void dcn10_log_hw_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

163

void dcn10_get_hw_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

167

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

169

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

187

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

189

enum dc_status dcn10_set_clock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

193

void dcn10_get_clock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

196

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

197

void dcn10_bios_golden_init(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

198

void dcn10_plane_atomic_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

202

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

205

void dcn10_wait_for_pending_cleared(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

208

void dcn10_verify_allow_pstate_change_high(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

210

void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

213

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

34

void dcn10_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

38

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

42

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

46

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

48

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

51

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

54

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

58

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

61

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

64

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

66

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

71

void dcn10_program_output_csc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

76

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

78

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

80

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

81

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

83

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

85

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

87

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

91

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

123

void dcn10_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

125

dc->hwss = dcn10_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

126

dc->hwseq->funcs = dcn10_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.h

31

void dcn10_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1001

void dcn20_program_output_csc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1007

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1029

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1033

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1050

cm_helper_translate_curve_to_hw_format(dc->ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1115

bool dcn20_set_input_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1119

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1191

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1215

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1232

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1235

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1237

if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1249

dc->hwss.set_disp_pattern_generator(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1262

dc->hwss.set_disp_pattern_generator(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1274

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1312

void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1318

dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1368

if (dc->vm_pa_config.valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1373

apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1374

apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1392

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1444

dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1458

dcn20_setup_gsl_group_as_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1470

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1483

if (dc->hwseq->funcs.perform_3dlut_wa_unlock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1484

dc->hwseq->funcs.perform_3dlut_wa_unlock(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

150

dc->caps.color.dpp.input_lut_shared,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

151

dc->caps.color.dpp.icsc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

152

dc->caps.color.dpp.dgam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

153

dc->caps.color.dpp.dgam_rom_caps.srgb,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

154

dc->caps.color.dpp.dgam_rom_caps.bt2020,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

155

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

156

dc->caps.color.dpp.dgam_rom_caps.pq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

157

dc->caps.color.dpp.dgam_rom_caps.hlg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

158

dc->caps.color.dpp.post_csc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

159

dc->caps.color.dpp.gamma_corr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

160

dc->caps.color.dpp.dgam_rom_for_yuv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

161

dc->caps.color.dpp.hw_3d_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

162

dc->caps.color.dpp.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

163

dc->caps.color.dpp.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1680

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1684

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1688

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1770

hws->funcs.update_mpcc(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1786

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1787

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1788

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1804

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1805

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1807

if (dc->hwss.set_cursor_sdr_white_level)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1808

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1819

dc->hwss.program_gamut_remap(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1822

dc->hwss.program_output_csc(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

183

dc->caps.color.mpc.gamut_remap,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

184

dc->caps.color.mpc.num_3dluts,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

185

dc->caps.color.mpc.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

186

dc->caps.color.mpc.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1862

params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1867

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

190

static int find_free_gsl_group(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1904

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

192

if (dc->res_pool->gsl_groups.gsl_0 == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1924

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1928

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1932

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1939

hws->funcs.blank_pixel_data(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

194

if (dc->res_pool->gsl_groups.gsl_1 == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1947

dcn20_program_tg(dc, pipe_ctx, context, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1950

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1954

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1956

dcn20_enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1958

if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1959

dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

196

if (dc->res_pool->gsl_groups.gsl_2 == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1963

if (dc->res_pool->hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1964

dc->res_pool->hubbub->funcs->program_det_size(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1965

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1967

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1968

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1969

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1975

dcn20_update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1986

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1995

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2020

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2032

dc->hwss.set_disp_pattern_generator(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2045

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2051

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2054

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2056

if (resource_is_pipe_topology_changed(dc->current_state, context))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2057

resource_log_pipe_topology_update(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2059

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2060

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2066

dc->hwss.program_triplebuffer(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2067

dc, pipe, pipe->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2072

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2073

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2080

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2081

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2082

dc->res_pool->hubbub, true, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2087

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2088

dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2094

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2095

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2097

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2100

dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2101

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2104

if (dc->hwseq->funcs.blank_pixel_data)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2105

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2112

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2117

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2120

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2123

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2137

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2138

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2139

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2140

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2142

hws->funcs.plane_atomic_disconnect(dc, dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2143

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2144

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2148

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2154

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2161

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2167

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2179

dcn20_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

218

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2193

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2200

dc->current_state->stream_status[0].plane_count == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2211

void dcn20_post_unlock_reset_opp(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2215

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2221

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, opp_head);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2226

if (dc->hwseq->funcs.dsc_pg_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2227

is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2245

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2251

struct dce_hwseq *hwseq = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2254

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2255

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2257

dcn20_post_unlock_reset_opp(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2258

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2260

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2262

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2270

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2284

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2286

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2306

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2307

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2308

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2310

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2324

if (dc->hwss.apply_update_flags_for_phantom)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2325

dc->hwss.apply_update_flags_for_phantom(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2326

if (dc->hwss.update_phantom_vp_position)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2327

dc->hwss.update_phantom_vp_position(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2328

dcn20_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

234

group_idx = find_free_gsl_group(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2346

dc->hwseq->funcs.update_force_pstate(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2352

hwseq->funcs.program_mall_pipe_config(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2356

dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2361

if (dc->current_state->stream_status[0].plane_count == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2364

struct timing_generator *tg = dc->res_pool->timing_generators[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2366

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2375

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2378

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2383

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2384

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2388

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2402

dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2404

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2415

dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2418

dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

242

dc->res_pool->gsl_groups.gsl_0 = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2426

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2429

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2432

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2445

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2448

if (dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2449

if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2450

context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2451

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2458

dc_dmub_srv_p_state_delegate(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

246

dc->res_pool->gsl_groups.gsl_1 = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2461

dc->clk_mgr->clks.fw_based_mclk_switching = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2463

dc->clk_mgr->clks.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2466

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2467

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2471

!dc->debug.disable_extblankadj) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2472

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2485

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2489

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2492

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2496

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2499

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

250

dc->res_pool->gsl_groups.gsl_2 = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2520

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2523

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2538

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2548

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2549

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2552

optc = dc->res_pool->timing_generators[dwb->otg_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2565

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2572

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2573

mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2611

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2613

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2626

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2628

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2663

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

268

dc->res_pool->gsl_groups.gsl_0 = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2680

dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2683

int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2698

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

272

dc->res_pool->gsl_groups.gsl_1 = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2729

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2741

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

276

dc->res_pool->gsl_groups.gsl_2 = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2763

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2778

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2797

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2800

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2810

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2816

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2819

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2832

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2834

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2842

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2845

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2857

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2878

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2879

&& dc->ctx->dce_version >= DCN_VERSION_3_5) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2902

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2906

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2909

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2911

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2924

dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2926

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2933

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2940

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2988

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2998

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3000

dc->res_pool->mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3003

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3010

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3029

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3031

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3038

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3041

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3046

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3071

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3072

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3073

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3081

if (dc->hwss.program_dmdata_engine)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3082

dc->hwss.program_dmdata_engine(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3085

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3088

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3131

void dcn20_fpga_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3134

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3135

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3136

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3138

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3139

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3163

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3164

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3167

dcn20_init_blank(dc, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3171

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3177

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3187

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3194

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3195

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3197

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3198

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3215

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3216

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3218

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3225

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3226

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3232

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3235

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3241

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3242

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3247

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3248

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3251

void dcn20_set_disp_pattern_generator(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

393

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

406

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

409

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

419

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

429

if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

433

opp = dc->res_pool->opps[opp_id_src0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

442

if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

446

bottom_opp = dc->res_pool->opps[opp_id_src1];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

483

if (hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

559

if (hws->ctx->dc->debug.disable_dpp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

620

struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

641

if (hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

710

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

712

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

716

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

722

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

727

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

735

hws->funcs.plane_atomic_power_down(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

74

void dcn20_log_color_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

750

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

755

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

760

dcn20_plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

77

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

772

void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

774

dcn20_blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

78

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

834

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

836

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

845

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

853

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

854

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

855

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

889

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

895

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

896

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

907

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

919

if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

920

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

958

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

111

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

115

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

119

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

127

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

137

void dcn20_fpga_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

142

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

145

void dcn20_set_disp_pattern_generator(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

154

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

163

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

167

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

171

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

31

void dcn20_log_color_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

38

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

41

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

43

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

44

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

45

bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

47

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

49

void dcn20_program_output_csc(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

57

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

59

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

63

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

67

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

71

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

74

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

77

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

80

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

85

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

86

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

87

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

88

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

90

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

94

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

98

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

141

void dcn20_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

143

dc->hwss = dcn20_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

144

dc->hwseq->funcs = dcn20_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.h

31

void dcn20_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

133

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

138

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

165

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

168

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

177

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

186

ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

187

opp = dc->res_pool->opps[opp_id_src0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

224

void dcn201_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

227

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

228

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

229

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

234

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

235

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

237

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

239

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

241

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

245

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

259

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

264

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

276

dcn201_init_blank(dc, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

326

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

343

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

364

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

375

void dcn201_plane_atomic_disconnect(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

379

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

382

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

413

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

418

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

419

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

422

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

430

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

433

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

436

} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

441

dc, pipe_ctx->stream->output_color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

486

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

50

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

506

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

508

dc->res_pool->mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

511

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

512

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

526

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

530

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

537

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

538

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

552

if (dc->debug.sanity_checks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

553

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

560

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq, &attributes->address);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

573

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

597

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

32

void dcn201_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

35

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

36

void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

37

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

40

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

44

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

132

void dcn201_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

134

dc->hwss = dcn201_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

135

dc->hwseq->funcs = dcn201_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.h

31

void dcn201_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

102

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

103

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

109

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

112

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

113

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

135

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

136

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

144

struct dc_context *dc = abm->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

157

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

162

static void dmub_abm_set_backlight(struct dc_context *dc, uint32_t backlight_pwm_u16_16,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

176

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

184

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

217

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

247

struct dc_context *dc = pipe_ctx->stream->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

260

if (dc->dc->res_pool->dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

283

dmub_abm_set_backlight(dc, backlight_pwm_u16_16, frame_ramp, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

288

bool dcn21_is_abm_supported(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

293

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

67

int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

83

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

88

bool dcn21_s0i3_golden_init_wa(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

90

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

99

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

34

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

37

bool dcn21_s0i3_golden_init_wa(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

40

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

44

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

56

bool dcn21_is_abm_supported(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

146

void dcn21_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

148

dc->hwss = dcn21_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

149

dc->hwseq->funcs = dcn21_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.h

31

void dcn21_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1003

unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1006

(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1030

(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1065

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1079

cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1081

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1098

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1103

bool dcn30_does_plane_fit_in_mall(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1112

unsigned int mall_size = dc->caps.mall_size_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1115

if (dc->debug.mall_size_override)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1116

mall_size = 1024 * 1024 * dc->debug.mall_size_override;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1119

cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1141

void dcn30_hardware_release(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1146

dc_dmub_srv_p_state_delegate(dc, false, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1147

dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1153

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1154

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1159

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1167

if (dc->current_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1168

if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1169

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1170

dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1171

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1172

dc->res_pool->hubbub, true, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1175

void dcn30_set_disp_pattern_generator(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1187

void dcn30_prepare_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1190

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1191

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1195

if (dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1196

if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1197

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1198

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1200

dcn20_prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1202

if (!dc->clk_mgr->clks.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1203

dc_dmub_srv_p_state_delegate(dc, false, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1233

void dcn30_get_underflow_debug_data(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1237

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1256

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

157

dc->caps.color.dpp.input_lut_shared,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

158

dc->caps.color.dpp.icsc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

159

dc->caps.color.dpp.dgam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

160

dc->caps.color.dpp.dgam_rom_caps.srgb,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

161

dc->caps.color.dpp.dgam_rom_caps.bt2020,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

162

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

163

dc->caps.color.dpp.dgam_rom_caps.pq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

164

dc->caps.color.dpp.dgam_rom_caps.hlg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

165

dc->caps.color.dpp.post_csc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

166

dc->caps.color.dpp.gamma_corr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

167

dc->caps.color.dpp.dgam_rom_for_yuv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

168

dc->caps.color.dpp.hw_3d_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

169

dc->caps.color.dpp.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

170

dc->caps.color.dpp.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

225

dc->caps.color.mpc.gamut_remap,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

226

dc->caps.color.mpc.num_3dluts,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

227

dc->caps.color.mpc.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

228

dc->caps.color.mpc.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

258

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

259

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

313

bool dcn30_set_input_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

317

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

360

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

391

bool dcn30_set_output_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

396

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

428

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

438

ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

439

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

443

dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

451

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

456

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

461

dcn30_set_writeback(dc, wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

468

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

478

dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

492

mcif_wb = dc->res_pool->mcif_wb[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

500

warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

507

mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

515

warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

525

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

532

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

533

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

540

dcn30_mmhubbub_warmup(dc, 1, wb_info);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

543

dcn30_set_writeback(dc, wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

552

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

559

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

560

mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

569

dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

573

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

592

ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

602

for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

618

dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

622

ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

623

dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

626

dc->hwss.update_writeback(dc, &wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

629

dc->hwss.enable_writeback(dc, &wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

633

dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

638

void dcn30_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

640

struct abm **abms = dc->res_pool->multiple_abms;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

641

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

642

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

643

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

649

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

65

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

650

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

657

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

658

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

661

if (dc->debug.enable_mem_low_power.bits.dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

663

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

669

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

674

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

679

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

681

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

686

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

702

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

707

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

72

void dcn30_log_color_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

722

dc->link_srv->blank_all_dp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

725

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

733

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

734

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

735

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

736

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

737

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

745

if (!dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

749

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

75

struct dc_context *dc_ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

754

dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

756

dc->hwss.edp_power_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

757

dc->hwss.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

758

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

759

dc->hwss.edp_power_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

76

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

761

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

762

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

767

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

781

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

782

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

790

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

798

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

807

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

808

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

810

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

811

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

814

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

815

!dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

816

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

818

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

819

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

820

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

821

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

822

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

825

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

826

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

827

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

909

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

918

if (!dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

922

if (dc->current_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

926

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

927

if (dc->current_state->stream_status[i].plane_count)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

932

if (i == dc->current_state->stream_count) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

939

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

944

stream = dc->current_state->streams[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

945

plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

965

if (dc->current_state->stream_count == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

967

dc->current_state->stream_status[0].plane_count == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

971

dc->hwss.does_plane_fit_in_mall &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

972

dc->hwss.does_plane_fit_in_mall(dc, plane->plane_size.surface_pitch,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

102

void dcn30_get_underflow_debug_data(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

34

void dcn30_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

36

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

40

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

44

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

48

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

52

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

56

void dcn30_log_color_state(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

62

bool dcn30_set_input_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

68

bool dcn30_set_output_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

75

bool dcn30_does_plane_fit_in_mall(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

81

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

83

void dcn30_hardware_release(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

85

void dcn30_set_disp_pattern_generator(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

93

void dcn30_set_hubp_blank(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

97

void dcn30_prepare_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

151

void dcn30_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

153

dc->hwss = dcn30_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

154

dc->hwseq->funcs = dcn30_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.h

31

void dcn30_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

148

void dcn301_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

150

dc->hwss = dcn301_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

151

dc->hwseq->funcs = dcn301_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.h

31

void dcn301_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

107

if (hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

165

if (hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

50

if (hws->ctx->dc->debug.disable_dpp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

34

void dcn302_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

36

dcn30_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

38

dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

39

dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

40

dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.h

31

void dcn302_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

32

void dcn303_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

34

dcn30_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

36

dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

37

dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

38

dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

39

dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.h

31

void dcn303_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

100

for (i = 0; i < dc->res_pool->stream_enc_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

101

if (dc->res_pool->stream_enc[i]->vpg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

102

dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

103

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

104

dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

109

void dcn31_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

111

struct abm **abms = dc->res_pool->multiple_abms;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

112

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

113

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

114

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

119

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

120

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

123

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

125

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

131

enable_memory_low_power(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

133

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

135

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

140

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

156

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

161

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

179

dc->link_srv->blank_all_dp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

182

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

190

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

193

if (!dc->caps.seamless_odm) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

194

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

195

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

207

dc->link_srv->blank_all_edp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

213

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

214

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

215

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

216

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

225

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

226

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

234

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

243

if (dc->debug.enable_mem_low_power.bits.i2c)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

249

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

258

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

259

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

261

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

262

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

264

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

265

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

267

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

268

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

269

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

271

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

272

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

276

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

277

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

278

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

290

if (hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

293

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

294

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

296

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

297

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

336

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

337

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

338

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

339

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

352

if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

366

if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

398

else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

419

void dcn31_z10_save_init(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

427

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

430

void dcn31_z10_restore(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

438

if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

445

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

453

if (hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

487

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

508

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

512

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

518

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

525

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

529

if (dc->hwseq)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

530

dc->hwseq->wa_state.skip_blank_stream = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

534

dc->hwss.blank_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

535

if (dc->hwseq)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

536

dc->hwseq->wa_state.skip_blank_stream = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

575

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

577

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

585

((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

589

dc->link_srv->set_dsc_enable(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

598

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

601

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

606

if (dc->hwseq)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

607

dc->hwseq->wa_state.skip_blank_stream = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

614

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

618

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

621

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

623

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

63

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

638

dc->res_pool->hubbub->funcs->program_det_size &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

639

dc->res_pool->hubbub->funcs->wait_for_det_apply) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

640

dc->res_pool->hubbub->funcs->program_det_size(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

641

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

643

dc->res_pool->hubbub->funcs->wait_for_det_apply(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

644

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

647

dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

649

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

656

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

657

link_enc_cfg_set_transient_mode(dc, dc->current_state, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

662

if (hws->ctx->dc->debug.hpo_optimization)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

684

static void dmub_abm_set_backlight(struct dc_context *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

70

static void enable_memory_low_power(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

704

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

710

struct dc_context *dc = pipe_ctx->stream->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

72

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

727

dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

75

if (dc->debug.enable_mem_low_power.bits.dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

77

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

83

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

88

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

93

if (dc->debug.enable_mem_low_power.bits.mpc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

94

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

95

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

98

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

33

void dcn31_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

46

void dcn31_z10_restore(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

47

void dcn31_z10_save_init(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

50

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

52

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

56

bool dcn31_is_abm_supported(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

58

void dcn31_init_pipes(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

153

void dcn31_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

155

dc->hwss = dcn31_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

156

dc->hwseq->funcs = dcn31_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.h

31

void dcn31_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

172

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

179

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

210

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

233

if (hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

236

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

237

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

239

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

240

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

287

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

288

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

289

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

290

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

300

if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

314

if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

336

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

364

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

368

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

398

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

404

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

408

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

420

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

425

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

427

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

431

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

457

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

460

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

461

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

462

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

482

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

488

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

493

dc->link_srv->dp_get_encoding_format(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

507

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

509

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

512

link->dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

514

link->dc->hwss.edp_backlight_control(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

527

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

551

if (hws->ctx->dc->debug.disable_dpp_power_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

556

struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

42

void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

44

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

160

void dcn314_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

162

dc->hwss = dcn314_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

163

dc->hwseq->funcs = dcn314_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.h

30

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.h

32

void dcn314_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1002

dc->debug.fams2_config.bits.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1003

if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1005

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1007

dc->debug.force_disable_subvp = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1008

dc->debug.disable_fpo_optimizations = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1016

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1020

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1131

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1161

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1180

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1188

struct dce_hwseq *hws = stream->ctx->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1193

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1222

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1226

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1243

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1250

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1255

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1256

dc_state = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1265

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1270

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1272

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1276

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1299

dc_trigger_sync(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1308

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1322

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1345

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1350

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1351

dc->debug.enable_dp_dig_pixel_rate_div_policy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1373

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1379

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1384

dc->link_srv->dp_get_encoding_format(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1398

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1400

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1403

link->dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1405

link->dc->hwss.edp_backlight_control(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1419

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1428

void dcn32_update_phantom_vp_position(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1435

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1513

void dcn32_update_dsc_pg(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1517

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1520

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1521

struct display_stream_compressor *dsc = dc->res_pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1536

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1538

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1541

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1543

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1549

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1560

hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1562

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1569

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1573

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1575

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1577

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1584

old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1593

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1595

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1619

dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1625

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1632

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1635

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1646

color_space_to_black_color(dc, color_space, &black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1656

if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1661

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1662

if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1663

opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1671

if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1675

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1676

if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1677

bottom_opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

168

if (hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1735

bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1743

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1788

void dcn32_prepare_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1795

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1796

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1800

if (dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1801

if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1802

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1803

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1805

dcn20_prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1808

dc_dmub_srv_p_state_delegate(dc, false, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1810

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1818

void dcn32_interdependent_update_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1825

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1835

dc->hwss.pipe_control_lock(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1837

dc->hwss.pipe_control_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1841

void dcn32_program_outstanding_updates(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1844

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

197

static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

202

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

203

if ((dc->current_state->stream_status[i].plane_count) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

204

(dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

209

if (i == dc->current_state->stream_count)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

220

static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

231

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

237

mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

241

if (dc->debug.force_mall_ss_num_ways > 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

242

num_ways = dc->debug.force_mall_ss_num_ways;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

243

} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

244

num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

252

bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

261

if (!dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

264

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

266

if (dc->current_state->streams[i] != NULL &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

267

dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

268

(dc->current_state->stream_count > 1 || (!dc->current_state->streams[i]->dpms_off &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

269

dc->current_state->stream_status[i].plane_count > 0)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

277

if (dcn32_check_no_memory_request_for_cab(dc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

284

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

293

ways = dcn32_calculate_cab_allocation(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

298

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

299

for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

300

plane = dc->current_state->stream_status[i].plane_states[j];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

311

if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

318

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

335

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

345

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

350

if (!dc->ctx || !dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

353

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

362

dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

371

void dcn32_subvp_pipe_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

384

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

405

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

417

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

423

struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

435

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

444

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

445

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

481

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

522

bool dcn32_set_input_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

526

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

527

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

562

bool dcn32_set_output_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

567

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

600

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

608

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

627

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

629

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

63

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

649

old_stream_status = dc_state_get_stream_status(dc->current_state, old_pipe->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

653

(!old_pipe->stream || (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_MAIN &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

667

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

670

unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

673

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

705

num_ways <= dc->caps.cache_num_ways &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

721

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

724

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

730

hws->funcs.update_mall_sel(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

733

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

749

static void dcn32_initialize_min_clocks(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

751

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

754

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

755

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

756

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

757

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

758

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

761

if (dc->debug.disable_boot_optimizations) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

762

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

769

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

77

struct dc *dc = hws->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

772

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

773

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

774

dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

778

void dcn32_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

780

struct abm **abms = dc->res_pool->multiple_abms;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

781

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

782

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

783

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

789

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

79

if (dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

790

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

797

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

798

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

802

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

807

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

812

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

814

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

818

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

82

if (!dc->debug.enable_double_buffered_dsc_pg_support)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

834

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

839

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

858

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

861

dc->link_srv->blank_all_dp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

869

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

873

if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

874

dc->hwss.enable_accelerated_mode(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

876

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

878

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

879

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

880

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

882

dcn32_initialize_min_clocks(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

891

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

892

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

900

if (!dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

904

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

910

dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

912

dc->hwss.edp_power_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

913

dc->hwss.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

914

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

915

dc->hwss.edp_power_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

919

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

920

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

925

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

939

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

940

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

948

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

956

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

965

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

966

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

968

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

969

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

971

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

972

!dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

973

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

975

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

976

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

977

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

979

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

980

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

982

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

983

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

986

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

987

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

988

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

989

dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

990

dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

991

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

992

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

995

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

996

if (dc->caps.dmub_caps.fams_ver == 2) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

dc->debug.fams2_config.bits.enable &= true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

999

} else if (dc->ctx->dmub_srv->dmub->fw_version <

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

100

void dcn32_update_phantom_vp_position(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

110

void dcn32_update_dsc_pg(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

114

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

116

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

119

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

122

bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

126

void dcn32_prepare_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

129

void dcn32_interdependent_update_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

132

void dcn32_program_outstanding_updates(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

44

bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

46

void dcn32_cab_for_ss_control(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

48

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

53

bool dcn32_set_input_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

60

bool dcn32_set_output_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

64

void dcn32_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

66

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

68

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

70

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

78

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

80

void dcn32_subvp_pipe_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

94

void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

169

void dcn32_hw_sequencer_init_functions(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

171

dc->hwss = dcn32_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

172

dc->hwseq->funcs = dcn32_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.h

31

void dcn32_hw_sequencer_init_functions(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

100

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1003

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

101

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1011

if (dc->caps.sequential_ono) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1012

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1026

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

103

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1035

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1036

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

105

for (i = 0; i < dc->res_pool->stream_enc_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

106

dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

108

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

109

dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1105

for (i = 0; i < dc->link_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1106

if (dc->links[i]->type != dc_connection_none)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1107

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1109

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1111

dc->res_pool->hpo_dp_stream_enc[i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1123

if (dc->caps.sequential_ono) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1124

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1135

for (j = 0; j < dc->res_pool->pipe_count; ++j) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1143

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

116

static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

118

if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1180

void dcn35_hw_block_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1184

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1188

if (dc->debug.ignore_pg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

119

if (dc->res_pool->pg_cntl->funcs->print_pg_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1196

if (!dc->caps.sequential_ono) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1197

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

120

dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1205

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1212

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1257

void dcn35_hw_block_power_up(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1261

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1265

if (dc->debug.ignore_pg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1272

if (!dc->caps.sequential_ono) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1273

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1280

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1287

if (dc->caps.sequential_ono) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1299

void dcn35_root_clock_control(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1303

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1309

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1312

if (dc->hwseq->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1313

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1316

if (dc->hwseq->funcs.dpstream_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1317

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1320

for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1322

if (dc->hwseq->funcs.physymclk_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1323

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1326

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1329

if (dc->res_pool->dccg->funcs->enable_dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1330

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1332

if (dc->res_pool->dccg->funcs->disable_dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1333

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1339

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1342

if (dc->hwseq->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1343

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1346

if (dc->hwseq->funcs.dpstream_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1347

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1350

for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1352

if (dc->hwseq->funcs.physymclk_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1353

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1359

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1364

if (dc->hwss.calc_blocks_to_ungate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1365

dc->hwss.calc_blocks_to_ungate(dc, context, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1367

if (dc->hwss.root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1368

dc->hwss.root_clock_control(dc, &pg_update_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1370

if (dc->hwss.hw_block_power_up)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1371

dc->hwss.hw_block_power_up(dc, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1374

dcn20_prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1376

print_pg_status(dc, __func__, ": after rcg and power up");

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

138

void dcn35_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1380

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1385

print_pg_status(dc, __func__, ": before rcg and power up");

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1387

dcn20_optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1389

if (dc->hwss.calc_blocks_to_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1390

dc->hwss.calc_blocks_to_gate(dc, context, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1392

if (dc->hwss.hw_block_power_down)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1393

dc->hwss.hw_block_power_down(dc, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1395

if (dc->hwss.root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1396

dc->hwss.root_clock_control(dc, &pg_update_state, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1399

print_pg_status(dc, __func__, ": after rcg and power up");

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

140

struct abm **abms = dc->res_pool->multiple_abms;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

141

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

142

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1425

if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1427

struct dc *dc = pipe_ctx[i]->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

143

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1430

if (frame_rate >= 120 && dc->caps.ips_support &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1431

dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

148

print_pg_status(dc, __func__, ": start");

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

150

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1504

const struct dc *dc = pipe_ctx->stream->link->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

151

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1516

if (pix_clk_mhz > dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1547

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1555

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1556

dc->debug.enable_dp_dig_pixel_rate_div_policy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1565

static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

157

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1571

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1583

void dcn35_hardware_release(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1587

dcn35_calc_blocks_to_ungate_for_hw_release(dc, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1589

if (dc->hwss.root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1590

dc->hwss.root_clock_control(dc, &pg_update_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1592

if (dc->hwss.hw_block_power_up)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1593

dc->hwss.hw_block_power_up(dc, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

166

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

168

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

173

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

189

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

194

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

212

dc->link_srv->blank_all_dp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

215

res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

222

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

225

if (!dc->caps.seamless_odm) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

226

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

227

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

239

dc->link_srv->blank_all_edp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

245

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

246

print_pg_status(dc, __func__, ": after init_pipes");

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

248

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

249

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

250

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

251

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

259

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

260

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

267

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

268

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

278

if (dc->debug.enable_mem_low_power.bits.i2c)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

284

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

289

if (dc->debug.disable_mem_low_power) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

292

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

293

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

295

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

296

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

298

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

299

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

303

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

304

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

305

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

307

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

308

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

310

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

311

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

313

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

314

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

315

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

316

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

317

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

320

if (dc->res_pool->pg_cntl) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

321

if (dc->res_pool->pg_cntl->funcs->init_pg_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

322

dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

324

print_pg_status(dc, __func__, ": after init_pg_status");

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

428

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

435

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

466

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

482

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

485

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

486

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

487

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

493

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

496

if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

497

hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

498

hws->ctx->dc->res_pool->dccg, dp_hpo_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

504

if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

507

if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

508

hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

509

hws->ctx->dc->res_pool->dccg, phy_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

518

void dcn35_power_down_on_boot(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

525

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

531

dc->hwseq->funcs.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

532

dc->hwseq->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

533

dc->hwss.edp_power_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

534

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

535

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

536

dc->hwss.edp_power_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

538

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

539

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

543

dc->hwseq->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

544

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

556

if (dc->clk_mgr->funcs->set_low_power_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

557

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

559

if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

560

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

563

bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

565

if (dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

572

for (i = 0; i < dc->current_state->stream_count; ++i) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

573

struct dc_stream_state *stream = dc->current_state->streams[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

605

dc_dmub_srv_apply_idle_power_optimizations(dc, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

610

void dcn35_z10_restore(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

612

if (dc->debug.disable_z10)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

615

dc_dmub_srv_apply_idle_power_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

617

dcn31_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

620

void dcn35_init_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

623

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

624

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

625

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

636

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

637

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

652

hws->funcs.init_blank(dc, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

663

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

665

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

680

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

687

dc->res_pool->mpc->funcs->mpc_init_single_inst(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

688

dc->res_pool->mpc, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

691

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

692

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

693

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

694

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

716

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

731

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

732

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

733

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

734

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

736

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

741

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

755

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

757

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

758

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

759

int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

76

static void enable_memory_low_power(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

762

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

78

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

781

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

782

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

797

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

802

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

809

pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

81

if (dc->debug.enable_mem_low_power.bits.dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

815

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

819

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

83

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

835

if (dc->vm_pa_config.valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

840

apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

841

apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

858

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

862

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

865

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

871

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

876

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

89

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

898

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

900

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

904

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

910

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

922

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

933

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

935

dc->res_pool->hpo_dp_stream_enc[i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

94

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

946

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

966

if (dc->caps.sequential_ono) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

973

for (j = 0; j < dc->res_pool->pipe_count; ++j) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

988

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

989

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

99

if (dc->debug.enable_mem_low_power.bits.mpc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

990

if (dc->links[i]->type != dc_connection_none)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

991

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

995

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

996

struct timing_generator *tg = dc->res_pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

102

void dcn35_hardware_release(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

32

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

48

void dcn35_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

54

void dcn35_power_down_on_boot(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

56

bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

58

void dcn35_z10_restore(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

60

void dcn35_init_pipes(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

61

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

62

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

64

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

66

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

68

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

70

void dcn35_hw_block_power_up(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

72

void dcn35_hw_block_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

74

void dcn35_root_clock_control(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

78

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

82

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

173

void dcn35_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

175

dc->hwss = dcn35_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

176

dc->hwseq->funcs = dcn35_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.h

30

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.h

32

void dcn35_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

103

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

105

if (!pg_cntl || dc->debug.ignore_pg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

108

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

152

void dcn351_hw_block_power_up(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

156

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

158

if (!pg_cntl || dc->debug.ignore_pg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

170

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

38

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

43

dcn35_calc_blocks_to_gate(dc, context, update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

45

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

58

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

63

dcn35_calc_blocks_to_ungate(dc, context, update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

65

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

99

void dcn351_hw_block_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

32

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

34

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

36

void dcn351_hw_block_power_up(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

38

void dcn351_hw_block_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

167

void dcn351_hw_sequencer_construct(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

169

dc->hwss = dcn351_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

170

dc->hwseq->funcs = dcn351_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.h

29

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.h

31

void dcn351_hw_sequencer_construct(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1000

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1023

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1028

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1044

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1046

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1049

link->dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1051

link->dc->hwss.edp_backlight_control(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1064

link->dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1066

link->dc->hwss.edp_power_control(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1070

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1080

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1225

static bool dcn401_check_no_memory_request_for_cab(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1230

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1231

if ((dc->current_state->stream_status[i].plane_count) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1232

(dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1240

static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1251

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1257

mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1261

if (dc->debug.force_mall_ss_num_ways > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1262

num_ways = dc->debug.force_mall_ss_num_ways;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1263

else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1264

num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1271

bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1279

if (!dc->ctx->dmub_srv || !dc->current_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1282

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1284

if (dc->current_state->streams[i] != NULL &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1285

dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1296

if (dcn401_check_no_memory_request_for_cab(dc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1307

ways = dcn401_calculate_cab_allocation(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1312

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1313

for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1314

plane = dc->current_state->stream_status[i].plane_states[j];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1325

if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1340

dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1345

void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

136

void dcn401_init_hw(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1365

if (is_wait_needed && dc->debug.dcc_meta_propagation_delay_us > 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1366

udelay(dc->debug.dcc_meta_propagation_delay_us);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1370

void dcn401_prepare_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1373

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1379

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

138

struct abm **abms = dc->res_pool->multiple_abms;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1383

if (dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1384

if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1385

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1386

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1389

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

139

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1390

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1398

dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

140

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1400

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1404

dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

141

struct resource_pool *res_pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1410

dc->optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1415

if (dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1416

dcn401_fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1417

dcn401_fams2_update_config(dc, context, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1418

dcn401_fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1429

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1433

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1436

if (dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1437

dcn401_fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1438

dcn401_fams2_update_config(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1439

dcn401_fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1445

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1452

if (dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1453

if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1454

context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1455

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1461

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1462

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1466

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1478

void dcn401_fams2_global_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

148

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1485

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

149

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1492

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1497

struct dc *dc = params->fams2_global_control_lock_fast_params.dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1507

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1511

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1515

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

152

dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1520

dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_required);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1523

static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

153

dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1533

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1537

&dc->current_state->res_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1562

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1597

update_dsc_for_odm_change(dc, context, otg_master);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1604

dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1613

struct dce_hwseq *hws = link->dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1622

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1634

void dcn401_hardware_release(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1636

if (!dc->debug.disable_force_pstate_allow_on_hw_release) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1637

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1638

dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1643

if (dc->current_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1644

if ((!dc->clk_mgr->clks.p_state_change_support ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1645

dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1646

dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1647

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1648

dc->res_pool->hubbub, true, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1650

dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1651

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1654

if (dc->current_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1655

dc->clk_mgr->clks.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1656

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1659

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

166

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1660

dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1664

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1668

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1697

void dcn401_interdependent_update_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1705

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

171

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1713

dc->hwss.pipe_control_lock(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1717

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1727

if (dc->scratch.pipes_to_unlock_first[i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1728

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1729

dc->hwss.pipe_control_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1731

dcn401_wait_for_det_buffer_update_under_otg_master(dc, dc->current_state, old_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1736

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1737

if (dc->scratch.pipes_to_unlock_first[i])

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1748

dc->hwss.pipe_control_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

176

if (dc->ctx->dc_bios->fw_info_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

178

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1801

void dcn401_program_outstanding_updates(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1804

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1812

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1819

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

182

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1832

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1834

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1842

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1845

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1857

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1881

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1882

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1900

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1904

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1907

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1909

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1923

hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1925

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1959

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1979

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1983

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1987

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1994

hws->funcs.blank_pixel_data(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

200

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2002

dcn401_program_tg(dc, pipe_ctx, context, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2005

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2009

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2011

dc->hwss.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2013

if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2014

dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2018

if (dc->res_pool->hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2019

dc->res_pool->hubbub->funcs->program_det_size(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2020

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2021

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2022

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2023

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2029

dc->hwss.update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2040

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2049

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

205

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2074

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2086

dc->hwss.set_disp_pattern_generator(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2099

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2105

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2108

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2110

if (resource_is_pipe_topology_changed(dc->current_state, context))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2111

resource_log_pipe_topology_update(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2113

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2114

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2122

dc->hwss.program_triplebuffer(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2123

dc, pipe, pipe->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2128

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2129

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2136

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2137

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2138

dc->res_pool->hubbub, true, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2143

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2144

dc->hwss.detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2150

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2151

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2153

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2156

dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2157

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2160

if (dc->hwseq->funcs.blank_pixel_data)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2168

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2173

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2177

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2180

struct hubbub *hubbub = dc->res_pool->hubbub;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2194

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2195

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2196

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2197

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2199

hws->funcs.plane_atomic_disconnect(dc, dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2200

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2201

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2205

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2211

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2218

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2236

dcn401_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2250

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2257

dc->current_state->stream_status[0].plane_count == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2265

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

227

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2271

struct dce_hwseq *hwseq = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2274

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2276

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2277

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2279

dc->hwss.post_unlock_reset_opp(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2280

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2282

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2284

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2292

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

230

dc->link_srv->blank_all_dp_displays(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2306

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2308

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2328

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2329

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2330

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2333

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2347

if (dc->hwss.apply_update_flags_for_phantom)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2348

dc->hwss.apply_update_flags_for_phantom(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2349

if (dc->hwss.update_phantom_vp_position)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2350

dc->hwss.update_phantom_vp_position(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2351

dcn401_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2369

dc->hwseq->funcs.update_force_pstate(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2375

hwseq->funcs.program_mall_pipe_config(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2379

dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

238

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2385

if (dc->current_state->stream_status[0].plane_count == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2388

struct timing_generator *tg = dc->res_pool->timing_generators[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2390

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2400

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2404

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2407

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2411

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2414

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

242

if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

243

dc->hwss.enable_accelerated_mode(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2435

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2438

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

245

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

247

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

248

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

249

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

251

dcn401_initialize_min_clocks(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

260

dc_allow_idle_optimizations(dc, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

261

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2649

void dcn401_plane_atomic_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2653

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2656

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

269

if (!dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

273

dc_get_edp_links(dc, edp_links, &edp_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

279

dc->hwss.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

281

dc->hwss.edp_power_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

282

dc->hwss.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

283

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

284

dc->hwss.edp_power_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

288

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

289

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

296

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

310

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

311

struct dc_link *link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

319

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

327

if (!dc->debug.disable_clock_gate) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

338

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

339

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

341

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

342

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

344

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

345

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

346

dc->res_pool->hubbub, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

348

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

349

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

351

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

352

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

355

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

356

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

357

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

358

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

359

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

360

dc->debug.fams2_config.bits.enable &=

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

361

dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; // sw & fw fams versions must match for support

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

365

if (dc->clk_mgr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

366

dc->res_pool->funcs->update_bw_bounding_box(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

367

dc->clk_mgr->bw_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

372

static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

379

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

405

void dcn401_populate_mcm_luts(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

413

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

428

dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

47

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

54

void dcn401_initialize_min_clocks(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

56

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

59

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

60

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

602

void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

61

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

616

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

617

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

62

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

623

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

63

if (dc->debug.disable_boot_optimizations) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

64

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

664

bool dcn401_set_output_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

669

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

71

if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

72

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

720

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

74

clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

760

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

762

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

77

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

780

enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

783

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

784

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

785

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

801

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

803

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

81

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

815

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

82

dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

821

if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

822

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

825

if (dc->debug.enable_hblank_borrow) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

83

dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

856

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

917

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

92

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

923

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

953

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

954

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

962

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

969

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

982

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

983

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

984

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

993

if (dc->hwss.program_dmdata_engine)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

994

dc->hwss.program_dmdata_engine(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

997

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

101

void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

102

void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

103

bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

109

void dcn401_plane_atomic_power_down(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

112

void dcn401_initialize_min_clocks(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

14

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

36

void dcn401_init_hw(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

40

bool dcn401_set_output_transfer_func(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

43

void dcn401_trigger_3dlut_dma_load(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

50

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

52

void dcn401_populate_mcm_luts(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

64

bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

66

void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

69

void dcn401_prepare_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

73

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

76

void dcn401_fams2_global_control_lock(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

79

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

82

void dcn401_hardware_release(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

83

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

86

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

87

void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

88

void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

90

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

94

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

97

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

149

void dcn401_hw_sequencer_init_functions(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

151

dc->hwss = dcn401_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

152

dc->hwseq->funcs = dcn401_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.h

10

void dcn401_hw_sequencer_init_functions(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.h

8

struct dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

109

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

115

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

147

const struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

152

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

211

void (*hardware_release)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

218

void (*init_hw)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

219

void (*power_down_on_boot)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

220

void (*enable_accelerated_mode)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

222

enum dc_status (*apply_ctx_to_hw)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

224

void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

225

void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

226

void (*apply_ctx_for_surface)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

229

void (*program_front_end_for_ctx)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

231

void (*wait_for_pending_cleared)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

233

void (*post_unlock_program_front_end)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

235

void (*update_plane_addr)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

239

void (*wait_for_mpcc_disconnect)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

245

void (*program_triplebuffer)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

248

void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

252

void (*pipe_control_lock)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

254

void (*interdependent_update_lock)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

258

void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

265

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

269

void (*enable_per_frame_crtc_position_reset)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

271

void (*enable_timing_synchronization)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

275

void (*enable_vblanks_synchronization)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

278

void (*setup_periodic_interrupt)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

294

void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

295

bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

296

void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

316

void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

319

void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

323

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

326

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

331

void (*update_writeback)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

334

void (*enable_writeback)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

337

void (*disable_writeback)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

341

enum dc_status (*set_clock)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

344

void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

346

void (*optimize_pwr_state)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

348

void (*exit_optimized_pwr_state)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

350

void (*calculate_pix_rate_divider)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

359

void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

362

void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

363

void (*log_color_state)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

365

void (*get_hw_state)(struct dc *dc, char *pBuf,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

367

void (*clear_status_bits)(struct dc *dc, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

395

void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

398

bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

400

bool (*does_plane_fit_in_mall)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

405

void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

406

void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

407

void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

408

void (*subvp_pipe_control_lock)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

416

void (*z10_restore)(const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

417

void (*z10_save_init)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

418

bool (*is_abm_supported)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

421

void (*set_disp_pattern_generator)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

428

void (*blank_phantom)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

432

void (*update_visual_confirm_color)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

435

void (*update_phantom_vp_position)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

440

void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

442

void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

444

void (*hw_block_power_up)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

446

void (*hw_block_power_down)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

448

void (*root_clock_control)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

450

bool (*is_pipe_topology_transition_seamless)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

453

void (*wait_for_dcc_meta_propagation)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

455

void (*fams2_global_control_lock)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

458

void (*fams2_update_config)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

463

void (*program_outstanding_updates)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

471

void (*enable_plane)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

474

void (*update_dchubp_dpp)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

477

void (*post_unlock_reset_opp)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

479

void (*get_underflow_debug_data)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

485

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

510

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

519

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

53

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

533

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

538

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

547

void hwss_execute_sequence(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

551

void hwss_build_fast_sequence(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

560

void hwss_wait_for_all_blank_complete(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

563

void hwss_wait_for_odm_update_pending_complete(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

566

void hwss_wait_for_no_pipes_pending(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

569

void hwss_wait_for_outstanding_hw_updates(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

572

void hwss_process_outstanding_hw_updates(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

59

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

70

const struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

76

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

81

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

103

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

106

void (*setup_vupdate_interrupt)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

108

bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

109

void (*init_blank)(struct dc *dc, struct timing_generator *tg);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

111

void (*bios_golden_init)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

112

void (*plane_atomic_power_down)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

115

void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

141

void (*update_odm)(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

143

void (*program_all_writeback_pipes_in_tree)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

146

bool (*s0i3_golden_init_wa)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

148

void (*verify_allow_pstate_change_high)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

149

void (*program_pipe)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

163

void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

165

void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

166

void (*update_force_pstate)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

167

void (*update_mall_sel)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

171

void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

177

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

179

void (*reset_back_end_for_pipe)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

182

void (*populate_mcm_luts)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

187

void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

188

void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

76

void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

77

void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

78

void (*init_pipes)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

79

void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

80

void (*plane_atomic_disconnect)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

83

void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

84

bool (*set_input_transfer_func)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

87

bool (*set_output_transfer_func)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

90

void (*power_down)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

93

bool (*enable_display_power_gating)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

97

void (*blank_pixel_data)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

100

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

109

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

121

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

136

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

160

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

165

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

178

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

183

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

189

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

205

struct dc *dc, struct dc_state *state,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

209

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

223

unsigned int (*get_max_hw_cursor_size)(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

85

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

89

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

94

struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

97

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

36

struct dc;

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

37

struct dc;

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

623

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

628

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

634

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

637

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

640

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

644

void dcn_bw_sync_calcs_and_dml(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

367

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

369

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

465

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

469

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

76

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

104

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

108

bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

111

bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

118

void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state);

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

39

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

58

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

78

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

83

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

88

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

93

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h

97

struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

133

void (*get_cur_res_map)(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

134

void (*restore_res_map)(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

148

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

160

void (*blank_all_dp_displays)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

161

void (*blank_all_edp_displays)(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

322

void (*dp_set_preferred_link_settings)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

325

void (*dp_set_preferred_training_settings)(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

84

const struct dc *dc;

sys/dev/pci/drm/amd/display/dc/inc/resource.h

102

struct resource_pool *dc_create_resource_pool(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

106

void dc_destroy_resource_pool(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

109

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

120

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

480

void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

578

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

583

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

606

void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

609

void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

613

void reset_sync_context_for_pipe(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

617

uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

625

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

636

enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

649

void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

98

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/inc/soc_and_ip_translator.h

12

void (*get_soc_bb)(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

207

struct dc *dc = irq_service->ctx->dc;

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

209

dc_interrupt_to_irq_source(irq_service->ctx->dc,

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

219

tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

1014

dm_helpers_dp_mst_update_branch_bandwidth(dc->ctx, link);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

1018

dp_set_preferred_link_settings(dc, &link->preferred_link_setting, link);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

102

if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

103

link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

110

link->dc->link_srv->dp_get_encoding_format(&pipes[i]->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

127

if (link->dc->config.disable_hbr_audio_dp2 &&

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

129

link->dc->link_srv->dp_is_128b_132b_signal(pipes[i]))

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

137

if (was_hpo_acquired != is_hpo_acquired && link->dc->hwss.setup_hpo_hw_control)

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

138

link->dc->hwss.setup_hpo_hw_control(link->dc->hwseq, is_hpo_acquired);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

154

dc_update_planes_and_stream(dc, NULL, 0, streams_on_link[i], &stream_update);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

195

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

349

test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

355

test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

495

resource_build_test_pattern_params(&link->dc->current_state->res_ctx,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

512

} else if (link->dc->hwss.set_disp_pattern_generator) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

528

link->dc->hwss.set_disp_pattern_generator(link->dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

552

} else if (link->dc->hwss.set_disp_pattern_generator) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

560

link->dc->hwss.set_disp_pattern_generator(link->dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

655

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

691

link->dc->hwss.unblank_stream(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

70

struct dc_state *state = link->dc->current_state;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

729

link->dc->hwss.blank_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

74

bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

81

struct dc *dc = (struct dc *)link->dc;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

83

needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) !=

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

84

link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings));

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

914

link->dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

94

link->dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

953

void dp_set_preferred_link_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

973

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

994

void dp_set_preferred_training_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.h

36

void dp_set_preferred_link_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.h

39

void dp_set_preferred_training_settings(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

110

link->dp_trace.detect_lt_trace.timestamps.start = dm_get_timestamp(link->dc->ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

112

link->dp_trace.commit_lt_trace.timestamps.start = dm_get_timestamp(link->dc->ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

119

link->dp_trace.detect_lt_trace.timestamps.end = dm_get_timestamp(link->dc->ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

121

link->dp_trace.commit_lt_trace.timestamps.end = dm_get_timestamp(link->dc->ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

152

link->dp_trace.edp_trace_power_timestamps.poweroff = dm_get_timestamp(link->dc->ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

154

link->dp_trace.edp_trace_power_timestamps.poweron = dm_get_timestamp(link->dc->ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

169

if (link != NULL && link->dc->debug.enable_driver_sequence_debug)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

106

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

148

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

160

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

177

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

187

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

195

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

205

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

213

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

223

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

239

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

275

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

295

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

330

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

54

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

64

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

84

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

107

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

120

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

132

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

139

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

150

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

152

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

154

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

156

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

158

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

52

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

54

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

56

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

58

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

60

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

62

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

64

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

66

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

68

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

70

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

100

uint8_t fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

117

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

128

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

132

if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

143

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

167

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

168

return link->is_dig_mapping_flexible && link->dc->res_pool->funcs->link_encs_assign;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

44

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

50

status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

69

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

76

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

95

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

99

if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

103

link->dc->link_srv->dp_trace_source_sequence(link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

118

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

119

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

120

link->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

142

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

143

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

144

link->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

155

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

55

hpo_dp_stream_encoder->ctx->dc->link_srv->dp_link_bandwidth_kbps(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

100

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

102

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

104

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

108

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

111

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

115

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

118

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

139

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

169

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

62

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

64

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

66

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

68

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

70

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

92

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

94

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

96

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

98

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1115

link->ctx->dc->debug.hdmi20_disable = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1197

if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1198

dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1256

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1257

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1258

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1282

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1283

link->dc->hwss.edp_power_control(link, false);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

209

&link->dc->res_pool->audio_support;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

307

.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

590

struct audio_support *audio_support = &link->dc->res_pool->audio_support;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

606

if (link->dc->debug.disable_dp_plus_plus_wa &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

700

!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

708

!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

752

static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

758

for (i = 0; i < dc->current_state->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

759

if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

768

static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

770

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

771

clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

774

static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

776

clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

784

should_prepare_phy_clocks_for_link_verification(link->dc, reason);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

787

prepare_phy_clocks_for_destructive_link_verification(link->dc);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

801

restore_phy_clocks_for_destructive_link_verification(link->dc);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

825

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

827

link->dc->res_pool->funcs->link_encs_assign &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

829

link->ctx->dc,

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

837

if (link->dc->debug.skip_detection_link_training ||

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

840

!link->dc->config.enable_dpia_pre_training)) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

877

struct audio_support *aud_support = &link->dc->res_pool->audio_support;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

881

struct dc *dc = dc_ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

895

(!link->dc->config.allow_edp_hotplug_detection)) &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

959

if (dc->config.enable_mipi_converter_optimization &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

964

dc->config.edp_no_power_sequencing = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

100

void link_blank_all_edp_displays(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

106

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

107

if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

108

(!dc->links[i]->edp_sink_present))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

112

status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

116

link_blank_dp_stream(dc->links[i], true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

123

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

134

for (j = 0; j < dc->res_pool->stream_enc_count; j++) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

135

if (fe == dc->res_pool->stream_enc[j]->id) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

136

dc->res_pool->stream_enc[j]->funcs->dp_blank(link,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

137

dc->res_pool->stream_enc[j]);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

143

if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

153

struct dc_state *state = link->dc->current_state;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

175

dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1928

link->dc->hwss.edp_power_control(link, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1949

link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1951

link->dc->hwss.disable_link_output(link, link_res, signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1973

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2024

dc->hwss.enable_tmds_link_output(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2071

!link->dc->config.enable_dpia_pre_training)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2080

link->dc->debug.set_mst_en_for_sst) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2090

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2091

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2092

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2170

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2177

dc->hwss.enable_lvds_link_output(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2218

link->dc->hwss.enable_dp_link_output(link,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2348

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2377

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2380

dc->hwss.blank_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2427

dc->hwss.disable_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2429

dc->hwss.disable_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2447

if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2459

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2490

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2521

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2533

dc->hwss.enable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2624

dc->hwss.enable_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2656

dc->hwss.unblank_stream(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2666

dc->hwss.enable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

333

cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

672

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

707

pipe_ctx->stream->link->dc, link_enc->transmitter);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

729

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

734

dc->hwss.set_avmute(pipe_ctx, enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

77

void link_blank_all_dp_displays(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

774

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

781

result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

787

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

794

result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

808

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

812

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

83

for (i = 0; i < dc->link_count; i++) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

84

if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

85

(dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

89

dp_retrieve_lttpr_cap(dc->links[i]);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

91

status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

95

link_blank_dp_stream(dc->links[i], true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

35

void link_blank_all_dp_displays(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

36

void link_blank_all_edp_displays(struct dc *dc);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

397

link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

398

link->dc->res_pool->dig_link_enc_count--;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

462

struct dc_bios *bios = init_params->dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

473

link->dc = init_params->dc;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

502

if (link->dc->res_pool->funcs->link_init)

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

503

link->dc->res_pool->funcs->link_init(link);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

546

if (!(!link->dc->config.smart_mux_version || dc_ctx->dc_edp_id_count == 0))

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

552

if (!link->dc->config.allow_edp_hotplug_detection

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

556

switch (link->dc->config.allow_edp_hotplug_detection) {

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

625

link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

639

link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

640

link->dc->res_pool->dig_link_enc_count++;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

644

if (link->dc->res_pool->funcs->panel_cntl_create &&

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

651

link->dc->res_pool->funcs->panel_cntl_create(

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

773

link->dc = init_params->dc;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

813

if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

814

link->dpia_preferred_eng_id = link->dc->res_pool->funcs->get_preferred_eng_id_dpia(link->ddc_hw_inst);

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

100

for (i = 0; i < dc->caps.max_links; i++) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

102

link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

41

pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

52

void link_get_cur_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

60

if (dc->caps.dp_hpo) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

61

for (i = 0; i < dc->caps.max_links; i++) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

62

link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

75

void link_restore_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

83

if (dc->caps.dp_hpo) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

84

available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

86

for (i = 0; i < dc->caps.max_links; i++) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

88

link = dc->links[i];

sys/dev/pci/drm/amd/display/dc/link/link_resource.h

28

void link_get_cur_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/link/link_resource.h

29

void link_restore_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

392

enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_validation.h

34

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

379

command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

405

if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

509

!ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

527

if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

528

ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1223

if (link->dc->caps.dp_hdmi21_pcon_support) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1386

if (!link->dc->vendor_signature.is_valid) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1437

link->dc->caps.min_horizontal_blanking_period != 0) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1439

uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1452

link->dc->caps.min_horizontal_blanking_period,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1462

link->dc->vendor_signature.data.raw,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1463

sizeof(link->dc->vendor_signature.data.raw));

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1494

link->dc, link->link_enc->transmitter);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1495

if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1583

bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1585

if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1996

link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2209

struct resource_context *res_ctx = &link->dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2210

struct resource_pool *res_pool = link->dc->res_pool;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2218

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2247

struct resource_context *res_ctx = &link->dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2248

struct resource_pool *res_pool = link->dc->res_pool;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2252

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2292

if (!link->dc->debug.ignore_cable_id &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2331

link->dc->debug.disable_uhbr)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2417

link->dc->debug.usbc_combo_phy_reset_wa)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

285

struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

343

struct resource_context *res_ctx = &link->dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

344

struct resource_pool *res_pool = link->dc->res_pool;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

347

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

370

|| !link->dc->caps.edp_dsc_support))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

509

if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

653

link->dc->debug.force_dp2_lt_fallback_method)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

228

if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

250

if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

268

struct dc_state *state = link->dc->current_state;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

287

link_set_dpms_on(link->dc->current_state, pipes[i]);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

450

!link->dc->config.enable_dpia_pre_training)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

149

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

184

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

66

link->dc->hwss.enable_dp_link_output(link, link_res, signal,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

75

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

82

dc->hwss.disable_link_output(link, link_res, signal);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

87

if (dc->clk_mgr->funcs->notify_link_rate_change)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

88

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1614

link->ctx->dc->debug_data.ltFailCount++;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1680

if (!link->dc->config.consolidated_dpia_dp_lt && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1734

!link->dc->config.enable_dpia_pre_training) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

709

if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_TRANSPARENT) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

711

} else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_TRANSPARENT) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

713

} else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_LTTPR) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

784

if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

813

if (!link->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

925

const struct dc *dc = link->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

927

enum dp_link_encoding encoding = dc->link_srv->dp_get_encoding_format(&lt_settings->link_settings);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

203

if (link->dc->debug.legacy_dp2_lt) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

158

bool vbios_lttpr_force_non_transparent = link->dc->caps.vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

159

bool vbios_lttpr_aware = link->dc->caps.vbios_lttpr_aware;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

174

if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

175

link->dc->caps.extended_aux_timeout_support) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

242

if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

434

if (link->ctx->dc->work_arounds.lt_early_cr_pattern)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

925

if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

967

if (!link->dc->config.consolidated_dpia_dp_lt)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

985

dc_process_dmub_dpia_set_tps_notification(link->ctx->dc, link->link_index, pattern);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

125

if (link->ctx->dc->work_arounds.lt_early_cr_pattern)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

229

pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

233

pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1016

dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1018

replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1023

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1031

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1037

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1092

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1093

struct dmub_replay *replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1101

if (dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1115

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1116

struct dmub_replay *replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1122

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1136

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1137

struct dmub_replay *replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1140

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1157

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1158

struct dmub_replay *replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1161

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1184

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1188

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1203

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1204

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1230

if (link->dc->caps.is_apu)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1232

if (!link->dc->config.smart_mux_version)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1238

static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1284

if (link->dc->config.use_assr_psp_message) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1285

edp_set_assr_enable(link->dc, link, link_res, enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

169

!link->dc->caps.dmub_caps.aux_backlight_support) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

403

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

405

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

406

if (link->dc->hwss.edp_backlight_control)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

407

link->dc->hwss.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

414

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

415

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

416

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

419

if (link->dc->hwss.edp_backlight_control)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

420

link->dc->hwss.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

429

if (link->dc->hwss.edp_backlight_control)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

430

link->dc->hwss.edp_backlight_control(link, false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

433

if (!link->dc->config.edp_no_power_sequencing)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

434

link->dc->hwss.edp_power_control(link, false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

440

if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

441

link->dc->hwss.edp_wait_for_T12(link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

534

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

538

if (dc->current_state->res_ctx.pipe_ctx[i].stream) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

539

if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

540

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

552

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

577

dc->hwss.set_backlight_level(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

587

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

588

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

589

struct dmub_psr *psr = dc->res_pool->psr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

595

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

620

dc_z10_restore(dc);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

635

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

636

struct dmcu *dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

637

struct dmub_psr *psr = dc->res_pool->psr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

640

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

692

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

732

dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

733

dmcu = dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

734

psr = dc->res_pool->psr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

739

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

800

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

806

dc->current_state->res_ctx.

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

834

link->dc->res_pool->timing_generator_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

854

if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

910

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

911

struct dmub_psr *psr = dc->res_pool->psr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

914

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

925

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

926

struct dmub_psr *psr = dc->res_pool->psr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

939

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

940

struct dmub_replay *replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

946

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

972

struct dc *dc = link->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

973

struct dmub_replay *replay = dc->res_pool->replay;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

977

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

990

struct dc *dc;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

412

if (mpc->ctx->dc->debug.cm_in_bypass) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

417

if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

439

if (mpc->ctx->dc->debug.cm_in_bypass) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1297

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1458

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

350

if (mpc->ctx->dc->debug.cm_in_bypass) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

385

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

834

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

845

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

878

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

272

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

52

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

695

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

76

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

80

} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

986

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

146

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

217

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

165

oppn10->base.ctx->dc->debug.force_chroma_subsampling_1tap;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

373

!opp->ctx->dc->debug.force_chroma_subsampling_1tap &&

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

346

struct dc *dc = optc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

348

if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

349

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

253

struct dc *dc = optc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

255

if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

256

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

221

if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

254

if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

278

struct dc *dc = optc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

280

if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

281

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

531

optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

294

struct dc *dc = optc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

296

if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams)

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

298

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

319

struct dc *dc = optc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

323

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

336

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

386

struct dc *dc = optc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

388

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

390

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

396

} else if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams) {

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

398

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

182

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

183

pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

184

pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

185

pg_cntl->ctx->dc->idle_optimizations_allowed;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

258

if (pg_cntl->ctx->dc->debug.ignore_pg ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

259

pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

260

pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

306

if (pg_cntl->ctx->dc->debug.ignore_pg ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

307

pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

350

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

360

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

370

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

388

if (pg_cntl->ctx->dc->debug.ignore_pg ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

389

pg_cntl->ctx->dc->debug.disable_optc_power_gate ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

390

pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

402

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

403

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

434

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

444

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

477

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

487

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

516

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

52

if (pg_cntl->ctx->dc->debug.ignore_pg)

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

83

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

84

pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

85

pg_cntl->ctx->dc->idle_optimizations_allowed;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1001

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1005

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1075

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1087

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1088

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1089

dc->caps.i2c_speed_in_khz_hdcp = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1090

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1091

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1092

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1093

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1094

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1095

dc->debug = debug_defaults;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1160

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1162

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1163

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1165

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1170

dce100_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1181

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1189

if (dce100_resource_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

689

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

824

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

841

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

848

const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

850

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

869

if (dc->ctx->dce_version == DCE_VERSION_6_0 ||

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

870

dc->ctx->dce_version == DCE_VERSION_6_4)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

902

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

912

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

918

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

921

result = resource_map_clock_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

924

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

34

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

40

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

45

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

49

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

54

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1093

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1103

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1109

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1112

result = resource_map_clock_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1116

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1128

struct dc *dc = stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1129

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1146

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1148

struct dc_bios *dcb = dc->ctx->dc_bios;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1151

dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1181

color_space_to_black_color(dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1277

ctx->dc->caps.max_slave_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1278

ctx->dc->caps.max_slave_yuv_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1279

ctx->dc->caps.max_slave_rgb_planes = 0;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1284

static void bw_calcs_data_update_from_pplib(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1290

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1294

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1296

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1298

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1300

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1302

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1304

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1306

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1308

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1310

dc->sclk_lvls = clks;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1314

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1317

dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1319

dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1321

dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1326

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1330

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1332

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1335

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1351

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1356

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1371

dc->caps.max_downscale_ratio = 150;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1372

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1373

dc->caps.i2c_speed_in_khz_hdcp = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1374

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1375

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1376

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1377

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1378

dc->debug = debug_defaults;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1438

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1504

if (dc->config.fbc_support)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1505

dc->fbc_compressor = dce110_compressor_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1510

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1515

dce110_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1517

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1520

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1522

dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1524

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1526

bw_calcs_data_update_from_pplib(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1537

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1546

if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

57

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

733

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

941

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

951

dc->res_pool->underlay_pipe_index))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

964

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

975

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

976

dc->bw_dceip,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

977

dc->bw_vbios,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

979

dc->res_pool->pipe_count,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

990

if (memcmp(&dc->current_state->bw_ctx.bw.dce,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.h

45

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1014

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1020

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1023

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1027

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1033

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1062

static void bw_calcs_data_update_from_pplib(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1070

if (!dc->bw_vbios)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1073

if (dc->bw_vbios->memory_type == bw_def_hbm)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1080

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1086

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1090

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1092

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1094

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1096

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1098

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1100

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1102

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1104

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1109

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1113

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1115

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1118

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1126

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1128

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1130

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1132

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1134

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1136

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1138

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1140

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1145

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1154

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1156

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1159

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1210

dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1225

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1229

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1242

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1243

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1244

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1245

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1246

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1247

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1248

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1249

dc->debug = debug_defaults;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1322

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1393

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1397

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1399

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1400

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1403

dce112_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1405

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1407

bw_calcs_data_update_from_pplib(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1418

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1426

if (dce112_resource_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

63

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

709

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

870

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

887

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

898

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

899

dc->bw_dceip,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

900

dc->bw_vbios,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

902

dc->res_pool->pipe_count,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

911

if (memcmp(&dc->current_state->bw_ctx.bw.dce,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

959

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

974

dc->res_pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

978

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

987

dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

36

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

39

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

46

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

51

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1048

dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1061

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1067

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1083

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1084

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1085

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1086

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1087

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1088

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1089

dc->caps.psp_setup_panel_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1090

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1091

dc->debug = debug_defaults;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1157

irq_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1252

if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1256

if (!dce120_hw_sequencer_create(dc))

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1259

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1261

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1262

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1264

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1266

bw_calcs_data_update_from_pplib(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1268

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1269

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1271

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1274

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1291

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1299

if (dce120_resource_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

455

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

564

static bool dce120_hw_sequencer_create(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

569

dce120_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

665

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

667

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

921

static void bw_calcs_data_update_from_pplib(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

934

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

948

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

950

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

952

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

954

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

956

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

958

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

960

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

962

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

967

dc->ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

989

if (dc->bw_vbios->memory_type == bw_def_hbm)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

992

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

994

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

997

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.h

36

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1046

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1048

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1049

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1051

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1053

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1058

dce60_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1069

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1077

if (dce60_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1087

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1091

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1106

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1107

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1108

dc->caps.max_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1109

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1176

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1244

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1246

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1247

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1249

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1251

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1256

dce60_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1267

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1275

if (dce61_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1285

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1289

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1304

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1305

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1306

dc->caps.max_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1307

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1373

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1441

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1443

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1444

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1446

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1448

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1453

dce60_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1464

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1472

if (dce64_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

540

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

889

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

893

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

908

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

909

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

910

dc->caps.max_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

911

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

912

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

978

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.h

36

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.h

40

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.h

44

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1056

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1058

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1059

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1061

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1063

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1068

dce80_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1079

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1087

if (dce80_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1097

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1101

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1116

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1117

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1118

dc->caps.i2c_speed_in_khz_hdcp = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1119

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1120

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1121

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1188

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1256

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1258

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1259

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1261

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1263

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1268

dce80_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1279

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1287

if (dce81_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1297

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1301

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1316

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1317

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1318

dc->caps.i2c_speed_in_khz_hdcp = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1319

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1320

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1321

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1322

dc->debug = debug_defaults;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1385

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1453

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1455

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1456

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1458

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1460

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1465

dce80_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1476

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1484

if (dce83_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

546

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

895

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

899

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

914

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

915

dc->caps.i2c_speed_in_khz = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

916

dc->caps.i2c_speed_in_khz_hdcp = 40;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

917

dc->caps.max_cursor_size = 128;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

918

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

919

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

920

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

921

dc->debug = debug_defaults;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

988

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.h

36

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.h

40

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.h

44

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1047

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1061

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1067

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1070

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1074

result = build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1110

static bool dcn10_get_dcc_compression_cap(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1114

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1115

dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1130

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1137

voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1153

static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1205

dc->dcn_soc->number_of_channels == 1)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1314

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1319

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1346

if (dc->ctx->dce_version == DCN_VERSION_1_01)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1348

dc->caps.max_video_width = 3840;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1349

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1350

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1351

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1352

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1353

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1354

dc->caps.max_slave_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1355

dc->caps.max_slave_yuv_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1356

dc->caps.max_slave_rgb_planes = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1357

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1358

dc->caps.post_blend_color_processing = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1359

dc->caps.extended_aux_timeout_support = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1362

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1365

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1366

dc->caps.color.dpp.input_lut_shared = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1367

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1368

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1369

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1370

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1371

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1372

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1373

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1374

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1375

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1376

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1378

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1379

dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1380

dc->caps.color.dpp.ogam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1381

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1382

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1383

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1384

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1385

dc->caps.color.dpp.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1388

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1389

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1390

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1391

dc->caps.color.mpc.ogam_ram = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1392

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1393

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1394

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1395

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1396

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1397

dc->caps.color.mpc.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1399

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1400

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1419

if (dc->ctx->dce_version == DCN_VERSION_1_0) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1428

if (dc->ctx->dce_version == DCN_VERSION_1_01)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1465

dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1466

memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1467

memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1470

dcn10_resource_construct_fp(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1473

if (!dc->config.is_vmin_only_asic)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1474

if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1475

switch (dc->ctx->asic_id.pci_revision_id) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1485

dc->config.is_vmin_only_asic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1499

dc->debug.az_endpoint_mute_only = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1502

if (!dc->debug.disable_pplib_clock_request) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1516

dcn_bw_update_from_pplib_fclks(dc, &fclks);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1531

dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1538

dcn_bw_sync_calcs_and_dml(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1539

if (!dc->debug.disable_pplib_wm_range) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1540

dc->res_pool = &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1543

dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1546

dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1551

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1636

dc->dml.ip.max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1637

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1653

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1657

dcn10_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1658

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1660

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1661

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1663

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1676

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1684

if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

631

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

35

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

47

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1190

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1192

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1224

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1225

struct dce_hwseq *hws = dc->hwseq;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1232

if (!dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1293

struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1310

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1325

void dcn20_acquire_dsc(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1331

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1332

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1376

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1384

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1396

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1410

static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1422

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1433

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1437

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1440

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1444

result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1447

result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1453

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1457

result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1479

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1485

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1524

dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1594

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1605

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1643

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1648

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1678

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1685

if (dc && primary_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1695

if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1696

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1703

dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1704

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1718

for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1719

if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1720

&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1741

for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1757

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1763

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1781

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1792

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1816

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1825

bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1830

if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1832

} else if (dc->debug.force_single_disp_pipe_split)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1835

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1855

if (plane_count > dc->res_pool->pipe_count / 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1859

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1877

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1896

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1900

&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1919

if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1923

if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2004

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2021

dcn20_merge_pipes_for_validate(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2024

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2039

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2045

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2055

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2058

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2062

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2079

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2089

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2092

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2095

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2109

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2127

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2133

pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2138

voltage_supported = dcn20_validate_bandwidth_fp(dc, context, validate_mode, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2172

bool dcn20_get_dcc_compression_cap(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2176

if (dc->res_pool->hubbub->funcs->get_dcc_compression_cap)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2177

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2178

dc->res_pool->hubbub, input, output);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2337

static bool init_soc_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2341

get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2343

get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2345

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2374

dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2386

dcn20_patch_bounding_box(dc, loaded_bb);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2393

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2397

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2424

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2425

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2426

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2427

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2428

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2429

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2431

dc->caps.max_slave_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2432

dc->caps.max_slave_yuv_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2433

dc->caps.max_slave_rgb_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2434

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2435

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2436

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2437

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2440

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2441

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2442

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2443

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2444

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2445

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2446

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2447

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2448

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2449

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2450

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2451

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2453

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2454

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2456

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2457

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2458

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2459

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2460

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2461

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2463

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2464

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2465

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2466

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2467

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2468

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2469

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2470

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2471

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2472

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2474

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2476

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2477

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2480

dc->work_arounds.dedcn20_305_wa = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2483

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2484

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2559

if (!init_soc_bounding_box(dc, pool)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2565

dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2567

if (!dc->debug.disable_pplib_wm_range) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2610

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2715

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2719

dcn20_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2727

if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2728

dc->hwseq->funcs.enable_power_gating_plane = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2729

dc->debug.disable_dpp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2730

dc->debug.disable_hubp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2734

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2736

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2737

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2739

dc->caps.max_odm_combine_factor = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2741

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2743

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2744

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2746

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2749

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2765

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2773

if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

798

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

118

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

122

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

124

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

127

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

135

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

142

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

146

void dcn20_acquire_dsc(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

150

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

155

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

163

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

164

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

165

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

166

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

35

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

50

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

76

bool dcn20_get_dcc_compression_cap(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1029

static bool dcn201_get_dcc_compression_cap(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1033

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1034

dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1039

static void dcn201_populate_dml_writeback_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1044

dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1088

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1092

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1106

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1107

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1108

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1109

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1110

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1111

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1113

dc->caps.max_slave_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1114

dc->caps.max_slave_yuv_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1115

dc->caps.max_slave_rgb_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1116

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1117

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1118

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1121

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1122

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1123

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1124

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1125

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1126

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1127

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1128

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1129

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1130

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1131

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1132

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1134

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1135

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1137

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1138

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1139

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1140

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1141

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1142

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1144

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1145

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1146

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1147

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1148

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1149

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1150

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1151

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1152

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1153

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1155

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1158

dc->work_arounds.no_connect_phy_config = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1159

dc->work_arounds.dedcn20_305_wa = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1196

dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1199

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1277

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1281

dcn201_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1283

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1285

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1286

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1288

dc->caps.max_odm_combine_factor = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1290

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1303

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1311

if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

690

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

39

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

48

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1355

if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1386

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1390

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1409

dc->caps.max_downscale_ratio = 200;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1410

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1411

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1412

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1413

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1414

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1416

dc->caps.max_slave_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1417

dc->caps.max_slave_yuv_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1418

dc->caps.max_slave_rgb_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1419

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1420

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1421

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1422

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1423

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1426

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1427

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1428

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1429

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1430

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1431

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1432

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1433

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1434

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1435

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1436

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1437

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1439

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1440

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1442

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1443

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1444

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1445

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1446

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1447

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1449

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1450

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1451

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1452

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1453

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1454

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1455

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1456

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1457

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1458

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1460

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1462

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1463

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1466

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1467

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1517

if (!dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1528

dc->debug.dmub_command_table = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1531

if (dc->config.disable_dmcu) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1541

if (dc->config.disable_dmcu)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1562

dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1564

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1676

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1680

dcn21_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1682

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1684

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1685

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1687

dc->caps.max_odm_combine_factor = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1689

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1702

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1710

if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

533

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

747

if (pool->base.abm->ctx->dc->config.disable_dmcu)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

766

bool dcn21_fast_validate_bw(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

783

dcn20_merge_pipes_for_validate(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

786

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

819

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

821

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

845

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

855

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

858

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

862

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

874

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

884

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

887

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

890

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

903

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

926

static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

932

pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

937

voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

34

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

46

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

48

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1190

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1192

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1280

enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1283

return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1320

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1328

dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1331

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1343

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1346

dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1374

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1386

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1486

static bool is_soc_bounding_box_valid(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1488

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1496

static bool init_soc_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1502

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1504

if (!is_soc_bounding_box_valid(dc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1511

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1512

dcn20_patch_bounding_box(dc, loaded_bb);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1514

patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1521

const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1528

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1562

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1583

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1596

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1597

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1598

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1613

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1625

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1648

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1649

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1669

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1689

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1699

if (!dc->config.enable_windowed_mpo_odm) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1700

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1721

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1742

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1766

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1768

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1796

hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1802

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1819

pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1824

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1838

pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1843

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1849

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1852

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1862

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1868

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1959

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1971

if (dc->debug.disable_fams)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1974

if (!dc->caps.dmub_caps.mclk_sw)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1994

if (context->streams[0]->vrr_active_variable && (dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2010

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2012

ASSERT(dc != NULL && context != NULL);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2013

if (dc == NULL || context == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2020

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2023

dcn30_fpu_update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2028

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2034

dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2038

enum dc_status dcn30_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2048

display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2050

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2058

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2075

if (dc->res_pool->funcs->calculate_wm_and_dlg)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2076

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2098

void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2116

if (dc->ctx->dc_bios->vram_info.num_chans)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2117

dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2120

dcn30_fpu_update_dram_channel_width_bytes(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2221

dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2270

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2274

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2301

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2302

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2303

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2304

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2305

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2306

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2307

dc->caps.mall_size_per_mem_channel = 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2309

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2310

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2312

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2313

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2314

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2315

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2316

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2317

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2318

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2321

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2322

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2323

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2324

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2325

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2326

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2327

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2328

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2329

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2330

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2331

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2332

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2334

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2335

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2337

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2338

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2339

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2340

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2341

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2342

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2344

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2345

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2346

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2347

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2348

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2349

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2350

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2351

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2352

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2354

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2355

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2356

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2365

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2374

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2378

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2379

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2382

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2383

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2440

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2451

dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2454

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2577

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2582

dcn30_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2584

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2586

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2587

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2589

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2591

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2593

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2594

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2596

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2599

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2618

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2626

if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

798

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

95

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

101

void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

103

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

104

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

105

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

34

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

46

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

49

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

59

enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

62

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

70

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

74

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

76

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

79

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

97

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1279

static bool is_soc_bounding_box_valid(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1281

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1289

static bool init_soc_bounding_box(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1295

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1297

if (!is_soc_bounding_box_valid(dc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1305

dcn20_patch_bounding_box(dc, loaded_bb);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1308

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1311

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1366

static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1369

dcn301_fpu_update_bw_bounding_box(dc, bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1373

static void dcn301_calculate_wm_and_dlg(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1380

dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1409

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1413

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1418

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1422

if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1434

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1435

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1436

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1437

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1438

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1439

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1440

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1441

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1442

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1443

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1444

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1445

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1446

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1447

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1450

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1451

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1452

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1453

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1454

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1455

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1456

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1457

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1458

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1459

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1460

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1461

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1463

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1464

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1466

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1467

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1468

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1469

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1470

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1471

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1473

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1474

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1475

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1476

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1477

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1478

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1479

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1480

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1481

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1483

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1491

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1499

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1502

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1503

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1506

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1507

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1555

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1557

if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1569

dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1572

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1697

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1702

dcn301_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1704

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1706

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1707

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1709

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1711

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1724

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1732

if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

759

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

96

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.h

31

struct dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.h

43

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1109

struct dc *dc = pool->oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1111

dc->link_srv->destroy_ddc_service(&pool->oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1122

void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1125

dcn302_fpu_update_bw_bounding_box(dc, bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1200

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1204

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1220

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1221

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1222

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1223

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1224

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1225

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1226

dc->caps.mall_size_per_mem_channel = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1228

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1229

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1230

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1231

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1232

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1233

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1234

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1235

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1236

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1237

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1238

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1241

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1242

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1243

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1244

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1245

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1246

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1247

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1248

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1249

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1250

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1251

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1252

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1254

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1255

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1257

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1258

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1259

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1260

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1261

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1262

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1264

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1265

dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1266

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1267

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1268

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1269

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1270

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1271

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1272

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1274

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1282

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1291

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1294

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1295

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1298

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1299

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1352

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1355

dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1358

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1473

if (!resource_construct(num_virtual_links, dc, pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1478

dcn302_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1480

dc->caps.max_planes = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1482

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1483

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1485

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1487

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1489

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1490

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1492

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1495

pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1509

struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1516

if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

79

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

795

&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

944

static bool is_soc_bounding_box_valid(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

946

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

954

static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

959

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

961

if (!is_soc_bounding_box_valid(dc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

968

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

970

dcn20_patch_bounding_box(dc, loaded_bb);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

973

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

976

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

977

dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

34

struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

36

void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1053

struct dc *dc = pool->oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1055

dc->link_srv->destroy_ddc_service(&pool->oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1071

void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1074

dcn303_fpu_update_bw_bounding_box(dc, bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1141

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1145

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1161

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1162

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1163

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1164

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1165

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1166

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1167

dc->caps.mall_size_per_mem_channel = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1169

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1170

dc->ctx->dc_bios->vram_info.num_chans *

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1172

dc->caps.cursor_cache_size =

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1173

dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1174

dc->caps.max_slave_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1175

dc->caps.max_slave_yuv_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1176

dc->caps.max_slave_rgb_planes = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1177

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1178

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1179

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1180

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1181

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1182

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1185

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1186

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1187

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1188

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1189

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1190

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1191

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1192

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1193

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1194

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1195

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1196

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1198

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1199

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1201

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1202

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1203

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1204

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1205

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1206

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1208

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1209

dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1210

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1211

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1212

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1213

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1214

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1215

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1216

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1218

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1220

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1227

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1235

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1238

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1239

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1242

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1243

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1284

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1287

dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1290

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1405

if (!resource_construct(num_virtual_links, dc, pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1410

dcn303_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1412

dc->caps.max_planes = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1414

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1415

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1417

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1419

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1421

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1422

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1424

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1427

pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1441

struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1448

if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

753

&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

78

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

889

static bool is_soc_bounding_box_valid(struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

891

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

899

static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

904

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

906

if (!is_soc_bounding_box_valid(dc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

913

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

915

dcn20_patch_bounding_box(dc, loaded_bb);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

918

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

921

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

922

dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.h

34

struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.h

36

void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

107

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1119

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1616

int dcn31x_populate_dml_pipes_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1626

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1630

if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1632

pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1633

} else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1635

else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1642

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1652

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1655

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1703

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1704

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1707

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1713

} else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1714

&& dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1715

context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1730

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1736

dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1741

dcn31_populate_dml_writeback_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1746

dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1751

dcn31_set_mcif_arb_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1757

dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1761

enum dc_status dcn31_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1771

display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1773

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1781

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1797

if (dc->res_pool->funcs->calculate_wm_and_dlg)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1798

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1884

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1888

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1903

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1904

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1905

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1906

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1907

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1908

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1910

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1911

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1912

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1913

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1914

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1915

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1916

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1917

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1918

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1919

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1920

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1921

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1922

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1923

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1926

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1927

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1928

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1929

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1930

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1931

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1932

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1933

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1934

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1935

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1936

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1937

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1939

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1940

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1942

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1943

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1944

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1945

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1946

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1947

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1949

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1950

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1951

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1952

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1953

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1954

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1955

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1956

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1957

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1959

dc->caps.num_of_host_routers = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1960

dc->caps.num_of_dpias_per_host_router = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1963

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1964

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1973

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1978

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1982

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1983

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1986

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1987

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2003

if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2053

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2184

if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2185

dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2186

!dc->debug.dpia_debug.bits.disable_dpia) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2191

if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2195

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2200

dcn31_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2202

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2204

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2205

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2207

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2209

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2211

dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2223

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2231

if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2245

struct dc_state *state = link->dc->current_state;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2251

link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2254

link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

964

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

40

enum dc_status dcn31_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

44

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

49

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

53

dcn31_populate_dml_writeback_from_context(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

57

dcn31_set_mcif_arb_params(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

64

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1000

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1177

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

122

dc->ctx->logger

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1670

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1677

pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1687

static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1690

dcn314_update_bw_bounding_box_fpu(dc, bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1699

enum dc_status dcn314_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1709

display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1711

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1720

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1736

if (dc->res_pool->funcs->calculate_wm_and_dlg)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1737

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1815

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1819

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1833

dc->caps.max_downscale_ratio = 400;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1834

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1835

dc->caps.i2c_speed_in_khz_hdcp = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1836

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1837

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1838

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1839

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1840

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1841

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1842

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1843

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1844

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1845

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1846

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1847

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1848

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1849

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1850

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1851

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1852

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1854

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1857

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1858

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1859

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1860

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1861

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1862

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1863

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1864

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1865

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1866

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1867

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1868

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1870

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1871

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1873

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1874

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1875

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1876

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1877

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1878

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1880

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1881

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1882

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1883

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1884

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1885

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1886

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1887

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1888

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1890

dc->caps.max_disp_clock_khz_at_vmin = 650000;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1892

dc->caps.num_of_host_routers = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1893

dc->caps.num_of_dpias_per_host_router = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1896

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1905

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1910

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1914

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1915

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1918

dc->debug.disable_dpp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1919

dc->debug.disable_hubp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1922

dc->debug.root_clock_optimization.u32All = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1925

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1926

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1977

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2112

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2117

dcn314_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2119

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2121

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2122

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2124

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2126

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2128

dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2141

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2149

if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

42

enum dc_status dcn314_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

48

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1117

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1634

static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1645

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1665

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1674

bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1677

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1680

for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1709

split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1746

for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1758

bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1788

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1789

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1792

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1797

&& pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1854

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1858

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1873

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1874

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1875

dc->caps.i2c_speed_in_khz_hdcp = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1876

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1877

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1878

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1879

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1880

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1881

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1882

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1883

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1884

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1885

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1886

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1887

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1888

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1889

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1890

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1891

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1894

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1895

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1896

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1897

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1898

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1899

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1900

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1901

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1902

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1903

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1904

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1905

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1907

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1908

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1910

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1911

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1912

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1913

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1914

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1915

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1917

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1918

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1919

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1920

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1921

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1922

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1923

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1924

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1925

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1934

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1939

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1943

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1944

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1947

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1948

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2001

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2133

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2138

dcn31_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2140

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2142

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2143

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2145

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2147

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2149

dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2162

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2170

if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

962

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.h

42

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1111

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1611

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1621

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1624

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1673

dc->config.enable_4to1MPC = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1674

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1677

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1730

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1734

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1749

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1750

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1751

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1752

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1753

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1754

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1755

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1756

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1757

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1758

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1759

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1760

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1761

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1762

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1763

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1764

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1765

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1766

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1767

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1770

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1771

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1772

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1773

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1774

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1775

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1776

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1777

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1778

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1779

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1780

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1781

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1783

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1784

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1786

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1787

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1788

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1789

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1790

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1791

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1793

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1794

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1795

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1796

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1797

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1798

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1799

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1800

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1801

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1810

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1815

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1819

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1820

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1823

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1824

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1877

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2001

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2006

dcn31_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2008

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2010

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2011

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2013

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2015

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2017

dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2030

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2038

if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

956

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.h

42

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1497

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1499

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1640

static void dcn32_enable_phantom_plane(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1653

phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1677

dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1684

static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1693

phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1702

dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1705

dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1712

void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1723

phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1727

dcn32_enable_phantom_plane(dc, context, phantom_stream, index);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1729

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1746

static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1754

display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1763

DC_LOGGER_INIT(dc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1771

out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1787

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1790

dcn32_override_min_req_memclk(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1793

dcn32_override_min_req_dcfclk(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1814

enum dc_status dcn32_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1831

if (dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1832

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1836

status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1855

if (dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1856

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1860

status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1867

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1885

dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1904

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1918

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1930

if (dc->config.enable_windowed_mpo_odm &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1931

dc->debug.enable_single_display_2to1_odm_policy) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2014

dcn32_set_det_allocations(dc, context, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2027

unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2035

if (dc->caps.max_cab_allocation_bytes == 0) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2040

cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2042

total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2043

lines_per_way = total_cache_lines / dc->caps.cache_num_ways;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2056

void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2062

dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2066

static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2070

dcn32_update_bw_bounding_box_fpu(dc, bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2072

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2073

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2075

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2076

dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2081

unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2090

return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2133

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2137

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2198

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2199

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2200

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2202

dc->caps.max_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2203

dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2204

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2205

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2206

dc->caps.mall_size_per_mem_channel = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2208

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2209

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2211

dc->caps.cache_line_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2212

dc->caps.cache_num_ways = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2215

dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2216

dc, dc->ctx->dc_bios->vram_info.num_chans) *

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2217

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2218

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2220

dc->caps.subvp_fw_processing_delay_us = 15;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2221

dc->caps.subvp_drr_max_vblank_margin_us = 40;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2222

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2223

dc->caps.subvp_swath_height_margin_lines = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2224

dc->caps.subvp_pstate_allow_width_us = 20;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2225

dc->caps.subvp_vertical_int_margin_us = 30;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2226

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2228

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2229

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2230

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2231

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2232

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2233

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2234

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2235

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2236

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2237

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2238

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2239

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2240

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2241

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2242

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2245

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2246

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2247

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2248

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2249

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2250

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2251

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2252

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2253

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2254

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2255

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2256

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2258

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2259

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2261

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2262

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2263

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2264

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2265

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2266

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2268

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2269

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2270

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2271

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2272

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2273

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2274

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2275

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2276

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2277

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2280

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2282

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2283

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2284

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2292

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2297

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2301

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2302

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2305

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2306

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2359

dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2362

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2495

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2500

dcn32_hw_sequencer_init_functions(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2502

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2504

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2505

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2507

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2509

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2511

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2512

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2514

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2517

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2522

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2523

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2524

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2526

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2527

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2528

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2529

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2531

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2532

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2533

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2534

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2536

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2537

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2539

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2540

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2541

dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2542

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2543

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2544

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2545

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2547

dc->dml2_options.max_segments_per_hubp = 18;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2548

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2549

dc->dml2_options.map_dc_pipes_with_callbacks = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2551

if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2552

dc->config.sdpif_request_limit_words_per_umc = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2555

memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2556

dc->dml2_dc_power_options.use_clock_dc_limits = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2569

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2577

if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2696

old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2734

struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2808

if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2861

dcn20_acquire_dsc(free_pipe->stream->ctx->dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2879

unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2919

if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2922

} else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

768

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

870

ctx->dc->dml.ip.det_buffer_size_kbytes,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

871

ctx->dc->dml.ip.pixel_chunk_size_kbytes,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

872

ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

101

enum dc_status dcn32_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

106

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

111

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

117

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

122

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

125

void dcn32_merge_pipes_for_subvp(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

128

bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

131

bool dcn32_subvp_in_use(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

136

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

162

void dcn32_determine_det_override(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

166

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

169

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

175

unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

177

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

181

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

183

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

185

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

187

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

189

unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

191

unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

77

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

95

void dcn32_add_phantom_pipes(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

107

void dcn32_merge_pipes_for_subvp(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

113

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

132

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

153

bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

158

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

170

bool dcn32_subvp_in_use(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

175

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

196

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

200

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

243

static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

259

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

263

if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

274

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

311

void dcn32_determine_det_override(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

338

for (j = 0; j < dc->res_pool->pipe_count; j++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

349

for (k = 0; k < dc->res_pool->pipe_count; k++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

358

for (k = 0; k < dc->res_pool->pipe_count; k++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

368

override_det_for_subvp(dc, context, pipe_segments);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

369

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

376

for (i = 0; i < dc->res_pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

381

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

387

bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

389

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

40

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

414

dcn32_determine_det_override(dc, context, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

477

if (fpo_candidate_stream->ctx->dc->config.enable_fpo_flicker_detection == 1 &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

515

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

527

if (dc->debug.disable_fams)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

530

if (!dc->caps.dmub_caps.mclk_sw)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

543

dcn32_assign_fpo_vactive_candidate(dc, context, &fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

548

is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, fpo_candidate_stream, dc->debug.fpo_vactive_min_active_margin_us);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

550

if (!is_fpo_vactive || dc->debug.disable_fpo_vactive)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

576

fpo_vactive_margin_us = is_fpo_vactive ? dc->debug.fpo_vactive_margin_us : 0; // For now hardcode the FPO + Vactive stretch margin to be 2000us

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

584

((dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE) ||

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

585

(context->stream_count > 1 && !(dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_ENABLE))))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

644

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

655

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

704

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

716

for (i = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

750

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

757

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

776

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

778

if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

91

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

95

if (dc->debug.force_subvp_num_ways) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

96

return dc->debug.force_subvp_num_ways;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

97

} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

98

return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1477

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1479

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1581

static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1585

dcn321_update_bw_bounding_box_fpu(dc, bw_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1587

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1588

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1590

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1591

dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1636

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1640

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1702

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1703

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1704

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1706

dc->caps.max_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1707

dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1708

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1709

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1710

dc->caps.mall_size_per_mem_channel = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1712

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1714

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1715

dc->caps.cache_line_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1716

dc->caps.cache_num_ways = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1719

dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1720

dc, dc->ctx->dc_bios->vram_info.num_chans) *

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1721

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1722

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1724

dc->caps.subvp_fw_processing_delay_us = 15;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1725

dc->caps.subvp_drr_max_vblank_margin_us = 40;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1726

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1727

dc->caps.subvp_swath_height_margin_lines = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1728

dc->caps.subvp_pstate_allow_width_us = 20;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1729

dc->caps.subvp_vertical_int_margin_us = 30;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1730

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1731

dc->caps.max_slave_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1732

dc->caps.max_slave_yuv_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1733

dc->caps.max_slave_rgb_planes = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1734

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1735

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1736

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1737

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1738

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1739

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1740

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1741

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1742

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1745

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1746

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1747

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1748

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1749

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1750

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1751

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1752

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1753

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1754

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1755

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1756

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1758

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1759

dc->caps.color.dpp.ogam_ram = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1761

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1762

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1763

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1764

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1765

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1766

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1768

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1769

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1770

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1771

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1772

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1773

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1774

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1775

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1776

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1777

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1780

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1782

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1783

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1784

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1792

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1797

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1801

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1802

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1805

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1806

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1859

dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1862

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1990

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1995

dcn32_hw_sequencer_init_functions(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1997

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1999

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2000

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2002

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2004

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2006

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2007

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2009

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2012

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2017

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2018

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2019

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2021

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2022

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2023

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2024

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2026

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2027

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2028

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2029

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2031

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2032

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2034

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2035

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2036

dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2037

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2038

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2039

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2040

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2042

dc->dml2_options.max_segments_per_hubp = 18;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2043

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2046

memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2047

dc->dml2_dc_power_options.use_clock_dc_limits = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2060

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2068

if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

762

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

864

ctx->dc->dml.ip.det_buffer_size_kbytes,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

865

ctx->dc->dml.ip.pixel_chunk_size_kbytes,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

866

ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.h

43

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1124

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1595

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1634

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1688

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1735

static enum dc_status dcn35_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1741

out = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1749

dcn35_decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1763

static int populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1771

ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1810

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1814

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1852

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1853

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1854

dc->caps.i2c_speed_in_khz_hdcp = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1855

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1856

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1857

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1858

dc->caps.max_slave_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1859

dc->caps.max_slave_yuv_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1860

dc->caps.max_slave_rgb_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1861

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1862

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1863

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1864

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1865

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1866

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1868

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1869

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1870

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1871

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1872

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1874

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1875

dc->caps.ips_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1876

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1877

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1880

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1881

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1882

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1883

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1884

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1885

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1886

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1887

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1888

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1889

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1890

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1891

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1893

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1894

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1896

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1897

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1898

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1899

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1900

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1901

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1903

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1904

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1905

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1906

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1907

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1908

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1909

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1910

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1911

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1912

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1914

dc->caps.num_of_host_routers = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1915

dc->caps.num_of_dpias_per_host_router = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1923

dc->caps.max_disp_clock_khz_at_vmin = 650000;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1926

if (dc->ctx->asic_id.hw_internal_rev >= 0x40)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1927

dc->caps.sequential_ono = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1930

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1933

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1941

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1946

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1950

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1951

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1953

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1955

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1956

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2000

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2022

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2155

if (dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2159

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2164

dcn35_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2166

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2168

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2169

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2171

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2173

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2175

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2177

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2178

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2179

dc->dml2_options.minimize_dispclk_using_odm = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2180

if (dc->config.EnableMinDispClkODM)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2181

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2182

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2184

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2185

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2187

dc->dml2_options.max_segments_per_hubp = 24;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2188

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2189

dc->dml2_options.override_det_buffer_size_kbytes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2191

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2192

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2205

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2213

if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

828

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

858

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

886

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

46

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1104

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1575

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1614

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1668

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1715

static enum dc_status dcn351_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1721

out = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1729

dcn35_decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1735

static int populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1743

ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1783

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1787

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1825

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1826

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1827

dc->caps.i2c_speed_in_khz_hdcp = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1828

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1829

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1830

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1831

dc->caps.max_slave_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1832

dc->caps.max_slave_yuv_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1833

dc->caps.max_slave_rgb_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1834

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1835

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1836

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1837

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1838

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1839

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1841

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1842

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1843

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1844

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1845

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1847

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1848

dc->caps.ips_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1849

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1850

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1853

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1854

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1855

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1856

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1857

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1858

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1859

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1860

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1861

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1862

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1863

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1864

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1866

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1867

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1869

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1870

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1871

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1872

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1873

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1874

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1876

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1877

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1878

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1879

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1880

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1881

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1882

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1883

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1884

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1885

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1887

dc->caps.num_of_host_routers = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1888

dc->caps.num_of_dpias_per_host_router = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1896

dc->caps.max_disp_clock_khz_at_vmin = 650000;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1899

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1903

dc->config.use_assr_psp_message = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1912

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1917

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1921

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1922

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1925

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1927

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1928

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1972

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1994

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2127

if (dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2131

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2136

dcn351_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2138

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2140

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2141

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2143

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2145

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2148

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2150

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2151

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2152

dc->dml2_options.minimize_dispclk_using_odm = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2153

if (dc->config.EnableMinDispClkODM)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2154

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2155

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2157

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2158

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2160

dc->dml2_options.max_segments_per_hubp = 24;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2161

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2162

dc->dml2_options.override_det_buffer_size_kbytes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2164

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2165

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2178

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2186

if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

808

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

838

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

866

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.h

21

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1105

if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1576

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1615

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1669

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1716

static enum dc_status dcn35_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1722

out = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1730

dcn35_decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1737

static int populate_dml_pipes_from_context_fpu(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1745

ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1783

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1787

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1825

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1826

dc->caps.i2c_speed_in_khz = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1827

dc->caps.i2c_speed_in_khz_hdcp = 100;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1828

dc->caps.max_cursor_size = 256;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1829

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1830

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1831

dc->caps.max_slave_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1832

dc->caps.max_slave_yuv_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1833

dc->caps.max_slave_rgb_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1834

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1835

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1836

if (dc->config.forceHBR2CP2520)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1837

dc->caps.force_dp_tps4_for_cp2520 = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1838

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1839

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1841

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1842

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1843

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1844

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1845

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1847

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1848

dc->caps.ips_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1849

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1850

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1853

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1854

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1855

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1856

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1857

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1858

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1859

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1860

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1861

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1862

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1863

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1864

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1866

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1867

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1869

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1870

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1871

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1872

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1873

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1874

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1876

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1877

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1878

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1879

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1880

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1881

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1882

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1883

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1884

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1885

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1887

dc->caps.num_of_host_routers = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1888

dc->caps.num_of_dpias_per_host_router = 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1896

dc->caps.max_disp_clock_khz_at_vmin = 650000;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1899

if (dc->ctx->asic_id.hw_internal_rev >= 0x40)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1900

dc->caps.sequential_ono = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1903

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1905

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1913

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1918

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1922

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1923

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1926

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1928

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1929

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1973

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1995

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2128

if (dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2132

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2137

dcn35_hw_sequencer_construct(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2139

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2141

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2142

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2144

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2146

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2148

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2150

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2151

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2152

dc->dml2_options.minimize_dispclk_using_odm = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2153

if (dc->config.EnableMinDispClkODM)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2154

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2155

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2157

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2158

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2160

dc->dml2_options.max_segments_per_hubp = 24;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2161

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2162

dc->dml2_options.override_det_buffer_size_kbytes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2164

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2165

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2178

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2186

if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

809

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

839

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

867

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h

21

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1297

static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1311

if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1313

} else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1500

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1502

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1587

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1609

static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1613

dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1614

dc, bw_params->num_channels) *

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1615

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1616

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1621

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1622

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1624

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1625

dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1637

enum dc_status dcn401_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1654

if (dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1655

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1676

if (dc->debug.using_dml2)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1677

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1685

void dcn401_prepare_mcache_programming(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1688

if (dc->debug.using_dml21)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1689

dml2_prepare_mcache_programming(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1705

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1744

if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1746

} else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1748

} else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1819

struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1823

struct dc_context *ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1878

dc->caps.max_downscale_ratio = 600;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1879

dc->caps.i2c_speed_in_khz = 95;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1880

dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1882

dc->caps.max_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1883

dc->caps.max_buffered_cursor_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1884

dc->caps.cursor_not_scaled = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1885

dc->caps.min_horizontal_blanking_period = 80;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1886

dc->caps.dmdata_alloc_size = 2048;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1887

dc->caps.mall_size_per_mem_channel = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1888

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1889

dc->caps.cache_line_size = 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1890

dc->caps.cache_num_ways = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1893

dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1894

dc, dc->ctx->dc_bios->vram_info.num_chans) *

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1895

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1896

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1898

dc->caps.subvp_fw_processing_delay_us = 15;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1899

dc->caps.subvp_drr_max_vblank_margin_us = 40;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1900

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1901

dc->caps.subvp_swath_height_margin_lines = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1902

dc->caps.subvp_pstate_allow_width_us = 20;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1903

dc->caps.subvp_vertical_int_margin_us = 30;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1904

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1906

dc->caps.max_slave_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1907

dc->caps.max_slave_yuv_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1908

dc->caps.max_slave_rgb_planes = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1909

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1910

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1911

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1912

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1913

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1914

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1915

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1916

dc->caps.max_v_total = (1 << 15) - 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1917

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1919

if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1920

dc->caps.dcc_plane_width_limit = 7680;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1923

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1924

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1925

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1926

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1927

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1928

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1929

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1930

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1931

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1932

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1933

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1934

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1936

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1937

dc->caps.color.dpp.ogam_ram = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1939

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1940

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1941

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1942

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1943

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1944

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1946

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1947

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1948

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1949

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1950

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1951

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1952

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1953

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1954

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1955

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1956

dc->config.use_spl = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1957

dc->config.prefer_easf = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1959

dc->config.dcn_sharpness_range.sdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1960

dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1961

dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1962

dc->config.dcn_sharpness_range.sdr_yuv_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1963

dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1964

dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1965

dc->config.dcn_sharpness_range.hdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1966

dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1967

dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1969

dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1970

dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1971

dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1972

dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1973

dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1974

dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1975

dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1976

dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1977

dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1979

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1980

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1981

dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1990

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1995

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1999

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2000

dc->debug = debug_defaults_drv;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2003

if (dc->vm_helper)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2004

vm_helper_init(dc->vm_helper, 16);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2057

init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2185

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2190

dcn401_hw_sequencer_init_functions(dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2192

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2194

for (i = 0; i < dc->caps.max_planes; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2195

dc->caps.planes[i] = plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2197

dc->caps.max_odm_combine_factor = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2199

dc->cap_funcs = cap_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2201

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2202

ddc_init_data.ctx = dc->ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2204

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2207

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2213

if (dc->config.sdpif_request_limit_words_per_umc == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2214

dc->config.sdpif_request_limit_words_per_umc = 16;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2216

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2217

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2218

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2219

dc->dml2_options.map_dc_pipes_with_callbacks = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2220

dc->dml2_options.force_tdlut_enable = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2222

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2223

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2224

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2225

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2227

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2228

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2229

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2230

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2232

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2233

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2235

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2236

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2237

dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2238

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2239

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2240

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2241

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2243

dc->dml2_options.max_segments_per_hubp = 20;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2244

dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2247

dc->caps.scl_caps.sharpener_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2250

memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2251

dc->dml2_dc_power_options.use_clock_dc_limits = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2264

struct dc *dc)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2272

if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

762

ctx->dc->caps.extended_aux_timeout_support);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

21

struct dc *dc);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

25

enum dc_status dcn401_validate_bandwidth(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

29

void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

209

void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

211

soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

212

soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

213

soc_bb->mall_allocated_for_dcn_mbytes = dc->caps.mall_size_total / (1024 * 1024);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

215

if (dc->clk_mgr->funcs->is_smu_present &&

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

216

dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) {

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

218

dc->clk_mgr->bw_params,

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

223

void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

225

soc_bb->dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

226

soc_bb->xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

229

if (dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

231

dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns / 10.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

233

if (dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

235

dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns / 10.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

237

if (dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

239

dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns / 10.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

242

void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

245

if (dc->bb_overrides.sr_exit_time_ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

247

dc->bb_overrides.sr_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

249

if (dc->bb_overrides.sr_enter_plus_exit_time_ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

251

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

253

if (dc->bb_overrides.dram_clock_change_latency_ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

255

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

257

if (dc->bb_overrides.fclk_clock_change_latency_ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

259

dc->bb_overrides.fclk_clock_change_latency_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

262

if (dc->bb_overrides.sr_exit_z8_time_ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

264

dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

266

if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

268

dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

271

static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

278

dcn401_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc, config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

279

dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

280

dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

283

void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

288

apply_soc_bb_updates(soc_bb, dc, config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

17

void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

18

void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

19

void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc);

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

20

void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc);

sys/dev/pci/drm/amd/display/include/logger_interface.h

128

unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)

sys/dev/pci/drm/amd/display/include/logger_interface.h

132

unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \

sys/dev/pci/drm/amd/display/include/logger_interface.h

133

if (dc->debug.performance_trace) { \

sys/dev/pci/drm/amd/display/include/logger_interface.h

44

struct dc *dc,

sys/dev/pci/drm/amd/display/include/logger_interface.h

48

void post_surface_trace(struct dc *dc);

sys/dev/pci/drm/amd/display/include/logger_interface.h

51

struct dc *dc,

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1183

cur_tick = dm_get_timestamp(core_freesync->dc->ctx);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1185

div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

127

unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

129

if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

55

struct dc *dc;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

61

struct mod_freesync *mod_freesync_create(struct dc *dc)

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

69

if (dc == NULL)

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

72

core_freesync->dc = dc;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

999

if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

110

struct mod_freesync *mod_freesync_create(struct dc *dc);

sys/dev/pci/drm/amd/display/modules/inc/mod_stats.h

44

struct mod_stats *mod_stats_create(struct dc *dc,

sys/dev/pci/drm/amd/display/modules/inc/mod_vmid.h

40

struct dc *dc,

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

943

bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

952

!dc->caps.edp_dsc_support ||

sys/dev/pci/drm/amd/display/modules/power/power_helpers.h

75

bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,

sys/dev/pci/drm/amd/display/modules/vmid/vmid.c

118

dc_setup_vm_context(core_vmid->dc, &va_config, vmid);

sys/dev/pci/drm/amd/display/modules/vmid/vmid.c

135

struct dc *dc,

sys/dev/pci/drm/amd/display/modules/vmid/vmid.c

144

if (dc == NULL)

sys/dev/pci/drm/amd/display/modules/vmid/vmid.c

152

core_vmid->dc = dc;

sys/dev/pci/drm/amd/display/modules/vmid/vmid.c

30

struct dc *dc;

sys/dev/pci/drm/amd/display/modules/vmid/vmid.c

60

uint16_t ord = dc_get_vmid_use_vector(core_vmid->dc);

sys/dev/pci/drm/i915/gt/selftest_rps.c

542

u64 dc, dt;

sys/dev/pci/drm/i915/gt/selftest_rps.c

544

dc = READ_ONCE(*cntr);

sys/dev/pci/drm/i915/gt/selftest_rps.c

547

dc = READ_ONCE(*cntr) - dc;

sys/dev/pci/drm/i915/gt/selftest_rps.c

550

return div64_u64(1000 * 1000 * dc, dt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

571

u64 dc, dt;

sys/dev/pci/drm/i915/gt/selftest_rps.c

573

dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0));

sys/dev/pci/drm/i915/gt/selftest_rps.c

576

dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc;

sys/dev/pci/drm/i915/gt/selftest_rps.c

579

return div64_u64(1000 * 1000 * dc, dt);

sys/dev/pci/if_em_hw.h

1332

uint64_t dc;

sys/dev/pci/if_ice.c

18527

uint8_t *dc, uint8_t *nm, uint16_t off, uint16_t len)

sys/dev/pci/if_ice.c

18550

dc ? dc[i] : 0, nm ? nm[i] : 0,

sys/dev/pci/if_ixgb.c

1942

sc->stats.dc += IXGB_READ_REG(&sc->hw, DC);

sys/dev/pci/if_ixgb.c

2054

(long long)sc->stats.dc);

sys/dev/pci/if_myx.c

329

pcireg_t dc = ((fls(4096) - 8) << 12) | PCI_PCIE_DCSR_ERO;

sys/dev/pci/if_myx.c

338

if ((dcsr & mask) != dc) {

sys/dev/pci/if_myx.c

340

SET(dcsr, dc);

sys/dev/pci/ixgb_hw.h

797

uint64_t dc;

sys/dev/pci/mfii.c

2268

mfii_ioctl_cache(struct scsi_link *link, u_long cmd, struct dk_cache *dc)

sys/dev/pci/mfii.c

2304

dc->wrcache = wrenable;

sys/dev/pci/mfii.c

2305

dc->rdcache = rdenable;

sys/dev/pci/mfii.c

2309

if (((dc->wrcache) ? 1 : 0) == wrenable &&

sys/dev/pci/mfii.c

2310

((dc->rdcache) ? 1 : 0) == rdenable)

sys/dev/pci/mfii.c

2319

if (dc->rdcache)

sys/dev/pci/mfii.c

2325

if (dc->wrcache)

sys/dev/pci/mfii.c

2332

if (dc->rdcache) {

sys/dev/pci/mfii.c

2336

if (dc->wrcache)

sys/dev/pci/mpii.c

3255

mpii_ioctl_cache(struct scsi_link *link, u_long cmd, struct dk_cache *dc)

sys/dev/pci/mpii.c

3289

dc->wrcache = enabled;

sys/dev/pci/mpii.c

3290

dc->rdcache = 0;

sys/dev/pci/mpii.c

3294

if (dc->rdcache) {

sys/dev/pci/mpii.c

3299

if (((dc->wrcache) ? 1 : 0) == enabled)

sys/dev/pci/mpii.c

3315

htolem32(&req->action_data, dc->wrcache ?

sys/dev/pci/mpii.c

3329

(dc->wrcache ? MPII_RAID_VOL_WRITE_CACHE_ENABLE :

sys/dev/pci/tga.c

1097

struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw;

sys/dev/pci/tga.c

1103

int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units;

sys/dev/pci/tga.c

1150

TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */

sys/dev/pci/tga.c

1151

TGAWALREG(dc, TGA_REG_GOPR, 3, 0x0003); /* SRC */

sys/dev/pci/tga.c

1175

TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);

sys/dev/pci/tga.c

1176

TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);

sys/dev/pci/tga.c

1177

TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64);

sys/dev/pci/tga.c

1178

TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64);

sys/dev/pci/tga.c

1179

TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64);

sys/dev/pci/tga.c

1180

TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64);

sys/dev/pci/tga.c

1181

TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64);

sys/dev/pci/tga.c

1182

TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64);

sys/dev/pci/tga.c

1188

TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);

sys/dev/pci/tga.c

1189

TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);

sys/dev/pci/tga.c

1194

TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */

sys/dev/pci/tga.c

1195

TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */

sys/dev/pci/tga.c

1222

TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64);

sys/dev/pci/tga.c

1223

TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64);

sys/dev/pci/tga.c

1224

TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64);

sys/dev/pci/tga.c

1225

TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64);

sys/dev/pci/tga.c

1226

TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64);

sys/dev/pci/tga.c

1227

TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64);

sys/dev/pci/tga.c

1228

TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64);

sys/dev/pci/tga.c

1229

TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64);

sys/dev/pci/tga.c

1237

TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);

sys/dev/pci/tga.c

1238

TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);

sys/dev/pci/tga.c

1243

TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */

sys/dev/pci/tga.c

1244

TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */

sys/dev/pci/tga.c

1264

struct tga_devconfig *dc = ri->ri_hw;

sys/dev/pci/tga.c

1284

TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]);

sys/dev/pci/tga.c

1285

TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]);

sys/dev/pci/tga.c

1289

TGAWREG(dc, TGA_REG_GOPR, 0x3);

sys/dev/pci/tga.c

1291

TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));

sys/dev/pci/tga.c

1294

TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1);

sys/dev/pci/tga.c

1297

TGAWREG(dc, TGA_REG_GMOR, 0x1);

sys/dev/pci/tga.c

1301

TGAREGWB(dc, TGA_REG_GMOR, 1);

sys/dev/pci/tga.c

1318

TGAWREG(dc, TGA_REG_GMOR, 0);

sys/dev/pci/tga.c

1319

TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);

sys/dev/pci/tga.c

1328

struct tga_devconfig *dc = ri->ri_hw;

sys/dev/pci/tga.c

1340

TGAWREG(dc, TGA_REG_GBCR0, color);

sys/dev/pci/tga.c

1341

TGAWREG(dc, TGA_REG_GBCR1, color);

sys/dev/pci/tga.c

1343

TGAWREG(dc, TGA_REG_GBCR2, color);

sys/dev/pci/tga.c

1344

TGAWREG(dc, TGA_REG_GBCR3, color);

sys/dev/pci/tga.c

1345

TGAWREG(dc, TGA_REG_GBCR4, color);

sys/dev/pci/tga.c

1346

TGAWREG(dc, TGA_REG_GBCR5, color);

sys/dev/pci/tga.c

1347

TGAWREG(dc, TGA_REG_GBCR6, color);

sys/dev/pci/tga.c

1348

TGAWREG(dc, TGA_REG_GBCR7, color);

sys/dev/pci/tga.c

1353

TGAWREG(dc, TGA_REG_GOPR, 0x3);

sys/dev/pci/tga.c

1355

TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));

sys/dev/pci/tga.c

1358

TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);

sys/dev/pci/tga.c

1361

TGAWREG(dc, TGA_REG_GMOR, 0x2d);

sys/dev/pci/tga.c

1365

TGAREGWB(dc, TGA_REG_GMOR, 1);

sys/dev/pci/tga.c

1373

TGAWREG(dc, TGA_REG_GMOR, 0);

sys/dev/pci/tga.c

1382

struct tga_devconfig *dc = ri->ri_hw;

sys/dev/pci/tga.c

1394

TGAWREG(dc, TGA_REG_GBCR0, color);

sys/dev/pci/tga.c

1395

TGAWREG(dc, TGA_REG_GBCR1, color);

sys/dev/pci/tga.c

1397

TGAWREG(dc, TGA_REG_GBCR2, color);

sys/dev/pci/tga.c

1398

TGAWREG(dc, TGA_REG_GBCR3, color);

sys/dev/pci/tga.c

1399

TGAWREG(dc, TGA_REG_GBCR4, color);

sys/dev/pci/tga.c

1400

TGAWREG(dc, TGA_REG_GBCR5, color);

sys/dev/pci/tga.c

1401

TGAWREG(dc, TGA_REG_GBCR6, color);

sys/dev/pci/tga.c

1402

TGAWREG(dc, TGA_REG_GBCR7, color);

sys/dev/pci/tga.c

1407

TGAWREG(dc, TGA_REG_GOPR, 0x3);

sys/dev/pci/tga.c

1409

TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));

sys/dev/pci/tga.c

1412

TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);

sys/dev/pci/tga.c

1415

TGAWREG(dc, TGA_REG_GMOR, 0x2d);

sys/dev/pci/tga.c

1419

TGAREGWB(dc, TGA_REG_GMOR, 1);

sys/dev/pci/tga.c

1427

TGAWREG(dc, TGA_REG_GMOR, 0);

sys/dev/pci/tga.c

1436

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

1441

TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */

sys/dev/pci/tga.c

1442

TGAREGWB(dc, TGA_REG_EPDR, 1);

sys/dev/pci/tga.c

1448

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

1454

bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +

sys/dev/pci/tga.c

1456

bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);

sys/dev/pci/tga.c

1457

bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);

sys/dev/pci/tga.c

1463

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

1471

TGAREGWB(dc, TGA_REG_EPSR, 1);

sys/dev/pci/tga.c

1472

TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);

sys/dev/pci/tga.c

1473

TGAREGWB(dc, TGA_REG_EPSR, 1);

sys/dev/pci/tga.c

1474

TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0);

sys/dev/pci/tga.c

1476

TGAREGRB(dc, TGA_REG_EPSR, 1);

sys/dev/pci/tga.c

1478

rdval = TGARREG(dc, TGA_REG_EPDR);

sys/dev/pci/tga.c

1479

TGAREGWB(dc, TGA_REG_EPSR, 1);

sys/dev/pci/tga.c

1480

TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);

sys/dev/pci/tga.c

1488

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

1500

TGAREGWB(dc, TGA_REG_EPDR, 1);

sys/dev/pci/tga.c

1501

TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);

sys/dev/pci/tga.c

1502

TGAREGWB(dc, TGA_REG_EPDR, 1);

sys/dev/pci/tga.c

1503

TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);

sys/dev/pci/tga.c

1504

TGAREGWB(dc, TGA_REG_EPDR, 1);

sys/dev/pci/tga.c

1505

TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);

sys/dev/pci/tga.c

1512

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

1518

TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */

sys/dev/pci/tga.c

1519

TGAREGWB(dc, TGA_REG_EPSR, 1);

sys/dev/pci/tga.c

1521

rdval = TGARREG(dc, TGA_REG_EPDR);

sys/dev/pci/tga.c

1528

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

1535

bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +

sys/dev/pci/tga.c

1537

retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;

sys/dev/pci/tga.c

1538

bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);

sys/dev/pci/tga.c

1544

struct tga_devconfig *dc,

sys/dev/pci/tga.c

1548

struct monitor *tga_getmonitor(struct tga_devconfig *dc);

sys/dev/pci/tga.c

1551

tga2_init(struct tga_devconfig *dc)

sys/dev/pci/tga.c

1553

struct monitor *m = tga_getmonitor(dc);

sys/dev/pci/tga.c

1558

if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) {

sys/dev/pci/tga.c

1562

tga2_ics9110_wr(dc, 14300000);

sys/dev/pci/tga.c

1568

tga2_ics9110_wr(dc, m->dotclock);

sys/dev/pci/tga.c

1571

TGAWREG(dc, TGA_REG_VHCR,

sys/dev/pci/tga.c

1577

TGAWREG(dc, TGA_REG_VHCR,

sys/dev/pci/tga.c

1583

TGAWREG(dc, TGA_REG_VVCR,

sys/dev/pci/tga.c

1588

TGAWREG(dc, TGA_REG_VVBR, 1);

sys/dev/pci/tga.c

1589

TGAREGRWB(dc, TGA_REG_VHCR, 3);

sys/dev/pci/tga.c

1590

TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1);

sys/dev/pci/tga.c

1591

TGAREGRWB(dc, TGA_REG_VVVR, 1);

sys/dev/pci/tga.c

1592

TGAWREG(dc, TGA_REG_GPMR, 0xffffffff);

sys/dev/pci/tga.c

1593

TGAREGRWB(dc, TGA_REG_GPMR, 1);

sys/dev/pci/tga.c

1597

tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock)

sys/dev/pci/tga.c

1648

bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +

sys/dev/pci/tga.c

1658

bus_space_write_4(dc->dc_memt, clock, 0, writeval);

sys/dev/pci/tga.c

1659

bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);

sys/dev/pci/tga.c

1661

bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +

sys/dev/pci/tga.c

1664

bus_space_write_4(dc->dc_memt, clock, 0, 0x0);

sys/dev/pci/tga.c

1665

bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);

sys/dev/pci/tga.c

1669

tga_getmonitor(struct tga_devconfig *dc)

sys/dev/pci/tga.c

1671

return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f];

sys/dev/pci/tga.c

1675

tga_getdotclock(struct tga_devconfig *dc)

sys/dev/pci/tga.c

1677

return tga_getmonitor(dc)->dotclock;

sys/dev/pci/tga.c

198

struct tga_devconfig *dc)

sys/dev/pci/tga.c

206

dc->dc_memt = memt;

sys/dev/pci/tga.c

208

dc->dc_pcitag = tag;

sys/dev/pci/tga.c

214

&dc->dc_pcipaddr, &pcisize, NULL))

sys/dev/pci/tga.c

218

if (bus_space_map(memt, dc->dc_pcipaddr, pcisize,

sys/dev/pci/tga.c

219

BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh))

sys/dev/pci/tga.c

222

dc->dc_vaddr = dc->dc_memh;

sys/dev/pci/tga.c

224

dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh);

sys/dev/pci/tga.c

229

dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */

sys/dev/pci/tga.c

232

bus_space_subregion(dc->dc_memt, dc->dc_memh,

sys/dev/pci/tga.c

234

&dc->dc_regs);

sys/dev/pci/tga.c

237

dc->dc_tga_type = tga_identify(dc);

sys/dev/pci/tga.c

240

tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);

sys/dev/pci/tga.c

251

switch (TGARREG(dc, TGA_REG_GREV) & 0xff) {

sys/dev/pci/tga.c

256

dc->dc_tga2 = 0;

sys/dev/pci/tga.c

261

dc->dc_tga2 = 1;

sys/dev/pci/tga.c

267

if (dc->dc_tga2) {

sys/dev/pci/tga.c

268

tga2_init(dc);

sys/dev/pci/tga.c

271

i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff;

sys/dev/pci/tga.c

275

dc->dc_wid = 8192;

sys/dev/pci/tga.c

279

dc->dc_wid = 8196;

sys/dev/pci/tga.c

283

dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */

sys/dev/pci/tga.c

287

DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid);

sys/dev/pci/tga.c

293

if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */

sys/dev/pci/tga.c

294

(TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */

sys/dev/pci/tga.c

295

TGAWREG(dc, TGA_REG_VHCR,

sys/dev/pci/tga.c

296

(TGARREG(dc, TGA_REG_VHCR) & ~0x80000001));

sys/dev/pci/tga.c

297

dc->dc_wid -= 4;

sys/dev/pci/tga.c

300

dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8);

sys/dev/pci/tga.c

301

dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */

sys/dev/pci/tga.c

304

dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth,

sys/dev/pci/tga.c

305

dc->dc_wid, dc->dc_ht);

sys/dev/pci/tga.c

309

TGAWREG(dc, TGA_REG_CCBR, 0);

sys/dev/pci/tga.c

310

TGAWREG(dc, TGA_REG_VVBR, 1);

sys/dev/pci/tga.c

311

dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] +

sys/dev/pci/tga.c

313

dc->dc_blanked = 1;

sys/dev/pci/tga.c

314

tga_unblank(dc);

sys/dev/pci/tga.c

320

dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0],

sys/dev/pci/tga.c

329

TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);

sys/dev/pci/tga.c

333

for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t))

sys/dev/pci/tga.c

334

*(u_int32_t *)(dc->dc_videobase + i) = 0;

sys/dev/pci/tga.c

338

rip = &dc->dc_rinfo;

sys/dev/pci/tga.c

341

rip->ri_bits = (void *)dc->dc_videobase;

sys/dev/pci/tga.c

342

rip->ri_width = dc->dc_wid;

sys/dev/pci/tga.c

343

rip->ri_height = dc->dc_ht;

sys/dev/pci/tga.c

344

rip->ri_stride = dc->dc_rowbytes;

sys/dev/pci/tga.c

345

rip->ri_hw = dc;

sys/dev/pci/tga.c

397

dc->dc_intrenabled = 0;

sys/dev/pci/tga.c

554

struct tga_devconfig *dc = sc->sc_dc;

sys/dev/pci/tga.c

555

struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;

sys/dev/pci/tga.c

556

struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;

sys/dev/pci/tga.c

568

TGAWREG(dc, TGA_REG_VVBR, 0);

sys/dev/pci/tga.c

572

TGAWREG(dc, TGA_REG_VVBR, 1);

sys/dev/pci/tga.c

633

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

635

if (dc->dc_intrenabled) {

sys/dev/pci/tga.c

637

dc->dc_ramdac_intr = f;

sys/dev/pci/tga.c

638

TGAWREG(dc, TGA_REG_SISR, 0x00010000);

sys/dev/pci/tga.c

641

TGAWREG(dc, TGA_REG_SISR, 0x00010001);

sys/dev/pci/tga.c

642

TGAREGWB(dc, TGA_REG_SISR, 1);

sys/dev/pci/tga.c

643

while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0)

sys/dev/pci/tga.c

645

f(dc->dc_ramdac_cookie);

sys/dev/pci/tga.c

646

TGAWREG(dc, TGA_REG_SISR, 0x00000001);

sys/dev/pci/tga.c

647

TGAREGWB(dc, TGA_REG_SISR, 1);

sys/dev/pci/tga.c

656

struct tga_devconfig *dc = v;

sys/dev/pci/tga.c

657

struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie;

sys/dev/pci/tga.c

661

reg = TGARREG(dc, TGA_REG_SISR);

sys/dev/pci/tga.c

666

TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));

sys/dev/pci/tga.c

667

TGAREGWB(dc, TGA_REG_SISR, 1);

sys/dev/pci/tga.c

678

if (dc->dc_ramdac_intr) {

sys/dev/pci/tga.c

679

dc->dc_ramdac_intr(dcrc);

sys/dev/pci/tga.c

680

dc->dc_ramdac_intr = NULL;

sys/dev/pci/tga.c

682

TGAWREG(dc, TGA_REG_SISR, 0x00000001);

sys/dev/pci/tga.c

683

TGAREGWB(dc, TGA_REG_SISR, 1);

sys/dev/pci/tga.c

691

struct tga_devconfig *dc = sc->sc_dc;

sys/dev/pci/tga.c

693

if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0)

sys/dev/pci/tga.c

700

offset += dc->dc_tgaconf->tgac_cspace_size / 2;

sys/dev/pci/tga.c

752

struct tga_devconfig *dc = sc->sc_dc;

sys/dev/pci/tga.c

753

struct rasops_info *ri = &dc->dc_rinfo;

sys/dev/pci/tga.c

798

struct tga_devconfig *dc = sc->sc_dc;

sys/dev/pci/tga.c

799

struct rasops_info *ri = &dc->dc_rinfo;

sys/dev/pci/tga.c

83

pcitag_t tag, struct tga_devconfig *dc);

sys/dev/pci/tga.c

84

unsigned tga_getdotclock(struct tga_devconfig *dc);

sys/dev/pci/tga.c

865

tga_blank(struct tga_devconfig *dc)

sys/dev/pci/tga.c

868

if (!dc->dc_blanked) {

sys/dev/pci/tga.c

869

dc->dc_blanked = 1;

sys/dev/pci/tga.c

871

TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK);

sys/dev/pci/tga.c

876

tga_unblank(struct tga_devconfig *dc)

sys/dev/pci/tga.c

879

if (dc->dc_blanked) {

sys/dev/pci/tga.c

880

dc->dc_blanked = 0;

sys/dev/pci/tga.c

882

TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK);

sys/dev/pci/tga.c

890

tga_builtin_set_cursor(struct tga_devconfig *dc,

sys/dev/pci/tga.c

893

struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;

sys/dev/pci/tga.c

894

struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;

sys/dev/pci/tga.c

916

TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04);

sys/dev/pci/tga.c

919

TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04);

sys/dev/pci/tga.c

922

TGAWREG(dc, TGA_REG_CXYR,

sys/dev/pci/tga.c

932

TGAWREG(dc, TGA_REG_CCBR,

sys/dev/pci/tga.c

933

(TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10));

sys/dev/pci/tga.c

934

if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr +

sys/dev/pci/tga.c

935

(TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0)

sys/dev/pci/tga.c

942

tga_builtin_get_cursor(struct tga_devconfig *dc,

sys/dev/pci/tga.c

945

struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;

sys/dev/pci/tga.c

946

struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;

sys/dev/pci/tga.c

952

cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;

sys/dev/pci/tga.c

953

cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;

sys/dev/pci/tga.c

954

cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;

sys/dev/pci/tga.c

956

cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f;

sys/dev/pci/tga.c

960

error = copyout((char *)(dc->dc_vaddr +

sys/dev/pci/tga.c

961

(TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),

sys/dev/pci/tga.c

972

tga_builtin_set_curpos(struct tga_devconfig *dc,

sys/dev/pci/tga.c

976

TGAWREG(dc, TGA_REG_CXYR,

sys/dev/pci/tga.c

982

tga_builtin_get_curpos(struct tga_devconfig *dc,

sys/dev/pci/tga.c

986

curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;

sys/dev/pci/tga.c

987

curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;

sys/dev/pci/tga.c

992

tga_builtin_get_curmax(struct tga_devconfig *dc,

sys/dev/pci/tga_conf.c

135

tga_identify(struct tga_devconfig *dc)

sys/dev/pci/tga_conf.c

143

gder = TGARREG(dc, TGA_REG_GDER);

sys/dev/pci/tga_conf.c

144

grev = TGARREG(dc, TGA_REG_GREV);

sys/dev/pci/tgavar.h

140

#define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

144

#define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

148

#define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \

sys/dev/pci/tgavar.h

149

(dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

154

#define TGAREGWB(dc,reg, nregs) bus_space_barrier( \

sys/dev/pci/tgavar.h

155

(dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

159

#define TGAREGRB(dc,reg, nregs) bus_space_barrier( \

sys/dev/pci/tgavar.h

160

(dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

164

#define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \

sys/dev/pci/tgavar.h

165

(dc)->dc_memt, (dc)->dc_regs, \

sys/dev/usb/if_umb.c

1513

struct mbim_cid_device_caps *dc = data;

sys/dev/usb/if_umb.c

1515

if (len < sizeof (*dc))

sys/dev/usb/if_umb.c

1517

sc->sc_maxsessions = letoh32(dc->max_sessions);

sys/dev/usb/if_umb.c

1518

sc->sc_info.supportedclasses = letoh32(dc->dataclass);

sys/dev/usb/if_umb.c

1519

umb_getinfobuf(data, len, dc->devid_offs, dc->devid_size,

sys/dev/usb/if_umb.c

1521

umb_getinfobuf(data, len, dc->fwinfo_offs, dc->fwinfo_size,

sys/dev/usb/if_umb.c

1523

umb_getinfobuf(data, len, dc->hwinfo_offs, dc->hwinfo_size,

sys/dev/wscons/wsdisplay.c

2101

struct wsscreen_internal *dc;

sys/dev/wscons/wsdisplay.c

2112

dc = &wsdisplay_console_conf;

sys/dev/wscons/wsdisplay.c

2116

(void)(*dc->wsemul->output)(dc->wsemulcookie, &c, 1, 1);

sys/dev/wscons/wsemul_vt100.c

352

u_int *ct, dc;

sys/dev/wscons/wsemul_vt100.c

360

(*edp->emulops->mapchar)(edp->emulcookie, instate->inchar, &dc);

sys/dev/wscons/wsemul_vt100.c

375

dc = ct ? ct[c] : c;

sys/dev/wscons/wsemul_vt100.c

397

(edp->emulcookie, edp->crow, edp->ccol << edp->dw, dc,

sys/dev/wscons/wsemul_vt100.c

401

(edp->emulcookie, edp->crow, edp->ccol, dc,

sys/kern/subr_autoconf.c

680

struct deferred_config *dc;

sys/kern/subr_autoconf.c

686

for (dc = TAILQ_FIRST(&deferred_config_queue); dc != NULL;

sys/kern/subr_autoconf.c

687

dc = TAILQ_NEXT(dc, dc_queue)) {

sys/kern/subr_autoconf.c

688

if (dc->dc_dev == dev)

sys/kern/subr_autoconf.c

693

if ((dc = malloc(sizeof(*dc), M_DEVBUF, M_NOWAIT)) == NULL)

sys/kern/subr_autoconf.c

696

dc->dc_dev = dev;

sys/kern/subr_autoconf.c

697

dc->dc_func = func;

sys/kern/subr_autoconf.c

698

TAILQ_INSERT_TAIL(&deferred_config_queue, dc, dc_queue);

sys/kern/subr_autoconf.c

709

struct deferred_config *dc;

sys/kern/subr_autoconf.c

720

for (dc = TAILQ_FIRST(&mountroot_config_queue); dc != NULL;

sys/kern/subr_autoconf.c

721

dc = TAILQ_NEXT(dc, dc_queue)) {

sys/kern/subr_autoconf.c

722

if (dc->dc_dev == dev)

sys/kern/subr_autoconf.c

727

if ((dc = malloc(sizeof(*dc), M_DEVBUF, M_NOWAIT)) == NULL)

sys/kern/subr_autoconf.c

730

dc->dc_dev = dev;

sys/kern/subr_autoconf.c

731

dc->dc_func = func;

sys/kern/subr_autoconf.c

732

TAILQ_INSERT_TAIL(&mountroot_config_queue, dc, dc_queue);

sys/kern/subr_autoconf.c

741

struct deferred_config *dc, *ndc;

sys/kern/subr_autoconf.c

743

for (dc = TAILQ_FIRST(&deferred_config_queue);

sys/kern/subr_autoconf.c

744

dc != NULL; dc = ndc) {

sys/kern/subr_autoconf.c

745

ndc = TAILQ_NEXT(dc, dc_queue);

sys/kern/subr_autoconf.c

746

if (dc->dc_dev->dv_parent == parent) {

sys/kern/subr_autoconf.c

747

TAILQ_REMOVE(&deferred_config_queue, dc, dc_queue);

sys/kern/subr_autoconf.c

748

(*dc->dc_func)(dc->dc_dev);

sys/kern/subr_autoconf.c

749

free(dc, M_DEVBUF, sizeof(*dc));

sys/kern/subr_autoconf.c

762

struct deferred_config *dc;

sys/kern/subr_autoconf.c

764

while ((dc = TAILQ_FIRST(&mountroot_config_queue)) != NULL) {

sys/kern/subr_autoconf.c

765

TAILQ_REMOVE(&mountroot_config_queue, dc, dc_queue);

sys/kern/subr_autoconf.c

766

(*dc->dc_func)(dc->dc_dev);

sys/kern/subr_autoconf.c

767

free(dc, M_DEVBUF, sizeof(*dc));

usr.bin/bc/bc.y

105

static pid_t dc;

usr.bin/bc/bc.y

1074

pid = waitpid(dc, &status, WCONTINUED | WNOHANG);

usr.bin/bc/bc.y

1147

dc = fork();

usr.bin/bc/bc.y

1148

if (dc == -1)

usr.bin/bc/bc.y

1150

else if (dc != 0) {

usr.bin/bc/bc.y

285

if (dc) {

usr.bin/lex/misc.c

57

bool dc; /**< do_copy */

usr.bin/lex/misc.c

62

sko_push(bool dc)

usr.bin/lex/misc.c

76

sko_stack[sko_len].dc = dc;

usr.bin/lex/misc.c

80

sko_peek(bool * dc)

usr.bin/lex/misc.c

84

if (dc)

usr.bin/lex/misc.c

85

*dc = sko_stack[sko_len - 1].dc;

usr.bin/lex/misc.c

88

sko_pop(bool * dc)

usr.bin/lex/misc.c

90

sko_peek(dc);

usr.bin/ssh/authfd.c

491

encode_dest_constraint(struct sshbuf *m, const struct dest_constraint *dc)

usr.bin/ssh/authfd.c

498

if ((r = encode_dest_constraint_hop(b, &dc->from)) != 0 ||

usr.bin/ssh/authfd.c

499

(r = encode_dest_constraint_hop(b, &dc->to)) != 0 ||

usr.bin/ssh/ssh-add.c

761

struct dest_constraint *dc;

usr.bin/ssh/ssh-add.c

764

dc = xcalloc(1, sizeof(*dc));

usr.bin/ssh/ssh-add.c

768

parse_dest_constraint_hop(os, &dc->to, hostkey_files);

usr.bin/ssh/ssh-add.c

772

parse_dest_constraint_hop(os, &dc->from, hostkey_files);

usr.bin/ssh/ssh-add.c

773

parse_dest_constraint_hop(cp, &dc->to, hostkey_files);

usr.bin/ssh/ssh-add.c

774

if (dc->from.user != NULL) {

usr.bin/ssh/ssh-add.c

781

dc->from.user ? dc->from.user : "", dc->from.user ? "@" : "",

usr.bin/ssh/ssh-add.c

782

dc->from.hostname ? dc->from.hostname : "(ORIGIN)", dc->from.nkeys,

usr.bin/ssh/ssh-add.c

783

dc->to.user ? dc->to.user : "", dc->to.user ? "@" : "",

usr.bin/ssh/ssh-add.c

784

dc->to.hostname ? dc->to.hostname : "(ANY)", dc->to.nkeys);

usr.bin/ssh/ssh-add.c

786

(*dcp)[(*ndcp)++] = dc;

usr.bin/ssh/ssh-agent.c

1131

parse_dest_constraint(struct sshbuf *m, struct dest_constraint *dc)

usr.bin/ssh/ssh-agent.c

1139

memset(dc, '\0', sizeof(*dc));

usr.bin/ssh/ssh-agent.c

1147

if ((r = parse_dest_constraint_hop(frombuf, &dc->from)) != 0 ||

usr.bin/ssh/ssh-agent.c

1148

(r = parse_dest_constraint_hop(tobuf, &dc->to)) != 0)

usr.bin/ssh/ssh-agent.c

1156

dc->from.hostname ? dc->from.hostname : "(ORIGIN)", dc->from.nkeys,

usr.bin/ssh/ssh-agent.c

1157

dc->to.user ? dc->to.user : "", dc->to.user ? "@" : "",

usr.bin/ssh/ssh-agent.c

1158

dc->to.hostname ? dc->to.hostname : "(ANY)", dc->to.nkeys);

usr.bin/ssh/ssh-agent.c

1160

if ((dc->from.hostname == NULL) != (dc->from.nkeys == 0) ||

usr.bin/ssh/ssh-agent.c

1161

dc->from.user != NULL) {

usr.bin/ssh/ssh-agent.c

1166

if (dc->to.hostname == NULL || dc->to.nkeys == 0) {

usr.sbin/amd/amd/info_file.c

154

char *dc = strdup(cp);

usr.sbin/amd/amd/info_file.c

156

(*fn)(m, strdup(kp), dc);

usr.sbin/amd/amd/info_file.c

158

*val = dc;

usr.sbin/amd/amd/info_file.c

160

dlog("%s returns %s", key, dc);

usr.sbin/ldomctl/ldomctl.c

187

struct ds_conn *dc;

usr.sbin/ldomctl/ldomctl.c

189

dc = ds_conn_open("/dev/spds", NULL);

usr.sbin/ldomctl/ldomctl.c

190

ds_conn_register_service(dc, &pri_service);

usr.sbin/ldomctl/ldomctl.c

192

ds_conn_handle(dc);

usr.sbin/ldomctl/ldomctl.c

274

struct ds_conn *dc;

usr.sbin/ldomctl/ldomctl.c

282

dc = ds_conn_open("/dev/spds", NULL);

usr.sbin/ldomctl/ldomctl.c

283

mdstore_register(dc);

usr.sbin/ldomctl/ldomctl.c

285

ds_conn_handle(dc);

usr.sbin/ldomctl/ldomctl.c

309

struct ds_conn *dc;

usr.sbin/ldomctl/ldomctl.c

316

dc = ds_conn_open("/dev/spds", NULL);

usr.sbin/ldomctl/ldomctl.c

317

mdstore_register(dc);

usr.sbin/ldomctl/ldomctl.c

319

ds_conn_handle(dc);

usr.sbin/ldomctl/ldomctl.c

321

mdstore_select(dc, argv[1]);

usr.sbin/ldomctl/ldomctl.c

327

struct ds_conn *dc;

usr.sbin/ldomctl/ldomctl.c

337

dc = ds_conn_open("/dev/spds", NULL);

usr.sbin/ldomctl/ldomctl.c

338

mdstore_register(dc);

usr.sbin/ldomctl/ldomctl.c

340

ds_conn_handle(dc);

usr.sbin/ldomctl/ldomctl.c

342

mdstore_delete(dc, argv[1]);

usr.sbin/ldomctl/ldomctl.c

390

struct ds_conn *dc;

usr.sbin/ldomctl/ldomctl.c

397

dc = ds_conn_open("/dev/spds", NULL);

usr.sbin/ldomctl/ldomctl.c

398

mdstore_register(dc);

usr.sbin/ldomctl/ldomctl.c

400

ds_conn_handle(dc);

usr.sbin/ldomctl/ldomctl.c

402

mdstore_download(dc, argv[1]);

usr.sbin/ldomctl/mdstore.c

172

mdstore_register(struct ds_conn *dc)

usr.sbin/ldomctl/mdstore.c

174

ds_conn_register_service(dc, &mdstore_service);

usr.sbin/ldomctl/mdstore.c

175

ds_conn_register_service(dc, &mdstore_service_v2);

usr.sbin/ldomctl/mdstore.c

176

ds_conn_register_service(dc, &mdstore_service_v3);

usr.sbin/ldomctl/mdstore.c

250

mdstore_begin_v1(struct ds_conn *dc, uint64_t svc_handle, const char *name,

usr.sbin/ldomctl/mdstore.c

266

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

270

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

274

mdstore_begin_v2(struct ds_conn *dc, uint64_t svc_handle, const char *name,

usr.sbin/ldomctl/mdstore.c

292

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

296

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

300

mdstore_begin_v3(struct ds_conn *dc, uint64_t svc_handle, const char *name,

usr.sbin/ldomctl/mdstore.c

320

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

324

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

328

mdstore_begin(struct ds_conn *dc, uint64_t svc_handle, const char *name,

usr.sbin/ldomctl/mdstore.c

332

mdstore_begin_v3(dc, svc_handle, name, nmds, config_size);

usr.sbin/ldomctl/mdstore.c

334

mdstore_begin_v2(dc, svc_handle, name, nmds, config_size);

usr.sbin/ldomctl/mdstore.c

336

mdstore_begin_v1(dc, svc_handle, name, nmds);

usr.sbin/ldomctl/mdstore.c

340

mdstore_transfer(struct ds_conn *dc, uint64_t svc_handle, const char *path,

usr.sbin/ldomctl/mdstore.c

369

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

375

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

379

mdstore_end(struct ds_conn *dc, uint64_t svc_handle, const char *name,

usr.sbin/ldomctl/mdstore.c

395

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

399

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

403

mdstore_select(struct ds_conn *dc, const char *name)

usr.sbin/ldomctl/mdstore.c

409

TAILQ_FOREACH(dcs, &dc->services, link)

usr.sbin/ldomctl/mdstore.c

424

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

428

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

432

mdstore_delete(struct ds_conn *dc, const char *name)

usr.sbin/ldomctl/mdstore.c

438

TAILQ_FOREACH(dcs, &dc->services, link)

usr.sbin/ldomctl/mdstore.c

453

ds_send_msg(&dc->lc, mr, len);

usr.sbin/ldomctl/mdstore.c

457

ds_conn_handle(dc);

usr.sbin/ldomctl/mdstore.c

467

mdstore_download(struct ds_conn *dc, const char *name)

usr.sbin/ldomctl/mdstore.c

478

TAILQ_FOREACH(dcs, &dc->services, link)

usr.sbin/ldomctl/mdstore.c

517

mdstore_begin(dc, dcs->svc_handle, name, nmds, total_size);

usr.sbin/ldomctl/mdstore.c

524

mdstore_transfer(dc, dcs->svc_handle, path, type, guest->mdpa);

usr.sbin/ldomctl/mdstore.c

529

mdstore_transfer(dc, dcs->svc_handle, path,

usr.sbin/ldomctl/mdstore.c

534

mdstore_transfer(dc, dcs->svc_handle, path,

usr.sbin/ldomctl/mdstore.c

537

mdstore_end(dc, dcs->svc_handle, name, nmds);

usr.sbin/ldomd/ds.c

425

struct ds_conn *dc = lc->lc_cookie;

usr.sbin/ldomd/ds.c

451

TAILQ_FOREACH(dcs, &dc->services, link) {

usr.sbin/ldomd/ds.c

463

TAILQ_FOREACH(dcs, &dc->services, link) {

usr.sbin/ldomd/ds.c

488

TAILQ_FOREACH(dcs, &dc->services, link) {

usr.sbin/ldomd/ds.c

670

struct ds_conn *dc;

usr.sbin/ldomd/ds.c

672

dc = xmalloc(sizeof(*dc));

usr.sbin/ldomd/ds.c

673

dc->path = xstrdup(path);

usr.sbin/ldomd/ds.c

674

dc->cookie = cookie;

usr.sbin/ldomd/ds.c

676

dc->fd = open(path, O_RDWR);

usr.sbin/ldomd/ds.c

677

if (dc->fd == -1)

usr.sbin/ldomd/ds.c

680

memset(&dc->lc, 0, sizeof(dc->lc));

usr.sbin/ldomd/ds.c

681

dc->lc.lc_fd = dc->fd;

usr.sbin/ldomd/ds.c

682

dc->lc.lc_cookie = dc;

usr.sbin/ldomd/ds.c

683

dc->lc.lc_rx_data = ds_rx_msg;

usr.sbin/ldomd/ds.c

685

TAILQ_INIT(&dc->services);

usr.sbin/ldomd/ds.c

686

TAILQ_INSERT_TAIL(&ds_conns, dc, link);

usr.sbin/ldomd/ds.c

687

dc->id = num_ds_conns++;

usr.sbin/ldomd/ds.c

688

return dc;

usr.sbin/ldomd/ds.c

692

ds_conn_register_service(struct ds_conn *dc, struct ds_service *ds)

usr.sbin/ldomd/ds.c

699

TAILQ_INSERT_TAIL(&dc->services, dcs, link);

usr.sbin/ldomd/ds.c

703

ds_conn_handle(struct ds_conn *dc)

usr.sbin/ldomd/ds.c

708

nbytes = read(dc->fd, &lp, sizeof(lp));

usr.sbin/ldomd/ds.c

710

ldc_reset(&dc->lc);

usr.sbin/ldomd/ds.c

716

ldc_rx_ctrl(&dc->lc, &lp);

usr.sbin/ldomd/ds.c

719

ldc_rx_data(&dc->lc, &lp);

usr.sbin/ldomd/ds.c

724

ldc_reset(&dc->lc);

usr.sbin/ldomd/ds.c

732

struct ds_conn *dc;

usr.sbin/ldomd/ds.c

737

TAILQ_FOREACH(dc, &ds_conns, link) {

usr.sbin/ldomd/ds.c

738

pfd[dc->id].fd = dc->fd;

usr.sbin/ldomd/ds.c

739

pfd[dc->id].events = POLLIN;

usr.sbin/ldomd/ds.c

749

TAILQ_FOREACH(dc, &ds_conns, link) {

usr.sbin/ldomd/ds.c

750

if (pfd[dc->id].revents)

usr.sbin/ldomd/ds.c

751

ds_conn_handle(dc);

usr.sbin/ldomd/ldomd.c

195

struct ds_conn *dc;

usr.sbin/ldomd/ldomd.c

202

dc = ds_conn_open(path, guest);

usr.sbin/ldomd/ldomd.c

203

ds_conn_register_service(dc, &var_config_service);

usr.sbin/ldomd/var-config.c

124

struct ds_conn *dc = lc->lc_cookie;

usr.sbin/ldomd/var-config.c

134

vx.result = set_variable(dc->cookie, vr->name,

usr.sbin/ldomd/var-config.c

142

vx.result = delete_variable(dc->cookie, vr->name);

usr.sbin/unbound/validator/autotrust.c

333

uint16_t dc)

usr.sbin/unbound/validator/autotrust.c

345

tp->dclass = dc;